system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6smoothPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0040*/ MOV R0, c[0x0][0xc] ; /* 0x0000030000007a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ IMAD R7, R7, R0, -0x1 ; /* 0xffffffff07077424 */
/* 0x000fe400078e0200 */
/*0080*/ IMAD R8, R8, c[0x0][0xc], R3 ; /* 0x0000030008087a24 */
/* 0x001fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R13, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x040fe200078e020d */
/*00a0*/ ISETP.NE.AND P1, PT, R8.reuse, R7, PT ; /* 0x000000070800720c */
/* 0x040fe40003f25270 */
/*00b0*/ ISETP.NE.AND P0, PT, R8.reuse, RZ, PT ; /* 0x000000ff0800720c */
/* 0x040fe40003f05270 */
/*00c0*/ IADD3 R0, R8, -0x1, RZ ; /* 0xffffffff08007810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea6000c1e1900 */
/*00e0*/ SEL R0, R0, RZ, P0 ; /* 0x000000ff00007207 */
/* 0x000fca0000000000 */
/*00f0*/ IMAD.WIDE R4, R0, R13, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e020d */
/*0100*/ @P1 IADD3 R7, R8, 0x1, RZ ; /* 0x0000000108071810 */
/* 0x000fca0007ffe0ff */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R7, R13, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fcc00078e020d */
/*0130*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*0140*/ FMUL R9, R4, 0.25 ; /* 0x3e80000004097820 */
/* 0x008fc80000400000 */
/*0150*/ FFMA R11, R2, 0.5, R9 ; /* 0x3f000000020b7823 */
/* 0x004fe40000000009 */
/*0160*/ IMAD.WIDE R8, R8, R13, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e020d */
/*0170*/ FFMA R11, R6, 0.25, R11 ; /* 0x3e800000060b7823 */
/* 0x010fca000000000b */
/*0180*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6smoothPfPKf
.globl _Z6smoothPfPKf
.p2align 8
.type _Z6smoothPfPKf,@function
_Z6smoothPfPKf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x1c
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s4, v0, s[2:3]
s_load_b128 s[0:3], s[0:1], 0x0
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s4, s5
s_add_i32 s4, s4, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_sub_nc_u32_e64 v3, v1, 1 clamp
v_add_nc_u32_e32 v0, 1, v1
v_cmp_eq_u32_e32 vcc_lo, s4, v1
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v0, v0, s4, vcc_lo
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[7:8], off
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v2, 0x3e800000, v2
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, 0.5, v3
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, 0x3e800000, v0
v_add_co_u32 v0, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6smoothPfPKf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6smoothPfPKf, .Lfunc_end0-_Z6smoothPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6smoothPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6smoothPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00199e9e_00000000-6_smooth.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6smoothPfPKfPfPKf
.type _Z28__device_stub__Z6smoothPfPKfPfPKf, @function
_Z28__device_stub__Z6smoothPfPKfPfPKf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6smoothPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z6smoothPfPKfPfPKf, .-_Z28__device_stub__Z6smoothPfPKfPfPKf
.globl _Z6smoothPfPKf
.type _Z6smoothPfPKf, @function
_Z6smoothPfPKf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6smoothPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6smoothPfPKf, .-_Z6smoothPfPKf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6smoothPfPKf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6smoothPfPKf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "smooth.hip"
.globl _Z21__device_stub__smoothPfPKf # -- Begin function _Z21__device_stub__smoothPfPKf
.p2align 4, 0x90
.type _Z21__device_stub__smoothPfPKf,@function
_Z21__device_stub__smoothPfPKf: # @_Z21__device_stub__smoothPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6smoothPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__smoothPfPKf, .Lfunc_end0-_Z21__device_stub__smoothPfPKf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6smoothPfPKf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6smoothPfPKf,@object # @_Z6smoothPfPKf
.section .rodata,"a",@progbits
.globl _Z6smoothPfPKf
.p2align 3, 0x0
_Z6smoothPfPKf:
.quad _Z21__device_stub__smoothPfPKf
.size _Z6smoothPfPKf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6smoothPfPKf"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__smoothPfPKf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6smoothPfPKf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
This program demonstrates the basics of working with cuda. We use
the GPU to add two arrays. We also introduce cuda's approach to
error handling and timing using cuda Events.
This is the main program. You should also look at the header add.h
for the important declarations, and then look at add.cu to see how
to define functions that execute on the GPU.
*/
#include <iostream>
#include <math.h>
// CUDA kernel to add elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory -- accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Launch kernel on 1M elements on the GPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord( start, 0 );
add<<<numBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
cudaEventRecord( end, 0 );
cudaEventSynchronize( end );
float elapsedTime;
cudaEventElapsedTime( &elapsedTime, start, end );
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
std::cout << "Yay! Your program's results are correct." << std::endl;
std::cout << "Your program took: " << elapsedTime << " ms." << std::endl;
// Cleanup in the event of success.
cudaEventDestroy( start );
cudaEventDestroy( end );
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0270*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0340*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R6, R3, R6, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fe200078e0206 */
/*0360*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0390*/ FADD R17, R2, R9 ; /* 0x0000000902117221 */
/* 0x004fe40000000000 */
/*03a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R19, R2, R13 ; /* 0x0000000d02137221 */
/* 0x004fe40000000000 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0208 */
/*0410*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R6, R0, 0x4, R14 ; /* 0x0000000400067825 */
/* 0x001fc800078e020e */
/*0450*/ FADD R21, R2, R5 ; /* 0x0000000502157221 */
/* 0x004fe40000000000 */
/*0460*/ IMAD.WIDE R4, R0, 0x4, R12 ; /* 0x0000000400047825 */
/* 0x000fc600078e020c */
/*0470*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*04e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101904 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
This program demonstrates the basics of working with cuda. We use
the GPU to add two arrays. We also introduce cuda's approach to
error handling and timing using cuda Events.
This is the main program. You should also look at the header add.h
for the important declarations, and then look at add.cu to see how
to define functions that execute on the GPU.
*/
#include <iostream>
#include <math.h>
// CUDA kernel to add elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory -- accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Launch kernel on 1M elements on the GPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord( start, 0 );
add<<<numBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
cudaEventRecord( end, 0 );
cudaEventSynchronize( end );
float elapsedTime;
cudaEventElapsedTime( &elapsedTime, start, end );
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
std::cout << "Yay! Your program's results are correct." << std::endl;
std::cout << "Your program took: " << elapsedTime << " ms." << std::endl;
// Cleanup in the event of success.
cudaEventDestroy( start );
cudaEventDestroy( end );
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | .file "tmpxft_000c32af_00000000-6_hellocuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max error: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Yay! Your program's results are correct."
.section .rodata.str1.1
.LC7:
.string "Your program took: "
.LC8:
.string " ms."
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $4096, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 24(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z3addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
This program demonstrates the basics of working with cuda. We use
the GPU to add two arrays. We also introduce cuda's approach to
error handling and timing using cuda Events.
This is the main program. You should also look at the header add.h
for the important declarations, and then look at add.cu to see how
to define functions that execute on the GPU.
*/
#include <iostream>
#include <math.h>
// CUDA kernel to add elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory -- accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Launch kernel on 1M elements on the GPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord( start, 0 );
add<<<numBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
cudaEventRecord( end, 0 );
cudaEventSynchronize( end );
float elapsedTime;
cudaEventElapsedTime( &elapsedTime, start, end );
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
std::cout << "Yay! Your program's results are correct." << std::endl;
std::cout << "Your program took: " << elapsedTime << " ms." << std::endl;
// Cleanup in the event of success.
cudaEventDestroy( start );
cudaEventDestroy( end );
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | /*
This program demonstrates the basics of working with cuda. We use
the GPU to add two arrays. We also introduce cuda's approach to
error handling and timing using cuda Events.
This is the main program. You should also look at the header add.h
for the important declarations, and then look at add.cu to see how
to define functions that execute on the GPU.
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// CUDA kernel to add elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory -- accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Launch kernel on 1M elements on the GPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord( start, 0 );
add<<<numBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
hipEventRecord( end, 0 );
hipEventSynchronize( end );
float elapsedTime;
hipEventElapsedTime( &elapsedTime, start, end );
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
std::cout << "Yay! Your program's results are correct." << std::endl;
std::cout << "Your program took: " << elapsedTime << " ms." << std::endl;
// Cleanup in the event of success.
hipEventDestroy( start );
hipEventDestroy( end );
// Free memory
hipFree(x);
hipFree(y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
This program demonstrates the basics of working with cuda. We use
the GPU to add two arrays. We also introduce cuda's approach to
error handling and timing using cuda Events.
This is the main program. You should also look at the header add.h
for the important declarations, and then look at add.cu to see how
to define functions that execute on the GPU.
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// CUDA kernel to add elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory -- accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Launch kernel on 1M elements on the GPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord( start, 0 );
add<<<numBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
hipEventRecord( end, 0 );
hipEventSynchronize( end );
float elapsedTime;
hipEventElapsedTime( &elapsedTime, start, end );
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
std::cout << "Yay! Your program's results are correct." << std::endl;
std::cout << "Your program took: " << elapsedTime << " ms." << std::endl;
// Cleanup in the event of success.
hipEventDestroy( start );
hipEventDestroy( end );
// Free memory
hipFree(x);
hipFree(y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[6:7], v0, off
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
This program demonstrates the basics of working with cuda. We use
the GPU to add two arrays. We also introduce cuda's approach to
error handling and timing using cuda Events.
This is the main program. You should also look at the header add.h
for the important declarations, and then look at add.cu to see how
to define functions that execute on the GPU.
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// CUDA kernel to add elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory -- accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Launch kernel on 1M elements on the GPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord( start, 0 );
add<<<numBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
hipEventRecord( end, 0 );
hipEventSynchronize( end );
float elapsedTime;
hipEventElapsedTime( &elapsedTime, start, end );
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
std::cout << "Yay! Your program's results are correct." << std::endl;
std::cout << "Your program took: " << elapsedTime << " ms." << std::endl;
// Cleanup in the event of success.
hipEventDestroy( start );
hipEventDestroy( end );
// Free memory
hipFree(x);
hipFree(y);
return 0;
} | .text
.file "hellocuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $168, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 32(%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movl $1048576, 44(%rsp) # imm = 0x100000
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
leaq 44(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
xorps %xmm2, %xmm2
movq 16(%rsp), %rax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rax,%rbx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rbx
movaps %xmm5, %xmm2
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 144(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 144(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $40, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
cmpb $0, 56(%rbx)
je .LBB1_13
# %bb.12:
movzbl 67(%rbx), %eax
jmp .LBB1_14
.LBB1_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i28
cmpb $0, 56(%r14)
je .LBB1_17
# %bb.16:
movzbl 67(%r14), %eax
jmp .LBB1_18
.LBB1_17:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit31
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Yay! Your program's results are correct."
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Your program took: "
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " ms."
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0270*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0340*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R6, R3, R6, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fe200078e0206 */
/*0360*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0390*/ FADD R17, R2, R9 ; /* 0x0000000902117221 */
/* 0x004fe40000000000 */
/*03a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R19, R2, R13 ; /* 0x0000000d02137221 */
/* 0x004fe40000000000 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0208 */
/*0410*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R6, R0, 0x4, R14 ; /* 0x0000000400067825 */
/* 0x001fc800078e020e */
/*0450*/ FADD R21, R2, R5 ; /* 0x0000000502157221 */
/* 0x004fe40000000000 */
/*0460*/ IMAD.WIDE R4, R0, 0x4, R12 ; /* 0x0000000400047825 */
/* 0x000fc600078e020c */
/*0470*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*04e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101904 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[6:7], v0, off
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c32af_00000000-6_hellocuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max error: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Yay! Your program's results are correct."
.section .rodata.str1.1
.LC7:
.string "Your program took: "
.LC8:
.string " ms."
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $4096, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 24(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z3addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hellocuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $168, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 32(%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movl $1048576, 44(%rsp) # imm = 0x100000
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
leaq 44(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
xorps %xmm2, %xmm2
movq 16(%rsp), %rax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rax,%rbx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rbx
movaps %xmm5, %xmm2
cmpq $1048576, %rbx # imm = 0x100000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 144(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 144(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $40, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
cmpb $0, 56(%rbx)
je .LBB1_13
# %bb.12:
movzbl 67(%rbx), %eax
jmp .LBB1_14
.LBB1_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i28
cmpb $0, 56(%r14)
je .LBB1_17
# %bb.16:
movzbl 67(%r14), %eax
jmp .LBB1_18
.LBB1_17:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit31
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Yay! Your program's results are correct."
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Your program took: "
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " ms."
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
#include <math.h>
#include <stdio.h>
#include <assert.h>
#include <fstream>
#include <time.h>
__global__ void image_convolution_kernel(float *input, float *out, float *kernelConv,
int img_width, const int img_height,
const int kernel_width, const int kernel_height )
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if ((x < img_width) && (y < img_height)){
float sum = 0;
for ( int j = 0; j < kernel_height; j++ )
{
for ( int i = 0; i < kernel_width; i++ )
{
int dX = x + i - kernel_width / 2;
int dY = y + j - kernel_height / 2;
if ( dX < 0 )
dX = 0;
if ( dX >= img_width )
dX = img_width - 1;
if ( dY < 0 )
dY = 0;
if ( dY >= img_height )
dY = img_height - 1;
const int idMat = j * kernel_width + i;
const int idPixel = dY * img_width + dX;
sum += (float)input[idPixel] * kernelConv[idMat];
}
}
const int idOut = y * img_width + x;
out[idOut] = abs(sum);
}
}
void MC(float * input,float* output, int img_height, int img_width, const int r, float & gpu_elapsed_time_ms)
{
// initialize kernel here
int kernel_height = r;
int kernel_width = r;
float *kernel;
kernel = new float[r*r];
for (int i = 0; i < r*r; i++){
kernel[i] = rand() % 10 + 1;
}
float * mask = new float[kernel_height*kernel_width];
for (int i = 0; i < kernel_height*kernel_width; i++)
{
mask[i] = kernel[i];
}
float * d_input, * d_output, * d_kernel;
cudaMalloc(&d_input, img_width*img_height*sizeof(float));
cudaMalloc(&d_output, img_width*img_height*sizeof(float));
cudaMalloc(&d_kernel, kernel_height*kernel_width*sizeof(float));
cudaMemcpy(d_input, input, img_width*img_height*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_kernel, mask, kernel_height*kernel_width*sizeof(float), cudaMemcpyHostToDevice);
dim3 blocksize(16,16);
dim3 gridsize;
gridsize.x=(img_width+blocksize.x-1)/blocksize.x;
gridsize.y=(img_height+blocksize.y-1)/blocksize.y;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
image_convolution_kernel<<<gridsize,blocksize>>>(d_input,d_output,d_kernel,img_width,img_height,kernel_width,kernel_height);
cudaMemcpy(output, d_output, img_width*img_height*sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
}
int main(){
// open the output file
std::ofstream ofile;
// customize output filename
ofile.open("matrix_conv_gpu_500_points_Quadro.csv");
// number of instances of data generated
int NUM = 500;
for (int iterator = 0; iterator < NUM; iterator++) {
if (iterator % 10 == 0) std::cout << "iter: " << iterator << std::endl;
float *in, *out;
int m = rand() % 1024 + 10;
int n = rand() % 1024 + 10;
int is = n * m;
int r = (rand() % 3 + 1) * 2 + 1;
in = new float[is];
out = new float[is];
// density
int power;
double d;
power = rand() % int((log2(double(m * n)) + 1));
d = 1 / pow(2, power);
// initialize matrix A
// if A is a sparse matrix
if (d <= 0.5) {
int count_a = m * n * d;
for (int it = 0; it < count_a; it++) {
int i = rand() % m;
int j = rand() % n;
in[i * n + j] = rand() % 1024 + 1;
}
// if A is a dense matrix
} else {
for (int i = 0; i < m * n; i++) {
in[i] = rand() % 1024 + 1;
}
}
float time;
// perform kernel operation
MC(in, out, n, m, r, time);
int c = (m-r+1)*(n-r+1)*r*r;
ofile << time / 1000;
ofile << "," << m << "," << n << "," << r << "," << d << "," << c << ",\n";
}
ofile.close();
return 0;
} | code for sm_80
Function : _Z24image_convolution_kernelPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R17, R17, c[0x0][0x4], R0 ; /* 0x0000010011117a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x17c], PT ; /* 0x00005f0011007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R16, R3, c[0x0][0x0], R2 ; /* 0x0000000003107a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R16, c[0x0][0x178], P0 ; /* 0x00005e0010007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff047624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e00ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x830 ; /* 0x0000074000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0e7624 */
/* 0x000fca00078e00ff */
/*0100*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0110*/ @!P0 BRA 0x830 ; /* 0x0000071000008947 */
/* 0x000fea0003800000 */
/*0120*/ LEA.HI R0, R14.reuse, c[0x0][0x180], RZ, 0x1 ; /* 0x000060000e007a11 */
/* 0x040fe200078f08ff */
/*0130*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R24, R14.reuse, -0x1, RZ ; /* 0xffffffff0e187810 */
/* 0x040fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0160*/ SHF.R.S32.HI R11, RZ, 0x1, R0 ; /* 0x00000001ff0b7819 */
/* 0x000fe20000011400 */
/*0170*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*0180*/ LOP3.LUT R14, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e0e7812 */
/* 0x000fe200078ec0ff */
/*0190*/ UIADD3 UR5, UR5, -0x1, URZ ; /* 0xffffffff05057890 */
/* 0x000fe4000fffe03f */
/*01a0*/ IMAD.IADD R0, R2, 0x1, -R11.reuse ; /* 0x0000000102007824 */
/* 0x100fe200078e0a0b */
/*01b0*/ LEA.HI R2, R4, c[0x0][0x184], RZ, 0x1 ; /* 0x0000610004027a11 */
/* 0x000fe200078f08ff */
/*01c0*/ IMAD.IADD R11, R16, 0x1, -R11 ; /* 0x00000001100b7824 */
/* 0x000fe200078e0a0b */
/*01d0*/ IADD3 R23, R14, -c[0x0][0x180], RZ ; /* 0x800060000e177a10 */
/* 0x000fe20007ffe0ff */
/*01e0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x000fe200078e0200 */
/*01f0*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011402 */
/*0200*/ UIADD3 UR6, UR4, -0x1, URZ ; /* 0xffffffff04067890 */
/* 0x000fc6000fffe03f */
/*0210*/ IADD3 R10, R0, 0x3, RZ ; /* 0x00000003000a7810 */
/* 0x000fe20007ffe0ff */
/*0220*/ IMAD.IADD R12, R17, 0x1, -R2 ; /* 0x00000001110c7824 */
/* 0x000fc800078e0a02 */
/*0230*/ IMAD.IADD R0, R12, 0x1, R13 ; /* 0x000000010c007824 */
/* 0x000fe200078e020d */
/*0240*/ ISETP.GE.U32.AND P3, PT, R24, 0x3, PT ; /* 0x000000031800780c */
/* 0x000fe20003f66070 */
/*0250*/ IMAD R20, R13.reuse, c[0x0][0x180], RZ ; /* 0x000060000d147a24 */
/* 0x040fe200078e02ff */
/*0260*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*0270*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0280*/ IMNMX R0, RZ, R0, !PT ; /* 0x00000000ff007217 */
/* 0x000fe40007800200 */
/*0290*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f25270 */
/*02a0*/ ISETP.GE.AND P2, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fc40003f46270 */
/*02b0*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x184], PT ; /* 0x000061000d007a0c */
/* 0x000fe40003f06270 */
/*02c0*/ SEL R0, R0, UR5, !P2 ; /* 0x0000000500007c07 */
/* 0x000fe2000d000000 */
/*02d0*/ @!P3 BRA 0x600 ; /* 0x000003200000b947 */
/* 0x000fec0003800000 */
/*02e0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fe200078e00ff */
/*02f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0300*/ IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff127224 */
/* 0x000fe400078e000a */
/*0310*/ IMAD.WIDE R2, R20, R19, c[0x0][0x170] ; /* 0x00005c0014027625 */
/* 0x000fc800078e0213 */
/*0320*/ IMAD.MOV.U32 R21, RZ, RZ, R2 ; /* 0x000000ffff157224 */
/* 0x000fe400078e0002 */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0003 */
/*0340*/ IADD3 R2, R18.reuse, -0x3, RZ ; /* 0xfffffffd12027810 */
/* 0x040fe40007ffe0ff */
/*0350*/ IADD3 R3, R18, -0x2, RZ ; /* 0xfffffffe12037810 */
/* 0x000fe40007ffe0ff */
/*0360*/ IMNMX R2, RZ, R2, !PT ; /* 0x00000002ff027217 */
/* 0x000fe40007800200 */
/*0370*/ IMNMX R5, RZ, R3, !PT ; /* 0x00000003ff057217 */
/* 0x000fe40007800200 */
/*0380*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fc40003f46270 */
/*0390*/ IADD3 R6, R18, -0x1, RZ ; /* 0xffffffff12067810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ SEL R3, R2, UR6, !P2 ; /* 0x0000000602037c07 */
/* 0x000fe4000d000000 */
/*03b0*/ IMNMX R6, RZ, R6, !PT ; /* 0x00000006ff067217 */
/* 0x000fe40007800200 */
/*03c0*/ ISETP.GE.AND P3, PT, R5.reuse, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x040fe20003f66270 */
/*03d0*/ IMAD R2, R0, c[0x0][0x178], R3 ; /* 0x00005e0000027a24 */
/* 0x000fe200078e0203 */
/*03e0*/ IMNMX R8, RZ, R18, !PT ; /* 0x00000012ff087217 */
/* 0x000fe40007800200 */
/*03f0*/ ISETP.GE.AND P2, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fe20003f46270 */
/*0400*/ IMAD.WIDE R2, R2, R19, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0213 */
/*0410*/ SEL R5, R5, UR6, !P3 ; /* 0x0000000605057c07 */
/* 0x000fc4000d800000 */
/*0420*/ ISETP.GE.AND P3, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fe40003f66270 */
/*0430*/ LDG.E R22, [R2.64] ; /* 0x0000000802167981 */
/* 0x0000a2000c1e1900 */
/*0440*/ SEL R7, R6, UR6, !P2 ; /* 0x0000000606077c07 */
/* 0x000fe2000d000000 */
/*0450*/ IMAD R6, R0, c[0x0][0x178], R5 ; /* 0x00005e0000067a24 */
/* 0x000fe400078e0205 */
/*0460*/ IMAD.MOV.U32 R2, RZ, RZ, R21 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0015 */
/*0470*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0004 */
/*0480*/ SEL R5, R8, UR6, !P3 ; /* 0x0000000608057c07 */
/* 0x000fc8000d800000 */
/*0490*/ LDG.E R21, [R2.64] ; /* 0x0000000802157981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IMAD R8, R0, c[0x0][0x178], R7 ; /* 0x00005e0000087a24 */
/* 0x000fe400078e0207 */
/*04b0*/ IMAD.WIDE R6, R6, R19.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe200078e0213 */
/*04c0*/ LDG.E R25, [R2.64+0x4] ; /* 0x0000040802197981 */
/* 0x000ee6000c1e1900 */
/*04d0*/ IMAD R26, R0, c[0x0][0x178], R5 ; /* 0x00005e00001a7a24 */
/* 0x000fe200078e0205 */
/*04e0*/ LDG.E R27, [R2.64+0x8] ; /* 0x00000808021b7981 */
/* 0x000f22000c1e1900 */
/*04f0*/ IMAD.WIDE R4, R8, R19, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fc600078e0213 */
/*0500*/ LDG.E R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ee2000c1e1900 */
/*0510*/ IMAD.WIDE R8, R26, R19, c[0x0][0x160] ; /* 0x000058001a087625 */
/* 0x000fc600078e0213 */
/*0520*/ LDG.E R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000f28000c1e1900 */
/*0530*/ LDG.E R9, [R8.64] ; /* 0x0000000808097981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R26, [R2.64+0xc] ; /* 0x00000c08021a7981 */
/* 0x000f62000c1e1900 */
/*0550*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0560*/ IADD3 R18, R18, 0x4, RZ ; /* 0x0000000412127810 */
/* 0x000fe20007ffe0ff */
/*0570*/ FFMA R21, R21, R22, R15 ; /* 0x0000001615157223 */
/* 0x004fc8000000000f */
/*0580*/ IADD3 R15, R23, UR4, RZ ; /* 0x00000004170f7c10 */
/* 0x000fc8000fffe0ff */
/*0590*/ ISETP.NE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f45270 */
/*05a0*/ FFMA R25, R25, R6, R21 ; /* 0x0000000619197223 */
/* 0x008fe20000000015 */
/*05b0*/ IADD3 R21, P3, R2, 0x10, RZ ; /* 0x0000001002157810 */
/* 0x000fc60007f7e0ff */
/*05c0*/ FFMA R25, R27, R4, R25 ; /* 0x000000041b197223 */
/* 0x010fe40000000019 */
/*05d0*/ IMAD.X R4, RZ, RZ, R3, P3 ; /* 0x000000ffff047224 */
/* 0x000fe400018e0603 */
/*05e0*/ FFMA R15, R26, R9, R25 ; /* 0x000000091a0f7223 */
/* 0x020fc80000000019 */
/*05f0*/ @P2 BRA 0x340 ; /* 0xfffffd4000002947 */
/* 0x000fea000383ffff */
/*0600*/ @!P1 BRA 0x820 ; /* 0x0000021000009947 */
/* 0x000fea0003800000 */
/*0610*/ IADD3 R9, R11, UR4, RZ ; /* 0x000000040b097c10 */
/* 0x000fe2000fffe0ff */
/*0620*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0630*/ IADD3 R7, R20, UR4, RZ ; /* 0x0000000414077c10 */
/* 0x000fe4000fffe0ff */
/*0640*/ IMNMX R2, RZ, R9, !PT ; /* 0x00000009ff027217 */
/* 0x000fc80007800200 */
/*0650*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fc80003f26270 */
/*0660*/ SEL R3, R2, UR6, !P1 ; /* 0x0000000602037c07 */
/* 0x000fca000c800000 */
/*0670*/ IMAD R5, R0, c[0x0][0x178], R3 ; /* 0x00005e0000057a24 */
/* 0x000fe400078e0203 */
/*0680*/ IMAD.WIDE R2, R7, R6, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fc800078e0206 */
/*0690*/ IMAD.WIDE R4, R5, R6, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0206 */
/*06a0*/ LDG.E R8, [R2.64] ; /* 0x0000000802087981 */
/* 0x000eaa000c1e1900 */
/*06b0*/ LDG.E R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ ISETP.NE.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe20003f25270 */
/*06d0*/ FFMA R15, R8, R4, R15 ; /* 0x00000004080f7223 */
/* 0x004fd8000000000f */
/*06e0*/ @!P1 BRA 0x820 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.NE.AND P2, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fe40003f45270 */
/*0700*/ IADD3 R4, R9, 0x1, RZ ; /* 0x0000000109047810 */
/* 0x000fc80007ffe0ff */
/*0710*/ IMNMX R4, RZ, R4, !PT ; /* 0x00000004ff047217 */
/* 0x000fc80007800200 */
/*0720*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc60003f26270 */
/*0730*/ @P2 IADD3 R5, R9, 0x2, RZ ; /* 0x0000000209052810 */
/* 0x000fe20007ffe0ff */
/*0740*/ @P2 LDG.E R8, [R2.64+0x8] ; /* 0x0000080802082981 */
/* 0x000ea6000c1e1900 */
/*0750*/ @P2 IMNMX R7, RZ, R5, !PT ; /* 0x00000005ff072217 */
/* 0x000fe40007800200 */
/*0760*/ SEL R5, R4, UR6, !P1 ; /* 0x0000000604057c07 */
/* 0x000fe4000c800000 */
/*0770*/ @P2 ISETP.GE.AND P3, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007002a0c */
/* 0x000fc60003f66270 */
/*0780*/ IMAD R5, R0, c[0x0][0x178], R5 ; /* 0x00005e0000057a24 */
/* 0x000fe200078e0205 */
/*0790*/ @P2 SEL R7, R7, UR6, !P3 ; /* 0x0000000607072c07 */
/* 0x000fc6000d800000 */
/*07a0*/ IMAD.WIDE R4, R5, R6, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0206 */
/*07b0*/ @P2 IMAD R7, R0, c[0x0][0x178], R7 ; /* 0x00005e0000072a24 */
/* 0x000fe400078e0207 */
/*07c0*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040802007981 */
/* 0x000ee4000c1e1900 */
/*07d0*/ @P2 IMAD.WIDE R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007062625 */
/* 0x000fe400078e0206 */
/*07e0*/ LDG.E R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ee8000c1e1900 */
/*07f0*/ @P2 LDG.E R6, [R6.64] ; /* 0x0000000806062981 */
/* 0x000ea2000c1e1900 */
/*0800*/ FFMA R15, R0, R4, R15 ; /* 0x00000004000f7223 */
/* 0x008fc8000000000f */
/*0810*/ @P2 FFMA R15, R8, R6, R15 ; /* 0x00000006080f2223 */
/* 0x004fe4000000000f */
/*0820*/ @!P0 BRA 0x230 ; /* 0xfffffa0000008947 */
/* 0x000fea000383ffff */
/*0830*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0840*/ IMAD R2, R17, c[0x0][0x178], R16 ; /* 0x00005e0011027a24 */
/* 0x000fe400078e0210 */
/*0850*/ FADD R15, |R15|, -RZ ; /* 0x800000ff0f0f7221 */
/* 0x000fe40000000200 */
/*0860*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0870*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101908 */
/*0880*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
#include <math.h>
#include <stdio.h>
#include <assert.h>
#include <fstream>
#include <time.h>
__global__ void image_convolution_kernel(float *input, float *out, float *kernelConv,
int img_width, const int img_height,
const int kernel_width, const int kernel_height )
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if ((x < img_width) && (y < img_height)){
float sum = 0;
for ( int j = 0; j < kernel_height; j++ )
{
for ( int i = 0; i < kernel_width; i++ )
{
int dX = x + i - kernel_width / 2;
int dY = y + j - kernel_height / 2;
if ( dX < 0 )
dX = 0;
if ( dX >= img_width )
dX = img_width - 1;
if ( dY < 0 )
dY = 0;
if ( dY >= img_height )
dY = img_height - 1;
const int idMat = j * kernel_width + i;
const int idPixel = dY * img_width + dX;
sum += (float)input[idPixel] * kernelConv[idMat];
}
}
const int idOut = y * img_width + x;
out[idOut] = abs(sum);
}
}
void MC(float * input,float* output, int img_height, int img_width, const int r, float & gpu_elapsed_time_ms)
{
// initialize kernel here
int kernel_height = r;
int kernel_width = r;
float *kernel;
kernel = new float[r*r];
for (int i = 0; i < r*r; i++){
kernel[i] = rand() % 10 + 1;
}
float * mask = new float[kernel_height*kernel_width];
for (int i = 0; i < kernel_height*kernel_width; i++)
{
mask[i] = kernel[i];
}
float * d_input, * d_output, * d_kernel;
cudaMalloc(&d_input, img_width*img_height*sizeof(float));
cudaMalloc(&d_output, img_width*img_height*sizeof(float));
cudaMalloc(&d_kernel, kernel_height*kernel_width*sizeof(float));
cudaMemcpy(d_input, input, img_width*img_height*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_kernel, mask, kernel_height*kernel_width*sizeof(float), cudaMemcpyHostToDevice);
dim3 blocksize(16,16);
dim3 gridsize;
gridsize.x=(img_width+blocksize.x-1)/blocksize.x;
gridsize.y=(img_height+blocksize.y-1)/blocksize.y;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
image_convolution_kernel<<<gridsize,blocksize>>>(d_input,d_output,d_kernel,img_width,img_height,kernel_width,kernel_height);
cudaMemcpy(output, d_output, img_width*img_height*sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
}
int main(){
// open the output file
std::ofstream ofile;
// customize output filename
ofile.open("matrix_conv_gpu_500_points_Quadro.csv");
// number of instances of data generated
int NUM = 500;
for (int iterator = 0; iterator < NUM; iterator++) {
if (iterator % 10 == 0) std::cout << "iter: " << iterator << std::endl;
float *in, *out;
int m = rand() % 1024 + 10;
int n = rand() % 1024 + 10;
int is = n * m;
int r = (rand() % 3 + 1) * 2 + 1;
in = new float[is];
out = new float[is];
// density
int power;
double d;
power = rand() % int((log2(double(m * n)) + 1));
d = 1 / pow(2, power);
// initialize matrix A
// if A is a sparse matrix
if (d <= 0.5) {
int count_a = m * n * d;
for (int it = 0; it < count_a; it++) {
int i = rand() % m;
int j = rand() % n;
in[i * n + j] = rand() % 1024 + 1;
}
// if A is a dense matrix
} else {
for (int i = 0; i < m * n; i++) {
in[i] = rand() % 1024 + 1;
}
}
float time;
// perform kernel operation
MC(in, out, n, m, r, time);
int c = (m-r+1)*(n-r+1)*r*r;
ofile << time / 1000;
ofile << "," << m << "," << n << "," << r << "," << d << "," << c << ",\n";
}
ofile.close();
return 0;
} | .file "tmpxft_00178e4e_00000000-6_MC_G_global.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3804:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3804:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii
.type _Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii, @function
_Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii:
.LFB3826:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24image_convolution_kernelPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3826:
.size _Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii, .-_Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii
.globl _Z24image_convolution_kernelPfS_S_iiii
.type _Z24image_convolution_kernelPfS_S_iiii, @function
_Z24image_convolution_kernelPfS_S_iiii:
.LFB3827:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3827:
.size _Z24image_convolution_kernelPfS_S_iiii, .-_Z24image_convolution_kernelPfS_S_iiii
.globl _Z2MCPfS_iiiRf
.type _Z2MCPfS_iiiRf, @function
_Z2MCPfS_iiiRf:
.LFB3800:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movl %edx, %r15d
movl %ecx, 4(%rsp)
movl %r8d, %r14d
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl %r8d, %ebx
imull %r8d, %ebx
movslq %ebx, %rbp
salq $2, %rbp
movq %rbp, %rdi
call _Znam@PLT
testl %ebx, %ebx
jle .L12
movq %rax, %r12
movq %rax, %rbx
leaq (%rax,%rbp), %r13
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r13, %rbx
jne .L13
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
movl $0, %eax
.L15:
movss (%r12,%rax), %xmm0
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L15
.L17:
movl 4(%rsp), %r13d
movl %r13d, %r12d
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 88(%rsp)
movl $1, 100(%rsp)
leal 15(%r13), %eax
shrl $4, %eax
movl %eax, 92(%rsp)
leal 15(%r15), %eax
shrl $4, %eax
movl %eax, 96(%rsp)
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L16:
movl $2, %ecx
movq %r12, %rdx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaEventElapsedTime@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq %r14
.cfi_def_cfa_offset 192
movl %r14d, %r9d
movl %r15d, %r8d
movl 20(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L16
.L12:
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
jmp .L17
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.size _Z2MCPfS_iiiRf, .-_Z2MCPfS_iiiRf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24image_convolution_kernelPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3829:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24image_convolution_kernelPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8
.align 8
.LC1:
.string "matrix_conv_gpu_500_points_Quadro.csv"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "iter: "
.LC7:
.string ","
.LC8:
.string ",\n"
.text
.globl main
.type main, @function
main:
.LFB3801:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3801
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $600, %rsp
.cfi_def_cfa_offset 656
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $16, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movl $0, 28(%rsp)
jmp .L42
.L59:
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L54
cmpb $0, 56(%rbp)
je .L32
movzbl 67(%rbp), %esi
.L33:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L55
.L54:
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L56
call _ZSt16__throw_bad_castv@PLT
.L46:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L44
call __stack_chk_fail@PLT
.L56:
call __stack_chk_fail@PLT
.L32:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L33
.L55:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L29:
call rand@PLT
cltd
shrl $22, %edx
leal (%rax,%rdx), %r12d
andl $1023, %r12d
subl %edx, %r12d
addl $10, %r12d
call rand@PLT
cltd
shrl $22, %edx
leal (%rax,%rdx), %ebp
andl $1023, %ebp
subl %edx, %ebp
addl $10, %ebp
movl %r12d, %r14d
imull %ebp, %r14d
call rand@PLT
movslq %eax, %rdx
imulq $1431655766, %rdx, %rdx
shrq $32, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,2), %edx
subl %edx, %eax
leal 3(%rax,%rax), %r15d
movslq %r14d, %rax
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L34
leaq 0(,%rax,4), %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movq %r13, %rdi
call _Znam@PLT
jmp .L57
.L34:
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L36
call __stack_chk_fail@PLT
.L36:
call __cxa_throw_bad_array_new_length@PLT
.L57:
movq %rax, 40(%rsp)
call rand@PLT
movl %eax, %ebx
pxor %xmm3, %xmm3
cvtsi2sdl %r14d, %xmm3
movsd %xmm3, 16(%rsp)
movapd %xmm3, %xmm0
call log2@PLT
addsd .LC3(%rip), %xmm0
cvttsd2sil %xmm0, %ecx
movl %ebx, %eax
cltd
idivl %ecx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
movsd .LC4(%rip), %xmm0
call pow@PLT
movsd .LC3(%rip), %xmm2
divsd %xmm0, %xmm2
movsd %xmm2, 32(%rsp)
movsd .LC5(%rip), %xmm4
comisd %xmm2, %xmm4
jnb .L37
movq 8(%rsp), %rax
movq %rax, %rbx
addq %rax, %r13
testl %r14d, %r14d
jle .L39
.L41:
call rand@PLT
cltd
shrl $22, %edx
addl %edx, %eax
andl $1023, %eax
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbx, %r13
jne .L41
jmp .L39
.L37:
movsd 16(%rsp), %xmm0
mulsd 32(%rsp), %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, 16(%rsp)
testl %eax, %eax
jle .L39
movl $0, %r13d
.L40:
call rand@PLT
cltd
idivl %r12d
movl %edx, %ebx
call rand@PLT
cltd
idivl %ebp
movl %edx, %r14d
call rand@PLT
imull %ebp, %ebx
addl %r14d, %ebx
movslq %ebx, %rbx
cltd
shrl $22, %edx
addl %edx, %eax
andl $1023, %eax
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%rbx,4)
addl $1, %r13d
cmpl %r13d, 16(%rsp)
jne .L40
.L39:
leaq 60(%rsp), %r9
movl %r15d, %r8d
movl %r12d, %ecx
movl %ebp, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z2MCPfS_iiiRf
movl %r12d, %ebx
subl %r15d, %ebx
addl $1, %ebx
movl %ebp, %eax
subl %r15d, %eax
addl $1, %eax
imull %eax, %ebx
imull %r15d, %ebx
imull %r15d, %ebx
movss 60(%rsp), %xmm0
divss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq 64(%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
leaq 64(%rsp), %rdi
movl $1, %edx
leaq .LC7(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 64(%rsp), %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r15d, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 32(%rsp), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC8(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, 28(%rsp)
movl 28(%rsp), %eax
cmpl $500, %eax
je .L58
.L42:
movl 28(%rsp), %ebx
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %eax, %ebx
jne .L29
movl $6, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L59
.L58:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.LEHE1:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3801:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3801-.LLSDACSB3801
.LLSDACSB3801:
.uleb128 .LEHB0-.LFB3801
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3801
.uleb128 .LEHE1-.LEHB1
.uleb128 .L46-.LFB3801
.uleb128 0
.uleb128 .LEHB2-.LFB3801
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3801:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long 0
.long 1073741824
.align 8
.LC5:
.long 0
.long 1071644672
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1148846080
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <math.h>
#include <stdio.h>
#include <assert.h>
#include <fstream>
#include <time.h>
__global__ void image_convolution_kernel(float *input, float *out, float *kernelConv,
int img_width, const int img_height,
const int kernel_width, const int kernel_height )
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if ((x < img_width) && (y < img_height)){
float sum = 0;
for ( int j = 0; j < kernel_height; j++ )
{
for ( int i = 0; i < kernel_width; i++ )
{
int dX = x + i - kernel_width / 2;
int dY = y + j - kernel_height / 2;
if ( dX < 0 )
dX = 0;
if ( dX >= img_width )
dX = img_width - 1;
if ( dY < 0 )
dY = 0;
if ( dY >= img_height )
dY = img_height - 1;
const int idMat = j * kernel_width + i;
const int idPixel = dY * img_width + dX;
sum += (float)input[idPixel] * kernelConv[idMat];
}
}
const int idOut = y * img_width + x;
out[idOut] = abs(sum);
}
}
void MC(float * input,float* output, int img_height, int img_width, const int r, float & gpu_elapsed_time_ms)
{
// initialize kernel here
int kernel_height = r;
int kernel_width = r;
float *kernel;
kernel = new float[r*r];
for (int i = 0; i < r*r; i++){
kernel[i] = rand() % 10 + 1;
}
float * mask = new float[kernel_height*kernel_width];
for (int i = 0; i < kernel_height*kernel_width; i++)
{
mask[i] = kernel[i];
}
float * d_input, * d_output, * d_kernel;
cudaMalloc(&d_input, img_width*img_height*sizeof(float));
cudaMalloc(&d_output, img_width*img_height*sizeof(float));
cudaMalloc(&d_kernel, kernel_height*kernel_width*sizeof(float));
cudaMemcpy(d_input, input, img_width*img_height*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_kernel, mask, kernel_height*kernel_width*sizeof(float), cudaMemcpyHostToDevice);
dim3 blocksize(16,16);
dim3 gridsize;
gridsize.x=(img_width+blocksize.x-1)/blocksize.x;
gridsize.y=(img_height+blocksize.y-1)/blocksize.y;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
image_convolution_kernel<<<gridsize,blocksize>>>(d_input,d_output,d_kernel,img_width,img_height,kernel_width,kernel_height);
cudaMemcpy(output, d_output, img_width*img_height*sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
}
int main(){
// open the output file
std::ofstream ofile;
// customize output filename
ofile.open("matrix_conv_gpu_500_points_Quadro.csv");
// number of instances of data generated
int NUM = 500;
for (int iterator = 0; iterator < NUM; iterator++) {
if (iterator % 10 == 0) std::cout << "iter: " << iterator << std::endl;
float *in, *out;
int m = rand() % 1024 + 10;
int n = rand() % 1024 + 10;
int is = n * m;
int r = (rand() % 3 + 1) * 2 + 1;
in = new float[is];
out = new float[is];
// density
int power;
double d;
power = rand() % int((log2(double(m * n)) + 1));
d = 1 / pow(2, power);
// initialize matrix A
// if A is a sparse matrix
if (d <= 0.5) {
int count_a = m * n * d;
for (int it = 0; it < count_a; it++) {
int i = rand() % m;
int j = rand() % n;
in[i * n + j] = rand() % 1024 + 1;
}
// if A is a dense matrix
} else {
for (int i = 0; i < m * n; i++) {
in[i] = rand() % 1024 + 1;
}
}
float time;
// perform kernel operation
MC(in, out, n, m, r, time);
int c = (m-r+1)*(n-r+1)*r*r;
ofile << time / 1000;
ofile << "," << m << "," << n << "," << r << "," << d << "," << c << ",\n";
}
ofile.close();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <math.h>
#include <stdio.h>
#include <assert.h>
#include <fstream>
#include <time.h>
__global__ void image_convolution_kernel(float *input, float *out, float *kernelConv,
int img_width, const int img_height,
const int kernel_width, const int kernel_height )
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if ((x < img_width) && (y < img_height)){
float sum = 0;
for ( int j = 0; j < kernel_height; j++ )
{
for ( int i = 0; i < kernel_width; i++ )
{
int dX = x + i - kernel_width / 2;
int dY = y + j - kernel_height / 2;
if ( dX < 0 )
dX = 0;
if ( dX >= img_width )
dX = img_width - 1;
if ( dY < 0 )
dY = 0;
if ( dY >= img_height )
dY = img_height - 1;
const int idMat = j * kernel_width + i;
const int idPixel = dY * img_width + dX;
sum += (float)input[idPixel] * kernelConv[idMat];
}
}
const int idOut = y * img_width + x;
out[idOut] = abs(sum);
}
}
void MC(float * input,float* output, int img_height, int img_width, const int r, float & gpu_elapsed_time_ms)
{
// initialize kernel here
int kernel_height = r;
int kernel_width = r;
float *kernel;
kernel = new float[r*r];
for (int i = 0; i < r*r; i++){
kernel[i] = rand() % 10 + 1;
}
float * mask = new float[kernel_height*kernel_width];
for (int i = 0; i < kernel_height*kernel_width; i++)
{
mask[i] = kernel[i];
}
float * d_input, * d_output, * d_kernel;
hipMalloc(&d_input, img_width*img_height*sizeof(float));
hipMalloc(&d_output, img_width*img_height*sizeof(float));
hipMalloc(&d_kernel, kernel_height*kernel_width*sizeof(float));
hipMemcpy(d_input, input, img_width*img_height*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_kernel, mask, kernel_height*kernel_width*sizeof(float), hipMemcpyHostToDevice);
dim3 blocksize(16,16);
dim3 gridsize;
gridsize.x=(img_width+blocksize.x-1)/blocksize.x;
gridsize.y=(img_height+blocksize.y-1)/blocksize.y;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
image_convolution_kernel<<<gridsize,blocksize>>>(d_input,d_output,d_kernel,img_width,img_height,kernel_width,kernel_height);
hipMemcpy(output, d_output, img_width*img_height*sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
}
int main(){
// open the output file
std::ofstream ofile;
// customize output filename
ofile.open("matrix_conv_gpu_500_points_Quadro.csv");
// number of instances of data generated
int NUM = 500;
for (int iterator = 0; iterator < NUM; iterator++) {
if (iterator % 10 == 0) std::cout << "iter: " << iterator << std::endl;
float *in, *out;
int m = rand() % 1024 + 10;
int n = rand() % 1024 + 10;
int is = n * m;
int r = (rand() % 3 + 1) * 2 + 1;
in = new float[is];
out = new float[is];
// density
int power;
double d;
power = rand() % int((log2(double(m * n)) + 1));
d = 1 / pow(2, power);
// initialize matrix A
// if A is a sparse matrix
if (d <= 0.5) {
int count_a = m * n * d;
for (int it = 0; it < count_a; it++) {
int i = rand() % m;
int j = rand() % n;
in[i * n + j] = rand() % 1024 + 1;
}
// if A is a dense matrix
} else {
for (int i = 0; i < m * n; i++) {
in[i] = rand() % 1024 + 1;
}
}
float time;
// perform kernel operation
MC(in, out, n, m, r, time);
int c = (m-r+1)*(n-r+1)*r*r;
ofile << time / 1000;
ofile << "," << m << "," << n << "," << r << "," << d << "," << c << ",\n";
}
ofile.close();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <math.h>
#include <stdio.h>
#include <assert.h>
#include <fstream>
#include <time.h>
__global__ void image_convolution_kernel(float *input, float *out, float *kernelConv,
int img_width, const int img_height,
const int kernel_width, const int kernel_height )
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if ((x < img_width) && (y < img_height)){
float sum = 0;
for ( int j = 0; j < kernel_height; j++ )
{
for ( int i = 0; i < kernel_width; i++ )
{
int dX = x + i - kernel_width / 2;
int dY = y + j - kernel_height / 2;
if ( dX < 0 )
dX = 0;
if ( dX >= img_width )
dX = img_width - 1;
if ( dY < 0 )
dY = 0;
if ( dY >= img_height )
dY = img_height - 1;
const int idMat = j * kernel_width + i;
const int idPixel = dY * img_width + dX;
sum += (float)input[idPixel] * kernelConv[idMat];
}
}
const int idOut = y * img_width + x;
out[idOut] = abs(sum);
}
}
void MC(float * input,float* output, int img_height, int img_width, const int r, float & gpu_elapsed_time_ms)
{
// initialize kernel here
int kernel_height = r;
int kernel_width = r;
float *kernel;
kernel = new float[r*r];
for (int i = 0; i < r*r; i++){
kernel[i] = rand() % 10 + 1;
}
float * mask = new float[kernel_height*kernel_width];
for (int i = 0; i < kernel_height*kernel_width; i++)
{
mask[i] = kernel[i];
}
float * d_input, * d_output, * d_kernel;
hipMalloc(&d_input, img_width*img_height*sizeof(float));
hipMalloc(&d_output, img_width*img_height*sizeof(float));
hipMalloc(&d_kernel, kernel_height*kernel_width*sizeof(float));
hipMemcpy(d_input, input, img_width*img_height*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_kernel, mask, kernel_height*kernel_width*sizeof(float), hipMemcpyHostToDevice);
dim3 blocksize(16,16);
dim3 gridsize;
gridsize.x=(img_width+blocksize.x-1)/blocksize.x;
gridsize.y=(img_height+blocksize.y-1)/blocksize.y;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
image_convolution_kernel<<<gridsize,blocksize>>>(d_input,d_output,d_kernel,img_width,img_height,kernel_width,kernel_height);
hipMemcpy(output, d_output, img_width*img_height*sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
}
int main(){
// open the output file
std::ofstream ofile;
// customize output filename
ofile.open("matrix_conv_gpu_500_points_Quadro.csv");
// number of instances of data generated
int NUM = 500;
for (int iterator = 0; iterator < NUM; iterator++) {
if (iterator % 10 == 0) std::cout << "iter: " << iterator << std::endl;
float *in, *out;
int m = rand() % 1024 + 10;
int n = rand() % 1024 + 10;
int is = n * m;
int r = (rand() % 3 + 1) * 2 + 1;
in = new float[is];
out = new float[is];
// density
int power;
double d;
power = rand() % int((log2(double(m * n)) + 1));
d = 1 / pow(2, power);
// initialize matrix A
// if A is a sparse matrix
if (d <= 0.5) {
int count_a = m * n * d;
for (int it = 0; it < count_a; it++) {
int i = rand() % m;
int j = rand() % n;
in[i * n + j] = rand() % 1024 + 1;
}
// if A is a dense matrix
} else {
for (int i = 0; i < m * n; i++) {
in[i] = rand() % 1024 + 1;
}
}
float time;
// perform kernel operation
MC(in, out, n, m, r, time);
int c = (m-r+1)*(n-r+1)*r*r;
ofile << time / 1000;
ofile << "," << m << "," << n << "," << r << "," << d << "," << c << ",\n";
}
ofile.close();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24image_convolution_kernelPfS_S_iiii
.globl _Z24image_convolution_kernelPfS_S_iiii
.p2align 8
.type _Z24image_convolution_kernelPfS_S_iiii,@function
_Z24image_convolution_kernelPfS_S_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s8, s14, s3
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_add_nc_u32_e32 v1, s8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
s_load_b32 s12, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x2
s_load_b32 s13, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s17, s9
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s13, 0
s_cselect_b32 s14, -1, 0
s_lshr_b32 s10, s13, 31
s_lshr_b32 s11, s12, 1
s_add_i32 s10, s13, s10
v_subrev_nc_u32_e32 v3, s11, v0
s_ashr_i32 s10, s10, 1
s_add_i32 s15, s4, -1
s_sub_i32 s8, s8, s10
s_add_i32 s16, s5, -1
v_add_nc_u32_e32 v4, s8, v4
s_mov_b32 s8, s9
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_add_i32 s17, s17, 1
s_add_i32 s8, s8, s13
s_cmp_eq_u32 s17, s12
s_cbranch_scc1 .LBB0_8
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_3
v_dual_mov_b32 v6, v4 :: v_dual_add_nc_u32 v5, s17, v3
s_lshl_b64 s[10:11], s[8:9], 2
s_mov_b32 s18, s13
s_add_u32 s10, s6, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v5, 0, v5
s_addc_u32 s11, s7, s11
v_cmp_gt_i32_e32 vcc_lo, s5, v5
v_cndmask_b32_e32 v5, s16, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s4
.p2align 6
.LBB0_6:
v_max_i32_e32 v7, 0, v6
s_load_b32 s19, s[10:11], 0x0
s_add_i32 s18, s18, -1
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
v_cmp_gt_i32_e32 vcc_lo, s4, v7
s_cmp_eq_u32 s18, 0
v_dual_cndmask_b32 v7, s15, v7 :: v_dual_add_nc_u32 v6, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, v7, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v2, s19, v7
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_3
.LBB0_7:
v_mov_b32_e32 v2, 0
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v0, s4, v[1:2]
v_and_b32_e32 v2, 0x7fffffff, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24image_convolution_kernelPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24image_convolution_kernelPfS_S_iiii, .Lfunc_end0-_Z24image_convolution_kernelPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24image_convolution_kernelPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z24image_convolution_kernelPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <math.h>
#include <stdio.h>
#include <assert.h>
#include <fstream>
#include <time.h>
__global__ void image_convolution_kernel(float *input, float *out, float *kernelConv,
int img_width, const int img_height,
const int kernel_width, const int kernel_height )
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if ((x < img_width) && (y < img_height)){
float sum = 0;
for ( int j = 0; j < kernel_height; j++ )
{
for ( int i = 0; i < kernel_width; i++ )
{
int dX = x + i - kernel_width / 2;
int dY = y + j - kernel_height / 2;
if ( dX < 0 )
dX = 0;
if ( dX >= img_width )
dX = img_width - 1;
if ( dY < 0 )
dY = 0;
if ( dY >= img_height )
dY = img_height - 1;
const int idMat = j * kernel_width + i;
const int idPixel = dY * img_width + dX;
sum += (float)input[idPixel] * kernelConv[idMat];
}
}
const int idOut = y * img_width + x;
out[idOut] = abs(sum);
}
}
void MC(float * input,float* output, int img_height, int img_width, const int r, float & gpu_elapsed_time_ms)
{
// initialize kernel here
int kernel_height = r;
int kernel_width = r;
float *kernel;
kernel = new float[r*r];
for (int i = 0; i < r*r; i++){
kernel[i] = rand() % 10 + 1;
}
float * mask = new float[kernel_height*kernel_width];
for (int i = 0; i < kernel_height*kernel_width; i++)
{
mask[i] = kernel[i];
}
float * d_input, * d_output, * d_kernel;
hipMalloc(&d_input, img_width*img_height*sizeof(float));
hipMalloc(&d_output, img_width*img_height*sizeof(float));
hipMalloc(&d_kernel, kernel_height*kernel_width*sizeof(float));
hipMemcpy(d_input, input, img_width*img_height*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_kernel, mask, kernel_height*kernel_width*sizeof(float), hipMemcpyHostToDevice);
dim3 blocksize(16,16);
dim3 gridsize;
gridsize.x=(img_width+blocksize.x-1)/blocksize.x;
gridsize.y=(img_height+blocksize.y-1)/blocksize.y;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
image_convolution_kernel<<<gridsize,blocksize>>>(d_input,d_output,d_kernel,img_width,img_height,kernel_width,kernel_height);
hipMemcpy(output, d_output, img_width*img_height*sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
}
int main(){
// open the output file
std::ofstream ofile;
// customize output filename
ofile.open("matrix_conv_gpu_500_points_Quadro.csv");
// number of instances of data generated
int NUM = 500;
for (int iterator = 0; iterator < NUM; iterator++) {
if (iterator % 10 == 0) std::cout << "iter: " << iterator << std::endl;
float *in, *out;
int m = rand() % 1024 + 10;
int n = rand() % 1024 + 10;
int is = n * m;
int r = (rand() % 3 + 1) * 2 + 1;
in = new float[is];
out = new float[is];
// density
int power;
double d;
power = rand() % int((log2(double(m * n)) + 1));
d = 1 / pow(2, power);
// initialize matrix A
// if A is a sparse matrix
if (d <= 0.5) {
int count_a = m * n * d;
for (int it = 0; it < count_a; it++) {
int i = rand() % m;
int j = rand() % n;
in[i * n + j] = rand() % 1024 + 1;
}
// if A is a dense matrix
} else {
for (int i = 0; i < m * n; i++) {
in[i] = rand() % 1024 + 1;
}
}
float time;
// perform kernel operation
MC(in, out, n, m, r, time);
int c = (m-r+1)*(n-r+1)*r*r;
ofile << time / 1000;
ofile << "," << m << "," << n << "," << r << "," << d << "," << c << ",\n";
}
ofile.close();
return 0;
} | .text
.file "MC_G_global.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z39__device_stub__image_convolution_kernelPfS_S_iiii # -- Begin function _Z39__device_stub__image_convolution_kernelPfS_S_iiii
.p2align 4, 0x90
.type _Z39__device_stub__image_convolution_kernelPfS_S_iiii,@function
_Z39__device_stub__image_convolution_kernelPfS_S_iiii: # @_Z39__device_stub__image_convolution_kernelPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24image_convolution_kernelPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__image_convolution_kernelPfS_S_iiii, .Lfunc_end0-_Z39__device_stub__image_convolution_kernelPfS_S_iiii
.cfi_endproc
# -- End function
.globl _Z2MCPfS_iiiRf # -- Begin function _Z2MCPfS_iiiRf
.p2align 4, 0x90
.type _Z2MCPfS_iiiRf,@function
_Z2MCPfS_iiiRf: # @_Z2MCPfS_iiiRf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 96(%rsp) # 8-byte Spill
movl %r8d, %ebp
# kill: def $ecx killed $ecx def $rcx
movq %rcx, 80(%rsp) # 8-byte Spill
# kill: def $edx killed $edx def $rdx
movq %rdx, 72(%rsp) # 8-byte Spill
movq %rsi, 88(%rsp) # 8-byte Spill
movq %rdi, 64(%rsp) # 8-byte Spill
movl %r8d, %r13d
imull %r13d, %r13d
leaq (,%r13,4), %rbx
movq %rbx, %rdi
callq _Znam
movq %rax, %r14
testl %ebp, %ebp
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
cmpl $1, %r13d
movl %r13d, %r15d
adcl $0, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq %rbx, %rdi
callq _Znam
movq %rax, %r15
testl %ebp, %ebp
je .LBB1_5
# %bb.4: # %.lr.ph61.preheader
cmpl $1, %r13d
adcl $0, %r13d
shlq $2, %r13
movq %r15, %rdi
movq %r14, %rsi
movq %r13, %rdx
callq memcpy@PLT
.LBB1_5: # %._crit_edge62
movq 80(%rsp), %r14 # 8-byte Reload
movl %r14d, %eax
movq 72(%rsp), %r12 # 8-byte Reload
imull %r12d, %eax
movslq %eax, %r13
shlq $2, %r13
leaq 56(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 56(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r14), %eax
shrl $4, %eax
leal 15(%r12), %ebx
shrl $4, %ebx
shlq $32, %rbx
orq %rax, %rbx
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %r14d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %ebp, 20(%rsp)
movl %ebp, 16(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 20(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z24image_convolution_kernelPfS_S_iiii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 48(%rsp), %rsi
movq 88(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
movq 96(%rsp), %rdi # 8-byte Reload
callq hipEventElapsedTime
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z2MCPfS_iiiRf, .Lfunc_end1-_Z2MCPfS_iiiRf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3ff0000000000000 # double 1
.LCPI2_1:
.quad 0x3fe0000000000000 # double 0.5
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_2:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $584, %rsp # imm = 0x248
.cfi_def_cfa_offset 640
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 72(%rsp), %rbx
movq %rbx, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
leaq 80(%rsp), %rdi
.Ltmp0:
movl $.L.str, %esi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 72(%rsp), %rcx
addq -24(%rcx), %rbx
xorl %esi, %esi
testq %rax, %rax
jne .LBB2_3
# %bb.2:
movl 32(%rbx), %esi
orl $4, %esi
.LBB2_3: # %.invoke
.Ltmp2:
movq %rbx, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_5: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
# =>This Loop Header: Depth=1
# Child Loop BB2_32 Depth 2
# Child Loop BB2_27 Depth 2
imull $-858993459, %ebp, %eax # imm = 0xCCCCCCCD
rorl %eax
cmpl $429496729, %eax # imm = 0x19999999
ja .LBB2_22
# %bb.6: # in Loop: Header=BB2_5 Depth=1
.Ltmp5:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp6:
# %bb.7: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB2_5 Depth=1
.Ltmp7:
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
.Ltmp8:
# %bb.8: # in Loop: Header=BB2_5 Depth=1
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_9
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_5 Depth=1
cmpb $0, 56(%r14)
je .LBB2_18
# %bb.17: # in Loop: Header=BB2_5 Depth=1
movzbl 67(%r14), %eax
jmp .LBB2_20
.LBB2_18: # in Loop: Header=BB2_5 Depth=1
.Ltmp9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp10:
# %bb.19: # %.noexc85
# in Loop: Header=BB2_5 Depth=1
movq (%r14), %rax
.Ltmp11:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp12:
.LBB2_20: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB2_5 Depth=1
.Ltmp13:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp14:
# %bb.21: # %.noexc87
# in Loop: Header=BB2_5 Depth=1
.Ltmp15:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp16:
.LBB2_22: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB2_5 Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
movl %ecx, 12(%rsp) # 4-byte Spill
# kill: def $ecx killed $ecx def $rcx
negl %ecx
movq %rax, 48(%rsp) # 8-byte Spill
leal (%rax,%rcx), %r15d
addl $10, %r15d
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
movl %ecx, 8(%rsp) # 4-byte Spill
# kill: def $ecx killed $ecx def $rcx
negl %ecx
movq %rax, 40(%rsp) # 8-byte Spill
leal (%rax,%rcx), %ebx
addl $10, %ebx
movl %ebx, %r13d
imull %r15d, %r13d
callq rand
movl %eax, 16(%rsp) # 4-byte Spill
movslq %r13d, %rax
leaq (,%rax,4), %r14
testl %eax, %eax
movq $-1, %rax
cmovsq %rax, %r14
.Ltmp18:
movq %r14, %rdi
callq _Znam
.Ltmp19:
# %bb.23: # in Loop: Header=BB2_5 Depth=1
.Ltmp20:
movq %rax, %r12
movq %r14, %rdi
callq _Znam
movq %rax, 64(%rsp) # 8-byte Spill
.Ltmp21:
# %bb.24: # in Loop: Header=BB2_5 Depth=1
movq %rbp, 56(%rsp) # 8-byte Spill
callq rand
movl %eax, %r14d
cvtsi2sd %r13d, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq log2
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
cvttsd2si %xmm0, %ecx
movl %r14d, %eax
cltd
idivl %ecx
movl %edx, %edi
movapd %xmm1, %xmm0
callq ldexp@PLT
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm1, %xmm0
movsd %xmm1, 32(%rsp) # 8-byte Spill
jae .LBB2_31
# %bb.25: # %.preheader
# in Loop: Header=BB2_5 Depth=1
testl %r13d, %r13d
jle .LBB2_33
# %bb.26: # %.lr.ph93.preheader
# in Loop: Header=BB2_5 Depth=1
movl %r13d, %r14d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_27: # %.lr.ph93
# Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq %r13, %r14
jne .LBB2_27
jmp .LBB2_33
.p2align 4, 0x90
.LBB2_31: # in Loop: Header=BB2_5 Depth=1
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd %xmm1, %xmm0
cvttsd2si %xmm0, %ebp
testl %ebp, %ebp
jle .LBB2_33
.p2align 4, 0x90
.LBB2_32: # %.lr.ph
# Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltd
idivl %r15d
movl %edx, %r14d
callq rand
cltd
idivl %ebx
movl %edx, %r13d
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
imull %ebx, %r14d
addl %r13d, %r14d
movslq %r14d, %rax
movss %xmm0, (%r12,%rax,4)
decl %ebp
jne .LBB2_32
.LBB2_33: # %.loopexit
# in Loop: Header=BB2_5 Depth=1
.Ltmp23:
movslq 16(%rsp), %r13 # 4-byte Folded Reload
imulq $1431655766, %r13, %rax # imm = 0x55555556
movq %rax, %rcx
shrq $63, %rcx
shrq $32, %rax
addl %ecx, %eax
leal (%rax,%rax,2), %eax
subl %eax, %r13d
leal 3(,%r13,2), %r14d
movq %r12, %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movl %ebx, %edx
movl %r15d, %ecx
movl %r14d, %r8d
leaq 20(%rsp), %r9
callq _Z2MCPfS_iiiRf
.Ltmp24:
# %bb.34: # in Loop: Header=BB2_5 Depth=1
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
.Ltmp26:
leaq 72(%rsp), %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp27:
movq 56(%rsp), %rbp # 8-byte Reload
# %bb.35: # %_ZNSolsEf.exit
# in Loop: Header=BB2_5 Depth=1
.Ltmp28:
movl $.L.str.2, %esi
movl $1, %edx
leaq 72(%rsp), %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp29:
# %bb.36: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit72
# in Loop: Header=BB2_5 Depth=1
.Ltmp30:
leaq 72(%rsp), %rdi
movl %r15d, %esi
callq _ZNSolsEi
.Ltmp31:
# %bb.37: # in Loop: Header=BB2_5 Depth=1
.Ltmp32:
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp33:
# %bb.38: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit74
# in Loop: Header=BB2_5 Depth=1
.Ltmp34:
movq %r15, %rdi
movl %ebx, %esi
callq _ZNSolsEi
.Ltmp35:
# %bb.39: # in Loop: Header=BB2_5 Depth=1
.Ltmp36:
movq %rax, %rbx
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp37:
# %bb.40: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit76
# in Loop: Header=BB2_5 Depth=1
.Ltmp38:
movq %rbx, %rdi
movl %r14d, %esi
callq _ZNSolsEi
.Ltmp39:
# %bb.41: # in Loop: Header=BB2_5 Depth=1
.Ltmp40:
movq %rax, %rbx
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp41:
# %bb.42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit78
# in Loop: Header=BB2_5 Depth=1
.Ltmp42:
movq %rbx, %rdi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp43:
# %bb.43: # %_ZNSolsEd.exit
# in Loop: Header=BB2_5 Depth=1
.Ltmp44:
movq %rax, %rbx
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp45:
# %bb.44: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit81
# in Loop: Header=BB2_5 Depth=1
.Ltmp46:
movq 48(%rsp), %rax # 8-byte Reload
subl 12(%rsp), %eax # 4-byte Folded Reload
movq 40(%rsp), %rcx # 8-byte Reload
subl 8(%rsp), %ecx # 4-byte Folded Reload
addl %r13d, %r13d
subl %r13d, %eax
addl $8, %eax
subl %r13d, %ecx
addl $8, %ecx
imull %eax, %ecx
imull %r14d, %r14d
imull %ecx, %r14d
movq %rbx, %rdi
movl %r14d, %esi
callq _ZNSolsEi
.Ltmp47:
# %bb.45: # in Loop: Header=BB2_5 Depth=1
.Ltmp48:
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp49:
# %bb.46: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit83
# in Loop: Header=BB2_5 Depth=1
incl %ebp
cmpl $500, %ebp # imm = 0x1F4
jne .LBB2_5
# %bb.10:
.Ltmp51:
leaq 80(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp52:
# %bb.11: # %.noexc66
testq %rax, %rax
jne .LBB2_13
# %bb.12:
movq 72(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $72, %rdi
movl 104(%rsp,%rax), %esi
orl $4, %esi
.Ltmp53:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp54:
.LBB2_13: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
leaq 72(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $584, %rsp # imm = 0x248
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_9:
.cfi_def_cfa_offset 640
.Ltmp56:
callq _ZSt16__throw_bad_castv
.Ltmp57:
# %bb.15: # %.noexc84
.LBB2_49:
.Ltmp55:
jmp .LBB2_50
.LBB2_14:
.Ltmp4:
jmp .LBB2_50
.LBB2_29: # %.loopexit.split-lp
.Ltmp58:
jmp .LBB2_50
.LBB2_47:
.Ltmp25:
jmp .LBB2_50
.LBB2_28: # %.loopexit90
.Ltmp17:
jmp .LBB2_50
.LBB2_30:
.Ltmp22:
jmp .LBB2_50
.LBB2_48:
.Ltmp50:
.LBB2_50:
movq %rax, %rbx
leaq 72(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp16-.Ltmp5 # Call between .Ltmp5 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp21-.Ltmp18 # Call between .Ltmp18 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp23-.Ltmp21 # Call between .Ltmp21 and .Ltmp23
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp49-.Ltmp26 # Call between .Ltmp26 and .Ltmp49
.uleb128 .Ltmp50-.Lfunc_begin0 # jumps to .Ltmp50
.byte 0 # On action: cleanup
.uleb128 .Ltmp51-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp54-.Ltmp51 # Call between .Ltmp51 and .Ltmp54
.uleb128 .Ltmp55-.Lfunc_begin0 # jumps to .Ltmp55
.byte 0 # On action: cleanup
.uleb128 .Ltmp56-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp57-.Ltmp56 # Call between .Ltmp56 and .Ltmp57
.uleb128 .Ltmp58-.Lfunc_begin0 # jumps to .Ltmp58
.byte 0 # On action: cleanup
.uleb128 .Ltmp57-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end2-.Ltmp57 # Call between .Ltmp57 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24image_convolution_kernelPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24image_convolution_kernelPfS_S_iiii,@object # @_Z24image_convolution_kernelPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z24image_convolution_kernelPfS_S_iiii
.p2align 3, 0x0
_Z24image_convolution_kernelPfS_S_iiii:
.quad _Z39__device_stub__image_convolution_kernelPfS_S_iiii
.size _Z24image_convolution_kernelPfS_S_iiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "matrix_conv_gpu_500_points_Quadro.csv"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "iter: "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ","
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ",\n"
.size .L.str.3, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24image_convolution_kernelPfS_S_iiii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__image_convolution_kernelPfS_S_iiii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z24image_convolution_kernelPfS_S_iiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24image_convolution_kernelPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R17, R17, c[0x0][0x4], R0 ; /* 0x0000010011117a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x17c], PT ; /* 0x00005f0011007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R16, R3, c[0x0][0x0], R2 ; /* 0x0000000003107a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R16, c[0x0][0x178], P0 ; /* 0x00005e0010007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff047624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e00ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x830 ; /* 0x0000074000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0e7624 */
/* 0x000fca00078e00ff */
/*0100*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0110*/ @!P0 BRA 0x830 ; /* 0x0000071000008947 */
/* 0x000fea0003800000 */
/*0120*/ LEA.HI R0, R14.reuse, c[0x0][0x180], RZ, 0x1 ; /* 0x000060000e007a11 */
/* 0x040fe200078f08ff */
/*0130*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R24, R14.reuse, -0x1, RZ ; /* 0xffffffff0e187810 */
/* 0x040fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0160*/ SHF.R.S32.HI R11, RZ, 0x1, R0 ; /* 0x00000001ff0b7819 */
/* 0x000fe20000011400 */
/*0170*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*0180*/ LOP3.LUT R14, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e0e7812 */
/* 0x000fe200078ec0ff */
/*0190*/ UIADD3 UR5, UR5, -0x1, URZ ; /* 0xffffffff05057890 */
/* 0x000fe4000fffe03f */
/*01a0*/ IMAD.IADD R0, R2, 0x1, -R11.reuse ; /* 0x0000000102007824 */
/* 0x100fe200078e0a0b */
/*01b0*/ LEA.HI R2, R4, c[0x0][0x184], RZ, 0x1 ; /* 0x0000610004027a11 */
/* 0x000fe200078f08ff */
/*01c0*/ IMAD.IADD R11, R16, 0x1, -R11 ; /* 0x00000001100b7824 */
/* 0x000fe200078e0a0b */
/*01d0*/ IADD3 R23, R14, -c[0x0][0x180], RZ ; /* 0x800060000e177a10 */
/* 0x000fe20007ffe0ff */
/*01e0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x000fe200078e0200 */
/*01f0*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011402 */
/*0200*/ UIADD3 UR6, UR4, -0x1, URZ ; /* 0xffffffff04067890 */
/* 0x000fc6000fffe03f */
/*0210*/ IADD3 R10, R0, 0x3, RZ ; /* 0x00000003000a7810 */
/* 0x000fe20007ffe0ff */
/*0220*/ IMAD.IADD R12, R17, 0x1, -R2 ; /* 0x00000001110c7824 */
/* 0x000fc800078e0a02 */
/*0230*/ IMAD.IADD R0, R12, 0x1, R13 ; /* 0x000000010c007824 */
/* 0x000fe200078e020d */
/*0240*/ ISETP.GE.U32.AND P3, PT, R24, 0x3, PT ; /* 0x000000031800780c */
/* 0x000fe20003f66070 */
/*0250*/ IMAD R20, R13.reuse, c[0x0][0x180], RZ ; /* 0x000060000d147a24 */
/* 0x040fe200078e02ff */
/*0260*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*0270*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0280*/ IMNMX R0, RZ, R0, !PT ; /* 0x00000000ff007217 */
/* 0x000fe40007800200 */
/*0290*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f25270 */
/*02a0*/ ISETP.GE.AND P2, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fc40003f46270 */
/*02b0*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x184], PT ; /* 0x000061000d007a0c */
/* 0x000fe40003f06270 */
/*02c0*/ SEL R0, R0, UR5, !P2 ; /* 0x0000000500007c07 */
/* 0x000fe2000d000000 */
/*02d0*/ @!P3 BRA 0x600 ; /* 0x000003200000b947 */
/* 0x000fec0003800000 */
/*02e0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fe200078e00ff */
/*02f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0300*/ IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff127224 */
/* 0x000fe400078e000a */
/*0310*/ IMAD.WIDE R2, R20, R19, c[0x0][0x170] ; /* 0x00005c0014027625 */
/* 0x000fc800078e0213 */
/*0320*/ IMAD.MOV.U32 R21, RZ, RZ, R2 ; /* 0x000000ffff157224 */
/* 0x000fe400078e0002 */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0003 */
/*0340*/ IADD3 R2, R18.reuse, -0x3, RZ ; /* 0xfffffffd12027810 */
/* 0x040fe40007ffe0ff */
/*0350*/ IADD3 R3, R18, -0x2, RZ ; /* 0xfffffffe12037810 */
/* 0x000fe40007ffe0ff */
/*0360*/ IMNMX R2, RZ, R2, !PT ; /* 0x00000002ff027217 */
/* 0x000fe40007800200 */
/*0370*/ IMNMX R5, RZ, R3, !PT ; /* 0x00000003ff057217 */
/* 0x000fe40007800200 */
/*0380*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fc40003f46270 */
/*0390*/ IADD3 R6, R18, -0x1, RZ ; /* 0xffffffff12067810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ SEL R3, R2, UR6, !P2 ; /* 0x0000000602037c07 */
/* 0x000fe4000d000000 */
/*03b0*/ IMNMX R6, RZ, R6, !PT ; /* 0x00000006ff067217 */
/* 0x000fe40007800200 */
/*03c0*/ ISETP.GE.AND P3, PT, R5.reuse, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x040fe20003f66270 */
/*03d0*/ IMAD R2, R0, c[0x0][0x178], R3 ; /* 0x00005e0000027a24 */
/* 0x000fe200078e0203 */
/*03e0*/ IMNMX R8, RZ, R18, !PT ; /* 0x00000012ff087217 */
/* 0x000fe40007800200 */
/*03f0*/ ISETP.GE.AND P2, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fe20003f46270 */
/*0400*/ IMAD.WIDE R2, R2, R19, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0213 */
/*0410*/ SEL R5, R5, UR6, !P3 ; /* 0x0000000605057c07 */
/* 0x000fc4000d800000 */
/*0420*/ ISETP.GE.AND P3, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fe40003f66270 */
/*0430*/ LDG.E R22, [R2.64] ; /* 0x0000000802167981 */
/* 0x0000a2000c1e1900 */
/*0440*/ SEL R7, R6, UR6, !P2 ; /* 0x0000000606077c07 */
/* 0x000fe2000d000000 */
/*0450*/ IMAD R6, R0, c[0x0][0x178], R5 ; /* 0x00005e0000067a24 */
/* 0x000fe400078e0205 */
/*0460*/ IMAD.MOV.U32 R2, RZ, RZ, R21 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0015 */
/*0470*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0004 */
/*0480*/ SEL R5, R8, UR6, !P3 ; /* 0x0000000608057c07 */
/* 0x000fc8000d800000 */
/*0490*/ LDG.E R21, [R2.64] ; /* 0x0000000802157981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IMAD R8, R0, c[0x0][0x178], R7 ; /* 0x00005e0000087a24 */
/* 0x000fe400078e0207 */
/*04b0*/ IMAD.WIDE R6, R6, R19.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe200078e0213 */
/*04c0*/ LDG.E R25, [R2.64+0x4] ; /* 0x0000040802197981 */
/* 0x000ee6000c1e1900 */
/*04d0*/ IMAD R26, R0, c[0x0][0x178], R5 ; /* 0x00005e00001a7a24 */
/* 0x000fe200078e0205 */
/*04e0*/ LDG.E R27, [R2.64+0x8] ; /* 0x00000808021b7981 */
/* 0x000f22000c1e1900 */
/*04f0*/ IMAD.WIDE R4, R8, R19, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fc600078e0213 */
/*0500*/ LDG.E R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ee2000c1e1900 */
/*0510*/ IMAD.WIDE R8, R26, R19, c[0x0][0x160] ; /* 0x000058001a087625 */
/* 0x000fc600078e0213 */
/*0520*/ LDG.E R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000f28000c1e1900 */
/*0530*/ LDG.E R9, [R8.64] ; /* 0x0000000808097981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R26, [R2.64+0xc] ; /* 0x00000c08021a7981 */
/* 0x000f62000c1e1900 */
/*0550*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0560*/ IADD3 R18, R18, 0x4, RZ ; /* 0x0000000412127810 */
/* 0x000fe20007ffe0ff */
/*0570*/ FFMA R21, R21, R22, R15 ; /* 0x0000001615157223 */
/* 0x004fc8000000000f */
/*0580*/ IADD3 R15, R23, UR4, RZ ; /* 0x00000004170f7c10 */
/* 0x000fc8000fffe0ff */
/*0590*/ ISETP.NE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f45270 */
/*05a0*/ FFMA R25, R25, R6, R21 ; /* 0x0000000619197223 */
/* 0x008fe20000000015 */
/*05b0*/ IADD3 R21, P3, R2, 0x10, RZ ; /* 0x0000001002157810 */
/* 0x000fc60007f7e0ff */
/*05c0*/ FFMA R25, R27, R4, R25 ; /* 0x000000041b197223 */
/* 0x010fe40000000019 */
/*05d0*/ IMAD.X R4, RZ, RZ, R3, P3 ; /* 0x000000ffff047224 */
/* 0x000fe400018e0603 */
/*05e0*/ FFMA R15, R26, R9, R25 ; /* 0x000000091a0f7223 */
/* 0x020fc80000000019 */
/*05f0*/ @P2 BRA 0x340 ; /* 0xfffffd4000002947 */
/* 0x000fea000383ffff */
/*0600*/ @!P1 BRA 0x820 ; /* 0x0000021000009947 */
/* 0x000fea0003800000 */
/*0610*/ IADD3 R9, R11, UR4, RZ ; /* 0x000000040b097c10 */
/* 0x000fe2000fffe0ff */
/*0620*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0630*/ IADD3 R7, R20, UR4, RZ ; /* 0x0000000414077c10 */
/* 0x000fe4000fffe0ff */
/*0640*/ IMNMX R2, RZ, R9, !PT ; /* 0x00000009ff027217 */
/* 0x000fc80007800200 */
/*0650*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fc80003f26270 */
/*0660*/ SEL R3, R2, UR6, !P1 ; /* 0x0000000602037c07 */
/* 0x000fca000c800000 */
/*0670*/ IMAD R5, R0, c[0x0][0x178], R3 ; /* 0x00005e0000057a24 */
/* 0x000fe400078e0203 */
/*0680*/ IMAD.WIDE R2, R7, R6, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fc800078e0206 */
/*0690*/ IMAD.WIDE R4, R5, R6, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe200078e0206 */
/*06a0*/ LDG.E R8, [R2.64] ; /* 0x0000000802087981 */
/* 0x000eaa000c1e1900 */
/*06b0*/ LDG.E R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ ISETP.NE.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe20003f25270 */
/*06d0*/ FFMA R15, R8, R4, R15 ; /* 0x00000004080f7223 */
/* 0x004fd8000000000f */
/*06e0*/ @!P1 BRA 0x820 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.NE.AND P2, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fe40003f45270 */
/*0700*/ IADD3 R4, R9, 0x1, RZ ; /* 0x0000000109047810 */
/* 0x000fc80007ffe0ff */
/*0710*/ IMNMX R4, RZ, R4, !PT ; /* 0x00000004ff047217 */
/* 0x000fc80007800200 */
/*0720*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc60003f26270 */
/*0730*/ @P2 IADD3 R5, R9, 0x2, RZ ; /* 0x0000000209052810 */
/* 0x000fe20007ffe0ff */
/*0740*/ @P2 LDG.E R8, [R2.64+0x8] ; /* 0x0000080802082981 */
/* 0x000ea6000c1e1900 */
/*0750*/ @P2 IMNMX R7, RZ, R5, !PT ; /* 0x00000005ff072217 */
/* 0x000fe40007800200 */
/*0760*/ SEL R5, R4, UR6, !P1 ; /* 0x0000000604057c07 */
/* 0x000fe4000c800000 */
/*0770*/ @P2 ISETP.GE.AND P3, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007002a0c */
/* 0x000fc60003f66270 */
/*0780*/ IMAD R5, R0, c[0x0][0x178], R5 ; /* 0x00005e0000057a24 */
/* 0x000fe200078e0205 */
/*0790*/ @P2 SEL R7, R7, UR6, !P3 ; /* 0x0000000607072c07 */
/* 0x000fc6000d800000 */
/*07a0*/ IMAD.WIDE R4, R5, R6, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0206 */
/*07b0*/ @P2 IMAD R7, R0, c[0x0][0x178], R7 ; /* 0x00005e0000072a24 */
/* 0x000fe400078e0207 */
/*07c0*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040802007981 */
/* 0x000ee4000c1e1900 */
/*07d0*/ @P2 IMAD.WIDE R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007062625 */
/* 0x000fe400078e0206 */
/*07e0*/ LDG.E R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ee8000c1e1900 */
/*07f0*/ @P2 LDG.E R6, [R6.64] ; /* 0x0000000806062981 */
/* 0x000ea2000c1e1900 */
/*0800*/ FFMA R15, R0, R4, R15 ; /* 0x00000004000f7223 */
/* 0x008fc8000000000f */
/*0810*/ @P2 FFMA R15, R8, R6, R15 ; /* 0x00000006080f2223 */
/* 0x004fe4000000000f */
/*0820*/ @!P0 BRA 0x230 ; /* 0xfffffa0000008947 */
/* 0x000fea000383ffff */
/*0830*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0840*/ IMAD R2, R17, c[0x0][0x178], R16 ; /* 0x00005e0011027a24 */
/* 0x000fe400078e0210 */
/*0850*/ FADD R15, |R15|, -RZ ; /* 0x800000ff0f0f7221 */
/* 0x000fe40000000200 */
/*0860*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0870*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101908 */
/*0880*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24image_convolution_kernelPfS_S_iiii
.globl _Z24image_convolution_kernelPfS_S_iiii
.p2align 8
.type _Z24image_convolution_kernelPfS_S_iiii,@function
_Z24image_convolution_kernelPfS_S_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s8, s14, s3
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_add_nc_u32_e32 v1, s8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
s_load_b32 s12, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x2
s_load_b32 s13, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s17, s9
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s13, 0
s_cselect_b32 s14, -1, 0
s_lshr_b32 s10, s13, 31
s_lshr_b32 s11, s12, 1
s_add_i32 s10, s13, s10
v_subrev_nc_u32_e32 v3, s11, v0
s_ashr_i32 s10, s10, 1
s_add_i32 s15, s4, -1
s_sub_i32 s8, s8, s10
s_add_i32 s16, s5, -1
v_add_nc_u32_e32 v4, s8, v4
s_mov_b32 s8, s9
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_add_i32 s17, s17, 1
s_add_i32 s8, s8, s13
s_cmp_eq_u32 s17, s12
s_cbranch_scc1 .LBB0_8
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_3
v_dual_mov_b32 v6, v4 :: v_dual_add_nc_u32 v5, s17, v3
s_lshl_b64 s[10:11], s[8:9], 2
s_mov_b32 s18, s13
s_add_u32 s10, s6, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v5, 0, v5
s_addc_u32 s11, s7, s11
v_cmp_gt_i32_e32 vcc_lo, s5, v5
v_cndmask_b32_e32 v5, s16, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s4
.p2align 6
.LBB0_6:
v_max_i32_e32 v7, 0, v6
s_load_b32 s19, s[10:11], 0x0
s_add_i32 s18, s18, -1
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
v_cmp_gt_i32_e32 vcc_lo, s4, v7
s_cmp_eq_u32 s18, 0
v_dual_cndmask_b32 v7, s15, v7 :: v_dual_add_nc_u32 v6, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, v7, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v2, s19, v7
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_3
.LBB0_7:
v_mov_b32_e32 v2, 0
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v0, s4, v[1:2]
v_and_b32_e32 v2, 0x7fffffff, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24image_convolution_kernelPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24image_convolution_kernelPfS_S_iiii, .Lfunc_end0-_Z24image_convolution_kernelPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24image_convolution_kernelPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z24image_convolution_kernelPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00178e4e_00000000-6_MC_G_global.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3804:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3804:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii
.type _Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii, @function
_Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii:
.LFB3826:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24image_convolution_kernelPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3826:
.size _Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii, .-_Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii
.globl _Z24image_convolution_kernelPfS_S_iiii
.type _Z24image_convolution_kernelPfS_S_iiii, @function
_Z24image_convolution_kernelPfS_S_iiii:
.LFB3827:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3827:
.size _Z24image_convolution_kernelPfS_S_iiii, .-_Z24image_convolution_kernelPfS_S_iiii
.globl _Z2MCPfS_iiiRf
.type _Z2MCPfS_iiiRf, @function
_Z2MCPfS_iiiRf:
.LFB3800:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movl %edx, %r15d
movl %ecx, 4(%rsp)
movl %r8d, %r14d
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl %r8d, %ebx
imull %r8d, %ebx
movslq %ebx, %rbp
salq $2, %rbp
movq %rbp, %rdi
call _Znam@PLT
testl %ebx, %ebx
jle .L12
movq %rax, %r12
movq %rax, %rbx
leaq (%rax,%rbp), %r13
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r13, %rbx
jne .L13
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
movl $0, %eax
.L15:
movss (%r12,%rax), %xmm0
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L15
.L17:
movl 4(%rsp), %r13d
movl %r13d, %r12d
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 88(%rsp)
movl $1, 100(%rsp)
leal 15(%r13), %eax
shrl $4, %eax
movl %eax, 92(%rsp)
leal 15(%r15), %eax
shrl $4, %eax
movl %eax, 96(%rsp)
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L16:
movl $2, %ecx
movq %r12, %rdx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaEventElapsedTime@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq %r14
.cfi_def_cfa_offset 192
movl %r14d, %r9d
movl %r15d, %r8d
movl 20(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z52__device_stub__Z24image_convolution_kernelPfS_S_iiiiPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L16
.L12:
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
jmp .L17
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.size _Z2MCPfS_iiiRf, .-_Z2MCPfS_iiiRf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24image_convolution_kernelPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3829:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24image_convolution_kernelPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8
.align 8
.LC1:
.string "matrix_conv_gpu_500_points_Quadro.csv"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "iter: "
.LC7:
.string ","
.LC8:
.string ",\n"
.text
.globl main
.type main, @function
main:
.LFB3801:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3801
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $600, %rsp
.cfi_def_cfa_offset 656
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $16, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movl $0, 28(%rsp)
jmp .L42
.L59:
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L54
cmpb $0, 56(%rbp)
je .L32
movzbl 67(%rbp), %esi
.L33:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L55
.L54:
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L56
call _ZSt16__throw_bad_castv@PLT
.L46:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L44
call __stack_chk_fail@PLT
.L56:
call __stack_chk_fail@PLT
.L32:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L33
.L55:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L29:
call rand@PLT
cltd
shrl $22, %edx
leal (%rax,%rdx), %r12d
andl $1023, %r12d
subl %edx, %r12d
addl $10, %r12d
call rand@PLT
cltd
shrl $22, %edx
leal (%rax,%rdx), %ebp
andl $1023, %ebp
subl %edx, %ebp
addl $10, %ebp
movl %r12d, %r14d
imull %ebp, %r14d
call rand@PLT
movslq %eax, %rdx
imulq $1431655766, %rdx, %rdx
shrq $32, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,2), %edx
subl %edx, %eax
leal 3(%rax,%rax), %r15d
movslq %r14d, %rax
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L34
leaq 0(,%rax,4), %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movq %r13, %rdi
call _Znam@PLT
jmp .L57
.L34:
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L36
call __stack_chk_fail@PLT
.L36:
call __cxa_throw_bad_array_new_length@PLT
.L57:
movq %rax, 40(%rsp)
call rand@PLT
movl %eax, %ebx
pxor %xmm3, %xmm3
cvtsi2sdl %r14d, %xmm3
movsd %xmm3, 16(%rsp)
movapd %xmm3, %xmm0
call log2@PLT
addsd .LC3(%rip), %xmm0
cvttsd2sil %xmm0, %ecx
movl %ebx, %eax
cltd
idivl %ecx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
movsd .LC4(%rip), %xmm0
call pow@PLT
movsd .LC3(%rip), %xmm2
divsd %xmm0, %xmm2
movsd %xmm2, 32(%rsp)
movsd .LC5(%rip), %xmm4
comisd %xmm2, %xmm4
jnb .L37
movq 8(%rsp), %rax
movq %rax, %rbx
addq %rax, %r13
testl %r14d, %r14d
jle .L39
.L41:
call rand@PLT
cltd
shrl $22, %edx
addl %edx, %eax
andl $1023, %eax
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbx, %r13
jne .L41
jmp .L39
.L37:
movsd 16(%rsp), %xmm0
mulsd 32(%rsp), %xmm0
cvttsd2sil %xmm0, %eax
movl %eax, 16(%rsp)
testl %eax, %eax
jle .L39
movl $0, %r13d
.L40:
call rand@PLT
cltd
idivl %r12d
movl %edx, %ebx
call rand@PLT
cltd
idivl %ebp
movl %edx, %r14d
call rand@PLT
imull %ebp, %ebx
addl %r14d, %ebx
movslq %ebx, %rbx
cltd
shrl $22, %edx
addl %edx, %eax
andl $1023, %eax
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%rbx,4)
addl $1, %r13d
cmpl %r13d, 16(%rsp)
jne .L40
.L39:
leaq 60(%rsp), %r9
movl %r15d, %r8d
movl %r12d, %ecx
movl %ebp, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z2MCPfS_iiiRf
movl %r12d, %ebx
subl %r15d, %ebx
addl $1, %ebx
movl %ebp, %eax
subl %r15d, %eax
addl $1, %eax
imull %eax, %ebx
imull %r15d, %ebx
imull %r15d, %ebx
movss 60(%rsp), %xmm0
divss .LC6(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq 64(%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
leaq 64(%rsp), %rdi
movl $1, %edx
leaq .LC7(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 64(%rsp), %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r15d, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 32(%rsp), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC8(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, 28(%rsp)
movl 28(%rsp), %eax
cmpl $500, %eax
je .L58
.L42:
movl 28(%rsp), %ebx
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %eax, %ebx
jne .L29
movl $6, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L59
.L58:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.LEHE1:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3801:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3801-.LLSDACSB3801
.LLSDACSB3801:
.uleb128 .LEHB0-.LFB3801
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3801
.uleb128 .LEHE1-.LEHB1
.uleb128 .L46-.LFB3801
.uleb128 0
.uleb128 .LEHB2-.LFB3801
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3801:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long 0
.long 1073741824
.align 8
.LC5:
.long 0
.long 1071644672
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1148846080
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MC_G_global.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z39__device_stub__image_convolution_kernelPfS_S_iiii # -- Begin function _Z39__device_stub__image_convolution_kernelPfS_S_iiii
.p2align 4, 0x90
.type _Z39__device_stub__image_convolution_kernelPfS_S_iiii,@function
_Z39__device_stub__image_convolution_kernelPfS_S_iiii: # @_Z39__device_stub__image_convolution_kernelPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24image_convolution_kernelPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__image_convolution_kernelPfS_S_iiii, .Lfunc_end0-_Z39__device_stub__image_convolution_kernelPfS_S_iiii
.cfi_endproc
# -- End function
.globl _Z2MCPfS_iiiRf # -- Begin function _Z2MCPfS_iiiRf
.p2align 4, 0x90
.type _Z2MCPfS_iiiRf,@function
_Z2MCPfS_iiiRf: # @_Z2MCPfS_iiiRf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 96(%rsp) # 8-byte Spill
movl %r8d, %ebp
# kill: def $ecx killed $ecx def $rcx
movq %rcx, 80(%rsp) # 8-byte Spill
# kill: def $edx killed $edx def $rdx
movq %rdx, 72(%rsp) # 8-byte Spill
movq %rsi, 88(%rsp) # 8-byte Spill
movq %rdi, 64(%rsp) # 8-byte Spill
movl %r8d, %r13d
imull %r13d, %r13d
leaq (,%r13,4), %rbx
movq %rbx, %rdi
callq _Znam
movq %rax, %r14
testl %ebp, %ebp
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
cmpl $1, %r13d
movl %r13d, %r15d
adcl $0, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq %rbx, %rdi
callq _Znam
movq %rax, %r15
testl %ebp, %ebp
je .LBB1_5
# %bb.4: # %.lr.ph61.preheader
cmpl $1, %r13d
adcl $0, %r13d
shlq $2, %r13
movq %r15, %rdi
movq %r14, %rsi
movq %r13, %rdx
callq memcpy@PLT
.LBB1_5: # %._crit_edge62
movq 80(%rsp), %r14 # 8-byte Reload
movl %r14d, %eax
movq 72(%rsp), %r12 # 8-byte Reload
imull %r12d, %eax
movslq %eax, %r13
shlq $2, %r13
leaq 56(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 56(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r14), %eax
shrl $4, %eax
leal 15(%r12), %ebx
shrl $4, %ebx
shlq $32, %rbx
orq %rax, %rbx
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %r14d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %ebp, 20(%rsp)
movl %ebp, 16(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 20(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z24image_convolution_kernelPfS_S_iiii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 48(%rsp), %rsi
movq 88(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
movq 96(%rsp), %rdi # 8-byte Reload
callq hipEventElapsedTime
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z2MCPfS_iiiRf, .Lfunc_end1-_Z2MCPfS_iiiRf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3ff0000000000000 # double 1
.LCPI2_1:
.quad 0x3fe0000000000000 # double 0.5
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_2:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $584, %rsp # imm = 0x248
.cfi_def_cfa_offset 640
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 72(%rsp), %rbx
movq %rbx, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
leaq 80(%rsp), %rdi
.Ltmp0:
movl $.L.str, %esi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 72(%rsp), %rcx
addq -24(%rcx), %rbx
xorl %esi, %esi
testq %rax, %rax
jne .LBB2_3
# %bb.2:
movl 32(%rbx), %esi
orl $4, %esi
.LBB2_3: # %.invoke
.Ltmp2:
movq %rbx, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_5: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
# =>This Loop Header: Depth=1
# Child Loop BB2_32 Depth 2
# Child Loop BB2_27 Depth 2
imull $-858993459, %ebp, %eax # imm = 0xCCCCCCCD
rorl %eax
cmpl $429496729, %eax # imm = 0x19999999
ja .LBB2_22
# %bb.6: # in Loop: Header=BB2_5 Depth=1
.Ltmp5:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp6:
# %bb.7: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB2_5 Depth=1
.Ltmp7:
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
.Ltmp8:
# %bb.8: # in Loop: Header=BB2_5 Depth=1
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_9
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_5 Depth=1
cmpb $0, 56(%r14)
je .LBB2_18
# %bb.17: # in Loop: Header=BB2_5 Depth=1
movzbl 67(%r14), %eax
jmp .LBB2_20
.LBB2_18: # in Loop: Header=BB2_5 Depth=1
.Ltmp9:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp10:
# %bb.19: # %.noexc85
# in Loop: Header=BB2_5 Depth=1
movq (%r14), %rax
.Ltmp11:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp12:
.LBB2_20: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB2_5 Depth=1
.Ltmp13:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp14:
# %bb.21: # %.noexc87
# in Loop: Header=BB2_5 Depth=1
.Ltmp15:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp16:
.LBB2_22: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB2_5 Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
movl %ecx, 12(%rsp) # 4-byte Spill
# kill: def $ecx killed $ecx def $rcx
negl %ecx
movq %rax, 48(%rsp) # 8-byte Spill
leal (%rax,%rcx), %r15d
addl $10, %r15d
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
movl %ecx, 8(%rsp) # 4-byte Spill
# kill: def $ecx killed $ecx def $rcx
negl %ecx
movq %rax, 40(%rsp) # 8-byte Spill
leal (%rax,%rcx), %ebx
addl $10, %ebx
movl %ebx, %r13d
imull %r15d, %r13d
callq rand
movl %eax, 16(%rsp) # 4-byte Spill
movslq %r13d, %rax
leaq (,%rax,4), %r14
testl %eax, %eax
movq $-1, %rax
cmovsq %rax, %r14
.Ltmp18:
movq %r14, %rdi
callq _Znam
.Ltmp19:
# %bb.23: # in Loop: Header=BB2_5 Depth=1
.Ltmp20:
movq %rax, %r12
movq %r14, %rdi
callq _Znam
movq %rax, 64(%rsp) # 8-byte Spill
.Ltmp21:
# %bb.24: # in Loop: Header=BB2_5 Depth=1
movq %rbp, 56(%rsp) # 8-byte Spill
callq rand
movl %eax, %r14d
cvtsi2sd %r13d, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq log2
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
cvttsd2si %xmm0, %ecx
movl %r14d, %eax
cltd
idivl %ecx
movl %edx, %edi
movapd %xmm1, %xmm0
callq ldexp@PLT
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm1, %xmm0
movsd %xmm1, 32(%rsp) # 8-byte Spill
jae .LBB2_31
# %bb.25: # %.preheader
# in Loop: Header=BB2_5 Depth=1
testl %r13d, %r13d
jle .LBB2_33
# %bb.26: # %.lr.ph93.preheader
# in Loop: Header=BB2_5 Depth=1
movl %r13d, %r14d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_27: # %.lr.ph93
# Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq %r13, %r14
jne .LBB2_27
jmp .LBB2_33
.p2align 4, 0x90
.LBB2_31: # in Loop: Header=BB2_5 Depth=1
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd %xmm1, %xmm0
cvttsd2si %xmm0, %ebp
testl %ebp, %ebp
jle .LBB2_33
.p2align 4, 0x90
.LBB2_32: # %.lr.ph
# Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltd
idivl %r15d
movl %edx, %r14d
callq rand
cltd
idivl %ebx
movl %edx, %r13d
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
imull %ebx, %r14d
addl %r13d, %r14d
movslq %r14d, %rax
movss %xmm0, (%r12,%rax,4)
decl %ebp
jne .LBB2_32
.LBB2_33: # %.loopexit
# in Loop: Header=BB2_5 Depth=1
.Ltmp23:
movslq 16(%rsp), %r13 # 4-byte Folded Reload
imulq $1431655766, %r13, %rax # imm = 0x55555556
movq %rax, %rcx
shrq $63, %rcx
shrq $32, %rax
addl %ecx, %eax
leal (%rax,%rax,2), %eax
subl %eax, %r13d
leal 3(,%r13,2), %r14d
movq %r12, %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movl %ebx, %edx
movl %r15d, %ecx
movl %r14d, %r8d
leaq 20(%rsp), %r9
callq _Z2MCPfS_iiiRf
.Ltmp24:
# %bb.34: # in Loop: Header=BB2_5 Depth=1
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
.Ltmp26:
leaq 72(%rsp), %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp27:
movq 56(%rsp), %rbp # 8-byte Reload
# %bb.35: # %_ZNSolsEf.exit
# in Loop: Header=BB2_5 Depth=1
.Ltmp28:
movl $.L.str.2, %esi
movl $1, %edx
leaq 72(%rsp), %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp29:
# %bb.36: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit72
# in Loop: Header=BB2_5 Depth=1
.Ltmp30:
leaq 72(%rsp), %rdi
movl %r15d, %esi
callq _ZNSolsEi
.Ltmp31:
# %bb.37: # in Loop: Header=BB2_5 Depth=1
.Ltmp32:
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp33:
# %bb.38: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit74
# in Loop: Header=BB2_5 Depth=1
.Ltmp34:
movq %r15, %rdi
movl %ebx, %esi
callq _ZNSolsEi
.Ltmp35:
# %bb.39: # in Loop: Header=BB2_5 Depth=1
.Ltmp36:
movq %rax, %rbx
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp37:
# %bb.40: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit76
# in Loop: Header=BB2_5 Depth=1
.Ltmp38:
movq %rbx, %rdi
movl %r14d, %esi
callq _ZNSolsEi
.Ltmp39:
# %bb.41: # in Loop: Header=BB2_5 Depth=1
.Ltmp40:
movq %rax, %rbx
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp41:
# %bb.42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit78
# in Loop: Header=BB2_5 Depth=1
.Ltmp42:
movq %rbx, %rdi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp43:
# %bb.43: # %_ZNSolsEd.exit
# in Loop: Header=BB2_5 Depth=1
.Ltmp44:
movq %rax, %rbx
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp45:
# %bb.44: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit81
# in Loop: Header=BB2_5 Depth=1
.Ltmp46:
movq 48(%rsp), %rax # 8-byte Reload
subl 12(%rsp), %eax # 4-byte Folded Reload
movq 40(%rsp), %rcx # 8-byte Reload
subl 8(%rsp), %ecx # 4-byte Folded Reload
addl %r13d, %r13d
subl %r13d, %eax
addl $8, %eax
subl %r13d, %ecx
addl $8, %ecx
imull %eax, %ecx
imull %r14d, %r14d
imull %ecx, %r14d
movq %rbx, %rdi
movl %r14d, %esi
callq _ZNSolsEi
.Ltmp47:
# %bb.45: # in Loop: Header=BB2_5 Depth=1
.Ltmp48:
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp49:
# %bb.46: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit83
# in Loop: Header=BB2_5 Depth=1
incl %ebp
cmpl $500, %ebp # imm = 0x1F4
jne .LBB2_5
# %bb.10:
.Ltmp51:
leaq 80(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp52:
# %bb.11: # %.noexc66
testq %rax, %rax
jne .LBB2_13
# %bb.12:
movq 72(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $72, %rdi
movl 104(%rsp,%rax), %esi
orl $4, %esi
.Ltmp53:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp54:
.LBB2_13: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
leaq 72(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $584, %rsp # imm = 0x248
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_9:
.cfi_def_cfa_offset 640
.Ltmp56:
callq _ZSt16__throw_bad_castv
.Ltmp57:
# %bb.15: # %.noexc84
.LBB2_49:
.Ltmp55:
jmp .LBB2_50
.LBB2_14:
.Ltmp4:
jmp .LBB2_50
.LBB2_29: # %.loopexit.split-lp
.Ltmp58:
jmp .LBB2_50
.LBB2_47:
.Ltmp25:
jmp .LBB2_50
.LBB2_28: # %.loopexit90
.Ltmp17:
jmp .LBB2_50
.LBB2_30:
.Ltmp22:
jmp .LBB2_50
.LBB2_48:
.Ltmp50:
.LBB2_50:
movq %rax, %rbx
leaq 72(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp16-.Ltmp5 # Call between .Ltmp5 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp21-.Ltmp18 # Call between .Ltmp18 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp23-.Ltmp21 # Call between .Ltmp21 and .Ltmp23
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp49-.Ltmp26 # Call between .Ltmp26 and .Ltmp49
.uleb128 .Ltmp50-.Lfunc_begin0 # jumps to .Ltmp50
.byte 0 # On action: cleanup
.uleb128 .Ltmp51-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp54-.Ltmp51 # Call between .Ltmp51 and .Ltmp54
.uleb128 .Ltmp55-.Lfunc_begin0 # jumps to .Ltmp55
.byte 0 # On action: cleanup
.uleb128 .Ltmp56-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp57-.Ltmp56 # Call between .Ltmp56 and .Ltmp57
.uleb128 .Ltmp58-.Lfunc_begin0 # jumps to .Ltmp58
.byte 0 # On action: cleanup
.uleb128 .Ltmp57-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end2-.Ltmp57 # Call between .Ltmp57 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24image_convolution_kernelPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24image_convolution_kernelPfS_S_iiii,@object # @_Z24image_convolution_kernelPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z24image_convolution_kernelPfS_S_iiii
.p2align 3, 0x0
_Z24image_convolution_kernelPfS_S_iiii:
.quad _Z39__device_stub__image_convolution_kernelPfS_S_iiii
.size _Z24image_convolution_kernelPfS_S_iiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "matrix_conv_gpu_500_points_Quadro.csv"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "iter: "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ","
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ",\n"
.size .L.str.3, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24image_convolution_kernelPfS_S_iiii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__image_convolution_kernelPfS_S_iiii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z24image_convolution_kernelPfS_S_iiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void sumaDatos(int* in, int* out, int size)
{
int IDx=blockIdx.x*blockDim.x+threadIdx.x;
if(IDx>size) return;
out[IDx]=in[IDx]+in[IDx];
}
int main(int argc, char **argv)
{
int datosCount=100000000;
int* h_datos=(int*)malloc(datosCount*sizeof(int));
int* h_datosout=(int*)malloc(datosCount*sizeof(int));
int* d_datos;
int* d_datosout;
cudaMalloc(&d_datos,datosCount*sizeof(int));
cudaMalloc(&d_datosout,datosCount*sizeof(int));
for(int i=0;i<datosCount;i++)
{
h_datos[i]=i*2;
}
cudaMemcpy(d_datos,h_datos,datosCount*sizeof(int),cudaMemcpyHostToDevice);
int numthreads=256;
int numbloques=datosCount/numthreads+1;
sumaDatos<<<numbloques,numthreads>>>(d_datos,d_datosout,datosCount);
cudaMemcpy(h_datosout,d_datosout,datosCount*sizeof(int),cudaMemcpyDeviceToHost);
printf("FIN\n");
return 0;
} | code for sm_80
Function : _Z9sumaDatosPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ SHF.L.U32 R7, R2, 0x1, RZ ; /* 0x0000000102077819 */
/* 0x004fca00000006ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void sumaDatos(int* in, int* out, int size)
{
int IDx=blockIdx.x*blockDim.x+threadIdx.x;
if(IDx>size) return;
out[IDx]=in[IDx]+in[IDx];
}
int main(int argc, char **argv)
{
int datosCount=100000000;
int* h_datos=(int*)malloc(datosCount*sizeof(int));
int* h_datosout=(int*)malloc(datosCount*sizeof(int));
int* d_datos;
int* d_datosout;
cudaMalloc(&d_datos,datosCount*sizeof(int));
cudaMalloc(&d_datosout,datosCount*sizeof(int));
for(int i=0;i<datosCount;i++)
{
h_datos[i]=i*2;
}
cudaMemcpy(d_datos,h_datos,datosCount*sizeof(int),cudaMemcpyHostToDevice);
int numthreads=256;
int numbloques=datosCount/numthreads+1;
sumaDatos<<<numbloques,numthreads>>>(d_datos,d_datosout,datosCount);
cudaMemcpy(h_datosout,d_datosout,datosCount*sizeof(int),cudaMemcpyDeviceToHost);
printf("FIN\n");
return 0;
} | .file "tmpxft_00058793_00000000-6_fuente.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9sumaDatosPiS_iPiS_i
.type _Z31__device_stub__Z9sumaDatosPiS_iPiS_i, @function
_Z31__device_stub__Z9sumaDatosPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9sumaDatosPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z9sumaDatosPiS_iPiS_i, .-_Z31__device_stub__Z9sumaDatosPiS_iPiS_i
.globl _Z9sumaDatosPiS_i
.type _Z9sumaDatosPiS_i, @function
_Z9sumaDatosPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9sumaDatosPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9sumaDatosPiS_i, .-_Z9sumaDatosPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "FIN\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
leal (%rax,%rax), %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq $100000000, %rax
jne .L12
movl $1, %ecx
movl $400000000, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $390626, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $400000000, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $100000000, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z9sumaDatosPiS_iPiS_i
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9sumaDatosPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sumaDatosPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void sumaDatos(int* in, int* out, int size)
{
int IDx=blockIdx.x*blockDim.x+threadIdx.x;
if(IDx>size) return;
out[IDx]=in[IDx]+in[IDx];
}
int main(int argc, char **argv)
{
int datosCount=100000000;
int* h_datos=(int*)malloc(datosCount*sizeof(int));
int* h_datosout=(int*)malloc(datosCount*sizeof(int));
int* d_datos;
int* d_datosout;
cudaMalloc(&d_datos,datosCount*sizeof(int));
cudaMalloc(&d_datosout,datosCount*sizeof(int));
for(int i=0;i<datosCount;i++)
{
h_datos[i]=i*2;
}
cudaMemcpy(d_datos,h_datos,datosCount*sizeof(int),cudaMemcpyHostToDevice);
int numthreads=256;
int numbloques=datosCount/numthreads+1;
sumaDatos<<<numbloques,numthreads>>>(d_datos,d_datosout,datosCount);
cudaMemcpy(h_datosout,d_datosout,datosCount*sizeof(int),cudaMemcpyDeviceToHost);
printf("FIN\n");
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void sumaDatos(int* in, int* out, int size)
{
int IDx=blockIdx.x*blockDim.x+threadIdx.x;
if(IDx>size) return;
out[IDx]=in[IDx]+in[IDx];
}
int main(int argc, char **argv)
{
int datosCount=100000000;
int* h_datos=(int*)malloc(datosCount*sizeof(int));
int* h_datosout=(int*)malloc(datosCount*sizeof(int));
int* d_datos;
int* d_datosout;
hipMalloc(&d_datos,datosCount*sizeof(int));
hipMalloc(&d_datosout,datosCount*sizeof(int));
for(int i=0;i<datosCount;i++)
{
h_datos[i]=i*2;
}
hipMemcpy(d_datos,h_datos,datosCount*sizeof(int),hipMemcpyHostToDevice);
int numthreads=256;
int numbloques=datosCount/numthreads+1;
sumaDatos<<<numbloques,numthreads>>>(d_datos,d_datosout,datosCount);
hipMemcpy(h_datosout,d_datosout,datosCount*sizeof(int),hipMemcpyDeviceToHost);
printf("FIN\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void sumaDatos(int* in, int* out, int size)
{
int IDx=blockIdx.x*blockDim.x+threadIdx.x;
if(IDx>size) return;
out[IDx]=in[IDx]+in[IDx];
}
int main(int argc, char **argv)
{
int datosCount=100000000;
int* h_datos=(int*)malloc(datosCount*sizeof(int));
int* h_datosout=(int*)malloc(datosCount*sizeof(int));
int* d_datos;
int* d_datosout;
hipMalloc(&d_datos,datosCount*sizeof(int));
hipMalloc(&d_datosout,datosCount*sizeof(int));
for(int i=0;i<datosCount;i++)
{
h_datos[i]=i*2;
}
hipMemcpy(d_datos,h_datos,datosCount*sizeof(int),hipMemcpyHostToDevice);
int numthreads=256;
int numbloques=datosCount/numthreads+1;
sumaDatos<<<numbloques,numthreads>>>(d_datos,d_datosout,datosCount);
hipMemcpy(h_datosout,d_datosout,datosCount*sizeof(int),hipMemcpyDeviceToHost);
printf("FIN\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9sumaDatosPiS_i
.globl _Z9sumaDatosPiS_i
.p2align 8
.type _Z9sumaDatosPiS_i,@function
_Z9sumaDatosPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9sumaDatosPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9sumaDatosPiS_i, .Lfunc_end0-_Z9sumaDatosPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9sumaDatosPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9sumaDatosPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void sumaDatos(int* in, int* out, int size)
{
int IDx=blockIdx.x*blockDim.x+threadIdx.x;
if(IDx>size) return;
out[IDx]=in[IDx]+in[IDx];
}
int main(int argc, char **argv)
{
int datosCount=100000000;
int* h_datos=(int*)malloc(datosCount*sizeof(int));
int* h_datosout=(int*)malloc(datosCount*sizeof(int));
int* d_datos;
int* d_datosout;
hipMalloc(&d_datos,datosCount*sizeof(int));
hipMalloc(&d_datosout,datosCount*sizeof(int));
for(int i=0;i<datosCount;i++)
{
h_datos[i]=i*2;
}
hipMemcpy(d_datos,h_datos,datosCount*sizeof(int),hipMemcpyHostToDevice);
int numthreads=256;
int numbloques=datosCount/numthreads+1;
sumaDatos<<<numbloques,numthreads>>>(d_datos,d_datosout,datosCount);
hipMemcpy(h_datosout,d_datosout,datosCount*sizeof(int),hipMemcpyDeviceToHost);
printf("FIN\n");
return 0;
} | .text
.file "fuente.hip"
.globl _Z24__device_stub__sumaDatosPiS_i # -- Begin function _Z24__device_stub__sumaDatosPiS_i
.p2align 4, 0x90
.type _Z24__device_stub__sumaDatosPiS_i,@function
_Z24__device_stub__sumaDatosPiS_i: # @_Z24__device_stub__sumaDatosPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9sumaDatosPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__sumaDatosPiS_i, .Lfunc_end0-_Z24__device_stub__sumaDatosPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r14
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,2)
addq $2, %rax
cmpq $200000000, %rax # imm = 0xBEBC200
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 390370(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $100000000, 12(%rsp) # imm = 0x5F5E100
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9sumaDatosPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sumaDatosPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9sumaDatosPiS_i,@object # @_Z9sumaDatosPiS_i
.section .rodata,"a",@progbits
.globl _Z9sumaDatosPiS_i
.p2align 3, 0x0
_Z9sumaDatosPiS_i:
.quad _Z24__device_stub__sumaDatosPiS_i
.size _Z9sumaDatosPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9sumaDatosPiS_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "FIN"
.size .Lstr, 4
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sumaDatosPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9sumaDatosPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9sumaDatosPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ SHF.L.U32 R7, R2, 0x1, RZ ; /* 0x0000000102077819 */
/* 0x004fca00000006ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9sumaDatosPiS_i
.globl _Z9sumaDatosPiS_i
.p2align 8
.type _Z9sumaDatosPiS_i,@function
_Z9sumaDatosPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9sumaDatosPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9sumaDatosPiS_i, .Lfunc_end0-_Z9sumaDatosPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9sumaDatosPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9sumaDatosPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00058793_00000000-6_fuente.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9sumaDatosPiS_iPiS_i
.type _Z31__device_stub__Z9sumaDatosPiS_iPiS_i, @function
_Z31__device_stub__Z9sumaDatosPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9sumaDatosPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z9sumaDatosPiS_iPiS_i, .-_Z31__device_stub__Z9sumaDatosPiS_iPiS_i
.globl _Z9sumaDatosPiS_i
.type _Z9sumaDatosPiS_i, @function
_Z9sumaDatosPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9sumaDatosPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9sumaDatosPiS_i, .-_Z9sumaDatosPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "FIN\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
leal (%rax,%rax), %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq $100000000, %rax
jne .L12
movl $1, %ecx
movl $400000000, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $390626, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $400000000, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $100000000, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z9sumaDatosPiS_iPiS_i
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9sumaDatosPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sumaDatosPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fuente.hip"
.globl _Z24__device_stub__sumaDatosPiS_i # -- Begin function _Z24__device_stub__sumaDatosPiS_i
.p2align 4, 0x90
.type _Z24__device_stub__sumaDatosPiS_i,@function
_Z24__device_stub__sumaDatosPiS_i: # @_Z24__device_stub__sumaDatosPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9sumaDatosPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__sumaDatosPiS_i, .Lfunc_end0-_Z24__device_stub__sumaDatosPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r14
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,2)
addq $2, %rax
cmpq $200000000, %rax # imm = 0xBEBC200
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 390370(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $100000000, 12(%rsp) # imm = 0x5F5E100
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9sumaDatosPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sumaDatosPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9sumaDatosPiS_i,@object # @_Z9sumaDatosPiS_i
.section .rodata,"a",@progbits
.globl _Z9sumaDatosPiS_i
.p2align 3, 0x0
_Z9sumaDatosPiS_i:
.quad _Z24__device_stub__sumaDatosPiS_i
.size _Z9sumaDatosPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9sumaDatosPiS_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "FIN"
.size .Lstr, 4
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sumaDatosPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9sumaDatosPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* This is a CUDA code that performs an iterative reverse edge
* detection algorithm.
*
* Training material developed by James Perry and Alan Gray
* Copyright EPCC, The University of Edinburgh, 2013
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//#include <sys/types.h>
//#include <sys/time.h>
#include<chrono>
#include <cuda_runtime_api.h>
#include <cuda.h>
#include "device_launch_parameters.h"
/* Utility Functions */
using std::chrono::time_point;
using std::chrono::system_clock;
/*
* Function to get an accurate time reading
*/
time_point<system_clock> get_current_time()
{
/*
static int start = 0, startu = 0;
struct timeval tval;
double result;
if (gettimeofday(&tval, NULL) == -1)
result = -1.0;
else if(!start) {
start = tval.tv_sec;
startu = tval.tv_usec;
result = 0.0;
}
else
result = (double) (tval.tv_sec - start) + 1.0e-6*(tval.tv_usec - startu);
return result;
*/
return std::chrono::system_clock::now();
}
/* Read the input file containing the edge data */
void datread(char *filename, void *vx, int nx, int ny)
{
FILE *fp;
int nxt, nyt, i, j, t;
float *x = (float *) vx;
if (NULL == (fp = fopen(filename,"r")))
{
fprintf(stderr, "datread: cannot open <%s>\n", filename);
exit(-1);
}
fscanf(fp,"%d %d",&nxt,&nyt);
if (nx != nxt || ny != nyt)
{
fprintf(stderr,
"datread: size mismatch, (nx,ny) = (%d,%d) expected (%d,%d)\n",
nxt, nyt, nx, ny);
exit(-1);
}
for (j=0; j<ny; j++)
{
for (i=0; i<nx; i++)
{
fscanf(fp,"%d", &t);
x[(ny-j-1)*nx + i] = (float)t;
}
}
fclose(fp);
}
/* Write the output image as a PGM file */
void pgmwrite(char *filename, void *vx, int nx, int ny)
{
FILE *fp;
int i, j, k, grey;
float xmin, xmax, tmp;
float thresh = 255.0;
float *x = (float *) vx;
if (NULL == (fp = fopen(filename,"w")))
{
fprintf(stderr, "pgmwrite: cannot create <%s>\n", filename);
exit(-1);
}
/*
* Find the max and min absolute values of the array
*/
xmin = fabs(x[0]);
xmax = fabs(x[0]);
for (i=0; i < nx*ny; i++)
{
if (fabs(x[i]) < xmin) xmin = fabs(x[i]);
if (fabs(x[i]) > xmax) xmax = fabs(x[i]);
}
fprintf(fp, "P2\n");
fprintf(fp, "# Written by pgmwrite\n");
fprintf(fp, "%d %d\n", nx, ny);
fprintf(fp, "%d\n", (int) thresh);
k = 0;
for (j=ny-1; j >=0 ; j--)
{
for (i=0; i < nx; i++)
{
/*
* Access the value of x[i][j]
*/
tmp = x[j*nx+i];
/*
* Scale the value appropriately so it lies between 0 and thresh
*/
if (xmin < 0 || xmax > thresh)
{
tmp = (int) ((thresh*((fabs(tmp-xmin))/(xmax-xmin))) + 0.5);
}
else
{
tmp = (int) (fabs(tmp) + 0.5);
}
/*
* Increase the contrast by boosting the lower values
*/
grey = (int) (thresh * sqrt(tmp/thresh));
fprintf(fp, "%3d ", grey);
if (0 == (k+1)%16) fprintf(fp, "\n");
k++;
}
}
if (0 != k%16) fprintf(fp, "\n");
fclose(fp);
}
/* Simple utility function to check for CUDA runtime errors */
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* This is a CUDA code that performs an iterative reverse edge
* detection algorithm.
*
* Training material developed by James Perry and Alan Gray
* Copyright EPCC, The University of Edinburgh, 2013
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//#include <sys/types.h>
//#include <sys/time.h>
#include<chrono>
#include <cuda_runtime_api.h>
#include <cuda.h>
#include "device_launch_parameters.h"
/* Utility Functions */
using std::chrono::time_point;
using std::chrono::system_clock;
/*
* Function to get an accurate time reading
*/
time_point<system_clock> get_current_time()
{
/*
static int start = 0, startu = 0;
struct timeval tval;
double result;
if (gettimeofday(&tval, NULL) == -1)
result = -1.0;
else if(!start) {
start = tval.tv_sec;
startu = tval.tv_usec;
result = 0.0;
}
else
result = (double) (tval.tv_sec - start) + 1.0e-6*(tval.tv_usec - startu);
return result;
*/
return std::chrono::system_clock::now();
}
/* Read the input file containing the edge data */
void datread(char *filename, void *vx, int nx, int ny)
{
FILE *fp;
int nxt, nyt, i, j, t;
float *x = (float *) vx;
if (NULL == (fp = fopen(filename,"r")))
{
fprintf(stderr, "datread: cannot open <%s>\n", filename);
exit(-1);
}
fscanf(fp,"%d %d",&nxt,&nyt);
if (nx != nxt || ny != nyt)
{
fprintf(stderr,
"datread: size mismatch, (nx,ny) = (%d,%d) expected (%d,%d)\n",
nxt, nyt, nx, ny);
exit(-1);
}
for (j=0; j<ny; j++)
{
for (i=0; i<nx; i++)
{
fscanf(fp,"%d", &t);
x[(ny-j-1)*nx + i] = (float)t;
}
}
fclose(fp);
}
/* Write the output image as a PGM file */
void pgmwrite(char *filename, void *vx, int nx, int ny)
{
FILE *fp;
int i, j, k, grey;
float xmin, xmax, tmp;
float thresh = 255.0;
float *x = (float *) vx;
if (NULL == (fp = fopen(filename,"w")))
{
fprintf(stderr, "pgmwrite: cannot create <%s>\n", filename);
exit(-1);
}
/*
* Find the max and min absolute values of the array
*/
xmin = fabs(x[0]);
xmax = fabs(x[0]);
for (i=0; i < nx*ny; i++)
{
if (fabs(x[i]) < xmin) xmin = fabs(x[i]);
if (fabs(x[i]) > xmax) xmax = fabs(x[i]);
}
fprintf(fp, "P2\n");
fprintf(fp, "# Written by pgmwrite\n");
fprintf(fp, "%d %d\n", nx, ny);
fprintf(fp, "%d\n", (int) thresh);
k = 0;
for (j=ny-1; j >=0 ; j--)
{
for (i=0; i < nx; i++)
{
/*
* Access the value of x[i][j]
*/
tmp = x[j*nx+i];
/*
* Scale the value appropriately so it lies between 0 and thresh
*/
if (xmin < 0 || xmax > thresh)
{
tmp = (int) ((thresh*((fabs(tmp-xmin))/(xmax-xmin))) + 0.5);
}
else
{
tmp = (int) (fabs(tmp) + 0.5);
}
/*
* Increase the contrast by boosting the lower values
*/
grey = (int) (thresh * sqrt(tmp/thresh));
fprintf(fp, "%3d ", grey);
if (0 == (k+1)%16) fprintf(fp, "\n");
k++;
}
}
if (0 != k%16) fprintf(fp, "\n");
fclose(fp);
}
/* Simple utility function to check for CUDA runtime errors */
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .file "tmpxft_001bdc9d_00000000-6_utilities.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2162:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2162:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16get_current_timev
.type _Z16get_current_timev, @function
_Z16get_current_timev:
.LFB2156:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2156:
.size _Z16get_current_timev, .-_Z16get_current_timev
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "datread: cannot open <%s>\n"
.LC2:
.string "%d %d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "datread: size mismatch, (nx,ny) = (%d,%d) expected (%d,%d)\n"
.section .rodata.str1.1
.LC4:
.string "%d"
.text
.globl _Z7datreadPcPvii
.type _Z7datreadPcPvii, @function
_Z7datreadPcPvii:
.LFB2157:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movl %edx, %r14d
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L16
movq %rax, %r12
leaq 32(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 28(%rsp), %ecx
cmpl %r14d, %ecx
jne .L7
movl 4(%rsp), %eax
cmpl %eax, 32(%rsp)
jne .L7
testl %eax, %eax
jle .L8
subl $1, %eax
imull %r14d, %eax
movl %eax, (%rsp)
movl $0, %r15d
leaq .LC4(%rip), %r13
jmp .L9
.L16:
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L7:
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 120
movl 12(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
movl %r14d, %r9d
movl 48(%rsp), %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L11:
.cfi_restore_state
movslq (%rsp), %rdx
movq 8(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
movslq %r14d, %rax
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L10:
leaq 36(%rsp), %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 36(%rsp), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L10
.L12:
addl $1, %r15d
subl %r14d, (%rsp)
cmpl %r15d, 4(%rsp)
je .L8
.L9:
testl %r14d, %r14d
jg .L11
jmp .L12
.L8:
movq %r12, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2157:
.size _Z7datreadPcPvii, .-_Z7datreadPcPvii
.section .rodata.str1.1
.LC5:
.string "w"
.LC6:
.string "pgmwrite: cannot create <%s>\n"
.LC8:
.string "P2\n"
.LC9:
.string "# Written by pgmwrite\n"
.LC10:
.string "%d %d\n"
.LC11:
.string "%d\n"
.LC15:
.string "%3d "
.LC16:
.string "\n"
.text
.globl _Z8pgmwritePcPvii
.type _Z8pgmwritePcPvii, @function
_Z8pgmwritePcPvii:
.LFB2158:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, 24(%rsp)
movl %edx, %r15d
movl %ecx, %r14d
leaq .LC5(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L47
movq %rax, %r12
movq 24(%rsp), %rsi
movq %rsi, %rax
movss (%rsi), %xmm0
movaps %xmm0, %xmm7
andps .LC7(%rip), %xmm7
movss %xmm7, 12(%rsp)
movl %r15d, %edx
imull %r14d, %edx
testl %edx, %edx
jle .L38
movslq %edx, %rdx
leaq (%rsi,%rdx,4), %rdx
movss %xmm7, 16(%rsp)
movss .LC7(%rip), %xmm1
.L23:
movss (%rax), %xmm0
andps %xmm1, %xmm0
movaps %xmm0, %xmm7
minss 12(%rsp), %xmm7
movss %xmm7, 12(%rsp)
maxss 16(%rsp), %xmm0
movss %xmm0, 16(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L23
.L20:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC9(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %r8d
movl %r15d, %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $255, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
subl $1, %r14d
js .L24
movl %r14d, %eax
imull %r15d, %eax
movl %eax, 20(%rsp)
movl $0, %ebx
jmp .L25
.L47:
movq %rbx, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L38:
movss 12(%rsp), %xmm7
movss %xmm7, 16(%rsp)
jmp .L20
.L26:
movss 12(%rsp), %xmm2
subss %xmm2, %xmm0
andps .LC7(%rip), %xmm0
movss 16(%rsp), %xmm1
subss %xmm2, %xmm1
divss %xmm1, %xmm0
mulss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
addsd .LC14(%rip), %xmm0
cvttsd2sil %xmm0, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
.L29:
divss .LC13(%rip), %xmm0
pxor %xmm5, %xmm5
ucomiss %xmm0, %xmm5
ja .L45
sqrtss %xmm0, %xmm0
.L32:
mulss .LC13(%rip), %xmm0
cvttss2sil %xmm0, %ecx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebx
testb $15, %bl
je .L48
.L33:
addq $4, %rbp
cmpl %r13d, %ebx
je .L37
.L34:
movss 0(%rbp), %xmm0
pxor %xmm3, %xmm3
comiss 12(%rsp), %xmm3
ja .L26
movss 16(%rsp), %xmm6
comiss .LC13(%rip), %xmm6
ja .L26
andps .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
addsd .LC14(%rip), %xmm0
cvttsd2sil %xmm0, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
jmp .L29
.L45:
call sqrtf@PLT
jmp .L32
.L48:
leaq .LC16(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L33
.L37:
subl $1, %r14d
subl %r15d, 20(%rsp)
cmpl $-1, %r14d
je .L35
.L25:
testl %r15d, %r15d
jle .L37
movslq 20(%rsp), %rax
movq 24(%rsp), %rdi
leaq (%rdi,%rax,4), %rbp
leal (%rbx,%r15), %r13d
jmp .L34
.L35:
testb $15, %bl
jne .L49
.L24:
movq %r12, %rdi
call fclose@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
leaq .LC16(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L24
.cfi_endproc
.LFE2158:
.size _Z8pgmwritePcPvii, .-_Z8pgmwritePcPvii
.section .rodata.str1.1
.LC17:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2159:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L53
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2159:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2185:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2185:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1132396544
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC14:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* This is a CUDA code that performs an iterative reverse edge
* detection algorithm.
*
* Training material developed by James Perry and Alan Gray
* Copyright EPCC, The University of Edinburgh, 2013
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//#include <sys/types.h>
//#include <sys/time.h>
#include<chrono>
#include <cuda_runtime_api.h>
#include <cuda.h>
#include "device_launch_parameters.h"
/* Utility Functions */
using std::chrono::time_point;
using std::chrono::system_clock;
/*
* Function to get an accurate time reading
*/
time_point<system_clock> get_current_time()
{
/*
static int start = 0, startu = 0;
struct timeval tval;
double result;
if (gettimeofday(&tval, NULL) == -1)
result = -1.0;
else if(!start) {
start = tval.tv_sec;
startu = tval.tv_usec;
result = 0.0;
}
else
result = (double) (tval.tv_sec - start) + 1.0e-6*(tval.tv_usec - startu);
return result;
*/
return std::chrono::system_clock::now();
}
/* Read the input file containing the edge data */
void datread(char *filename, void *vx, int nx, int ny)
{
FILE *fp;
int nxt, nyt, i, j, t;
float *x = (float *) vx;
if (NULL == (fp = fopen(filename,"r")))
{
fprintf(stderr, "datread: cannot open <%s>\n", filename);
exit(-1);
}
fscanf(fp,"%d %d",&nxt,&nyt);
if (nx != nxt || ny != nyt)
{
fprintf(stderr,
"datread: size mismatch, (nx,ny) = (%d,%d) expected (%d,%d)\n",
nxt, nyt, nx, ny);
exit(-1);
}
for (j=0; j<ny; j++)
{
for (i=0; i<nx; i++)
{
fscanf(fp,"%d", &t);
x[(ny-j-1)*nx + i] = (float)t;
}
}
fclose(fp);
}
/* Write the output image as a PGM file */
void pgmwrite(char *filename, void *vx, int nx, int ny)
{
FILE *fp;
int i, j, k, grey;
float xmin, xmax, tmp;
float thresh = 255.0;
float *x = (float *) vx;
if (NULL == (fp = fopen(filename,"w")))
{
fprintf(stderr, "pgmwrite: cannot create <%s>\n", filename);
exit(-1);
}
/*
* Find the max and min absolute values of the array
*/
xmin = fabs(x[0]);
xmax = fabs(x[0]);
for (i=0; i < nx*ny; i++)
{
if (fabs(x[i]) < xmin) xmin = fabs(x[i]);
if (fabs(x[i]) > xmax) xmax = fabs(x[i]);
}
fprintf(fp, "P2\n");
fprintf(fp, "# Written by pgmwrite\n");
fprintf(fp, "%d %d\n", nx, ny);
fprintf(fp, "%d\n", (int) thresh);
k = 0;
for (j=ny-1; j >=0 ; j--)
{
for (i=0; i < nx; i++)
{
/*
* Access the value of x[i][j]
*/
tmp = x[j*nx+i];
/*
* Scale the value appropriately so it lies between 0 and thresh
*/
if (xmin < 0 || xmax > thresh)
{
tmp = (int) ((thresh*((fabs(tmp-xmin))/(xmax-xmin))) + 0.5);
}
else
{
tmp = (int) (fabs(tmp) + 0.5);
}
/*
* Increase the contrast by boosting the lower values
*/
grey = (int) (thresh * sqrt(tmp/thresh));
fprintf(fp, "%3d ", grey);
if (0 == (k+1)%16) fprintf(fp, "\n");
k++;
}
}
if (0 != k%16) fprintf(fp, "\n");
fclose(fp);
}
/* Simple utility function to check for CUDA runtime errors */
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | /*
* This is a CUDA code that performs an iterative reverse edge
* detection algorithm.
*
* Training material developed by James Perry and Alan Gray
* Copyright EPCC, The University of Edinburgh, 2013
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//#include <sys/types.h>
//#include <sys/time.h>
#include<chrono>
#include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
/* Utility Functions */
using std::chrono::time_point;
using std::chrono::system_clock;
/*
* Function to get an accurate time reading
*/
time_point<system_clock> get_current_time()
{
/*
static int start = 0, startu = 0;
struct timeval tval;
double result;
if (gettimeofday(&tval, NULL) == -1)
result = -1.0;
else if(!start) {
start = tval.tv_sec;
startu = tval.tv_usec;
result = 0.0;
}
else
result = (double) (tval.tv_sec - start) + 1.0e-6*(tval.tv_usec - startu);
return result;
*/
return std::chrono::system_clock::now();
}
/* Read the input file containing the edge data */
void datread(char *filename, void *vx, int nx, int ny)
{
FILE *fp;
int nxt, nyt, i, j, t;
float *x = (float *) vx;
if (NULL == (fp = fopen(filename,"r")))
{
fprintf(stderr, "datread: cannot open <%s>\n", filename);
exit(-1);
}
fscanf(fp,"%d %d",&nxt,&nyt);
if (nx != nxt || ny != nyt)
{
fprintf(stderr,
"datread: size mismatch, (nx,ny) = (%d,%d) expected (%d,%d)\n",
nxt, nyt, nx, ny);
exit(-1);
}
for (j=0; j<ny; j++)
{
for (i=0; i<nx; i++)
{
fscanf(fp,"%d", &t);
x[(ny-j-1)*nx + i] = (float)t;
}
}
fclose(fp);
}
/* Write the output image as a PGM file */
void pgmwrite(char *filename, void *vx, int nx, int ny)
{
FILE *fp;
int i, j, k, grey;
float xmin, xmax, tmp;
float thresh = 255.0;
float *x = (float *) vx;
if (NULL == (fp = fopen(filename,"w")))
{
fprintf(stderr, "pgmwrite: cannot create <%s>\n", filename);
exit(-1);
}
/*
* Find the max and min absolute values of the array
*/
xmin = fabs(x[0]);
xmax = fabs(x[0]);
for (i=0; i < nx*ny; i++)
{
if (fabs(x[i]) < xmin) xmin = fabs(x[i]);
if (fabs(x[i]) > xmax) xmax = fabs(x[i]);
}
fprintf(fp, "P2\n");
fprintf(fp, "# Written by pgmwrite\n");
fprintf(fp, "%d %d\n", nx, ny);
fprintf(fp, "%d\n", (int) thresh);
k = 0;
for (j=ny-1; j >=0 ; j--)
{
for (i=0; i < nx; i++)
{
/*
* Access the value of x[i][j]
*/
tmp = x[j*nx+i];
/*
* Scale the value appropriately so it lies between 0 and thresh
*/
if (xmin < 0 || xmax > thresh)
{
tmp = (int) ((thresh*((fabs(tmp-xmin))/(xmax-xmin))) + 0.5);
}
else
{
tmp = (int) (fabs(tmp) + 0.5);
}
/*
* Increase the contrast by boosting the lower values
*/
grey = (int) (thresh * sqrt(tmp/thresh));
fprintf(fp, "%3d ", grey);
if (0 == (k+1)%16) fprintf(fp, "\n");
k++;
}
}
if (0 != k%16) fprintf(fp, "\n");
fclose(fp);
}
/* Simple utility function to check for CUDA runtime errors */
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* This is a CUDA code that performs an iterative reverse edge
* detection algorithm.
*
* Training material developed by James Perry and Alan Gray
* Copyright EPCC, The University of Edinburgh, 2013
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//#include <sys/types.h>
//#include <sys/time.h>
#include<chrono>
#include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
/* Utility Functions */
using std::chrono::time_point;
using std::chrono::system_clock;
/*
* Function to get an accurate time reading
*/
time_point<system_clock> get_current_time()
{
/*
static int start = 0, startu = 0;
struct timeval tval;
double result;
if (gettimeofday(&tval, NULL) == -1)
result = -1.0;
else if(!start) {
start = tval.tv_sec;
startu = tval.tv_usec;
result = 0.0;
}
else
result = (double) (tval.tv_sec - start) + 1.0e-6*(tval.tv_usec - startu);
return result;
*/
return std::chrono::system_clock::now();
}
/* Read the input file containing the edge data */
void datread(char *filename, void *vx, int nx, int ny)
{
FILE *fp;
int nxt, nyt, i, j, t;
float *x = (float *) vx;
if (NULL == (fp = fopen(filename,"r")))
{
fprintf(stderr, "datread: cannot open <%s>\n", filename);
exit(-1);
}
fscanf(fp,"%d %d",&nxt,&nyt);
if (nx != nxt || ny != nyt)
{
fprintf(stderr,
"datread: size mismatch, (nx,ny) = (%d,%d) expected (%d,%d)\n",
nxt, nyt, nx, ny);
exit(-1);
}
for (j=0; j<ny; j++)
{
for (i=0; i<nx; i++)
{
fscanf(fp,"%d", &t);
x[(ny-j-1)*nx + i] = (float)t;
}
}
fclose(fp);
}
/* Write the output image as a PGM file */
void pgmwrite(char *filename, void *vx, int nx, int ny)
{
FILE *fp;
int i, j, k, grey;
float xmin, xmax, tmp;
float thresh = 255.0;
float *x = (float *) vx;
if (NULL == (fp = fopen(filename,"w")))
{
fprintf(stderr, "pgmwrite: cannot create <%s>\n", filename);
exit(-1);
}
/*
* Find the max and min absolute values of the array
*/
xmin = fabs(x[0]);
xmax = fabs(x[0]);
for (i=0; i < nx*ny; i++)
{
if (fabs(x[i]) < xmin) xmin = fabs(x[i]);
if (fabs(x[i]) > xmax) xmax = fabs(x[i]);
}
fprintf(fp, "P2\n");
fprintf(fp, "# Written by pgmwrite\n");
fprintf(fp, "%d %d\n", nx, ny);
fprintf(fp, "%d\n", (int) thresh);
k = 0;
for (j=ny-1; j >=0 ; j--)
{
for (i=0; i < nx; i++)
{
/*
* Access the value of x[i][j]
*/
tmp = x[j*nx+i];
/*
* Scale the value appropriately so it lies between 0 and thresh
*/
if (xmin < 0 || xmax > thresh)
{
tmp = (int) ((thresh*((fabs(tmp-xmin))/(xmax-xmin))) + 0.5);
}
else
{
tmp = (int) (fabs(tmp) + 0.5);
}
/*
* Increase the contrast by boosting the lower values
*/
grey = (int) (thresh * sqrt(tmp/thresh));
fprintf(fp, "%3d ", grey);
if (0 == (k+1)%16) fprintf(fp, "\n");
k++;
}
}
if (0 != k%16) fprintf(fp, "\n");
fclose(fp);
}
/* Simple utility function to check for CUDA runtime errors */
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* This is a CUDA code that performs an iterative reverse edge
* detection algorithm.
*
* Training material developed by James Perry and Alan Gray
* Copyright EPCC, The University of Edinburgh, 2013
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//#include <sys/types.h>
//#include <sys/time.h>
#include<chrono>
#include <hip/hip_runtime_api.h>
#include <hip/hip_runtime.h>
/* Utility Functions */
using std::chrono::time_point;
using std::chrono::system_clock;
/*
* Function to get an accurate time reading
*/
time_point<system_clock> get_current_time()
{
/*
static int start = 0, startu = 0;
struct timeval tval;
double result;
if (gettimeofday(&tval, NULL) == -1)
result = -1.0;
else if(!start) {
start = tval.tv_sec;
startu = tval.tv_usec;
result = 0.0;
}
else
result = (double) (tval.tv_sec - start) + 1.0e-6*(tval.tv_usec - startu);
return result;
*/
return std::chrono::system_clock::now();
}
/* Read the input file containing the edge data */
void datread(char *filename, void *vx, int nx, int ny)
{
FILE *fp;
int nxt, nyt, i, j, t;
float *x = (float *) vx;
if (NULL == (fp = fopen(filename,"r")))
{
fprintf(stderr, "datread: cannot open <%s>\n", filename);
exit(-1);
}
fscanf(fp,"%d %d",&nxt,&nyt);
if (nx != nxt || ny != nyt)
{
fprintf(stderr,
"datread: size mismatch, (nx,ny) = (%d,%d) expected (%d,%d)\n",
nxt, nyt, nx, ny);
exit(-1);
}
for (j=0; j<ny; j++)
{
for (i=0; i<nx; i++)
{
fscanf(fp,"%d", &t);
x[(ny-j-1)*nx + i] = (float)t;
}
}
fclose(fp);
}
/* Write the output image as a PGM file */
void pgmwrite(char *filename, void *vx, int nx, int ny)
{
FILE *fp;
int i, j, k, grey;
float xmin, xmax, tmp;
float thresh = 255.0;
float *x = (float *) vx;
if (NULL == (fp = fopen(filename,"w")))
{
fprintf(stderr, "pgmwrite: cannot create <%s>\n", filename);
exit(-1);
}
/*
* Find the max and min absolute values of the array
*/
xmin = fabs(x[0]);
xmax = fabs(x[0]);
for (i=0; i < nx*ny; i++)
{
if (fabs(x[i]) < xmin) xmin = fabs(x[i]);
if (fabs(x[i]) > xmax) xmax = fabs(x[i]);
}
fprintf(fp, "P2\n");
fprintf(fp, "# Written by pgmwrite\n");
fprintf(fp, "%d %d\n", nx, ny);
fprintf(fp, "%d\n", (int) thresh);
k = 0;
for (j=ny-1; j >=0 ; j--)
{
for (i=0; i < nx; i++)
{
/*
* Access the value of x[i][j]
*/
tmp = x[j*nx+i];
/*
* Scale the value appropriately so it lies between 0 and thresh
*/
if (xmin < 0 || xmax > thresh)
{
tmp = (int) ((thresh*((fabs(tmp-xmin))/(xmax-xmin))) + 0.5);
}
else
{
tmp = (int) (fabs(tmp) + 0.5);
}
/*
* Increase the contrast by boosting the lower values
*/
grey = (int) (thresh * sqrt(tmp/thresh));
fprintf(fp, "%3d ", grey);
if (0 == (k+1)%16) fprintf(fp, "\n");
k++;
}
}
if (0 != k%16) fprintf(fp, "\n");
fclose(fp);
}
/* Simple utility function to check for CUDA runtime errors */
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .text
.file "utilities.hip"
.globl _Z16get_current_timev # -- Begin function _Z16get_current_timev
.p2align 4, 0x90
.type _Z16get_current_timev,@function
_Z16get_current_timev: # @_Z16get_current_timev
.cfi_startproc
# %bb.0:
jmp _ZNSt6chrono3_V212system_clock3nowEv # TAILCALL
.Lfunc_end0:
.size _Z16get_current_timev, .Lfunc_end0-_Z16get_current_timev
.cfi_endproc
# -- End function
.globl _Z7datreadPcPvii # -- Begin function _Z7datreadPcPvii
.p2align 4, 0x90
.type _Z7datreadPcPvii,@function
_Z7datreadPcPvii: # @_Z7datreadPcPvii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %ebx
movq %rsi, %r15
movq %rdi, %r12
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_10
# %bb.1:
movq %rax, %r14
leaq 20(%rsp), %rdx
leaq 16(%rsp), %rcx
movl $.L.str.2, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 20(%rsp), %edx
movl 16(%rsp), %ecx
cmpl %ebx, %edx
movl %ebx, %r8d
jne .LBB1_11
# %bb.2:
cmpl %ebp, %ecx
jne .LBB1_11
# %bb.3: # %.preheader25
testl %ebp, %ebp
jle .LBB1_9
# %bb.4: # %.preheader.lr.ph
movslq %r8d, %rcx
movl %ebp, %eax
movl %r8d, %ebp
movq %rax, 24(%rsp) # 8-byte Spill
decq %rax
imulq %rcx, %rax
leaq (%r15,%rax,4), %rbx
shlq $2, %rcx
negq %rcx
movq %rcx, 32(%rsp) # 8-byte Spill
leaq 12(%rsp), %r15
xorl %r13d, %r13d
movl %r8d, 8(%rsp) # 4-byte Spill
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # %._crit_edge
# in Loop: Header=BB1_5 Depth=1
incq %r13
addq 32(%rsp), %rbx # 8-byte Folded Reload
cmpq 24(%rsp), %r13 # 8-byte Folded Reload
movl 8(%rsp), %r8d # 4-byte Reload
je .LBB1_9
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_7 Depth 2
testl %r8d, %r8d
jle .LBB1_8
# %bb.6: # %.lr.ph
# in Loop: Header=BB1_5 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.4, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
xorps %xmm0, %xmm0
cvtsi2ssl 12(%rsp), %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq %r12, %rbp
jne .LBB1_7
jmp .LBB1_8
.LBB1_9: # %._crit_edge28
movq %r14, %rdi
callq fclose
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
movq %r12, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB1_11:
movq stderr(%rip), %rdi
movl $.L.str.3, %esi
movl %ebp, %r9d
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z7datreadPcPvii, .Lfunc_end1-_Z7datreadPcPvii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z8pgmwritePcPvii
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x437f0000 # float 255
.LCPI2_3:
.long 0x00000000 # float 0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z8pgmwritePcPvii
.p2align 4, 0x90
.type _Z8pgmwritePcPvii,@function
_Z8pgmwritePcPvii: # @_Z8pgmwritePcPvii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r14d
movl %edx, %ebp
movq %rsi, %r15
movq %rdi, %r12
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB2_23
# %bb.1:
movq %rax, %rbx
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
andps .LCPI2_0(%rip), %xmm0
movl %r14d, %eax
movl %ebp, 4(%rsp) # 4-byte Spill
imull %ebp, %eax
testl %eax, %eax
jle .LBB2_2
# %bb.3: # %.lr.ph.preheader
movl %eax, %eax
xorl %ecx, %ecx
movaps .LCPI2_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm0, %xmm2
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r15,%rcx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
andps %xmm1, %xmm3
movaps %xmm3, %xmm4
minss %xmm2, %xmm4
maxss %xmm0, %xmm3
incq %rcx
movaps %xmm3, %xmm0
movaps %xmm4, %xmm2
cmpq %rcx, %rax
jne .LBB2_4
jmp .LBB2_5
.LBB2_2:
movaps %xmm0, %xmm4
movaps %xmm0, %xmm3
.LBB2_5: # %._crit_edge
movaps %xmm4, 64(%rsp) # 16-byte Spill
movaps %xmm3, 32(%rsp) # 16-byte Spill
movl $1, %r12d
movl $.L.str.7, %edi
movl $3, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.8, %edi
movl $22, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.9, %esi
movq %rbx, %rdi
movl 4(%rsp), %ebp # 4-byte Reload
movl %ebp, %edx
movl %r14d, %ecx
xorl %eax, %eax
callq fprintf
movl $.L.str.10, %esi
movq %rbx, %rdi
movl $255, %edx
xorl %eax, %eax
callq fprintf
testl %r14d, %r14d
jle .LBB2_22
# %bb.6: # %.preheader.lr.ph
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps 32(%rsp), %xmm2 # 16-byte Reload
cmpltps %xmm2, %xmm0
xorps %xmm4, %xmm4
movaps 64(%rsp), %xmm3 # 16-byte Reload
movaps %xmm3, %xmm1
cmpltps %xmm4, %xmm1
orps %xmm0, %xmm1
movaps %xmm2, %xmm0
movd %xmm1, %r13d
subss %xmm3, %xmm0
movl %r14d, 8(%rsp) # 4-byte Spill
movl %r14d, %edx
movslq %ebp, %rcx
testl %ebp, %ebp
movl $0, %eax
cmovgl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, %r14d
movq %rdx, 24(%rsp) # 8-byte Spill
leaq -1(%rdx), %rax
imulq %rcx, %rax
leaq (%r15,%rax,4), %r15
shlq $2, %rcx
negq %rcx
movq %rcx, 56(%rsp) # 8-byte Spill
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl $0, 12(%rsp) # 4-byte Folded Spill
movaps %xmm0, 32(%rsp) # 16-byte Spill
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_7: # %.loopexit.loopexit
# in Loop: Header=BB2_9 Depth=1
movl 4(%rsp), %ebp # 4-byte Reload
addl %ebp, 12(%rsp) # 4-byte Folded Spill
.LBB2_8: # %.loopexit
# in Loop: Header=BB2_9 Depth=1
movq 24(%rsp), %rcx # 8-byte Reload
leaq -1(%rcx), %rax
addq 56(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r12 # 8-byte Folded Reload
cmpq $2, %rcx
movq %rax, 24(%rsp) # 8-byte Spill
jl .LBB2_20
.LBB2_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_11 Depth 2
testl %ebp, %ebp
jle .LBB2_8
# %bb.10: # %.lr.ph72
# in Loop: Header=BB2_9 Depth=1
xorl %ebp, %ebp
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_19: # in Loop: Header=BB2_11 Depth=2
incq %rbp
cmpq %rbp, %r14
movaps 64(%rsp), %xmm3 # 16-byte Reload
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
je .LBB2_7
.LBB2_11: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
testb $1, %r13b
je .LBB2_13
# %bb.12: # in Loop: Header=BB2_11 Depth=2
subss %xmm3, %xmm0
andps .LCPI2_0(%rip), %xmm0
divss 32(%rsp), %xmm0 # 16-byte Folded Reload
mulss %xmm1, %xmm0
jmp .LBB2_14
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_11 Depth=2
andps .LCPI2_0(%rip), %xmm0
.LBB2_14: # in Loop: Header=BB2_11 Depth=2
cvtss2sd %xmm0, %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvttpd2dq %xmm0, %xmm0
cvtdq2ps %xmm0, %xmm0
divss %xmm1, %xmm0
ucomiss .LCPI2_3(%rip), %xmm0
jb .LBB2_16
# %bb.15: # in Loop: Header=BB2_11 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_16: # %call.sqrt
# in Loop: Header=BB2_11 Depth=2
callq sqrtf
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.LBB2_17: # %.split
# in Loop: Header=BB2_11 Depth=2
mulss %xmm1, %xmm0
cvttss2si %xmm0, %edx
movl $.L.str.11, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
leal (%r12,%rbp), %eax
testb $15, %al
jne .LBB2_19
# %bb.18: # in Loop: Header=BB2_11 Depth=2
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
jmp .LBB2_19
.LBB2_20: # %._crit_edge77.loopexit
movq 16(%rsp), %rax # 8-byte Reload
imull 8(%rsp), %eax # 4-byte Folded Reload
testb $15, %al
je .LBB2_22
# %bb.21:
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
.LBB2_22: # %.critedge
movq %rbx, %rdi
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB2_23:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movq %r12, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z8pgmwritePcPvii, .Lfunc_end2-_Z8pgmwritePcPvii
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB3_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z14checkCUDAErrorPKc, .Lfunc_end3-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "datread: cannot open <%s>\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d %d"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "datread: size mismatch, (nx,ny) = (%d,%d) expected (%d,%d)\n"
.size .L.str.3, 60
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "pgmwrite: cannot create <%s>\n"
.size .L.str.6, 30
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "P2\n"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "# Written by pgmwrite\n"
.size .L.str.8, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d %d\n"
.size .L.str.9, 7
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d\n"
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%3d "
.size .L.str.11, 5
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.13, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bdc9d_00000000-6_utilities.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2162:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2162:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16get_current_timev
.type _Z16get_current_timev, @function
_Z16get_current_timev:
.LFB2156:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2156:
.size _Z16get_current_timev, .-_Z16get_current_timev
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "datread: cannot open <%s>\n"
.LC2:
.string "%d %d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "datread: size mismatch, (nx,ny) = (%d,%d) expected (%d,%d)\n"
.section .rodata.str1.1
.LC4:
.string "%d"
.text
.globl _Z7datreadPcPvii
.type _Z7datreadPcPvii, @function
_Z7datreadPcPvii:
.LFB2157:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movl %edx, %r14d
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L16
movq %rax, %r12
leaq 32(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 28(%rsp), %ecx
cmpl %r14d, %ecx
jne .L7
movl 4(%rsp), %eax
cmpl %eax, 32(%rsp)
jne .L7
testl %eax, %eax
jle .L8
subl $1, %eax
imull %r14d, %eax
movl %eax, (%rsp)
movl $0, %r15d
leaq .LC4(%rip), %r13
jmp .L9
.L16:
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L7:
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 120
movl 12(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
movl %r14d, %r9d
movl 48(%rsp), %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L11:
.cfi_restore_state
movslq (%rsp), %rdx
movq 8(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
movslq %r14d, %rax
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L10:
leaq 36(%rsp), %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 36(%rsp), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L10
.L12:
addl $1, %r15d
subl %r14d, (%rsp)
cmpl %r15d, 4(%rsp)
je .L8
.L9:
testl %r14d, %r14d
jg .L11
jmp .L12
.L8:
movq %r12, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2157:
.size _Z7datreadPcPvii, .-_Z7datreadPcPvii
.section .rodata.str1.1
.LC5:
.string "w"
.LC6:
.string "pgmwrite: cannot create <%s>\n"
.LC8:
.string "P2\n"
.LC9:
.string "# Written by pgmwrite\n"
.LC10:
.string "%d %d\n"
.LC11:
.string "%d\n"
.LC15:
.string "%3d "
.LC16:
.string "\n"
.text
.globl _Z8pgmwritePcPvii
.type _Z8pgmwritePcPvii, @function
_Z8pgmwritePcPvii:
.LFB2158:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, 24(%rsp)
movl %edx, %r15d
movl %ecx, %r14d
leaq .LC5(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L47
movq %rax, %r12
movq 24(%rsp), %rsi
movq %rsi, %rax
movss (%rsi), %xmm0
movaps %xmm0, %xmm7
andps .LC7(%rip), %xmm7
movss %xmm7, 12(%rsp)
movl %r15d, %edx
imull %r14d, %edx
testl %edx, %edx
jle .L38
movslq %edx, %rdx
leaq (%rsi,%rdx,4), %rdx
movss %xmm7, 16(%rsp)
movss .LC7(%rip), %xmm1
.L23:
movss (%rax), %xmm0
andps %xmm1, %xmm0
movaps %xmm0, %xmm7
minss 12(%rsp), %xmm7
movss %xmm7, 12(%rsp)
maxss 16(%rsp), %xmm0
movss %xmm0, 16(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L23
.L20:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC9(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %r8d
movl %r15d, %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $255, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
subl $1, %r14d
js .L24
movl %r14d, %eax
imull %r15d, %eax
movl %eax, 20(%rsp)
movl $0, %ebx
jmp .L25
.L47:
movq %rbx, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L38:
movss 12(%rsp), %xmm7
movss %xmm7, 16(%rsp)
jmp .L20
.L26:
movss 12(%rsp), %xmm2
subss %xmm2, %xmm0
andps .LC7(%rip), %xmm0
movss 16(%rsp), %xmm1
subss %xmm2, %xmm1
divss %xmm1, %xmm0
mulss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
addsd .LC14(%rip), %xmm0
cvttsd2sil %xmm0, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
.L29:
divss .LC13(%rip), %xmm0
pxor %xmm5, %xmm5
ucomiss %xmm0, %xmm5
ja .L45
sqrtss %xmm0, %xmm0
.L32:
mulss .LC13(%rip), %xmm0
cvttss2sil %xmm0, %ecx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebx
testb $15, %bl
je .L48
.L33:
addq $4, %rbp
cmpl %r13d, %ebx
je .L37
.L34:
movss 0(%rbp), %xmm0
pxor %xmm3, %xmm3
comiss 12(%rsp), %xmm3
ja .L26
movss 16(%rsp), %xmm6
comiss .LC13(%rip), %xmm6
ja .L26
andps .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
addsd .LC14(%rip), %xmm0
cvttsd2sil %xmm0, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
jmp .L29
.L45:
call sqrtf@PLT
jmp .L32
.L48:
leaq .LC16(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L33
.L37:
subl $1, %r14d
subl %r15d, 20(%rsp)
cmpl $-1, %r14d
je .L35
.L25:
testl %r15d, %r15d
jle .L37
movslq 20(%rsp), %rax
movq 24(%rsp), %rdi
leaq (%rdi,%rax,4), %rbp
leal (%rbx,%r15), %r13d
jmp .L34
.L35:
testb $15, %bl
jne .L49
.L24:
movq %r12, %rdi
call fclose@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
leaq .LC16(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L24
.cfi_endproc
.LFE2158:
.size _Z8pgmwritePcPvii, .-_Z8pgmwritePcPvii
.section .rodata.str1.1
.LC17:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2159:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L53
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2159:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2185:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2185:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1132396544
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC14:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "utilities.hip"
.globl _Z16get_current_timev # -- Begin function _Z16get_current_timev
.p2align 4, 0x90
.type _Z16get_current_timev,@function
_Z16get_current_timev: # @_Z16get_current_timev
.cfi_startproc
# %bb.0:
jmp _ZNSt6chrono3_V212system_clock3nowEv # TAILCALL
.Lfunc_end0:
.size _Z16get_current_timev, .Lfunc_end0-_Z16get_current_timev
.cfi_endproc
# -- End function
.globl _Z7datreadPcPvii # -- Begin function _Z7datreadPcPvii
.p2align 4, 0x90
.type _Z7datreadPcPvii,@function
_Z7datreadPcPvii: # @_Z7datreadPcPvii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %ebx
movq %rsi, %r15
movq %rdi, %r12
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_10
# %bb.1:
movq %rax, %r14
leaq 20(%rsp), %rdx
leaq 16(%rsp), %rcx
movl $.L.str.2, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 20(%rsp), %edx
movl 16(%rsp), %ecx
cmpl %ebx, %edx
movl %ebx, %r8d
jne .LBB1_11
# %bb.2:
cmpl %ebp, %ecx
jne .LBB1_11
# %bb.3: # %.preheader25
testl %ebp, %ebp
jle .LBB1_9
# %bb.4: # %.preheader.lr.ph
movslq %r8d, %rcx
movl %ebp, %eax
movl %r8d, %ebp
movq %rax, 24(%rsp) # 8-byte Spill
decq %rax
imulq %rcx, %rax
leaq (%r15,%rax,4), %rbx
shlq $2, %rcx
negq %rcx
movq %rcx, 32(%rsp) # 8-byte Spill
leaq 12(%rsp), %r15
xorl %r13d, %r13d
movl %r8d, 8(%rsp) # 4-byte Spill
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # %._crit_edge
# in Loop: Header=BB1_5 Depth=1
incq %r13
addq 32(%rsp), %rbx # 8-byte Folded Reload
cmpq 24(%rsp), %r13 # 8-byte Folded Reload
movl 8(%rsp), %r8d # 4-byte Reload
je .LBB1_9
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_7 Depth 2
testl %r8d, %r8d
jle .LBB1_8
# %bb.6: # %.lr.ph
# in Loop: Header=BB1_5 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.4, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
xorps %xmm0, %xmm0
cvtsi2ssl 12(%rsp), %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq %r12, %rbp
jne .LBB1_7
jmp .LBB1_8
.LBB1_9: # %._crit_edge28
movq %r14, %rdi
callq fclose
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
movq %r12, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB1_11:
movq stderr(%rip), %rdi
movl $.L.str.3, %esi
movl %ebp, %r9d
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z7datreadPcPvii, .Lfunc_end1-_Z7datreadPcPvii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z8pgmwritePcPvii
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x437f0000 # float 255
.LCPI2_3:
.long 0x00000000 # float 0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z8pgmwritePcPvii
.p2align 4, 0x90
.type _Z8pgmwritePcPvii,@function
_Z8pgmwritePcPvii: # @_Z8pgmwritePcPvii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r14d
movl %edx, %ebp
movq %rsi, %r15
movq %rdi, %r12
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB2_23
# %bb.1:
movq %rax, %rbx
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
andps .LCPI2_0(%rip), %xmm0
movl %r14d, %eax
movl %ebp, 4(%rsp) # 4-byte Spill
imull %ebp, %eax
testl %eax, %eax
jle .LBB2_2
# %bb.3: # %.lr.ph.preheader
movl %eax, %eax
xorl %ecx, %ecx
movaps .LCPI2_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm0, %xmm2
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r15,%rcx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
andps %xmm1, %xmm3
movaps %xmm3, %xmm4
minss %xmm2, %xmm4
maxss %xmm0, %xmm3
incq %rcx
movaps %xmm3, %xmm0
movaps %xmm4, %xmm2
cmpq %rcx, %rax
jne .LBB2_4
jmp .LBB2_5
.LBB2_2:
movaps %xmm0, %xmm4
movaps %xmm0, %xmm3
.LBB2_5: # %._crit_edge
movaps %xmm4, 64(%rsp) # 16-byte Spill
movaps %xmm3, 32(%rsp) # 16-byte Spill
movl $1, %r12d
movl $.L.str.7, %edi
movl $3, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.8, %edi
movl $22, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.9, %esi
movq %rbx, %rdi
movl 4(%rsp), %ebp # 4-byte Reload
movl %ebp, %edx
movl %r14d, %ecx
xorl %eax, %eax
callq fprintf
movl $.L.str.10, %esi
movq %rbx, %rdi
movl $255, %edx
xorl %eax, %eax
callq fprintf
testl %r14d, %r14d
jle .LBB2_22
# %bb.6: # %.preheader.lr.ph
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps 32(%rsp), %xmm2 # 16-byte Reload
cmpltps %xmm2, %xmm0
xorps %xmm4, %xmm4
movaps 64(%rsp), %xmm3 # 16-byte Reload
movaps %xmm3, %xmm1
cmpltps %xmm4, %xmm1
orps %xmm0, %xmm1
movaps %xmm2, %xmm0
movd %xmm1, %r13d
subss %xmm3, %xmm0
movl %r14d, 8(%rsp) # 4-byte Spill
movl %r14d, %edx
movslq %ebp, %rcx
testl %ebp, %ebp
movl $0, %eax
cmovgl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, %r14d
movq %rdx, 24(%rsp) # 8-byte Spill
leaq -1(%rdx), %rax
imulq %rcx, %rax
leaq (%r15,%rax,4), %r15
shlq $2, %rcx
negq %rcx
movq %rcx, 56(%rsp) # 8-byte Spill
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl $0, 12(%rsp) # 4-byte Folded Spill
movaps %xmm0, 32(%rsp) # 16-byte Spill
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_7: # %.loopexit.loopexit
# in Loop: Header=BB2_9 Depth=1
movl 4(%rsp), %ebp # 4-byte Reload
addl %ebp, 12(%rsp) # 4-byte Folded Spill
.LBB2_8: # %.loopexit
# in Loop: Header=BB2_9 Depth=1
movq 24(%rsp), %rcx # 8-byte Reload
leaq -1(%rcx), %rax
addq 56(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r12 # 8-byte Folded Reload
cmpq $2, %rcx
movq %rax, 24(%rsp) # 8-byte Spill
jl .LBB2_20
.LBB2_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_11 Depth 2
testl %ebp, %ebp
jle .LBB2_8
# %bb.10: # %.lr.ph72
# in Loop: Header=BB2_9 Depth=1
xorl %ebp, %ebp
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_19: # in Loop: Header=BB2_11 Depth=2
incq %rbp
cmpq %rbp, %r14
movaps 64(%rsp), %xmm3 # 16-byte Reload
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
je .LBB2_7
.LBB2_11: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
testb $1, %r13b
je .LBB2_13
# %bb.12: # in Loop: Header=BB2_11 Depth=2
subss %xmm3, %xmm0
andps .LCPI2_0(%rip), %xmm0
divss 32(%rsp), %xmm0 # 16-byte Folded Reload
mulss %xmm1, %xmm0
jmp .LBB2_14
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_11 Depth=2
andps .LCPI2_0(%rip), %xmm0
.LBB2_14: # in Loop: Header=BB2_11 Depth=2
cvtss2sd %xmm0, %xmm0
addsd .LCPI2_2(%rip), %xmm0
cvttpd2dq %xmm0, %xmm0
cvtdq2ps %xmm0, %xmm0
divss %xmm1, %xmm0
ucomiss .LCPI2_3(%rip), %xmm0
jb .LBB2_16
# %bb.15: # in Loop: Header=BB2_11 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_16: # %call.sqrt
# in Loop: Header=BB2_11 Depth=2
callq sqrtf
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.LBB2_17: # %.split
# in Loop: Header=BB2_11 Depth=2
mulss %xmm1, %xmm0
cvttss2si %xmm0, %edx
movl $.L.str.11, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
leal (%r12,%rbp), %eax
testb $15, %al
jne .LBB2_19
# %bb.18: # in Loop: Header=BB2_11 Depth=2
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
jmp .LBB2_19
.LBB2_20: # %._crit_edge77.loopexit
movq 16(%rsp), %rax # 8-byte Reload
imull 8(%rsp), %eax # 4-byte Folded Reload
testb $15, %al
je .LBB2_22
# %bb.21:
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
.LBB2_22: # %.critedge
movq %rbx, %rdi
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB2_23:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movq %r12, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z8pgmwritePcPvii, .Lfunc_end2-_Z8pgmwritePcPvii
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB3_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z14checkCUDAErrorPKc, .Lfunc_end3-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "datread: cannot open <%s>\n"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d %d"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "datread: size mismatch, (nx,ny) = (%d,%d) expected (%d,%d)\n"
.size .L.str.3, 60
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "pgmwrite: cannot create <%s>\n"
.size .L.str.6, 30
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "P2\n"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "# Written by pgmwrite\n"
.size .L.str.8, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d %d\n"
.size .L.str.9, 7
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d\n"
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%3d "
.size .L.str.11, 5
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.13, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
inline cudaError_t checkCuda(cudaError_t result)
{
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
return result;
}
void checkResults(float *A, float *B, int width) {
float maxError = 0.0f;
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
int index = i*width + j;
//printf("A=%f B=%f \n", A[index], B[index]);
maxError = fmax(maxError, fabs(A[index] - B[index] - 3.0f));
}
}
printf("Max error: %f \n", maxError );
if (maxError != 3.0f) {
printf("Unsuccessful results\n");
}
else {
printf("Successful results\n");
}
}
__global__ void dgemm(float *M, float *N, float *P, int width) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if ((row < width) && (col < width)) {
float pVal = 0;
for (int i = 0; i < width; i++) {
pVal = pVal + M[row * width + i] * N[col + i*width];
}
P[row * width + col] = pVal;
}
}
void dgemm_cpu(float *M, float *N, float *P, int width) {
for (int row = 0; row < width; row++)
for (int col = 0; col < width; col++) {
float pVal = 0;
for (int k = 0; k < width; k++) {
pVal = pVal + M[row * width + k] * N[col + k*width];
}
P[row * width + col] = pVal;
}
}
int main(int argc, char **argv)
{
int width = (argc > 1)?atoi (argv[1]) : 256;
const int mem_size = width*width*sizeof(float);
int blockSize = 32;
int numBlocks = (width + blockSize - 1) / blockSize;
dim3 dimBlock(blockSize, blockSize, 1);
dim3 dimGrid(numBlocks, numBlocks, 1);
float *A_h = (float*)malloc(mem_size);
float *B_h = (float*)malloc(mem_size);
float *C_h = (float*)malloc(mem_size);
float *S_h = (float*)malloc(mem_size);
float *O_h = (float*)malloc(mem_size);
for (int j = 0; j < width; j++) {
for (int i = 0; i < width; i++) {
int index = j*width + i;
A_h[index] = 2;
B_h[index] = 2;
C_h[index] = 2;
}
}
clock_t tStart = clock();
dgemm_cpu(A_h, B_h, S_h, width);
dgemm_cpu(S_h, C_h, O_h, width);
printf("Time taken by Host: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
float *A_d;
float *B_d;
float *C_d;
float *O_d;
float *S_d;
checkCuda( cudaMalloc(&A_d, mem_size) );
checkCuda( cudaMalloc(&B_d, mem_size) );
checkCuda( cudaMalloc(&C_d, mem_size) );
checkCuda( cudaMalloc(&S_d, mem_size) );
checkCuda( cudaMalloc(&O_d, mem_size) );
checkCuda( cudaMemcpy(A_d, A_h, mem_size, cudaMemcpyHostToDevice) );
checkCuda( cudaMemcpy(B_d, B_h, mem_size, cudaMemcpyHostToDevice) );
tStart = clock();
dgemm<<<dimGrid, dimBlock>>>(A_d, B_d, S_d, width);
cudaDeviceSynchronize();
checkCuda( cudaMemcpy(C_d, C_h, mem_size, cudaMemcpyHostToDevice) );
dgemm<<<dimGrid, dimBlock>>>(S_d, C_d, O_d, width);
cudaDeviceSynchronize();
clock_t tEnd = clock();
checkCuda( cudaMemcpy(S_h, O_d, mem_size, cudaMemcpyDeviceToHost) );
printf("Time taken by GPU: %.6fs\n", (double)(tEnd - tStart) / CLOCKS_PER_SEC);
checkResults(O_h, S_h, width);
error_exit:
checkCuda( cudaFree(A_d) );
checkCuda( cudaFree(B_d) );
checkCuda( cudaFree(C_d) );
checkCuda( cudaFree(O_d) );
free(C_h);
free(A_h);
free(B_h);
free(S_h);
free(O_h);
} | code for sm_80
Function : _Z5dgemmPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
inline cudaError_t checkCuda(cudaError_t result)
{
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
return result;
}
void checkResults(float *A, float *B, int width) {
float maxError = 0.0f;
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
int index = i*width + j;
//printf("A=%f B=%f \n", A[index], B[index]);
maxError = fmax(maxError, fabs(A[index] - B[index] - 3.0f));
}
}
printf("Max error: %f \n", maxError );
if (maxError != 3.0f) {
printf("Unsuccessful results\n");
}
else {
printf("Successful results\n");
}
}
__global__ void dgemm(float *M, float *N, float *P, int width) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if ((row < width) && (col < width)) {
float pVal = 0;
for (int i = 0; i < width; i++) {
pVal = pVal + M[row * width + i] * N[col + i*width];
}
P[row * width + col] = pVal;
}
}
void dgemm_cpu(float *M, float *N, float *P, int width) {
for (int row = 0; row < width; row++)
for (int col = 0; col < width; col++) {
float pVal = 0;
for (int k = 0; k < width; k++) {
pVal = pVal + M[row * width + k] * N[col + k*width];
}
P[row * width + col] = pVal;
}
}
int main(int argc, char **argv)
{
int width = (argc > 1)?atoi (argv[1]) : 256;
const int mem_size = width*width*sizeof(float);
int blockSize = 32;
int numBlocks = (width + blockSize - 1) / blockSize;
dim3 dimBlock(blockSize, blockSize, 1);
dim3 dimGrid(numBlocks, numBlocks, 1);
float *A_h = (float*)malloc(mem_size);
float *B_h = (float*)malloc(mem_size);
float *C_h = (float*)malloc(mem_size);
float *S_h = (float*)malloc(mem_size);
float *O_h = (float*)malloc(mem_size);
for (int j = 0; j < width; j++) {
for (int i = 0; i < width; i++) {
int index = j*width + i;
A_h[index] = 2;
B_h[index] = 2;
C_h[index] = 2;
}
}
clock_t tStart = clock();
dgemm_cpu(A_h, B_h, S_h, width);
dgemm_cpu(S_h, C_h, O_h, width);
printf("Time taken by Host: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
float *A_d;
float *B_d;
float *C_d;
float *O_d;
float *S_d;
checkCuda( cudaMalloc(&A_d, mem_size) );
checkCuda( cudaMalloc(&B_d, mem_size) );
checkCuda( cudaMalloc(&C_d, mem_size) );
checkCuda( cudaMalloc(&S_d, mem_size) );
checkCuda( cudaMalloc(&O_d, mem_size) );
checkCuda( cudaMemcpy(A_d, A_h, mem_size, cudaMemcpyHostToDevice) );
checkCuda( cudaMemcpy(B_d, B_h, mem_size, cudaMemcpyHostToDevice) );
tStart = clock();
dgemm<<<dimGrid, dimBlock>>>(A_d, B_d, S_d, width);
cudaDeviceSynchronize();
checkCuda( cudaMemcpy(C_d, C_h, mem_size, cudaMemcpyHostToDevice) );
dgemm<<<dimGrid, dimBlock>>>(S_d, C_d, O_d, width);
cudaDeviceSynchronize();
clock_t tEnd = clock();
checkCuda( cudaMemcpy(S_h, O_d, mem_size, cudaMemcpyDeviceToHost) );
printf("Time taken by GPU: %.6fs\n", (double)(tEnd - tStart) / CLOCKS_PER_SEC);
checkResults(O_h, S_h, width);
error_exit:
checkCuda( cudaFree(A_d) );
checkCuda( cudaFree(B_d) );
checkCuda( cudaFree(C_d) );
checkCuda( cudaFree(O_d) );
free(C_h);
free(A_h);
free(B_h);
free(S_h);
free(O_h);
} | .file "tmpxft_0018f032_00000000-6_DoubleMulMat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9checkCuda9cudaError.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA Runtime Error: %s\n"
.section .text._Z9checkCuda9cudaError,"axG",@progbits,_Z9checkCuda9cudaError,comdat
.weak _Z9checkCuda9cudaError
.type _Z9checkCuda9cudaError, @function
_Z9checkCuda9cudaError:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
testl %edi, %edi
jne .L6
.L4:
movl %ebx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L4
.cfi_endproc
.LFE2057:
.size _Z9checkCuda9cudaError, .-_Z9checkCuda9cudaError
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Max error: %f \n"
.LC5:
.string "Unsuccessful results\n"
.LC6:
.string "Successful results\n"
.text
.globl _Z12checkResultsPfS_i
.type _Z12checkResultsPfS_i, @function
_Z12checkResultsPfS_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 28(%rsp)
testl %edx, %edx
jle .L8
movslq %edx, %r15
salq $2, %r15
leaq (%rdi,%r15), %r12
movl $0, %r13d
movl $0, %r14d
movl $0x00000000, 24(%rsp)
.L9:
movq 8(%rsp), %rax
leaq (%rax,%r13), %rbx
movq 16(%rsp), %rax
leaq (%rax,%r13), %rbp
.L10:
movss (%rbx), %xmm0
subss 0(%rbp), %xmm0
subss .LC2(%rip), %xmm0
andps .LC3(%rip), %xmm0
movss 24(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 24(%rsp)
addq $4, %rbx
addq $4, %rbp
cmpq %r12, %rbx
jne .L10
addl $1, %r14d
addq %r15, %r12
addq %r15, %r13
cmpl %r14d, 28(%rsp)
jne .L9
pxor %xmm0, %xmm0
cvtss2sd 24(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 24(%rsp), %xmm2
ucomiss .LC2(%rip), %xmm2
jp .L15
jne .L15
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L8:
pxor %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L15:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L7:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12checkResultsPfS_i, .-_Z12checkResultsPfS_i
.globl _Z9dgemm_cpuPfS_S_i
.type _Z9dgemm_cpuPfS_S_i, @function
_Z9dgemm_cpuPfS_S_i:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L26
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbx
movq %rdx, %r9
movl %ecx, %r12d
movslq %ecx, %r11
leaq 0(,%r11,4), %rcx
movq %rdi, %r10
leaq (%rdi,%rcx), %rsi
movl $0, %ebp
.L20:
movq %rbx, %r8
movl $0, %edi
.L23:
movq %r8, %rdx
movq %r10, %rax
pxor %xmm1, %xmm1
.L21:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rcx, %rdx
cmpq %rsi, %rax
jne .L21
movss %xmm1, (%r9,%rdi,4)
addq $1, %rdi
addq $4, %r8
cmpq %r11, %rdi
jne .L23
addl $1, %ebp
addq %rcx, %r9
addq %rcx, %r10
addq %rcx, %rsi
cmpl %ebp, %r12d
jne .L20
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2059:
.size _Z9dgemm_cpuPfS_S_i, .-_Z9dgemm_cpuPfS_S_i
.globl _Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i
.type _Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5dgemmPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i, .-_Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i
.globl _Z5dgemmPfS_S_i
.type _Z5dgemmPfS_S_i, @function
_Z5dgemmPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z5dgemmPfS_S_i, .-_Z5dgemmPfS_S_i
.section .rodata.str1.1
.LC10:
.string "Time taken by Host: %.6fs\n"
.LC11:
.string "Time taken by GPU: %.6fs\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $256, %r13d
cmpl $1, %edi
jg .L48
.L38:
movl $32, 80(%rsp)
movl $32, 84(%rsp)
movl $1, 88(%rsp)
leal 62(%r13), %eax
movl %r13d, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 92(%rsp)
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl %r13d, %r14d
imull %r13d, %r14d
sall $2, %r14d
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %r15
movq %r14, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %r13d, %r13d
jle .L39
movslq %r13d, %rsi
leaq 0(,%rsi,4), %rdi
negq %rsi
salq $2, %rsi
movq %rdi, %rdx
movl $0, %ecx
movss .LC8(%rip), %xmm0
.L40:
leaq (%rdx,%rsi), %rax
.L41:
movss %xmm0, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
movss %xmm0, (%r12,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L41
addl $1, %ecx
addq %rdi, %rdx
cmpl %ecx, %r13d
jne .L40
.L39:
call clock@PLT
movq %rax, 16(%rsp)
movl %r13d, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z9dgemm_cpuPfS_S_i
movl %r13d, %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq %r15, %rdi
call _Z9dgemm_cpuPfS_S_i
call clock@PLT
movq 16(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC9(%rip), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 72(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 64(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call clock@PLT
movq %rax, 16(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L42:
call cudaDeviceSynchronize@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L43:
call cudaDeviceSynchronize@PLT
call clock@PLT
movq %rax, 24(%rsp)
movl $2, %ecx
movq %r14, %rdx
movq 64(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC9(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %r13d, %edx
movq %r15, %rsi
movq 8(%rsp), %r14
movq %r14, %rdi
call _Z12checkResultsPfS_i
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
jmp .L38
.L49:
movl %r13d, %ecx
movq 72(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i
jmp .L42
.L50:
movl %r13d, %ecx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i
jmp .L43
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z5dgemmPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z5dgemmPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC8:
.long 1073741824
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
inline cudaError_t checkCuda(cudaError_t result)
{
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
return result;
}
void checkResults(float *A, float *B, int width) {
float maxError = 0.0f;
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
int index = i*width + j;
//printf("A=%f B=%f \n", A[index], B[index]);
maxError = fmax(maxError, fabs(A[index] - B[index] - 3.0f));
}
}
printf("Max error: %f \n", maxError );
if (maxError != 3.0f) {
printf("Unsuccessful results\n");
}
else {
printf("Successful results\n");
}
}
__global__ void dgemm(float *M, float *N, float *P, int width) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if ((row < width) && (col < width)) {
float pVal = 0;
for (int i = 0; i < width; i++) {
pVal = pVal + M[row * width + i] * N[col + i*width];
}
P[row * width + col] = pVal;
}
}
void dgemm_cpu(float *M, float *N, float *P, int width) {
for (int row = 0; row < width; row++)
for (int col = 0; col < width; col++) {
float pVal = 0;
for (int k = 0; k < width; k++) {
pVal = pVal + M[row * width + k] * N[col + k*width];
}
P[row * width + col] = pVal;
}
}
int main(int argc, char **argv)
{
int width = (argc > 1)?atoi (argv[1]) : 256;
const int mem_size = width*width*sizeof(float);
int blockSize = 32;
int numBlocks = (width + blockSize - 1) / blockSize;
dim3 dimBlock(blockSize, blockSize, 1);
dim3 dimGrid(numBlocks, numBlocks, 1);
float *A_h = (float*)malloc(mem_size);
float *B_h = (float*)malloc(mem_size);
float *C_h = (float*)malloc(mem_size);
float *S_h = (float*)malloc(mem_size);
float *O_h = (float*)malloc(mem_size);
for (int j = 0; j < width; j++) {
for (int i = 0; i < width; i++) {
int index = j*width + i;
A_h[index] = 2;
B_h[index] = 2;
C_h[index] = 2;
}
}
clock_t tStart = clock();
dgemm_cpu(A_h, B_h, S_h, width);
dgemm_cpu(S_h, C_h, O_h, width);
printf("Time taken by Host: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
float *A_d;
float *B_d;
float *C_d;
float *O_d;
float *S_d;
checkCuda( cudaMalloc(&A_d, mem_size) );
checkCuda( cudaMalloc(&B_d, mem_size) );
checkCuda( cudaMalloc(&C_d, mem_size) );
checkCuda( cudaMalloc(&S_d, mem_size) );
checkCuda( cudaMalloc(&O_d, mem_size) );
checkCuda( cudaMemcpy(A_d, A_h, mem_size, cudaMemcpyHostToDevice) );
checkCuda( cudaMemcpy(B_d, B_h, mem_size, cudaMemcpyHostToDevice) );
tStart = clock();
dgemm<<<dimGrid, dimBlock>>>(A_d, B_d, S_d, width);
cudaDeviceSynchronize();
checkCuda( cudaMemcpy(C_d, C_h, mem_size, cudaMemcpyHostToDevice) );
dgemm<<<dimGrid, dimBlock>>>(S_d, C_d, O_d, width);
cudaDeviceSynchronize();
clock_t tEnd = clock();
checkCuda( cudaMemcpy(S_h, O_d, mem_size, cudaMemcpyDeviceToHost) );
printf("Time taken by GPU: %.6fs\n", (double)(tEnd - tStart) / CLOCKS_PER_SEC);
checkResults(O_h, S_h, width);
error_exit:
checkCuda( cudaFree(A_d) );
checkCuda( cudaFree(B_d) );
checkCuda( cudaFree(C_d) );
checkCuda( cudaFree(O_d) );
free(C_h);
free(A_h);
free(B_h);
free(S_h);
free(O_h);
} | #include <hip/hip_runtime.h>
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
inline hipError_t checkCuda(hipError_t result)
{
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
return result;
}
void checkResults(float *A, float *B, int width) {
float maxError = 0.0f;
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
int index = i*width + j;
//printf("A=%f B=%f \n", A[index], B[index]);
maxError = fmax(maxError, fabs(A[index] - B[index] - 3.0f));
}
}
printf("Max error: %f \n", maxError );
if (maxError != 3.0f) {
printf("Unsuccessful results\n");
}
else {
printf("Successful results\n");
}
}
__global__ void dgemm(float *M, float *N, float *P, int width) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if ((row < width) && (col < width)) {
float pVal = 0;
for (int i = 0; i < width; i++) {
pVal = pVal + M[row * width + i] * N[col + i*width];
}
P[row * width + col] = pVal;
}
}
void dgemm_cpu(float *M, float *N, float *P, int width) {
for (int row = 0; row < width; row++)
for (int col = 0; col < width; col++) {
float pVal = 0;
for (int k = 0; k < width; k++) {
pVal = pVal + M[row * width + k] * N[col + k*width];
}
P[row * width + col] = pVal;
}
}
int main(int argc, char **argv)
{
int width = (argc > 1)?atoi (argv[1]) : 256;
const int mem_size = width*width*sizeof(float);
int blockSize = 32;
int numBlocks = (width + blockSize - 1) / blockSize;
dim3 dimBlock(blockSize, blockSize, 1);
dim3 dimGrid(numBlocks, numBlocks, 1);
float *A_h = (float*)malloc(mem_size);
float *B_h = (float*)malloc(mem_size);
float *C_h = (float*)malloc(mem_size);
float *S_h = (float*)malloc(mem_size);
float *O_h = (float*)malloc(mem_size);
for (int j = 0; j < width; j++) {
for (int i = 0; i < width; i++) {
int index = j*width + i;
A_h[index] = 2;
B_h[index] = 2;
C_h[index] = 2;
}
}
clock_t tStart = clock();
dgemm_cpu(A_h, B_h, S_h, width);
dgemm_cpu(S_h, C_h, O_h, width);
printf("Time taken by Host: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
float *A_d;
float *B_d;
float *C_d;
float *O_d;
float *S_d;
checkCuda( hipMalloc(&A_d, mem_size) );
checkCuda( hipMalloc(&B_d, mem_size) );
checkCuda( hipMalloc(&C_d, mem_size) );
checkCuda( hipMalloc(&S_d, mem_size) );
checkCuda( hipMalloc(&O_d, mem_size) );
checkCuda( hipMemcpy(A_d, A_h, mem_size, hipMemcpyHostToDevice) );
checkCuda( hipMemcpy(B_d, B_h, mem_size, hipMemcpyHostToDevice) );
tStart = clock();
dgemm<<<dimGrid, dimBlock>>>(A_d, B_d, S_d, width);
hipDeviceSynchronize();
checkCuda( hipMemcpy(C_d, C_h, mem_size, hipMemcpyHostToDevice) );
dgemm<<<dimGrid, dimBlock>>>(S_d, C_d, O_d, width);
hipDeviceSynchronize();
clock_t tEnd = clock();
checkCuda( hipMemcpy(S_h, O_d, mem_size, hipMemcpyDeviceToHost) );
printf("Time taken by GPU: %.6fs\n", (double)(tEnd - tStart) / CLOCKS_PER_SEC);
checkResults(O_h, S_h, width);
error_exit:
checkCuda( hipFree(A_d) );
checkCuda( hipFree(B_d) );
checkCuda( hipFree(C_d) );
checkCuda( hipFree(O_d) );
free(C_h);
free(A_h);
free(B_h);
free(S_h);
free(O_h);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
inline hipError_t checkCuda(hipError_t result)
{
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
return result;
}
void checkResults(float *A, float *B, int width) {
float maxError = 0.0f;
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
int index = i*width + j;
//printf("A=%f B=%f \n", A[index], B[index]);
maxError = fmax(maxError, fabs(A[index] - B[index] - 3.0f));
}
}
printf("Max error: %f \n", maxError );
if (maxError != 3.0f) {
printf("Unsuccessful results\n");
}
else {
printf("Successful results\n");
}
}
__global__ void dgemm(float *M, float *N, float *P, int width) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if ((row < width) && (col < width)) {
float pVal = 0;
for (int i = 0; i < width; i++) {
pVal = pVal + M[row * width + i] * N[col + i*width];
}
P[row * width + col] = pVal;
}
}
void dgemm_cpu(float *M, float *N, float *P, int width) {
for (int row = 0; row < width; row++)
for (int col = 0; col < width; col++) {
float pVal = 0;
for (int k = 0; k < width; k++) {
pVal = pVal + M[row * width + k] * N[col + k*width];
}
P[row * width + col] = pVal;
}
}
int main(int argc, char **argv)
{
int width = (argc > 1)?atoi (argv[1]) : 256;
const int mem_size = width*width*sizeof(float);
int blockSize = 32;
int numBlocks = (width + blockSize - 1) / blockSize;
dim3 dimBlock(blockSize, blockSize, 1);
dim3 dimGrid(numBlocks, numBlocks, 1);
float *A_h = (float*)malloc(mem_size);
float *B_h = (float*)malloc(mem_size);
float *C_h = (float*)malloc(mem_size);
float *S_h = (float*)malloc(mem_size);
float *O_h = (float*)malloc(mem_size);
for (int j = 0; j < width; j++) {
for (int i = 0; i < width; i++) {
int index = j*width + i;
A_h[index] = 2;
B_h[index] = 2;
C_h[index] = 2;
}
}
clock_t tStart = clock();
dgemm_cpu(A_h, B_h, S_h, width);
dgemm_cpu(S_h, C_h, O_h, width);
printf("Time taken by Host: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
float *A_d;
float *B_d;
float *C_d;
float *O_d;
float *S_d;
checkCuda( hipMalloc(&A_d, mem_size) );
checkCuda( hipMalloc(&B_d, mem_size) );
checkCuda( hipMalloc(&C_d, mem_size) );
checkCuda( hipMalloc(&S_d, mem_size) );
checkCuda( hipMalloc(&O_d, mem_size) );
checkCuda( hipMemcpy(A_d, A_h, mem_size, hipMemcpyHostToDevice) );
checkCuda( hipMemcpy(B_d, B_h, mem_size, hipMemcpyHostToDevice) );
tStart = clock();
dgemm<<<dimGrid, dimBlock>>>(A_d, B_d, S_d, width);
hipDeviceSynchronize();
checkCuda( hipMemcpy(C_d, C_h, mem_size, hipMemcpyHostToDevice) );
dgemm<<<dimGrid, dimBlock>>>(S_d, C_d, O_d, width);
hipDeviceSynchronize();
clock_t tEnd = clock();
checkCuda( hipMemcpy(S_h, O_d, mem_size, hipMemcpyDeviceToHost) );
printf("Time taken by GPU: %.6fs\n", (double)(tEnd - tStart) / CLOCKS_PER_SEC);
checkResults(O_h, S_h, width);
error_exit:
checkCuda( hipFree(A_d) );
checkCuda( hipFree(B_d) );
checkCuda( hipFree(C_d) );
checkCuda( hipFree(O_d) );
free(C_h);
free(A_h);
free(B_h);
free(S_h);
free(O_h);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5dgemmPfS_S_i
.globl _Z5dgemmPfS_S_i
.p2align 8
.type _Z5dgemmPfS_S_i,@function
_Z5dgemmPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5dgemmPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5dgemmPfS_S_i, .Lfunc_end0-_Z5dgemmPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5dgemmPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5dgemmPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
inline hipError_t checkCuda(hipError_t result)
{
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
return result;
}
void checkResults(float *A, float *B, int width) {
float maxError = 0.0f;
for (int i = 0; i < width; i++) {
for (int j = 0; j < width; j++) {
int index = i*width + j;
//printf("A=%f B=%f \n", A[index], B[index]);
maxError = fmax(maxError, fabs(A[index] - B[index] - 3.0f));
}
}
printf("Max error: %f \n", maxError );
if (maxError != 3.0f) {
printf("Unsuccessful results\n");
}
else {
printf("Successful results\n");
}
}
__global__ void dgemm(float *M, float *N, float *P, int width) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if ((row < width) && (col < width)) {
float pVal = 0;
for (int i = 0; i < width; i++) {
pVal = pVal + M[row * width + i] * N[col + i*width];
}
P[row * width + col] = pVal;
}
}
void dgemm_cpu(float *M, float *N, float *P, int width) {
for (int row = 0; row < width; row++)
for (int col = 0; col < width; col++) {
float pVal = 0;
for (int k = 0; k < width; k++) {
pVal = pVal + M[row * width + k] * N[col + k*width];
}
P[row * width + col] = pVal;
}
}
int main(int argc, char **argv)
{
int width = (argc > 1)?atoi (argv[1]) : 256;
const int mem_size = width*width*sizeof(float);
int blockSize = 32;
int numBlocks = (width + blockSize - 1) / blockSize;
dim3 dimBlock(blockSize, blockSize, 1);
dim3 dimGrid(numBlocks, numBlocks, 1);
float *A_h = (float*)malloc(mem_size);
float *B_h = (float*)malloc(mem_size);
float *C_h = (float*)malloc(mem_size);
float *S_h = (float*)malloc(mem_size);
float *O_h = (float*)malloc(mem_size);
for (int j = 0; j < width; j++) {
for (int i = 0; i < width; i++) {
int index = j*width + i;
A_h[index] = 2;
B_h[index] = 2;
C_h[index] = 2;
}
}
clock_t tStart = clock();
dgemm_cpu(A_h, B_h, S_h, width);
dgemm_cpu(S_h, C_h, O_h, width);
printf("Time taken by Host: %.6fs\n", (double)(clock() - tStart) / CLOCKS_PER_SEC);
float *A_d;
float *B_d;
float *C_d;
float *O_d;
float *S_d;
checkCuda( hipMalloc(&A_d, mem_size) );
checkCuda( hipMalloc(&B_d, mem_size) );
checkCuda( hipMalloc(&C_d, mem_size) );
checkCuda( hipMalloc(&S_d, mem_size) );
checkCuda( hipMalloc(&O_d, mem_size) );
checkCuda( hipMemcpy(A_d, A_h, mem_size, hipMemcpyHostToDevice) );
checkCuda( hipMemcpy(B_d, B_h, mem_size, hipMemcpyHostToDevice) );
tStart = clock();
dgemm<<<dimGrid, dimBlock>>>(A_d, B_d, S_d, width);
hipDeviceSynchronize();
checkCuda( hipMemcpy(C_d, C_h, mem_size, hipMemcpyHostToDevice) );
dgemm<<<dimGrid, dimBlock>>>(S_d, C_d, O_d, width);
hipDeviceSynchronize();
clock_t tEnd = clock();
checkCuda( hipMemcpy(S_h, O_d, mem_size, hipMemcpyDeviceToHost) );
printf("Time taken by GPU: %.6fs\n", (double)(tEnd - tStart) / CLOCKS_PER_SEC);
checkResults(O_h, S_h, width);
error_exit:
checkCuda( hipFree(A_d) );
checkCuda( hipFree(B_d) );
checkCuda( hipFree(C_d) );
checkCuda( hipFree(O_d) );
free(C_h);
free(A_h);
free(B_h);
free(S_h);
free(O_h);
} | .text
.file "DoubleMulMat.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12checkResultsPfS_i
.LCPI0_0:
.long 0xc0400000 # float -3
.LCPI0_2:
.long 0x40400000 # float 3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z12checkResultsPfS_i
.p2align 4, 0x90
.type _Z12checkResultsPfS_i,@function
_Z12checkResultsPfS_i: # @_Z12checkResultsPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB0_1
# %bb.2: # %.preheader.lr.ph
movl %edx, %eax
xorps %xmm5, %xmm5
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI0_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movl %ecx, %r10d
leaq (%rsi,%r10,4), %r9
leaq (%rdi,%r10,4), %r10
xorl %r11d, %r11d
movaps %xmm5, %xmm2
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r10,%r11,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss (%r9,%r11,4), %xmm3
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm2, %xmm2
movaps %xmm2, %xmm4
andps %xmm3, %xmm4
maxss %xmm5, %xmm3
andnps %xmm3, %xmm2
orps %xmm4, %xmm2
movaps %xmm2, %xmm5
incq %r11
cmpq %r11, %rax
jne .LBB0_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB0_3 Depth=1
incq %r8
addl %edx, %ecx
cmpq %rax, %r8
jne .LBB0_3
jmp .LBB0_6
.LBB0_1:
xorps %xmm5, %xmm5
.LBB0_6: # %._crit_edge23
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm5, 4(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm5, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI0_2(%rip), %xmm0
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmovneq %rax, %rdi
cmovpq %rax, %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z12checkResultsPfS_i, .Lfunc_end0-_Z12checkResultsPfS_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__dgemmPfS_S_i # -- Begin function _Z20__device_stub__dgemmPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__dgemmPfS_S_i,@function
_Z20__device_stub__dgemmPfS_S_i: # @_Z20__device_stub__dgemmPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5dgemmPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z20__device_stub__dgemmPfS_S_i, .Lfunc_end1-_Z20__device_stub__dgemmPfS_S_i
.cfi_endproc
# -- End function
.globl _Z9dgemm_cpuPfS_S_i # -- Begin function _Z9dgemm_cpuPfS_S_i
.p2align 4, 0x90
.type _Z9dgemm_cpuPfS_S_i,@function
_Z9dgemm_cpuPfS_S_i: # @_Z9dgemm_cpuPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_8
# %bb.1: # %.preheader26.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
movl %r9d, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
leaq (%rdx,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
xorps %xmm0, %xmm0
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r11,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12), %xmm1
addss %xmm1, %xmm0
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB2_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB2_3 Depth=2
movss %xmm0, (%rbx,%r15,4)
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB2_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB2_2 Depth=1
incq %r10
addl %ecx, %r9d
cmpq %rax, %r10
jne .LBB2_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB2_8: # %._crit_edge32
retq
.Lfunc_end2:
.size _Z9dgemm_cpuPfS_S_i, .Lfunc_end2-_Z9dgemm_cpuPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0xc0400000 # float -3
.LCPI3_3:
.long 0x40400000 # float 3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $256, %ebp # imm = 0x100
cmpl $2, %edi
jl .LBB3_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
.LBB3_2:
movl %ebp, %eax
imull %ebp, %eax
shll $2, %eax
leal 31(%rbp), %ecx
leal 62(%rbp), %ebx
testl %ecx, %ecx
cmovnsl %ecx, %ebx
movslq %eax, %r13
movq %r13, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, %r12
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, 8(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %r12, %r9
movq %rax, %r12
movl %ebp, %r13d
testl %ebp, %ebp
jle .LBB3_7
# %bb.3: # %.preheader.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
movl %eax, %edi
leaq (%r9,%rdi,4), %rdx
leaq (%r14,%rdi,4), %rsi
movq 40(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rdi,%r8,4) # imm = 0x40000000
movl $1073741824, (%rsi,%r8,4) # imm = 0x40000000
movl $1073741824, (%rdx,%r8,4) # imm = 0x40000000
incq %r8
cmpq %r8, %r13
jne .LBB3_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB3_4 Depth=1
incq %rcx
addl %ebp, %eax
cmpq %r13, %rcx
jne .LBB3_4
.LBB3_7: # %._crit_edge147
movq %r9, 56(%rsp) # 8-byte Spill
callq clock
movq %rax, 32(%rsp) # 8-byte Spill
testl %ebp, %ebp
jle .LBB3_21
# %bb.8: # %.preheader26.lr.ph.i
leaq (,%r13,4), %rax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_9: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
# Child Loop BB3_11 Depth 3
movl %ecx, %esi
movq 40(%rsp), %rdi # 8-byte Reload
leaq (%rdi,%rsi,4), %rsi
movq %rdx, %rdi
imulq %r13, %rdi
leaq (%r15,%rdi,4), %rdi
movq %r14, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_10: # %.preheader.i
# Parent Loop BB3_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_11 Depth 3
xorps %xmm0, %xmm0
movq %r8, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB3_11: # Parent Loop BB3_9 Depth=1
# Parent Loop BB3_10 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r11), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10), %xmm1
addss %xmm1, %xmm0
addq $4, %r11
addq %rax, %r10
cmpq %r11, %rax
jne .LBB3_11
# %bb.12: # %._crit_edge.i
# in Loop: Header=BB3_10 Depth=2
movss %xmm0, (%rdi,%r9,4)
incq %r9
addq $4, %r8
cmpq %r13, %r9
jne .LBB3_10
# %bb.13: # %._crit_edge30.i
# in Loop: Header=BB3_9 Depth=1
incq %rdx
addl %ebp, %ecx
cmpq %r13, %rdx
jne .LBB3_9
# %bb.14: # %_Z9dgemm_cpuPfS_S_i.exit
testl %ebp, %ebp
jle .LBB3_21
# %bb.15: # %.preheader26.lr.ph.i82
leaq (,%r13,4), %rax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_16: # %.preheader26.i84
# =>This Loop Header: Depth=1
# Child Loop BB3_17 Depth 2
# Child Loop BB3_18 Depth 3
movl %ecx, %esi
leaq (%r15,%rsi,4), %rsi
movq %rdx, %rdi
imulq %r13, %rdi
leaq (%r12,%rdi,4), %rdi
movq 56(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_17: # %.preheader.i87
# Parent Loop BB3_16 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_18 Depth 3
xorps %xmm0, %xmm0
movq %r8, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB3_18: # Parent Loop BB3_16 Depth=1
# Parent Loop BB3_17 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r11), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10), %xmm1
addss %xmm1, %xmm0
addq $4, %r11
addq %rax, %r10
cmpq %r11, %rax
jne .LBB3_18
# %bb.19: # %._crit_edge.i94
# in Loop: Header=BB3_17 Depth=2
movss %xmm0, (%rdi,%r9,4)
incq %r9
addq $4, %r8
cmpq %r13, %r9
jne .LBB3_17
# %bb.20: # %._crit_edge30.i97
# in Loop: Header=BB3_16 Depth=1
incq %rdx
addl %ebp, %ecx
cmpq %r13, %rdx
jne .LBB3_16
.LBB3_21: # %_Z9dgemm_cpuPfS_S_i.exit100
movq %r12, 24(%rsp) # 8-byte Spill
callq clock
subq 32(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
leaq 88(%rsp), %rdi
movq 8(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_22
.LBB3_23: # %_Z9checkCuda10hipError_t.exit
leaq 80(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_24
.LBB3_25: # %_Z9checkCuda10hipError_t.exit102
leaq 72(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_26
.LBB3_27: # %_Z9checkCuda10hipError_t.exit104
movq %r14, 32(%rsp) # 8-byte Spill
sarl $5, %ebx
leaq 168(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_28
.LBB3_29: # %_Z9checkCuda10hipError_t.exit106
leaq 64(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
movq %r12, %r14
jne .LBB3_30
.LBB3_31: # %_Z9checkCuda10hipError_t.exit108
movq %rbx, %r12
shlq $32, %r12
movq 88(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_32
.LBB3_33: # %_Z9checkCuda10hipError_t.exit110
orq %r12, %rbx
movq 80(%rsp), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_34
.LBB3_35: # %_Z9checkCuda10hipError_t.exit112
movabsq $137438953504, %r12 # imm = 0x2000000020
callq clock
movq %rax, 208(%rsp) # 8-byte Spill
movq %rbx, 48(%rsp) # 8-byte Spill
movq %rbx, %rdi
movq %r12, %rbx
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_37
# %bb.36:
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
movq 168(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
movl %ebp, 20(%rsp)
leaq 160(%rsp), %rax
movq %rax, 176(%rsp)
leaq 152(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 20(%rsp), %rax
movq %rax, 200(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z5dgemmPfS_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_37:
callq hipDeviceSynchronize
movq 72(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq 8(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
movq 32(%rsp), %r14 # 8-byte Reload
jne .LBB3_38
.LBB3_39: # %_Z9checkCuda10hipError_t.exit114
movq 48(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_41
# %bb.40:
movq 168(%rsp), %rax
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
movl %ebp, 20(%rsp)
leaq 160(%rsp), %rax
movq %rax, 176(%rsp)
leaq 152(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 20(%rsp), %rax
movq %rax, 200(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z5dgemmPfS_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_41:
callq hipDeviceSynchronize
callq clock
movq %rax, %r12
movq 64(%rsp), %rsi
movq %r15, %rdi
movq 8(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_42
.LBB3_43: # %_Z9checkCuda10hipError_t.exit122
subq 208(%rsp), %r12 # 8-byte Folded Reload
cvtsi2sd %r12, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
xorps %xmm5, %xmm5
testl %ebp, %ebp
jle .LBB3_44
# %bb.45: # %.preheader.lr.ph.i
xorl %eax, %eax
movss .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI3_2(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
xorl %ecx, %ecx
movq 24(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB3_46: # %.preheader.i123
# =>This Loop Header: Depth=1
# Child Loop BB3_47 Depth 2
movl %eax, %esi
leaq (%r15,%rsi,4), %rdx
leaq (%r12,%rsi,4), %rsi
xorl %edi, %edi
movaps %xmm5, %xmm2
.p2align 4, 0x90
.LBB3_47: # Parent Loop BB3_46 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%rdi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss (%rdx,%rdi,4), %xmm3
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm2, %xmm2
movaps %xmm2, %xmm4
andps %xmm3, %xmm4
maxss %xmm5, %xmm3
andnps %xmm3, %xmm2
orps %xmm4, %xmm2
movaps %xmm2, %xmm5
incq %rdi
cmpq %rdi, %r13
jne .LBB3_47
# %bb.48: # %._crit_edge.i128
# in Loop: Header=BB3_46 Depth=1
incq %rcx
addl %ebp, %eax
cmpq %r13, %rcx
jne .LBB3_46
jmp .LBB3_49
.LBB3_44:
movq 24(%rsp), %r12 # 8-byte Reload
.LBB3_49: # %._crit_edge23.i
movss %xmm5, 8(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm5, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI3_3(%rip), %xmm0
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmovneq %rax, %rdi
cmovpq %rax, %rdi
callq puts@PLT
movq 88(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_50
.LBB3_51: # %_Z9checkCuda10hipError_t.exit130
movq 80(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_52
.LBB3_53: # %_Z9checkCuda10hipError_t.exit132
movq 72(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_54
.LBB3_55: # %_Z9checkCuda10hipError_t.exit134
movq 64(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_56
.LBB3_57: # %_Z9checkCuda10hipError_t.exit136
movq 56(%rsp), %rdi # 8-byte Reload
callq free
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_22:
.cfi_def_cfa_offset 272
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 8(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_23
.LBB3_24:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 8(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_25
.LBB3_26:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 8(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_27
.LBB3_28:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 8(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_29
.LBB3_30:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_31
.LBB3_32:
movq stderr(%rip), %rcx
movq %rcx, 48(%rsp) # 8-byte Spill
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq 48(%rsp), %rdi # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_33
.LBB3_34:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_35
.LBB3_38:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_39
.LBB3_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_43
.LBB3_50:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 24(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_51
.LBB3_52:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 24(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_53
.LBB3_54:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 24(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_55
.LBB3_56:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 24(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_57
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5dgemmPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: %f \n"
.size .L.str, 16
.type _Z5dgemmPfS_S_i,@object # @_Z5dgemmPfS_S_i
.section .rodata,"a",@progbits
.globl _Z5dgemmPfS_S_i
.p2align 3, 0x0
_Z5dgemmPfS_S_i:
.quad _Z20__device_stub__dgemmPfS_S_i
.size _Z5dgemmPfS_S_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Time taken by Host: %.6fs\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time taken by GPU: %.6fs\n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CUDA Runtime Error: %s\n"
.size .L.str.5, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5dgemmPfS_S_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Successful results"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Unsuccessful results"
.size .Lstr.1, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__dgemmPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5dgemmPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5dgemmPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5dgemmPfS_S_i
.globl _Z5dgemmPfS_S_i
.p2align 8
.type _Z5dgemmPfS_S_i,@function
_Z5dgemmPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5dgemmPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5dgemmPfS_S_i, .Lfunc_end0-_Z5dgemmPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5dgemmPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5dgemmPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018f032_00000000-6_DoubleMulMat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9checkCuda9cudaError.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA Runtime Error: %s\n"
.section .text._Z9checkCuda9cudaError,"axG",@progbits,_Z9checkCuda9cudaError,comdat
.weak _Z9checkCuda9cudaError
.type _Z9checkCuda9cudaError, @function
_Z9checkCuda9cudaError:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
testl %edi, %edi
jne .L6
.L4:
movl %ebx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L4
.cfi_endproc
.LFE2057:
.size _Z9checkCuda9cudaError, .-_Z9checkCuda9cudaError
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Max error: %f \n"
.LC5:
.string "Unsuccessful results\n"
.LC6:
.string "Successful results\n"
.text
.globl _Z12checkResultsPfS_i
.type _Z12checkResultsPfS_i, @function
_Z12checkResultsPfS_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 28(%rsp)
testl %edx, %edx
jle .L8
movslq %edx, %r15
salq $2, %r15
leaq (%rdi,%r15), %r12
movl $0, %r13d
movl $0, %r14d
movl $0x00000000, 24(%rsp)
.L9:
movq 8(%rsp), %rax
leaq (%rax,%r13), %rbx
movq 16(%rsp), %rax
leaq (%rax,%r13), %rbp
.L10:
movss (%rbx), %xmm0
subss 0(%rbp), %xmm0
subss .LC2(%rip), %xmm0
andps .LC3(%rip), %xmm0
movss 24(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 24(%rsp)
addq $4, %rbx
addq $4, %rbp
cmpq %r12, %rbx
jne .L10
addl $1, %r14d
addq %r15, %r12
addq %r15, %r13
cmpl %r14d, 28(%rsp)
jne .L9
pxor %xmm0, %xmm0
cvtss2sd 24(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 24(%rsp), %xmm2
ucomiss .LC2(%rip), %xmm2
jp .L15
jne .L15
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L8:
pxor %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L15:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L7:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12checkResultsPfS_i, .-_Z12checkResultsPfS_i
.globl _Z9dgemm_cpuPfS_S_i
.type _Z9dgemm_cpuPfS_S_i, @function
_Z9dgemm_cpuPfS_S_i:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L26
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbx
movq %rdx, %r9
movl %ecx, %r12d
movslq %ecx, %r11
leaq 0(,%r11,4), %rcx
movq %rdi, %r10
leaq (%rdi,%rcx), %rsi
movl $0, %ebp
.L20:
movq %rbx, %r8
movl $0, %edi
.L23:
movq %r8, %rdx
movq %r10, %rax
pxor %xmm1, %xmm1
.L21:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rcx, %rdx
cmpq %rsi, %rax
jne .L21
movss %xmm1, (%r9,%rdi,4)
addq $1, %rdi
addq $4, %r8
cmpq %r11, %rdi
jne .L23
addl $1, %ebp
addq %rcx, %r9
addq %rcx, %r10
addq %rcx, %rsi
cmpl %ebp, %r12d
jne .L20
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2059:
.size _Z9dgemm_cpuPfS_S_i, .-_Z9dgemm_cpuPfS_S_i
.globl _Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i
.type _Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5dgemmPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i, .-_Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i
.globl _Z5dgemmPfS_S_i
.type _Z5dgemmPfS_S_i, @function
_Z5dgemmPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z5dgemmPfS_S_i, .-_Z5dgemmPfS_S_i
.section .rodata.str1.1
.LC10:
.string "Time taken by Host: %.6fs\n"
.LC11:
.string "Time taken by GPU: %.6fs\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $256, %r13d
cmpl $1, %edi
jg .L48
.L38:
movl $32, 80(%rsp)
movl $32, 84(%rsp)
movl $1, 88(%rsp)
leal 62(%r13), %eax
movl %r13d, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 92(%rsp)
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl %r13d, %r14d
imull %r13d, %r14d
sall $2, %r14d
movslq %r14d, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %r15
movq %r14, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %r13d, %r13d
jle .L39
movslq %r13d, %rsi
leaq 0(,%rsi,4), %rdi
negq %rsi
salq $2, %rsi
movq %rdi, %rdx
movl $0, %ecx
movss .LC8(%rip), %xmm0
.L40:
leaq (%rdx,%rsi), %rax
.L41:
movss %xmm0, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
movss %xmm0, (%r12,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L41
addl $1, %ecx
addq %rdi, %rdx
cmpl %ecx, %r13d
jne .L40
.L39:
call clock@PLT
movq %rax, 16(%rsp)
movl %r13d, %ecx
movq %r15, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z9dgemm_cpuPfS_S_i
movl %r13d, %ecx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq %r15, %rdi
call _Z9dgemm_cpuPfS_S_i
call clock@PLT
movq 16(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC9(%rip), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 72(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 64(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call clock@PLT
movq %rax, 16(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L42:
call cudaDeviceSynchronize@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L43:
call cudaDeviceSynchronize@PLT
call clock@PLT
movq %rax, 24(%rsp)
movl $2, %ecx
movq %r14, %rdx
movq 64(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC9(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %r13d, %edx
movq %r15, %rsi
movq 8(%rsp), %r14
movq %r14, %rdi
call _Z12checkResultsPfS_i
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
jmp .L38
.L49:
movl %r13d, %ecx
movq 72(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i
jmp .L42
.L50:
movl %r13d, %ecx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z29__device_stub__Z5dgemmPfS_S_iPfS_S_i
jmp .L43
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z5dgemmPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z5dgemmPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC8:
.long 1073741824
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "DoubleMulMat.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12checkResultsPfS_i
.LCPI0_0:
.long 0xc0400000 # float -3
.LCPI0_2:
.long 0x40400000 # float 3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z12checkResultsPfS_i
.p2align 4, 0x90
.type _Z12checkResultsPfS_i,@function
_Z12checkResultsPfS_i: # @_Z12checkResultsPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB0_1
# %bb.2: # %.preheader.lr.ph
movl %edx, %eax
xorps %xmm5, %xmm5
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI0_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movl %ecx, %r10d
leaq (%rsi,%r10,4), %r9
leaq (%rdi,%r10,4), %r10
xorl %r11d, %r11d
movaps %xmm5, %xmm2
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r10,%r11,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss (%r9,%r11,4), %xmm3
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm2, %xmm2
movaps %xmm2, %xmm4
andps %xmm3, %xmm4
maxss %xmm5, %xmm3
andnps %xmm3, %xmm2
orps %xmm4, %xmm2
movaps %xmm2, %xmm5
incq %r11
cmpq %r11, %rax
jne .LBB0_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB0_3 Depth=1
incq %r8
addl %edx, %ecx
cmpq %rax, %r8
jne .LBB0_3
jmp .LBB0_6
.LBB0_1:
xorps %xmm5, %xmm5
.LBB0_6: # %._crit_edge23
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm5, 4(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm5, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI0_2(%rip), %xmm0
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmovneq %rax, %rdi
cmovpq %rax, %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z12checkResultsPfS_i, .Lfunc_end0-_Z12checkResultsPfS_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__dgemmPfS_S_i # -- Begin function _Z20__device_stub__dgemmPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__dgemmPfS_S_i,@function
_Z20__device_stub__dgemmPfS_S_i: # @_Z20__device_stub__dgemmPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5dgemmPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z20__device_stub__dgemmPfS_S_i, .Lfunc_end1-_Z20__device_stub__dgemmPfS_S_i
.cfi_endproc
# -- End function
.globl _Z9dgemm_cpuPfS_S_i # -- Begin function _Z9dgemm_cpuPfS_S_i
.p2align 4, 0x90
.type _Z9dgemm_cpuPfS_S_i,@function
_Z9dgemm_cpuPfS_S_i: # @_Z9dgemm_cpuPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_8
# %bb.1: # %.preheader26.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
movl %r9d, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
leaq (%rdx,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
xorps %xmm0, %xmm0
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r11,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12), %xmm1
addss %xmm1, %xmm0
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB2_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB2_3 Depth=2
movss %xmm0, (%rbx,%r15,4)
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB2_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB2_2 Depth=1
incq %r10
addl %ecx, %r9d
cmpq %rax, %r10
jne .LBB2_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB2_8: # %._crit_edge32
retq
.Lfunc_end2:
.size _Z9dgemm_cpuPfS_S_i, .Lfunc_end2-_Z9dgemm_cpuPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0xc0400000 # float -3
.LCPI3_3:
.long 0x40400000 # float 3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $256, %ebp # imm = 0x100
cmpl $2, %edi
jl .LBB3_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
.LBB3_2:
movl %ebp, %eax
imull %ebp, %eax
shll $2, %eax
leal 31(%rbp), %ecx
leal 62(%rbp), %ebx
testl %ecx, %ecx
cmovnsl %ecx, %ebx
movslq %eax, %r13
movq %r13, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, %r12
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, 8(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %r12, %r9
movq %rax, %r12
movl %ebp, %r13d
testl %ebp, %ebp
jle .LBB3_7
# %bb.3: # %.preheader.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
movl %eax, %edi
leaq (%r9,%rdi,4), %rdx
leaq (%r14,%rdi,4), %rsi
movq 40(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rdi,%r8,4) # imm = 0x40000000
movl $1073741824, (%rsi,%r8,4) # imm = 0x40000000
movl $1073741824, (%rdx,%r8,4) # imm = 0x40000000
incq %r8
cmpq %r8, %r13
jne .LBB3_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB3_4 Depth=1
incq %rcx
addl %ebp, %eax
cmpq %r13, %rcx
jne .LBB3_4
.LBB3_7: # %._crit_edge147
movq %r9, 56(%rsp) # 8-byte Spill
callq clock
movq %rax, 32(%rsp) # 8-byte Spill
testl %ebp, %ebp
jle .LBB3_21
# %bb.8: # %.preheader26.lr.ph.i
leaq (,%r13,4), %rax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_9: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
# Child Loop BB3_11 Depth 3
movl %ecx, %esi
movq 40(%rsp), %rdi # 8-byte Reload
leaq (%rdi,%rsi,4), %rsi
movq %rdx, %rdi
imulq %r13, %rdi
leaq (%r15,%rdi,4), %rdi
movq %r14, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_10: # %.preheader.i
# Parent Loop BB3_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_11 Depth 3
xorps %xmm0, %xmm0
movq %r8, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB3_11: # Parent Loop BB3_9 Depth=1
# Parent Loop BB3_10 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r11), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10), %xmm1
addss %xmm1, %xmm0
addq $4, %r11
addq %rax, %r10
cmpq %r11, %rax
jne .LBB3_11
# %bb.12: # %._crit_edge.i
# in Loop: Header=BB3_10 Depth=2
movss %xmm0, (%rdi,%r9,4)
incq %r9
addq $4, %r8
cmpq %r13, %r9
jne .LBB3_10
# %bb.13: # %._crit_edge30.i
# in Loop: Header=BB3_9 Depth=1
incq %rdx
addl %ebp, %ecx
cmpq %r13, %rdx
jne .LBB3_9
# %bb.14: # %_Z9dgemm_cpuPfS_S_i.exit
testl %ebp, %ebp
jle .LBB3_21
# %bb.15: # %.preheader26.lr.ph.i82
leaq (,%r13,4), %rax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_16: # %.preheader26.i84
# =>This Loop Header: Depth=1
# Child Loop BB3_17 Depth 2
# Child Loop BB3_18 Depth 3
movl %ecx, %esi
leaq (%r15,%rsi,4), %rsi
movq %rdx, %rdi
imulq %r13, %rdi
leaq (%r12,%rdi,4), %rdi
movq 56(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_17: # %.preheader.i87
# Parent Loop BB3_16 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_18 Depth 3
xorps %xmm0, %xmm0
movq %r8, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB3_18: # Parent Loop BB3_16 Depth=1
# Parent Loop BB3_17 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r11), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10), %xmm1
addss %xmm1, %xmm0
addq $4, %r11
addq %rax, %r10
cmpq %r11, %rax
jne .LBB3_18
# %bb.19: # %._crit_edge.i94
# in Loop: Header=BB3_17 Depth=2
movss %xmm0, (%rdi,%r9,4)
incq %r9
addq $4, %r8
cmpq %r13, %r9
jne .LBB3_17
# %bb.20: # %._crit_edge30.i97
# in Loop: Header=BB3_16 Depth=1
incq %rdx
addl %ebp, %ecx
cmpq %r13, %rdx
jne .LBB3_16
.LBB3_21: # %_Z9dgemm_cpuPfS_S_i.exit100
movq %r12, 24(%rsp) # 8-byte Spill
callq clock
subq 32(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
leaq 88(%rsp), %rdi
movq 8(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_22
.LBB3_23: # %_Z9checkCuda10hipError_t.exit
leaq 80(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_24
.LBB3_25: # %_Z9checkCuda10hipError_t.exit102
leaq 72(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_26
.LBB3_27: # %_Z9checkCuda10hipError_t.exit104
movq %r14, 32(%rsp) # 8-byte Spill
sarl $5, %ebx
leaq 168(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_28
.LBB3_29: # %_Z9checkCuda10hipError_t.exit106
leaq 64(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
movq %r12, %r14
jne .LBB3_30
.LBB3_31: # %_Z9checkCuda10hipError_t.exit108
movq %rbx, %r12
shlq $32, %r12
movq 88(%rsp), %rdi
movq 40(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_32
.LBB3_33: # %_Z9checkCuda10hipError_t.exit110
orq %r12, %rbx
movq 80(%rsp), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_34
.LBB3_35: # %_Z9checkCuda10hipError_t.exit112
movabsq $137438953504, %r12 # imm = 0x2000000020
callq clock
movq %rax, 208(%rsp) # 8-byte Spill
movq %rbx, 48(%rsp) # 8-byte Spill
movq %rbx, %rdi
movq %r12, %rbx
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_37
# %bb.36:
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
movq 168(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
movl %ebp, 20(%rsp)
leaq 160(%rsp), %rax
movq %rax, 176(%rsp)
leaq 152(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 20(%rsp), %rax
movq %rax, 200(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z5dgemmPfS_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_37:
callq hipDeviceSynchronize
movq 72(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq 8(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
movq 32(%rsp), %r14 # 8-byte Reload
jne .LBB3_38
.LBB3_39: # %_Z9checkCuda10hipError_t.exit114
movq 48(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_41
# %bb.40:
movq 168(%rsp), %rax
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
movl %ebp, 20(%rsp)
leaq 160(%rsp), %rax
movq %rax, 176(%rsp)
leaq 152(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 20(%rsp), %rax
movq %rax, 200(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z5dgemmPfS_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_41:
callq hipDeviceSynchronize
callq clock
movq %rax, %r12
movq 64(%rsp), %rsi
movq %r15, %rdi
movq 8(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_42
.LBB3_43: # %_Z9checkCuda10hipError_t.exit122
subq 208(%rsp), %r12 # 8-byte Folded Reload
cvtsi2sd %r12, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
xorps %xmm5, %xmm5
testl %ebp, %ebp
jle .LBB3_44
# %bb.45: # %.preheader.lr.ph.i
xorl %eax, %eax
movss .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI3_2(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
xorl %ecx, %ecx
movq 24(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB3_46: # %.preheader.i123
# =>This Loop Header: Depth=1
# Child Loop BB3_47 Depth 2
movl %eax, %esi
leaq (%r15,%rsi,4), %rdx
leaq (%r12,%rsi,4), %rsi
xorl %edi, %edi
movaps %xmm5, %xmm2
.p2align 4, 0x90
.LBB3_47: # Parent Loop BB3_46 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%rdi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss (%rdx,%rdi,4), %xmm3
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm2, %xmm2
movaps %xmm2, %xmm4
andps %xmm3, %xmm4
maxss %xmm5, %xmm3
andnps %xmm3, %xmm2
orps %xmm4, %xmm2
movaps %xmm2, %xmm5
incq %rdi
cmpq %rdi, %r13
jne .LBB3_47
# %bb.48: # %._crit_edge.i128
# in Loop: Header=BB3_46 Depth=1
incq %rcx
addl %ebp, %eax
cmpq %r13, %rcx
jne .LBB3_46
jmp .LBB3_49
.LBB3_44:
movq 24(%rsp), %r12 # 8-byte Reload
.LBB3_49: # %._crit_edge23.i
movss %xmm5, 8(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm5, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI3_3(%rip), %xmm0
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmovneq %rax, %rdi
cmovpq %rax, %rdi
callq puts@PLT
movq 88(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_50
.LBB3_51: # %_Z9checkCuda10hipError_t.exit130
movq 80(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_52
.LBB3_53: # %_Z9checkCuda10hipError_t.exit132
movq 72(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_54
.LBB3_55: # %_Z9checkCuda10hipError_t.exit134
movq 64(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_56
.LBB3_57: # %_Z9checkCuda10hipError_t.exit136
movq 56(%rsp), %rdi # 8-byte Reload
callq free
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_22:
.cfi_def_cfa_offset 272
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 8(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_23
.LBB3_24:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 8(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_25
.LBB3_26:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 8(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_27
.LBB3_28:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 8(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_29
.LBB3_30:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_31
.LBB3_32:
movq stderr(%rip), %rcx
movq %rcx, 48(%rsp) # 8-byte Spill
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq 48(%rsp), %rdi # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_33
.LBB3_34:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_35
.LBB3_38:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_39
.LBB3_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_43
.LBB3_50:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 24(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_51
.LBB3_52:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 24(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_53
.LBB3_54:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 24(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_55
.LBB3_56:
movq stderr(%rip), %r12
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r12, %rdi
movq 24(%rsp), %r12 # 8-byte Reload
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB3_57
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5dgemmPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: %f \n"
.size .L.str, 16
.type _Z5dgemmPfS_S_i,@object # @_Z5dgemmPfS_S_i
.section .rodata,"a",@progbits
.globl _Z5dgemmPfS_S_i
.p2align 3, 0x0
_Z5dgemmPfS_S_i:
.quad _Z20__device_stub__dgemmPfS_S_i
.size _Z5dgemmPfS_S_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Time taken by Host: %.6fs\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time taken by GPU: %.6fs\n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CUDA Runtime Error: %s\n"
.size .L.str.5, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5dgemmPfS_S_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Successful results"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Unsuccessful results"
.size .Lstr.1, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__dgemmPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5dgemmPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
extern "C" {
__device__
static int THREADS_IN_BLOCK = 1024;
__device__
void min_max(int* tab, int for_min, int for_max, int size) {
if (for_min >= size || for_max >= size) {
return;
}
int min = tab[for_min];
int max = tab[for_max];
if (max < min) {
atomicExch(tab + for_max, min);
atomicExch(tab + for_min, max);
}
};
__global__
void bitonic_sort(int* to_sort, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x;
if (thid >= size) {
return;
}
int d_traingle;
int local_thid;
int opposite;
for (d_traingle = 2; d_traingle <= THREADS_IN_BLOCK; d_traingle*=2) {
local_thid = thid % d_traingle;
opposite = thid - local_thid + d_traingle - 1 - local_thid;
if (local_thid < d_traingle/2) {
min_max(to_sort, thid, opposite, size);
}
__syncthreads();
for (int d = d_traingle/2; d >= 2; d /= 2) {
local_thid = thid % d;
if (local_thid < d/2) {
opposite = thid + d/2;
min_max(to_sort, thid, opposite, size);
}
__syncthreads();
}
__syncthreads();
}
}
__global__
void bitonic_merge(int* to_sort, int d, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x*blockDim.x;
if (thid >= size) {
return;
}
int local_thid = thid % d;
int opposite = thid + d/2;
if (local_thid < d/2) {
min_max(to_sort, thid, opposite, size);
}
}
__global__
void bitonic_triangle_merge(int* to_sort, int d_traingle, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x*blockDim.x;
if (thid >= size) {
return;
}
int local_thid = thid % d_traingle;
int opposite = thid - local_thid + d_traingle - 1 - local_thid;
if (local_thid < d_traingle/2) {
min_max(to_sort, thid, opposite, size);
}
}
} | code for sm_80
Function : bitonic_triangle_merge
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IABS R6, c[0x0][0x168] ; /* 0x00005a0000067a13 */
/* 0x000fe20000000000 */
/*00b0*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fe20000000000 */
/*00d0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*00e0*/ I2F.RP R4, R6 ; /* 0x0000000600047306 */
/* 0x000e220000209400 */
/*00f0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f46270 */
/*0100*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fca0008011404 */
/*0110*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0140*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0150*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0160*/ IMAD R5, R5, R6, RZ ; /* 0x0000000605057224 */
/* 0x000fca00078e02ff */
/*0170*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0007 */
/*0190*/ IMAD.HI.U32 R3, R3, R5, RZ ; /* 0x0000000503037227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*01b0*/ IMAD R3, R6, R3, R5 ; /* 0x0000000306037224 */
/* 0x000fca00078e0205 */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f04070 */
/*01d0*/ @!P0 IADD3 R3, R3, -R6, RZ ; /* 0x8000000603038210 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05270 */
/*01f0*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f24070 */
/*0200*/ @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103039824 */
/* 0x000fca00078e0a06 */
/*0210*/ @!P2 IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff0303a210 */
/* 0x000fe40007ffe1ff */
/*0220*/ @!P0 LOP3.LUT R3, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff038a12 */
/* 0x000fc800078e33ff */
/*0230*/ LOP3.LUT R2, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff027212 */
/* 0x000fe400078e33ff */
/*0240*/ IADD3 R5, -R3, c[0x0][0x168], R0 ; /* 0x00005a0003057a10 */
/* 0x000fca0007ffe100 */
/*0250*/ IMAD.IADD R2, R2, 0x1, R5 ; /* 0x0000000102027824 */
/* 0x000fca00078e0205 */
/*0260*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fc80003f06270 */
/*0270*/ ISETP.GE.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fda0008706670 */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0290*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*02a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*02b0*/ IMAD.WIDE R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0203 */
/*02c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe400078e0203 */
/*02d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x004fda0003f06270 */
/*0300*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0310*/ ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R4.64], R7 ; /* 0x0000000704ff79a8 */
/* 0x000fe8000c1ee1c4 */
/*0320*/ ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64], R0 ; /* 0x0000000002ff79a8 */
/* 0x000fe2000c1ee1c4 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ BRA 0x340; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : bitonic_merge
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IABS R6, c[0x0][0x168] ; /* 0x00005a0000067a13 */
/* 0x000fe40000000000 */
/*00b0*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fe40000000000 */
/*00c0*/ I2F.RP R4, R6 ; /* 0x0000000600047306 */
/* 0x000e220000209400 */
/*00d0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R5, R5, R6, RZ ; /* 0x0000000605057224 */
/* 0x000fca00078e02ff */
/*0140*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0007 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.HI.U32 R3, R3, R5, RZ ; /* 0x0000000503037227 */
/* 0x000fc600078e00ff */
/*0180*/ LEA.HI R2, R2, c[0x0][0x168], RZ, 0x1 ; /* 0x00005a0002027a11 */
/* 0x000fe200078f08ff */
/*0190*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*01a0*/ IMAD R3, R6, R3, R5 ; /* 0x0000000306037224 */
/* 0x000fe200078e0205 */
/*01b0*/ SHF.R.S32.HI R5, RZ, 0x1, R2 ; /* 0x00000001ff057819 */
/* 0x000fc80000011402 */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe20003f04070 */
/*01d0*/ IMAD.IADD R2, R0, 0x1, R5 ; /* 0x0000000100027824 */
/* 0x000fd800078e0205 */
/*01e0*/ @!P0 IADD3 R3, R3, -R6, RZ ; /* 0x8000000603038210 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05270 */
/*0200*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f24070 */
/*0210*/ @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103039824 */
/* 0x000fca00078e0a06 */
/*0220*/ @!P2 IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff0303a210 */
/* 0x000fe40007ffe1ff */
/*0230*/ @!P0 LOP3.LUT R3, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff038a12 */
/* 0x000fc800078e33ff */
/*0240*/ ISETP.GE.AND P0, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x000fc80003f06270 */
/*0250*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x16c], P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0000706670 */
/*0260*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0270*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0280*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0290*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*02a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x000fca00078e0202 */
/*02c0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ ISETP.GE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x004fda0003f06270 */
/*02e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02f0*/ ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R4.64], R0 ; /* 0x0000000004ff79a8 */
/* 0x000fe8000c1ee1c4 */
/*0300*/ ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R2.64], R7 ; /* 0x0000000702ff79a8 */
/* 0x000fe2000c1ee1c4 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : bitonic_sort
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0070*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0080*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0205 */
/*00a0*/ IMAD R5, R4, c[0x0][0x4], R7 ; /* 0x0000010004057a24 */
/* 0x002fc800078e0207 */
/*00b0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ISETP.GE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fc80003f06270 */
/*00d0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], !P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0004706670 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0205 */
/*0120*/ IABS R10, R7.reuse ; /* 0x00000007000a7213 */
/* 0x081fe20000000000 */
/*0130*/ BSSY B0, 0x3b0 ; /* 0x0000027000007945 */
/* 0x000fe20003800000 */
/*0140*/ IABS R12, R7 ; /* 0x00000007000c7213 */
/* 0x000fe40000000000 */
/*0150*/ I2F.RP R6, R10 ; /* 0x0000000a00067306 */
/* 0x000e220000209400 */
/*0160*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f26270 */
/*0170*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fca00078e0a0c */
/*0180*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0190*/ IADD3 R8, R6, 0xffffffe, RZ ; /* 0x0ffffffe06087810 */
/* 0x001fe40007ffe0ff */
/*01a0*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc80000000000 */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*01c0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe200078e00ff */
/*01d0*/ IADD3 R11, RZ, -R9, RZ ; /* 0x80000009ff0b7210 */
/* 0x002fca0007ffe0ff */
/*01e0*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*01f0*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fc800078e0008 */
/*0200*/ IMAD.MOV.U32 R11, RZ, RZ, R12 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000c */
/*0210*/ IMAD.HI.U32 R9, R9, R6, RZ ; /* 0x0000000609097227 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD R9, R9, R11, R6 ; /* 0x0000000b09097224 */
/* 0x000fca00078e0206 */
/*0230*/ ISETP.GT.U32.AND P0, PT, R10, R9, PT ; /* 0x000000090a00720c */
/* 0x000fda0003f04070 */
/*0240*/ @!P0 IMAD.IADD R9, R9, 0x1, -R10 ; /* 0x0000000109098824 */
/* 0x000fe200078e0a0a */
/*0250*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*0260*/ ISETP.GT.U32.AND P2, PT, R10, R9, PT ; /* 0x000000090a00720c */
/* 0x000fda0003f44070 */
/*0270*/ @!P2 IADD3 R9, R9, -R10, RZ ; /* 0x8000000a0909a210 */
/* 0x000fca0007ffe0ff */
/*0280*/ IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0009 */
/*0290*/ @!P1 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0a08 */
/*02a0*/ @!P0 LOP3.LUT R8, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff088212 */
/* 0x000fc800078e33ff */
/*02b0*/ LOP3.LUT R9, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff097212 */
/* 0x000fe400078e33ff */
/*02c0*/ IADD3 R10, -R8, R7, R0 ; /* 0x00000007080a7210 */
/* 0x000fca0007ffe100 */
/*02d0*/ IMAD.IADD R10, R9, 0x1, R10 ; /* 0x00000001090a7824 */
/* 0x000fe200078e020a */
/*02e0*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fc80000011607 */
/*02f0*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x168], PT ; /* 0x00005a000a007a0c */
/* 0x000fc80003f06270 */
/*0300*/ ISETP.GE.OR P0, PT, R8, R9, P0 ; /* 0x000000090800720c */
/* 0x000fda0000706670 */
/*0310*/ @P0 BRA 0x3a0 ; /* 0x0000008000000947 */
/* 0x020fea0003800000 */
/*0320*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0330*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000eb2000c1e1900 */
/*0340*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e020b */
/*0350*/ LDG.E R8, [R10.64] ; /* 0x000000040a087981 */
/* 0x000ea4000c1e1900 */
/*0360*/ ISETP.GE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x004fda0003f06270 */
/*0370*/ @P0 BRA 0x3a0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0380*/ ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R10.64], R13 ; /* 0x0000000d0aff79a8 */
/* 0x000168000c1ee1c4 */
/*0390*/ ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R4.64], R8 ; /* 0x0000000804ff79a8 */
/* 0x000164000c1ee1c4 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03c0*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fda0003f06070 */
/*03d0*/ @!P0 BRA 0x660 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.MOV.U32 R8, RZ, RZ, R9.reuse ; /* 0x000000ffff087224 */
/* 0x101fe200078e0009 */
/*03f0*/ IABS R16, R0 ; /* 0x0000000000107213 */
/* 0x000fe20000000000 */
/*0400*/ BSSY B0, 0x630 ; /* 0x0000022000007945 */
/* 0x000fe20003800000 */
/*0410*/ SHF.R.U32.HI R9, RZ, 0x1, R9 ; /* 0x00000001ff097819 */
/* 0x000fe40000011609 */
/*0420*/ IABS R14, R8.reuse ; /* 0x00000008000e7213 */
/* 0x080fe40000000000 */
/*0430*/ IABS R15, R8 ; /* 0x00000008000f7213 */
/* 0x000fe40000000000 */
/*0440*/ I2F.RP R12, R14 ; /* 0x0000000e000c7306 */
/* 0x000e300000209400 */
/*0450*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e240000001000 */
/*0460*/ IADD3 R10, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c0a7810 */
/* 0x001fc40007ffe0ff */
/*0470*/ IADD3 R12, RZ, -R15, RZ ; /* 0x8000000fff0c7210 */
/* 0x000fc80007ffe0ff */
/*0480*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x000064000021f000 */
/*0490*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e00ff */
/*04a0*/ IMAD.MOV R13, RZ, RZ, -R11 ; /* 0x000000ffff0d7224 */
/* 0x002fc800078e0a0b */
/*04b0*/ IMAD R13, R13, R14, RZ ; /* 0x0000000e0d0d7224 */
/* 0x000fc800078e02ff */
/*04c0*/ IMAD.HI.U32 R11, R11, R13, R10 ; /* 0x0000000d0b0b7227 */
/* 0x000fc800078e000a */
/*04d0*/ IMAD.MOV.U32 R13, RZ, RZ, R16 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0010 */
/*04e0*/ IMAD.HI.U32 R11, R11, R6, RZ ; /* 0x000000060b0b7227 */
/* 0x000fc800078e00ff */
/*04f0*/ IMAD R11, R11, R12, R13 ; /* 0x0000000c0b0b7224 */
/* 0x000fe400078e020d */
/*0500*/ IMAD.IADD R10, R0, 0x1, R9 ; /* 0x00000001000a7824 */
/* 0x000fc600078e0209 */
/*0510*/ ISETP.GT.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x000fda0003f04070 */
/*0520*/ @!P0 IMAD.IADD R11, R11, 0x1, -R14 ; /* 0x000000010b0b8824 */
/* 0x000fe200078e0a0e */
/*0530*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05270 */
/*0540*/ ISETP.GT.U32.AND P2, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x000fda0003f44070 */
/*0550*/ @!P2 IMAD.IADD R11, R11, 0x1, -R14 ; /* 0x000000010b0ba824 */
/* 0x000fca00078e0a0e */
/*0560*/ @!P1 IADD3 R11, -R11, RZ, RZ ; /* 0x000000ff0b0b9210 */
/* 0x000fe40007ffe1ff */
/*0570*/ @!P0 LOP3.LUT R11, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff0b8212 */
/* 0x000fc800078e33ff */
/*0580*/ ISETP.GE.AND P0, PT, R11, R9, PT ; /* 0x000000090b00720c */
/* 0x000fc80003f06270 */
/*0590*/ ISETP.GE.OR P0, PT, R10, c[0x0][0x168], P0 ; /* 0x00005a000a007a0c */
/* 0x000fda0000706670 */
/*05a0*/ @P0 BRA 0x620 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*05b0*/ IMAD.WIDE.U32 R10, R9, 0x4, R4 ; /* 0x00000004090a7825 */
/* 0x000fe200078e0004 */
/*05c0*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ ISETP.GE.AND P0, PT, R12, R13, PT ; /* 0x0000000d0c00720c */
/* 0x004fda0003f06270 */
/*05f0*/ @P0 BRA 0x620 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0600*/ ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R10.64], R13 ; /* 0x0000000d0aff79a8 */
/* 0x000168000c1ee1c4 */
/*0610*/ ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R4.64], R12 ; /* 0x0000000c04ff79a8 */
/* 0x000164000c1ee1c4 */
/*0620*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0640*/ ISETP.GT.U32.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fda0003f04070 */
/*0650*/ @P0 BRA 0x3e0 ; /* 0xfffffd8000000947 */
/* 0x000fea000383ffff */
/*0660*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0670*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0680*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fca00078e00ff */
/*0690*/ ISETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x004fda0003f04270 */
/*06a0*/ @!P0 BRA 0x120 ; /* 0xfffffa7000008947 */
/* 0x000fea000383ffff */
/*06b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06c0*/ BRA 0x6c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
extern "C" {
__device__
static int THREADS_IN_BLOCK = 1024;
__device__
void min_max(int* tab, int for_min, int for_max, int size) {
if (for_min >= size || for_max >= size) {
return;
}
int min = tab[for_min];
int max = tab[for_max];
if (max < min) {
atomicExch(tab + for_max, min);
atomicExch(tab + for_min, max);
}
};
__global__
void bitonic_sort(int* to_sort, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x;
if (thid >= size) {
return;
}
int d_traingle;
int local_thid;
int opposite;
for (d_traingle = 2; d_traingle <= THREADS_IN_BLOCK; d_traingle*=2) {
local_thid = thid % d_traingle;
opposite = thid - local_thid + d_traingle - 1 - local_thid;
if (local_thid < d_traingle/2) {
min_max(to_sort, thid, opposite, size);
}
__syncthreads();
for (int d = d_traingle/2; d >= 2; d /= 2) {
local_thid = thid % d;
if (local_thid < d/2) {
opposite = thid + d/2;
min_max(to_sort, thid, opposite, size);
}
__syncthreads();
}
__syncthreads();
}
}
__global__
void bitonic_merge(int* to_sort, int d, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x*blockDim.x;
if (thid >= size) {
return;
}
int local_thid = thid % d;
int opposite = thid + d/2;
if (local_thid < d/2) {
min_max(to_sort, thid, opposite, size);
}
}
__global__
void bitonic_triangle_merge(int* to_sort, int d_traingle, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x*blockDim.x;
if (thid >= size) {
return;
}
int local_thid = thid % d_traingle;
int opposite = thid - local_thid + d_traingle - 1 - local_thid;
if (local_thid < d_traingle/2) {
min_max(to_sort, thid, opposite, size);
}
}
} | .file "tmpxft_001aa198_00000000-6_bitonic_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl min_max
.type min_max, @function
min_max:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size min_max, .-min_max
.globl _Z33__device_stub__Z12bitonic_sortPiiPii
.type _Z33__device_stub__Z12bitonic_sortPiiPii, @function
_Z33__device_stub__Z12bitonic_sortPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq bitonic_sort(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z12bitonic_sortPiiPii, .-_Z33__device_stub__Z12bitonic_sortPiiPii
.globl bitonic_sort
.type bitonic_sort, @function
bitonic_sort:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12bitonic_sortPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size bitonic_sort, .-bitonic_sort
.globl _Z35__device_stub__Z13bitonic_mergePiiiPiii
.type _Z35__device_stub__Z13bitonic_mergePiiiPiii, @function
_Z35__device_stub__Z13bitonic_mergePiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq bitonic_merge(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z13bitonic_mergePiiiPiii, .-_Z35__device_stub__Z13bitonic_mergePiiiPiii
.globl bitonic_merge
.type bitonic_merge, @function
bitonic_merge:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13bitonic_mergePiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size bitonic_merge, .-bitonic_merge
.globl _Z44__device_stub__Z22bitonic_triangle_mergePiiiPiii
.type _Z44__device_stub__Z22bitonic_triangle_mergePiiiPiii, @function
_Z44__device_stub__Z22bitonic_triangle_mergePiiiPiii:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq bitonic_triangle_merge(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z44__device_stub__Z22bitonic_triangle_mergePiiiPiii, .-_Z44__device_stub__Z22bitonic_triangle_mergePiiiPiii
.globl bitonic_triangle_merge
.type bitonic_triangle_merge, @function
bitonic_triangle_merge:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z22bitonic_triangle_mergePiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size bitonic_triangle_merge, .-bitonic_triangle_merge
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "bitonic_triangle_merge"
.LC1:
.string "bitonic_merge"
.LC2:
.string "bitonic_sort"
.LC3:
.string "THREADS_IN_BLOCK"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq bitonic_triangle_merge(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq bitonic_merge(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq bitonic_sort(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16THREADS_IN_BLOCK(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL16THREADS_IN_BLOCK
.comm _ZL16THREADS_IN_BLOCK,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
extern "C" {
__device__
static int THREADS_IN_BLOCK = 1024;
__device__
void min_max(int* tab, int for_min, int for_max, int size) {
if (for_min >= size || for_max >= size) {
return;
}
int min = tab[for_min];
int max = tab[for_max];
if (max < min) {
atomicExch(tab + for_max, min);
atomicExch(tab + for_min, max);
}
};
__global__
void bitonic_sort(int* to_sort, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x;
if (thid >= size) {
return;
}
int d_traingle;
int local_thid;
int opposite;
for (d_traingle = 2; d_traingle <= THREADS_IN_BLOCK; d_traingle*=2) {
local_thid = thid % d_traingle;
opposite = thid - local_thid + d_traingle - 1 - local_thid;
if (local_thid < d_traingle/2) {
min_max(to_sort, thid, opposite, size);
}
__syncthreads();
for (int d = d_traingle/2; d >= 2; d /= 2) {
local_thid = thid % d;
if (local_thid < d/2) {
opposite = thid + d/2;
min_max(to_sort, thid, opposite, size);
}
__syncthreads();
}
__syncthreads();
}
}
__global__
void bitonic_merge(int* to_sort, int d, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x*blockDim.x;
if (thid >= size) {
return;
}
int local_thid = thid % d;
int opposite = thid + d/2;
if (local_thid < d/2) {
min_max(to_sort, thid, opposite, size);
}
}
__global__
void bitonic_triangle_merge(int* to_sort, int d_traingle, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x*blockDim.x;
if (thid >= size) {
return;
}
int local_thid = thid % d_traingle;
int opposite = thid - local_thid + d_traingle - 1 - local_thid;
if (local_thid < d_traingle/2) {
min_max(to_sort, thid, opposite, size);
}
}
} | #include <hip/hip_runtime.h>
#include <cstdio>
extern "C" {
__device__
static int THREADS_IN_BLOCK = 1024;
__device__
void min_max(int* tab, int for_min, int for_max, int size) {
if (for_min >= size || for_max >= size) {
return;
}
int min = tab[for_min];
int max = tab[for_max];
if (max < min) {
atomicExch(tab + for_max, min);
atomicExch(tab + for_min, max);
}
};
__global__
void bitonic_sort(int* to_sort, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x;
if (thid >= size) {
return;
}
int d_traingle;
int local_thid;
int opposite;
for (d_traingle = 2; d_traingle <= THREADS_IN_BLOCK; d_traingle*=2) {
local_thid = thid % d_traingle;
opposite = thid - local_thid + d_traingle - 1 - local_thid;
if (local_thid < d_traingle/2) {
min_max(to_sort, thid, opposite, size);
}
__syncthreads();
for (int d = d_traingle/2; d >= 2; d /= 2) {
local_thid = thid % d;
if (local_thid < d/2) {
opposite = thid + d/2;
min_max(to_sort, thid, opposite, size);
}
__syncthreads();
}
__syncthreads();
}
}
__global__
void bitonic_merge(int* to_sort, int d, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x*blockDim.x;
if (thid >= size) {
return;
}
int local_thid = thid % d;
int opposite = thid + d/2;
if (local_thid < d/2) {
min_max(to_sort, thid, opposite, size);
}
}
__global__
void bitonic_triangle_merge(int* to_sort, int d_traingle, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x*blockDim.x;
if (thid >= size) {
return;
}
int local_thid = thid % d_traingle;
int opposite = thid - local_thid + d_traingle - 1 - local_thid;
if (local_thid < d_traingle/2) {
min_max(to_sort, thid, opposite, size);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
extern "C" {
__device__
static int THREADS_IN_BLOCK = 1024;
__device__
void min_max(int* tab, int for_min, int for_max, int size) {
if (for_min >= size || for_max >= size) {
return;
}
int min = tab[for_min];
int max = tab[for_max];
if (max < min) {
atomicExch(tab + for_max, min);
atomicExch(tab + for_min, max);
}
};
__global__
void bitonic_sort(int* to_sort, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x;
if (thid >= size) {
return;
}
int d_traingle;
int local_thid;
int opposite;
for (d_traingle = 2; d_traingle <= THREADS_IN_BLOCK; d_traingle*=2) {
local_thid = thid % d_traingle;
opposite = thid - local_thid + d_traingle - 1 - local_thid;
if (local_thid < d_traingle/2) {
min_max(to_sort, thid, opposite, size);
}
__syncthreads();
for (int d = d_traingle/2; d >= 2; d /= 2) {
local_thid = thid % d;
if (local_thid < d/2) {
opposite = thid + d/2;
min_max(to_sort, thid, opposite, size);
}
__syncthreads();
}
__syncthreads();
}
}
__global__
void bitonic_merge(int* to_sort, int d, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x*blockDim.x;
if (thid >= size) {
return;
}
int local_thid = thid % d;
int opposite = thid + d/2;
if (local_thid < d/2) {
min_max(to_sort, thid, opposite, size);
}
}
__global__
void bitonic_triangle_merge(int* to_sort, int d_traingle, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x*blockDim.x;
if (thid >= size) {
return;
}
int local_thid = thid % d_traingle;
int opposite = thid - local_thid + d_traingle - 1 - local_thid;
if (local_thid < d_traingle/2) {
min_max(to_sort, thid, opposite, size);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected bitonic_sort
.globl bitonic_sort
.p2align 8
.type bitonic_sort,@function
bitonic_sort:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b32 s4, s[0:1], 0x8
s_mul_i32 s14, s14, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s14, v0, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_14
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v5, 31, v0
s_mov_b32 s1, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v3, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v6, v3, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s0, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s3, v2, s0
s_branch .LBB0_3
.LBB0_2:
s_lshl_b32 s0, s1, 1
s_cmpk_gt_u32 s1, 0x200
s_mov_b32 s1, s0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
.LBB0_3:
s_ashr_i32 s0, s1, 31
s_mov_b32 s6, exec_lo
s_add_i32 s5, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s0
v_cvt_f32_u32_e32 v3, s5
s_sub_i32 s0, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s0, v3
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_mul_hi_u32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, s5
v_sub_nc_u32_e32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v4, s5, v3
v_cmp_le_u32_e64 s0, s5, v3
v_cndmask_b32_e64 v3, v3, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v4, s5, v3
v_cmp_le_u32_e64 s0, s5, v3
s_lshr_b32 s5, s1, 1
v_cndmask_b32_e64 v3, v3, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v3, v5
v_sub_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v3
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v4, s1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v4, v3
v_xad_u32 v3, v3, -1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s4, v3
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_clause 0x1
global_load_b32 v7, v[1:2], off
global_load_b32 v8, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s0, v8, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s0
s_clause 0x1
global_atomic_swap_b32 v[3:4], v7, off
global_atomic_swap_b32 v[1:2], v8, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lt_u32 s1, 3
s_waitcnt_vscnt null, 0x0
s_branch .LBB0_9
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt_vscnt null, 0x0
s_cmp_lt_u32 s6, 4
.LBB0_9:
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_2
s_mov_b32 s6, s5
s_sub_i32 s0, 0, s5
v_cvt_f32_u32_e32 v3, s6
s_lshr_b32 s5, s5, 1
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s0, v3
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_mul_hi_u32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, s6
v_sub_nc_u32_e32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v4, s6, v3
v_cmp_le_u32_e64 s0, s6, v3
v_cndmask_b32_e64 v3, v3, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v4, s6, v3
v_cmp_le_u32_e64 s0, s6, v3
v_cndmask_b32_e64 v3, v3, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v3, v5
v_sub_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v3
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v3, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s4, v3
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_clause 0x1
global_load_b32 v7, v[1:2], off
global_load_b32 v8, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s0, v8, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_8
s_clause 0x1
global_atomic_swap_b32 v[3:4], v7, off
global_atomic_swap_b32 v[1:2], v8, off
s_branch .LBB0_8
.LBB0_14:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel bitonic_sort
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size bitonic_sort, .Lfunc_end0-bitonic_sort
.section .AMDGPU.csdata,"",@progbits
.text
.protected bitonic_merge
.globl bitonic_merge
.p2align 8
.type bitonic_merge,@function
bitonic_merge:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0xc
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB1_5
s_load_b32 s3, s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v0, v3
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s3, s4
s_xor_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s5, 0, s4
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v4, v1
v_mul_lo_u32 v1, v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v4, v1
v_subrev_nc_u32_e32 v2, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_subrev_nc_u32_e32 v2, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_lshr_b32 s4, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s3, s3, s4
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v3
v_sub_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_5
v_add_nc_u32_e32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_5
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_clause 0x1
global_atomic_swap_b32 v[2:3], v4, off
global_atomic_swap_b32 v[0:1], v5, off
.LBB1_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel bitonic_merge
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size bitonic_merge, .Lfunc_end1-bitonic_merge
.section .AMDGPU.csdata,"",@progbits
.text
.protected bitonic_triangle_merge
.globl bitonic_triangle_merge
.p2align 8
.type bitonic_triangle_merge,@function
bitonic_triangle_merge:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0xc
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB2_5
s_load_b32 s3, s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v0, v3
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s3, s4
s_xor_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s5, 0, s4
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v4, v1
v_mul_lo_u32 v1, v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v4, v1
v_subrev_nc_u32_e32 v2, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_subrev_nc_u32_e32 v2, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_lshr_b32 s4, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s4, s3, s4
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
s_ashr_i32 s4, s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v3
v_sub_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_5
v_add_nc_u32_e32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v1
v_xad_u32 v2, v1, -1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_5
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_clause 0x1
global_atomic_swap_b32 v[2:3], v4, off
global_atomic_swap_b32 v[0:1], v5, off
.LBB2_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel bitonic_triangle_merge
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size bitonic_triangle_merge, .Lfunc_end2-bitonic_triangle_merge
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: bitonic_sort
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: bitonic_sort.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: bitonic_merge
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: bitonic_merge.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: bitonic_triangle_merge
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: bitonic_triangle_merge.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
extern "C" {
__device__
static int THREADS_IN_BLOCK = 1024;
__device__
void min_max(int* tab, int for_min, int for_max, int size) {
if (for_min >= size || for_max >= size) {
return;
}
int min = tab[for_min];
int max = tab[for_max];
if (max < min) {
atomicExch(tab + for_max, min);
atomicExch(tab + for_min, max);
}
};
__global__
void bitonic_sort(int* to_sort, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x;
if (thid >= size) {
return;
}
int d_traingle;
int local_thid;
int opposite;
for (d_traingle = 2; d_traingle <= THREADS_IN_BLOCK; d_traingle*=2) {
local_thid = thid % d_traingle;
opposite = thid - local_thid + d_traingle - 1 - local_thid;
if (local_thid < d_traingle/2) {
min_max(to_sort, thid, opposite, size);
}
__syncthreads();
for (int d = d_traingle/2; d >= 2; d /= 2) {
local_thid = thid % d;
if (local_thid < d/2) {
opposite = thid + d/2;
min_max(to_sort, thid, opposite, size);
}
__syncthreads();
}
__syncthreads();
}
}
__global__
void bitonic_merge(int* to_sort, int d, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x*blockDim.x;
if (thid >= size) {
return;
}
int local_thid = thid % d;
int opposite = thid + d/2;
if (local_thid < d/2) {
min_max(to_sort, thid, opposite, size);
}
}
__global__
void bitonic_triangle_merge(int* to_sort, int d_traingle, int size) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int thid = x + y*gridDim.x*blockDim.x;
if (thid >= size) {
return;
}
int local_thid = thid % d_traingle;
int opposite = thid - local_thid + d_traingle - 1 - local_thid;
if (local_thid < d_traingle/2) {
min_max(to_sort, thid, opposite, size);
}
}
} | .text
.file "bitonic_sort.hip"
.globl __device_stub__bitonic_sort # -- Begin function __device_stub__bitonic_sort
.p2align 4, 0x90
.type __device_stub__bitonic_sort,@function
__device_stub__bitonic_sort: # @__device_stub__bitonic_sort
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $bitonic_sort, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__bitonic_sort, .Lfunc_end0-__device_stub__bitonic_sort
.cfi_endproc
# -- End function
.globl __device_stub__bitonic_merge # -- Begin function __device_stub__bitonic_merge
.p2align 4, 0x90
.type __device_stub__bitonic_merge,@function
__device_stub__bitonic_merge: # @__device_stub__bitonic_merge
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $bitonic_merge, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size __device_stub__bitonic_merge, .Lfunc_end1-__device_stub__bitonic_merge
.cfi_endproc
# -- End function
.globl __device_stub__bitonic_triangle_merge # -- Begin function __device_stub__bitonic_triangle_merge
.p2align 4, 0x90
.type __device_stub__bitonic_triangle_merge,@function
__device_stub__bitonic_triangle_merge: # @__device_stub__bitonic_triangle_merge
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $bitonic_triangle_merge, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__bitonic_triangle_merge, .Lfunc_end2-__device_stub__bitonic_triangle_merge
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $bitonic_sort, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $bitonic_merge, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $bitonic_triangle_merge, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type bitonic_sort,@object # @bitonic_sort
.section .rodata,"a",@progbits
.globl bitonic_sort
.p2align 3, 0x0
bitonic_sort:
.quad __device_stub__bitonic_sort
.size bitonic_sort, 8
.type bitonic_merge,@object # @bitonic_merge
.globl bitonic_merge
.p2align 3, 0x0
bitonic_merge:
.quad __device_stub__bitonic_merge
.size bitonic_merge, 8
.type bitonic_triangle_merge,@object # @bitonic_triangle_merge
.globl bitonic_triangle_merge
.p2align 3, 0x0
bitonic_triangle_merge:
.quad __device_stub__bitonic_triangle_merge
.size bitonic_triangle_merge, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "bitonic_sort"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "bitonic_merge"
.size .L__unnamed_2, 14
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "bitonic_triangle_merge"
.size .L__unnamed_3, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__bitonic_sort
.addrsig_sym __device_stub__bitonic_merge
.addrsig_sym __device_stub__bitonic_triangle_merge
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym bitonic_sort
.addrsig_sym bitonic_merge
.addrsig_sym bitonic_triangle_merge
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aa198_00000000-6_bitonic_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl min_max
.type min_max, @function
min_max:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size min_max, .-min_max
.globl _Z33__device_stub__Z12bitonic_sortPiiPii
.type _Z33__device_stub__Z12bitonic_sortPiiPii, @function
_Z33__device_stub__Z12bitonic_sortPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq bitonic_sort(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z12bitonic_sortPiiPii, .-_Z33__device_stub__Z12bitonic_sortPiiPii
.globl bitonic_sort
.type bitonic_sort, @function
bitonic_sort:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12bitonic_sortPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size bitonic_sort, .-bitonic_sort
.globl _Z35__device_stub__Z13bitonic_mergePiiiPiii
.type _Z35__device_stub__Z13bitonic_mergePiiiPiii, @function
_Z35__device_stub__Z13bitonic_mergePiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq bitonic_merge(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z13bitonic_mergePiiiPiii, .-_Z35__device_stub__Z13bitonic_mergePiiiPiii
.globl bitonic_merge
.type bitonic_merge, @function
bitonic_merge:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13bitonic_mergePiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size bitonic_merge, .-bitonic_merge
.globl _Z44__device_stub__Z22bitonic_triangle_mergePiiiPiii
.type _Z44__device_stub__Z22bitonic_triangle_mergePiiiPiii, @function
_Z44__device_stub__Z22bitonic_triangle_mergePiiiPiii:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq bitonic_triangle_merge(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z44__device_stub__Z22bitonic_triangle_mergePiiiPiii, .-_Z44__device_stub__Z22bitonic_triangle_mergePiiiPiii
.globl bitonic_triangle_merge
.type bitonic_triangle_merge, @function
bitonic_triangle_merge:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z22bitonic_triangle_mergePiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size bitonic_triangle_merge, .-bitonic_triangle_merge
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "bitonic_triangle_merge"
.LC1:
.string "bitonic_merge"
.LC2:
.string "bitonic_sort"
.LC3:
.string "THREADS_IN_BLOCK"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq bitonic_triangle_merge(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq bitonic_merge(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq bitonic_sort(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16THREADS_IN_BLOCK(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL16THREADS_IN_BLOCK
.comm _ZL16THREADS_IN_BLOCK,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bitonic_sort.hip"
.globl __device_stub__bitonic_sort # -- Begin function __device_stub__bitonic_sort
.p2align 4, 0x90
.type __device_stub__bitonic_sort,@function
__device_stub__bitonic_sort: # @__device_stub__bitonic_sort
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $bitonic_sort, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__bitonic_sort, .Lfunc_end0-__device_stub__bitonic_sort
.cfi_endproc
# -- End function
.globl __device_stub__bitonic_merge # -- Begin function __device_stub__bitonic_merge
.p2align 4, 0x90
.type __device_stub__bitonic_merge,@function
__device_stub__bitonic_merge: # @__device_stub__bitonic_merge
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $bitonic_merge, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size __device_stub__bitonic_merge, .Lfunc_end1-__device_stub__bitonic_merge
.cfi_endproc
# -- End function
.globl __device_stub__bitonic_triangle_merge # -- Begin function __device_stub__bitonic_triangle_merge
.p2align 4, 0x90
.type __device_stub__bitonic_triangle_merge,@function
__device_stub__bitonic_triangle_merge: # @__device_stub__bitonic_triangle_merge
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $bitonic_triangle_merge, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__bitonic_triangle_merge, .Lfunc_end2-__device_stub__bitonic_triangle_merge
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $bitonic_sort, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $bitonic_merge, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $bitonic_triangle_merge, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type bitonic_sort,@object # @bitonic_sort
.section .rodata,"a",@progbits
.globl bitonic_sort
.p2align 3, 0x0
bitonic_sort:
.quad __device_stub__bitonic_sort
.size bitonic_sort, 8
.type bitonic_merge,@object # @bitonic_merge
.globl bitonic_merge
.p2align 3, 0x0
bitonic_merge:
.quad __device_stub__bitonic_merge
.size bitonic_merge, 8
.type bitonic_triangle_merge,@object # @bitonic_triangle_merge
.globl bitonic_triangle_merge
.p2align 3, 0x0
bitonic_triangle_merge:
.quad __device_stub__bitonic_triangle_merge
.size bitonic_triangle_merge, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "bitonic_sort"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "bitonic_merge"
.size .L__unnamed_2, 14
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "bitonic_triangle_merge"
.size .L__unnamed_3, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__bitonic_sort
.addrsig_sym __device_stub__bitonic_merge
.addrsig_sym __device_stub__bitonic_triangle_merge
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym bitonic_sort
.addrsig_sym bitonic_merge
.addrsig_sym bitonic_triangle_merge
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void convKernelFullNaive(float* d_Input, float* d_Output, float* d_Kernel, int imageW, int imageH, int kernelR)
{
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
int loc = row * imageW + col;
float s = 0;
float t = 0;
for (int i = -KERNAL_RAD; i <= KERNAL_RAD; i++)
for (int j = -KERNAL_RAD; j <= KERNAL_RAD; j++)
{
t = 0;
if (row + i >= 0 && row + i < imageH && col + j >= 0 && col + j < imageW )
t = d_Input[loc + i * imageW + j];
s += t * d_Kernel[(KERNAL_RAD - i) * (KERNAL_RAD + KERNAL_RAD + 1) + KERNAL_RAD - j];
}
d_Output[loc] = s;
} | code for sm_80
Function : _Z19convKernelFullNaivePfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e00ff */
/*0040*/ UIADD3 UR4, UP0, UR4, 0x480, URZ ; /* 0x0000048004047890 */
/* 0x000fe2000ff1e03f */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e260000002100 */
/*0060*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0070*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*00a0*/ ISETP.GE.AND P0, PT, R3.reuse, 0x8, PT ; /* 0x000000080300780c */
/* 0x040fe40003f06270 */
/*00b0*/ IADD3 R0, R3.reuse, -0x8, RZ ; /* 0xfffffff803007810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD R6, R6, c[0x0][0x4], R5 ; /* 0x0000010006067a24 */
/* 0x002fe200078e0205 */
/*00d0*/ ISETP.GE.AND P1, PT, R3.reuse, 0x7, PT ; /* 0x000000070300780c */
/* 0x040fe40003f26270 */
/*00e0*/ IADD3 R2, R3.reuse, -0x7, RZ ; /* 0xfffffff903027810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ ISETP.GE.AND P2, PT, R3.reuse, 0x6, PT ; /* 0x000000060300780c */
/* 0x040fe40003f46270 */
/*0100*/ IADD3 R4, R3, -0x6, RZ ; /* 0xfffffffa03047810 */
/* 0x000fc40007ffe0ff */
/*0110*/ ISETP.GE.OR P3, PT, R0, c[0x0][0x178], !P0 ; /* 0x00005e0000007a0c */
/* 0x000fe40004766670 */
/*0120*/ ISETP.GE.OR P1, PT, R2, c[0x0][0x178], !P1 ; /* 0x00005e0002007a0c */
/* 0x000fe40004f26670 */
/*0130*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x178], !P2 ; /* 0x00005e0004007a0c */
/* 0x000fe40005706670 */
/*0140*/ P2R R28, PR, RZ, 0x8 ; /* 0x00000008ff1c7803 */
/* 0x000fe40000000000 */
/*0150*/ ISETP.GE.AND P3, PT, R3.reuse, 0x5, PT ; /* 0x000000050300780c */
/* 0x040fe40003f66270 */
/*0160*/ IADD3 R0, R3, -0x5, RZ ; /* 0xfffffffb03007810 */
/* 0x000fc40007ffe0ff */
/*0170*/ P2R R29, PR, RZ, 0x2 ; /* 0x00000002ff1d7803 */
/* 0x000fe40000000000 */
/*0180*/ ISETP.GE.AND P2, PT, R3.reuse, 0x4, PT ; /* 0x000000040300780c */
/* 0x040fe40003f46270 */
/*0190*/ IADD3 R2, R3.reuse, -0x4, RZ ; /* 0xfffffffc03027810 */
/* 0x040fe40007ffe0ff */
/*01a0*/ P2R R30, PR, RZ, 0x1 ; /* 0x00000001ff1e7803 */
/* 0x000fe40000000000 */
/*01b0*/ ISETP.GE.AND P1, PT, R3.reuse, 0x3, PT ; /* 0x000000030300780c */
/* 0x040fe40003f26270 */
/*01c0*/ IADD3 R4, R3, -0x3, RZ ; /* 0xfffffffd03047810 */
/* 0x000fc40007ffe0ff */
/*01d0*/ ISETP.GE.AND P0, PT, R3.reuse, 0x2, PT ; /* 0x000000020300780c */
/* 0x040fe40003f06270 */
/*01e0*/ IADD3 R5, R3, -0x2, RZ ; /* 0xfffffffe03057810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.GE.OR P4, PT, R0, c[0x0][0x178], !P3 ; /* 0x00005e0000007a0c */
/* 0x000fe40005f86670 */
/*0200*/ ISETP.GE.OR P3, PT, R2, c[0x0][0x178], !P2 ; /* 0x00005e0002007a0c */
/* 0x000fe20005766670 */
/*0210*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe2000f8e00ff */
/*0220*/ ISETP.GE.OR P2, PT, R4, c[0x0][0x178], !P1 ; /* 0x00005e0004007a0c */
/* 0x000fe20004f46670 */
/*0230*/ IMAD.MOV.U32 R4, RZ, RZ, -0x8 ; /* 0xfffffff8ff047424 */
/* 0x000fe200078e00ff */
/*0240*/ ISETP.GE.OR P1, PT, R5, c[0x0][0x178], !P0 ; /* 0x00005e0005007a0c */
/* 0x000fc40004726670 */
/*0250*/ IADD3 R0, R3.reuse, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x040fe40007ffe0ff */
/*0260*/ ISETP.GE.AND P0, PT, R3.reuse, -0x1, PT ; /* 0xffffffff0300780c */
/* 0x040fe40003f06270 */
/*0270*/ P2R R34, PR, RZ, 0x2 ; /* 0x00000002ff227803 */
/* 0x000fe40000000000 */
/*0280*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], !P0 ; /* 0x00005e0000007a0c */
/* 0x000fe40004726670 */
/*0290*/ IADD3 R0, R3.reuse, 0x2, RZ ; /* 0x0000000203007810 */
/* 0x040fe40007ffe0ff */
/*02a0*/ ISETP.GE.AND P0, PT, R3, -0x2, PT ; /* 0xfffffffe0300780c */
/* 0x000fc40003f06270 */
/*02b0*/ P2R R35, PR, RZ, 0x2 ; /* 0x00000002ff237803 */
/* 0x000fe40000000000 */
/*02c0*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], !P0 ; /* 0x00005e0000007a0c */
/* 0x000fe40004726670 */
/*02d0*/ IADD3 R0, R3.reuse, 0x3, RZ ; /* 0x0000000303007810 */
/* 0x040fe40007ffe0ff */
/*02e0*/ ISETP.GE.AND P0, PT, R3, -0x3, PT ; /* 0xfffffffd0300780c */
/* 0x000fe40003f06270 */
/*02f0*/ P2R R36, PR, RZ, 0x2 ; /* 0x00000002ff247803 */
/* 0x000fe40000000000 */
/*0300*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], !P0 ; /* 0x00005e0000007a0c */
/* 0x000fc40004726670 */
/*0310*/ IADD3 R0, R3.reuse, 0x4, RZ ; /* 0x0000000403007810 */
/* 0x040fe40007ffe0ff */
/*0320*/ ISETP.GE.AND P0, PT, R3.reuse, -0x4, PT ; /* 0xfffffffc0300780c */
/* 0x040fe40003f06270 */
/*0330*/ P2R R27, PR, RZ, 0x2 ; /* 0x00000002ff1b7803 */
/* 0x000fe40000000000 */
/*0340*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], !P0 ; /* 0x00005e0000007a0c */
/* 0x000fe40004706670 */
/*0350*/ IADD3 R0, R3.reuse, 0x5, RZ ; /* 0x0000000503007810 */
/* 0x040fe40007ffe0ff */
/*0360*/ ISETP.GE.AND P1, PT, R3, -0x5, PT ; /* 0xfffffffb0300780c */
/* 0x000fc40003f26270 */
/*0370*/ P2R R33, PR, RZ, 0x4 ; /* 0x00000004ff217803 */
/* 0x000fe40000000000 */
/*0380*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], !P1 ; /* 0x00005e0000007a0c */
/* 0x000fe40004f26670 */
/*0390*/ IADD3 R0, R3.reuse, 0x6, RZ ; /* 0x0000000603007810 */
/* 0x040fe40007ffe0ff */
/*03a0*/ ISETP.GE.AND P2, PT, R3, -0x6, PT ; /* 0xfffffffa0300780c */
/* 0x000fe40003f46270 */
/*03b0*/ P2R R32, PR, RZ, 0x8 ; /* 0x00000008ff207803 */
/* 0x000fe40000000000 */
/*03c0*/ ISETP.GE.OR P2, PT, R0, c[0x0][0x178], !P2 ; /* 0x00005e0000007a0c */
/* 0x000fc40005746670 */
/*03d0*/ IADD3 R0, R3.reuse, 0x7, RZ ; /* 0x0000000703007810 */
/* 0x040fe40007ffe0ff */
/*03e0*/ ISETP.GE.AND P3, PT, R3.reuse, -0x7, PT ; /* 0xfffffff90300780c */
/* 0x040fe40003f66270 */
/*03f0*/ IADD3 R8, R6.reuse, -0x8, RZ ; /* 0xfffffff806087810 */
/* 0x040fe20007ffe0ff */
/*0400*/ IMAD R6, R6, c[0x0][0x178], R3.reuse ; /* 0x00005e0006067a24 */
/* 0x100fe200078e0203 */
/*0410*/ P2R R31, PR, RZ, 0x10 ; /* 0x00000010ff1f7803 */
/* 0x000fe40000000000 */
/*0420*/ ISETP.GE.OR P3, PT, R0, c[0x0][0x178], !P3 ; /* 0x00005e0000007a0c */
/* 0x000fe20005f66670 */
/*0430*/ IMAD R5, R8, c[0x0][0x178], R3 ; /* 0x00005e0008057a24 */
/* 0x000fe200078e0203 */
/*0440*/ IADD3 R0, R3, 0x8, RZ ; /* 0x0000000803007810 */
/* 0x000fc40007ffe0ff */
/*0450*/ ISETP.GE.AND P4, PT, R3, -0x8, PT ; /* 0xfffffff80300780c */
/* 0x000fc80003f86270 */
/*0460*/ ISETP.GE.OR P4, PT, R0, c[0x0][0x178], !P4 ; /* 0x00005e0000007a0c */
/* 0x000fe20006786670 */
/*0470*/ IMAD.U32 R0, RZ, RZ, UR5 ; /* 0x00000005ff007e24 */
/* 0x000fe2000f8e00ff */
/*0480*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0490*/ ISETP.GE.AND P5, PT, R8, c[0x0][0x17c], PT ; /* 0x00005f0008007a0c */
/* 0x000fe20003fa6270 */
/*04a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fe200078e00ff */
/*04b0*/ ISETP.NE.AND P6, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fe20003fc5270 */
/*04c0*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*04d0*/ ISETP.LT.OR P5, PT, R8, RZ, P5 ; /* 0x000000ff0800720c */
/* 0x000fe20002fa1670 */
/*04e0*/ IMAD.WIDE R18, R5, R10, c[0x0][0x160] ; /* 0x0000580005127625 */
/* 0x000fc600078e020a */
/*04f0*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe200037cb570 */
/*0500*/ IMAD.MOV.U32 R38, RZ, RZ, R2 ; /* 0x000000ffff267224 */
/* 0x000fe400078e0002 */
/*0510*/ IMAD.MOV.U32 R39, RZ, RZ, R0 ; /* 0x000000ffff277224 */
/* 0x000fe200078e0000 */
/*0520*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fc8000001ff00 */
/*0530*/ LDG.E R37, [R38.64] ; /* 0x0000000426257981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R0, [R38.64+-0x4] ; /* 0xfffffc0426007981 */
/* 0x000ee8000c1e1900 */
/*0550*/ @!P6 LDG.E R25, [R18.64+-0x20] ; /* 0xffffe0041219e981 */
/* 0x000ea2000c1e1900 */
/*0560*/ ISETP.NE.AND P6, PT, R29, RZ, PT ; /* 0x000000ff1d00720c */
/* 0x000fe20003fc5270 */
/*0570*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*0580*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0590*/ CS2R R22, SRZ ; /* 0x0000000000167805 */
/* 0x000fe2000001ff00 */
/*05a0*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe200037cb570 */
/*05b0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*05c0*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*05d0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*05e0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*05f0*/ LDG.E R40, [R38.64+-0x24] ; /* 0xffffdc0426287981 */
/* 0x000f30000c1e1900 */
/*0600*/ @!P6 LDG.E R12, [R18.64+-0x1c] ; /* 0xffffe404120ce981 */
/* 0x000ee2000c1e1900 */
/*0610*/ ISETP.NE.AND P6, PT, R30, RZ, PT ; /* 0x000000ff1e00720c */
/* 0x000fc80003fc5270 */
/*0620*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*0630*/ @!P6 LDG.E R14, [R18.64+-0x18] ; /* 0xffffe804120ee981 */
/* 0x000f62000c1e1900 */
/*0640*/ ISETP.NE.AND P6, PT, R31, RZ, PT ; /* 0x000000ff1f00720c */
/* 0x000fc80003fc5270 */
/*0650*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*0660*/ @!P6 LDG.E R9, [R18.64+-0x14] ; /* 0xffffec041209e981 */
/* 0x000f22000c1e1900 */
/*0670*/ ISETP.NE.AND P6, PT, R32, RZ, PT ; /* 0x000000ff2000720c */
/* 0x000fc80003fc5270 */
/*0680*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*0690*/ @!P6 LDG.E R23, [R18.64+-0x10] ; /* 0xfffff0041217e981 */
/* 0x000122000c1e1900 */
/*06a0*/ ISETP.NE.AND P6, PT, R33, RZ, PT ; /* 0x000000ff2100720c */
/* 0x000fc80003fc5270 */
/*06b0*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*06c0*/ @!P6 LDG.E R7, [R18.64+-0xc] ; /* 0xfffff4041207e981 */
/* 0x000122000c1e1900 */
/*06d0*/ ISETP.NE.AND P6, PT, R34, RZ, PT ; /* 0x000000ff2200720c */
/* 0x000fc80003fc5270 */
/*06e0*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*06f0*/ @!P6 LDG.E R17, [R18.64+-0x8] ; /* 0xfffff8041211e981 */
/* 0x000122000c1e1900 */
/*0700*/ ISETP.GE.AND P6, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fc80003fc6270 */
/*0710*/ ISETP.GT.OR P6, PT, R3, c[0x0][0x178], !P6 ; /* 0x00005e0003007a0c */
/* 0x000fc800077c4670 */
/*0720*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*0730*/ @!P6 LDG.E R15, [R18.64+-0x4] ; /* 0xfffffc04120fe981 */
/* 0x000122000c1e1900 */
/*0740*/ ISETP.GE.AND P6, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003fc6270 */
/*0750*/ ISETP.GE.OR P6, PT, R3, c[0x0][0x178], !P6 ; /* 0x00005e0003007a0c */
/* 0x000fc800077c6670 */
/*0760*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*0770*/ @!P6 LDG.E R21, [R18.64] ; /* 0x000000041215e981 */
/* 0x000122000c1e1900 */
/*0780*/ ISETP.NE.AND P6, PT, R35, RZ, PT ; /* 0x000000ff2300720c */
/* 0x000fc80003fc5270 */
/*0790*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*07a0*/ @!P6 LDG.E R13, [R18.64+0x4] ; /* 0x00000404120de981 */
/* 0x000122000c1e1900 */
/*07b0*/ ISETP.NE.AND P6, PT, R36, RZ, PT ; /* 0x000000ff2400720c */
/* 0x000fc80003fc5270 */
/*07c0*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*07d0*/ @!P6 LDG.E R11, [R18.64+0x8] ; /* 0x00000804120be981 */
/* 0x000122000c1e1900 */
/*07e0*/ ISETP.NE.AND P6, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fc80003fc5270 */
/*07f0*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*0800*/ @!P6 LDG.E R22, [R18.64+0xc] ; /* 0x00000c041216e981 */
/* 0x000122000c1e1900 */
/*0810*/ PLOP3.LUT P6, PT, P0, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00007cb570 */
/*0820*/ @!P6 LDG.E R20, [R18.64+0x10] ; /* 0x000010041214e981 */
/* 0x000122000c1e1900 */
/*0830*/ PLOP3.LUT P6, PT, P1, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000fcb570 */
/*0840*/ @!P6 LDG.E R16, [R18.64+0x14] ; /* 0x000014041210e981 */
/* 0x000122000c1e1900 */
/*0850*/ FFMA R37, R37, R25, R26 ; /* 0x0000001925257223 */
/* 0x004fc8000000001a */
/*0860*/ FFMA R0, R0, R12, R37 ; /* 0x0000000c00007223 */
/* 0x008fe40000000025 */
/*0870*/ LDG.E R37, [R38.64+-0x8] ; /* 0xfffff80426257981 */
/* 0x000f68000c1e1900 */
/*0880*/ LDG.E R12, [R38.64+-0xc] ; /* 0xfffff404260c7981 */
/* 0x000f22000c1e1900 */
/*0890*/ PLOP3.LUT P6, PT, P2, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe200017cb570 */
/*08a0*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe400078e00ff */
/*08b0*/ IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a7224 */
/* 0x000fd400078e00ff */
/*08c0*/ @!P6 LDG.E R24, [R18.64+0x18] ; /* 0x000018041218e981 */
/* 0x0000a2000c1e1900 */
/*08d0*/ FFMA R14, R37, R14, R0 ; /* 0x0000000e250e7223 */
/* 0x020fc80000000000 */
/*08e0*/ FFMA R9, R12, R9, R14 ; /* 0x000000090c097223 */
/* 0x010fe4000000000e */
/*08f0*/ LDG.E R12, [R38.64+-0x10] ; /* 0xfffff004260c7981 */
/* 0x000ee8000c1e1900 */
/*0900*/ LDG.E R14, [R38.64+-0x14] ; /* 0xffffec04260e7981 */
/* 0x000f22000c1e1900 */
/*0910*/ PLOP3.LUT P6, PT, P3, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40001fcb570 */
/*0920*/ PLOP3.LUT P5, PT, P4, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fd600027ab570 */
/*0930*/ @!P6 LDG.E R25, [R18.64+0x1c] ; /* 0x00001c041219e981 */
/* 0x000168000c1e1900 */
/*0940*/ @!P5 LDG.E R26, [R18.64+0x20] ; /* 0x00002004121ad981 */
/* 0x0000a8000c1e1900 */
/*0950*/ LDG.E R18, [R38.64+-0x18] ; /* 0xffffe80426127981 */
/* 0x001ea8000c1e1900 */
/*0960*/ LDG.E R19, [R38.64+-0x40] ; /* 0xffffc00426137981 */
/* 0x000f62000c1e1900 */
/*0970*/ FFMA R9, R12, R23, R9 ; /* 0x000000170c097223 */
/* 0x008fc60000000009 */
/*0980*/ LDG.E R12, [R38.64+-0x1c] ; /* 0xffffe404260c7981 */
/* 0x000ee2000c1e1900 */
/*0990*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x010fc60000000009 */
/*09a0*/ LDG.E R14, [R38.64+-0x20] ; /* 0xffffe004260e7981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R9, [R38.64+-0x2c] ; /* 0xffffd40426097981 */
/* 0x000f62000c1e1900 */
/*09c0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x004fc60000000007 */
/*09d0*/ LDG.E R18, [R38.64+-0x28] ; /* 0xffffd80426127981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R17, [R38.64+-0x34] ; /* 0xffffcc0426117981 */
/* 0x000f62000c1e1900 */
/*09f0*/ FFMA R12, R12, R15, R7 ; /* 0x0000000f0c0c7223 */
/* 0x008fc60000000007 */
/*0a00*/ LDG.E R7, [R38.64+-0x30] ; /* 0xffffd00426077981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R15, [R38.64+-0x38] ; /* 0xffffc804260f7981 */
/* 0x000ee2000c1e1900 */
/*0a20*/ FFMA R14, R14, R21, R12 ; /* 0x000000150e0e7223 */
/* 0x010fc6000000000c */
/*0a30*/ LDG.E R12, [R38.64+-0x3c] ; /* 0xffffc404260c7981 */
/* 0x000f22000c1e1900 */
/*0a40*/ FFMA R13, R40, R13, R14 ; /* 0x0000000d280d7223 */
/* 0x000fe2000000000e */
/*0a50*/ IADD3 R2, P5, R38, -0x44, RZ ; /* 0xffffffbc26027810 */
/* 0x000fe40007fbe0ff */
/*0a60*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ IADD3.X R0, R39, -0x1, RZ, P5, !PT ; /* 0xffffffff27007810 */
/* 0x000fe40002ffe4ff */
/*0a80*/ ISETP.NE.AND P5, PT, R4, 0x9, PT ; /* 0x000000090400780c */
/* 0x000fe20003fa5270 */
/*0a90*/ FFMA R11, R18, R11, R13 ; /* 0x0000000b120b7223 */
/* 0x004fc8000000000d */
/*0aa0*/ FFMA R9, R9, R22, R11 ; /* 0x0000001609097223 */
/* 0x020fe2000000000b */
/*0ab0*/ IADD3 R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a10 */
/* 0x000fe40007ffe0ff */
/*0ac0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ FFMA R7, R7, R20, R9 ; /* 0x0000001407077223 */
/* 0x008fc80000000009 */
/*0ae0*/ FFMA R7, R17, R16, R7 ; /* 0x0000001011077223 */
/* 0x000fc80000000007 */
/*0af0*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x000fc80000000007 */
/*0b00*/ FFMA R7, R12, R25, R7 ; /* 0x000000190c077223 */
/* 0x010fc80000000007 */
/*0b10*/ FFMA R26, R19, R26, R7 ; /* 0x0000001a131a7223 */
/* 0x000fe20000000007 */
/*0b20*/ @P5 BRA 0x490 ; /* 0xfffff96000005947 */
/* 0x000fea000383ffff */
/*0b30*/ IMAD.WIDE R6, R6, R10, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fca00078e020a */
/*0b40*/ STG.E [R6.64], R26 ; /* 0x0000001a06007986 */
/* 0x000fe2000c101904 */
/*0b50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b60*/ BRA 0xb60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void convKernelFullNaive(float* d_Input, float* d_Output, float* d_Kernel, int imageW, int imageH, int kernelR)
{
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
int loc = row * imageW + col;
float s = 0;
float t = 0;
for (int i = -KERNAL_RAD; i <= KERNAL_RAD; i++)
for (int j = -KERNAL_RAD; j <= KERNAL_RAD; j++)
{
t = 0;
if (row + i >= 0 && row + i < imageH && col + j >= 0 && col + j < imageW )
t = d_Input[loc + i * imageW + j];
s += t * d_Kernel[(KERNAL_RAD - i) * (KERNAL_RAD + KERNAL_RAD + 1) + KERNAL_RAD - j];
}
d_Output[loc] = s;
} | .file "tmpxft_00155d10_00000000-6_convKernelFullNaive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z19convKernelFullNaivePfS_S_iiiPfS_S_iii
.type _Z46__device_stub__Z19convKernelFullNaivePfS_S_iiiPfS_S_iii, @function
_Z46__device_stub__Z19convKernelFullNaivePfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19convKernelFullNaivePfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z19convKernelFullNaivePfS_S_iiiPfS_S_iii, .-_Z46__device_stub__Z19convKernelFullNaivePfS_S_iiiPfS_S_iii
.globl _Z19convKernelFullNaivePfS_S_iii
.type _Z19convKernelFullNaivePfS_S_iii, @function
_Z19convKernelFullNaivePfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19convKernelFullNaivePfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19convKernelFullNaivePfS_S_iii, .-_Z19convKernelFullNaivePfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19convKernelFullNaivePfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19convKernelFullNaivePfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void convKernelFullNaive(float* d_Input, float* d_Output, float* d_Kernel, int imageW, int imageH, int kernelR)
{
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
int loc = row * imageW + col;
float s = 0;
float t = 0;
for (int i = -KERNAL_RAD; i <= KERNAL_RAD; i++)
for (int j = -KERNAL_RAD; j <= KERNAL_RAD; j++)
{
t = 0;
if (row + i >= 0 && row + i < imageH && col + j >= 0 && col + j < imageW )
t = d_Input[loc + i * imageW + j];
s += t * d_Kernel[(KERNAL_RAD - i) * (KERNAL_RAD + KERNAL_RAD + 1) + KERNAL_RAD - j];
}
d_Output[loc] = s;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convKernelFullNaive(float* d_Input, float* d_Output, float* d_Kernel, int imageW, int imageH, int kernelR)
{
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
int loc = row * imageW + col;
float s = 0;
float t = 0;
for (int i = -KERNAL_RAD; i <= KERNAL_RAD; i++)
for (int j = -KERNAL_RAD; j <= KERNAL_RAD; j++)
{
t = 0;
if (row + i >= 0 && row + i < imageH && col + j >= 0 && col + j < imageW )
t = d_Input[loc + i * imageW + j];
s += t * d_Kernel[(KERNAL_RAD - i) * (KERNAL_RAD + KERNAL_RAD + 1) + KERNAL_RAD - j];
}
d_Output[loc] = s;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convKernelFullNaive(float* d_Input, float* d_Output, float* d_Kernel, int imageW, int imageH, int kernelR)
{
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
int loc = row * imageW + col;
float s = 0;
float t = 0;
for (int i = -KERNAL_RAD; i <= KERNAL_RAD; i++)
for (int j = -KERNAL_RAD; j <= KERNAL_RAD; j++)
{
t = 0;
if (row + i >= 0 && row + i < imageH && col + j >= 0 && col + j < imageW )
t = d_Input[loc + i * imageW + j];
s += t * d_Kernel[(KERNAL_RAD - i) * (KERNAL_RAD + KERNAL_RAD + 1) + KERNAL_RAD - j];
}
d_Output[loc] = s;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19convKernelFullNaivePfS_S_iii
.globl _Z19convKernelFullNaivePfS_S_iii
.p2align 8
.type _Z19convKernelFullNaivePfS_S_iii,@function
_Z19convKernelFullNaivePfS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
s_load_b64 s[8:9], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
v_and_b32_e32 v4, 0x3ff, v0
s_mul_i32 s14, s14, s2
s_add_u32 s4, s4, 0x480
s_addc_u32 s5, s5, 0
s_mov_b32 s3, -8
v_add3_u32 v0, v4, s14, -8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, -8, v1
v_mad_u64_u32 v[2:3], null, s6, v5, v[0:1]
v_mov_b32_e32 v3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_add_i32 s3, s3, 1
v_add_nc_u32_e32 v2, s6, v2
s_add_u32 s4, s4, 0xffffffbc
s_addc_u32 s5, s5, -1
s_cmp_eq_u32 s3, 9
s_cbranch_scc1 .LBB0_8
.LBB0_2:
v_add_nc_u32_e32 v5, s3, v1
s_mov_b32 s12, 0
s_mov_b64 s[10:11], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s2, s7, v5
s_and_b32 s13, vcc_lo, s2
s_branch .LBB0_5
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s15
s_load_b32 s2, s[10:11], 0x0
s_add_u32 s10, s10, -4
s_addc_u32 s11, s11, -1
s_add_i32 s12, s12, 1
s_cmp_eq_u32 s12, 17
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v3, s2, v5
s_cbranch_scc1 .LBB0_1
.LBB0_5:
v_mov_b32_e32 v5, 0
s_and_saveexec_b32 s15, s13
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v5, s12, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s2, s6, v5
v_mov_b32_e32 v5, 0
s_and_b32 s16, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s16
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v5, s12, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_branch .LBB0_3
.LBB0_8:
s_set_inst_prefetch_distance 0x2
v_mul_lo_u32 v0, v1, s6
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v4, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19convKernelFullNaivePfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19convKernelFullNaivePfS_S_iii, .Lfunc_end0-_Z19convKernelFullNaivePfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19convKernelFullNaivePfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z19convKernelFullNaivePfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convKernelFullNaive(float* d_Input, float* d_Output, float* d_Kernel, int imageW, int imageH, int kernelR)
{
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
int loc = row * imageW + col;
float s = 0;
float t = 0;
for (int i = -KERNAL_RAD; i <= KERNAL_RAD; i++)
for (int j = -KERNAL_RAD; j <= KERNAL_RAD; j++)
{
t = 0;
if (row + i >= 0 && row + i < imageH && col + j >= 0 && col + j < imageW )
t = d_Input[loc + i * imageW + j];
s += t * d_Kernel[(KERNAL_RAD - i) * (KERNAL_RAD + KERNAL_RAD + 1) + KERNAL_RAD - j];
}
d_Output[loc] = s;
} | .text
.file "convKernelFullNaive.hip"
.globl _Z34__device_stub__convKernelFullNaivePfS_S_iii # -- Begin function _Z34__device_stub__convKernelFullNaivePfS_S_iii
.p2align 4, 0x90
.type _Z34__device_stub__convKernelFullNaivePfS_S_iii,@function
_Z34__device_stub__convKernelFullNaivePfS_S_iii: # @_Z34__device_stub__convKernelFullNaivePfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19convKernelFullNaivePfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__convKernelFullNaivePfS_S_iii, .Lfunc_end0-_Z34__device_stub__convKernelFullNaivePfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19convKernelFullNaivePfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19convKernelFullNaivePfS_S_iii,@object # @_Z19convKernelFullNaivePfS_S_iii
.section .rodata,"a",@progbits
.globl _Z19convKernelFullNaivePfS_S_iii
.p2align 3, 0x0
_Z19convKernelFullNaivePfS_S_iii:
.quad _Z34__device_stub__convKernelFullNaivePfS_S_iii
.size _Z19convKernelFullNaivePfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19convKernelFullNaivePfS_S_iii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__convKernelFullNaivePfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19convKernelFullNaivePfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19convKernelFullNaivePfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e00ff */
/*0040*/ UIADD3 UR4, UP0, UR4, 0x480, URZ ; /* 0x0000048004047890 */
/* 0x000fe2000ff1e03f */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e260000002100 */
/*0060*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0070*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*00a0*/ ISETP.GE.AND P0, PT, R3.reuse, 0x8, PT ; /* 0x000000080300780c */
/* 0x040fe40003f06270 */
/*00b0*/ IADD3 R0, R3.reuse, -0x8, RZ ; /* 0xfffffff803007810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD R6, R6, c[0x0][0x4], R5 ; /* 0x0000010006067a24 */
/* 0x002fe200078e0205 */
/*00d0*/ ISETP.GE.AND P1, PT, R3.reuse, 0x7, PT ; /* 0x000000070300780c */
/* 0x040fe40003f26270 */
/*00e0*/ IADD3 R2, R3.reuse, -0x7, RZ ; /* 0xfffffff903027810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ ISETP.GE.AND P2, PT, R3.reuse, 0x6, PT ; /* 0x000000060300780c */
/* 0x040fe40003f46270 */
/*0100*/ IADD3 R4, R3, -0x6, RZ ; /* 0xfffffffa03047810 */
/* 0x000fc40007ffe0ff */
/*0110*/ ISETP.GE.OR P3, PT, R0, c[0x0][0x178], !P0 ; /* 0x00005e0000007a0c */
/* 0x000fe40004766670 */
/*0120*/ ISETP.GE.OR P1, PT, R2, c[0x0][0x178], !P1 ; /* 0x00005e0002007a0c */
/* 0x000fe40004f26670 */
/*0130*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x178], !P2 ; /* 0x00005e0004007a0c */
/* 0x000fe40005706670 */
/*0140*/ P2R R28, PR, RZ, 0x8 ; /* 0x00000008ff1c7803 */
/* 0x000fe40000000000 */
/*0150*/ ISETP.GE.AND P3, PT, R3.reuse, 0x5, PT ; /* 0x000000050300780c */
/* 0x040fe40003f66270 */
/*0160*/ IADD3 R0, R3, -0x5, RZ ; /* 0xfffffffb03007810 */
/* 0x000fc40007ffe0ff */
/*0170*/ P2R R29, PR, RZ, 0x2 ; /* 0x00000002ff1d7803 */
/* 0x000fe40000000000 */
/*0180*/ ISETP.GE.AND P2, PT, R3.reuse, 0x4, PT ; /* 0x000000040300780c */
/* 0x040fe40003f46270 */
/*0190*/ IADD3 R2, R3.reuse, -0x4, RZ ; /* 0xfffffffc03027810 */
/* 0x040fe40007ffe0ff */
/*01a0*/ P2R R30, PR, RZ, 0x1 ; /* 0x00000001ff1e7803 */
/* 0x000fe40000000000 */
/*01b0*/ ISETP.GE.AND P1, PT, R3.reuse, 0x3, PT ; /* 0x000000030300780c */
/* 0x040fe40003f26270 */
/*01c0*/ IADD3 R4, R3, -0x3, RZ ; /* 0xfffffffd03047810 */
/* 0x000fc40007ffe0ff */
/*01d0*/ ISETP.GE.AND P0, PT, R3.reuse, 0x2, PT ; /* 0x000000020300780c */
/* 0x040fe40003f06270 */
/*01e0*/ IADD3 R5, R3, -0x2, RZ ; /* 0xfffffffe03057810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.GE.OR P4, PT, R0, c[0x0][0x178], !P3 ; /* 0x00005e0000007a0c */
/* 0x000fe40005f86670 */
/*0200*/ ISETP.GE.OR P3, PT, R2, c[0x0][0x178], !P2 ; /* 0x00005e0002007a0c */
/* 0x000fe20005766670 */
/*0210*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe2000f8e00ff */
/*0220*/ ISETP.GE.OR P2, PT, R4, c[0x0][0x178], !P1 ; /* 0x00005e0004007a0c */
/* 0x000fe20004f46670 */
/*0230*/ IMAD.MOV.U32 R4, RZ, RZ, -0x8 ; /* 0xfffffff8ff047424 */
/* 0x000fe200078e00ff */
/*0240*/ ISETP.GE.OR P1, PT, R5, c[0x0][0x178], !P0 ; /* 0x00005e0005007a0c */
/* 0x000fc40004726670 */
/*0250*/ IADD3 R0, R3.reuse, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x040fe40007ffe0ff */
/*0260*/ ISETP.GE.AND P0, PT, R3.reuse, -0x1, PT ; /* 0xffffffff0300780c */
/* 0x040fe40003f06270 */
/*0270*/ P2R R34, PR, RZ, 0x2 ; /* 0x00000002ff227803 */
/* 0x000fe40000000000 */
/*0280*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], !P0 ; /* 0x00005e0000007a0c */
/* 0x000fe40004726670 */
/*0290*/ IADD3 R0, R3.reuse, 0x2, RZ ; /* 0x0000000203007810 */
/* 0x040fe40007ffe0ff */
/*02a0*/ ISETP.GE.AND P0, PT, R3, -0x2, PT ; /* 0xfffffffe0300780c */
/* 0x000fc40003f06270 */
/*02b0*/ P2R R35, PR, RZ, 0x2 ; /* 0x00000002ff237803 */
/* 0x000fe40000000000 */
/*02c0*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], !P0 ; /* 0x00005e0000007a0c */
/* 0x000fe40004726670 */
/*02d0*/ IADD3 R0, R3.reuse, 0x3, RZ ; /* 0x0000000303007810 */
/* 0x040fe40007ffe0ff */
/*02e0*/ ISETP.GE.AND P0, PT, R3, -0x3, PT ; /* 0xfffffffd0300780c */
/* 0x000fe40003f06270 */
/*02f0*/ P2R R36, PR, RZ, 0x2 ; /* 0x00000002ff247803 */
/* 0x000fe40000000000 */
/*0300*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], !P0 ; /* 0x00005e0000007a0c */
/* 0x000fc40004726670 */
/*0310*/ IADD3 R0, R3.reuse, 0x4, RZ ; /* 0x0000000403007810 */
/* 0x040fe40007ffe0ff */
/*0320*/ ISETP.GE.AND P0, PT, R3.reuse, -0x4, PT ; /* 0xfffffffc0300780c */
/* 0x040fe40003f06270 */
/*0330*/ P2R R27, PR, RZ, 0x2 ; /* 0x00000002ff1b7803 */
/* 0x000fe40000000000 */
/*0340*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], !P0 ; /* 0x00005e0000007a0c */
/* 0x000fe40004706670 */
/*0350*/ IADD3 R0, R3.reuse, 0x5, RZ ; /* 0x0000000503007810 */
/* 0x040fe40007ffe0ff */
/*0360*/ ISETP.GE.AND P1, PT, R3, -0x5, PT ; /* 0xfffffffb0300780c */
/* 0x000fc40003f26270 */
/*0370*/ P2R R33, PR, RZ, 0x4 ; /* 0x00000004ff217803 */
/* 0x000fe40000000000 */
/*0380*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x178], !P1 ; /* 0x00005e0000007a0c */
/* 0x000fe40004f26670 */
/*0390*/ IADD3 R0, R3.reuse, 0x6, RZ ; /* 0x0000000603007810 */
/* 0x040fe40007ffe0ff */
/*03a0*/ ISETP.GE.AND P2, PT, R3, -0x6, PT ; /* 0xfffffffa0300780c */
/* 0x000fe40003f46270 */
/*03b0*/ P2R R32, PR, RZ, 0x8 ; /* 0x00000008ff207803 */
/* 0x000fe40000000000 */
/*03c0*/ ISETP.GE.OR P2, PT, R0, c[0x0][0x178], !P2 ; /* 0x00005e0000007a0c */
/* 0x000fc40005746670 */
/*03d0*/ IADD3 R0, R3.reuse, 0x7, RZ ; /* 0x0000000703007810 */
/* 0x040fe40007ffe0ff */
/*03e0*/ ISETP.GE.AND P3, PT, R3.reuse, -0x7, PT ; /* 0xfffffff90300780c */
/* 0x040fe40003f66270 */
/*03f0*/ IADD3 R8, R6.reuse, -0x8, RZ ; /* 0xfffffff806087810 */
/* 0x040fe20007ffe0ff */
/*0400*/ IMAD R6, R6, c[0x0][0x178], R3.reuse ; /* 0x00005e0006067a24 */
/* 0x100fe200078e0203 */
/*0410*/ P2R R31, PR, RZ, 0x10 ; /* 0x00000010ff1f7803 */
/* 0x000fe40000000000 */
/*0420*/ ISETP.GE.OR P3, PT, R0, c[0x0][0x178], !P3 ; /* 0x00005e0000007a0c */
/* 0x000fe20005f66670 */
/*0430*/ IMAD R5, R8, c[0x0][0x178], R3 ; /* 0x00005e0008057a24 */
/* 0x000fe200078e0203 */
/*0440*/ IADD3 R0, R3, 0x8, RZ ; /* 0x0000000803007810 */
/* 0x000fc40007ffe0ff */
/*0450*/ ISETP.GE.AND P4, PT, R3, -0x8, PT ; /* 0xfffffff80300780c */
/* 0x000fc80003f86270 */
/*0460*/ ISETP.GE.OR P4, PT, R0, c[0x0][0x178], !P4 ; /* 0x00005e0000007a0c */
/* 0x000fe20006786670 */
/*0470*/ IMAD.U32 R0, RZ, RZ, UR5 ; /* 0x00000005ff007e24 */
/* 0x000fe2000f8e00ff */
/*0480*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0490*/ ISETP.GE.AND P5, PT, R8, c[0x0][0x17c], PT ; /* 0x00005f0008007a0c */
/* 0x000fe20003fa6270 */
/*04a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fe200078e00ff */
/*04b0*/ ISETP.NE.AND P6, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fe20003fc5270 */
/*04c0*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*04d0*/ ISETP.LT.OR P5, PT, R8, RZ, P5 ; /* 0x000000ff0800720c */
/* 0x000fe20002fa1670 */
/*04e0*/ IMAD.WIDE R18, R5, R10, c[0x0][0x160] ; /* 0x0000580005127625 */
/* 0x000fc600078e020a */
/*04f0*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe200037cb570 */
/*0500*/ IMAD.MOV.U32 R38, RZ, RZ, R2 ; /* 0x000000ffff267224 */
/* 0x000fe400078e0002 */
/*0510*/ IMAD.MOV.U32 R39, RZ, RZ, R0 ; /* 0x000000ffff277224 */
/* 0x000fe200078e0000 */
/*0520*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fc8000001ff00 */
/*0530*/ LDG.E R37, [R38.64] ; /* 0x0000000426257981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R0, [R38.64+-0x4] ; /* 0xfffffc0426007981 */
/* 0x000ee8000c1e1900 */
/*0550*/ @!P6 LDG.E R25, [R18.64+-0x20] ; /* 0xffffe0041219e981 */
/* 0x000ea2000c1e1900 */
/*0560*/ ISETP.NE.AND P6, PT, R29, RZ, PT ; /* 0x000000ff1d00720c */
/* 0x000fe20003fc5270 */
/*0570*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*0580*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0590*/ CS2R R22, SRZ ; /* 0x0000000000167805 */
/* 0x000fe2000001ff00 */
/*05a0*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe200037cb570 */
/*05b0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*05c0*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*05d0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*05e0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*05f0*/ LDG.E R40, [R38.64+-0x24] ; /* 0xffffdc0426287981 */
/* 0x000f30000c1e1900 */
/*0600*/ @!P6 LDG.E R12, [R18.64+-0x1c] ; /* 0xffffe404120ce981 */
/* 0x000ee2000c1e1900 */
/*0610*/ ISETP.NE.AND P6, PT, R30, RZ, PT ; /* 0x000000ff1e00720c */
/* 0x000fc80003fc5270 */
/*0620*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*0630*/ @!P6 LDG.E R14, [R18.64+-0x18] ; /* 0xffffe804120ee981 */
/* 0x000f62000c1e1900 */
/*0640*/ ISETP.NE.AND P6, PT, R31, RZ, PT ; /* 0x000000ff1f00720c */
/* 0x000fc80003fc5270 */
/*0650*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*0660*/ @!P6 LDG.E R9, [R18.64+-0x14] ; /* 0xffffec041209e981 */
/* 0x000f22000c1e1900 */
/*0670*/ ISETP.NE.AND P6, PT, R32, RZ, PT ; /* 0x000000ff2000720c */
/* 0x000fc80003fc5270 */
/*0680*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*0690*/ @!P6 LDG.E R23, [R18.64+-0x10] ; /* 0xfffff0041217e981 */
/* 0x000122000c1e1900 */
/*06a0*/ ISETP.NE.AND P6, PT, R33, RZ, PT ; /* 0x000000ff2100720c */
/* 0x000fc80003fc5270 */
/*06b0*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*06c0*/ @!P6 LDG.E R7, [R18.64+-0xc] ; /* 0xfffff4041207e981 */
/* 0x000122000c1e1900 */
/*06d0*/ ISETP.NE.AND P6, PT, R34, RZ, PT ; /* 0x000000ff2200720c */
/* 0x000fc80003fc5270 */
/*06e0*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*06f0*/ @!P6 LDG.E R17, [R18.64+-0x8] ; /* 0xfffff8041211e981 */
/* 0x000122000c1e1900 */
/*0700*/ ISETP.GE.AND P6, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fc80003fc6270 */
/*0710*/ ISETP.GT.OR P6, PT, R3, c[0x0][0x178], !P6 ; /* 0x00005e0003007a0c */
/* 0x000fc800077c4670 */
/*0720*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*0730*/ @!P6 LDG.E R15, [R18.64+-0x4] ; /* 0xfffffc04120fe981 */
/* 0x000122000c1e1900 */
/*0740*/ ISETP.GE.AND P6, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003fc6270 */
/*0750*/ ISETP.GE.OR P6, PT, R3, c[0x0][0x178], !P6 ; /* 0x00005e0003007a0c */
/* 0x000fc800077c6670 */
/*0760*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*0770*/ @!P6 LDG.E R21, [R18.64] ; /* 0x000000041215e981 */
/* 0x000122000c1e1900 */
/*0780*/ ISETP.NE.AND P6, PT, R35, RZ, PT ; /* 0x000000ff2300720c */
/* 0x000fc80003fc5270 */
/*0790*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*07a0*/ @!P6 LDG.E R13, [R18.64+0x4] ; /* 0x00000404120de981 */
/* 0x000122000c1e1900 */
/*07b0*/ ISETP.NE.AND P6, PT, R36, RZ, PT ; /* 0x000000ff2400720c */
/* 0x000fc80003fc5270 */
/*07c0*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*07d0*/ @!P6 LDG.E R11, [R18.64+0x8] ; /* 0x00000804120be981 */
/* 0x000122000c1e1900 */
/*07e0*/ ISETP.NE.AND P6, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fc80003fc5270 */
/*07f0*/ PLOP3.LUT P6, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00037cb570 */
/*0800*/ @!P6 LDG.E R22, [R18.64+0xc] ; /* 0x00000c041216e981 */
/* 0x000122000c1e1900 */
/*0810*/ PLOP3.LUT P6, PT, P0, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00007cb570 */
/*0820*/ @!P6 LDG.E R20, [R18.64+0x10] ; /* 0x000010041214e981 */
/* 0x000122000c1e1900 */
/*0830*/ PLOP3.LUT P6, PT, P1, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000fcb570 */
/*0840*/ @!P6 LDG.E R16, [R18.64+0x14] ; /* 0x000014041210e981 */
/* 0x000122000c1e1900 */
/*0850*/ FFMA R37, R37, R25, R26 ; /* 0x0000001925257223 */
/* 0x004fc8000000001a */
/*0860*/ FFMA R0, R0, R12, R37 ; /* 0x0000000c00007223 */
/* 0x008fe40000000025 */
/*0870*/ LDG.E R37, [R38.64+-0x8] ; /* 0xfffff80426257981 */
/* 0x000f68000c1e1900 */
/*0880*/ LDG.E R12, [R38.64+-0xc] ; /* 0xfffff404260c7981 */
/* 0x000f22000c1e1900 */
/*0890*/ PLOP3.LUT P6, PT, P2, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe200017cb570 */
/*08a0*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe400078e00ff */
/*08b0*/ IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a7224 */
/* 0x000fd400078e00ff */
/*08c0*/ @!P6 LDG.E R24, [R18.64+0x18] ; /* 0x000018041218e981 */
/* 0x0000a2000c1e1900 */
/*08d0*/ FFMA R14, R37, R14, R0 ; /* 0x0000000e250e7223 */
/* 0x020fc80000000000 */
/*08e0*/ FFMA R9, R12, R9, R14 ; /* 0x000000090c097223 */
/* 0x010fe4000000000e */
/*08f0*/ LDG.E R12, [R38.64+-0x10] ; /* 0xfffff004260c7981 */
/* 0x000ee8000c1e1900 */
/*0900*/ LDG.E R14, [R38.64+-0x14] ; /* 0xffffec04260e7981 */
/* 0x000f22000c1e1900 */
/*0910*/ PLOP3.LUT P6, PT, P3, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40001fcb570 */
/*0920*/ PLOP3.LUT P5, PT, P4, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fd600027ab570 */
/*0930*/ @!P6 LDG.E R25, [R18.64+0x1c] ; /* 0x00001c041219e981 */
/* 0x000168000c1e1900 */
/*0940*/ @!P5 LDG.E R26, [R18.64+0x20] ; /* 0x00002004121ad981 */
/* 0x0000a8000c1e1900 */
/*0950*/ LDG.E R18, [R38.64+-0x18] ; /* 0xffffe80426127981 */
/* 0x001ea8000c1e1900 */
/*0960*/ LDG.E R19, [R38.64+-0x40] ; /* 0xffffc00426137981 */
/* 0x000f62000c1e1900 */
/*0970*/ FFMA R9, R12, R23, R9 ; /* 0x000000170c097223 */
/* 0x008fc60000000009 */
/*0980*/ LDG.E R12, [R38.64+-0x1c] ; /* 0xffffe404260c7981 */
/* 0x000ee2000c1e1900 */
/*0990*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x010fc60000000009 */
/*09a0*/ LDG.E R14, [R38.64+-0x20] ; /* 0xffffe004260e7981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R9, [R38.64+-0x2c] ; /* 0xffffd40426097981 */
/* 0x000f62000c1e1900 */
/*09c0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x004fc60000000007 */
/*09d0*/ LDG.E R18, [R38.64+-0x28] ; /* 0xffffd80426127981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R17, [R38.64+-0x34] ; /* 0xffffcc0426117981 */
/* 0x000f62000c1e1900 */
/*09f0*/ FFMA R12, R12, R15, R7 ; /* 0x0000000f0c0c7223 */
/* 0x008fc60000000007 */
/*0a00*/ LDG.E R7, [R38.64+-0x30] ; /* 0xffffd00426077981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R15, [R38.64+-0x38] ; /* 0xffffc804260f7981 */
/* 0x000ee2000c1e1900 */
/*0a20*/ FFMA R14, R14, R21, R12 ; /* 0x000000150e0e7223 */
/* 0x010fc6000000000c */
/*0a30*/ LDG.E R12, [R38.64+-0x3c] ; /* 0xffffc404260c7981 */
/* 0x000f22000c1e1900 */
/*0a40*/ FFMA R13, R40, R13, R14 ; /* 0x0000000d280d7223 */
/* 0x000fe2000000000e */
/*0a50*/ IADD3 R2, P5, R38, -0x44, RZ ; /* 0xffffffbc26027810 */
/* 0x000fe40007fbe0ff */
/*0a60*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ IADD3.X R0, R39, -0x1, RZ, P5, !PT ; /* 0xffffffff27007810 */
/* 0x000fe40002ffe4ff */
/*0a80*/ ISETP.NE.AND P5, PT, R4, 0x9, PT ; /* 0x000000090400780c */
/* 0x000fe20003fa5270 */
/*0a90*/ FFMA R11, R18, R11, R13 ; /* 0x0000000b120b7223 */
/* 0x004fc8000000000d */
/*0aa0*/ FFMA R9, R9, R22, R11 ; /* 0x0000001609097223 */
/* 0x020fe2000000000b */
/*0ab0*/ IADD3 R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a10 */
/* 0x000fe40007ffe0ff */
/*0ac0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ FFMA R7, R7, R20, R9 ; /* 0x0000001407077223 */
/* 0x008fc80000000009 */
/*0ae0*/ FFMA R7, R17, R16, R7 ; /* 0x0000001011077223 */
/* 0x000fc80000000007 */
/*0af0*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x000fc80000000007 */
/*0b00*/ FFMA R7, R12, R25, R7 ; /* 0x000000190c077223 */
/* 0x010fc80000000007 */
/*0b10*/ FFMA R26, R19, R26, R7 ; /* 0x0000001a131a7223 */
/* 0x000fe20000000007 */
/*0b20*/ @P5 BRA 0x490 ; /* 0xfffff96000005947 */
/* 0x000fea000383ffff */
/*0b30*/ IMAD.WIDE R6, R6, R10, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fca00078e020a */
/*0b40*/ STG.E [R6.64], R26 ; /* 0x0000001a06007986 */
/* 0x000fe2000c101904 */
/*0b50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b60*/ BRA 0xb60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19convKernelFullNaivePfS_S_iii
.globl _Z19convKernelFullNaivePfS_S_iii
.p2align 8
.type _Z19convKernelFullNaivePfS_S_iii,@function
_Z19convKernelFullNaivePfS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
s_load_b64 s[8:9], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
v_and_b32_e32 v4, 0x3ff, v0
s_mul_i32 s14, s14, s2
s_add_u32 s4, s4, 0x480
s_addc_u32 s5, s5, 0
s_mov_b32 s3, -8
v_add3_u32 v0, v4, s14, -8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, -8, v1
v_mad_u64_u32 v[2:3], null, s6, v5, v[0:1]
v_mov_b32_e32 v3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_add_i32 s3, s3, 1
v_add_nc_u32_e32 v2, s6, v2
s_add_u32 s4, s4, 0xffffffbc
s_addc_u32 s5, s5, -1
s_cmp_eq_u32 s3, 9
s_cbranch_scc1 .LBB0_8
.LBB0_2:
v_add_nc_u32_e32 v5, s3, v1
s_mov_b32 s12, 0
s_mov_b64 s[10:11], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s2, s7, v5
s_and_b32 s13, vcc_lo, s2
s_branch .LBB0_5
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s15
s_load_b32 s2, s[10:11], 0x0
s_add_u32 s10, s10, -4
s_addc_u32 s11, s11, -1
s_add_i32 s12, s12, 1
s_cmp_eq_u32 s12, 17
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v3, s2, v5
s_cbranch_scc1 .LBB0_1
.LBB0_5:
v_mov_b32_e32 v5, 0
s_and_saveexec_b32 s15, s13
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v5, s12, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s2, s6, v5
v_mov_b32_e32 v5, 0
s_and_b32 s16, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s16
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v5, s12, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_branch .LBB0_3
.LBB0_8:
s_set_inst_prefetch_distance 0x2
v_mul_lo_u32 v0, v1, s6
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v4, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19convKernelFullNaivePfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19convKernelFullNaivePfS_S_iii, .Lfunc_end0-_Z19convKernelFullNaivePfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19convKernelFullNaivePfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z19convKernelFullNaivePfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00155d10_00000000-6_convKernelFullNaive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z19convKernelFullNaivePfS_S_iiiPfS_S_iii
.type _Z46__device_stub__Z19convKernelFullNaivePfS_S_iiiPfS_S_iii, @function
_Z46__device_stub__Z19convKernelFullNaivePfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19convKernelFullNaivePfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z19convKernelFullNaivePfS_S_iiiPfS_S_iii, .-_Z46__device_stub__Z19convKernelFullNaivePfS_S_iiiPfS_S_iii
.globl _Z19convKernelFullNaivePfS_S_iii
.type _Z19convKernelFullNaivePfS_S_iii, @function
_Z19convKernelFullNaivePfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19convKernelFullNaivePfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19convKernelFullNaivePfS_S_iii, .-_Z19convKernelFullNaivePfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19convKernelFullNaivePfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19convKernelFullNaivePfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convKernelFullNaive.hip"
.globl _Z34__device_stub__convKernelFullNaivePfS_S_iii # -- Begin function _Z34__device_stub__convKernelFullNaivePfS_S_iii
.p2align 4, 0x90
.type _Z34__device_stub__convKernelFullNaivePfS_S_iii,@function
_Z34__device_stub__convKernelFullNaivePfS_S_iii: # @_Z34__device_stub__convKernelFullNaivePfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19convKernelFullNaivePfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__convKernelFullNaivePfS_S_iii, .Lfunc_end0-_Z34__device_stub__convKernelFullNaivePfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19convKernelFullNaivePfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19convKernelFullNaivePfS_S_iii,@object # @_Z19convKernelFullNaivePfS_S_iii
.section .rodata,"a",@progbits
.globl _Z19convKernelFullNaivePfS_S_iii
.p2align 3, 0x0
_Z19convKernelFullNaivePfS_S_iii:
.quad _Z34__device_stub__convKernelFullNaivePfS_S_iii
.size _Z19convKernelFullNaivePfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19convKernelFullNaivePfS_S_iii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__convKernelFullNaivePfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19convKernelFullNaivePfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cassert>
#include <iostream>
#include <math.h>
#include <cooperative_groups.h>
using namespace cooperative_groups;
// Reduces a thread group to a single element
__device__ int reduce_sum(thread_group g, int *temp, int val){
int lane = g.thread_rank();
// Each thread adds its partial sum[i] to sum[lane+i]
for (int i = g.size() / 2; i > 0; i /= 2){
temp[lane] = val;
// wait for all threads to store
g.sync();
if (lane < i) {
val += temp[lane + i];
}
// wait for all threads to load
g.sync();
}
// note: only thread 0 will return full sum
return val;
}
// Creates partials sums from the original array
__device__ int thread_sum(int *input, int n){
int sum = 0;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = tid; i < n / 4; i += blockDim.x * gridDim.x){
// Cast as int4
int4 in = ((int4*)input)[i];
sum += in.x + in.y + in.z + in.w;
}
return sum;
}
__global__ void sum_reduction(int *sum, int *input, int n){
// Create partial sums from the array
int my_sum = thread_sum(input, n);
// Dynamic shared memory allocation
extern __shared__ int temp[];
// Identifier for a TB
auto g = this_thread_block();
// Reudce each TB
int block_sum = reduce_sum(g, temp, my_sum);
// Collect the partial result from each TB
if (g.thread_rank() == 0) {
atomicAdd(sum, block_sum);
}
}
void initialize_vector(int *v, int n) {
for (int i = 0; i < n; i++) {
v[i] = 1;//rand() % 10;
}
}
int main() {
int n = 1<<13;
size_t bytes = n * sizeof(int);
int *sum, *data;
cudaMallocManaged(&sum, sizeof(int));
cudaMallocManaged(&data, bytes);
initialize_vector(data,n);
int TB_SIZE = 256;
int GRID = (n + TB_SIZE -1 ) / TB_SIZE;
sum_reduction<<<GRID,TB_SIZE, n*sizeof(int)>>>(sum,data,n);
cudaDeviceSynchronize();
assert(*sum == 8192);
printf("Done\n");
return 0;
} | code for sm_80
Function : _Z13sum_reductionPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x1a0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0040*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR5 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011405 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0080*/ ULEA.HI UR4, UR4, UR5, URZ, 0x2 ; /* 0x0000000504047291 */
/* 0x000fe2000f8f103f */
/*0090*/ S2R R2, SR_TID.Z ; /* 0x0000000000027919 */
/* 0x000e660000002300 */
/*00a0*/ USHF.R.S32.HI UR4, URZ, 0x2, UR4 ; /* 0x000000023f047899 */
/* 0x000fe20008011404 */
/*00b0*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ea20000002200 */
/*00c0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00e0*/ @P0 BRA 0x190 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x006fe400000001ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0205 */
/*0120*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1d00 */
/*0130*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*0150*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe4000bf06270 */
/*0160*/ IADD3 R8, R4, R5, R8 ; /* 0x0000000504087210 */
/* 0x004fc80007ffe008 */
/*0170*/ IADD3 R8, R7, R8, R6 ; /* 0x0000000807087210 */
/* 0x000fce0007ffe006 */
/*0180*/ @!P0 BRA 0x100 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x006fea0003800000 */
/*01a0*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ IMAD R0, R2, c[0x0][0x4], R9 ; /* 0x0000010002007a24 */
/* 0x000fe200078e0209 */
/*01c0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*01d0*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fe40007ffe1ff */
/*01e0*/ ULDC UR5, c[0x0][0x8] ; /* 0x0000020000057ab9 */
/* 0x000fe20000000800 */
/*01f0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fe200078e02ff */
/*0200*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc8000f8e023f */
/*0210*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0220*/ ISETP.NE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fca0003f05270 */
/*0230*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*0240*/ @!P1 BRA 0x330 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fe400078e0203 */
/*0260*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fc6000f8e00ff */
/*0270*/ SHF.L.U32 R5, R3, 0x2, RZ ; /* 0x0000000203057819 */
/* 0x000fe400000006ff */
/*0280*/ ISETP.GT.AND P1, PT, R0.reuse, R3, PT ; /* 0x000000030000720c */
/* 0x040fe20003f24270 */
/*0290*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x000fe80000004800 */
/*02a0*/ BAR.SYNC 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000000000 */
/*02b0*/ ISETP.GT.AND P2, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc40003f44270 */
/*02c0*/ @P1 IMAD R2, R0.reuse, 0x4, R5 ; /* 0x0000000400021824 */
/* 0x040fe200078e0205 */
/*02d0*/ LEA.HI R4, R0, R0, RZ, 0x1 ; /* 0x0000000000047211 */
/* 0x000fc800078f08ff */
/*02e0*/ @P1 LDS R7, [R2] ; /* 0x0000000002071984 */
/* 0x000e220000000800 */
/*02f0*/ SHF.R.S32.HI R0, RZ, 0x1, R4 ; /* 0x00000001ff007819 */
/* 0x000fe20000011404 */
/*0300*/ @P1 IMAD.IADD R8, R8, 0x1, R7 ; /* 0x0000000108081824 */
/* 0x001fe400078e0207 */
/*0310*/ BAR.SYNC 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000000000 */
/*0320*/ @P2 BRA 0x280 ; /* 0xffffff5000002947 */
/* 0x000fea000383ffff */
/*0330*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0340*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0350*/ REDUX.SUM UR5, R8 ; /* 0x00000000080573c4 */
/* 0x000e62000000c000 */
/*0360*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0370*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0380*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*03a0*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe4000bf02070 */
/*03b0*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x002fd60008000f00 */
/*03c0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x000fe2000c10e186 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cassert>
#include <iostream>
#include <math.h>
#include <cooperative_groups.h>
using namespace cooperative_groups;
// Reduces a thread group to a single element
__device__ int reduce_sum(thread_group g, int *temp, int val){
int lane = g.thread_rank();
// Each thread adds its partial sum[i] to sum[lane+i]
for (int i = g.size() / 2; i > 0; i /= 2){
temp[lane] = val;
// wait for all threads to store
g.sync();
if (lane < i) {
val += temp[lane + i];
}
// wait for all threads to load
g.sync();
}
// note: only thread 0 will return full sum
return val;
}
// Creates partials sums from the original array
__device__ int thread_sum(int *input, int n){
int sum = 0;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = tid; i < n / 4; i += blockDim.x * gridDim.x){
// Cast as int4
int4 in = ((int4*)input)[i];
sum += in.x + in.y + in.z + in.w;
}
return sum;
}
__global__ void sum_reduction(int *sum, int *input, int n){
// Create partial sums from the array
int my_sum = thread_sum(input, n);
// Dynamic shared memory allocation
extern __shared__ int temp[];
// Identifier for a TB
auto g = this_thread_block();
// Reudce each TB
int block_sum = reduce_sum(g, temp, my_sum);
// Collect the partial result from each TB
if (g.thread_rank() == 0) {
atomicAdd(sum, block_sum);
}
}
void initialize_vector(int *v, int n) {
for (int i = 0; i < n; i++) {
v[i] = 1;//rand() % 10;
}
}
int main() {
int n = 1<<13;
size_t bytes = n * sizeof(int);
int *sum, *data;
cudaMallocManaged(&sum, sizeof(int));
cudaMallocManaged(&data, bytes);
initialize_vector(data,n);
int TB_SIZE = 256;
int GRID = (n + TB_SIZE -1 ) / TB_SIZE;
sum_reduction<<<GRID,TB_SIZE, n*sizeof(int)>>>(sum,data,n);
cudaDeviceSynchronize();
assert(*sum == 8192);
printf("Done\n");
return 0;
} | .file "tmpxft_0019b296_00000000-6_groups.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6872:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6872:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii
.type _Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii, @function
_Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii:
.LFB6866:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE6866:
.size _Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii, .-_Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii
.globl _Z10thread_sumPii
.type _Z10thread_sumPii, @function
_Z10thread_sumPii:
.LFB6867:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE6867:
.size _Z10thread_sumPii, .-_Z10thread_sumPii
.globl _Z17initialize_vectorPii
.type _Z17initialize_vectorPii, @function
_Z17initialize_vectorPii:
.LFB6868:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L7
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L9:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L9
.L7:
ret
.cfi_endproc
.LFE6868:
.size _Z17initialize_vectorPii, .-_Z17initialize_vectorPii
.globl _Z36__device_stub__Z13sum_reductionPiS_iPiS_i
.type _Z36__device_stub__Z13sum_reductionPiS_iPiS_i, @function
_Z36__device_stub__Z13sum_reductionPiS_iPiS_i:
.LFB6894:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13sum_reductionPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6894:
.size _Z36__device_stub__Z13sum_reductionPiS_iPiS_i, .-_Z36__device_stub__Z13sum_reductionPiS_iPiS_i
.globl _Z13sum_reductionPiS_i
.type _Z13sum_reductionPiS_i, @function
_Z13sum_reductionPiS_i:
.LFB6895:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13sum_reductionPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6895:
.size _Z13sum_reductionPiS_i, .-_Z13sum_reductionPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Done\n"
.text
.globl main
.type main, @function
main:
.LFB6869:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $32768, %esi
call cudaMallocManaged@PLT
movl $8192, %esi
movq 8(%rsp), %rdi
call _Z17initialize_vectorPii
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $32768, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
call cudaDeviceSynchronize@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $8192, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z36__device_stub__Z13sum_reductionPiS_iPiS_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6869:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13sum_reductionPiS_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_ZN39_INTERNAL_978cdd9e_9_groups_cu_115040b94cuda3std3__419piecewise_constructE"
.align 8
.LC3:
.string "_ZN39_INTERNAL_978cdd9e_9_groups_cu_115040b94cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC4:
.string "_ZN39_INTERNAL_978cdd9e_9_groups_cu_115040b94cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6897:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13sum_reductionPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6897:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cassert>
#include <iostream>
#include <math.h>
#include <cooperative_groups.h>
using namespace cooperative_groups;
// Reduces a thread group to a single element
__device__ int reduce_sum(thread_group g, int *temp, int val){
int lane = g.thread_rank();
// Each thread adds its partial sum[i] to sum[lane+i]
for (int i = g.size() / 2; i > 0; i /= 2){
temp[lane] = val;
// wait for all threads to store
g.sync();
if (lane < i) {
val += temp[lane + i];
}
// wait for all threads to load
g.sync();
}
// note: only thread 0 will return full sum
return val;
}
// Creates partials sums from the original array
__device__ int thread_sum(int *input, int n){
int sum = 0;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = tid; i < n / 4; i += blockDim.x * gridDim.x){
// Cast as int4
int4 in = ((int4*)input)[i];
sum += in.x + in.y + in.z + in.w;
}
return sum;
}
__global__ void sum_reduction(int *sum, int *input, int n){
// Create partial sums from the array
int my_sum = thread_sum(input, n);
// Dynamic shared memory allocation
extern __shared__ int temp[];
// Identifier for a TB
auto g = this_thread_block();
// Reudce each TB
int block_sum = reduce_sum(g, temp, my_sum);
// Collect the partial result from each TB
if (g.thread_rank() == 0) {
atomicAdd(sum, block_sum);
}
}
void initialize_vector(int *v, int n) {
for (int i = 0; i < n; i++) {
v[i] = 1;//rand() % 10;
}
}
int main() {
int n = 1<<13;
size_t bytes = n * sizeof(int);
int *sum, *data;
cudaMallocManaged(&sum, sizeof(int));
cudaMallocManaged(&data, bytes);
initialize_vector(data,n);
int TB_SIZE = 256;
int GRID = (n + TB_SIZE -1 ) / TB_SIZE;
sum_reduction<<<GRID,TB_SIZE, n*sizeof(int)>>>(sum,data,n);
cudaDeviceSynchronize();
assert(*sum == 8192);
printf("Done\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <cassert>
#include <iostream>
#include <math.h>
#include <hip/hip_cooperative_groups.h>
using namespace cooperative_groups;
// Reduces a thread group to a single element
__device__ int reduce_sum(thread_group g, int *temp, int val){
int lane = g.thread_rank();
// Each thread adds its partial sum[i] to sum[lane+i]
for (int i = g.size() / 2; i > 0; i /= 2){
temp[lane] = val;
// wait for all threads to store
g.sync();
if (lane < i) {
val += temp[lane + i];
}
// wait for all threads to load
g.sync();
}
// note: only thread 0 will return full sum
return val;
}
// Creates partials sums from the original array
__device__ int thread_sum(int *input, int n){
int sum = 0;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = tid; i < n / 4; i += blockDim.x * gridDim.x){
// Cast as int4
int4 in = ((int4*)input)[i];
sum += in.x + in.y + in.z + in.w;
}
return sum;
}
__global__ void sum_reduction(int *sum, int *input, int n){
// Create partial sums from the array
int my_sum = thread_sum(input, n);
// Dynamic shared memory allocation
extern __shared__ int temp[];
// Identifier for a TB
auto g = this_thread_block();
// Reudce each TB
int block_sum = reduce_sum(g, temp, my_sum);
// Collect the partial result from each TB
if (g.thread_rank() == 0) {
atomicAdd(sum, block_sum);
}
}
void initialize_vector(int *v, int n) {
for (int i = 0; i < n; i++) {
v[i] = 1;//rand() % 10;
}
}
int main() {
int n = 1<<13;
size_t bytes = n * sizeof(int);
int *sum, *data;
hipMallocManaged(&sum, sizeof(int));
hipMallocManaged(&data, bytes);
initialize_vector(data,n);
int TB_SIZE = 256;
int GRID = (n + TB_SIZE -1 ) / TB_SIZE;
sum_reduction<<<GRID,TB_SIZE, n*sizeof(int)>>>(sum,data,n);
hipDeviceSynchronize();
assert(*sum == 8192);
printf("Done\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cassert>
#include <iostream>
#include <math.h>
#include <hip/hip_cooperative_groups.h>
using namespace cooperative_groups;
// Reduces a thread group to a single element
__device__ int reduce_sum(thread_group g, int *temp, int val){
int lane = g.thread_rank();
// Each thread adds its partial sum[i] to sum[lane+i]
for (int i = g.size() / 2; i > 0; i /= 2){
temp[lane] = val;
// wait for all threads to store
g.sync();
if (lane < i) {
val += temp[lane + i];
}
// wait for all threads to load
g.sync();
}
// note: only thread 0 will return full sum
return val;
}
// Creates partials sums from the original array
__device__ int thread_sum(int *input, int n){
int sum = 0;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = tid; i < n / 4; i += blockDim.x * gridDim.x){
// Cast as int4
int4 in = ((int4*)input)[i];
sum += in.x + in.y + in.z + in.w;
}
return sum;
}
__global__ void sum_reduction(int *sum, int *input, int n){
// Create partial sums from the array
int my_sum = thread_sum(input, n);
// Dynamic shared memory allocation
extern __shared__ int temp[];
// Identifier for a TB
auto g = this_thread_block();
// Reudce each TB
int block_sum = reduce_sum(g, temp, my_sum);
// Collect the partial result from each TB
if (g.thread_rank() == 0) {
atomicAdd(sum, block_sum);
}
}
void initialize_vector(int *v, int n) {
for (int i = 0; i < n; i++) {
v[i] = 1;//rand() % 10;
}
}
int main() {
int n = 1<<13;
size_t bytes = n * sizeof(int);
int *sum, *data;
hipMallocManaged(&sum, sizeof(int));
hipMallocManaged(&data, bytes);
initialize_vector(data,n);
int TB_SIZE = 256;
int GRID = (n + TB_SIZE -1 ) / TB_SIZE;
sum_reduction<<<GRID,TB_SIZE, n*sizeof(int)>>>(sum,data,n);
hipDeviceSynchronize();
assert(*sum == 8192);
printf("Done\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13sum_reductionPiS_i
.globl _Z13sum_reductionPiS_i
.p2align 8
.type _Z13sum_reductionPiS_i,@function
_Z13sum_reductionPiS_i:
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s15, s8
s_cselect_b32 s4, 12, 18
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s4
s_load_b32 s4, s[0:1], 0x10
global_load_u16 v5, v1, s[2:3]
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s5, s5, 30
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_ashr_i32 s7, s4, 2
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, v5, v[1:2]
v_cmpx_gt_i32_e64 s7, v2
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x8
v_mul_lo_u32 v5, s8, v5
v_mov_b32_e32 v4, 0
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[6:7], 4, v[2:3]
v_add_nc_u32_e32 v2, v2, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s7, v2
global_load_b128 v[6:9], v[6:7], off
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add3_u32 v3, v6, v4, v7
v_add3_u32 v4, v3, v8, v9
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s8
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[4:5], s[2:3], 0xc
v_bfe_u32 v5, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s4, 0xffff
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s5, 0xffff
s_mul_i32 s5, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s5, s4
s_cmp_lt_u32 s4, 2
s_cbranch_scc1 .LBB0_10
v_mad_u32_u24 v6, v0, s3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v6, s2, v[1:2]
v_lshl_add_u32 v3, v2, 2, 0
.p2align 6
.LBB0_6:
s_lshr_b32 s5, s4, 1
s_mov_b32 s6, exec_lo
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s5, v2
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v6, s5, 2, v3
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v6, v4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_gt_u32 s4, 3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
s_mov_b32 s4, s5
s_branch .LBB0_6
.LBB0_10:
v_mad_u32_u24 v0, v0, s3, v5
v_sub_nc_u32_e32 v1, 0, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
s_mov_b32 s2, 0
v_cmpx_eq_u32_e64 v0, v1
s_cbranch_execz .LBB0_15
s_mov_b32 s3, exec_lo
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ctz_i32_b32 s4, s3
v_readlane_b32 s5, v4, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, s4
s_add_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_12
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13sum_reductionPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13sum_reductionPiS_i, .Lfunc_end0-_Z13sum_reductionPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13sum_reductionPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13sum_reductionPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cassert>
#include <iostream>
#include <math.h>
#include <hip/hip_cooperative_groups.h>
using namespace cooperative_groups;
// Reduces a thread group to a single element
__device__ int reduce_sum(thread_group g, int *temp, int val){
int lane = g.thread_rank();
// Each thread adds its partial sum[i] to sum[lane+i]
for (int i = g.size() / 2; i > 0; i /= 2){
temp[lane] = val;
// wait for all threads to store
g.sync();
if (lane < i) {
val += temp[lane + i];
}
// wait for all threads to load
g.sync();
}
// note: only thread 0 will return full sum
return val;
}
// Creates partials sums from the original array
__device__ int thread_sum(int *input, int n){
int sum = 0;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = tid; i < n / 4; i += blockDim.x * gridDim.x){
// Cast as int4
int4 in = ((int4*)input)[i];
sum += in.x + in.y + in.z + in.w;
}
return sum;
}
__global__ void sum_reduction(int *sum, int *input, int n){
// Create partial sums from the array
int my_sum = thread_sum(input, n);
// Dynamic shared memory allocation
extern __shared__ int temp[];
// Identifier for a TB
auto g = this_thread_block();
// Reudce each TB
int block_sum = reduce_sum(g, temp, my_sum);
// Collect the partial result from each TB
if (g.thread_rank() == 0) {
atomicAdd(sum, block_sum);
}
}
void initialize_vector(int *v, int n) {
for (int i = 0; i < n; i++) {
v[i] = 1;//rand() % 10;
}
}
int main() {
int n = 1<<13;
size_t bytes = n * sizeof(int);
int *sum, *data;
hipMallocManaged(&sum, sizeof(int));
hipMallocManaged(&data, bytes);
initialize_vector(data,n);
int TB_SIZE = 256;
int GRID = (n + TB_SIZE -1 ) / TB_SIZE;
sum_reduction<<<GRID,TB_SIZE, n*sizeof(int)>>>(sum,data,n);
hipDeviceSynchronize();
assert(*sum == 8192);
printf("Done\n");
return 0;
} | .text
.file "groups.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__sum_reductionPiS_i # -- Begin function _Z28__device_stub__sum_reductionPiS_i
.p2align 4, 0x90
.type _Z28__device_stub__sum_reductionPiS_i,@function
_Z28__device_stub__sum_reductionPiS_i: # @_Z28__device_stub__sum_reductionPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13sum_reductionPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__sum_reductionPiS_i, .Lfunc_end0-_Z28__device_stub__sum_reductionPiS_i
.cfi_endproc
# -- End function
.globl _Z17initialize_vectorPii # -- Begin function _Z17initialize_vectorPii
.p2align 4, 0x90
.type _Z17initialize_vectorPii,@function
_Z17initialize_vectorPii: # @_Z17initialize_vectorPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z17initialize_vectorPii, .Lfunc_end1-_Z17initialize_vectorPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 24(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 16(%rsp), %rcx
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rcx,%rax,4)
incq %rax
cmpq $8192, %rax # imm = 0x2000
jne .LBB2_1
# %bb.2: # %_Z17initialize_vectorPii.exit
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
movl $32768, %r8d # imm = 0x8000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $8192, 12(%rsp) # imm = 0x2000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13sum_reductionPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13sum_reductionPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13sum_reductionPiS_i,@object # @_Z13sum_reductionPiS_i
.section .rodata,"a",@progbits
.globl _Z13sum_reductionPiS_i
.p2align 3, 0x0
_Z13sum_reductionPiS_i:
.quad _Z28__device_stub__sum_reductionPiS_i
.size _Z13sum_reductionPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13sum_reductionPiS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Done"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__sum_reductionPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13sum_reductionPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13sum_reductionPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x1a0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0040*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR5 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011405 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0080*/ ULEA.HI UR4, UR4, UR5, URZ, 0x2 ; /* 0x0000000504047291 */
/* 0x000fe2000f8f103f */
/*0090*/ S2R R2, SR_TID.Z ; /* 0x0000000000027919 */
/* 0x000e660000002300 */
/*00a0*/ USHF.R.S32.HI UR4, URZ, 0x2, UR4 ; /* 0x000000023f047899 */
/* 0x000fe20008011404 */
/*00b0*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ea20000002200 */
/*00c0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00e0*/ @P0 BRA 0x190 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x006fe400000001ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0205 */
/*0120*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1d00 */
/*0130*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*0150*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe4000bf06270 */
/*0160*/ IADD3 R8, R4, R5, R8 ; /* 0x0000000504087210 */
/* 0x004fc80007ffe008 */
/*0170*/ IADD3 R8, R7, R8, R6 ; /* 0x0000000807087210 */
/* 0x000fce0007ffe006 */
/*0180*/ @!P0 BRA 0x100 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x006fea0003800000 */
/*01a0*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ IMAD R0, R2, c[0x0][0x4], R9 ; /* 0x0000010002007a24 */
/* 0x000fe200078e0209 */
/*01c0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*01d0*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fe40007ffe1ff */
/*01e0*/ ULDC UR5, c[0x0][0x8] ; /* 0x0000020000057ab9 */
/* 0x000fe20000000800 */
/*01f0*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fe200078e02ff */
/*0200*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc8000f8e023f */
/*0210*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0220*/ ISETP.NE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fca0003f05270 */
/*0230*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*0240*/ @!P1 BRA 0x330 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fe400078e0203 */
/*0260*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fc6000f8e00ff */
/*0270*/ SHF.L.U32 R5, R3, 0x2, RZ ; /* 0x0000000203057819 */
/* 0x000fe400000006ff */
/*0280*/ ISETP.GT.AND P1, PT, R0.reuse, R3, PT ; /* 0x000000030000720c */
/* 0x040fe20003f24270 */
/*0290*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x000fe80000004800 */
/*02a0*/ BAR.SYNC 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000000000 */
/*02b0*/ ISETP.GT.AND P2, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc40003f44270 */
/*02c0*/ @P1 IMAD R2, R0.reuse, 0x4, R5 ; /* 0x0000000400021824 */
/* 0x040fe200078e0205 */
/*02d0*/ LEA.HI R4, R0, R0, RZ, 0x1 ; /* 0x0000000000047211 */
/* 0x000fc800078f08ff */
/*02e0*/ @P1 LDS R7, [R2] ; /* 0x0000000002071984 */
/* 0x000e220000000800 */
/*02f0*/ SHF.R.S32.HI R0, RZ, 0x1, R4 ; /* 0x00000001ff007819 */
/* 0x000fe20000011404 */
/*0300*/ @P1 IMAD.IADD R8, R8, 0x1, R7 ; /* 0x0000000108081824 */
/* 0x001fe400078e0207 */
/*0310*/ BAR.SYNC 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000000000 */
/*0320*/ @P2 BRA 0x280 ; /* 0xffffff5000002947 */
/* 0x000fea000383ffff */
/*0330*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0340*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0350*/ REDUX.SUM UR5, R8 ; /* 0x00000000080573c4 */
/* 0x000e62000000c000 */
/*0360*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0370*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0380*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*03a0*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe4000bf02070 */
/*03b0*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x002fd60008000f00 */
/*03c0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x000fe2000c10e186 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13sum_reductionPiS_i
.globl _Z13sum_reductionPiS_i
.p2align 8
.type _Z13sum_reductionPiS_i,@function
_Z13sum_reductionPiS_i:
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s15, s8
s_cselect_b32 s4, 12, 18
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s4
s_load_b32 s4, s[0:1], 0x10
global_load_u16 v5, v1, s[2:3]
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s5, s5, 30
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_ashr_i32 s7, s4, 2
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, s15, v5, v[1:2]
v_cmpx_gt_i32_e64 s7, v2
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x8
v_mul_lo_u32 v5, s8, v5
v_mov_b32_e32 v4, 0
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[6:7], 4, v[2:3]
v_add_nc_u32_e32 v2, v2, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s7, v2
global_load_b128 v[6:9], v[6:7], off
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add3_u32 v3, v6, v4, v7
v_add3_u32 v4, v3, v8, v9
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s8
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[4:5], s[2:3], 0xc
v_bfe_u32 v5, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s4, 0xffff
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s5, 0xffff
s_mul_i32 s5, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s5, s4
s_cmp_lt_u32 s4, 2
s_cbranch_scc1 .LBB0_10
v_mad_u32_u24 v6, v0, s3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v6, s2, v[1:2]
v_lshl_add_u32 v3, v2, 2, 0
.p2align 6
.LBB0_6:
s_lshr_b32 s5, s4, 1
s_mov_b32 s6, exec_lo
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s5, v2
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v6, s5, 2, v3
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v6, v4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_gt_u32 s4, 3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
s_mov_b32 s4, s5
s_branch .LBB0_6
.LBB0_10:
v_mad_u32_u24 v0, v0, s3, v5
v_sub_nc_u32_e32 v1, 0, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
s_mov_b32 s2, 0
v_cmpx_eq_u32_e64 v0, v1
s_cbranch_execz .LBB0_15
s_mov_b32 s3, exec_lo
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ctz_i32_b32 s4, s3
v_readlane_b32 s5, v4, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s3, s3, s4
s_add_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_12
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13sum_reductionPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13sum_reductionPiS_i, .Lfunc_end0-_Z13sum_reductionPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13sum_reductionPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13sum_reductionPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019b296_00000000-6_groups.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6872:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6872:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii
.type _Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii, @function
_Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii:
.LFB6866:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE6866:
.size _Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii, .-_Z10reduce_sumN18cooperative_groups4__v112thread_groupEPii
.globl _Z10thread_sumPii
.type _Z10thread_sumPii, @function
_Z10thread_sumPii:
.LFB6867:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE6867:
.size _Z10thread_sumPii, .-_Z10thread_sumPii
.globl _Z17initialize_vectorPii
.type _Z17initialize_vectorPii, @function
_Z17initialize_vectorPii:
.LFB6868:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L7
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L9:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L9
.L7:
ret
.cfi_endproc
.LFE6868:
.size _Z17initialize_vectorPii, .-_Z17initialize_vectorPii
.globl _Z36__device_stub__Z13sum_reductionPiS_iPiS_i
.type _Z36__device_stub__Z13sum_reductionPiS_iPiS_i, @function
_Z36__device_stub__Z13sum_reductionPiS_iPiS_i:
.LFB6894:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13sum_reductionPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6894:
.size _Z36__device_stub__Z13sum_reductionPiS_iPiS_i, .-_Z36__device_stub__Z13sum_reductionPiS_iPiS_i
.globl _Z13sum_reductionPiS_i
.type _Z13sum_reductionPiS_i, @function
_Z13sum_reductionPiS_i:
.LFB6895:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13sum_reductionPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6895:
.size _Z13sum_reductionPiS_i, .-_Z13sum_reductionPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Done\n"
.text
.globl main
.type main, @function
main:
.LFB6869:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $32768, %esi
call cudaMallocManaged@PLT
movl $8192, %esi
movq 8(%rsp), %rdi
call _Z17initialize_vectorPii
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $32768, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
call cudaDeviceSynchronize@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $8192, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z36__device_stub__Z13sum_reductionPiS_iPiS_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6869:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z13sum_reductionPiS_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_ZN39_INTERNAL_978cdd9e_9_groups_cu_115040b94cuda3std3__419piecewise_constructE"
.align 8
.LC3:
.string "_ZN39_INTERNAL_978cdd9e_9_groups_cu_115040b94cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC4:
.string "_ZN39_INTERNAL_978cdd9e_9_groups_cu_115040b94cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6897:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13sum_reductionPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6897:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "groups.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__sum_reductionPiS_i # -- Begin function _Z28__device_stub__sum_reductionPiS_i
.p2align 4, 0x90
.type _Z28__device_stub__sum_reductionPiS_i,@function
_Z28__device_stub__sum_reductionPiS_i: # @_Z28__device_stub__sum_reductionPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13sum_reductionPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__sum_reductionPiS_i, .Lfunc_end0-_Z28__device_stub__sum_reductionPiS_i
.cfi_endproc
# -- End function
.globl _Z17initialize_vectorPii # -- Begin function _Z17initialize_vectorPii
.p2align 4, 0x90
.type _Z17initialize_vectorPii,@function
_Z17initialize_vectorPii: # @_Z17initialize_vectorPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z17initialize_vectorPii, .Lfunc_end1-_Z17initialize_vectorPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 24(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 16(%rsp), %rcx
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rcx,%rax,4)
incq %rax
cmpq $8192, %rax # imm = 0x2000
jne .LBB2_1
# %bb.2: # %_Z17initialize_vectorPii.exit
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
movl $32768, %r8d # imm = 0x8000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $8192, 12(%rsp) # imm = 0x2000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13sum_reductionPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13sum_reductionPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13sum_reductionPiS_i,@object # @_Z13sum_reductionPiS_i
.section .rodata,"a",@progbits
.globl _Z13sum_reductionPiS_i
.p2align 3, 0x0
_Z13sum_reductionPiS_i:
.quad _Z28__device_stub__sum_reductionPiS_i
.size _Z13sum_reductionPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13sum_reductionPiS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Done"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__sum_reductionPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13sum_reductionPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_set_vector_to_zero(double *d_vec, int dimension)
{
int iam = threadIdx.x;
int bid = blockIdx.x;
int threads_in_block = blockDim.x;
int gid = bid*threads_in_block + iam;
if (gid < dimension){
d_vec[gid] = 0;
}
} | code for sm_80
Function : _Z25kernel_set_vector_to_zeroPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_set_vector_to_zero(double *d_vec, int dimension)
{
int iam = threadIdx.x;
int bid = blockIdx.x;
int threads_in_block = blockDim.x;
int gid = bid*threads_in_block + iam;
if (gid < dimension){
d_vec[gid] = 0;
}
} | .file "tmpxft_00119dd8_00000000-6_kernel_set_vector_to_zero.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z25kernel_set_vector_to_zeroPdiPdi
.type _Z46__device_stub__Z25kernel_set_vector_to_zeroPdiPdi, @function
_Z46__device_stub__Z25kernel_set_vector_to_zeroPdiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25kernel_set_vector_to_zeroPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z25kernel_set_vector_to_zeroPdiPdi, .-_Z46__device_stub__Z25kernel_set_vector_to_zeroPdiPdi
.globl _Z25kernel_set_vector_to_zeroPdi
.type _Z25kernel_set_vector_to_zeroPdi, @function
_Z25kernel_set_vector_to_zeroPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z25kernel_set_vector_to_zeroPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25kernel_set_vector_to_zeroPdi, .-_Z25kernel_set_vector_to_zeroPdi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25kernel_set_vector_to_zeroPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25kernel_set_vector_to_zeroPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_set_vector_to_zero(double *d_vec, int dimension)
{
int iam = threadIdx.x;
int bid = blockIdx.x;
int threads_in_block = blockDim.x;
int gid = bid*threads_in_block + iam;
if (gid < dimension){
d_vec[gid] = 0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_set_vector_to_zero(double *d_vec, int dimension)
{
int iam = threadIdx.x;
int bid = blockIdx.x;
int threads_in_block = blockDim.x;
int gid = bid*threads_in_block + iam;
if (gid < dimension){
d_vec[gid] = 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_set_vector_to_zero(double *d_vec, int dimension)
{
int iam = threadIdx.x;
int bid = blockIdx.x;
int threads_in_block = blockDim.x;
int gid = bid*threads_in_block + iam;
if (gid < dimension){
d_vec[gid] = 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25kernel_set_vector_to_zeroPdi
.globl _Z25kernel_set_vector_to_zeroPdi
.p2align 8
.type _Z25kernel_set_vector_to_zeroPdi,@function
_Z25kernel_set_vector_to_zeroPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25kernel_set_vector_to_zeroPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25kernel_set_vector_to_zeroPdi, .Lfunc_end0-_Z25kernel_set_vector_to_zeroPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25kernel_set_vector_to_zeroPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25kernel_set_vector_to_zeroPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_set_vector_to_zero(double *d_vec, int dimension)
{
int iam = threadIdx.x;
int bid = blockIdx.x;
int threads_in_block = blockDim.x;
int gid = bid*threads_in_block + iam;
if (gid < dimension){
d_vec[gid] = 0;
}
} | .text
.file "kernel_set_vector_to_zero.hip"
.globl _Z40__device_stub__kernel_set_vector_to_zeroPdi # -- Begin function _Z40__device_stub__kernel_set_vector_to_zeroPdi
.p2align 4, 0x90
.type _Z40__device_stub__kernel_set_vector_to_zeroPdi,@function
_Z40__device_stub__kernel_set_vector_to_zeroPdi: # @_Z40__device_stub__kernel_set_vector_to_zeroPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25kernel_set_vector_to_zeroPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z40__device_stub__kernel_set_vector_to_zeroPdi, .Lfunc_end0-_Z40__device_stub__kernel_set_vector_to_zeroPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25kernel_set_vector_to_zeroPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25kernel_set_vector_to_zeroPdi,@object # @_Z25kernel_set_vector_to_zeroPdi
.section .rodata,"a",@progbits
.globl _Z25kernel_set_vector_to_zeroPdi
.p2align 3, 0x0
_Z25kernel_set_vector_to_zeroPdi:
.quad _Z40__device_stub__kernel_set_vector_to_zeroPdi
.size _Z25kernel_set_vector_to_zeroPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25kernel_set_vector_to_zeroPdi"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__kernel_set_vector_to_zeroPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25kernel_set_vector_to_zeroPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25kernel_set_vector_to_zeroPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25kernel_set_vector_to_zeroPdi
.globl _Z25kernel_set_vector_to_zeroPdi
.p2align 8
.type _Z25kernel_set_vector_to_zeroPdi,@function
_Z25kernel_set_vector_to_zeroPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25kernel_set_vector_to_zeroPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25kernel_set_vector_to_zeroPdi, .Lfunc_end0-_Z25kernel_set_vector_to_zeroPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25kernel_set_vector_to_zeroPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25kernel_set_vector_to_zeroPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00119dd8_00000000-6_kernel_set_vector_to_zero.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z25kernel_set_vector_to_zeroPdiPdi
.type _Z46__device_stub__Z25kernel_set_vector_to_zeroPdiPdi, @function
_Z46__device_stub__Z25kernel_set_vector_to_zeroPdiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25kernel_set_vector_to_zeroPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z25kernel_set_vector_to_zeroPdiPdi, .-_Z46__device_stub__Z25kernel_set_vector_to_zeroPdiPdi
.globl _Z25kernel_set_vector_to_zeroPdi
.type _Z25kernel_set_vector_to_zeroPdi, @function
_Z25kernel_set_vector_to_zeroPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z25kernel_set_vector_to_zeroPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25kernel_set_vector_to_zeroPdi, .-_Z25kernel_set_vector_to_zeroPdi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25kernel_set_vector_to_zeroPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25kernel_set_vector_to_zeroPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_set_vector_to_zero.hip"
.globl _Z40__device_stub__kernel_set_vector_to_zeroPdi # -- Begin function _Z40__device_stub__kernel_set_vector_to_zeroPdi
.p2align 4, 0x90
.type _Z40__device_stub__kernel_set_vector_to_zeroPdi,@function
_Z40__device_stub__kernel_set_vector_to_zeroPdi: # @_Z40__device_stub__kernel_set_vector_to_zeroPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25kernel_set_vector_to_zeroPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z40__device_stub__kernel_set_vector_to_zeroPdi, .Lfunc_end0-_Z40__device_stub__kernel_set_vector_to_zeroPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25kernel_set_vector_to_zeroPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25kernel_set_vector_to_zeroPdi,@object # @_Z25kernel_set_vector_to_zeroPdi
.section .rodata,"a",@progbits
.globl _Z25kernel_set_vector_to_zeroPdi
.p2align 3, 0x0
_Z25kernel_set_vector_to_zeroPdi:
.quad _Z40__device_stub__kernel_set_vector_to_zeroPdi
.size _Z25kernel_set_vector_to_zeroPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25kernel_set_vector_to_zeroPdi"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__kernel_set_vector_to_zeroPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25kernel_set_vector_to_zeroPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // cuda_example3.cu : Defines the entry point for the console application.
//
#include <stdio.h>
#include <cuda.h>
#include <string.h>
#define A(x,y) A[M*x+y]
#define a_h(x,y) a_h[M*x+y]
typedef struct cudaDeviceProp cudaDevProp_t;
// Kernel that executes on the CUDA device
__global__ void foo( float *A, int N, int M)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if ( idx < N ){ //aqui idx representa a linha. Cada elemento (idx,y) e gerado
for(int i = 0; i<M; ++i){
A(idx,i) = M*idx+i;
}
}
}
// main routine that executes on the host
int main( void )
{
float *a_h, *a_d;
const int N = 1000;
const int M = 10000;
int ct, dev;
cudaDevProp_t prop;
cudaGetDeviceCount(&ct); //is there a cuda device??
if(ct == 0){
printf("\nNo CUDA device found.\n");
exit(0);
}
cudaGetDevice(&dev);
cudaGetDeviceProperties(&prop,dev);
int block_size = prop.maxThreadsPerBlock; //maior quantidade de threads permitida em um bloco unidimensional
int n_blocks = N*M / block_size + ( N % block_size == 0 ? 0 : 1 );
size_t size = N * M *sizeof( float );
a_h = (float *)malloc( size ); //Tudo sera alocado da mesma forma, pois temos matriz A[N*M] mas estamos visualizando A[N][M]
cudaMalloc( (void **)&a_d, size );
cudaMemcpy( a_d, a_h, size, cudaMemcpyHostToDevice );
foo <<< n_blocks, block_size >>> ( a_d, N,M );
cudaMemcpy( a_h, a_d, sizeof( float ) * N * M, cudaMemcpyDeviceToHost ); //recuperando resultados
/*for ( int i = 0; i < N; i++ ){
printf("%d[ ", i);
for(int j = 0; j<M; ++j){
printf( "%d ",(int)a_h(i,j) );
}
puts(" ]");
puts("\n");
}*/
printf("\n\n%d\n\n", (int)a_h((N-1),(M-1)));
free( a_h );
cudaFree( a_d );
return 0;
} | code for sm_80
Function : _Z3fooPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x168], !P0 ; /* 0x00005a0004007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*00d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f05270 */
/*00e0*/ @!P1 BRA 0x2b0 ; /* 0x000001c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R12, R0, -c[0x0][0x16c], RZ ; /* 0x80005b00000c7a10 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD R6, R4, c[0x0][0x16c], RZ ; /* 0x00005b0004067a24 */
/* 0x000fe400078e02ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.WIDE R2, R6.reuse, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x040fe200078e0203 */
/*0140*/ IADD3 R6, R6, 0x3, RZ ; /* 0x0000000306067810 */
/* 0x000fc60007ffe0ff */
/*0150*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*0160*/ IMAD.MOV.U32 R15, RZ, RZ, R3 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0003 */
/*0170*/ IADD3 R2, R6.reuse, -0x3, RZ ; /* 0xfffffffd06027810 */
/* 0x041fe20007ffe0ff */
/*0180*/ I2F R13, R6 ; /* 0x00000006000d7306 */
/* 0x0000620000201400 */
/*0190*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ IADD3 R3, R6.reuse, -0x2, RZ ; /* 0xfffffffe06037810 */
/* 0x040fe40007ffe0ff */
/*01b0*/ IADD3 R8, R6, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x000fc60007ffe0ff */
/*01c0*/ I2F R7, R2 ; /* 0x0000000200077306 */
/* 0x0004e20000201400 */
/*01d0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x001fce0007ffe0ff */
/*01e0*/ I2F R9, R3 ; /* 0x0000000300097306 */
/* 0x0001220000201400 */
/*01f0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x004fe400078e000a */
/*0200*/ IMAD.IADD R10, R12, 0x1, R5 ; /* 0x000000010c0a7824 */
/* 0x000fca00078e0205 */
/*0210*/ I2F R11, R8 ; /* 0x00000008000b7306 */
/* 0x000ea20000201400 */
/*0220*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x001fe200078e000f */
/*0240*/ IADD3 R10, P2, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fc80007f5e0ff */
/*0250*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x0021e2000c101904 */
/*0260*/ IMAD.X R15, RZ, RZ, R3, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fc600010e0603 */
/*0270*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0081e8000c101904 */
/*0280*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x0101e8000c101904 */
/*0290*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x0041e2000c101904 */
/*02a0*/ @P1 BRA 0x170 ; /* 0xfffffec000001947 */
/* 0x000fea000383ffff */
/*02b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fe400078e00ff */
/*02d0*/ IMAD R4, R4, c[0x0][0x16c], R5 ; /* 0x00005b0004047a24 */
/* 0x000fc800078e0205 */
/*02e0*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0203 */
/*02f0*/ I2F R5, R4 ; /* 0x0000000400057306 */
/* 0x0000620000201400 */
/*0300*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0310*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0320*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x001fe20007ffe0ff */
/*0330*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0021e4000c101904 */
/*0340*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f3e0ff */
/*0350*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fc600008e0603 */
/*0360*/ @P0 BRA 0x2f0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // cuda_example3.cu : Defines the entry point for the console application.
//
#include <stdio.h>
#include <cuda.h>
#include <string.h>
#define A(x,y) A[M*x+y]
#define a_h(x,y) a_h[M*x+y]
typedef struct cudaDeviceProp cudaDevProp_t;
// Kernel that executes on the CUDA device
__global__ void foo( float *A, int N, int M)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if ( idx < N ){ //aqui idx representa a linha. Cada elemento (idx,y) e gerado
for(int i = 0; i<M; ++i){
A(idx,i) = M*idx+i;
}
}
}
// main routine that executes on the host
int main( void )
{
float *a_h, *a_d;
const int N = 1000;
const int M = 10000;
int ct, dev;
cudaDevProp_t prop;
cudaGetDeviceCount(&ct); //is there a cuda device??
if(ct == 0){
printf("\nNo CUDA device found.\n");
exit(0);
}
cudaGetDevice(&dev);
cudaGetDeviceProperties(&prop,dev);
int block_size = prop.maxThreadsPerBlock; //maior quantidade de threads permitida em um bloco unidimensional
int n_blocks = N*M / block_size + ( N % block_size == 0 ? 0 : 1 );
size_t size = N * M *sizeof( float );
a_h = (float *)malloc( size ); //Tudo sera alocado da mesma forma, pois temos matriz A[N*M] mas estamos visualizando A[N][M]
cudaMalloc( (void **)&a_d, size );
cudaMemcpy( a_d, a_h, size, cudaMemcpyHostToDevice );
foo <<< n_blocks, block_size >>> ( a_d, N,M );
cudaMemcpy( a_h, a_d, sizeof( float ) * N * M, cudaMemcpyDeviceToHost ); //recuperando resultados
/*for ( int i = 0; i < N; i++ ){
printf("%d[ ", i);
for(int j = 0; j<M; ++j){
printf( "%d ",(int)a_h(i,j) );
}
puts(" ]");
puts("\n");
}*/
printf("\n\n%d\n\n", (int)a_h((N-1),(M-1)));
free( a_h );
cudaFree( a_d );
return 0;
} | .file "tmpxft_000c5131_00000000-6_first_sample_2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3fooPfiiPfii
.type _Z24__device_stub__Z3fooPfiiPfii, @function
_Z24__device_stub__Z3fooPfiiPfii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3fooPfiiPfii, .-_Z24__device_stub__Z3fooPfiiPfii
.globl _Z3fooPfii
.type _Z3fooPfii, @function
_Z3fooPfii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3fooPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3fooPfii, .-_Z3fooPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nNo CUDA device found.\n"
.LC1:
.string "\n\n%d\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1088, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 8(%rsp)
jne .L12
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 48(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl 368(%rsp), %ebp
movl $1000, %eax
movl $0, %edx
idivl %ebp
testl %edx, %edx
setne %r12b
movzbl %r12b, %r12d
movl $10000000, %eax
movl $0, %edx
idivl %ebp
addl %eax, %r12d
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl %r12d, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movl $40000000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
cvttss2sil 39999996(%rbx), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L17
movl $0, %eax
addq $1088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $10000, %edx
movl $1000, %esi
movq 16(%rsp), %rdi
call _Z24__device_stub__Z3fooPfiiPfii
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3fooPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // cuda_example3.cu : Defines the entry point for the console application.
//
#include <stdio.h>
#include <cuda.h>
#include <string.h>
#define A(x,y) A[M*x+y]
#define a_h(x,y) a_h[M*x+y]
typedef struct cudaDeviceProp cudaDevProp_t;
// Kernel that executes on the CUDA device
__global__ void foo( float *A, int N, int M)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if ( idx < N ){ //aqui idx representa a linha. Cada elemento (idx,y) e gerado
for(int i = 0; i<M; ++i){
A(idx,i) = M*idx+i;
}
}
}
// main routine that executes on the host
int main( void )
{
float *a_h, *a_d;
const int N = 1000;
const int M = 10000;
int ct, dev;
cudaDevProp_t prop;
cudaGetDeviceCount(&ct); //is there a cuda device??
if(ct == 0){
printf("\nNo CUDA device found.\n");
exit(0);
}
cudaGetDevice(&dev);
cudaGetDeviceProperties(&prop,dev);
int block_size = prop.maxThreadsPerBlock; //maior quantidade de threads permitida em um bloco unidimensional
int n_blocks = N*M / block_size + ( N % block_size == 0 ? 0 : 1 );
size_t size = N * M *sizeof( float );
a_h = (float *)malloc( size ); //Tudo sera alocado da mesma forma, pois temos matriz A[N*M] mas estamos visualizando A[N][M]
cudaMalloc( (void **)&a_d, size );
cudaMemcpy( a_d, a_h, size, cudaMemcpyHostToDevice );
foo <<< n_blocks, block_size >>> ( a_d, N,M );
cudaMemcpy( a_h, a_d, sizeof( float ) * N * M, cudaMemcpyDeviceToHost ); //recuperando resultados
/*for ( int i = 0; i < N; i++ ){
printf("%d[ ", i);
for(int j = 0; j<M; ++j){
printf( "%d ",(int)a_h(i,j) );
}
puts(" ]");
puts("\n");
}*/
printf("\n\n%d\n\n", (int)a_h((N-1),(M-1)));
free( a_h );
cudaFree( a_d );
return 0;
} | // cuda_example3.cu : Defines the entry point for the console application.
//
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <string.h>
#define A(x,y) A[M*x+y]
#define a_h(x,y) a_h[M*x+y]
typedef struct hipDeviceProp_t cudaDevProp_t;
// Kernel that executes on the CUDA device
__global__ void foo( float *A, int N, int M)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if ( idx < N ){ //aqui idx representa a linha. Cada elemento (idx,y) e gerado
for(int i = 0; i<M; ++i){
A(idx,i) = M*idx+i;
}
}
}
// main routine that executes on the host
int main( void )
{
float *a_h, *a_d;
const int N = 1000;
const int M = 10000;
int ct, dev;
cudaDevProp_t prop;
hipGetDeviceCount(&ct); //is there a cuda device??
if(ct == 0){
printf("\nNo CUDA device found.\n");
exit(0);
}
hipGetDevice(&dev);
hipGetDeviceProperties(&prop,dev);
int block_size = prop.maxThreadsPerBlock; //maior quantidade de threads permitida em um bloco unidimensional
int n_blocks = N*M / block_size + ( N % block_size == 0 ? 0 : 1 );
size_t size = N * M *sizeof( float );
a_h = (float *)malloc( size ); //Tudo sera alocado da mesma forma, pois temos matriz A[N*M] mas estamos visualizando A[N][M]
hipMalloc( (void **)&a_d, size );
hipMemcpy( a_d, a_h, size, hipMemcpyHostToDevice );
foo <<< n_blocks, block_size >>> ( a_d, N,M );
hipMemcpy( a_h, a_d, sizeof( float ) * N * M, hipMemcpyDeviceToHost ); //recuperando resultados
/*for ( int i = 0; i < N; i++ ){
printf("%d[ ", i);
for(int j = 0; j<M; ++j){
printf( "%d ",(int)a_h(i,j) );
}
puts(" ]");
puts("\n");
}*/
printf("\n\n%d\n\n", (int)a_h((N-1),(M-1)));
free( a_h );
hipFree( a_d );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // cuda_example3.cu : Defines the entry point for the console application.
//
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <string.h>
#define A(x,y) A[M*x+y]
#define a_h(x,y) a_h[M*x+y]
typedef struct hipDeviceProp_t cudaDevProp_t;
// Kernel that executes on the CUDA device
__global__ void foo( float *A, int N, int M)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if ( idx < N ){ //aqui idx representa a linha. Cada elemento (idx,y) e gerado
for(int i = 0; i<M; ++i){
A(idx,i) = M*idx+i;
}
}
}
// main routine that executes on the host
int main( void )
{
float *a_h, *a_d;
const int N = 1000;
const int M = 10000;
int ct, dev;
cudaDevProp_t prop;
hipGetDeviceCount(&ct); //is there a cuda device??
if(ct == 0){
printf("\nNo CUDA device found.\n");
exit(0);
}
hipGetDevice(&dev);
hipGetDeviceProperties(&prop,dev);
int block_size = prop.maxThreadsPerBlock; //maior quantidade de threads permitida em um bloco unidimensional
int n_blocks = N*M / block_size + ( N % block_size == 0 ? 0 : 1 );
size_t size = N * M *sizeof( float );
a_h = (float *)malloc( size ); //Tudo sera alocado da mesma forma, pois temos matriz A[N*M] mas estamos visualizando A[N][M]
hipMalloc( (void **)&a_d, size );
hipMemcpy( a_d, a_h, size, hipMemcpyHostToDevice );
foo <<< n_blocks, block_size >>> ( a_d, N,M );
hipMemcpy( a_h, a_d, sizeof( float ) * N * M, hipMemcpyDeviceToHost ); //recuperando resultados
/*for ( int i = 0; i < N; i++ ){
printf("%d[ ", i);
for(int j = 0; j<M; ++j){
printf( "%d ",(int)a_h(i,j) );
}
puts(" ]");
puts("\n");
}*/
printf("\n\n%d\n\n", (int)a_h((N-1),(M-1)));
free( a_h );
hipFree( a_d );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPfii
.globl _Z3fooPfii
.p2align 8
.type _Z3fooPfii,@function
_Z3fooPfii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_cselect_b32 s2, -1, 0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_lo_u32 v0, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
.LBB0_2:
v_cvt_f32_i32_e32 v3, v0
v_add_nc_u32_e32 v0, 1, v0
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s3, 0
global_store_b32 v[1:2], v3, off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPfii, .Lfunc_end0-_Z3fooPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3fooPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // cuda_example3.cu : Defines the entry point for the console application.
//
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <string.h>
#define A(x,y) A[M*x+y]
#define a_h(x,y) a_h[M*x+y]
typedef struct hipDeviceProp_t cudaDevProp_t;
// Kernel that executes on the CUDA device
__global__ void foo( float *A, int N, int M)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if ( idx < N ){ //aqui idx representa a linha. Cada elemento (idx,y) e gerado
for(int i = 0; i<M; ++i){
A(idx,i) = M*idx+i;
}
}
}
// main routine that executes on the host
int main( void )
{
float *a_h, *a_d;
const int N = 1000;
const int M = 10000;
int ct, dev;
cudaDevProp_t prop;
hipGetDeviceCount(&ct); //is there a cuda device??
if(ct == 0){
printf("\nNo CUDA device found.\n");
exit(0);
}
hipGetDevice(&dev);
hipGetDeviceProperties(&prop,dev);
int block_size = prop.maxThreadsPerBlock; //maior quantidade de threads permitida em um bloco unidimensional
int n_blocks = N*M / block_size + ( N % block_size == 0 ? 0 : 1 );
size_t size = N * M *sizeof( float );
a_h = (float *)malloc( size ); //Tudo sera alocado da mesma forma, pois temos matriz A[N*M] mas estamos visualizando A[N][M]
hipMalloc( (void **)&a_d, size );
hipMemcpy( a_d, a_h, size, hipMemcpyHostToDevice );
foo <<< n_blocks, block_size >>> ( a_d, N,M );
hipMemcpy( a_h, a_d, sizeof( float ) * N * M, hipMemcpyDeviceToHost ); //recuperando resultados
/*for ( int i = 0; i < N; i++ ){
printf("%d[ ", i);
for(int j = 0; j<M; ++j){
printf( "%d ",(int)a_h(i,j) );
}
puts(" ]");
puts("\n");
}*/
printf("\n\n%d\n\n", (int)a_h((N-1),(M-1)));
free( a_h );
hipFree( a_d );
return 0;
} | .text
.file "first_sample_2d.hip"
.globl _Z18__device_stub__fooPfii # -- Begin function _Z18__device_stub__fooPfii
.p2align 4, 0x90
.type _Z18__device_stub__fooPfii,@function
_Z18__device_stub__fooPfii: # @_Z18__device_stub__fooPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3fooPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPfii, .Lfunc_end0-_Z18__device_stub__fooPfii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 1616
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
je .LBB1_4
# %bb.1:
leaq 8(%rsp), %rdi
callq hipGetDevice
movl 8(%rsp), %esi
leaq 112(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl 432(%rsp), %r14d
movl $10000000, %eax # imm = 0x989680
xorl %edx, %edx
idivl %r14d
movl %eax, %r15d
movl $1000, %eax # imm = 0x3E8
xorl %edx, %edx
idivl %r14d
cmpl $1, %edx
sbbl $-1, %r15d
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq (%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
orq %rax, %r14
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movl $1000, 20(%rsp) # imm = 0x3E8
movl $10000, 16(%rsp) # imm = 0x2710
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3fooPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
movq (%rsp), %rsi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
cvttss2si 39999996(%rbx), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 1616
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPfii,@object # @_Z3fooPfii
.section .rodata,"a",@progbits
.globl _Z3fooPfii
.p2align 3, 0x0
_Z3fooPfii:
.quad _Z18__device_stub__fooPfii
.size _Z3fooPfii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\n\n%d\n\n"
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3fooPfii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nNo CUDA device found."
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3fooPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x168], !P0 ; /* 0x00005a0004007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*00d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f05270 */
/*00e0*/ @!P1 BRA 0x2b0 ; /* 0x000001c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R12, R0, -c[0x0][0x16c], RZ ; /* 0x80005b00000c7a10 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD R6, R4, c[0x0][0x16c], RZ ; /* 0x00005b0004067a24 */
/* 0x000fe400078e02ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.WIDE R2, R6.reuse, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x040fe200078e0203 */
/*0140*/ IADD3 R6, R6, 0x3, RZ ; /* 0x0000000306067810 */
/* 0x000fc60007ffe0ff */
/*0150*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*0160*/ IMAD.MOV.U32 R15, RZ, RZ, R3 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0003 */
/*0170*/ IADD3 R2, R6.reuse, -0x3, RZ ; /* 0xfffffffd06027810 */
/* 0x041fe20007ffe0ff */
/*0180*/ I2F R13, R6 ; /* 0x00000006000d7306 */
/* 0x0000620000201400 */
/*0190*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ IADD3 R3, R6.reuse, -0x2, RZ ; /* 0xfffffffe06037810 */
/* 0x040fe40007ffe0ff */
/*01b0*/ IADD3 R8, R6, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x000fc60007ffe0ff */
/*01c0*/ I2F R7, R2 ; /* 0x0000000200077306 */
/* 0x0004e20000201400 */
/*01d0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x001fce0007ffe0ff */
/*01e0*/ I2F R9, R3 ; /* 0x0000000300097306 */
/* 0x0001220000201400 */
/*01f0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x004fe400078e000a */
/*0200*/ IMAD.IADD R10, R12, 0x1, R5 ; /* 0x000000010c0a7824 */
/* 0x000fca00078e0205 */
/*0210*/ I2F R11, R8 ; /* 0x00000008000b7306 */
/* 0x000ea20000201400 */
/*0220*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x001fe200078e000f */
/*0240*/ IADD3 R10, P2, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fc80007f5e0ff */
/*0250*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x0021e2000c101904 */
/*0260*/ IMAD.X R15, RZ, RZ, R3, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fc600010e0603 */
/*0270*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0081e8000c101904 */
/*0280*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x0101e8000c101904 */
/*0290*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x0041e2000c101904 */
/*02a0*/ @P1 BRA 0x170 ; /* 0xfffffec000001947 */
/* 0x000fea000383ffff */
/*02b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fe400078e00ff */
/*02d0*/ IMAD R4, R4, c[0x0][0x16c], R5 ; /* 0x00005b0004047a24 */
/* 0x000fc800078e0205 */
/*02e0*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0203 */
/*02f0*/ I2F R5, R4 ; /* 0x0000000400057306 */
/* 0x0000620000201400 */
/*0300*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0310*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0320*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x001fe20007ffe0ff */
/*0330*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0021e4000c101904 */
/*0340*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f3e0ff */
/*0350*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fc600008e0603 */
/*0360*/ @P0 BRA 0x2f0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPfii
.globl _Z3fooPfii
.p2align 8
.type _Z3fooPfii,@function
_Z3fooPfii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_cselect_b32 s2, -1, 0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_lo_u32 v0, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
.LBB0_2:
v_cvt_f32_i32_e32 v3, v0
v_add_nc_u32_e32 v0, 1, v0
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s3, 0
global_store_b32 v[1:2], v3, off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPfii, .Lfunc_end0-_Z3fooPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3fooPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c5131_00000000-6_first_sample_2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3fooPfiiPfii
.type _Z24__device_stub__Z3fooPfiiPfii, @function
_Z24__device_stub__Z3fooPfiiPfii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3fooPfiiPfii, .-_Z24__device_stub__Z3fooPfiiPfii
.globl _Z3fooPfii
.type _Z3fooPfii, @function
_Z3fooPfii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3fooPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3fooPfii, .-_Z3fooPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nNo CUDA device found.\n"
.LC1:
.string "\n\n%d\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1088, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 8(%rsp)
jne .L12
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 48(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl 368(%rsp), %ebp
movl $1000, %eax
movl $0, %edx
idivl %ebp
testl %edx, %edx
setne %r12b
movzbl %r12b, %r12d
movl $10000000, %eax
movl $0, %edx
idivl %ebp
addl %eax, %r12d
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl %r12d, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movl $40000000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
cvttss2sil 39999996(%rbx), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L17
movl $0, %eax
addq $1088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $10000, %edx
movl $1000, %esi
movq 16(%rsp), %rdi
call _Z24__device_stub__Z3fooPfiiPfii
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3fooPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "first_sample_2d.hip"
.globl _Z18__device_stub__fooPfii # -- Begin function _Z18__device_stub__fooPfii
.p2align 4, 0x90
.type _Z18__device_stub__fooPfii,@function
_Z18__device_stub__fooPfii: # @_Z18__device_stub__fooPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3fooPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPfii, .Lfunc_end0-_Z18__device_stub__fooPfii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 1616
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
je .LBB1_4
# %bb.1:
leaq 8(%rsp), %rdi
callq hipGetDevice
movl 8(%rsp), %esi
leaq 112(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl 432(%rsp), %r14d
movl $10000000, %eax # imm = 0x989680
xorl %edx, %edx
idivl %r14d
movl %eax, %r15d
movl $1000, %eax # imm = 0x3E8
xorl %edx, %edx
idivl %r14d
cmpl $1, %edx
sbbl $-1, %r15d
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq (%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
orq %rax, %r14
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movl $1000, 20(%rsp) # imm = 0x3E8
movl $10000, 16(%rsp) # imm = 0x2710
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3fooPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
movq (%rsp), %rsi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
cvttss2si 39999996(%rbx), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 1616
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPfii,@object # @_Z3fooPfii
.section .rodata,"a",@progbits
.globl _Z3fooPfii
.p2align 3, 0x0
_Z3fooPfii:
.quad _Z18__device_stub__fooPfii
.size _Z3fooPfii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\n\n%d\n\n"
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3fooPfii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nNo CUDA device found."
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "stdio.h"
#define N 2048*2048 //Total threads
#define THREADS_PER_BLOCK 512
__global__ void add(int *a, int *b, int *c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x; //thread_no + block_no * no.ofthreads/block
c[index] = a[index] + b[index];
}
void random_ints(int* a, int n)
{
int i;
for(i =0; i<n; ++i){
a[i]=rand()/2000;
}
}
int main(void)
{
int *a,*b,*c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
a = (int*)malloc(size);
random_ints(a, N);
b = (int*)malloc(size);
random_ints(b, N);
c = (int*)malloc(size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
add<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
printf("%d + %d is %d\n", *a, *b, *c);
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
#define N 2048*2048 //Total threads
#define THREADS_PER_BLOCK 512
__global__ void add(int *a, int *b, int *c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x; //thread_no + block_no * no.ofthreads/block
c[index] = a[index] + b[index];
}
void random_ints(int* a, int n)
{
int i;
for(i =0; i<n; ++i){
a[i]=rand()/2000;
}
}
int main(void)
{
int *a,*b,*c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
a = (int*)malloc(size);
random_ints(a, N);
b = (int*)malloc(size);
random_ints(b, N);
c = (int*)malloc(size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
add<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
printf("%d + %d is %d\n", *a, *b, *c);
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_0009a1ea_00000000-6_newc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $39, %rdx
sarl $31, %eax
subl %eax, %edx
movl %edx, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d is %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl (%rbx), %ecx
movl 0(%rbp), %edx
movl (%r12), %r8d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
#define N 2048*2048 //Total threads
#define THREADS_PER_BLOCK 512
__global__ void add(int *a, int *b, int *c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x; //thread_no + block_no * no.ofthreads/block
c[index] = a[index] + b[index];
}
void random_ints(int* a, int n)
{
int i;
for(i =0; i<n; ++i){
a[i]=rand()/2000;
}
}
int main(void)
{
int *a,*b,*c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
a = (int*)malloc(size);
random_ints(a, N);
b = (int*)malloc(size);
random_ints(b, N);
c = (int*)malloc(size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
add<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
printf("%d + %d is %d\n", *a, *b, *c);
free(a);
free(b);
free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include "stdio.h"
#define N 2048*2048 //Total threads
#define THREADS_PER_BLOCK 512
__global__ void add(int *a, int *b, int *c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x; //thread_no + block_no * no.ofthreads/block
c[index] = a[index] + b[index];
}
void random_ints(int* a, int n)
{
int i;
for(i =0; i<n; ++i){
a[i]=rand()/2000;
}
}
int main(void)
{
int *a,*b,*c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
a = (int*)malloc(size);
random_ints(a, N);
b = (int*)malloc(size);
random_ints(b, N);
c = (int*)malloc(size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
add<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
printf("%d + %d is %d\n", *a, *b, *c);
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#define N 2048*2048 //Total threads
#define THREADS_PER_BLOCK 512
__global__ void add(int *a, int *b, int *c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x; //thread_no + block_no * no.ofthreads/block
c[index] = a[index] + b[index];
}
void random_ints(int* a, int n)
{
int i;
for(i =0; i<n; ++i){
a[i]=rand()/2000;
}
}
int main(void)
{
int *a,*b,*c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
a = (int*)malloc(size);
random_ints(a, N);
b = (int*)malloc(size);
random_ints(b, N);
c = (int*)malloc(size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
add<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
printf("%d + %d is %d\n", *a, *b, *c);
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#define N 2048*2048 //Total threads
#define THREADS_PER_BLOCK 512
__global__ void add(int *a, int *b, int *c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x; //thread_no + block_no * no.ofthreads/block
c[index] = a[index] + b[index];
}
void random_ints(int* a, int n)
{
int i;
for(i =0; i<n; ++i){
a[i]=rand()/2000;
}
}
int main(void)
{
int *a,*b,*c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
a = (int*)malloc(size);
random_ints(a, N);
b = (int*)malloc(size);
random_ints(b, N);
c = (int*)malloc(size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
add<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
printf("%d + %d is %d\n", *a, *b, *c);
free(a);
free(b);
free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "newc.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rax # imm = 0x10624DD3
movq %rax, %rcx
shrq $63, %rcx
sarq $39, %rax
addl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rax # imm = 0x10624DD3
movq %rax, %rcx
shrq $63, %rcx
sarq $39, %rax
addl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $4194304, %r14 # imm = 0x400000
jne .LBB2_1
# %bb.2: # %_Z11random_intsPii.exit
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i21
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rax # imm = 0x10624DD3
movq %rax, %rcx
shrq $63, %rcx
sarq $39, %rax
addl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $4194304, %r15 # imm = 0x400000
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit25
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 7680(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl (%r14), %edx
movl (%r15), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d is %d\n"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009a1ea_00000000-6_newc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $39, %rdx
sarl $31, %eax
subl %eax, %edx
movl %edx, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d is %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl (%rbx), %ecx
movl 0(%rbp), %edx
movl (%r12), %r8d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "newc.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rax # imm = 0x10624DD3
movq %rax, %rcx
shrq $63, %rcx
sarq $39, %rax
addl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rax # imm = 0x10624DD3
movq %rax, %rcx
shrq $63, %rcx
sarq $39, %rax
addl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $4194304, %r14 # imm = 0x400000
jne .LBB2_1
# %bb.2: # %_Z11random_intsPii.exit
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i21
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rax # imm = 0x10624DD3
movq %rax, %rcx
shrq $63, %rcx
sarq $39, %rax
addl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $4194304, %r15 # imm = 0x400000
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit25
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 7680(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl (%r14), %edx
movl (%r15), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d is %d\n"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <fstream>
#include <iostream>
#define BLUR_SIZE 3
using namespace std;
__global__
void blurKernel(float * in, float * out, int w, int h)
{
//Obtencion de los datos del thread en X y Y
int Col = blockIdx.x * blockDim.x + threadIdx.x;
int Row = blockIdx.y * blockDim.y + threadIdx.y;
//Comprobando que el thread este dentro de los limites
if (Col < w && Row < h)
{
int pixVal = 0;
int pixels = 0;
//Calculando el promedio del valor de la sub matriz del pixel de 2xBLUR_SIZE x 2xBLUR_SIZE
//EJE Y
for(int blurRow = -BLUR_SIZE; blurRow < BLUR_SIZE+1; ++blurRow)
{
//EJE X
for(int blurCol = -BLUR_SIZE; blurCol < BLUR_SIZE+1; ++blurCol)
{
//Calculo de la posicion actual
int curRow = Row + blurRow;
int curCol = Col + blurCol;
//Comprobacion de los limites
if(curRow > -1 && curRow < h && curCol > -1 && curCol < w)
{
//Linealizando la sub matriz de 2xBLUR_SIZE x 2xBLUR_SIZE
//Estos valores seran usados para el promedio
pixVal += in[curRow * w + curCol];
pixels++; // Contador del numero de pixeles usados para el blur
}
}
}
// Write our new pixel value out
// Escribiendo el nuevo valor del pixel segun el promedio de los datos calculados anteriormente
//Acceso lineal a la memoria para la salida
out[Row * w + Col] = (float)(pixVal / pixels);
}
}
//Funcion auxiliar para guardar la data en una imagen .dat
void save_data(float r[225][225], float g[225][225], float b[225][225])
{
ofstream archivo("bluur.dat");
for (int i = 0; i < 225; ++i)
{
for (int j = 0; j < 225; ++j)
{
archivo<<r[i][j]<<" "<<g[i][j]<<" "<<b[i][j]<<" ";
}
archivo<<endl;
}
}
void Blur(float r[225][225], float g[225][225], float b[225][225], int width, int height)
{
//Vectores de salida rgb
float o_r[225][225];
float o_g[225][225];
float o_b[225][225];
//tamaño de imagen
int size = width * height;
//cantidad de memoria necesaria
int memSize = size * sizeof(float);
//Direcciones de memoria del device
float *d_A, *d_B;
//Separando memoria en el device
cudaMalloc((void **) &d_A, memSize);
cudaMalloc((void **) &d_B, memSize);
//COLOR ROJO
//Copia del host al device
cudaMemcpy(d_A, r, memSize, cudaMemcpyHostToDevice);
//Grid 3D (aunque solo se usa 2D) de bloques
dim3 DimGrid(floor((width-1)/16 + 1), floor((height-1)/16+1), 1);
//Bloque 3D de threads
dim3 DimBlock(16, 16, 1);
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia de memoria del device al host (Salida Roja)
cudaMemcpy(o_r, d_B, memSize, cudaMemcpyDeviceToHost);
//COLOR VERDE
cudaMemcpy(d_A, g, memSize, cudaMemcpyHostToDevice);
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia de memoria del device al host (Salida Verde)
cudaMemcpy(o_g, d_B, memSize, cudaMemcpyDeviceToHost);
//Copia del host al device
cudaMemcpy(d_A, b, memSize, cudaMemcpyHostToDevice);
//COLOR AZUL
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia del device al host (salida Azul)
cudaMemcpy(o_b, d_B, memSize, cudaMemcpyDeviceToHost);
//Liberando memoria del device
cudaFree(d_A);
cudaFree(d_B);
//Guardar la data en imagen .dat
save_data(o_r,o_g,o_b);
}
//Funcion de apoyo para la lectura de la imagen
void leer_data(const char *file, float r[225][225], float g[225][225], float b[225][225])
{
char buffer[100];
ifstream archivo2("lena.dat");
for (int ii = 0; ii < 225; ++ii)
{
for (int jj = 0; jj < 225; ++jj)
{
archivo2>>r[ii][jj]>>g[ii][jj]>>b[ii][jj];
}
archivo2.getline(buffer,100);
}
}
int main()
{
int width=225, height=225;
float r[225][225];
float g[225][225];
float b[225][225];
leer_data("lena.dat",r,g,b);
Blur(r,g,b,width,height);
printf("HECHO\n");
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z10blurKernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R15, R0, -0x3, RZ ; /* 0xfffffffd000f7810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3 R8, R5.reuse, -0x3, RZ ; /* 0xfffffffd05087810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*00e0*/ IADD3 R9, R5, -0x2, RZ ; /* 0xfffffffe05097810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R16, R15, c[0x0][0x170], R5 ; /* 0x00005c000f107a24 */
/* 0x000fe200078e0205 */
/*0100*/ IADD3 R10, R5.reuse, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x040fe20007ffe0ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IADD3 R11, R5.reuse, 0x1, RZ ; /* 0x00000001050b7810 */
/* 0x040fe40007ffe0ff */
/*0130*/ IADD3 R12, R5, 0x2, RZ ; /* 0x00000002050c7810 */
/* 0x000fc40007ffe0ff */
/*0140*/ IADD3 R14, R5, 0x3, RZ ; /* 0x00000003050e7810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GE.AND P5, PT, R15, c[0x0][0x174], PT ; /* 0x00005d000f007a0c */
/* 0x000fe20003fa6270 */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0170*/ LOP3.LUT R2, R8, R15, RZ, 0xfc, !PT ; /* 0x0000000f08027212 */
/* 0x000fe200078efcff */
/*0180*/ IMAD R3, R13, c[0x0][0x170], R16 ; /* 0x00005c000d037a24 */
/* 0x000fc600078e0210 */
/*0190*/ ISETP.LT.OR P4, PT, R2, RZ, P5 ; /* 0x000000ff0200720c */
/* 0x000fe20002f81670 */
/*01a0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0204 */
/*01b0*/ ISETP.GE.OR P4, PT, R8, c[0x0][0x170], P4 ; /* 0x00005c0008007a0c */
/* 0x000fda0002786670 */
/*01c0*/ @!P4 LDG.E R17, [R2.64+-0xc] ; /* 0xfffff4040211c981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ LOP3.LUT R18, R9, R15, RZ, 0xfc, !PT ; /* 0x0000000f09127212 */
/* 0x000fc800078efcff */
/*01e0*/ ISETP.LT.OR P3, PT, R18, RZ, P5 ; /* 0x000000ff1200720c */
/* 0x000fc80002f61670 */
/*01f0*/ ISETP.GE.OR P3, PT, R9, c[0x0][0x170], P3 ; /* 0x00005c0009007a0c */
/* 0x000fda0001f66670 */
/*0200*/ @!P3 LDG.E R22, [R2.64+-0x8] ; /* 0xfffff8040216b981 */
/* 0x000ee2000c1e1900 */
/*0210*/ LOP3.LUT R18, R10, R15, RZ, 0xfc, !PT ; /* 0x0000000f0a127212 */
/* 0x000fc800078efcff */
/*0220*/ ISETP.LT.OR P2, PT, R18, RZ, P5 ; /* 0x000000ff1200720c */
/* 0x000fc80002f41670 */
/*0230*/ ISETP.GT.OR P2, PT, R5, c[0x0][0x170], P2 ; /* 0x00005c0005007a0c */
/* 0x000fda0001744670 */
/*0240*/ @!P2 LDG.E R21, [R2.64+-0x4] ; /* 0xfffffc040215a981 */
/* 0x000f22000c1e1900 */
/*0250*/ LOP3.LUT R18, R5, R15, RZ, 0xfc, !PT ; /* 0x0000000f05127212 */
/* 0x000fc800078efcff */
/*0260*/ ISETP.LT.OR P6, PT, R18, RZ, P5 ; /* 0x000000ff1200720c */
/* 0x000fda0002fc1670 */
/*0270*/ @!P6 LDG.E R20, [R2.64] ; /* 0x000000040214e981 */
/* 0x000f62000c1e1900 */
/*0280*/ LOP3.LUT R18, R11, R15, RZ, 0xfc, !PT ; /* 0x0000000f0b127212 */
/* 0x000fc800078efcff */
/*0290*/ ISETP.LT.OR P1, PT, R18, RZ, P5 ; /* 0x000000ff1200720c */
/* 0x000fc80002f21670 */
/*02a0*/ ISETP.GE.OR P1, PT, R11, c[0x0][0x170], P1 ; /* 0x00005c000b007a0c */
/* 0x000fda0000f26670 */
/*02b0*/ @!P1 LDG.E R19, [R2.64+0x4] ; /* 0x0000040402139981 */
/* 0x001162000c1e1900 */
/*02c0*/ LOP3.LUT R18, R12, R15, RZ, 0xfc, !PT ; /* 0x0000000f0c127212 */
/* 0x000fc800078efcff */
/*02d0*/ ISETP.LT.OR P0, PT, R18, RZ, P5 ; /* 0x000000ff1200720c */
/* 0x000fc80002f01670 */
/*02e0*/ ISETP.GE.OR P0, PT, R12, c[0x0][0x170], P0 ; /* 0x00005c000c007a0c */
/* 0x000fda0000706670 */
/*02f0*/ @!P0 LDG.E R18, [R2.64+0x8] ; /* 0x0000080402128981 */
/* 0x000162000c1e1900 */
/*0300*/ LOP3.LUT R23, R14, R15, RZ, 0xfc, !PT ; /* 0x0000000f0e177212 */
/* 0x000fc800078efcff */
/*0310*/ ISETP.LT.OR P5, PT, R23, RZ, P5 ; /* 0x000000ff1700720c */
/* 0x000fc80002fa1670 */
/*0320*/ ISETP.GE.OR P5, PT, R14, c[0x0][0x170], P5 ; /* 0x00005c000e007a0c */
/* 0x000fda0002fa6670 */
/*0330*/ @!P5 LDG.E R23, [R2.64+0xc] ; /* 0x00000c040217d981 */
/* 0x000162000c1e1900 */
/*0340*/ @!P4 I2F R24, R7 ; /* 0x000000070018c306 */
/* 0x002ea20000201400 */
/*0350*/ @!P4 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606c810 */
/* 0x000fe40007ffe0ff */
/*0360*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe40007ffe0ff */
/*0370*/ @!P3 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606b810 */
/* 0x000fc80007ffe0ff */
/*0380*/ @!P2 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606a810 */
/* 0x000fc80007ffe0ff */
/*0390*/ @!P6 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606e810 */
/* 0x000fc80007ffe0ff */
/*03a0*/ @!P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106069810 */
/* 0x000fc80007ffe0ff */
/*03b0*/ @!P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106068810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ @!P5 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606d810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ @!P4 FADD R17, R24, R17 ; /* 0x000000111811c221 */
/* 0x004fc80000000000 */
/*03e0*/ @!P4 F2I.TRUNC.NTZ R7, R17 ; /* 0x000000110007c305 */
/* 0x000e70000020f100 */
/*03f0*/ @!P3 I2F R25, R7 ; /* 0x000000070019b306 */
/* 0x002ee40000201400 */
/*0400*/ @!P3 FADD R22, R25, R22 ; /* 0x000000161916b221 */
/* 0x008fcc0000000000 */
/*0410*/ @!P3 F2I.TRUNC.NTZ R7, R22 ; /* 0x000000160007b305 */
/* 0x000e70000020f100 */
/*0420*/ @!P2 I2F R24, R7 ; /* 0x000000070018a306 */
/* 0x002f240000201400 */
/*0430*/ @!P2 FADD R21, R24, R21 ; /* 0x000000151815a221 */
/* 0x010fcc0000000000 */
/*0440*/ @!P2 F2I.TRUNC.NTZ R7, R21 ; /* 0x000000150007a305 */
/* 0x000e70000020f100 */
/*0450*/ @!P6 I2F R25, R7 ; /* 0x000000070019e306 */
/* 0x002f640000201400 */
/*0460*/ @!P6 FADD R20, R25, R20 ; /* 0x000000141914e221 */
/* 0x020fcc0000000000 */
/*0470*/ @!P6 F2I.TRUNC.NTZ R7, R20 ; /* 0x000000140007e305 */
/* 0x000e30000020f100 */
/*0480*/ @!P1 I2F R2, R7 ; /* 0x0000000700029306 */
/* 0x001e240000201400 */
/*0490*/ @!P1 FADD R19, R2, R19 ; /* 0x0000001302139221 */
/* 0x001fcc0000000000 */
/*04a0*/ @!P1 F2I.TRUNC.NTZ R7, R19 ; /* 0x0000001300079305 */
/* 0x000e22000020f100 */
/*04b0*/ ISETP.NE.AND P1, PT, R13.reuse, 0x6, PT ; /* 0x000000060d00780c */
/* 0x040fe40003f25270 */
/*04c0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fca0007ffe0ff */
/*04d0*/ @!P0 I2F R3, R7 ; /* 0x0000000700038306 */
/* 0x001e240000201400 */
/*04e0*/ @!P0 FADD R18, R3, R18 ; /* 0x0000001203128221 */
/* 0x001fcc0000000000 */
/*04f0*/ @!P0 F2I.TRUNC.NTZ R7, R18 ; /* 0x0000001200078305 */
/* 0x000e30000020f100 */
/*0500*/ @!P5 I2F R2, R7 ; /* 0x000000070002d306 */
/* 0x001e240000201400 */
/*0510*/ @!P5 FADD R23, R2, R23 ; /* 0x000000170217d221 */
/* 0x001fcc0000000000 */
/*0520*/ @!P5 F2I.TRUNC.NTZ R7, R23 ; /* 0x000000170007d305 */
/* 0x000062000020f100 */
/*0530*/ @P1 BRA 0x150 ; /* 0xfffffc1000001947 */
/* 0x000fea000383ffff */
/*0540*/ IABS R9, R6.reuse ; /* 0x0000000600097213 */
/* 0x080fe20000000000 */
/*0550*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fe200078e0205 */
/*0560*/ IABS R12, R7 ; /* 0x00000007000c7213 */
/* 0x002fe40000000000 */
/*0570*/ I2F.RP R8, R9 ; /* 0x0000000900087306 */
/* 0x000e620000209400 */
/*0580*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x000fe20000000000 */
/*0590*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fe200078e0204 */
/*05a0*/ LOP3.LUT R7, R7, R6, RZ, 0x3c, !PT ; /* 0x0000000607077212 */
/* 0x000fc800078e3cff */
/*05b0*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f46270 */
/*05c0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e640000001000 */
/*05d0*/ IADD3 R2, R8, 0xffffffe, RZ ; /* 0x0ffffffe08027810 */
/* 0x002fe20007ffe0ff */
/*05e0*/ IMAD.MOV R8, RZ, RZ, -R13 ; /* 0x000000ffff087224 */
/* 0x000fca00078e0a0d */
/*05f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0002a4000021f000 */
/*0600*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x002fe400078e00ff */
/*0610*/ IMAD.MOV R10, RZ, RZ, -R3 ; /* 0x000000ffff0a7224 */
/* 0x004fc800078e0a03 */
/*0620*/ IMAD R11, R10, R9, RZ ; /* 0x000000090a0b7224 */
/* 0x000fe400078e02ff */
/*0630*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000c */
/*0640*/ IMAD.HI.U32 R3, R3, R11, R2 ; /* 0x0000000b03037227 */
/* 0x000fcc00078e0002 */
/*0650*/ IMAD.HI.U32 R3, R3, R10, RZ ; /* 0x0000000a03037227 */
/* 0x000fc800078e00ff */
/*0660*/ IMAD R2, R3, R8, R10 ; /* 0x0000000803027224 */
/* 0x000fca00078e020a */
/*0670*/ ISETP.GT.U32.AND P1, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f24070 */
/*0680*/ @!P1 IMAD.IADD R2, R2, 0x1, -R9 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a09 */
/*0690*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*06b0*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fda0003f06070 */
/*06c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*06d0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*06e0*/ @!P1 LOP3.LUT R3, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff039212 */
/* 0x000fcc00078e33ff */
/*06f0*/ I2F R3, R3 ; /* 0x0000000300037306 */
/* 0x000e640000201400 */
/*0700*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x002fe2000c101904 */
/*0710*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0720*/ BRA 0x720; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <fstream>
#include <iostream>
#define BLUR_SIZE 3
using namespace std;
__global__
void blurKernel(float * in, float * out, int w, int h)
{
//Obtencion de los datos del thread en X y Y
int Col = blockIdx.x * blockDim.x + threadIdx.x;
int Row = blockIdx.y * blockDim.y + threadIdx.y;
//Comprobando que el thread este dentro de los limites
if (Col < w && Row < h)
{
int pixVal = 0;
int pixels = 0;
//Calculando el promedio del valor de la sub matriz del pixel de 2xBLUR_SIZE x 2xBLUR_SIZE
//EJE Y
for(int blurRow = -BLUR_SIZE; blurRow < BLUR_SIZE+1; ++blurRow)
{
//EJE X
for(int blurCol = -BLUR_SIZE; blurCol < BLUR_SIZE+1; ++blurCol)
{
//Calculo de la posicion actual
int curRow = Row + blurRow;
int curCol = Col + blurCol;
//Comprobacion de los limites
if(curRow > -1 && curRow < h && curCol > -1 && curCol < w)
{
//Linealizando la sub matriz de 2xBLUR_SIZE x 2xBLUR_SIZE
//Estos valores seran usados para el promedio
pixVal += in[curRow * w + curCol];
pixels++; // Contador del numero de pixeles usados para el blur
}
}
}
// Write our new pixel value out
// Escribiendo el nuevo valor del pixel segun el promedio de los datos calculados anteriormente
//Acceso lineal a la memoria para la salida
out[Row * w + Col] = (float)(pixVal / pixels);
}
}
//Funcion auxiliar para guardar la data en una imagen .dat
void save_data(float r[225][225], float g[225][225], float b[225][225])
{
ofstream archivo("bluur.dat");
for (int i = 0; i < 225; ++i)
{
for (int j = 0; j < 225; ++j)
{
archivo<<r[i][j]<<" "<<g[i][j]<<" "<<b[i][j]<<" ";
}
archivo<<endl;
}
}
void Blur(float r[225][225], float g[225][225], float b[225][225], int width, int height)
{
//Vectores de salida rgb
float o_r[225][225];
float o_g[225][225];
float o_b[225][225];
//tamaño de imagen
int size = width * height;
//cantidad de memoria necesaria
int memSize = size * sizeof(float);
//Direcciones de memoria del device
float *d_A, *d_B;
//Separando memoria en el device
cudaMalloc((void **) &d_A, memSize);
cudaMalloc((void **) &d_B, memSize);
//COLOR ROJO
//Copia del host al device
cudaMemcpy(d_A, r, memSize, cudaMemcpyHostToDevice);
//Grid 3D (aunque solo se usa 2D) de bloques
dim3 DimGrid(floor((width-1)/16 + 1), floor((height-1)/16+1), 1);
//Bloque 3D de threads
dim3 DimBlock(16, 16, 1);
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia de memoria del device al host (Salida Roja)
cudaMemcpy(o_r, d_B, memSize, cudaMemcpyDeviceToHost);
//COLOR VERDE
cudaMemcpy(d_A, g, memSize, cudaMemcpyHostToDevice);
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia de memoria del device al host (Salida Verde)
cudaMemcpy(o_g, d_B, memSize, cudaMemcpyDeviceToHost);
//Copia del host al device
cudaMemcpy(d_A, b, memSize, cudaMemcpyHostToDevice);
//COLOR AZUL
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia del device al host (salida Azul)
cudaMemcpy(o_b, d_B, memSize, cudaMemcpyDeviceToHost);
//Liberando memoria del device
cudaFree(d_A);
cudaFree(d_B);
//Guardar la data en imagen .dat
save_data(o_r,o_g,o_b);
}
//Funcion de apoyo para la lectura de la imagen
void leer_data(const char *file, float r[225][225], float g[225][225], float b[225][225])
{
char buffer[100];
ifstream archivo2("lena.dat");
for (int ii = 0; ii < 225; ++ii)
{
for (int jj = 0; jj < 225; ++jj)
{
archivo2>>r[ii][jj]>>g[ii][jj]>>b[ii][jj];
}
archivo2.getline(buffer,100);
}
}
int main()
{
int width=225, height=225;
float r[225][225];
float g[225][225];
float b[225][225];
leer_data("lena.dat",r,g,b);
Blur(r,g,b,width,height);
printf("HECHO\n");
return EXIT_SUCCESS;
} | .file "tmpxft_001034ac_00000000-6_image_blur.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3806:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3806:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii
.type _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii, @function
_Z34__device_stub__Z10blurKernelPfS_iiPfS_ii:
.LFB3828:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10blurKernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3828:
.size _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii, .-_Z34__device_stub__Z10blurKernelPfS_iiPfS_ii
.globl _Z10blurKernelPfS_ii
.type _Z10blurKernelPfS_ii, @function
_Z10blurKernelPfS_ii:
.LFB3829:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _Z10blurKernelPfS_ii, .-_Z10blurKernelPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10blurKernelPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3831:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10blurKernelPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3831:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "bluur.dat"
.LC2:
.string " "
.text
.globl _Z9save_dataPA225_fS0_S0_
.type _Z9save_dataPA225_fS0_S0_, @function
_Z9save_dataPA225_fS0_S0_:
.LFB3800:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3800
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $568, %rsp
.cfi_def_cfa_offset 624
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rbx
leaq 280(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 280(%rsp)
movq $0, 496(%rsp)
movb $0, 504(%rsp)
movb $0, 505(%rsp)
movq $0, 512(%rsp)
movq $0, 520(%rsp)
movq $0, 528(%rsp)
movq $0, 536(%rsp)
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 32(%rsp,%rax)
movq 32(%rsp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 280(%rsp)
leaq 40(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 40(%rsp), %rsi
leaq 280(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
leaq 40(%rsp), %rdi
movl $16, %edx
leaq .LC1(%rip), %rsi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L40
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L16
.L40:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE2:
.L16:
movq $0, (%rsp)
leaq .LC2(%rip), %r12
jmp .L15
.L35:
endbr64
movq %rax, %rbx
leaq 40(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L18:
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 32(%rsp,%rax)
.L19:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 280(%rsp)
leaq 280(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L34:
endbr64
movq %rax, %rbx
jmp .L18
.L33:
endbr64
movq %rax, %rbx
jmp .L19
.L20:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L42:
movq %rax, %rbp
movl $1, %edx
movq %r12, %rsi
movq %rax, %rdi
.LEHB4:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r12, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq $900, %rbx
je .L41
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx), %xmm0
leaq 32(%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L42
.L41:
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L43
cmpb $0, 56(%rbx)
je .L24
movzbl 67(%rbx), %eax
.L25:
movsbl %al, %esi
leaq 32(%rsp), %rdi
call _ZNSo3putEc@PLT
jmp .L44
.L43:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L32:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L45:
call __stack_chk_fail@PLT
.L24:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L25
.L44:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.LEHE4:
addq $900, (%rsp)
movq (%rsp), %rax
cmpq $202500, %rax
je .L26
.L15:
movq 8(%rsp), %rcx
movq (%rsp), %rax
leaq (%rcx,%rax), %r15
movq 16(%rsp), %rcx
leaq (%rcx,%rax), %r14
movq 24(%rsp), %rcx
leaq (%rcx,%rax), %r13
movl $0, %ebx
jmp .L21
.L26:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 280(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rdi
.LEHB5:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE5:
jmp .L28
.L36:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L28:
leaq 144(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 32(%rsp,%rax)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 280(%rsp)
leaq 280(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $568, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA3800:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3800-.LLSDATTD3800
.LLSDATTD3800:
.byte 0x1
.uleb128 .LLSDACSE3800-.LLSDACSB3800
.LLSDACSB3800:
.uleb128 .LEHB0-.LFB3800
.uleb128 .LEHE0-.LEHB0
.uleb128 .L33-.LFB3800
.uleb128 0
.uleb128 .LEHB1-.LFB3800
.uleb128 .LEHE1-.LEHB1
.uleb128 .L34-.LFB3800
.uleb128 0
.uleb128 .LEHB2-.LFB3800
.uleb128 .LEHE2-.LEHB2
.uleb128 .L35-.LFB3800
.uleb128 0
.uleb128 .LEHB3-.LFB3800
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB3800
.uleb128 .LEHE4-.LEHB4
.uleb128 .L32-.LFB3800
.uleb128 0
.uleb128 .LEHB5-.LFB3800
.uleb128 .LEHE5-.LEHB5
.uleb128 .L36-.LFB3800
.uleb128 0x1
.uleb128 .LEHB6-.LFB3800
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE3800:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT3800:
.text
.size _Z9save_dataPA225_fS0_S0_, .-_Z9save_dataPA225_fS0_S0_
.globl _Z4BlurPA225_fS0_S0_ii
.type _Z4BlurPA225_fS0_S0_ii, @function
_Z4BlurPA225_fS0_S0_ii:
.LFB3801:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -606208(%rsp), %r11
.cfi_def_cfa 11, 606264
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1384, %rsp
.cfi_def_cfa_offset 607648
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %r13
movl %ecx, %ebp
movl %r8d, %r12d
movq %fs:40, %rax
movq %rax, 607576(%rsp)
xorl %eax, %eax
movl %ecx, %ebx
imull %r8d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leal 14(%rbp), %eax
movl %ebp, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $4, %eax
addl $1, %eax
movl %eax, 24(%rsp)
leal 14(%r12), %eax
movl %r12d, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $4, %eax
addl $1, %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $16, 36(%rsp)
movl $16, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L48:
leaq 48(%rsp), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L49:
leaq 202560(%rsp), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L50:
leaq 405072(%rsp), %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 202560(%rsp), %rsi
leaq 48(%rsp), %rdi
movq %rbp, %rdx
call _Z9save_dataPA225_fS0_S0_
movq 607576(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $607592, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
movl %r12d, %ecx
movl %ebp, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii
jmp .L48
.L54:
movl %r12d, %ecx
movl %ebp, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii
jmp .L49
.L55:
movl %r12d, %ecx
movl %ebp, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii
jmp .L50
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.size _Z4BlurPA225_fS0_S0_ii, .-_Z4BlurPA225_fS0_S0_ii
.section .rodata.str1.1
.LC3:
.string "lena.dat"
.text
.globl _Z9leer_dataPKcPA225_fS2_S2_
.type _Z9leer_dataPKcPA225_fS2_S2_, @function
_Z9leer_dataPKcPA225_fS2_S2_:
.LFB3802:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3802
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $648, %rsp
.cfi_def_cfa_offset 704
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %r15
movq %fs:40, %rax
movq %rax, 632(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
leaq 256(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 256(%rsp)
movq $0, 472(%rsp)
movb $0, 480(%rsp)
movb $0, 481(%rsp)
movq $0, 488(%rsp)
movq $0, 496(%rsp)
movq $0, 504(%rsp)
movq $0, 512(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rdx
movq %rdx, (%rsp,%rax)
movq $0, 8(%rsp)
movq (%rsp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB7:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE7:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
leaq 40(%rax), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rdi
.LEHB8:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE8:
leaq 16(%rsp), %rsi
leaq 256(%rsp), %rdi
.LEHB9:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
leaq 16(%rsp), %rdi
movl $8, %edx
leaq .LC3(%rip), %rsi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L84
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L60
.L84:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE9:
.L60:
movq %r15, %rbp
addq $202500, %r15
movq %rsp, %r14
jmp .L59
.L79:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L62:
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rdx
movq %rdx, (%rsp,%rax)
movq $0, 8(%rsp)
.L63:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 256(%rsp)
leaq 256(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 632(%rsp), %rax
subq %fs:40, %rax
je .L64
call __stack_chk_fail@PLT
.L78:
endbr64
movq %rax, %rbx
jmp .L62
.L77:
endbr64
movq %rax, %rbx
jmp .L63
.L64:
movq %rbx, %rdi
.LEHB10:
call _Unwind_Resume@PLT
.LEHE10:
.L86:
movq %rax, %rdi
leaq (%r12,%rbx), %rsi
.LEHB11:
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
leaq 0(%rbp,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
addq $4, %rbx
cmpq $900, %rbx
je .L85
.L65:
leaq (%rbx,%r13), %rsi
movq %r14, %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
jmp .L86
.L85:
movq (%rsp), %rax
movq -24(%rax), %rax
movq 240(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L87
cmpb $0, 56(%rbx)
je .L68
movzbl 67(%rbx), %eax
.L69:
movsbl %al, %ecx
leaq 528(%rsp), %rsi
movl $100, %edx
movq %r14, %rdi
call _ZNSi7getlineEPclc@PLT
jmp .L88
.L87:
movq 632(%rsp), %rax
subq %fs:40, %rax
jne .L89
call _ZSt16__throw_bad_castv@PLT
.L76:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 632(%rsp), %rax
subq %fs:40, %rax
je .L74
call __stack_chk_fail@PLT
.L89:
call __stack_chk_fail@PLT
.L68:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
.LEHE11:
jmp .L69
.L88:
addq $900, %rbp
addq $900, %r12
addq $900, %r13
cmpq %r15, %rbp
je .L70
.L59:
movl $0, %ebx
jmp .L65
.L70:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
leaq 40(%rax), %rax
movq %rax, 256(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 16(%rsp), %rdi
.LEHB12:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE12:
jmp .L72
.L80:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L72:
leaq 120(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 72(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rdx
movq %rdx, (%rsp,%rax)
movq $0, 8(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 256(%rsp)
leaq 256(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 632(%rsp), %rax
subq %fs:40, %rax
jne .L90
addq $648, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L74:
.cfi_restore_state
movq %rbx, %rdi
.LEHB13:
call _Unwind_Resume@PLT
.LEHE13:
.L90:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3802:
.section .gcc_except_table
.align 4
.LLSDA3802:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3802-.LLSDATTD3802
.LLSDATTD3802:
.byte 0x1
.uleb128 .LLSDACSE3802-.LLSDACSB3802
.LLSDACSB3802:
.uleb128 .LEHB7-.LFB3802
.uleb128 .LEHE7-.LEHB7
.uleb128 .L77-.LFB3802
.uleb128 0
.uleb128 .LEHB8-.LFB3802
.uleb128 .LEHE8-.LEHB8
.uleb128 .L78-.LFB3802
.uleb128 0
.uleb128 .LEHB9-.LFB3802
.uleb128 .LEHE9-.LEHB9
.uleb128 .L79-.LFB3802
.uleb128 0
.uleb128 .LEHB10-.LFB3802
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.uleb128 .LEHB11-.LFB3802
.uleb128 .LEHE11-.LEHB11
.uleb128 .L76-.LFB3802
.uleb128 0
.uleb128 .LEHB12-.LFB3802
.uleb128 .LEHE12-.LEHB12
.uleb128 .L80-.LFB3802
.uleb128 0x1
.uleb128 .LEHB13-.LFB3802
.uleb128 .LEHE13-.LEHB13
.uleb128 0
.uleb128 0
.LLSDACSE3802:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT3802:
.text
.size _Z9leer_dataPKcPA225_fS2_S2_, .-_Z9leer_dataPKcPA225_fS2_S2_
.section .rodata.str1.1
.LC4:
.string "HECHO\n"
.text
.globl main
.type main, @function
main:
.LFB3803:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -606208(%rsp), %r11
.cfi_def_cfa 11, 606240
.LPSRL1:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL1
.cfi_def_cfa_register 7
subq $1328, %rsp
.cfi_def_cfa_offset 607568
movq %fs:40, %rax
movq %rax, 607528(%rsp)
xorl %eax, %eax
leaq 405024(%rsp), %r12
leaq 202512(%rsp), %rbp
movq %rsp, %rbx
movq %r12, %rcx
movq %rbp, %rdx
movq %rbx, %rsi
leaq .LC3(%rip), %rdi
call _Z9leer_dataPKcPA225_fS2_S2_
movl $225, %r8d
movl $225, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z4BlurPA225_fS0_S0_ii
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 607528(%rsp), %rax
subq %fs:40, %rax
jne .L94
movl $0, %eax
addq $607536, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3803:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <fstream>
#include <iostream>
#define BLUR_SIZE 3
using namespace std;
__global__
void blurKernel(float * in, float * out, int w, int h)
{
//Obtencion de los datos del thread en X y Y
int Col = blockIdx.x * blockDim.x + threadIdx.x;
int Row = blockIdx.y * blockDim.y + threadIdx.y;
//Comprobando que el thread este dentro de los limites
if (Col < w && Row < h)
{
int pixVal = 0;
int pixels = 0;
//Calculando el promedio del valor de la sub matriz del pixel de 2xBLUR_SIZE x 2xBLUR_SIZE
//EJE Y
for(int blurRow = -BLUR_SIZE; blurRow < BLUR_SIZE+1; ++blurRow)
{
//EJE X
for(int blurCol = -BLUR_SIZE; blurCol < BLUR_SIZE+1; ++blurCol)
{
//Calculo de la posicion actual
int curRow = Row + blurRow;
int curCol = Col + blurCol;
//Comprobacion de los limites
if(curRow > -1 && curRow < h && curCol > -1 && curCol < w)
{
//Linealizando la sub matriz de 2xBLUR_SIZE x 2xBLUR_SIZE
//Estos valores seran usados para el promedio
pixVal += in[curRow * w + curCol];
pixels++; // Contador del numero de pixeles usados para el blur
}
}
}
// Write our new pixel value out
// Escribiendo el nuevo valor del pixel segun el promedio de los datos calculados anteriormente
//Acceso lineal a la memoria para la salida
out[Row * w + Col] = (float)(pixVal / pixels);
}
}
//Funcion auxiliar para guardar la data en una imagen .dat
void save_data(float r[225][225], float g[225][225], float b[225][225])
{
ofstream archivo("bluur.dat");
for (int i = 0; i < 225; ++i)
{
for (int j = 0; j < 225; ++j)
{
archivo<<r[i][j]<<" "<<g[i][j]<<" "<<b[i][j]<<" ";
}
archivo<<endl;
}
}
void Blur(float r[225][225], float g[225][225], float b[225][225], int width, int height)
{
//Vectores de salida rgb
float o_r[225][225];
float o_g[225][225];
float o_b[225][225];
//tamaño de imagen
int size = width * height;
//cantidad de memoria necesaria
int memSize = size * sizeof(float);
//Direcciones de memoria del device
float *d_A, *d_B;
//Separando memoria en el device
cudaMalloc((void **) &d_A, memSize);
cudaMalloc((void **) &d_B, memSize);
//COLOR ROJO
//Copia del host al device
cudaMemcpy(d_A, r, memSize, cudaMemcpyHostToDevice);
//Grid 3D (aunque solo se usa 2D) de bloques
dim3 DimGrid(floor((width-1)/16 + 1), floor((height-1)/16+1), 1);
//Bloque 3D de threads
dim3 DimBlock(16, 16, 1);
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia de memoria del device al host (Salida Roja)
cudaMemcpy(o_r, d_B, memSize, cudaMemcpyDeviceToHost);
//COLOR VERDE
cudaMemcpy(d_A, g, memSize, cudaMemcpyHostToDevice);
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia de memoria del device al host (Salida Verde)
cudaMemcpy(o_g, d_B, memSize, cudaMemcpyDeviceToHost);
//Copia del host al device
cudaMemcpy(d_A, b, memSize, cudaMemcpyHostToDevice);
//COLOR AZUL
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia del device al host (salida Azul)
cudaMemcpy(o_b, d_B, memSize, cudaMemcpyDeviceToHost);
//Liberando memoria del device
cudaFree(d_A);
cudaFree(d_B);
//Guardar la data en imagen .dat
save_data(o_r,o_g,o_b);
}
//Funcion de apoyo para la lectura de la imagen
void leer_data(const char *file, float r[225][225], float g[225][225], float b[225][225])
{
char buffer[100];
ifstream archivo2("lena.dat");
for (int ii = 0; ii < 225; ++ii)
{
for (int jj = 0; jj < 225; ++jj)
{
archivo2>>r[ii][jj]>>g[ii][jj]>>b[ii][jj];
}
archivo2.getline(buffer,100);
}
}
int main()
{
int width=225, height=225;
float r[225][225];
float g[225][225];
float b[225][225];
leer_data("lena.dat",r,g,b);
Blur(r,g,b,width,height);
printf("HECHO\n");
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <fstream>
#include <iostream>
#define BLUR_SIZE 3
using namespace std;
__global__
void blurKernel(float * in, float * out, int w, int h)
{
//Obtencion de los datos del thread en X y Y
int Col = blockIdx.x * blockDim.x + threadIdx.x;
int Row = blockIdx.y * blockDim.y + threadIdx.y;
//Comprobando que el thread este dentro de los limites
if (Col < w && Row < h)
{
int pixVal = 0;
int pixels = 0;
//Calculando el promedio del valor de la sub matriz del pixel de 2xBLUR_SIZE x 2xBLUR_SIZE
//EJE Y
for(int blurRow = -BLUR_SIZE; blurRow < BLUR_SIZE+1; ++blurRow)
{
//EJE X
for(int blurCol = -BLUR_SIZE; blurCol < BLUR_SIZE+1; ++blurCol)
{
//Calculo de la posicion actual
int curRow = Row + blurRow;
int curCol = Col + blurCol;
//Comprobacion de los limites
if(curRow > -1 && curRow < h && curCol > -1 && curCol < w)
{
//Linealizando la sub matriz de 2xBLUR_SIZE x 2xBLUR_SIZE
//Estos valores seran usados para el promedio
pixVal += in[curRow * w + curCol];
pixels++; // Contador del numero de pixeles usados para el blur
}
}
}
// Write our new pixel value out
// Escribiendo el nuevo valor del pixel segun el promedio de los datos calculados anteriormente
//Acceso lineal a la memoria para la salida
out[Row * w + Col] = (float)(pixVal / pixels);
}
}
//Funcion auxiliar para guardar la data en una imagen .dat
void save_data(float r[225][225], float g[225][225], float b[225][225])
{
ofstream archivo("bluur.dat");
for (int i = 0; i < 225; ++i)
{
for (int j = 0; j < 225; ++j)
{
archivo<<r[i][j]<<" "<<g[i][j]<<" "<<b[i][j]<<" ";
}
archivo<<endl;
}
}
void Blur(float r[225][225], float g[225][225], float b[225][225], int width, int height)
{
//Vectores de salida rgb
float o_r[225][225];
float o_g[225][225];
float o_b[225][225];
//tamaño de imagen
int size = width * height;
//cantidad de memoria necesaria
int memSize = size * sizeof(float);
//Direcciones de memoria del device
float *d_A, *d_B;
//Separando memoria en el device
hipMalloc((void **) &d_A, memSize);
hipMalloc((void **) &d_B, memSize);
//COLOR ROJO
//Copia del host al device
hipMemcpy(d_A, r, memSize, hipMemcpyHostToDevice);
//Grid 3D (aunque solo se usa 2D) de bloques
dim3 DimGrid(floor((width-1)/16 + 1), floor((height-1)/16+1), 1);
//Bloque 3D de threads
dim3 DimBlock(16, 16, 1);
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia de memoria del device al host (Salida Roja)
hipMemcpy(o_r, d_B, memSize, hipMemcpyDeviceToHost);
//COLOR VERDE
hipMemcpy(d_A, g, memSize, hipMemcpyHostToDevice);
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia de memoria del device al host (Salida Verde)
hipMemcpy(o_g, d_B, memSize, hipMemcpyDeviceToHost);
//Copia del host al device
hipMemcpy(d_A, b, memSize, hipMemcpyHostToDevice);
//COLOR AZUL
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia del device al host (salida Azul)
hipMemcpy(o_b, d_B, memSize, hipMemcpyDeviceToHost);
//Liberando memoria del device
hipFree(d_A);
hipFree(d_B);
//Guardar la data en imagen .dat
save_data(o_r,o_g,o_b);
}
//Funcion de apoyo para la lectura de la imagen
void leer_data(const char *file, float r[225][225], float g[225][225], float b[225][225])
{
char buffer[100];
ifstream archivo2("lena.dat");
for (int ii = 0; ii < 225; ++ii)
{
for (int jj = 0; jj < 225; ++jj)
{
archivo2>>r[ii][jj]>>g[ii][jj]>>b[ii][jj];
}
archivo2.getline(buffer,100);
}
}
int main()
{
int width=225, height=225;
float r[225][225];
float g[225][225];
float b[225][225];
leer_data("lena.dat",r,g,b);
Blur(r,g,b,width,height);
printf("HECHO\n");
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <fstream>
#include <iostream>
#define BLUR_SIZE 3
using namespace std;
__global__
void blurKernel(float * in, float * out, int w, int h)
{
//Obtencion de los datos del thread en X y Y
int Col = blockIdx.x * blockDim.x + threadIdx.x;
int Row = blockIdx.y * blockDim.y + threadIdx.y;
//Comprobando que el thread este dentro de los limites
if (Col < w && Row < h)
{
int pixVal = 0;
int pixels = 0;
//Calculando el promedio del valor de la sub matriz del pixel de 2xBLUR_SIZE x 2xBLUR_SIZE
//EJE Y
for(int blurRow = -BLUR_SIZE; blurRow < BLUR_SIZE+1; ++blurRow)
{
//EJE X
for(int blurCol = -BLUR_SIZE; blurCol < BLUR_SIZE+1; ++blurCol)
{
//Calculo de la posicion actual
int curRow = Row + blurRow;
int curCol = Col + blurCol;
//Comprobacion de los limites
if(curRow > -1 && curRow < h && curCol > -1 && curCol < w)
{
//Linealizando la sub matriz de 2xBLUR_SIZE x 2xBLUR_SIZE
//Estos valores seran usados para el promedio
pixVal += in[curRow * w + curCol];
pixels++; // Contador del numero de pixeles usados para el blur
}
}
}
// Write our new pixel value out
// Escribiendo el nuevo valor del pixel segun el promedio de los datos calculados anteriormente
//Acceso lineal a la memoria para la salida
out[Row * w + Col] = (float)(pixVal / pixels);
}
}
//Funcion auxiliar para guardar la data en una imagen .dat
void save_data(float r[225][225], float g[225][225], float b[225][225])
{
ofstream archivo("bluur.dat");
for (int i = 0; i < 225; ++i)
{
for (int j = 0; j < 225; ++j)
{
archivo<<r[i][j]<<" "<<g[i][j]<<" "<<b[i][j]<<" ";
}
archivo<<endl;
}
}
void Blur(float r[225][225], float g[225][225], float b[225][225], int width, int height)
{
//Vectores de salida rgb
float o_r[225][225];
float o_g[225][225];
float o_b[225][225];
//tamaño de imagen
int size = width * height;
//cantidad de memoria necesaria
int memSize = size * sizeof(float);
//Direcciones de memoria del device
float *d_A, *d_B;
//Separando memoria en el device
hipMalloc((void **) &d_A, memSize);
hipMalloc((void **) &d_B, memSize);
//COLOR ROJO
//Copia del host al device
hipMemcpy(d_A, r, memSize, hipMemcpyHostToDevice);
//Grid 3D (aunque solo se usa 2D) de bloques
dim3 DimGrid(floor((width-1)/16 + 1), floor((height-1)/16+1), 1);
//Bloque 3D de threads
dim3 DimBlock(16, 16, 1);
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia de memoria del device al host (Salida Roja)
hipMemcpy(o_r, d_B, memSize, hipMemcpyDeviceToHost);
//COLOR VERDE
hipMemcpy(d_A, g, memSize, hipMemcpyHostToDevice);
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia de memoria del device al host (Salida Verde)
hipMemcpy(o_g, d_B, memSize, hipMemcpyDeviceToHost);
//Copia del host al device
hipMemcpy(d_A, b, memSize, hipMemcpyHostToDevice);
//COLOR AZUL
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia del device al host (salida Azul)
hipMemcpy(o_b, d_B, memSize, hipMemcpyDeviceToHost);
//Liberando memoria del device
hipFree(d_A);
hipFree(d_B);
//Guardar la data en imagen .dat
save_data(o_r,o_g,o_b);
}
//Funcion de apoyo para la lectura de la imagen
void leer_data(const char *file, float r[225][225], float g[225][225], float b[225][225])
{
char buffer[100];
ifstream archivo2("lena.dat");
for (int ii = 0; ii < 225; ++ii)
{
for (int jj = 0; jj < 225; ++jj)
{
archivo2>>r[ii][jj]>>g[ii][jj]>>b[ii][jj];
}
archivo2.getline(buffer,100);
}
}
int main()
{
int width=225, height=225;
float r[225][225];
float g[225][225];
float b[225][225];
leer_data("lena.dat",r,g,b);
Blur(r,g,b,width,height);
printf("HECHO\n");
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10blurKernelPfS_ii
.globl _Z10blurKernelPfS_ii
.p2align 8
.type _Z10blurKernelPfS_ii,@function
_Z10blurKernelPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s15, s15, s2
v_add_nc_u32_e32 v0, s14, v2
v_add_nc_u32_e32 v1, s15, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s2, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
s_load_b64 s[8:9], s[0:1], 0x0
v_add3_u32 v3, v3, s15, -3
v_add3_u32 v5, v2, s14, -3
v_mov_b32_e32 v2, 0
s_mov_b32 s5, -3
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v4, s6, v3
v_mov_b32_e32 v3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, s6, v4
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 4
s_cbranch_scc1 .LBB0_9
.LBB0_3:
v_add_nc_u32_e32 v6, s5, v1
s_mov_b32 s10, 7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v6
v_cmp_gt_i32_e64 s2, s7, v6
v_mov_b32_e32 v6, v5
s_branch .LBB0_6
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v6, 1, v6
s_add_i32 s10, s10, -1
s_cmp_eq_u32 s10, 0
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_and_saveexec_b32 s11, vcc_lo
s_cbranch_execz .LBB0_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s3, -1, v6
v_cmp_gt_i32_e64 s4, s6, v6
s_and_b32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v7, v4, v6
v_cvt_f32_i32_e32 v2, v2
v_add_nc_u32_e32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s3, s8, v7
v_add_co_ci_u32_e64 v8, s3, s9, v8, s3
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v7, v2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v2
s_branch .LBB0_4
.LBB0_9:
s_set_inst_prefetch_distance 0x2
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v2
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v3, v4
v_add_nc_u32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v3, v4
v_xor_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v3, v5
v_sub_nc_u32_e32 v6, 0, v5
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v6, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v3, v6
v_add_nc_u32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_mul_lo_u32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v6
v_add_nc_u32_e32 v6, 1, v3
v_sub_nc_u32_e32 v8, v2, v5
v_cmp_ge_u32_e32 vcc_lo, v2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v8, v2, v8, vcc_lo
v_cndmask_b32_e32 v6, v3, v6, vcc_lo
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
v_xor_b32_e32 v0, v7, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ge_u32_e32 vcc_lo, v8, v5
v_add_nc_u32_e32 v9, 1, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_cndmask_b32_e32 v1, v6, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v0
v_sub_nc_u32_e32 v4, v1, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_cvt_f32_i32_e32 v2, v4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10blurKernelPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10blurKernelPfS_ii, .Lfunc_end0-_Z10blurKernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10blurKernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10blurKernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <fstream>
#include <iostream>
#define BLUR_SIZE 3
using namespace std;
__global__
void blurKernel(float * in, float * out, int w, int h)
{
//Obtencion de los datos del thread en X y Y
int Col = blockIdx.x * blockDim.x + threadIdx.x;
int Row = blockIdx.y * blockDim.y + threadIdx.y;
//Comprobando que el thread este dentro de los limites
if (Col < w && Row < h)
{
int pixVal = 0;
int pixels = 0;
//Calculando el promedio del valor de la sub matriz del pixel de 2xBLUR_SIZE x 2xBLUR_SIZE
//EJE Y
for(int blurRow = -BLUR_SIZE; blurRow < BLUR_SIZE+1; ++blurRow)
{
//EJE X
for(int blurCol = -BLUR_SIZE; blurCol < BLUR_SIZE+1; ++blurCol)
{
//Calculo de la posicion actual
int curRow = Row + blurRow;
int curCol = Col + blurCol;
//Comprobacion de los limites
if(curRow > -1 && curRow < h && curCol > -1 && curCol < w)
{
//Linealizando la sub matriz de 2xBLUR_SIZE x 2xBLUR_SIZE
//Estos valores seran usados para el promedio
pixVal += in[curRow * w + curCol];
pixels++; // Contador del numero de pixeles usados para el blur
}
}
}
// Write our new pixel value out
// Escribiendo el nuevo valor del pixel segun el promedio de los datos calculados anteriormente
//Acceso lineal a la memoria para la salida
out[Row * w + Col] = (float)(pixVal / pixels);
}
}
//Funcion auxiliar para guardar la data en una imagen .dat
void save_data(float r[225][225], float g[225][225], float b[225][225])
{
ofstream archivo("bluur.dat");
for (int i = 0; i < 225; ++i)
{
for (int j = 0; j < 225; ++j)
{
archivo<<r[i][j]<<" "<<g[i][j]<<" "<<b[i][j]<<" ";
}
archivo<<endl;
}
}
void Blur(float r[225][225], float g[225][225], float b[225][225], int width, int height)
{
//Vectores de salida rgb
float o_r[225][225];
float o_g[225][225];
float o_b[225][225];
//tamaño de imagen
int size = width * height;
//cantidad de memoria necesaria
int memSize = size * sizeof(float);
//Direcciones de memoria del device
float *d_A, *d_B;
//Separando memoria en el device
hipMalloc((void **) &d_A, memSize);
hipMalloc((void **) &d_B, memSize);
//COLOR ROJO
//Copia del host al device
hipMemcpy(d_A, r, memSize, hipMemcpyHostToDevice);
//Grid 3D (aunque solo se usa 2D) de bloques
dim3 DimGrid(floor((width-1)/16 + 1), floor((height-1)/16+1), 1);
//Bloque 3D de threads
dim3 DimBlock(16, 16, 1);
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia de memoria del device al host (Salida Roja)
hipMemcpy(o_r, d_B, memSize, hipMemcpyDeviceToHost);
//COLOR VERDE
hipMemcpy(d_A, g, memSize, hipMemcpyHostToDevice);
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia de memoria del device al host (Salida Verde)
hipMemcpy(o_g, d_B, memSize, hipMemcpyDeviceToHost);
//Copia del host al device
hipMemcpy(d_A, b, memSize, hipMemcpyHostToDevice);
//COLOR AZUL
//Llamado al kernel
blurKernel<<<DimGrid,DimBlock>>>(d_A, d_B, width, height);
//Copia del device al host (salida Azul)
hipMemcpy(o_b, d_B, memSize, hipMemcpyDeviceToHost);
//Liberando memoria del device
hipFree(d_A);
hipFree(d_B);
//Guardar la data en imagen .dat
save_data(o_r,o_g,o_b);
}
//Funcion de apoyo para la lectura de la imagen
void leer_data(const char *file, float r[225][225], float g[225][225], float b[225][225])
{
char buffer[100];
ifstream archivo2("lena.dat");
for (int ii = 0; ii < 225; ++ii)
{
for (int jj = 0; jj < 225; ++jj)
{
archivo2>>r[ii][jj]>>g[ii][jj]>>b[ii][jj];
}
archivo2.getline(buffer,100);
}
}
int main()
{
int width=225, height=225;
float r[225][225];
float g[225][225];
float b[225][225];
leer_data("lena.dat",r,g,b);
Blur(r,g,b,width,height);
printf("HECHO\n");
return EXIT_SUCCESS;
} | .text
.file "image_blur.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__blurKernelPfS_ii # -- Begin function _Z25__device_stub__blurKernelPfS_ii
.p2align 4, 0x90
.type _Z25__device_stub__blurKernelPfS_ii,@function
_Z25__device_stub__blurKernelPfS_ii: # @_Z25__device_stub__blurKernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10blurKernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__blurKernelPfS_ii, .Lfunc_end0-_Z25__device_stub__blurKernelPfS_ii
.cfi_endproc
# -- End function
.globl _Z9save_dataPA225_fS0_S0_ # -- Begin function _Z9save_dataPA225_fS0_S0_
.p2align 4, 0x90
.type _Z9save_dataPA225_fS0_S0_,@function
_Z9save_dataPA225_fS0_S0_: # @_Z9save_dataPA225_fS0_S0_
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $520, %rsp # imm = 0x208
.cfi_def_cfa_offset 576
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 8(%rsp), %r12
movl $.L.str, %esi
movq %r12, %rdi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movq %rbp, (%rsp) # 8-byte Spill
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp0:
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp1:
# %bb.3: # %_ZNSolsEf.exit
# in Loop: Header=BB1_2 Depth=2
.Ltmp2:
movq %rax, %r13
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp3:
# %bb.4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_2 Depth=2
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp4:
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp5:
# %bb.5: # %_ZNSolsEf.exit18
# in Loop: Header=BB1_2 Depth=2
.Ltmp6:
movq %rax, %r13
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit19
# in Loop: Header=BB1_2 Depth=2
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp8:
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp9:
# %bb.7: # %_ZNSolsEf.exit20
# in Loop: Header=BB1_2 Depth=2
.Ltmp10:
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp11:
# %bb.8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit21
# in Loop: Header=BB1_2 Depth=2
incq %rbp
cmpq $225, %rbp
jne .LBB1_2
# %bb.9: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movq -24(%rax), %rax
movq 248(%rsp,%rax), %r13
testq %r13, %r13
je .LBB1_10
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%r13)
movq (%rsp), %rbp # 8-byte Reload
je .LBB1_14
# %bb.13: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%r13), %eax
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_1 Depth=1
.Ltmp13:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp14:
# %bb.15: # %.noexc22
# in Loop: Header=BB1_1 Depth=1
movq (%r13), %rax
.Ltmp15:
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp16:
.LBB1_16: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB1_1 Depth=1
.Ltmp17:
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp18:
# %bb.17: # %.noexc24
# in Loop: Header=BB1_1 Depth=1
.Ltmp19:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp20:
# %bb.18: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_1 Depth=1
incq %rbp
addq $900, %rbx # imm = 0x384
addq $900, %r14 # imm = 0x384
addq $900, %r15 # imm = 0x384
cmpq $225, %rbp
jne .LBB1_1
# %bb.19:
leaq 8(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
addq $520, %rsp # imm = 0x208
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 576
.Ltmp22:
callq _ZSt16__throw_bad_castv
.Ltmp23:
# %bb.11: # %.noexc
.LBB1_21: # %.loopexit.split-lp
.Ltmp24:
jmp .LBB1_22
.LBB1_20: # %.loopexit
.Ltmp21:
jmp .LBB1_22
.LBB1_23:
.Ltmp12:
.LBB1_22:
movq %rax, %rbx
leaq 8(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _Z9save_dataPA225_fS0_S0_, .Lfunc_end1-_Z9save_dataPA225_fS0_S0_
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp11-.Ltmp0 # Call between .Ltmp0 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp20-.Ltmp13 # Call between .Ltmp13 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end1-.Ltmp23 # Call between .Ltmp23 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z4BlurPA225_fS0_S0_ii # -- Begin function _Z4BlurPA225_fS0_S0_ii
.p2align 4, 0x90
.type _Z4BlurPA225_fS0_S0_ii,@function
_Z4BlurPA225_fS0_S0_ii: # @_Z4BlurPA225_fS0_S0_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $607624, %rsp # imm = 0x94588
.cfi_def_cfa_offset 607680
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %r14d
movl %ecx, %r15d
movq %rdx, 88(%rsp) # 8-byte Spill
movq %rsi, %r12
movq %rdi, %rbp
movabsq $68719476752, %r13 # imm = 0x1000000010
movl %ecx, %eax
imull %r8d, %eax
shll $2, %eax
movslq %eax, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leal -1(%r15), %eax
leal 14(%r15), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
incl %ecx
leal -1(%r14), %eax
leal 14(%r14), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $4, %ebp
incl %ebp
shlq $32, %rbp
orq %rcx, %rbp
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 72(%rsp)
movl %r15d, 32(%rsp)
movl %r14d, 24(%rsp)
leaq 56(%rsp), %rax
movq %rax, 405120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 405128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 405136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 405144(%rsp)
leaq 202608(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 202608(%rsp), %rsi
movl 202616(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 405120(%rsp), %r9
movl $_Z10blurKernelPfS_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq (%rsp), %rsi
leaq 405120(%rsp), %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 48(%rsp)
movl %r15d, 24(%rsp)
movl %r14d, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 202608(%rsp)
leaq 48(%rsp), %rax
movq %rax, 202616(%rsp)
leaq 24(%rsp), %rax
movq %rax, 202624(%rsp)
leaq 20(%rsp), %rax
movq %rax, 202632(%rsp)
leaq 96(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 202608(%rsp), %r9
movl $_Z10blurKernelPfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
leaq 202608(%rsp), %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 88(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 84(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 84(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10blurKernelPfS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
leaq 96(%rsp), %r14
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
leaq 405120(%rsp), %rdi
leaq 202608(%rsp), %rsi
movq %r14, %rdx
callq _Z9save_dataPA225_fS0_S0_
addq $607624, %rsp # imm = 0x94588
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z4BlurPA225_fS0_S0_ii, .Lfunc_end2-_Z4BlurPA225_fS0_S0_ii
.cfi_endproc
# -- End function
.globl _Z9leer_dataPKcPA225_fS2_S2_ # -- Begin function _Z9leer_dataPKcPA225_fS2_S2_
.p2align 4, 0x90
.type _Z9leer_dataPKcPA225_fS2_S2_,@function
_Z9leer_dataPKcPA225_fS2_S2_: # @_Z9leer_dataPKcPA225_fS2_S2_
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $632, %rsp # imm = 0x278
.cfi_def_cfa_offset 688
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
leaq 8(%rsp), %r12
movl $.L.str.2, %esi
movq %r12, %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%rbp), %rsi
.Ltmp25:
movq %r12, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp26:
# %bb.3: # %_ZNSirsERf.exit
# in Loop: Header=BB3_2 Depth=2
leaq (%r14,%rbp), %rsi
.Ltmp27:
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp28:
# %bb.4: # %_ZNSirsERf.exit23
# in Loop: Header=BB3_2 Depth=2
leaq (%rbx,%rbp), %rsi
.Ltmp29:
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp30:
# %bb.5: # %_ZNSirsERf.exit25
# in Loop: Header=BB3_2 Depth=2
addq $4, %rbp
cmpq $900, %rbp # imm = 0x384
jne .LBB3_2
# %bb.6: # in Loop: Header=BB3_1 Depth=1
movq 8(%rsp), %rax
movq -24(%rax), %rax
movq 248(%rsp,%rax), %rbp
testq %rbp, %rbp
je .LBB3_7
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB3_1 Depth=1
cmpb $0, 56(%rbp)
je .LBB3_11
# %bb.10: # in Loop: Header=BB3_1 Depth=1
movzbl 67(%rbp), %eax
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_1 Depth=1
.Ltmp32:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp33:
# %bb.12: # %.noexc18
# in Loop: Header=BB3_1 Depth=1
movq (%rbp), %rax
.Ltmp34:
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp35:
.LBB3_13: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB3_1 Depth=1
.Ltmp36:
movsbl %al, %ecx
movl $100, %edx
movq %r12, %rdi
leaq 528(%rsp), %rsi
callq _ZNSi7getlineEPclc
.Ltmp37:
# %bb.14: # %_ZNSi7getlineEPcl.exit
# in Loop: Header=BB3_1 Depth=1
incq %r13
addq $900, %rbx # imm = 0x384
addq $900, %r14 # imm = 0x384
addq $900, %r15 # imm = 0x384
cmpq $225, %r13
jne .LBB3_1
# %bb.15:
leaq 8(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 264(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
addq $632, %rsp # imm = 0x278
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 688
.Ltmp39:
callq _ZSt16__throw_bad_castv
.Ltmp40:
# %bb.8: # %.noexc
.LBB3_17: # %.loopexit.split-lp
.Ltmp41:
jmp .LBB3_18
.LBB3_16: # %.loopexit
.Ltmp38:
jmp .LBB3_18
.LBB3_19:
.Ltmp31:
.LBB3_18:
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 264(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size _Z9leer_dataPKcPA225_fS2_S2_, .Lfunc_end3-_Z9leer_dataPKcPA225_fS2_S2_
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp25-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp25
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp30-.Ltmp25 # Call between .Ltmp25 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin1 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp37-.Ltmp32 # Call between .Ltmp32 and .Ltmp37
.uleb128 .Ltmp38-.Lfunc_begin1 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin1 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Lfunc_end3-.Ltmp40 # Call between .Ltmp40 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $607536, %rsp # imm = 0x94530
.cfi_def_cfa_offset 607568
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 405024(%rsp), %rbx
leaq 202512(%rsp), %r14
movq %rsp, %r15
movq %rbx, %rsi
movq %r14, %rdx
movq %r15, %rcx
callq _Z9leer_dataPKcPA225_fS2_S2_
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $225, %ecx
movl $225, %r8d
callq _Z4BlurPA225_fS0_S0_ii
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $607536, %rsp # imm = 0x94530
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10blurKernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10blurKernelPfS_ii,@object # @_Z10blurKernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z10blurKernelPfS_ii
.p2align 3, 0x0
_Z10blurKernelPfS_ii:
.quad _Z25__device_stub__blurKernelPfS_ii
.size _Z10blurKernelPfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "bluur.dat"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "lena.dat"
.size .L.str.2, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10blurKernelPfS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "HECHO"
.size .Lstr, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__blurKernelPfS_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z10blurKernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10blurKernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R15, R0, -0x3, RZ ; /* 0xfffffffd000f7810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3 R8, R5.reuse, -0x3, RZ ; /* 0xfffffffd05087810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*00e0*/ IADD3 R9, R5, -0x2, RZ ; /* 0xfffffffe05097810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R16, R15, c[0x0][0x170], R5 ; /* 0x00005c000f107a24 */
/* 0x000fe200078e0205 */
/*0100*/ IADD3 R10, R5.reuse, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x040fe20007ffe0ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IADD3 R11, R5.reuse, 0x1, RZ ; /* 0x00000001050b7810 */
/* 0x040fe40007ffe0ff */
/*0130*/ IADD3 R12, R5, 0x2, RZ ; /* 0x00000002050c7810 */
/* 0x000fc40007ffe0ff */
/*0140*/ IADD3 R14, R5, 0x3, RZ ; /* 0x00000003050e7810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GE.AND P5, PT, R15, c[0x0][0x174], PT ; /* 0x00005d000f007a0c */
/* 0x000fe20003fa6270 */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0170*/ LOP3.LUT R2, R8, R15, RZ, 0xfc, !PT ; /* 0x0000000f08027212 */
/* 0x000fe200078efcff */
/*0180*/ IMAD R3, R13, c[0x0][0x170], R16 ; /* 0x00005c000d037a24 */
/* 0x000fc600078e0210 */
/*0190*/ ISETP.LT.OR P4, PT, R2, RZ, P5 ; /* 0x000000ff0200720c */
/* 0x000fe20002f81670 */
/*01a0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0204 */
/*01b0*/ ISETP.GE.OR P4, PT, R8, c[0x0][0x170], P4 ; /* 0x00005c0008007a0c */
/* 0x000fda0002786670 */
/*01c0*/ @!P4 LDG.E R17, [R2.64+-0xc] ; /* 0xfffff4040211c981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ LOP3.LUT R18, R9, R15, RZ, 0xfc, !PT ; /* 0x0000000f09127212 */
/* 0x000fc800078efcff */
/*01e0*/ ISETP.LT.OR P3, PT, R18, RZ, P5 ; /* 0x000000ff1200720c */
/* 0x000fc80002f61670 */
/*01f0*/ ISETP.GE.OR P3, PT, R9, c[0x0][0x170], P3 ; /* 0x00005c0009007a0c */
/* 0x000fda0001f66670 */
/*0200*/ @!P3 LDG.E R22, [R2.64+-0x8] ; /* 0xfffff8040216b981 */
/* 0x000ee2000c1e1900 */
/*0210*/ LOP3.LUT R18, R10, R15, RZ, 0xfc, !PT ; /* 0x0000000f0a127212 */
/* 0x000fc800078efcff */
/*0220*/ ISETP.LT.OR P2, PT, R18, RZ, P5 ; /* 0x000000ff1200720c */
/* 0x000fc80002f41670 */
/*0230*/ ISETP.GT.OR P2, PT, R5, c[0x0][0x170], P2 ; /* 0x00005c0005007a0c */
/* 0x000fda0001744670 */
/*0240*/ @!P2 LDG.E R21, [R2.64+-0x4] ; /* 0xfffffc040215a981 */
/* 0x000f22000c1e1900 */
/*0250*/ LOP3.LUT R18, R5, R15, RZ, 0xfc, !PT ; /* 0x0000000f05127212 */
/* 0x000fc800078efcff */
/*0260*/ ISETP.LT.OR P6, PT, R18, RZ, P5 ; /* 0x000000ff1200720c */
/* 0x000fda0002fc1670 */
/*0270*/ @!P6 LDG.E R20, [R2.64] ; /* 0x000000040214e981 */
/* 0x000f62000c1e1900 */
/*0280*/ LOP3.LUT R18, R11, R15, RZ, 0xfc, !PT ; /* 0x0000000f0b127212 */
/* 0x000fc800078efcff */
/*0290*/ ISETP.LT.OR P1, PT, R18, RZ, P5 ; /* 0x000000ff1200720c */
/* 0x000fc80002f21670 */
/*02a0*/ ISETP.GE.OR P1, PT, R11, c[0x0][0x170], P1 ; /* 0x00005c000b007a0c */
/* 0x000fda0000f26670 */
/*02b0*/ @!P1 LDG.E R19, [R2.64+0x4] ; /* 0x0000040402139981 */
/* 0x001162000c1e1900 */
/*02c0*/ LOP3.LUT R18, R12, R15, RZ, 0xfc, !PT ; /* 0x0000000f0c127212 */
/* 0x000fc800078efcff */
/*02d0*/ ISETP.LT.OR P0, PT, R18, RZ, P5 ; /* 0x000000ff1200720c */
/* 0x000fc80002f01670 */
/*02e0*/ ISETP.GE.OR P0, PT, R12, c[0x0][0x170], P0 ; /* 0x00005c000c007a0c */
/* 0x000fda0000706670 */
/*02f0*/ @!P0 LDG.E R18, [R2.64+0x8] ; /* 0x0000080402128981 */
/* 0x000162000c1e1900 */
/*0300*/ LOP3.LUT R23, R14, R15, RZ, 0xfc, !PT ; /* 0x0000000f0e177212 */
/* 0x000fc800078efcff */
/*0310*/ ISETP.LT.OR P5, PT, R23, RZ, P5 ; /* 0x000000ff1700720c */
/* 0x000fc80002fa1670 */
/*0320*/ ISETP.GE.OR P5, PT, R14, c[0x0][0x170], P5 ; /* 0x00005c000e007a0c */
/* 0x000fda0002fa6670 */
/*0330*/ @!P5 LDG.E R23, [R2.64+0xc] ; /* 0x00000c040217d981 */
/* 0x000162000c1e1900 */
/*0340*/ @!P4 I2F R24, R7 ; /* 0x000000070018c306 */
/* 0x002ea20000201400 */
/*0350*/ @!P4 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606c810 */
/* 0x000fe40007ffe0ff */
/*0360*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe40007ffe0ff */
/*0370*/ @!P3 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606b810 */
/* 0x000fc80007ffe0ff */
/*0380*/ @!P2 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606a810 */
/* 0x000fc80007ffe0ff */
/*0390*/ @!P6 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606e810 */
/* 0x000fc80007ffe0ff */
/*03a0*/ @!P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106069810 */
/* 0x000fc80007ffe0ff */
/*03b0*/ @!P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106068810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ @!P5 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606d810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ @!P4 FADD R17, R24, R17 ; /* 0x000000111811c221 */
/* 0x004fc80000000000 */
/*03e0*/ @!P4 F2I.TRUNC.NTZ R7, R17 ; /* 0x000000110007c305 */
/* 0x000e70000020f100 */
/*03f0*/ @!P3 I2F R25, R7 ; /* 0x000000070019b306 */
/* 0x002ee40000201400 */
/*0400*/ @!P3 FADD R22, R25, R22 ; /* 0x000000161916b221 */
/* 0x008fcc0000000000 */
/*0410*/ @!P3 F2I.TRUNC.NTZ R7, R22 ; /* 0x000000160007b305 */
/* 0x000e70000020f100 */
/*0420*/ @!P2 I2F R24, R7 ; /* 0x000000070018a306 */
/* 0x002f240000201400 */
/*0430*/ @!P2 FADD R21, R24, R21 ; /* 0x000000151815a221 */
/* 0x010fcc0000000000 */
/*0440*/ @!P2 F2I.TRUNC.NTZ R7, R21 ; /* 0x000000150007a305 */
/* 0x000e70000020f100 */
/*0450*/ @!P6 I2F R25, R7 ; /* 0x000000070019e306 */
/* 0x002f640000201400 */
/*0460*/ @!P6 FADD R20, R25, R20 ; /* 0x000000141914e221 */
/* 0x020fcc0000000000 */
/*0470*/ @!P6 F2I.TRUNC.NTZ R7, R20 ; /* 0x000000140007e305 */
/* 0x000e30000020f100 */
/*0480*/ @!P1 I2F R2, R7 ; /* 0x0000000700029306 */
/* 0x001e240000201400 */
/*0490*/ @!P1 FADD R19, R2, R19 ; /* 0x0000001302139221 */
/* 0x001fcc0000000000 */
/*04a0*/ @!P1 F2I.TRUNC.NTZ R7, R19 ; /* 0x0000001300079305 */
/* 0x000e22000020f100 */
/*04b0*/ ISETP.NE.AND P1, PT, R13.reuse, 0x6, PT ; /* 0x000000060d00780c */
/* 0x040fe40003f25270 */
/*04c0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fca0007ffe0ff */
/*04d0*/ @!P0 I2F R3, R7 ; /* 0x0000000700038306 */
/* 0x001e240000201400 */
/*04e0*/ @!P0 FADD R18, R3, R18 ; /* 0x0000001203128221 */
/* 0x001fcc0000000000 */
/*04f0*/ @!P0 F2I.TRUNC.NTZ R7, R18 ; /* 0x0000001200078305 */
/* 0x000e30000020f100 */
/*0500*/ @!P5 I2F R2, R7 ; /* 0x000000070002d306 */
/* 0x001e240000201400 */
/*0510*/ @!P5 FADD R23, R2, R23 ; /* 0x000000170217d221 */
/* 0x001fcc0000000000 */
/*0520*/ @!P5 F2I.TRUNC.NTZ R7, R23 ; /* 0x000000170007d305 */
/* 0x000062000020f100 */
/*0530*/ @P1 BRA 0x150 ; /* 0xfffffc1000001947 */
/* 0x000fea000383ffff */
/*0540*/ IABS R9, R6.reuse ; /* 0x0000000600097213 */
/* 0x080fe20000000000 */
/*0550*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fe200078e0205 */
/*0560*/ IABS R12, R7 ; /* 0x00000007000c7213 */
/* 0x002fe40000000000 */
/*0570*/ I2F.RP R8, R9 ; /* 0x0000000900087306 */
/* 0x000e620000209400 */
/*0580*/ IABS R13, R6 ; /* 0x00000006000d7213 */
/* 0x000fe20000000000 */
/*0590*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fe200078e0204 */
/*05a0*/ LOP3.LUT R7, R7, R6, RZ, 0x3c, !PT ; /* 0x0000000607077212 */
/* 0x000fc800078e3cff */
/*05b0*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f46270 */
/*05c0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e640000001000 */
/*05d0*/ IADD3 R2, R8, 0xffffffe, RZ ; /* 0x0ffffffe08027810 */
/* 0x002fe20007ffe0ff */
/*05e0*/ IMAD.MOV R8, RZ, RZ, -R13 ; /* 0x000000ffff087224 */
/* 0x000fca00078e0a0d */
/*05f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0002a4000021f000 */
/*0600*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x002fe400078e00ff */
/*0610*/ IMAD.MOV R10, RZ, RZ, -R3 ; /* 0x000000ffff0a7224 */
/* 0x004fc800078e0a03 */
/*0620*/ IMAD R11, R10, R9, RZ ; /* 0x000000090a0b7224 */
/* 0x000fe400078e02ff */
/*0630*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000c */
/*0640*/ IMAD.HI.U32 R3, R3, R11, R2 ; /* 0x0000000b03037227 */
/* 0x000fcc00078e0002 */
/*0650*/ IMAD.HI.U32 R3, R3, R10, RZ ; /* 0x0000000a03037227 */
/* 0x000fc800078e00ff */
/*0660*/ IMAD R2, R3, R8, R10 ; /* 0x0000000803027224 */
/* 0x000fca00078e020a */
/*0670*/ ISETP.GT.U32.AND P1, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f24070 */
/*0680*/ @!P1 IMAD.IADD R2, R2, 0x1, -R9 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a09 */
/*0690*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*06b0*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fda0003f06070 */
/*06c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*06d0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*06e0*/ @!P1 LOP3.LUT R3, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff039212 */
/* 0x000fcc00078e33ff */
/*06f0*/ I2F R3, R3 ; /* 0x0000000300037306 */
/* 0x000e640000201400 */
/*0700*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x002fe2000c101904 */
/*0710*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0720*/ BRA 0x720; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10blurKernelPfS_ii
.globl _Z10blurKernelPfS_ii
.p2align 8
.type _Z10blurKernelPfS_ii,@function
_Z10blurKernelPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s15, s15, s2
v_add_nc_u32_e32 v0, s14, v2
v_add_nc_u32_e32 v1, s15, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s2, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
s_load_b64 s[8:9], s[0:1], 0x0
v_add3_u32 v3, v3, s15, -3
v_add3_u32 v5, v2, s14, -3
v_mov_b32_e32 v2, 0
s_mov_b32 s5, -3
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v4, s6, v3
v_mov_b32_e32 v3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, s6, v4
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 4
s_cbranch_scc1 .LBB0_9
.LBB0_3:
v_add_nc_u32_e32 v6, s5, v1
s_mov_b32 s10, 7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v6
v_cmp_gt_i32_e64 s2, s7, v6
v_mov_b32_e32 v6, v5
s_branch .LBB0_6
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v6, 1, v6
s_add_i32 s10, s10, -1
s_cmp_eq_u32 s10, 0
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_and_saveexec_b32 s11, vcc_lo
s_cbranch_execz .LBB0_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s3, -1, v6
v_cmp_gt_i32_e64 s4, s6, v6
s_and_b32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v7, v4, v6
v_cvt_f32_i32_e32 v2, v2
v_add_nc_u32_e32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s3, s8, v7
v_add_co_ci_u32_e64 v8, s3, s9, v8, s3
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v7, v2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v2
s_branch .LBB0_4
.LBB0_9:
s_set_inst_prefetch_distance 0x2
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v2
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v3, v4
v_add_nc_u32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v3, v4
v_xor_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v3, v5
v_sub_nc_u32_e32 v6, 0, v5
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v6, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v3, v6
v_add_nc_u32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_mul_lo_u32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v6
v_add_nc_u32_e32 v6, 1, v3
v_sub_nc_u32_e32 v8, v2, v5
v_cmp_ge_u32_e32 vcc_lo, v2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v8, v2, v8, vcc_lo
v_cndmask_b32_e32 v6, v3, v6, vcc_lo
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
v_xor_b32_e32 v0, v7, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ge_u32_e32 vcc_lo, v8, v5
v_add_nc_u32_e32 v9, 1, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_cndmask_b32_e32 v1, v6, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v0
v_sub_nc_u32_e32 v4, v1, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_cvt_f32_i32_e32 v2, v4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10blurKernelPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10blurKernelPfS_ii, .Lfunc_end0-_Z10blurKernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10blurKernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10blurKernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001034ac_00000000-6_image_blur.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3806:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3806:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii
.type _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii, @function
_Z34__device_stub__Z10blurKernelPfS_iiPfS_ii:
.LFB3828:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10blurKernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3828:
.size _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii, .-_Z34__device_stub__Z10blurKernelPfS_iiPfS_ii
.globl _Z10blurKernelPfS_ii
.type _Z10blurKernelPfS_ii, @function
_Z10blurKernelPfS_ii:
.LFB3829:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _Z10blurKernelPfS_ii, .-_Z10blurKernelPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10blurKernelPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3831:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10blurKernelPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3831:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "bluur.dat"
.LC2:
.string " "
.text
.globl _Z9save_dataPA225_fS0_S0_
.type _Z9save_dataPA225_fS0_S0_, @function
_Z9save_dataPA225_fS0_S0_:
.LFB3800:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3800
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $568, %rsp
.cfi_def_cfa_offset 624
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rbx
leaq 280(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 280(%rsp)
movq $0, 496(%rsp)
movb $0, 504(%rsp)
movb $0, 505(%rsp)
movq $0, 512(%rsp)
movq $0, 520(%rsp)
movq $0, 528(%rsp)
movq $0, 536(%rsp)
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 32(%rsp,%rax)
movq 32(%rsp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 280(%rsp)
leaq 40(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 40(%rsp), %rsi
leaq 280(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
leaq 40(%rsp), %rdi
movl $16, %edx
leaq .LC1(%rip), %rsi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L40
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L16
.L40:
movq 32(%rsp), %rax
movq -24(%rax), %rax
leaq 32(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE2:
.L16:
movq $0, (%rsp)
leaq .LC2(%rip), %r12
jmp .L15
.L35:
endbr64
movq %rax, %rbx
leaq 40(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L18:
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 32(%rsp,%rax)
.L19:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 280(%rsp)
leaq 280(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L34:
endbr64
movq %rax, %rbx
jmp .L18
.L33:
endbr64
movq %rax, %rbx
jmp .L19
.L20:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L42:
movq %rax, %rbp
movl $1, %edx
movq %r12, %rsi
movq %rax, %rdi
.LEHB4:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r12, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq $900, %rbx
je .L41
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx), %xmm0
leaq 32(%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L42
.L41:
movq 32(%rsp), %rax
movq -24(%rax), %rax
movq 272(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L43
cmpb $0, 56(%rbx)
je .L24
movzbl 67(%rbx), %eax
.L25:
movsbl %al, %esi
leaq 32(%rsp), %rdi
call _ZNSo3putEc@PLT
jmp .L44
.L43:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L32:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L45:
call __stack_chk_fail@PLT
.L24:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L25
.L44:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.LEHE4:
addq $900, (%rsp)
movq (%rsp), %rax
cmpq $202500, %rax
je .L26
.L15:
movq 8(%rsp), %rcx
movq (%rsp), %rax
leaq (%rcx,%rax), %r15
movq 16(%rsp), %rcx
leaq (%rcx,%rax), %r14
movq 24(%rsp), %rcx
leaq (%rcx,%rax), %r13
movl $0, %ebx
jmp .L21
.L26:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 40(%rax), %rax
movq %rax, 280(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rdi
.LEHB5:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE5:
jmp .L28
.L36:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L28:
leaq 144(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rcx
movq %rcx, 32(%rsp,%rax)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 280(%rsp)
leaq 280(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $568, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA3800:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3800-.LLSDATTD3800
.LLSDATTD3800:
.byte 0x1
.uleb128 .LLSDACSE3800-.LLSDACSB3800
.LLSDACSB3800:
.uleb128 .LEHB0-.LFB3800
.uleb128 .LEHE0-.LEHB0
.uleb128 .L33-.LFB3800
.uleb128 0
.uleb128 .LEHB1-.LFB3800
.uleb128 .LEHE1-.LEHB1
.uleb128 .L34-.LFB3800
.uleb128 0
.uleb128 .LEHB2-.LFB3800
.uleb128 .LEHE2-.LEHB2
.uleb128 .L35-.LFB3800
.uleb128 0
.uleb128 .LEHB3-.LFB3800
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB3800
.uleb128 .LEHE4-.LEHB4
.uleb128 .L32-.LFB3800
.uleb128 0
.uleb128 .LEHB5-.LFB3800
.uleb128 .LEHE5-.LEHB5
.uleb128 .L36-.LFB3800
.uleb128 0x1
.uleb128 .LEHB6-.LFB3800
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE3800:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT3800:
.text
.size _Z9save_dataPA225_fS0_S0_, .-_Z9save_dataPA225_fS0_S0_
.globl _Z4BlurPA225_fS0_S0_ii
.type _Z4BlurPA225_fS0_S0_ii, @function
_Z4BlurPA225_fS0_S0_ii:
.LFB3801:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -606208(%rsp), %r11
.cfi_def_cfa 11, 606264
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1384, %rsp
.cfi_def_cfa_offset 607648
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %r13
movl %ecx, %ebp
movl %r8d, %r12d
movq %fs:40, %rax
movq %rax, 607576(%rsp)
xorl %eax, %eax
movl %ecx, %ebx
imull %r8d, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leal 14(%rbp), %eax
movl %ebp, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $4, %eax
addl $1, %eax
movl %eax, 24(%rsp)
leal 14(%r12), %eax
movl %r12d, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $4, %eax
addl $1, %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl $16, 36(%rsp)
movl $16, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L48:
leaq 48(%rsp), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L49:
leaq 202560(%rsp), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L50:
leaq 405072(%rsp), %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 202560(%rsp), %rsi
leaq 48(%rsp), %rdi
movq %rbp, %rdx
call _Z9save_dataPA225_fS0_S0_
movq 607576(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $607592, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
movl %r12d, %ecx
movl %ebp, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii
jmp .L48
.L54:
movl %r12d, %ecx
movl %ebp, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii
jmp .L49
.L55:
movl %r12d, %ecx
movl %ebp, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10blurKernelPfS_iiPfS_ii
jmp .L50
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.size _Z4BlurPA225_fS0_S0_ii, .-_Z4BlurPA225_fS0_S0_ii
.section .rodata.str1.1
.LC3:
.string "lena.dat"
.text
.globl _Z9leer_dataPKcPA225_fS2_S2_
.type _Z9leer_dataPKcPA225_fS2_S2_, @function
_Z9leer_dataPKcPA225_fS2_S2_:
.LFB3802:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3802
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $648, %rsp
.cfi_def_cfa_offset 704
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %r15
movq %fs:40, %rax
movq %rax, 632(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
leaq 256(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 256(%rsp)
movq $0, 472(%rsp)
movb $0, 480(%rsp)
movb $0, 481(%rsp)
movq $0, 488(%rsp)
movq $0, 496(%rsp)
movq $0, 504(%rsp)
movq $0, 512(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rdx
movq %rdx, (%rsp,%rax)
movq $0, 8(%rsp)
movq (%rsp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB7:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE7:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
leaq 40(%rax), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rdi
.LEHB8:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE8:
leaq 16(%rsp), %rsi
leaq 256(%rsp), %rdi
.LEHB9:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
leaq 16(%rsp), %rdi
movl $8, %edx
leaq .LC3(%rip), %rsi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L84
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L60
.L84:
movq (%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE9:
.L60:
movq %r15, %rbp
addq $202500, %r15
movq %rsp, %r14
jmp .L59
.L79:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L62:
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rdx
movq %rdx, (%rsp,%rax)
movq $0, 8(%rsp)
.L63:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 256(%rsp)
leaq 256(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 632(%rsp), %rax
subq %fs:40, %rax
je .L64
call __stack_chk_fail@PLT
.L78:
endbr64
movq %rax, %rbx
jmp .L62
.L77:
endbr64
movq %rax, %rbx
jmp .L63
.L64:
movq %rbx, %rdi
.LEHB10:
call _Unwind_Resume@PLT
.LEHE10:
.L86:
movq %rax, %rdi
leaq (%r12,%rbx), %rsi
.LEHB11:
call _ZNSi10_M_extractIfEERSiRT_@PLT
movq %rax, %rdi
leaq 0(%rbp,%rbx), %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
addq $4, %rbx
cmpq $900, %rbx
je .L85
.L65:
leaq (%rbx,%r13), %rsi
movq %r14, %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
jmp .L86
.L85:
movq (%rsp), %rax
movq -24(%rax), %rax
movq 240(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L87
cmpb $0, 56(%rbx)
je .L68
movzbl 67(%rbx), %eax
.L69:
movsbl %al, %ecx
leaq 528(%rsp), %rsi
movl $100, %edx
movq %r14, %rdi
call _ZNSi7getlineEPclc@PLT
jmp .L88
.L87:
movq 632(%rsp), %rax
subq %fs:40, %rax
jne .L89
call _ZSt16__throw_bad_castv@PLT
.L76:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 632(%rsp), %rax
subq %fs:40, %rax
je .L74
call __stack_chk_fail@PLT
.L89:
call __stack_chk_fail@PLT
.L68:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
.LEHE11:
jmp .L69
.L88:
addq $900, %rbp
addq $900, %r12
addq $900, %r13
cmpq %r15, %rbp
je .L70
.L59:
movl $0, %ebx
jmp .L65
.L70:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
leaq 40(%rax), %rax
movq %rax, 256(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 16(%rsp), %rdi
.LEHB12:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE12:
jmp .L72
.L80:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L72:
leaq 120(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 72(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, (%rsp)
movq -24(%rax), %rax
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rdx
movq %rdx, (%rsp,%rax)
movq $0, 8(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 256(%rsp)
leaq 256(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 632(%rsp), %rax
subq %fs:40, %rax
jne .L90
addq $648, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L74:
.cfi_restore_state
movq %rbx, %rdi
.LEHB13:
call _Unwind_Resume@PLT
.LEHE13:
.L90:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3802:
.section .gcc_except_table
.align 4
.LLSDA3802:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3802-.LLSDATTD3802
.LLSDATTD3802:
.byte 0x1
.uleb128 .LLSDACSE3802-.LLSDACSB3802
.LLSDACSB3802:
.uleb128 .LEHB7-.LFB3802
.uleb128 .LEHE7-.LEHB7
.uleb128 .L77-.LFB3802
.uleb128 0
.uleb128 .LEHB8-.LFB3802
.uleb128 .LEHE8-.LEHB8
.uleb128 .L78-.LFB3802
.uleb128 0
.uleb128 .LEHB9-.LFB3802
.uleb128 .LEHE9-.LEHB9
.uleb128 .L79-.LFB3802
.uleb128 0
.uleb128 .LEHB10-.LFB3802
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.uleb128 .LEHB11-.LFB3802
.uleb128 .LEHE11-.LEHB11
.uleb128 .L76-.LFB3802
.uleb128 0
.uleb128 .LEHB12-.LFB3802
.uleb128 .LEHE12-.LEHB12
.uleb128 .L80-.LFB3802
.uleb128 0x1
.uleb128 .LEHB13-.LFB3802
.uleb128 .LEHE13-.LEHB13
.uleb128 0
.uleb128 0
.LLSDACSE3802:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT3802:
.text
.size _Z9leer_dataPKcPA225_fS2_S2_, .-_Z9leer_dataPKcPA225_fS2_S2_
.section .rodata.str1.1
.LC4:
.string "HECHO\n"
.text
.globl main
.type main, @function
main:
.LFB3803:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -606208(%rsp), %r11
.cfi_def_cfa 11, 606240
.LPSRL1:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL1
.cfi_def_cfa_register 7
subq $1328, %rsp
.cfi_def_cfa_offset 607568
movq %fs:40, %rax
movq %rax, 607528(%rsp)
xorl %eax, %eax
leaq 405024(%rsp), %r12
leaq 202512(%rsp), %rbp
movq %rsp, %rbx
movq %r12, %rcx
movq %rbp, %rdx
movq %rbx, %rsi
leaq .LC3(%rip), %rdi
call _Z9leer_dataPKcPA225_fS2_S2_
movl $225, %r8d
movl $225, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z4BlurPA225_fS0_S0_ii
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 607528(%rsp), %rax
subq %fs:40, %rax
jne .L94
movl $0, %eax
addq $607536, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3803:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "image_blur.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__blurKernelPfS_ii # -- Begin function _Z25__device_stub__blurKernelPfS_ii
.p2align 4, 0x90
.type _Z25__device_stub__blurKernelPfS_ii,@function
_Z25__device_stub__blurKernelPfS_ii: # @_Z25__device_stub__blurKernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10blurKernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__blurKernelPfS_ii, .Lfunc_end0-_Z25__device_stub__blurKernelPfS_ii
.cfi_endproc
# -- End function
.globl _Z9save_dataPA225_fS0_S0_ # -- Begin function _Z9save_dataPA225_fS0_S0_
.p2align 4, 0x90
.type _Z9save_dataPA225_fS0_S0_,@function
_Z9save_dataPA225_fS0_S0_: # @_Z9save_dataPA225_fS0_S0_
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $520, %rsp # imm = 0x208
.cfi_def_cfa_offset 576
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 8(%rsp), %r12
movl $.L.str, %esi
movq %r12, %rdi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movq %rbp, (%rsp) # 8-byte Spill
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp0:
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp1:
# %bb.3: # %_ZNSolsEf.exit
# in Loop: Header=BB1_2 Depth=2
.Ltmp2:
movq %rax, %r13
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp3:
# %bb.4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_2 Depth=2
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp4:
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp5:
# %bb.5: # %_ZNSolsEf.exit18
# in Loop: Header=BB1_2 Depth=2
.Ltmp6:
movq %rax, %r13
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit19
# in Loop: Header=BB1_2 Depth=2
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp8:
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp9:
# %bb.7: # %_ZNSolsEf.exit20
# in Loop: Header=BB1_2 Depth=2
.Ltmp10:
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp11:
# %bb.8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit21
# in Loop: Header=BB1_2 Depth=2
incq %rbp
cmpq $225, %rbp
jne .LBB1_2
# %bb.9: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movq -24(%rax), %rax
movq 248(%rsp,%rax), %r13
testq %r13, %r13
je .LBB1_10
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%r13)
movq (%rsp), %rbp # 8-byte Reload
je .LBB1_14
# %bb.13: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%r13), %eax
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_1 Depth=1
.Ltmp13:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp14:
# %bb.15: # %.noexc22
# in Loop: Header=BB1_1 Depth=1
movq (%r13), %rax
.Ltmp15:
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp16:
.LBB1_16: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB1_1 Depth=1
.Ltmp17:
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp18:
# %bb.17: # %.noexc24
# in Loop: Header=BB1_1 Depth=1
.Ltmp19:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp20:
# %bb.18: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_1 Depth=1
incq %rbp
addq $900, %rbx # imm = 0x384
addq $900, %r14 # imm = 0x384
addq $900, %r15 # imm = 0x384
cmpq $225, %rbp
jne .LBB1_1
# %bb.19:
leaq 8(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
addq $520, %rsp # imm = 0x208
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 576
.Ltmp22:
callq _ZSt16__throw_bad_castv
.Ltmp23:
# %bb.11: # %.noexc
.LBB1_21: # %.loopexit.split-lp
.Ltmp24:
jmp .LBB1_22
.LBB1_20: # %.loopexit
.Ltmp21:
jmp .LBB1_22
.LBB1_23:
.Ltmp12:
.LBB1_22:
movq %rax, %rbx
leaq 8(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _Z9save_dataPA225_fS0_S0_, .Lfunc_end1-_Z9save_dataPA225_fS0_S0_
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp11-.Ltmp0 # Call between .Ltmp0 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp20-.Ltmp13 # Call between .Ltmp13 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end1-.Ltmp23 # Call between .Ltmp23 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z4BlurPA225_fS0_S0_ii # -- Begin function _Z4BlurPA225_fS0_S0_ii
.p2align 4, 0x90
.type _Z4BlurPA225_fS0_S0_ii,@function
_Z4BlurPA225_fS0_S0_ii: # @_Z4BlurPA225_fS0_S0_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $607624, %rsp # imm = 0x94588
.cfi_def_cfa_offset 607680
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %r14d
movl %ecx, %r15d
movq %rdx, 88(%rsp) # 8-byte Spill
movq %rsi, %r12
movq %rdi, %rbp
movabsq $68719476752, %r13 # imm = 0x1000000010
movl %ecx, %eax
imull %r8d, %eax
shll $2, %eax
movslq %eax, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leal -1(%r15), %eax
leal 14(%r15), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
incl %ecx
leal -1(%r14), %eax
leal 14(%r14), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $4, %ebp
incl %ebp
shlq $32, %rbp
orq %rcx, %rbp
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 72(%rsp)
movl %r15d, 32(%rsp)
movl %r14d, 24(%rsp)
leaq 56(%rsp), %rax
movq %rax, 405120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 405128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 405136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 405144(%rsp)
leaq 202608(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 202608(%rsp), %rsi
movl 202616(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 405120(%rsp), %r9
movl $_Z10blurKernelPfS_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq (%rsp), %rsi
leaq 405120(%rsp), %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 48(%rsp)
movl %r15d, 24(%rsp)
movl %r14d, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 202608(%rsp)
leaq 48(%rsp), %rax
movq %rax, 202616(%rsp)
leaq 24(%rsp), %rax
movq %rax, 202624(%rsp)
leaq 20(%rsp), %rax
movq %rax, 202632(%rsp)
leaq 96(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 202608(%rsp), %r9
movl $_Z10blurKernelPfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
leaq 202608(%rsp), %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 88(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 84(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 84(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10blurKernelPfS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
leaq 96(%rsp), %r14
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
leaq 405120(%rsp), %rdi
leaq 202608(%rsp), %rsi
movq %r14, %rdx
callq _Z9save_dataPA225_fS0_S0_
addq $607624, %rsp # imm = 0x94588
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z4BlurPA225_fS0_S0_ii, .Lfunc_end2-_Z4BlurPA225_fS0_S0_ii
.cfi_endproc
# -- End function
.globl _Z9leer_dataPKcPA225_fS2_S2_ # -- Begin function _Z9leer_dataPKcPA225_fS2_S2_
.p2align 4, 0x90
.type _Z9leer_dataPKcPA225_fS2_S2_,@function
_Z9leer_dataPKcPA225_fS2_S2_: # @_Z9leer_dataPKcPA225_fS2_S2_
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $632, %rsp # imm = 0x278
.cfi_def_cfa_offset 688
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
leaq 8(%rsp), %r12
movl $.L.str.2, %esi
movq %r12, %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%rbp), %rsi
.Ltmp25:
movq %r12, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp26:
# %bb.3: # %_ZNSirsERf.exit
# in Loop: Header=BB3_2 Depth=2
leaq (%r14,%rbp), %rsi
.Ltmp27:
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp28:
# %bb.4: # %_ZNSirsERf.exit23
# in Loop: Header=BB3_2 Depth=2
leaq (%rbx,%rbp), %rsi
.Ltmp29:
movq %rax, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp30:
# %bb.5: # %_ZNSirsERf.exit25
# in Loop: Header=BB3_2 Depth=2
addq $4, %rbp
cmpq $900, %rbp # imm = 0x384
jne .LBB3_2
# %bb.6: # in Loop: Header=BB3_1 Depth=1
movq 8(%rsp), %rax
movq -24(%rax), %rax
movq 248(%rsp,%rax), %rbp
testq %rbp, %rbp
je .LBB3_7
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB3_1 Depth=1
cmpb $0, 56(%rbp)
je .LBB3_11
# %bb.10: # in Loop: Header=BB3_1 Depth=1
movzbl 67(%rbp), %eax
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_1 Depth=1
.Ltmp32:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp33:
# %bb.12: # %.noexc18
# in Loop: Header=BB3_1 Depth=1
movq (%rbp), %rax
.Ltmp34:
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp35:
.LBB3_13: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB3_1 Depth=1
.Ltmp36:
movsbl %al, %ecx
movl $100, %edx
movq %r12, %rdi
leaq 528(%rsp), %rsi
callq _ZNSi7getlineEPclc
.Ltmp37:
# %bb.14: # %_ZNSi7getlineEPcl.exit
# in Loop: Header=BB3_1 Depth=1
incq %r13
addq $900, %rbx # imm = 0x384
addq $900, %r14 # imm = 0x384
addq $900, %r15 # imm = 0x384
cmpq $225, %r13
jne .LBB3_1
# %bb.15:
leaq 8(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 264(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
addq $632, %rsp # imm = 0x278
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 688
.Ltmp39:
callq _ZSt16__throw_bad_castv
.Ltmp40:
# %bb.8: # %.noexc
.LBB3_17: # %.loopexit.split-lp
.Ltmp41:
jmp .LBB3_18
.LBB3_16: # %.loopexit
.Ltmp38:
jmp .LBB3_18
.LBB3_19:
.Ltmp31:
.LBB3_18:
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 264(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size _Z9leer_dataPKcPA225_fS2_S2_, .Lfunc_end3-_Z9leer_dataPKcPA225_fS2_S2_
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp25-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp25
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp30-.Ltmp25 # Call between .Ltmp25 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin1 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp37-.Ltmp32 # Call between .Ltmp32 and .Ltmp37
.uleb128 .Ltmp38-.Lfunc_begin1 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin1 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Lfunc_end3-.Ltmp40 # Call between .Ltmp40 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $607536, %rsp # imm = 0x94530
.cfi_def_cfa_offset 607568
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 405024(%rsp), %rbx
leaq 202512(%rsp), %r14
movq %rsp, %r15
movq %rbx, %rsi
movq %r14, %rdx
movq %r15, %rcx
callq _Z9leer_dataPKcPA225_fS2_S2_
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $225, %ecx
movl $225, %r8d
callq _Z4BlurPA225_fS0_S0_ii
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $607536, %rsp # imm = 0x94530
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10blurKernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10blurKernelPfS_ii,@object # @_Z10blurKernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z10blurKernelPfS_ii
.p2align 3, 0x0
_Z10blurKernelPfS_ii:
.quad _Z25__device_stub__blurKernelPfS_ii
.size _Z10blurKernelPfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "bluur.dat"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "lena.dat"
.size .L.str.2, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10blurKernelPfS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "HECHO"
.size .Lstr, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__blurKernelPfS_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z10blurKernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
static void HandleError(cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
cout << cudaGetErrorString(err) << " in "
<< file << " at line " << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
//#define MAGNITUDE (1)
#define MAGNITUDE (1024 * 1024)
#define NUM_BLOCKS 8 * MAGNITUDE
#define NUM_THREADS 16
#define NUM_ELEM 100 * MAGNITUDE
__global__ void kernel_compute(int* data) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// invalid access
data[idx] = 1111 * idx;
}
int main(int argc, char *argv[]) {
int* data = NULL;
// echivalent cu macroul DIE
HANDLE_ERROR(cudaMalloc(&data, 1 * sizeof(int)));
// launch kernel
kernel_compute<<<NUM_BLOCKS, NUM_THREADS>>>(data);
HANDLE_ERROR(cudaDeviceSynchronize());
return 0;
} | code for sm_80
Function : _Z14kernel_computePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R5, R2.reuse, 0x457, RZ ; /* 0x0000045702057824 */
/* 0x040fe400078e02ff */
/*0070*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
static void HandleError(cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
cout << cudaGetErrorString(err) << " in "
<< file << " at line " << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
//#define MAGNITUDE (1)
#define MAGNITUDE (1024 * 1024)
#define NUM_BLOCKS 8 * MAGNITUDE
#define NUM_THREADS 16
#define NUM_ELEM 100 * MAGNITUDE
__global__ void kernel_compute(int* data) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// invalid access
data[idx] = 1111 * idx;
}
int main(int argc, char *argv[]) {
int* data = NULL;
// echivalent cu macroul DIE
HANDLE_ERROR(cudaMalloc(&data, 1 * sizeof(int)));
// launch kernel
kernel_compute<<<NUM_BLOCKS, NUM_THREADS>>>(data);
HANDLE_ERROR(cudaDeviceSynchronize());
return 0;
} | .file "tmpxft_00080dc0_00000000-6_debug.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " in "
.LC1:
.string " at line "
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movl %edx, %ebx
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z14kernel_computePiPi
.type _Z34__device_stub__Z14kernel_computePiPi, @function
_Z34__device_stub__Z14kernel_computePiPi:
.LFB3695:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14kernel_computePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z34__device_stub__Z14kernel_computePiPi, .-_Z34__device_stub__Z14kernel_computePiPi
.globl _Z14kernel_computePi
.type _Z14kernel_computePi, @function
_Z14kernel_computePi:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14kernel_computePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z14kernel_computePi, .-_Z14kernel_computePi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/florinrm/ASC-Lab-Tutorial/master/Lab8/debug.cu"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $30, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $8388608, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $34, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z34__device_stub__Z14kernel_computePiPi
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z14kernel_computePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernel_computePi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
static void HandleError(cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
cout << cudaGetErrorString(err) << " in "
<< file << " at line " << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
//#define MAGNITUDE (1)
#define MAGNITUDE (1024 * 1024)
#define NUM_BLOCKS 8 * MAGNITUDE
#define NUM_THREADS 16
#define NUM_ELEM 100 * MAGNITUDE
__global__ void kernel_compute(int* data) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// invalid access
data[idx] = 1111 * idx;
}
int main(int argc, char *argv[]) {
int* data = NULL;
// echivalent cu macroul DIE
HANDLE_ERROR(cudaMalloc(&data, 1 * sizeof(int)));
// launch kernel
kernel_compute<<<NUM_BLOCKS, NUM_THREADS>>>(data);
HANDLE_ERROR(cudaDeviceSynchronize());
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
static void HandleError(hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
cout << hipGetErrorString(err) << " in "
<< file << " at line " << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
//#define MAGNITUDE (1)
#define MAGNITUDE (1024 * 1024)
#define NUM_BLOCKS 8 * MAGNITUDE
#define NUM_THREADS 16
#define NUM_ELEM 100 * MAGNITUDE
__global__ void kernel_compute(int* data) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// invalid access
data[idx] = 1111 * idx;
}
int main(int argc, char *argv[]) {
int* data = NULL;
// echivalent cu macroul DIE
HANDLE_ERROR(hipMalloc(&data, 1 * sizeof(int)));
// launch kernel
kernel_compute<<<NUM_BLOCKS, NUM_THREADS>>>(data);
HANDLE_ERROR(hipDeviceSynchronize());
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
static void HandleError(hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
cout << hipGetErrorString(err) << " in "
<< file << " at line " << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
//#define MAGNITUDE (1)
#define MAGNITUDE (1024 * 1024)
#define NUM_BLOCKS 8 * MAGNITUDE
#define NUM_THREADS 16
#define NUM_ELEM 100 * MAGNITUDE
__global__ void kernel_compute(int* data) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// invalid access
data[idx] = 1111 * idx;
}
int main(int argc, char *argv[]) {
int* data = NULL;
// echivalent cu macroul DIE
HANDLE_ERROR(hipMalloc(&data, 1 * sizeof(int)));
// launch kernel
kernel_compute<<<NUM_BLOCKS, NUM_THREADS>>>(data);
HANDLE_ERROR(hipDeviceSynchronize());
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14kernel_computePi
.globl _Z14kernel_computePi
.p2align 8
.type _Z14kernel_computePi,@function
_Z14kernel_computePi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v4, v1, 0x457
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14kernel_computePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14kernel_computePi, .Lfunc_end0-_Z14kernel_computePi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14kernel_computePi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14kernel_computePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
static void HandleError(hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
cout << hipGetErrorString(err) << " in "
<< file << " at line " << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
//#define MAGNITUDE (1)
#define MAGNITUDE (1024 * 1024)
#define NUM_BLOCKS 8 * MAGNITUDE
#define NUM_THREADS 16
#define NUM_ELEM 100 * MAGNITUDE
__global__ void kernel_compute(int* data) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// invalid access
data[idx] = 1111 * idx;
}
int main(int argc, char *argv[]) {
int* data = NULL;
// echivalent cu macroul DIE
HANDLE_ERROR(hipMalloc(&data, 1 * sizeof(int)));
// launch kernel
kernel_compute<<<NUM_BLOCKS, NUM_THREADS>>>(data);
HANDLE_ERROR(hipDeviceSynchronize());
return 0;
} | .text
.file "debug.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__kernel_computePi # -- Begin function _Z29__device_stub__kernel_computePi
.p2align 4, 0x90
.type _Z29__device_stub__kernel_computePi,@function
_Z29__device_stub__kernel_computePi: # @_Z29__device_stub__kernel_computePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14kernel_computePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__kernel_computePi, .Lfunc_end0-_Z29__device_stub__kernel_computePi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl %eax, %edi
movl $32, %esi
callq _ZL11HandleError10hipError_tPKci
movabsq $4294967312, %rdx # imm = 0x100000010
leaq 8388592(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14kernel_computePi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl %eax, %edi
movl $36, %esi
callq _ZL11HandleError10hipError_tPKci
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL11HandleError10hipError_tPKci
.type _ZL11HandleError10hipError_tPKci,@function
_ZL11HandleError10hipError_tPKci: # @_ZL11HandleError10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB2_2
# %bb.1:
retq
.LBB2_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %ebx
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end2:
.size _ZL11HandleError10hipError_tPKci, .Lfunc_end2-_ZL11HandleError10hipError_tPKci
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernel_computePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14kernel_computePi,@object # @_Z14kernel_computePi
.section .rodata,"a",@progbits
.globl _Z14kernel_computePi
.p2align 3, 0x0
_Z14kernel_computePi:
.quad _Z29__device_stub__kernel_computePi
.size _Z14kernel_computePi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/florinrm/ASC-Lab-Tutorial/master/Lab8/debug.hip"
.size .L.str, 105
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " in "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " at line "
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14kernel_computePi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__kernel_computePi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14kernel_computePi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14kernel_computePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R5, R2.reuse, 0x457, RZ ; /* 0x0000045702057824 */
/* 0x040fe400078e02ff */
/*0070*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14kernel_computePi
.globl _Z14kernel_computePi
.p2align 8
.type _Z14kernel_computePi,@function
_Z14kernel_computePi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v4, v1, 0x457
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14kernel_computePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14kernel_computePi, .Lfunc_end0-_Z14kernel_computePi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14kernel_computePi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14kernel_computePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00080dc0_00000000-6_debug.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " in "
.LC1:
.string " at line "
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movl %edx, %ebx
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z14kernel_computePiPi
.type _Z34__device_stub__Z14kernel_computePiPi, @function
_Z34__device_stub__Z14kernel_computePiPi:
.LFB3695:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14kernel_computePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z34__device_stub__Z14kernel_computePiPi, .-_Z34__device_stub__Z14kernel_computePiPi
.globl _Z14kernel_computePi
.type _Z14kernel_computePi, @function
_Z14kernel_computePi:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14kernel_computePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z14kernel_computePi, .-_Z14kernel_computePi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/florinrm/ASC-Lab-Tutorial/master/Lab8/debug.cu"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $30, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $8388608, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $34, %edx
leaq .LC2(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z34__device_stub__Z14kernel_computePiPi
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z14kernel_computePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernel_computePi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "debug.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__kernel_computePi # -- Begin function _Z29__device_stub__kernel_computePi
.p2align 4, 0x90
.type _Z29__device_stub__kernel_computePi,@function
_Z29__device_stub__kernel_computePi: # @_Z29__device_stub__kernel_computePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14kernel_computePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__kernel_computePi, .Lfunc_end0-_Z29__device_stub__kernel_computePi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl %eax, %edi
movl $32, %esi
callq _ZL11HandleError10hipError_tPKci
movabsq $4294967312, %rdx # imm = 0x100000010
leaq 8388592(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14kernel_computePi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl %eax, %edi
movl $36, %esi
callq _ZL11HandleError10hipError_tPKci
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL11HandleError10hipError_tPKci
.type _ZL11HandleError10hipError_tPKci,@function
_ZL11HandleError10hipError_tPKci: # @_ZL11HandleError10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB2_2
# %bb.1:
retq
.LBB2_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %ebx
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end2:
.size _ZL11HandleError10hipError_tPKci, .Lfunc_end2-_ZL11HandleError10hipError_tPKci
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernel_computePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14kernel_computePi,@object # @_Z14kernel_computePi
.section .rodata,"a",@progbits
.globl _Z14kernel_computePi
.p2align 3, 0x0
_Z14kernel_computePi:
.quad _Z29__device_stub__kernel_computePi
.size _Z14kernel_computePi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/florinrm/ASC-Lab-Tutorial/master/Lab8/debug.hip"
.size .L.str, 105
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " in "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " at line "
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14kernel_computePi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__kernel_computePi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14kernel_computePi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Passing array of a Class and assigning elements at odd/even elements to another array.
// @alpha74
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include "stdio.h"
using namespace std;
class Coord
{
int x;
int y;
public:
Coord()
{
x = 0;
y = 0;
}
void set(int a, int b)
{
x = a;
y = b;
}
void print()
{
printf(" (%d,%d) ", x, y);
}
};
__global__ void foo( int lim, Coord C[], Coord *oddi, Coord *eveni)
{
int tid = blockIdx.x;
if (tid < lim)
{
if (tid % 2 == 0)
{
eveni[tid / 2] = C[tid];
}
else
{
oddi[tid / 2] = C[tid];
}
}
}
int main()
{
const int N = 20;
// Declare an array of size N
Coord C[N];
Coord result_odd[ N/2], result_even[ N/2 ];
// Initialize the elements
for (int i = 0; i < N; i++)
{
if (i % 2 == 0)
{
C[i].set(2, 2);
}
else
C[i].set(-1, -1);
}
// Declare and allocate device memory
Coord *dev_C;
Coord *dev_odd, *dev_even;
cudaMalloc((void**)&dev_C, N * sizeof(Coord));
cudaMalloc((void**)&dev_odd, N / 2 * sizeof(Coord));
cudaMalloc((void**)&dev_even, N / 2 * sizeof(Coord));
cudaMemcpy(dev_C, C, N * sizeof(Coord), cudaMemcpyHostToDevice);
cudaMemcpy(dev_odd, C, N/2 * sizeof(Coord), cudaMemcpyHostToDevice); // Adding part of the array for comparison.
cudaMemcpy(dev_even, C, N / 2 * sizeof(Coord), cudaMemcpyHostToDevice); // Adding part of the array for comparison.
foo <<<N, 1 >>> ( N, dev_C, dev_odd, dev_even );
// Copying back the results
cudaMemcpy(&result_even, dev_even, N/2 * sizeof(Coord), cudaMemcpyDeviceToHost);
cudaMemcpy(&result_odd, dev_odd, N/2 * sizeof(Coord), cudaMemcpyDeviceToHost);
cout << "\n At even pos: ";
for (int i = 0 ; i < N / 2; i++)
{
result_even[i].print();
}
cout << "\n At odd pos: ";
for (int i = 0; i < N / 2; i++)
{
result_odd[i].print();
}
cout << "\n ";
// Freeing device memory
cudaFree(dev_C);
cudaFree(dev_odd);
cudaFree(dev_even);
return 0;
} | code for sm_80
Function : _Z3fooiP5CoordS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ee2000c1e1900 */
/*0090*/ LOP3.LUT R0, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104007812 */
/* 0x000fc800078ec0ff */
/*00a0*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f05070 */
/*00b0*/ LEA.HI R0, R4, R4, RZ, 0x1 ; /* 0x0000000404007211 */
/* 0x000fc800078f08ff */
/*00c0*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc80000011400 */
/*00d0*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fc60000011400 */
/*00e0*/ @!P0 LEA R4, P1, R0, c[0x0][0x170], 0x3 ; /* 0x00005c0000048a11 */
/* 0x000fc800078218ff */
/*00f0*/ @!P0 LEA.HI.X R5, R0, c[0x0][0x174], R11, 0x3, P1 ; /* 0x00005d0000058a11 */
/* 0x000fca00008f1c0b */
/*0100*/ @!P0 STG.E [R4.64], R7 ; /* 0x0000000704008986 */
/* 0x0041e8000c101904 */
/*0110*/ @!P0 STG.E [R4.64+0x4], R9 ; /* 0x0000040904008986 */
/* 0x0081e2000c101904 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0130*/ LEA R2, P0, R0, c[0x0][0x178], 0x3 ; /* 0x00005e0000027a11 */
/* 0x000fc800078018ff */
/*0140*/ LEA.HI.X R3, R0, c[0x0][0x17c], R11, 0x3, P0 ; /* 0x00005f0000037a11 */
/* 0x000fca00000f1c0b */
/*0150*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0160*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Passing array of a Class and assigning elements at odd/even elements to another array.
// @alpha74
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include "stdio.h"
using namespace std;
class Coord
{
int x;
int y;
public:
Coord()
{
x = 0;
y = 0;
}
void set(int a, int b)
{
x = a;
y = b;
}
void print()
{
printf(" (%d,%d) ", x, y);
}
};
__global__ void foo( int lim, Coord C[], Coord *oddi, Coord *eveni)
{
int tid = blockIdx.x;
if (tid < lim)
{
if (tid % 2 == 0)
{
eveni[tid / 2] = C[tid];
}
else
{
oddi[tid / 2] = C[tid];
}
}
}
int main()
{
const int N = 20;
// Declare an array of size N
Coord C[N];
Coord result_odd[ N/2], result_even[ N/2 ];
// Initialize the elements
for (int i = 0; i < N; i++)
{
if (i % 2 == 0)
{
C[i].set(2, 2);
}
else
C[i].set(-1, -1);
}
// Declare and allocate device memory
Coord *dev_C;
Coord *dev_odd, *dev_even;
cudaMalloc((void**)&dev_C, N * sizeof(Coord));
cudaMalloc((void**)&dev_odd, N / 2 * sizeof(Coord));
cudaMalloc((void**)&dev_even, N / 2 * sizeof(Coord));
cudaMemcpy(dev_C, C, N * sizeof(Coord), cudaMemcpyHostToDevice);
cudaMemcpy(dev_odd, C, N/2 * sizeof(Coord), cudaMemcpyHostToDevice); // Adding part of the array for comparison.
cudaMemcpy(dev_even, C, N / 2 * sizeof(Coord), cudaMemcpyHostToDevice); // Adding part of the array for comparison.
foo <<<N, 1 >>> ( N, dev_C, dev_odd, dev_even );
// Copying back the results
cudaMemcpy(&result_even, dev_even, N/2 * sizeof(Coord), cudaMemcpyDeviceToHost);
cudaMemcpy(&result_odd, dev_odd, N/2 * sizeof(Coord), cudaMemcpyDeviceToHost);
cout << "\n At even pos: ";
for (int i = 0 ; i < N / 2; i++)
{
result_even[i].print();
}
cout << "\n At odd pos: ";
for (int i = 0; i < N / 2; i++)
{
result_odd[i].print();
}
cout << "\n ";
// Freeing device memory
cudaFree(dev_C);
cudaFree(dev_odd);
cudaFree(dev_even);
return 0;
} | .file "tmpxft_001943c1_00000000-6_extract_odd_even.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_
.type _Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_, @function
_Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3fooiP5CoordS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_, .-_Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_
.globl _Z3fooiP5CoordS0_S0_
.type _Z3fooiP5CoordS0_S0_, @function
_Z3fooiP5CoordS0_S0_:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z3fooiP5CoordS0_S0_, .-_Z3fooiP5CoordS0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n At even pos: "
.LC1:
.string " (%d,%d) "
.LC2:
.string "\n At odd pos: "
.LC3:
.string "\n "
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $384, %rsp
.cfi_def_cfa_offset 432
movq %fs:40, %rax
movq %rax, 376(%rsp)
xorl %eax, %eax
leaq 208(%rsp), %rdx
leaq 368(%rsp), %rcx
movq %rdx, %rax
.L12:
movl $0, (%rax)
movl $0, 4(%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L12
leaq 48(%rsp), %rbx
leaq 128(%rsp), %r12
movq %rbx, %rax
.L13:
movl $0, (%rax)
movl $0, 4(%rax)
addq $8, %rax
cmpq %r12, %rax
jne .L13
leaq 128(%rsp), %rbp
leaq 208(%rsp), %r13
movq %rbp, %rax
.L14:
movl $0, (%rax)
movl $0, 4(%rax)
addq $8, %rax
cmpq %r13, %rax
jne .L14
movl $0, %ecx
.L16:
movl %ecx, %eax
andl $1, %eax
negl %eax
sbbl %eax, %eax
orl $2, %eax
movl %eax, (%rdx)
movl %eax, 4(%rdx)
addl $1, %ecx
addq $8, %rdx
cmpl $20, %ecx
jne .L16
movq %rsp, %rdi
movl $160, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 208(%rsp), %r14
movl $1, %ecx
movl $160, %edx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $20, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L17:
leaq 128(%rsp), %rdi
movl $2, %ecx
movl $80, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $80, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC1(%rip), %r14
.L18:
movl 4(%rbp), %ecx
movl 0(%rbp), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbp
cmpq %r13, %rbp
jne .L18
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC1(%rip), %rbp
.L19:
movl 4(%rbx), %ecx
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L19
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 376(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $20, %edi
call _Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_
jmp .L17
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3fooiP5CoordS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooiP5CoordS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Passing array of a Class and assigning elements at odd/even elements to another array.
// @alpha74
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include "stdio.h"
using namespace std;
class Coord
{
int x;
int y;
public:
Coord()
{
x = 0;
y = 0;
}
void set(int a, int b)
{
x = a;
y = b;
}
void print()
{
printf(" (%d,%d) ", x, y);
}
};
__global__ void foo( int lim, Coord C[], Coord *oddi, Coord *eveni)
{
int tid = blockIdx.x;
if (tid < lim)
{
if (tid % 2 == 0)
{
eveni[tid / 2] = C[tid];
}
else
{
oddi[tid / 2] = C[tid];
}
}
}
int main()
{
const int N = 20;
// Declare an array of size N
Coord C[N];
Coord result_odd[ N/2], result_even[ N/2 ];
// Initialize the elements
for (int i = 0; i < N; i++)
{
if (i % 2 == 0)
{
C[i].set(2, 2);
}
else
C[i].set(-1, -1);
}
// Declare and allocate device memory
Coord *dev_C;
Coord *dev_odd, *dev_even;
cudaMalloc((void**)&dev_C, N * sizeof(Coord));
cudaMalloc((void**)&dev_odd, N / 2 * sizeof(Coord));
cudaMalloc((void**)&dev_even, N / 2 * sizeof(Coord));
cudaMemcpy(dev_C, C, N * sizeof(Coord), cudaMemcpyHostToDevice);
cudaMemcpy(dev_odd, C, N/2 * sizeof(Coord), cudaMemcpyHostToDevice); // Adding part of the array for comparison.
cudaMemcpy(dev_even, C, N / 2 * sizeof(Coord), cudaMemcpyHostToDevice); // Adding part of the array for comparison.
foo <<<N, 1 >>> ( N, dev_C, dev_odd, dev_even );
// Copying back the results
cudaMemcpy(&result_even, dev_even, N/2 * sizeof(Coord), cudaMemcpyDeviceToHost);
cudaMemcpy(&result_odd, dev_odd, N/2 * sizeof(Coord), cudaMemcpyDeviceToHost);
cout << "\n At even pos: ";
for (int i = 0 ; i < N / 2; i++)
{
result_even[i].print();
}
cout << "\n At odd pos: ";
for (int i = 0; i < N / 2; i++)
{
result_odd[i].print();
}
cout << "\n ";
// Freeing device memory
cudaFree(dev_C);
cudaFree(dev_odd);
cudaFree(dev_even);
return 0;
} | // Passing array of a Class and assigning elements at odd/even elements to another array.
// @alpha74
#include "hip/hip_runtime.h"
#include <iostream>
#include "stdio.h"
using namespace std;
class Coord
{
int x;
int y;
public:
Coord()
{
x = 0;
y = 0;
}
void set(int a, int b)
{
x = a;
y = b;
}
void print()
{
printf(" (%d,%d) ", x, y);
}
};
__global__ void foo( int lim, Coord C[], Coord *oddi, Coord *eveni)
{
int tid = blockIdx.x;
if (tid < lim)
{
if (tid % 2 == 0)
{
eveni[tid / 2] = C[tid];
}
else
{
oddi[tid / 2] = C[tid];
}
}
}
int main()
{
const int N = 20;
// Declare an array of size N
Coord C[N];
Coord result_odd[ N/2], result_even[ N/2 ];
// Initialize the elements
for (int i = 0; i < N; i++)
{
if (i % 2 == 0)
{
C[i].set(2, 2);
}
else
C[i].set(-1, -1);
}
// Declare and allocate device memory
Coord *dev_C;
Coord *dev_odd, *dev_even;
hipMalloc((void**)&dev_C, N * sizeof(Coord));
hipMalloc((void**)&dev_odd, N / 2 * sizeof(Coord));
hipMalloc((void**)&dev_even, N / 2 * sizeof(Coord));
hipMemcpy(dev_C, C, N * sizeof(Coord), hipMemcpyHostToDevice);
hipMemcpy(dev_odd, C, N/2 * sizeof(Coord), hipMemcpyHostToDevice); // Adding part of the array for comparison.
hipMemcpy(dev_even, C, N / 2 * sizeof(Coord), hipMemcpyHostToDevice); // Adding part of the array for comparison.
foo <<<N, 1 >>> ( N, dev_C, dev_odd, dev_even );
// Copying back the results
hipMemcpy(&result_even, dev_even, N/2 * sizeof(Coord), hipMemcpyDeviceToHost);
hipMemcpy(&result_odd, dev_odd, N/2 * sizeof(Coord), hipMemcpyDeviceToHost);
cout << "\n At even pos: ";
for (int i = 0 ; i < N / 2; i++)
{
result_even[i].print();
}
cout << "\n At odd pos: ";
for (int i = 0; i < N / 2; i++)
{
result_odd[i].print();
}
cout << "\n ";
// Freeing device memory
hipFree(dev_C);
hipFree(dev_odd);
hipFree(dev_even);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Passing array of a Class and assigning elements at odd/even elements to another array.
// @alpha74
#include "hip/hip_runtime.h"
#include <iostream>
#include "stdio.h"
using namespace std;
class Coord
{
int x;
int y;
public:
Coord()
{
x = 0;
y = 0;
}
void set(int a, int b)
{
x = a;
y = b;
}
void print()
{
printf(" (%d,%d) ", x, y);
}
};
__global__ void foo( int lim, Coord C[], Coord *oddi, Coord *eveni)
{
int tid = blockIdx.x;
if (tid < lim)
{
if (tid % 2 == 0)
{
eveni[tid / 2] = C[tid];
}
else
{
oddi[tid / 2] = C[tid];
}
}
}
int main()
{
const int N = 20;
// Declare an array of size N
Coord C[N];
Coord result_odd[ N/2], result_even[ N/2 ];
// Initialize the elements
for (int i = 0; i < N; i++)
{
if (i % 2 == 0)
{
C[i].set(2, 2);
}
else
C[i].set(-1, -1);
}
// Declare and allocate device memory
Coord *dev_C;
Coord *dev_odd, *dev_even;
hipMalloc((void**)&dev_C, N * sizeof(Coord));
hipMalloc((void**)&dev_odd, N / 2 * sizeof(Coord));
hipMalloc((void**)&dev_even, N / 2 * sizeof(Coord));
hipMemcpy(dev_C, C, N * sizeof(Coord), hipMemcpyHostToDevice);
hipMemcpy(dev_odd, C, N/2 * sizeof(Coord), hipMemcpyHostToDevice); // Adding part of the array for comparison.
hipMemcpy(dev_even, C, N / 2 * sizeof(Coord), hipMemcpyHostToDevice); // Adding part of the array for comparison.
foo <<<N, 1 >>> ( N, dev_C, dev_odd, dev_even );
// Copying back the results
hipMemcpy(&result_even, dev_even, N/2 * sizeof(Coord), hipMemcpyDeviceToHost);
hipMemcpy(&result_odd, dev_odd, N/2 * sizeof(Coord), hipMemcpyDeviceToHost);
cout << "\n At even pos: ";
for (int i = 0 ; i < N / 2; i++)
{
result_even[i].print();
}
cout << "\n At odd pos: ";
for (int i = 0; i < N / 2; i++)
{
result_odd[i].print();
}
cout << "\n ";
// Freeing device memory
hipFree(dev_C);
hipFree(dev_odd);
hipFree(dev_even);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooiP5CoordS0_S0_
.globl _Z3fooiP5CoordS0_S0_
.p2align 8
.type _Z3fooiP5CoordS0_S0_,@function
_Z3fooiP5CoordS0_S0_:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x8
s_bitcmp1_b32 s15, 0
s_mov_b32 s2, s15
s_cselect_b32 s8, -1, 0
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[2:3], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_and_b32 vcc_lo, exec_lo, s8
s_load_b64 s[4:5], s[4:5], 0x0
s_cbranch_vccz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x10
s_lshr_b32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s2, s3
s_ashr_i32 s8, s3, 1
s_cbranch_execz .LBB0_4
s_branch .LBB0_5
.LBB0_3:
.LBB0_4:
s_waitcnt lgkmcnt(0)
s_load_b64 s[6:7], s[0:1], 0x18
s_ashr_i32 s8, s2, 1
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s4
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
s_lshl_b64 s[0:1], s[8:9], 3
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooiP5CoordS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooiP5CoordS0_S0_, .Lfunc_end0-_Z3fooiP5CoordS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooiP5CoordS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3fooiP5CoordS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Passing array of a Class and assigning elements at odd/even elements to another array.
// @alpha74
#include "hip/hip_runtime.h"
#include <iostream>
#include "stdio.h"
using namespace std;
class Coord
{
int x;
int y;
public:
Coord()
{
x = 0;
y = 0;
}
void set(int a, int b)
{
x = a;
y = b;
}
void print()
{
printf(" (%d,%d) ", x, y);
}
};
__global__ void foo( int lim, Coord C[], Coord *oddi, Coord *eveni)
{
int tid = blockIdx.x;
if (tid < lim)
{
if (tid % 2 == 0)
{
eveni[tid / 2] = C[tid];
}
else
{
oddi[tid / 2] = C[tid];
}
}
}
int main()
{
const int N = 20;
// Declare an array of size N
Coord C[N];
Coord result_odd[ N/2], result_even[ N/2 ];
// Initialize the elements
for (int i = 0; i < N; i++)
{
if (i % 2 == 0)
{
C[i].set(2, 2);
}
else
C[i].set(-1, -1);
}
// Declare and allocate device memory
Coord *dev_C;
Coord *dev_odd, *dev_even;
hipMalloc((void**)&dev_C, N * sizeof(Coord));
hipMalloc((void**)&dev_odd, N / 2 * sizeof(Coord));
hipMalloc((void**)&dev_even, N / 2 * sizeof(Coord));
hipMemcpy(dev_C, C, N * sizeof(Coord), hipMemcpyHostToDevice);
hipMemcpy(dev_odd, C, N/2 * sizeof(Coord), hipMemcpyHostToDevice); // Adding part of the array for comparison.
hipMemcpy(dev_even, C, N / 2 * sizeof(Coord), hipMemcpyHostToDevice); // Adding part of the array for comparison.
foo <<<N, 1 >>> ( N, dev_C, dev_odd, dev_even );
// Copying back the results
hipMemcpy(&result_even, dev_even, N/2 * sizeof(Coord), hipMemcpyDeviceToHost);
hipMemcpy(&result_odd, dev_odd, N/2 * sizeof(Coord), hipMemcpyDeviceToHost);
cout << "\n At even pos: ";
for (int i = 0 ; i < N / 2; i++)
{
result_even[i].print();
}
cout << "\n At odd pos: ";
for (int i = 0; i < N / 2; i++)
{
result_odd[i].print();
}
cout << "\n ";
// Freeing device memory
hipFree(dev_C);
hipFree(dev_odd);
hipFree(dev_even);
return 0;
} | .text
.file "extract_odd_even.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__fooiP5CoordS0_S0_ # -- Begin function _Z18__device_stub__fooiP5CoordS0_S0_
.p2align 4, 0x90
.type _Z18__device_stub__fooiP5CoordS0_S0_,@function
_Z18__device_stub__fooiP5CoordS0_S0_: # @_Z18__device_stub__fooiP5CoordS0_S0_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3fooiP5CoordS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__fooiP5CoordS0_S0_, .Lfunc_end0-_Z18__device_stub__fooiP5CoordS0_S0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.preheader.preheader
pushq %rbx
.cfi_def_cfa_offset 16
subq $464, %rsp # imm = 0x1D0
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -16
xorps %xmm0, %xmm0
movaps %xmm0, 448(%rsp)
movaps %xmm0, 432(%rsp)
movaps %xmm0, 416(%rsp)
movaps %xmm0, 400(%rsp)
movaps %xmm0, 384(%rsp)
movaps %xmm0, 368(%rsp)
movaps %xmm0, 352(%rsp)
movaps %xmm0, 336(%rsp)
movaps %xmm0, 320(%rsp)
movaps %xmm0, 304(%rsp)
movaps %xmm0, 288(%rsp)
movaps %xmm0, 272(%rsp)
movaps %xmm0, 256(%rsp)
movaps %xmm0, 240(%rsp)
movaps %xmm0, 224(%rsp)
movaps %xmm0, 208(%rsp)
movaps %xmm0, 192(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, %ecx
andl $1, %ecx
negl %ecx
orl $2, %ecx
movl %ecx, 304(%rsp,%rax,8)
movl %ecx, 308(%rsp,%rax,8)
incq %rax
cmpq $20, %rax
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $160, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 304(%rsp), %rbx
movl $160, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 19(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $20, 36(%rsp)
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3fooiP5CoordS0_S0_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 144(%rsp), %rdi
movl $80, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
leaq 224(%rsp), %rdi
movl $80, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 144(%rsp,%rbx,8), %esi
movl 148(%rsp,%rbx,8), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 224(%rsp,%rbx,8), %esi
movl 228(%rsp,%rbx,8), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_7
# %bb.8:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $464, %rsp # imm = 0x1D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooiP5CoordS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooiP5CoordS0_S0_,@object # @_Z3fooiP5CoordS0_S0_
.section .rodata,"a",@progbits
.globl _Z3fooiP5CoordS0_S0_
.p2align 3, 0x0
_Z3fooiP5CoordS0_S0_:
.quad _Z18__device_stub__fooiP5CoordS0_S0_
.size _Z3fooiP5CoordS0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n At even pos: "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n At odd pos: "
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n "
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " (%d,%d) "
.size .L.str.3, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3fooiP5CoordS0_S0_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooiP5CoordS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooiP5CoordS0_S0_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3fooiP5CoordS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ee2000c1e1900 */
/*0090*/ LOP3.LUT R0, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104007812 */
/* 0x000fc800078ec0ff */
/*00a0*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f05070 */
/*00b0*/ LEA.HI R0, R4, R4, RZ, 0x1 ; /* 0x0000000404007211 */
/* 0x000fc800078f08ff */
/*00c0*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc80000011400 */
/*00d0*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fc60000011400 */
/*00e0*/ @!P0 LEA R4, P1, R0, c[0x0][0x170], 0x3 ; /* 0x00005c0000048a11 */
/* 0x000fc800078218ff */
/*00f0*/ @!P0 LEA.HI.X R5, R0, c[0x0][0x174], R11, 0x3, P1 ; /* 0x00005d0000058a11 */
/* 0x000fca00008f1c0b */
/*0100*/ @!P0 STG.E [R4.64], R7 ; /* 0x0000000704008986 */
/* 0x0041e8000c101904 */
/*0110*/ @!P0 STG.E [R4.64+0x4], R9 ; /* 0x0000040904008986 */
/* 0x0081e2000c101904 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0130*/ LEA R2, P0, R0, c[0x0][0x178], 0x3 ; /* 0x00005e0000027a11 */
/* 0x000fc800078018ff */
/*0140*/ LEA.HI.X R3, R0, c[0x0][0x17c], R11, 0x3, P0 ; /* 0x00005f0000037a11 */
/* 0x000fca00000f1c0b */
/*0150*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0160*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooiP5CoordS0_S0_
.globl _Z3fooiP5CoordS0_S0_
.p2align 8
.type _Z3fooiP5CoordS0_S0_,@function
_Z3fooiP5CoordS0_S0_:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x8
s_bitcmp1_b32 s15, 0
s_mov_b32 s2, s15
s_cselect_b32 s8, -1, 0
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[2:3], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_and_b32 vcc_lo, exec_lo, s8
s_load_b64 s[4:5], s[4:5], 0x0
s_cbranch_vccz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x10
s_lshr_b32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s2, s3
s_ashr_i32 s8, s3, 1
s_cbranch_execz .LBB0_4
s_branch .LBB0_5
.LBB0_3:
.LBB0_4:
s_waitcnt lgkmcnt(0)
s_load_b64 s[6:7], s[0:1], 0x18
s_ashr_i32 s8, s2, 1
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s4
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s5
s_lshl_b64 s[0:1], s[8:9], 3
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooiP5CoordS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooiP5CoordS0_S0_, .Lfunc_end0-_Z3fooiP5CoordS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooiP5CoordS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3fooiP5CoordS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001943c1_00000000-6_extract_odd_even.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_
.type _Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_, @function
_Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3fooiP5CoordS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_, .-_Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_
.globl _Z3fooiP5CoordS0_S0_
.type _Z3fooiP5CoordS0_S0_, @function
_Z3fooiP5CoordS0_S0_:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z3fooiP5CoordS0_S0_, .-_Z3fooiP5CoordS0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n At even pos: "
.LC1:
.string " (%d,%d) "
.LC2:
.string "\n At odd pos: "
.LC3:
.string "\n "
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $384, %rsp
.cfi_def_cfa_offset 432
movq %fs:40, %rax
movq %rax, 376(%rsp)
xorl %eax, %eax
leaq 208(%rsp), %rdx
leaq 368(%rsp), %rcx
movq %rdx, %rax
.L12:
movl $0, (%rax)
movl $0, 4(%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L12
leaq 48(%rsp), %rbx
leaq 128(%rsp), %r12
movq %rbx, %rax
.L13:
movl $0, (%rax)
movl $0, 4(%rax)
addq $8, %rax
cmpq %r12, %rax
jne .L13
leaq 128(%rsp), %rbp
leaq 208(%rsp), %r13
movq %rbp, %rax
.L14:
movl $0, (%rax)
movl $0, 4(%rax)
addq $8, %rax
cmpq %r13, %rax
jne .L14
movl $0, %ecx
.L16:
movl %ecx, %eax
andl $1, %eax
negl %eax
sbbl %eax, %eax
orl $2, %eax
movl %eax, (%rdx)
movl %eax, 4(%rdx)
addl $1, %ecx
addq $8, %rdx
cmpl $20, %ecx
jne .L16
movq %rsp, %rdi
movl $160, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 208(%rsp), %r14
movl $1, %ecx
movl $160, %edx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $20, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L17:
leaq 128(%rsp), %rdi
movl $2, %ecx
movl $80, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $80, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC1(%rip), %r14
.L18:
movl 4(%rbp), %ecx
movl 0(%rbp), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbp
cmpq %r13, %rbp
jne .L18
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC1(%rip), %rbp
.L19:
movl 4(%rbx), %ecx
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L19
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 376(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $20, %edi
call _Z34__device_stub__Z3fooiP5CoordS0_S0_iP5CoordS0_S0_
jmp .L17
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3fooiP5CoordS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooiP5CoordS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "extract_odd_even.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__fooiP5CoordS0_S0_ # -- Begin function _Z18__device_stub__fooiP5CoordS0_S0_
.p2align 4, 0x90
.type _Z18__device_stub__fooiP5CoordS0_S0_,@function
_Z18__device_stub__fooiP5CoordS0_S0_: # @_Z18__device_stub__fooiP5CoordS0_S0_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3fooiP5CoordS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__fooiP5CoordS0_S0_, .Lfunc_end0-_Z18__device_stub__fooiP5CoordS0_S0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.preheader.preheader
pushq %rbx
.cfi_def_cfa_offset 16
subq $464, %rsp # imm = 0x1D0
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -16
xorps %xmm0, %xmm0
movaps %xmm0, 448(%rsp)
movaps %xmm0, 432(%rsp)
movaps %xmm0, 416(%rsp)
movaps %xmm0, 400(%rsp)
movaps %xmm0, 384(%rsp)
movaps %xmm0, 368(%rsp)
movaps %xmm0, 352(%rsp)
movaps %xmm0, 336(%rsp)
movaps %xmm0, 320(%rsp)
movaps %xmm0, 304(%rsp)
movaps %xmm0, 288(%rsp)
movaps %xmm0, 272(%rsp)
movaps %xmm0, 256(%rsp)
movaps %xmm0, 240(%rsp)
movaps %xmm0, 224(%rsp)
movaps %xmm0, 208(%rsp)
movaps %xmm0, 192(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %eax, %ecx
andl $1, %ecx
negl %ecx
orl $2, %ecx
movl %ecx, 304(%rsp,%rax,8)
movl %ecx, 308(%rsp,%rax,8)
incq %rax
cmpq $20, %rax
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $160, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 304(%rsp), %rbx
movl $160, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 19(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $20, 36(%rsp)
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3fooiP5CoordS0_S0_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 144(%rsp), %rdi
movl $80, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
leaq 224(%rsp), %rdi
movl $80, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 144(%rsp,%rbx,8), %esi
movl 148(%rsp,%rbx,8), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 224(%rsp,%rbx,8), %esi
movl 228(%rsp,%rbx,8), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_7
# %bb.8:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $464, %rsp # imm = 0x1D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooiP5CoordS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooiP5CoordS0_S0_,@object # @_Z3fooiP5CoordS0_S0_
.section .rodata,"a",@progbits
.globl _Z3fooiP5CoordS0_S0_
.p2align 3, 0x0
_Z3fooiP5CoordS0_S0_:
.quad _Z18__device_stub__fooiP5CoordS0_S0_
.size _Z3fooiP5CoordS0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n At even pos: "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n At odd pos: "
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n "
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " (%d,%d) "
.size .L.str.3, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3fooiP5CoordS0_S0_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooiP5CoordS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooiP5CoordS0_S0_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void lif_update_membrane_potentials(float *d_membrane_potentials_v, float * d_membrane_resistances_R, float * d_membrane_time_constants_tau_m, float * d_resting_potentials, float* d_current_injections, float timestep, size_t total_number_of_neurons){
// // Get thread IDs
int idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < total_number_of_neurons) {
float equation_constant = timestep / d_membrane_time_constants_tau_m[idx];
float membrane_potential_Vi = d_membrane_potentials_v[idx];
float current_injection_Ii = d_current_injections[idx];
float resting_potential_V0 = d_resting_potentials[idx];
float temp_membrane_resistance_R = d_membrane_resistances_R[idx];
float new_membrane_potential = equation_constant * (resting_potential_V0 + temp_membrane_resistance_R * current_injection_Ii) + (1 - equation_constant) * membrane_potential_Vi;
d_membrane_potentials_v[idx] = new_membrane_potential;
idx += blockDim.x * gridDim.x;
}
__syncthreads();
} | code for sm_80
Function : _Z30lif_update_membrane_potentialsPfS_S_S_S_fm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0x390 ; /* 0x0000036000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x190], PT ; /* 0x0000640000007a0c */
/* 0x000fe40003f06070 */
/*0060*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x194], PT, P0 ; /* 0x0000650002007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @P0 BRA 0x380 ; /* 0x000002f000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0000 */
/*00b0*/ IMAD.SHL.U32 R3, R2.reuse, 0x4, RZ ; /* 0x0000000402037824 */
/* 0x040fe200078e00ff */
/*00c0*/ SHF.L.U64.HI R2, R2, 0x2, R7 ; /* 0x0000000202027819 */
/* 0x000fe20000010207 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IADD3 R4, P0, R3, c[0x0][0x170], RZ ; /* 0x00005c0003047a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R5, R2, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0002057a10 */
/* 0x000fca00007fe4ff */
/*0100*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0110*/ ULDC UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x000fe20000000800 */
/*0120*/ BSSY B1, 0x1f0 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*0130*/ IMAD.U32 R10, RZ, RZ, UR4 ; /* 0x00000004ff0a7e24 */
/* 0x000fe2000f8e00ff */
/*0140*/ MUFU.RCP R6, R11 ; /* 0x0000000b00067308 */
/* 0x004e300000001000 */
/*0150*/ FCHK P0, R10, R11 ; /* 0x0000000b0a007302 */
/* 0x000e620000000000 */
/*0160*/ FFMA R7, -R11, R6, 1 ; /* 0x3f8000000b077423 */
/* 0x001fc80000000106 */
/*0170*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*0180*/ FFMA R6, R7, c[0x0][0x188], RZ ; /* 0x0000620007067a23 */
/* 0x000fc800000000ff */
/*0190*/ FFMA R8, -R11, R6, c[0x0][0x188] ; /* 0x000062000b087623 */
/* 0x000fc80000000106 */
/*01a0*/ FFMA R12, R7, R8, R6 ; /* 0x00000008070c7223 */
/* 0x000fe20000000006 */
/*01b0*/ @!P0 BRA 0x1e0 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*01c0*/ MOV R4, 0x1e0 ; /* 0x000001e000047802 */
/* 0x000fe40000000f00 */
/*01d0*/ CALL.REL.NOINC 0x3b0 ; /* 0x000001d000007944 */
/* 0x000fea0003c00000 */
/*01e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R8, P1, R3.reuse, c[0x0][0x180], RZ ; /* 0x0000600003087a10 */
/* 0x040fe20007f3e0ff */
/*0200*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0210*/ IADD3 R6, P0, R3.reuse, c[0x0][0x168], RZ ; /* 0x00005a0003067a10 */
/* 0x040fe40007f1e0ff */
/*0220*/ IADD3 R10, P2, R3, c[0x0][0x178], RZ ; /* 0x00005e00030a7a10 */
/* 0x000fe40007f5e0ff */
/*0230*/ IADD3.X R9, R2.reuse, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610002097a10 */
/* 0x040fe40000ffe4ff */
/*0240*/ IADD3.X R7, R2.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0002077a10 */
/* 0x040fe400007fe4ff */
/*0250*/ IADD3.X R11, R2, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f00020b7a10 */
/* 0x000fc400017fe4ff */
/*0260*/ IADD3 R4, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fe20007f1e0ff */
/*0270*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0290*/ IADD3.X R5, R2, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590002057a10 */
/* 0x000fc600007fe4ff */
/*02a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ee2000c1e1900 */
/*02c0*/ FADD R2, -R12, 1 ; /* 0x3f8000000c027421 */
/* 0x000fe40000000100 */
/*02d0*/ FFMA R3, R6, R9, R10 ; /* 0x0000000906037223 */
/* 0x004fc8000000000a */
/*02e0*/ FMUL R3, R3, R12 ; /* 0x0000000c03037220 */
/* 0x000fc80000400000 */
/*02f0*/ FFMA R3, R2, R13, R3 ; /* 0x0000000d02037223 */
/* 0x008fe40000000003 */
/*0300*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fc600078e00ff */
/*0310*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001e2000c101904 */
/*0320*/ IMAD R2, R13, c[0x0][0xc], R0 ; /* 0x000003000d027a24 */
/* 0x000fc800078e0200 */
/*0330*/ IMAD.MOV.U32 R0, RZ, RZ, R2.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0002 */
/*0340*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fe40003f06070 */
/*0350*/ SHF.R.S32.HI R7, RZ, 0x1f, R2 ; /* 0x0000001fff077819 */
/* 0x000fc80000011402 */
/*0360*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x194], PT, P0 ; /* 0x0000650007007a0c */
/* 0x000fda0003f06100 */
/*0370*/ @!P0 BRA 0xb0 ; /* 0xfffffd3000008947 */
/* 0x001fea000383ffff */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ SHF.R.U32.HI R5, RZ, 0x17, R11.reuse ; /* 0x00000017ff057819 */
/* 0x100fe2000001160b */
/*03c0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0c7624 */
/* 0x000fe200078e00ff */
/*03d0*/ BSSY B2, 0xa30 ; /* 0x0000065000027945 */
/* 0x000fe20003800000 */
/*03e0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff077624 */
/* 0x000fe200078e00ff */
/*03f0*/ LOP3.LUT R13, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050d7812 */
/* 0x000fe200078ec0ff */
/*0400*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000b */
/*0410*/ SHF.R.U32.HI R5, RZ, 0x17, R12 ; /* 0x00000017ff057819 */
/* 0x000fc4000001160c */
/*0420*/ IADD3 R14, R13, -0x1, RZ ; /* 0xffffffff0d0e7810 */
/* 0x000fe40007ffe0ff */
/*0430*/ LOP3.LUT R6, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05067812 */
/* 0x000fe400078ec0ff */
/*0440*/ ISETP.GT.U32.AND P0, PT, R14, 0xfd, PT ; /* 0x000000fd0e00780c */
/* 0x000fe40003f04070 */
/*0450*/ IADD3 R10, R6, -0x1, RZ ; /* 0xffffffff060a7810 */
/* 0x000fc80007ffe0ff */
/*0460*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0470*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0480*/ @!P0 BRA 0x610 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0490*/ FSETP.GTU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe20003f1c200 */
/*04a0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*04b0*/ FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fc80003f3c200 */
/*04c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*04d0*/ @P0 BRA 0xa10 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*04e0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*04f0*/ @!P0 BRA 0x9f0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0500*/ FSETP.NEU.FTZ.AND P2, PT, |R12|.reuse, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x040fe40003f5d200 */
/*0510*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0520*/ FSETP.NEU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fd60003f1d200 */
/*0530*/ @!P1 BRA !P2, 0x9f0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0540*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0550*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0560*/ @P1 BRA 0x9d0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0570*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0580*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0590*/ @P0 BRA 0x9a0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*05b0*/ ISETP.GE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fd60003f26270 */
/*05c0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*05d0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*05e0*/ @!P0 FFMA R7, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c078823 */
/* 0x000fe400000000ff */
/*05f0*/ @!P1 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005089823 */
/* 0x000fe200000000ff */
/*0600*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0610*/ LEA R5, R13, 0xc0800000, 0x17 ; /* 0xc08000000d057811 */
/* 0x000fe200078eb8ff */
/*0620*/ BSSY B3, 0x990 ; /* 0x0000036000037945 */
/* 0x000fe20003800000 */
/*0630*/ IADD3 R6, R6, -0x7f, RZ ; /* 0xffffff8106067810 */
/* 0x000fc60007ffe0ff */
/*0640*/ IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108087824 */
/* 0x000fe400078e0a05 */
/*0650*/ IMAD R7, R6, -0x800000, R7 ; /* 0xff80000006077824 */
/* 0x000fe400078e0207 */
/*0660*/ MUFU.RCP R5, R8 ; /* 0x0000000800057308 */
/* 0x0000620000001000 */
/*0670*/ FADD.FTZ R10, -R8, -RZ ; /* 0x800000ff080a7221 */
/* 0x000fe20000010100 */
/*0680*/ IADD3 R8, R6, 0x7f, -R13 ; /* 0x0000007f06087810 */
/* 0x001fca0007ffe80d */
/*0690*/ IMAD.IADD R8, R8, 0x1, R9 ; /* 0x0000000108087824 */
/* 0x000fe400078e0209 */
/*06a0*/ FFMA R12, R5, R10, 1 ; /* 0x3f800000050c7423 */
/* 0x002fc8000000000a */
/*06b0*/ FFMA R14, R5, R12, R5 ; /* 0x0000000c050e7223 */
/* 0x000fc80000000005 */
/*06c0*/ FFMA R5, R7, R14, RZ ; /* 0x0000000e07057223 */
/* 0x000fc800000000ff */
/*06d0*/ FFMA R12, R10, R5, R7 ; /* 0x000000050a0c7223 */
/* 0x000fc80000000007 */
/*06e0*/ FFMA R11, R14, R12, R5 ; /* 0x0000000c0e0b7223 */
/* 0x000fc80000000005 */
/*06f0*/ FFMA R7, R10, R11, R7 ; /* 0x0000000b0a077223 */
/* 0x000fc80000000007 */
/*0700*/ FFMA R5, R14, R7, R11 ; /* 0x000000070e057223 */
/* 0x000fca000000000b */
/*0710*/ SHF.R.U32.HI R6, RZ, 0x17, R5 ; /* 0x00000017ff067819 */
/* 0x000fc80000011605 */
/*0720*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fca00078ec0ff */
/*0730*/ IMAD.IADD R10, R6, 0x1, R8 ; /* 0x00000001060a7824 */
/* 0x000fca00078e0208 */
/*0740*/ IADD3 R6, R10, -0x1, RZ ; /* 0xffffffff0a067810 */
/* 0x000fc80007ffe0ff */
/*0750*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*0760*/ @!P0 BRA 0x970 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0780*/ @P0 BRA 0x940 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0790*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*07a0*/ @P0 BRA 0x980 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*07b0*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*07c0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*07d0*/ @!P0 BRA 0x980 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*07e0*/ FFMA.RZ R6, R14, R7.reuse, R11.reuse ; /* 0x000000070e067223 */
/* 0x180fe2000000c00b */
/*07f0*/ IADD3 R9, R10.reuse, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x040fe40007ffe0ff */
/*0800*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*0810*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*0820*/ FFMA.RP R6, R14, R7.reuse, R11.reuse ; /* 0x000000070e067223 */
/* 0x180fe2000000800b */
/*0830*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0840*/ FFMA.RM R7, R14, R7, R11 ; /* 0x000000070e077223 */
/* 0x000fe2000000400b */
/*0850*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe200078efcff */
/*0860*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0a0a */
/*0870*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0880*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fe40003f1d000 */
/*0890*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*08a0*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*08b0*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*08c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*08d0*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fe40000011607 */
/*08e0*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*08f0*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0900*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0910*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*0920*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe200078efcff */
/*0930*/ BRA 0x980 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*0950*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0960*/ BRA 0x980 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0970*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe400078e0205 */
/*0980*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0990*/ BRA 0xa20 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*09a0*/ LOP3.LUT R5, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fc800078e4807 */
/*09b0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*09c0*/ BRA 0xa20 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*09d0*/ LOP3.LUT R5, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fe200078e4807 */
/*09e0*/ BRA 0xa20 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*09f0*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0a00*/ BRA 0xa20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a10*/ FADD.FTZ R5, R5, c[0x0][0x188] ; /* 0x0000620005057621 */
/* 0x000fe40000010000 */
/*0a20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a30*/ IMAD.MOV.U32 R12, RZ, RZ, R5 ; /* 0x000000ffff0c7224 */
/* 0x001fe400078e0005 */
/*0a40*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0a50*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff5a004007950 */
/* 0x000fea0003c3ffff */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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