system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float tanh_(float x)
{
// e**2x - 1
// ---------
// e**2x + 1
float exp2x = exp(2.0*x);
return (exp2x - 1.0)/(exp2x + 1.0);
}
__global__ void LSTM1(float* layer1, float* lstm1, const float* gate1i, const float* gate1o, const int offset)
{
int i = blockDim.x*blockIdx.x + threadIdx.x; //256
float g_i = gate1i[256*offset + i];
float g_f = 1.0 - g_i;
float g_o = gate1o[256*offset + i];
float i_t = tanh_(layer1[256*offset + i]) * g_i;
float i_p = 0.0;
if (offset > 0)
i_p = g_f * lstm1[256*(offset-1) + i];
float sum = i_p + i_t;
lstm1[256*offset + i] = sum;
layer1[256*offset + i] = tanh_(sum) * g_o;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5LSTM1PfS_PKfS1_i
.globl _Z5LSTM1PfS_PKfS1_i
.p2align 8
.type _Z5LSTM1PfS_PKfS1_i,@function
_Z5LSTM1PfS_PKfS1_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s9, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_lshl_b32 s8, s9, 8
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_load_b256 s[0:7], s[0:1], 0x0
s_cmp_lt_i32 s9, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s8, v4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v6, v[5:6], off
global_load_b32 v5, v[7:8], off
global_load_b32 v7, v[2:3], off
s_cbranch_scc1 .LBB0_2
v_add3_u32 v8, v4, s8, 0xffffff00
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v4, v[8:9], off
s_waitcnt vmcnt(3)
v_sub_f32_e32 v8, 1.0, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v4, v8, v4
s_branch .LBB0_3
.LBB0_2:
v_mov_b32_e32 v4, 0
.LBB0_3:
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[7:8], v7
s_mov_b32 s5, 0x3ff71547
s_mov_b32 s4, 0x652b82fe
s_mov_b32 s7, 0xbfe62e42
s_mov_b32 s6, 0xfefa39ef
s_mov_b32 s9, 0xbc7abc9e
s_mov_b32 s8, 0x3b39803f
s_mov_b32 s11, 0x3e928af3
s_mov_b32 s10, 0xfca7ab0c
s_mov_b32 s13, 0x3e5ade15
s_mov_b32 s12, 0x6a5dcb37
s_mov_b32 s15, 0x3ec71dee
s_mov_b32 s14, 0x623fde64
s_mov_b32 s17, 0x3efa0199
s_mov_b32 s16, 0x7c89e6b0
s_mov_b32 s19, 0x3f2a01a0
s_mov_b32 s18, 0x14761f6e
s_mov_b32 s21, 0x3f56c16c
s_mov_b32 s20, 0x1852b7b0
s_mov_b32 s23, 0x3f811111
s_mov_b32 s22, 0x11122322
s_mov_b32 s25, 0x3fa55555
s_mov_b32 s24, 0x555502a1
s_mov_b32 s27, 0x3fc55555
s_mov_b32 s26, 0x55555511
s_mov_b32 s29, 0x3fe00000
s_mov_b32 s28, 11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], v[7:8]
v_mul_f64 v[9:10], v[7:8], s[4:5]
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[7:8]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[9:10], v[9:10]
v_fma_f64 v[11:12], v[9:10], s[6:7], v[7:8]
v_cvt_i32_f64_e32 v15, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[9:10], s[8:9], v[11:12]
v_fma_f64 v[13:14], v[11:12], s[12:13], s[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[14:15]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[18:19]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[22:23]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[26:27]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], 1.0
v_fma_f64 v[9:10], v[11:12], v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[9:10], v[9:10], v15
v_cndmask_b32_e32 v10, 0x7ff00000, v10, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, 0, v9, vcc_lo
v_cndmask_b32_e64 v8, 0, v10, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v7, v[7:8]
v_cvt_f64_f32_e32 v[7:8], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[9:10], v[7:8], -1.0
v_add_f64 v[7:8], v[7:8], 1.0
v_div_scale_f64 v[11:12], null, v[7:8], v[7:8], v[9:10]
v_div_scale_f64 v[17:18], vcc_lo, v[9:10], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[17:18], v[13:14]
v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
v_div_fixup_f64 v[7:8], v[11:12], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v7, v[7:8]
v_fmac_f32_e32 v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[6:7], v4
v_add_f64 v[6:7], v[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f64 v[8:9], v[6:7], s[4:5]
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[6:7]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[6:7]
v_rndne_f64_e32 v[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[8:9], s[6:7], v[6:7]
v_cvt_i32_f64_e32 v14, v[8:9]
v_fma_f64 v[10:11], v[8:9], s[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[10:11], s[12:13], s[10:11]
v_fma_f64 v[12:13], v[10:11], v[12:13], s[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[16:17]
v_fma_f64 v[12:13], v[10:11], v[12:13], s[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[20:21]
v_fma_f64 v[12:13], v[10:11], v[12:13], s[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[24:25]
v_fma_f64 v[12:13], v[10:11], v[12:13], s[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[28:29]
v_fma_f64 v[12:13], v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[12:13], 1.0
v_ldexp_f64 v[8:9], v[8:9], v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v9, 0x7ff00000, v9, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
v_cndmask_b32_e32 v6, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, 0, v9, s0
v_cvt_f32_f64_e32 v6, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[6:7], v6
v_add_f64 v[8:9], v[6:7], -1.0
v_add_f64 v[6:7], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[8:9]
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_div_scale_f64 v[14:15], vcc_lo, v[8:9], v[6:7], v[8:9]
v_mul_f64 v[16:17], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[6:7], v[10:11], v[6:7], v[8:9]
v_cvt_f32_f64_e32 v6, v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v5, v5, v6
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5LSTM1PfS_PKfS1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 30
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5LSTM1PfS_PKfS1_i, .Lfunc_end0-_Z5LSTM1PfS_PKfS1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5LSTM1PfS_PKfS1_i
.private_segment_fixed_size: 0
.sgpr_count: 32
.sgpr_spill_count: 0
.symbol: _Z5LSTM1PfS_PKfS1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float tanh_(float x)
{
// e**2x - 1
// ---------
// e**2x + 1
float exp2x = exp(2.0*x);
return (exp2x - 1.0)/(exp2x + 1.0);
}
__global__ void LSTM1(float* layer1, float* lstm1, const float* gate1i, const float* gate1o, const int offset)
{
int i = blockDim.x*blockIdx.x + threadIdx.x; //256
float g_i = gate1i[256*offset + i];
float g_f = 1.0 - g_i;
float g_o = gate1o[256*offset + i];
float i_t = tanh_(layer1[256*offset + i]) * g_i;
float i_p = 0.0;
if (offset > 0)
i_p = g_f * lstm1[256*(offset-1) + i];
float sum = i_p + i_t;
lstm1[256*offset + i] = sum;
layer1[256*offset + i] = tanh_(sum) * g_o;
} | .text
.file "LSTM1.hip"
.globl _Z20__device_stub__LSTM1PfS_PKfS1_i # -- Begin function _Z20__device_stub__LSTM1PfS_PKfS1_i
.p2align 4, 0x90
.type _Z20__device_stub__LSTM1PfS_PKfS1_i,@function
_Z20__device_stub__LSTM1PfS_PKfS1_i: # @_Z20__device_stub__LSTM1PfS_PKfS1_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5LSTM1PfS_PKfS1_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z20__device_stub__LSTM1PfS_PKfS1_i, .Lfunc_end0-_Z20__device_stub__LSTM1PfS_PKfS1_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5LSTM1PfS_PKfS1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5LSTM1PfS_PKfS1_i,@object # @_Z5LSTM1PfS_PKfS1_i
.section .rodata,"a",@progbits
.globl _Z5LSTM1PfS_PKfS1_i
.p2align 3, 0x0
_Z5LSTM1PfS_PKfS1_i:
.quad _Z20__device_stub__LSTM1PfS_PKfS1_i
.size _Z5LSTM1PfS_PKfS1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5LSTM1PfS_PKfS1_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__LSTM1PfS_PKfS1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5LSTM1PfS_PKfS1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011da24_00000000-6_LSTM1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5tanh_f
.type _Z5tanh_f, @function
_Z5tanh_f:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z5tanh_f, .-_Z5tanh_f
.globl _Z33__device_stub__Z5LSTM1PfS_PKfS1_iPfS_PKfS1_i
.type _Z33__device_stub__Z5LSTM1PfS_PKfS1_iPfS_PKfS1_i, @function
_Z33__device_stub__Z5LSTM1PfS_PKfS1_iPfS_PKfS1_i:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5LSTM1PfS_PKfS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z33__device_stub__Z5LSTM1PfS_PKfS1_iPfS_PKfS1_i, .-_Z33__device_stub__Z5LSTM1PfS_PKfS1_iPfS_PKfS1_i
.globl _Z5LSTM1PfS_PKfS1_i
.type _Z5LSTM1PfS_PKfS1_i, @function
_Z5LSTM1PfS_PKfS1_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z5LSTM1PfS_PKfS1_iPfS_PKfS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z5LSTM1PfS_PKfS1_i, .-_Z5LSTM1PfS_PKfS1_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5LSTM1PfS_PKfS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5LSTM1PfS_PKfS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "LSTM1.hip"
.globl _Z20__device_stub__LSTM1PfS_PKfS1_i # -- Begin function _Z20__device_stub__LSTM1PfS_PKfS1_i
.p2align 4, 0x90
.type _Z20__device_stub__LSTM1PfS_PKfS1_i,@function
_Z20__device_stub__LSTM1PfS_PKfS1_i: # @_Z20__device_stub__LSTM1PfS_PKfS1_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5LSTM1PfS_PKfS1_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z20__device_stub__LSTM1PfS_PKfS1_i, .Lfunc_end0-_Z20__device_stub__LSTM1PfS_PKfS1_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5LSTM1PfS_PKfS1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5LSTM1PfS_PKfS1_i,@object # @_Z5LSTM1PfS_PKfS1_i
.section .rodata,"a",@progbits
.globl _Z5LSTM1PfS_PKfS1_i
.p2align 3, 0x0
_Z5LSTM1PfS_PKfS1_i:
.quad _Z20__device_stub__LSTM1PfS_PKfS1_i
.size _Z5LSTM1PfS_PKfS1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5LSTM1PfS_PKfS1_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__LSTM1PfS_PKfS1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5LSTM1PfS_PKfS1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void kernel(double* d_array, double* d_sum){
// int i = (blockIdx.x*blockDim.x) + threadIdx.x;
// int x = i % 2560;
// int y = i % 2560;
for (int i = threadIdx.x + blockIdx.x * blockDim.x; i < 2560*2560; i += blockDim.x*gridDim.x){
d_array[i] = i+0.1;
printf("d_array[%d] = %.2f\n", i ,d_array[i] );
*d_sum += d_array[i];
}
}
int main(int argc, char** argv){
int N = 2560*2560;
double* array = (double*) calloc(N,sizeof(double));
double sum = 2.03;
double* d_array, *d_sum;
size_t size = N*sizeof(double);
cudaMalloc((void**) &d_array, size);
cudaMalloc((void**) &d_sum, sizeof(double));
cudaMemcpy(d_array,array,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_sum, &sum, sizeof(double), cudaMemcpyHostToDevice);
for (int k = 0; k < 100000; k++){
kernel<<<1,1024>>>(d_array,d_sum);
cudaMemcpy(array, d_array, size, cudaMemcpyDeviceToHost);
cudaMemcpy(&sum, d_sum, sizeof(double), cudaMemcpyDeviceToHost);
// for (int i=0; i<N; i++){
// printf("array[%d] = %.2f\n",i, array[i] );
// }
printf("sum = %.2f\n", sum );
}
cudaFree(d_array);
cudaFree(d_sum);
return 0;
} | code for sm_80
Function : _Z6kernelPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R18, SR_CTAID.X ; /* 0x0000000000127919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R18, R18, c[0x0][0x0], R3 ; /* 0x0000000012127a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GT.AND P0, PT, R18, 0x63ffff, PT ; /* 0x0063ffff1200780c */
/* 0x000fda0003f04270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001027a10 */
/* 0x000fe20007f1e0ff */
/*0080*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fc80000000a00 */
/*0090*/ IMAD.X R19, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff137624 */
/* 0x000fe400000e06ff */
/*00a0*/ I2F.F64 R10, R18 ; /* 0x00000012000a7312 */
/* 0x0010620000201c00 */
/*00b0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; /* 0x00000008ff117424 */
/* 0x000fe200078e00ff */
/*00c0*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x000fe200078e00ff */
/*00e0*/ STL [R1], R18 ; /* 0x0000001201007387 */
/* 0x0001e20000100800 */
/*00f0*/ IMAD.WIDE R16, R18, R17, c[0x0][0x160] ; /* 0x0000580012107625 */
/* 0x000fc600078e0211 */
/*0100*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000ea20000000a00 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*0140*/ IMAD R18, R3, c[0x0][0xc], R18 ; /* 0x0000030003127a24 */
/* 0x001fe200078e0212 */
/*0150*/ DADD R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7629 */
/* 0x002e220000000000 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0013 */
/*0170*/ ISETP.GE.AND P0, PT, R18, 0x640000, PT ; /* 0x006400001200780c */
/* 0x000fc60003f06270 */
/*0180*/ STG.E.64 [R16.64], R10 ; /* 0x0000000a10007986 */
/* 0x0011e2000c101b24 */
/*0190*/ P2R R22, PR, RZ, 0x1 ; /* 0x00000001ff167803 */
/* 0x000fc60000000000 */
/*01a0*/ STL.64 [R1+0x8], R10 ; /* 0x0000080a01007387 */
/* 0x0001e80000100a00 */
/*01b0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x001fe40000000000 */
/*01c0*/ MOV R3, 0x230 ; /* 0x0000023000037802 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R20, 0x1b0 ; /* 0x000001b000147802 */
/* 0x000fe40000000f00 */
/*01e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0200*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0210*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0220*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x004fea0003c00000 */
/*0230*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0240*/ LDG.E.64 R16, [R16.64] ; /* 0x0000002410107981 */
/* 0x000ea2000c1e1b00 */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0260*/ ISETP.NE.AND P6, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc80003fc5270 */
/*0270*/ LDG.E.64 R6, [R4.64] ; /* 0x0000002404067981 */
/* 0x000ea4000c1e1b00 */
/*0280*/ DADD R6, R6, R16 ; /* 0x0000000006067229 */
/* 0x004e0e0000000010 */
/*0290*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0011e2000c101b24 */
/*02a0*/ @!P6 BRA 0xa0 ; /* 0xfffffdf00000e947 */
/* 0x000fea000383ffff */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void kernel(double* d_array, double* d_sum){
// int i = (blockIdx.x*blockDim.x) + threadIdx.x;
// int x = i % 2560;
// int y = i % 2560;
for (int i = threadIdx.x + blockIdx.x * blockDim.x; i < 2560*2560; i += blockDim.x*gridDim.x){
d_array[i] = i+0.1;
printf("d_array[%d] = %.2f\n", i ,d_array[i] );
*d_sum += d_array[i];
}
}
int main(int argc, char** argv){
int N = 2560*2560;
double* array = (double*) calloc(N,sizeof(double));
double sum = 2.03;
double* d_array, *d_sum;
size_t size = N*sizeof(double);
cudaMalloc((void**) &d_array, size);
cudaMalloc((void**) &d_sum, sizeof(double));
cudaMemcpy(d_array,array,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_sum, &sum, sizeof(double), cudaMemcpyHostToDevice);
for (int k = 0; k < 100000; k++){
kernel<<<1,1024>>>(d_array,d_sum);
cudaMemcpy(array, d_array, size, cudaMemcpyDeviceToHost);
cudaMemcpy(&sum, d_sum, sizeof(double), cudaMemcpyDeviceToHost);
// for (int i=0; i<N; i++){
// printf("array[%d] = %.2f\n",i, array[i] );
// }
printf("sum = %.2f\n", sum );
}
cudaFree(d_array);
cudaFree(d_sum);
return 0;
} | .file "tmpxft_00117c63_00000000-6_copy_array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPdS_PdS_
.type _Z27__device_stub__Z6kernelPdS_PdS_, @function
_Z27__device_stub__Z6kernelPdS_PdS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6kernelPdS_PdS_, .-_Z27__device_stub__Z6kernelPdS_PdS_
.globl _Z6kernelPdS_
.type _Z6kernelPdS_, @function
_Z6kernelPdS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPdS_, .-_Z6kernelPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "sum = %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $8, %esi
movl $6553600, %edi
call calloc@PLT
movq %rax, %rbp
movq .LC0(%rip), %rax
movq %rax, 8(%rsp)
leaq 16(%rsp), %rdi
movl $52428800, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $52428800, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $100000, %ebx
leaq .LC1(%rip), %r12
jmp .L13
.L12:
movl $2, %ecx
movl $52428800, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movsd 8(%rsp), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
subl $1, %ebx
je .L17
.L13:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6kernelPdS_PdS_
jmp .L12
.L17:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1546188227
.long 1073757552
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void kernel(double* d_array, double* d_sum){
// int i = (blockIdx.x*blockDim.x) + threadIdx.x;
// int x = i % 2560;
// int y = i % 2560;
for (int i = threadIdx.x + blockIdx.x * blockDim.x; i < 2560*2560; i += blockDim.x*gridDim.x){
d_array[i] = i+0.1;
printf("d_array[%d] = %.2f\n", i ,d_array[i] );
*d_sum += d_array[i];
}
}
int main(int argc, char** argv){
int N = 2560*2560;
double* array = (double*) calloc(N,sizeof(double));
double sum = 2.03;
double* d_array, *d_sum;
size_t size = N*sizeof(double);
cudaMalloc((void**) &d_array, size);
cudaMalloc((void**) &d_sum, sizeof(double));
cudaMemcpy(d_array,array,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_sum, &sum, sizeof(double), cudaMemcpyHostToDevice);
for (int k = 0; k < 100000; k++){
kernel<<<1,1024>>>(d_array,d_sum);
cudaMemcpy(array, d_array, size, cudaMemcpyDeviceToHost);
cudaMemcpy(&sum, d_sum, sizeof(double), cudaMemcpyDeviceToHost);
// for (int i=0; i<N; i++){
// printf("array[%d] = %.2f\n",i, array[i] );
// }
printf("sum = %.2f\n", sum );
}
cudaFree(d_array);
cudaFree(d_sum);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void kernel(double* d_array, double* d_sum){
// int i = (blockIdx.x*blockDim.x) + threadIdx.x;
// int x = i % 2560;
// int y = i % 2560;
for (int i = threadIdx.x + blockIdx.x * blockDim.x; i < 2560*2560; i += blockDim.x*gridDim.x){
d_array[i] = i+0.1;
printf("d_array[%d] = %.2f\n", i ,d_array[i] );
*d_sum += d_array[i];
}
}
int main(int argc, char** argv){
int N = 2560*2560;
double* array = (double*) calloc(N,sizeof(double));
double sum = 2.03;
double* d_array, *d_sum;
size_t size = N*sizeof(double);
hipMalloc((void**) &d_array, size);
hipMalloc((void**) &d_sum, sizeof(double));
hipMemcpy(d_array,array,size,hipMemcpyHostToDevice);
hipMemcpy(d_sum, &sum, sizeof(double), hipMemcpyHostToDevice);
for (int k = 0; k < 100000; k++){
kernel<<<1,1024>>>(d_array,d_sum);
hipMemcpy(array, d_array, size, hipMemcpyDeviceToHost);
hipMemcpy(&sum, d_sum, sizeof(double), hipMemcpyDeviceToHost);
// for (int i=0; i<N; i++){
// printf("array[%d] = %.2f\n",i, array[i] );
// }
printf("sum = %.2f\n", sum );
}
hipFree(d_array);
hipFree(d_sum);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void kernel(double* d_array, double* d_sum){
// int i = (blockIdx.x*blockDim.x) + threadIdx.x;
// int x = i % 2560;
// int y = i % 2560;
for (int i = threadIdx.x + blockIdx.x * blockDim.x; i < 2560*2560; i += blockDim.x*gridDim.x){
d_array[i] = i+0.1;
printf("d_array[%d] = %.2f\n", i ,d_array[i] );
*d_sum += d_array[i];
}
}
int main(int argc, char** argv){
int N = 2560*2560;
double* array = (double*) calloc(N,sizeof(double));
double sum = 2.03;
double* d_array, *d_sum;
size_t size = N*sizeof(double);
hipMalloc((void**) &d_array, size);
hipMalloc((void**) &d_sum, sizeof(double));
hipMemcpy(d_array,array,size,hipMemcpyHostToDevice);
hipMemcpy(d_sum, &sum, sizeof(double), hipMemcpyHostToDevice);
for (int k = 0; k < 100000; k++){
kernel<<<1,1024>>>(d_array,d_sum);
hipMemcpy(array, d_array, size, hipMemcpyDeviceToHost);
hipMemcpy(&sum, d_sum, sizeof(double), hipMemcpyDeviceToHost);
// for (int i=0; i<N; i++){
// printf("array[%d] = %.2f\n",i, array[i] );
// }
printf("sum = %.2f\n", sum );
}
hipFree(d_array);
hipFree(d_sum);
return 0;
} | .text
.file "copy_array.hip"
.globl _Z21__device_stub__kernelPdS_ # -- Begin function _Z21__device_stub__kernelPdS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPdS_,@function
_Z21__device_stub__kernelPdS_: # @_Z21__device_stub__kernelPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPdS_, .Lfunc_end0-_Z21__device_stub__kernelPdS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movl $6553600, %edi # imm = 0x640000
movl $8, %esi
callq calloc
movq %rax, %r14
movabsq $4611753572421798461, %rax # imm = 0x40003D70A3D70A3D
movq %rax, 24(%rsp)
leaq 16(%rsp), %rdi
movl $52428800, %esi # imm = 0x3200000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $52428800, %edx # imm = 0x3200000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 24(%rsp), %r15
movl $8, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $100000, %ebp # imm = 0x186A0
leaq 1023(%rbx), %r12
leaq 96(%rsp), %r13
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rsi
movl $52428800, %edx # imm = 0x3200000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $8, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movsd 24(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
decl %ebp
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z6kernelPdS_, %edi
movq %r13, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPdS_,@object # @_Z6kernelPdS_
.section .rodata,"a",@progbits
.globl _Z6kernelPdS_
.p2align 3, 0x0
_Z6kernelPdS_:
.quad _Z21__device_stub__kernelPdS_
.size _Z6kernelPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sum = %.2f\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPdS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00117c63_00000000-6_copy_array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPdS_PdS_
.type _Z27__device_stub__Z6kernelPdS_PdS_, @function
_Z27__device_stub__Z6kernelPdS_PdS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6kernelPdS_PdS_, .-_Z27__device_stub__Z6kernelPdS_PdS_
.globl _Z6kernelPdS_
.type _Z6kernelPdS_, @function
_Z6kernelPdS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPdS_, .-_Z6kernelPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "sum = %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $8, %esi
movl $6553600, %edi
call calloc@PLT
movq %rax, %rbp
movq .LC0(%rip), %rax
movq %rax, 8(%rsp)
leaq 16(%rsp), %rdi
movl $52428800, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $52428800, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $100000, %ebx
leaq .LC1(%rip), %r12
jmp .L13
.L12:
movl $2, %ecx
movl $52428800, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movsd 8(%rsp), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
subl $1, %ebx
je .L17
.L13:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6kernelPdS_PdS_
jmp .L12
.L17:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1546188227
.long 1073757552
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "copy_array.hip"
.globl _Z21__device_stub__kernelPdS_ # -- Begin function _Z21__device_stub__kernelPdS_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPdS_,@function
_Z21__device_stub__kernelPdS_: # @_Z21__device_stub__kernelPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPdS_, .Lfunc_end0-_Z21__device_stub__kernelPdS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movl $6553600, %edi # imm = 0x640000
movl $8, %esi
callq calloc
movq %rax, %r14
movabsq $4611753572421798461, %rax # imm = 0x40003D70A3D70A3D
movq %rax, 24(%rsp)
leaq 16(%rsp), %rdi
movl $52428800, %esi # imm = 0x3200000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $52428800, %edx # imm = 0x3200000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 24(%rsp), %r15
movl $8, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $100000, %ebp # imm = 0x186A0
leaq 1023(%rbx), %r12
leaq 96(%rsp), %r13
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rsi
movl $52428800, %edx # imm = 0x3200000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $8, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movsd 24(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
decl %ebp
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z6kernelPdS_, %edi
movq %r13, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPdS_,@object # @_Z6kernelPdS_
.section .rodata,"a",@progbits
.globl _Z6kernelPdS_
.p2align 3, 0x0
_Z6kernelPdS_:
.quad _Z21__device_stub__kernelPdS_
.size _Z6kernelPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sum = %.2f\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPdS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
int main(int argc, char **argv) {
int nDevices;
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
printf("Device name: %s\n", prop.name);
printf("Capabilities: %d.%d\n", prop.major, prop.minor);
printf("Global mem: %lu\n", prop.totalGlobalMem / 1024 / 1024 / 1024);
printf("Max threads per block: %d\n", prop.maxThreadsPerBlock);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
int main(int argc, char **argv) {
int nDevices;
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
printf("Device name: %s\n", prop.name);
printf("Capabilities: %d.%d\n", prop.major, prop.minor);
printf("Global mem: %lu\n", prop.totalGlobalMem / 1024 / 1024 / 1024);
printf("Max threads per block: %d\n", prop.maxThreadsPerBlock);
return 0;
} | .file "tmpxft_0002dfdf_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device name: %s\n"
.LC1:
.string "Capabilities: %d.%d\n"
.LC2:
.string "Global mem: %lu\n"
.LC3:
.string "Max threads per block: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %ecx
movl 360(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 288(%rsp), %rdx
shrq $30, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
int main(int argc, char **argv) {
int nDevices;
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
printf("Device name: %s\n", prop.name);
printf("Capabilities: %d.%d\n", prop.major, prop.minor);
printf("Global mem: %lu\n", prop.totalGlobalMem / 1024 / 1024 / 1024);
printf("Max threads per block: %d\n", prop.maxThreadsPerBlock);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(int argc, char **argv) {
int nDevices;
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
printf("Device name: %s\n", prop.name);
printf("Capabilities: %d.%d\n", prop.major, prop.minor);
printf("Global mem: %lu\n", prop.totalGlobalMem / 1024 / 1024 / 1024);
printf("Max threads per block: %d\n", prop.maxThreadsPerBlock);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(int argc, char **argv) {
int nDevices;
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
printf("Device name: %s\n", prop.name);
printf("Capabilities: %d.%d\n", prop.major, prop.minor);
printf("Global mem: %lu\n", prop.totalGlobalMem / 1024 / 1024 / 1024);
printf("Max threads per block: %d\n", prop.maxThreadsPerBlock);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(int argc, char **argv) {
int nDevices;
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
printf("Device name: %s\n", prop.name);
printf("Capabilities: %d.%d\n", prop.major, prop.minor);
printf("Global mem: %lu\n", prop.totalGlobalMem / 1024 / 1024 / 1024);
printf("Max threads per block: %d\n", prop.maxThreadsPerBlock);
return 0;
} | .text
.file "test.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 360(%rsp), %esi
movl 364(%rsp), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 288(%rsp), %rsi
shrq $30, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 320(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device name: %s\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Capabilities: %d.%d\n"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Global mem: %lu\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Max threads per block: %d\n"
.size .L.str.3, 27
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002dfdf_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device name: %s\n"
.LC1:
.string "Capabilities: %d.%d\n"
.LC2:
.string "Global mem: %lu\n"
.LC3:
.string "Max threads per block: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %ecx
movl 360(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 288(%rsp), %rdx
shrq $30, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 360(%rsp), %esi
movl 364(%rsp), %edx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 288(%rsp), %rsi
shrq $30, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 320(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device name: %s\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Capabilities: %d.%d\n"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Global mem: %lu\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Max threads per block: %d\n"
.size .L.str.3, 27
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | # include <cuda.h>
# include <cuda_runtime.h>
extern "C"
unsigned char * DFTimageCuda(unsigned char * data, int width, int height);
__global__ void processPixelVertical(unsigned char * data_dev, double * PkbReal_dev, double * PkbIm_dev, int width, int height){
int posThread = blockIdx.x*blockDim.x + threadIdx.x;
if(posThread < width*height){
int k = posThread/width;
int b = posThread - k*width;
double sumReal = 0.0;
double sumIm = 0.0;
for(int a = 0; a < height; a++){
double theta = -2.0*3.1416*k*a/height;
sumReal += (double)data_dev[b + width*a]*cosf(theta);
sumIm += (double)data_dev[b + width*a]*sinf(theta);
}
PkbReal_dev[b + width*k] = sumReal/(double)height;
PkbIm_dev[b + width*k] = sumIm/(double)height;
}
}
__global__ void processPixelHorizontal(unsigned char *data_dev, double * PkbReal_dev, double * PkbIm_dev, int width, int height){
int posThread = blockIdx.x*blockDim.x + threadIdx.x;
if(posThread < width*height){
int k = posThread/width;
int l = posThread - k*width;
double sumReal = 0.0;
double sumIm = 0.0;
for(int b = 0; b < width; b++){
double theta = -2.0*3.1416*l*b/width;
sumReal += (double)PkbReal_dev[b + k*width]*cosf(theta) - (double)PkbIm_dev[b+k*width]*sinf(theta);
sumIm += (double)PkbReal_dev[b + k*width]*sinf(theta) + (double)PkbIm_dev[b+k*width]*cos(theta);
}
sumReal = sumReal/width;
sumIm += sumIm/width;
sumReal = sqrtf(sumReal*sumReal + sumIm*sumIm);
data_dev[k*width + l] = (unsigned char) sumReal;
}
}
unsigned char * DFTimageCuda(unsigned char * data, int width, int height){
unsigned char * dataDev;
cudaMalloc((void**)&dataDev, width*height*sizeof(unsigned char));
double * PkbRealDev;
double * PkbImDev;
cudaMalloc((void**)&PkbRealDev, width*height*sizeof(double));
cudaMalloc((void**)&PkbImDev, width*height*sizeof(double));
cudaMemcpy(dataDev, data, width*height*sizeof(unsigned char), cudaMemcpyHostToDevice);
int nthreads = 1024;
int nblocks = width*height/nthreads;
if(width*height % nthreads > 0)
nblocks++;
processPixelVertical<<<nblocks, nthreads>>>(dataDev, PkbRealDev, PkbImDev, width, height);
processPixelHorizontal<<<nblocks, nthreads>>>(dataDev, PkbRealDev, PkbImDev, width, height);
unsigned char * Dft = new unsigned char[width*height];
cudaMemcpy(Dft, dataDev, width*height*sizeof(unsigned char), cudaMemcpyDeviceToHost);
cudaFree(dataDev);
cudaFree(PkbRealDev);
cudaFree(PkbImDev);
return Dft;
}
int main(){
} | .file "tmpxft_00044167_00000000-6_transformations.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2028:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2028:
.size main, .-main
.globl _Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii
.type _Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii, @function
_Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20processPixelVerticalPhPdS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii, .-_Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii
.globl _Z20processPixelVerticalPhPdS0_ii
.type _Z20processPixelVerticalPhPdS0_ii, @function
_Z20processPixelVerticalPhPdS0_ii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z20processPixelVerticalPhPdS0_ii, .-_Z20processPixelVerticalPhPdS0_ii
.globl _Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii
.type _Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii, @function
_Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22processPixelHorizontalPhPdS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii, .-_Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii
.globl _Z22processPixelHorizontalPhPdS0_ii
.type _Z22processPixelHorizontalPhPdS0_ii, @function
_Z22processPixelHorizontalPhPdS0_ii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z22processPixelHorizontalPhPdS0_ii, .-_Z22processPixelHorizontalPhPdS0_ii
.globl DFTimageCuda
.type DFTimageCuda, @function
DFTimageCuda:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movl %esi, %r12d
movl %edx, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %esi, %ebx
imull %edx, %ebx
movslq %ebx, %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 0(,%rbp,8), %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leal 1023(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $10, %eax
movl %ebx, %edx
sarl $31, %edx
shrl $22, %edx
addl %edx, %ebx
andl $1023, %ebx
subl %edx, %ebx
testl %ebx, %ebx
setg %dl
movzbl %dl, %edx
leal (%rax,%rdx), %ebx
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
movl $2, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movq %rbx, %rax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %r13d, %r8d
movl %r12d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii
jmp .L22
.L27:
movl %r13d, %r8d
movl %r12d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size DFTimageCuda, .-DFTimageCuda
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22processPixelHorizontalPhPdS0_ii"
.align 8
.LC1:
.string "_Z20processPixelVerticalPhPdS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22processPixelHorizontalPhPdS0_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20processPixelVerticalPhPdS0_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | # include <cuda.h>
# include <cuda_runtime.h>
extern "C"
unsigned char * DFTimageCuda(unsigned char * data, int width, int height);
__global__ void processPixelVertical(unsigned char * data_dev, double * PkbReal_dev, double * PkbIm_dev, int width, int height){
int posThread = blockIdx.x*blockDim.x + threadIdx.x;
if(posThread < width*height){
int k = posThread/width;
int b = posThread - k*width;
double sumReal = 0.0;
double sumIm = 0.0;
for(int a = 0; a < height; a++){
double theta = -2.0*3.1416*k*a/height;
sumReal += (double)data_dev[b + width*a]*cosf(theta);
sumIm += (double)data_dev[b + width*a]*sinf(theta);
}
PkbReal_dev[b + width*k] = sumReal/(double)height;
PkbIm_dev[b + width*k] = sumIm/(double)height;
}
}
__global__ void processPixelHorizontal(unsigned char *data_dev, double * PkbReal_dev, double * PkbIm_dev, int width, int height){
int posThread = blockIdx.x*blockDim.x + threadIdx.x;
if(posThread < width*height){
int k = posThread/width;
int l = posThread - k*width;
double sumReal = 0.0;
double sumIm = 0.0;
for(int b = 0; b < width; b++){
double theta = -2.0*3.1416*l*b/width;
sumReal += (double)PkbReal_dev[b + k*width]*cosf(theta) - (double)PkbIm_dev[b+k*width]*sinf(theta);
sumIm += (double)PkbReal_dev[b + k*width]*sinf(theta) + (double)PkbIm_dev[b+k*width]*cos(theta);
}
sumReal = sumReal/width;
sumIm += sumIm/width;
sumReal = sqrtf(sumReal*sumReal + sumIm*sumIm);
data_dev[k*width + l] = (unsigned char) sumReal;
}
}
unsigned char * DFTimageCuda(unsigned char * data, int width, int height){
unsigned char * dataDev;
cudaMalloc((void**)&dataDev, width*height*sizeof(unsigned char));
double * PkbRealDev;
double * PkbImDev;
cudaMalloc((void**)&PkbRealDev, width*height*sizeof(double));
cudaMalloc((void**)&PkbImDev, width*height*sizeof(double));
cudaMemcpy(dataDev, data, width*height*sizeof(unsigned char), cudaMemcpyHostToDevice);
int nthreads = 1024;
int nblocks = width*height/nthreads;
if(width*height % nthreads > 0)
nblocks++;
processPixelVertical<<<nblocks, nthreads>>>(dataDev, PkbRealDev, PkbImDev, width, height);
processPixelHorizontal<<<nblocks, nthreads>>>(dataDev, PkbRealDev, PkbImDev, width, height);
unsigned char * Dft = new unsigned char[width*height];
cudaMemcpy(Dft, dataDev, width*height*sizeof(unsigned char), cudaMemcpyDeviceToHost);
cudaFree(dataDev);
cudaFree(PkbRealDev);
cudaFree(PkbImDev);
return Dft;
}
int main(){
} | # include <hip/hip_runtime.h>
extern "C"
unsigned char * DFTimageCuda(unsigned char * data, int width, int height);
__global__ void processPixelVertical(unsigned char * data_dev, double * PkbReal_dev, double * PkbIm_dev, int width, int height){
int posThread = blockIdx.x*blockDim.x + threadIdx.x;
if(posThread < width*height){
int k = posThread/width;
int b = posThread - k*width;
double sumReal = 0.0;
double sumIm = 0.0;
for(int a = 0; a < height; a++){
double theta = -2.0*3.1416*k*a/height;
sumReal += (double)data_dev[b + width*a]*cosf(theta);
sumIm += (double)data_dev[b + width*a]*sinf(theta);
}
PkbReal_dev[b + width*k] = sumReal/(double)height;
PkbIm_dev[b + width*k] = sumIm/(double)height;
}
}
__global__ void processPixelHorizontal(unsigned char *data_dev, double * PkbReal_dev, double * PkbIm_dev, int width, int height){
int posThread = blockIdx.x*blockDim.x + threadIdx.x;
if(posThread < width*height){
int k = posThread/width;
int l = posThread - k*width;
double sumReal = 0.0;
double sumIm = 0.0;
for(int b = 0; b < width; b++){
double theta = -2.0*3.1416*l*b/width;
sumReal += (double)PkbReal_dev[b + k*width]*cosf(theta) - (double)PkbIm_dev[b+k*width]*sinf(theta);
sumIm += (double)PkbReal_dev[b + k*width]*sinf(theta) + (double)PkbIm_dev[b+k*width]*cos(theta);
}
sumReal = sumReal/width;
sumIm += sumIm/width;
sumReal = sqrtf(sumReal*sumReal + sumIm*sumIm);
data_dev[k*width + l] = (unsigned char) sumReal;
}
}
unsigned char * DFTimageCuda(unsigned char * data, int width, int height){
unsigned char * dataDev;
hipMalloc((void**)&dataDev, width*height*sizeof(unsigned char));
double * PkbRealDev;
double * PkbImDev;
hipMalloc((void**)&PkbRealDev, width*height*sizeof(double));
hipMalloc((void**)&PkbImDev, width*height*sizeof(double));
hipMemcpy(dataDev, data, width*height*sizeof(unsigned char), hipMemcpyHostToDevice);
int nthreads = 1024;
int nblocks = width*height/nthreads;
if(width*height % nthreads > 0)
nblocks++;
processPixelVertical<<<nblocks, nthreads>>>(dataDev, PkbRealDev, PkbImDev, width, height);
processPixelHorizontal<<<nblocks, nthreads>>>(dataDev, PkbRealDev, PkbImDev, width, height);
unsigned char * Dft = new unsigned char[width*height];
hipMemcpy(Dft, dataDev, width*height*sizeof(unsigned char), hipMemcpyDeviceToHost);
hipFree(dataDev);
hipFree(PkbRealDev);
hipFree(PkbImDev);
return Dft;
}
int main(){
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | # include <hip/hip_runtime.h>
extern "C"
unsigned char * DFTimageCuda(unsigned char * data, int width, int height);
__global__ void processPixelVertical(unsigned char * data_dev, double * PkbReal_dev, double * PkbIm_dev, int width, int height){
int posThread = blockIdx.x*blockDim.x + threadIdx.x;
if(posThread < width*height){
int k = posThread/width;
int b = posThread - k*width;
double sumReal = 0.0;
double sumIm = 0.0;
for(int a = 0; a < height; a++){
double theta = -2.0*3.1416*k*a/height;
sumReal += (double)data_dev[b + width*a]*cosf(theta);
sumIm += (double)data_dev[b + width*a]*sinf(theta);
}
PkbReal_dev[b + width*k] = sumReal/(double)height;
PkbIm_dev[b + width*k] = sumIm/(double)height;
}
}
__global__ void processPixelHorizontal(unsigned char *data_dev, double * PkbReal_dev, double * PkbIm_dev, int width, int height){
int posThread = blockIdx.x*blockDim.x + threadIdx.x;
if(posThread < width*height){
int k = posThread/width;
int l = posThread - k*width;
double sumReal = 0.0;
double sumIm = 0.0;
for(int b = 0; b < width; b++){
double theta = -2.0*3.1416*l*b/width;
sumReal += (double)PkbReal_dev[b + k*width]*cosf(theta) - (double)PkbIm_dev[b+k*width]*sinf(theta);
sumIm += (double)PkbReal_dev[b + k*width]*sinf(theta) + (double)PkbIm_dev[b+k*width]*cos(theta);
}
sumReal = sumReal/width;
sumIm += sumIm/width;
sumReal = sqrtf(sumReal*sumReal + sumIm*sumIm);
data_dev[k*width + l] = (unsigned char) sumReal;
}
}
unsigned char * DFTimageCuda(unsigned char * data, int width, int height){
unsigned char * dataDev;
hipMalloc((void**)&dataDev, width*height*sizeof(unsigned char));
double * PkbRealDev;
double * PkbImDev;
hipMalloc((void**)&PkbRealDev, width*height*sizeof(double));
hipMalloc((void**)&PkbImDev, width*height*sizeof(double));
hipMemcpy(dataDev, data, width*height*sizeof(unsigned char), hipMemcpyHostToDevice);
int nthreads = 1024;
int nblocks = width*height/nthreads;
if(width*height % nthreads > 0)
nblocks++;
processPixelVertical<<<nblocks, nthreads>>>(dataDev, PkbRealDev, PkbImDev, width, height);
processPixelHorizontal<<<nblocks, nthreads>>>(dataDev, PkbRealDev, PkbImDev, width, height);
unsigned char * Dft = new unsigned char[width*height];
hipMemcpy(Dft, dataDev, width*height*sizeof(unsigned char), hipMemcpyDeviceToHost);
hipFree(dataDev);
hipFree(PkbRealDev);
hipFree(PkbImDev);
return Dft;
}
int main(){
} | .text
.file "transformations.hip"
.globl _Z35__device_stub__processPixelVerticalPhPdS0_ii # -- Begin function _Z35__device_stub__processPixelVerticalPhPdS0_ii
.p2align 4, 0x90
.type _Z35__device_stub__processPixelVerticalPhPdS0_ii,@function
_Z35__device_stub__processPixelVerticalPhPdS0_ii: # @_Z35__device_stub__processPixelVerticalPhPdS0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20processPixelVerticalPhPdS0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__processPixelVerticalPhPdS0_ii, .Lfunc_end0-_Z35__device_stub__processPixelVerticalPhPdS0_ii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__processPixelHorizontalPhPdS0_ii # -- Begin function _Z37__device_stub__processPixelHorizontalPhPdS0_ii
.p2align 4, 0x90
.type _Z37__device_stub__processPixelHorizontalPhPdS0_ii,@function
_Z37__device_stub__processPixelHorizontalPhPdS0_ii: # @_Z37__device_stub__processPixelHorizontalPhPdS0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22processPixelHorizontalPhPdS0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z37__device_stub__processPixelHorizontalPhPdS0_ii, .Lfunc_end1-_Z37__device_stub__processPixelHorizontalPhPdS0_ii
.cfi_endproc
# -- End function
.globl DFTimageCuda # -- Begin function DFTimageCuda
.p2align 4, 0x90
.type DFTimageCuda,@function
DFTimageCuda: # @DFTimageCuda
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r14d
movq %rdi, %r12
movabsq $4294968320, %r15 # imm = 0x100000400
movl %edx, %eax
imull %esi, %eax
movslq %eax, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq (,%rbx,8), %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leal 1023(%rbx), %eax
testl %ebx, %ebx
cmovnsl %ebx, %eax
sarl $10, %eax
xorl %ecx, %ecx
testl $-2147482625, %ebx # imm = 0x800003FF
setg %cl
addl %eax, %ecx
leaq (%rcx,%r15), %r12
addq $-1024, %r12 # imm = 0xFC00
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r14d, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20processPixelVerticalPhPdS0_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r14d, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z22processPixelHorizontalPhPdS0_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq %rbx, %rdi
callq _Znam
movq %rax, %r14
movq 16(%rsp), %rsi
movq %rax, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r14, %rax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size DFTimageCuda, .Lfunc_end2-DFTimageCuda
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20processPixelVerticalPhPdS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22processPixelHorizontalPhPdS0_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20processPixelVerticalPhPdS0_ii,@object # @_Z20processPixelVerticalPhPdS0_ii
.section .rodata,"a",@progbits
.globl _Z20processPixelVerticalPhPdS0_ii
.p2align 3, 0x0
_Z20processPixelVerticalPhPdS0_ii:
.quad _Z35__device_stub__processPixelVerticalPhPdS0_ii
.size _Z20processPixelVerticalPhPdS0_ii, 8
.type _Z22processPixelHorizontalPhPdS0_ii,@object # @_Z22processPixelHorizontalPhPdS0_ii
.globl _Z22processPixelHorizontalPhPdS0_ii
.p2align 3, 0x0
_Z22processPixelHorizontalPhPdS0_ii:
.quad _Z37__device_stub__processPixelHorizontalPhPdS0_ii
.size _Z22processPixelHorizontalPhPdS0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20processPixelVerticalPhPdS0_ii"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22processPixelHorizontalPhPdS0_ii"
.size .L__unnamed_2, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__processPixelVerticalPhPdS0_ii
.addrsig_sym _Z37__device_stub__processPixelHorizontalPhPdS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20processPixelVerticalPhPdS0_ii
.addrsig_sym _Z22processPixelHorizontalPhPdS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00044167_00000000-6_transformations.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2028:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2028:
.size main, .-main
.globl _Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii
.type _Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii, @function
_Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20processPixelVerticalPhPdS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii, .-_Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii
.globl _Z20processPixelVerticalPhPdS0_ii
.type _Z20processPixelVerticalPhPdS0_ii, @function
_Z20processPixelVerticalPhPdS0_ii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z20processPixelVerticalPhPdS0_ii, .-_Z20processPixelVerticalPhPdS0_ii
.globl _Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii
.type _Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii, @function
_Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22processPixelHorizontalPhPdS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii, .-_Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii
.globl _Z22processPixelHorizontalPhPdS0_ii
.type _Z22processPixelHorizontalPhPdS0_ii, @function
_Z22processPixelHorizontalPhPdS0_ii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z22processPixelHorizontalPhPdS0_ii, .-_Z22processPixelHorizontalPhPdS0_ii
.globl DFTimageCuda
.type DFTimageCuda, @function
DFTimageCuda:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movl %esi, %r12d
movl %edx, %r13d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %esi, %ebx
imull %edx, %ebx
movslq %ebx, %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 0(,%rbp,8), %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leal 1023(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $10, %eax
movl %ebx, %edx
sarl $31, %edx
shrl $22, %edx
addl %edx, %ebx
andl $1023, %ebx
subl %edx, %ebx
testl %ebx, %ebx
setg %dl
movzbl %dl, %edx
leal (%rax,%rdx), %ebx
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %rbx
movl $2, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movq %rbx, %rax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %r13d, %r8d
movl %r12d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z47__device_stub__Z20processPixelVerticalPhPdS0_iiPhPdS0_ii
jmp .L22
.L27:
movl %r13d, %r8d
movl %r12d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z49__device_stub__Z22processPixelHorizontalPhPdS0_iiPhPdS0_ii
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size DFTimageCuda, .-DFTimageCuda
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22processPixelHorizontalPhPdS0_ii"
.align 8
.LC1:
.string "_Z20processPixelVerticalPhPdS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22processPixelHorizontalPhPdS0_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20processPixelVerticalPhPdS0_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transformations.hip"
.globl _Z35__device_stub__processPixelVerticalPhPdS0_ii # -- Begin function _Z35__device_stub__processPixelVerticalPhPdS0_ii
.p2align 4, 0x90
.type _Z35__device_stub__processPixelVerticalPhPdS0_ii,@function
_Z35__device_stub__processPixelVerticalPhPdS0_ii: # @_Z35__device_stub__processPixelVerticalPhPdS0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20processPixelVerticalPhPdS0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__processPixelVerticalPhPdS0_ii, .Lfunc_end0-_Z35__device_stub__processPixelVerticalPhPdS0_ii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__processPixelHorizontalPhPdS0_ii # -- Begin function _Z37__device_stub__processPixelHorizontalPhPdS0_ii
.p2align 4, 0x90
.type _Z37__device_stub__processPixelHorizontalPhPdS0_ii,@function
_Z37__device_stub__processPixelHorizontalPhPdS0_ii: # @_Z37__device_stub__processPixelHorizontalPhPdS0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22processPixelHorizontalPhPdS0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z37__device_stub__processPixelHorizontalPhPdS0_ii, .Lfunc_end1-_Z37__device_stub__processPixelHorizontalPhPdS0_ii
.cfi_endproc
# -- End function
.globl DFTimageCuda # -- Begin function DFTimageCuda
.p2align 4, 0x90
.type DFTimageCuda,@function
DFTimageCuda: # @DFTimageCuda
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r14d
movq %rdi, %r12
movabsq $4294968320, %r15 # imm = 0x100000400
movl %edx, %eax
imull %esi, %eax
movslq %eax, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq (,%rbx,8), %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leal 1023(%rbx), %eax
testl %ebx, %ebx
cmovnsl %ebx, %eax
sarl $10, %eax
xorl %ecx, %ecx
testl $-2147482625, %ebx # imm = 0x800003FF
setg %cl
addl %eax, %ecx
leaq (%rcx,%r15), %r12
addq $-1024, %r12 # imm = 0xFC00
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r14d, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20processPixelVerticalPhPdS0_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r14d, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z22processPixelHorizontalPhPdS0_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq %rbx, %rdi
callq _Znam
movq %rax, %r14
movq 16(%rsp), %rsi
movq %rax, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r14, %rax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size DFTimageCuda, .Lfunc_end2-DFTimageCuda
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20processPixelVerticalPhPdS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22processPixelHorizontalPhPdS0_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20processPixelVerticalPhPdS0_ii,@object # @_Z20processPixelVerticalPhPdS0_ii
.section .rodata,"a",@progbits
.globl _Z20processPixelVerticalPhPdS0_ii
.p2align 3, 0x0
_Z20processPixelVerticalPhPdS0_ii:
.quad _Z35__device_stub__processPixelVerticalPhPdS0_ii
.size _Z20processPixelVerticalPhPdS0_ii, 8
.type _Z22processPixelHorizontalPhPdS0_ii,@object # @_Z22processPixelHorizontalPhPdS0_ii
.globl _Z22processPixelHorizontalPhPdS0_ii
.p2align 3, 0x0
_Z22processPixelHorizontalPhPdS0_ii:
.quad _Z37__device_stub__processPixelHorizontalPhPdS0_ii
.size _Z22processPixelHorizontalPhPdS0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20processPixelVerticalPhPdS0_ii"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22processPixelHorizontalPhPdS0_ii"
.size .L__unnamed_2, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__processPixelVerticalPhPdS0_ii
.addrsig_sym _Z37__device_stub__processPixelHorizontalPhPdS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20processPixelVerticalPhPdS0_ii
.addrsig_sym _Z22processPixelHorizontalPhPdS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
By : Johan S. Suarez L. or @jadry92 in twitter
This kernel make inverse of the matrix A in the matrix B
*/
// Macro for mastrix index
#define Ind(a,i,j) (a)[(j)+(i)*N]
#include <stdio.h> //manipulacion de ficheros, lectura-escritura ficheros, scandf-printf
#include <stdlib.h> //Conversion de tipos de datos, memoria dinamica, abs
#include <string.h> //Uso de memcpy principalmente
#include <math.h> //funciones matemáticas
#include <time.h>
/* Funtion check malloc of variables */
void checkMalloc(void * var,const char *name){
if( var == NULL){
printf("It's not possible to allocate %s. \n",name);}
else {
printf(" Memory has already been allocated %s.\n",name);}
}
int main(int argc, char **argv){
/* Initiation of variables*/
int i,j; // i == rows and j == colms
int N =3;
float* A;
float* B;
/* Reservation of memory */
A = (float*)malloc(N*sizeof(float));
checkMalloc(A,"A");
B = (float*)malloc(N*sizeof(float));
checkMalloc(B,"B");
/* Initialitation Matix A*/
/* Initialitation Matix A*/
printf("A =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
Ind(A,i,j) = rand()/(RAND_MAX/10.0);
printf(" %f ",Ind(A,i,j));
}
printf("\n");
}
/* Gaussian Elimination*/
// The B has to be identity matrix
memset(B,0.0,N*sizeof(float));
for(i = 0; i < N; i++){
Ind(B,i,i) = 1.0;
}
printf("B =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(B,i,j));
}
printf("\n");
}
int y;
float key;
for(i = 0; i < N; i++){ // for to rows
for(j = 0; j <N ; j++){
y=0;
if(i==j){
}else{
while(y<N){
if(i+1<N ){
Ind(A,i,j+y) = Ind(A,i,j+y) - Ind(A,i+1,j+y)*(Ind(A,i,j)/Ind(A,i+1,j));
Ind(B,i,j+y) = Ind(B,i,j+y) - Ind(B,i+1,j+y)*(Ind(A,i,j)/Ind(A,i+1,j));
}else{
Ind(A,i,j+y) = Ind(A,i,j+y) - Ind(A,i-N-1+y,j+y)*(Ind(A,i,j)/Ind(A,i-N-1,j));
Ind(B,i,j+y) = Ind(B,i,j+y) - Ind(B,i-N-1+y,j+y)*(Ind(A,i,j)/Ind(A,i-N-1,j));
}
y++;
}
}
//Ind(A,i,j) = 1;
//Ind(B,i,j) = Ind(B,i,j)/Ind(A,i,j);
//}
}
}
printf("A =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(A,i,j));
}
printf("\n");
}
printf("B =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(B,i,j));
}
printf("\n");
}
/* Descompotition LU*/
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
By : Johan S. Suarez L. or @jadry92 in twitter
This kernel make inverse of the matrix A in the matrix B
*/
// Macro for mastrix index
#define Ind(a,i,j) (a)[(j)+(i)*N]
#include <stdio.h> //manipulacion de ficheros, lectura-escritura ficheros, scandf-printf
#include <stdlib.h> //Conversion de tipos de datos, memoria dinamica, abs
#include <string.h> //Uso de memcpy principalmente
#include <math.h> //funciones matemáticas
#include <time.h>
/* Funtion check malloc of variables */
void checkMalloc(void * var,const char *name){
if( var == NULL){
printf("It's not possible to allocate %s. \n",name);}
else {
printf(" Memory has already been allocated %s.\n",name);}
}
int main(int argc, char **argv){
/* Initiation of variables*/
int i,j; // i == rows and j == colms
int N =3;
float* A;
float* B;
/* Reservation of memory */
A = (float*)malloc(N*sizeof(float));
checkMalloc(A,"A");
B = (float*)malloc(N*sizeof(float));
checkMalloc(B,"B");
/* Initialitation Matix A*/
/* Initialitation Matix A*/
printf("A =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
Ind(A,i,j) = rand()/(RAND_MAX/10.0);
printf(" %f ",Ind(A,i,j));
}
printf("\n");
}
/* Gaussian Elimination*/
// The B has to be identity matrix
memset(B,0.0,N*sizeof(float));
for(i = 0; i < N; i++){
Ind(B,i,i) = 1.0;
}
printf("B =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(B,i,j));
}
printf("\n");
}
int y;
float key;
for(i = 0; i < N; i++){ // for to rows
for(j = 0; j <N ; j++){
y=0;
if(i==j){
}else{
while(y<N){
if(i+1<N ){
Ind(A,i,j+y) = Ind(A,i,j+y) - Ind(A,i+1,j+y)*(Ind(A,i,j)/Ind(A,i+1,j));
Ind(B,i,j+y) = Ind(B,i,j+y) - Ind(B,i+1,j+y)*(Ind(A,i,j)/Ind(A,i+1,j));
}else{
Ind(A,i,j+y) = Ind(A,i,j+y) - Ind(A,i-N-1+y,j+y)*(Ind(A,i,j)/Ind(A,i-N-1,j));
Ind(B,i,j+y) = Ind(B,i,j+y) - Ind(B,i-N-1+y,j+y)*(Ind(A,i,j)/Ind(A,i-N-1,j));
}
y++;
}
}
//Ind(A,i,j) = 1;
//Ind(B,i,j) = Ind(B,i,j)/Ind(A,i,j);
//}
}
}
printf("A =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(A,i,j));
}
printf("\n");
}
printf("B =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(B,i,j));
}
printf("\n");
}
/* Descompotition LU*/
return 0;
} | .file "tmpxft_00028700_00000000-6_matrix_inverse.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "It's not possible to allocate %s. \n"
.align 8
.LC1:
.string " Memory has already been allocated %s.\n"
.text
.globl _Z11checkMallocPvPKc
.type _Z11checkMallocPvPKc, @function
_Z11checkMallocPvPKc:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
testq %rdi, %rdi
je .L7
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z11checkMallocPvPKc, .-_Z11checkMallocPvPKc
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "A"
.LC3:
.string "B"
.LC4:
.string "A =\n"
.LC6:
.string " %f "
.LC7:
.string "\n"
.LC9:
.string "B =\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $12, %edi
call malloc@PLT
movq %rax, %rbx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _Z11checkMallocPvPKc
movl $12, %edi
call malloc@PLT
movq %rax, %rbp
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _Z11checkMallocPvPKc
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, (%rsp)
movq %rbx, %r12
movl $0, %r14d
leaq .LC6(%rip), %r13
leaq .LC7(%rip), %r15
movq %rbx, 8(%rsp)
.L9:
movl $0, %ebx
.L10:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rbx,4)
cvtss2sd %xmm0, %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L10
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r14d
addq $12, %r12
cmpl $9, %r14d
jne .L9
movq 8(%rsp), %rbx
movq $0, 4(%rbp)
movss .LC8(%rip), %xmm0
movss %xmm0, 0(%rbp)
movss %xmm0, 16(%rbp)
movss %xmm0, 32(%rbp)
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %r15
movq %rbp, %r12
movl $0, %r14d
leaq .LC6(%rip), %r13
movq %rbx, 8(%rsp)
.L12:
movl $0, %ebx
.L13:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L13
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r14d
addq $12, %r12
cmpl $9, %r14d
jne .L12
movq 8(%rsp), %rbx
movl $0, %ecx
movl $0, %r10d
movq %r15, 8(%rsp)
jmp .L14
.L16:
movslq %r9d, %rax
salq $2, %rax
leaq (%rbx,%rax), %r12
movslq %esi, %r8
movss 24(%rbx,%rdx,4), %xmm0
divss -24(%rbx,%rdx,4), %xmm0
mulss (%rbx,%r8,4), %xmm0
movss (%r12), %xmm1
subss %xmm0, %xmm1
movss %xmm1, (%r12)
addq %rbp, %rax
movss 24(%rbx,%rdx,4), %xmm0
divss -24(%rbx,%rdx,4), %xmm0
mulss 0(%rbp,%r8,4), %xmm0
movss (%rax), %xmm1
subss %xmm0, %xmm1
movss %xmm1, (%rax)
.L17:
addl $1, %edi
addl $1, %r9d
addl $4, %esi
cmpl %esi, %r13d
je .L15
.L18:
cmpl $1, %r10d
jg .L16
movslq %edi, %rax
salq $2, %rax
leaq (%rbx,%rax), %r12
leal 3(%rdi), %r8d
movslq %r8d, %r8
movss (%r15), %xmm0
divss (%r14), %xmm0
mulss (%rbx,%r8,4), %xmm0
movss (%r12), %xmm1
subss %xmm0, %xmm1
movss %xmm1, (%r12)
addq %rbp, %rax
movss (%r15), %xmm0
divss (%r14), %xmm0
mulss 0(%rbp,%r8,4), %xmm0
movss (%rax), %xmm1
subss %xmm0, %xmm1
movss %xmm1, (%rax)
jmp .L17
.L15:
addq $1, %rdx
addl $1, %r11d
cmpq $3, %rdx
je .L35
.L19:
cmpl %edx, %r10d
je .L15
movslq %r11d, %rax
leaq (%rbx,%rax,4), %r15
leal 3(%r11), %eax
cltq
leaq (%rbx,%rax,4), %r14
leal 6(%rdx), %r13d
leal -6(%rdx), %esi
movl %r13d, %r9d
movl %r11d, %edi
jmp .L18
.L35:
addl $1, %r10d
cmpl $3, %r10d
je .L36
.L14:
movl %ecx, %r11d
addl $3, %ecx
movl $0, %edx
jmp .L19
.L36:
movq 8(%rsp), %r15
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC6(%rip), %rbp
leaq .LC7(%rip), %r13
movq (%rsp), %r14
.L21:
movl $0, %ebx
.L22:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L22
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r12d
addq $12, %r14
cmpl $9, %r12d
jne .L21
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC6(%rip), %rbp
leaq .LC7(%rip), %r13
.L24:
movl $0, %ebx
.L25:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L25
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r12d
addq $12, %r15
cmpl $9, %r12d
jne .L24
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long -1721342362
.long 1101633945
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
By : Johan S. Suarez L. or @jadry92 in twitter
This kernel make inverse of the matrix A in the matrix B
*/
// Macro for mastrix index
#define Ind(a,i,j) (a)[(j)+(i)*N]
#include <stdio.h> //manipulacion de ficheros, lectura-escritura ficheros, scandf-printf
#include <stdlib.h> //Conversion de tipos de datos, memoria dinamica, abs
#include <string.h> //Uso de memcpy principalmente
#include <math.h> //funciones matemáticas
#include <time.h>
/* Funtion check malloc of variables */
void checkMalloc(void * var,const char *name){
if( var == NULL){
printf("It's not possible to allocate %s. \n",name);}
else {
printf(" Memory has already been allocated %s.\n",name);}
}
int main(int argc, char **argv){
/* Initiation of variables*/
int i,j; // i == rows and j == colms
int N =3;
float* A;
float* B;
/* Reservation of memory */
A = (float*)malloc(N*sizeof(float));
checkMalloc(A,"A");
B = (float*)malloc(N*sizeof(float));
checkMalloc(B,"B");
/* Initialitation Matix A*/
/* Initialitation Matix A*/
printf("A =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
Ind(A,i,j) = rand()/(RAND_MAX/10.0);
printf(" %f ",Ind(A,i,j));
}
printf("\n");
}
/* Gaussian Elimination*/
// The B has to be identity matrix
memset(B,0.0,N*sizeof(float));
for(i = 0; i < N; i++){
Ind(B,i,i) = 1.0;
}
printf("B =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(B,i,j));
}
printf("\n");
}
int y;
float key;
for(i = 0; i < N; i++){ // for to rows
for(j = 0; j <N ; j++){
y=0;
if(i==j){
}else{
while(y<N){
if(i+1<N ){
Ind(A,i,j+y) = Ind(A,i,j+y) - Ind(A,i+1,j+y)*(Ind(A,i,j)/Ind(A,i+1,j));
Ind(B,i,j+y) = Ind(B,i,j+y) - Ind(B,i+1,j+y)*(Ind(A,i,j)/Ind(A,i+1,j));
}else{
Ind(A,i,j+y) = Ind(A,i,j+y) - Ind(A,i-N-1+y,j+y)*(Ind(A,i,j)/Ind(A,i-N-1,j));
Ind(B,i,j+y) = Ind(B,i,j+y) - Ind(B,i-N-1+y,j+y)*(Ind(A,i,j)/Ind(A,i-N-1,j));
}
y++;
}
}
//Ind(A,i,j) = 1;
//Ind(B,i,j) = Ind(B,i,j)/Ind(A,i,j);
//}
}
}
printf("A =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(A,i,j));
}
printf("\n");
}
printf("B =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(B,i,j));
}
printf("\n");
}
/* Descompotition LU*/
return 0;
} | /*
By : Johan S. Suarez L. or @jadry92 in twitter
This kernel make inverse of the matrix A in the matrix B
*/
// Macro for mastrix index
#define Ind(a,i,j) (a)[(j)+(i)*N]
#include <hip/hip_runtime.h>
#include <stdio.h> //manipulacion de ficheros, lectura-escritura ficheros, scandf-printf
#include <stdlib.h> //Conversion de tipos de datos, memoria dinamica, abs
#include <string.h> //Uso de memcpy principalmente
#include <math.h> //funciones matemáticas
#include <time.h>
/* Funtion check malloc of variables */
void checkMalloc(void * var,const char *name){
if( var == NULL){
printf("It's not possible to allocate %s. \n",name);}
else {
printf(" Memory has already been allocated %s.\n",name);}
}
int main(int argc, char **argv){
/* Initiation of variables*/
int i,j; // i == rows and j == colms
int N =3;
float* A;
float* B;
/* Reservation of memory */
A = (float*)malloc(N*sizeof(float));
checkMalloc(A,"A");
B = (float*)malloc(N*sizeof(float));
checkMalloc(B,"B");
/* Initialitation Matix A*/
/* Initialitation Matix A*/
printf("A =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
Ind(A,i,j) = rand()/(RAND_MAX/10.0);
printf(" %f ",Ind(A,i,j));
}
printf("\n");
}
/* Gaussian Elimination*/
// The B has to be identity matrix
memset(B,0.0,N*sizeof(float));
for(i = 0; i < N; i++){
Ind(B,i,i) = 1.0;
}
printf("B =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(B,i,j));
}
printf("\n");
}
int y;
float key;
for(i = 0; i < N; i++){ // for to rows
for(j = 0; j <N ; j++){
y=0;
if(i==j){
}else{
while(y<N){
if(i+1<N ){
Ind(A,i,j+y) = Ind(A,i,j+y) - Ind(A,i+1,j+y)*(Ind(A,i,j)/Ind(A,i+1,j));
Ind(B,i,j+y) = Ind(B,i,j+y) - Ind(B,i+1,j+y)*(Ind(A,i,j)/Ind(A,i+1,j));
}else{
Ind(A,i,j+y) = Ind(A,i,j+y) - Ind(A,i-N-1+y,j+y)*(Ind(A,i,j)/Ind(A,i-N-1,j));
Ind(B,i,j+y) = Ind(B,i,j+y) - Ind(B,i-N-1+y,j+y)*(Ind(A,i,j)/Ind(A,i-N-1,j));
}
y++;
}
}
//Ind(A,i,j) = 1;
//Ind(B,i,j) = Ind(B,i,j)/Ind(A,i,j);
//}
}
}
printf("A =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(A,i,j));
}
printf("\n");
}
printf("B =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(B,i,j));
}
printf("\n");
}
/* Descompotition LU*/
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
By : Johan S. Suarez L. or @jadry92 in twitter
This kernel make inverse of the matrix A in the matrix B
*/
// Macro for mastrix index
#define Ind(a,i,j) (a)[(j)+(i)*N]
#include <hip/hip_runtime.h>
#include <stdio.h> //manipulacion de ficheros, lectura-escritura ficheros, scandf-printf
#include <stdlib.h> //Conversion de tipos de datos, memoria dinamica, abs
#include <string.h> //Uso de memcpy principalmente
#include <math.h> //funciones matemáticas
#include <time.h>
/* Funtion check malloc of variables */
void checkMalloc(void * var,const char *name){
if( var == NULL){
printf("It's not possible to allocate %s. \n",name);}
else {
printf(" Memory has already been allocated %s.\n",name);}
}
int main(int argc, char **argv){
/* Initiation of variables*/
int i,j; // i == rows and j == colms
int N =3;
float* A;
float* B;
/* Reservation of memory */
A = (float*)malloc(N*sizeof(float));
checkMalloc(A,"A");
B = (float*)malloc(N*sizeof(float));
checkMalloc(B,"B");
/* Initialitation Matix A*/
/* Initialitation Matix A*/
printf("A =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
Ind(A,i,j) = rand()/(RAND_MAX/10.0);
printf(" %f ",Ind(A,i,j));
}
printf("\n");
}
/* Gaussian Elimination*/
// The B has to be identity matrix
memset(B,0.0,N*sizeof(float));
for(i = 0; i < N; i++){
Ind(B,i,i) = 1.0;
}
printf("B =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(B,i,j));
}
printf("\n");
}
int y;
float key;
for(i = 0; i < N; i++){ // for to rows
for(j = 0; j <N ; j++){
y=0;
if(i==j){
}else{
while(y<N){
if(i+1<N ){
Ind(A,i,j+y) = Ind(A,i,j+y) - Ind(A,i+1,j+y)*(Ind(A,i,j)/Ind(A,i+1,j));
Ind(B,i,j+y) = Ind(B,i,j+y) - Ind(B,i+1,j+y)*(Ind(A,i,j)/Ind(A,i+1,j));
}else{
Ind(A,i,j+y) = Ind(A,i,j+y) - Ind(A,i-N-1+y,j+y)*(Ind(A,i,j)/Ind(A,i-N-1,j));
Ind(B,i,j+y) = Ind(B,i,j+y) - Ind(B,i-N-1+y,j+y)*(Ind(A,i,j)/Ind(A,i-N-1,j));
}
y++;
}
}
//Ind(A,i,j) = 1;
//Ind(B,i,j) = Ind(B,i,j)/Ind(A,i,j);
//}
}
}
printf("A =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(A,i,j));
}
printf("\n");
}
printf("B =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(B,i,j));
}
printf("\n");
}
/* Descompotition LU*/
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
By : Johan S. Suarez L. or @jadry92 in twitter
This kernel make inverse of the matrix A in the matrix B
*/
// Macro for mastrix index
#define Ind(a,i,j) (a)[(j)+(i)*N]
#include <hip/hip_runtime.h>
#include <stdio.h> //manipulacion de ficheros, lectura-escritura ficheros, scandf-printf
#include <stdlib.h> //Conversion de tipos de datos, memoria dinamica, abs
#include <string.h> //Uso de memcpy principalmente
#include <math.h> //funciones matemáticas
#include <time.h>
/* Funtion check malloc of variables */
void checkMalloc(void * var,const char *name){
if( var == NULL){
printf("It's not possible to allocate %s. \n",name);}
else {
printf(" Memory has already been allocated %s.\n",name);}
}
int main(int argc, char **argv){
/* Initiation of variables*/
int i,j; // i == rows and j == colms
int N =3;
float* A;
float* B;
/* Reservation of memory */
A = (float*)malloc(N*sizeof(float));
checkMalloc(A,"A");
B = (float*)malloc(N*sizeof(float));
checkMalloc(B,"B");
/* Initialitation Matix A*/
/* Initialitation Matix A*/
printf("A =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
Ind(A,i,j) = rand()/(RAND_MAX/10.0);
printf(" %f ",Ind(A,i,j));
}
printf("\n");
}
/* Gaussian Elimination*/
// The B has to be identity matrix
memset(B,0.0,N*sizeof(float));
for(i = 0; i < N; i++){
Ind(B,i,i) = 1.0;
}
printf("B =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(B,i,j));
}
printf("\n");
}
int y;
float key;
for(i = 0; i < N; i++){ // for to rows
for(j = 0; j <N ; j++){
y=0;
if(i==j){
}else{
while(y<N){
if(i+1<N ){
Ind(A,i,j+y) = Ind(A,i,j+y) - Ind(A,i+1,j+y)*(Ind(A,i,j)/Ind(A,i+1,j));
Ind(B,i,j+y) = Ind(B,i,j+y) - Ind(B,i+1,j+y)*(Ind(A,i,j)/Ind(A,i+1,j));
}else{
Ind(A,i,j+y) = Ind(A,i,j+y) - Ind(A,i-N-1+y,j+y)*(Ind(A,i,j)/Ind(A,i-N-1,j));
Ind(B,i,j+y) = Ind(B,i,j+y) - Ind(B,i-N-1+y,j+y)*(Ind(A,i,j)/Ind(A,i-N-1,j));
}
y++;
}
}
//Ind(A,i,j) = 1;
//Ind(B,i,j) = Ind(B,i,j)/Ind(A,i,j);
//}
}
}
printf("A =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(A,i,j));
}
printf("\n");
}
printf("B =\n");
for(i = 0; i < N; i++){
for(j = 0; j < N ; j++){
printf(" %f ",Ind(B,i,j));
}
printf("\n");
}
/* Descompotition LU*/
return 0;
} | .text
.file "matrix_inverse.hip"
.globl _Z11checkMallocPvPKc # -- Begin function _Z11checkMallocPvPKc
.p2align 4, 0x90
.type _Z11checkMallocPvPKc,@function
_Z11checkMallocPvPKc: # @_Z11checkMallocPvPKc
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
movl $.L.str, %eax
movl $.L.str.1, %edi
cmoveq %rax, %rdi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z11checkMallocPvPKc, .Lfunc_end0-_Z11checkMallocPvPKc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41a9999999666666 # double 214748364.69999999
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %_Z11checkMallocPvPKc.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $12, %edi
callq malloc
movq %rax, %r14
testq %rax, %rax
movl $.L.str, %r13d
movl $.L.str.1, %r15d
movl $.L.str.1, %edi
cmoveq %r13, %rdi
xorl %r12d, %r12d
movl $.L.str.2, %esi
xorl %eax, %eax
callq printf
movl $12, %edi
callq malloc
movq %rax, %rbx
testq %rax, %rax
cmoveq %r13, %r15
movl $.L.str.3, %esi
movq %r15, %rdi
xorl %eax, %eax
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq %r14, %r15
.p2align 4, 0x90
.LBB1_1: # %.preheader186
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%r13,4)
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r13
cmpq $3, %r13
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $12, %r15
cmpq $3, %r12
jne .LBB1_1
# %bb.4:
movl $0, 8(%rbx)
movq $0, (%rbx)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax) # imm = 0x3F800000
addq $16, %rax
cmpq $48, %rax
jne .LBB1_5
# %bb.6:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB1_7: # %.preheader185
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r13
cmpq $3, %r13
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $12, %r12
cmpq $3, %r15
jne .LBB1_7
# %bb.10: # %.preheader184
leaq -24(%r14), %rax
movq %rax, 8(%rsp) # 8-byte Spill
movl $3, %r8d
xorl %edx, %edx
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_11 Depth=1
incq %rdx
movq (%rsp), %r8 # 8-byte Reload
addq $3, %r8
cmpq $3, %rdx
je .LBB1_20
.LBB1_11: # %.preheader183
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
# Child Loop BB1_14 Depth 3
leaq (%rdx,%rdx,2), %rax
movq %rax, 16(%rsp) # 8-byte Spill
leaq (%r14,%rax,4), %rdi
movq %r8, (%rsp) # 8-byte Spill
xorl %r9d, %r9d
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_18: # %.loopexit
# in Loop: Header=BB1_12 Depth=2
incq %r9
incq %r8
cmpq $3, %r9
je .LBB1_19
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_14 Depth 3
cmpq %r9, %rdx
je .LBB1_18
# %bb.13: # %.preheader182
# in Loop: Header=BB1_12 Depth=2
leaq (%rdi,%r9,4), %r10
leaq (%rdi,%r9,4), %rax
addq $12, %rax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%r9,4), %r15
movq $-6, %r12
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%r9,%rcx), %r13
xorl %ebp, %ebp
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_16: # in Loop: Header=BB1_14 Depth=3
leaq (%r9,%rbp), %rcx
addq %r12, %rcx
movq %r15, %r11
.LBB1_17: # in Loop: Header=BB1_14 Depth=3
movq %r13, %rsi
addq %rbp, %rsi
movss (%r10), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss (%r11), %xmm0
movss (%r14,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r14,%rcx,4), %xmm0
subss %xmm0, %xmm1
movss %xmm1, (%r14,%rsi,4)
movss (%r10), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss (%r11), %xmm0
movss (%rbx,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbx,%rcx,4), %xmm0
subss %xmm0, %xmm1
movss %xmm1, (%rbx,%rsi,4)
incq %rbp
addq $3, %r12
cmpq $3, %rbp
je .LBB1_18
.LBB1_14: # Parent Loop BB1_11 Depth=1
# Parent Loop BB1_12 Depth=2
# => This Inner Loop Header: Depth=3
cmpq $2, %rdx
je .LBB1_16
# %bb.15: # in Loop: Header=BB1_14 Depth=3
leaq (%r8,%rbp), %rcx
movq %rax, %r11
jmp .LBB1_17
.LBB1_20:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_21: # %.preheader181
# =>This Loop Header: Depth=1
# Child Loop BB1_22 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_22: # Parent Loop BB1_21 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r12
cmpq $3, %r12
jne .LBB1_22
# %bb.23: # in Loop: Header=BB1_21 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $12, %r14
cmpq $3, %r15
jne .LBB1_21
# %bb.24:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_25: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_26 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_26: # Parent Loop BB1_25 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r15
cmpq $3, %r15
jne .LBB1_26
# %bb.27: # in Loop: Header=BB1_25 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $12, %rbx
cmpq $3, %r14
jne .LBB1_25
# %bb.28:
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "It's not possible to allocate %s. \n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Memory has already been allocated %s.\n"
.size .L.str.1, 40
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "A"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "B"
.size .L.str.3, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " %f "
.size .L.str.5, 5
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.2,@object # @str.2
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.2:
.asciz "A ="
.size .Lstr.2, 4
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "B ="
.size .Lstr.3, 4
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00028700_00000000-6_matrix_inverse.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "It's not possible to allocate %s. \n"
.align 8
.LC1:
.string " Memory has already been allocated %s.\n"
.text
.globl _Z11checkMallocPvPKc
.type _Z11checkMallocPvPKc, @function
_Z11checkMallocPvPKc:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rsi, %rdx
testq %rdi, %rdi
je .L7
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z11checkMallocPvPKc, .-_Z11checkMallocPvPKc
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "A"
.LC3:
.string "B"
.LC4:
.string "A =\n"
.LC6:
.string " %f "
.LC7:
.string "\n"
.LC9:
.string "B =\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $12, %edi
call malloc@PLT
movq %rax, %rbx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _Z11checkMallocPvPKc
movl $12, %edi
call malloc@PLT
movq %rax, %rbp
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _Z11checkMallocPvPKc
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, (%rsp)
movq %rbx, %r12
movl $0, %r14d
leaq .LC6(%rip), %r13
leaq .LC7(%rip), %r15
movq %rbx, 8(%rsp)
.L9:
movl $0, %ebx
.L10:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC5(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rbx,4)
cvtss2sd %xmm0, %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L10
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r14d
addq $12, %r12
cmpl $9, %r14d
jne .L9
movq 8(%rsp), %rbx
movq $0, 4(%rbp)
movss .LC8(%rip), %xmm0
movss %xmm0, 0(%rbp)
movss %xmm0, 16(%rbp)
movss %xmm0, 32(%rbp)
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %r15
movq %rbp, %r12
movl $0, %r14d
leaq .LC6(%rip), %r13
movq %rbx, 8(%rsp)
.L12:
movl $0, %ebx
.L13:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L13
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r14d
addq $12, %r12
cmpl $9, %r14d
jne .L12
movq 8(%rsp), %rbx
movl $0, %ecx
movl $0, %r10d
movq %r15, 8(%rsp)
jmp .L14
.L16:
movslq %r9d, %rax
salq $2, %rax
leaq (%rbx,%rax), %r12
movslq %esi, %r8
movss 24(%rbx,%rdx,4), %xmm0
divss -24(%rbx,%rdx,4), %xmm0
mulss (%rbx,%r8,4), %xmm0
movss (%r12), %xmm1
subss %xmm0, %xmm1
movss %xmm1, (%r12)
addq %rbp, %rax
movss 24(%rbx,%rdx,4), %xmm0
divss -24(%rbx,%rdx,4), %xmm0
mulss 0(%rbp,%r8,4), %xmm0
movss (%rax), %xmm1
subss %xmm0, %xmm1
movss %xmm1, (%rax)
.L17:
addl $1, %edi
addl $1, %r9d
addl $4, %esi
cmpl %esi, %r13d
je .L15
.L18:
cmpl $1, %r10d
jg .L16
movslq %edi, %rax
salq $2, %rax
leaq (%rbx,%rax), %r12
leal 3(%rdi), %r8d
movslq %r8d, %r8
movss (%r15), %xmm0
divss (%r14), %xmm0
mulss (%rbx,%r8,4), %xmm0
movss (%r12), %xmm1
subss %xmm0, %xmm1
movss %xmm1, (%r12)
addq %rbp, %rax
movss (%r15), %xmm0
divss (%r14), %xmm0
mulss 0(%rbp,%r8,4), %xmm0
movss (%rax), %xmm1
subss %xmm0, %xmm1
movss %xmm1, (%rax)
jmp .L17
.L15:
addq $1, %rdx
addl $1, %r11d
cmpq $3, %rdx
je .L35
.L19:
cmpl %edx, %r10d
je .L15
movslq %r11d, %rax
leaq (%rbx,%rax,4), %r15
leal 3(%r11), %eax
cltq
leaq (%rbx,%rax,4), %r14
leal 6(%rdx), %r13d
leal -6(%rdx), %esi
movl %r13d, %r9d
movl %r11d, %edi
jmp .L18
.L35:
addl $1, %r10d
cmpl $3, %r10d
je .L36
.L14:
movl %ecx, %r11d
addl $3, %ecx
movl $0, %edx
jmp .L19
.L36:
movq 8(%rsp), %r15
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC6(%rip), %rbp
leaq .LC7(%rip), %r13
movq (%rsp), %r14
.L21:
movl $0, %ebx
.L22:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L22
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r12d
addq $12, %r14
cmpl $9, %r12d
jne .L21
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC6(%rip), %rbp
leaq .LC7(%rip), %r13
.L24:
movl $0, %ebx
.L25:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L25
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $3, %r12d
addq $12, %r15
cmpl $9, %r12d
jne .L24
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long -1721342362
.long 1101633945
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_inverse.hip"
.globl _Z11checkMallocPvPKc # -- Begin function _Z11checkMallocPvPKc
.p2align 4, 0x90
.type _Z11checkMallocPvPKc,@function
_Z11checkMallocPvPKc: # @_Z11checkMallocPvPKc
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
movl $.L.str, %eax
movl $.L.str.1, %edi
cmoveq %rax, %rdi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z11checkMallocPvPKc, .Lfunc_end0-_Z11checkMallocPvPKc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41a9999999666666 # double 214748364.69999999
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %_Z11checkMallocPvPKc.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $12, %edi
callq malloc
movq %rax, %r14
testq %rax, %rax
movl $.L.str, %r13d
movl $.L.str.1, %r15d
movl $.L.str.1, %edi
cmoveq %r13, %rdi
xorl %r12d, %r12d
movl $.L.str.2, %esi
xorl %eax, %eax
callq printf
movl $12, %edi
callq malloc
movq %rax, %rbx
testq %rax, %rax
cmoveq %r13, %r15
movl $.L.str.3, %esi
movq %r15, %rdi
xorl %eax, %eax
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq %r14, %r15
.p2align 4, 0x90
.LBB1_1: # %.preheader186
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%r13,4)
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r13
cmpq $3, %r13
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq $12, %r15
cmpq $3, %r12
jne .LBB1_1
# %bb.4:
movl $0, 8(%rbx)
movq $0, (%rbx)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax) # imm = 0x3F800000
addq $16, %rax
cmpq $48, %rax
jne .LBB1_5
# %bb.6:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB1_7: # %.preheader185
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r13
cmpq $3, %r13
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $12, %r12
cmpq $3, %r15
jne .LBB1_7
# %bb.10: # %.preheader184
leaq -24(%r14), %rax
movq %rax, 8(%rsp) # 8-byte Spill
movl $3, %r8d
xorl %edx, %edx
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_11 Depth=1
incq %rdx
movq (%rsp), %r8 # 8-byte Reload
addq $3, %r8
cmpq $3, %rdx
je .LBB1_20
.LBB1_11: # %.preheader183
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
# Child Loop BB1_14 Depth 3
leaq (%rdx,%rdx,2), %rax
movq %rax, 16(%rsp) # 8-byte Spill
leaq (%r14,%rax,4), %rdi
movq %r8, (%rsp) # 8-byte Spill
xorl %r9d, %r9d
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_18: # %.loopexit
# in Loop: Header=BB1_12 Depth=2
incq %r9
incq %r8
cmpq $3, %r9
je .LBB1_19
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_14 Depth 3
cmpq %r9, %rdx
je .LBB1_18
# %bb.13: # %.preheader182
# in Loop: Header=BB1_12 Depth=2
leaq (%rdi,%r9,4), %r10
leaq (%rdi,%r9,4), %rax
addq $12, %rax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%r9,4), %r15
movq $-6, %r12
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%r9,%rcx), %r13
xorl %ebp, %ebp
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_16: # in Loop: Header=BB1_14 Depth=3
leaq (%r9,%rbp), %rcx
addq %r12, %rcx
movq %r15, %r11
.LBB1_17: # in Loop: Header=BB1_14 Depth=3
movq %r13, %rsi
addq %rbp, %rsi
movss (%r10), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss (%r11), %xmm0
movss (%r14,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r14,%rcx,4), %xmm0
subss %xmm0, %xmm1
movss %xmm1, (%r14,%rsi,4)
movss (%r10), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss (%r11), %xmm0
movss (%rbx,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbx,%rcx,4), %xmm0
subss %xmm0, %xmm1
movss %xmm1, (%rbx,%rsi,4)
incq %rbp
addq $3, %r12
cmpq $3, %rbp
je .LBB1_18
.LBB1_14: # Parent Loop BB1_11 Depth=1
# Parent Loop BB1_12 Depth=2
# => This Inner Loop Header: Depth=3
cmpq $2, %rdx
je .LBB1_16
# %bb.15: # in Loop: Header=BB1_14 Depth=3
leaq (%r8,%rbp), %rcx
movq %rax, %r11
jmp .LBB1_17
.LBB1_20:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_21: # %.preheader181
# =>This Loop Header: Depth=1
# Child Loop BB1_22 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_22: # Parent Loop BB1_21 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r12
cmpq $3, %r12
jne .LBB1_22
# %bb.23: # in Loop: Header=BB1_21 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $12, %r14
cmpq $3, %r15
jne .LBB1_21
# %bb.24:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_25: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_26 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_26: # Parent Loop BB1_25 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
incq %r15
cmpq $3, %r15
jne .LBB1_26
# %bb.27: # in Loop: Header=BB1_25 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $12, %rbx
cmpq $3, %r14
jne .LBB1_25
# %bb.28:
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "It's not possible to allocate %s. \n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Memory has already been allocated %s.\n"
.size .L.str.1, 40
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "A"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "B"
.size .L.str.3, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " %f "
.size .L.str.5, 5
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.2,@object # @str.2
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.2:
.asciz "A ="
.size .Lstr.2, 4
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "B ="
.size .Lstr.3, 4
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*****************************************************************************
*
* String Pattern Matching - Serial Implementation
*
* Reference: http://people.maths.ox.ac.uk/~gilesm/cuda/
*
*****************************************************************************/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// Includes CUDA
#include <cuda_runtime.h>
#define LINEWIDTH 20
// citation: https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define checkCudaErrors(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void matchPattern_CPU(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
for (int l=0; l<length; l++)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[l];
else
word = (text[l]>>(8*offset)) + (text[l+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
matches[w] += (word==words[w]);
}
}
}
}
__global__ void matchPattern_gpu_1(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < length)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[idx];
else
word = (text[idx]>>(8*offset)) + (text[idx+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
if (word==words[w]){
atomicAdd(&matches[w],1);
}
}
}
}
}
int main(int argc, const char **argv)
{
int length, len, nwords=5, matches[nwords];
char *ctext, keywords[nwords][LINEWIDTH], *line;
line = (char*) malloc(sizeof(char)*LINEWIDTH);
unsigned int *text, *words;
memset(matches, 0, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile)
{ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = nwords;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--)
{
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen("./data/small.txt","r");
if (!fp)
{ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
ctext = (char *) malloc(length+4);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
printf("Length : %d\n", length );
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
words = (unsigned int *) malloc(nwords*sizeof(unsigned int));
for (int w=0; w<nwords; w++)
{
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
// CPU execution
const clock_t begin_time = clock();
matchPattern_CPU(text, words, matches, nwords, len);
float runTime = (float)( clock() - begin_time ) / CLOCKS_PER_SEC;
printf("Time for matching keywords: %fs\n\n", runTime);
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < nwords; ++i)
printf("%s\t |\t%d\n", keywords[i], matches[i]);
// GPU execution
unsigned int *d_text; unsigned int *d_words; int *d_matches;
int *h_matches;
h_matches = (int *)malloc(nwords*sizeof(int));
cudaMalloc((void**)&d_words, nwords*sizeof(unsigned int));
cudaMalloc((void**)&d_matches, nwords*sizeof(int));
cudaMalloc((void**)&d_text, sizeof(char)*strlen(ctext));
cudaMemcpy(d_text, text, sizeof(char)*strlen(ctext), cudaMemcpyHostToDevice);
cudaMemcpy(d_words, words, nwords*sizeof(unsigned int), cudaMemcpyHostToDevice);
matchPattern_gpu_1<<<len/32,32>>>(d_text, d_words, d_matches, nwords, len);
checkCudaErrors(cudaPeekAtLastError());
checkCudaErrors(cudaMemcpy(h_matches, d_matches, nwords*sizeof(int), cudaMemcpyDeviceToHost));
for(int i = 0; i<nwords; i++) {
if(matches[i] != h_matches[i]) {
printf("WRONG OUTPUT:\t %s\t|\t%d\n", keywords[i], h_matches[i]);
}
}
free(ctext);
free(words);
cudaFree(d_words);
cudaFree(d_matches);
cudaFree(d_text);
} | .file "tmpxft_00132190_00000000-6_pattern_CPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z16matchPattern_CPUPjS_Piii
.type _Z16matchPattern_CPUPjS_Piii, @function
_Z16matchPattern_CPUPjS_Piii:
.LFB2058:
.cfi_startproc
endbr64
testl %r8d, %r8d
jle .L24
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %r9
movl %ecx, %r11d
movq %rdi, %r10
movslq %r8d, %r8
leaq (%rdi,%r8,4), %rbx
movslq %ecx, %rdi
salq $2, %rdi
jmp .L13
.L29:
movl (%r10), %esi
testl %r11d, %r11d
jle .L27
.L15:
movl $0, %eax
.L18:
cmpl %esi, (%r9,%rax)
sete %cl
movzbl %cl, %ecx
addl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %rdi, %rax
jne .L18
.L17:
addl $1, %r8d
cmpl $4, %r8d
je .L28
.L20:
testl %r8d, %r8d
je .L29
movl %r8d, %eax
negl %eax
leal 32(,%rax,8), %ecx
movl 4(%r10), %esi
sall %cl, %esi
leal 0(,%r8,8), %ecx
movl (%r10), %eax
shrl %cl, %eax
addl %eax, %esi
testl %r11d, %r11d
jg .L15
jmp .L17
.L28:
addq $4, %r10
cmpq %rbx, %r10
je .L11
.L13:
movl $0, %r8d
jmp .L20
.L27:
addl $1, %r8d
jmp .L20
.L11:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore 3
ret
.cfi_endproc
.LFE2058:
.size _Z16matchPattern_CPUPjS_Piii, .-_Z16matchPattern_CPUPjS_Piii
.globl _Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii
.type _Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii, @function
_Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18matchPattern_gpu_1PjS_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii, .-_Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii
.globl _Z18matchPattern_gpu_1PjS_Piii
.type _Z18matchPattern_gpu_1PjS_Piii, @function
_Z18matchPattern_gpu_1PjS_Piii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18matchPattern_gpu_1PjS_Piii, .-_Z18matchPattern_gpu_1PjS_Piii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "./data/keywords.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "keywords.txt: File not found.\n"
.section .rodata.str1.1
.LC4:
.string "./data/small.txt"
.LC5:
.string "Unable to open the file.\n"
.LC6:
.string "Length : %d\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Time for matching keywords: %fs\n\n"
.section .rodata.str1.1
.LC9:
.string "Printing Matches:\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Word\t |\tNumber of Matches\n===================================\n"
.section .rodata.str1.1
.LC11:
.string "%s\t |\t%d\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "/home/ubuntu/Datasets/stackv2/train-structured/sedflix/cuda_pattern_matching/master/pattern_CPU.cu"
.section .rodata.str1.1
.LC13:
.string "WRONG OUTPUT:\t %s\t|\t%d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $232, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movl $20, %edi
call malloc@PLT
movq %rax, 16(%rsp)
pxor %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movl $0, 96(%rsp)
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L60
movq %rax, %rbp
movq $20, 24(%rsp)
movl $0, %ebx
leaq 24(%rsp), %r12
.L41:
leaq 16(%rsp), %rdi
movq %rbp, %rcx
movl $10, %edx
movq %r12, %rsi
call __getdelim@PLT
cmpq $-1, %rax
je .L40
cmpq $100, %rbx
je .L40
movl $100, %ecx
cmpq %rcx, %rbx
cmovnb %rbx, %rcx
subq %rbx, %rcx
leaq 112(%rsp,%rbx), %rdi
movl $8, %edx
movq 16(%rsp), %rsi
call __strncpy_chk@PLT
movb $0, 116(%rsp,%rbx)
addq $20, %rbx
jmp .L41
.L60:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L40:
movq %rbp, %rdi
call fclose@PLT
leaq .LC1(%rip), %rsi
leaq .LC4(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L61
movl $0, %ebx
jmp .L42
.L61:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L43:
addl $1, %ebx
.L42:
movq %r12, %rdi
call getc@PLT
cmpl $-1, %eax
jne .L43
leal 4(%rbx), %edi
movslq %edi, %rdi
call malloc@PLT
movq %rax, %r13
movq %r12, %rdi
call rewind@PLT
testl %ebx, %ebx
jle .L44
movq %r13, %rbp
movslq %ebx, %r14
addq %r13, %r14
.L45:
movq %r12, %rdi
call getc@PLT
movb %al, 0(%rbp)
addq $1, %rbp
cmpq %r14, %rbp
jne .L45
.L44:
movslq %ebx, %rdx
leaq 0(%r13,%rdx), %rax
leaq 4(%r13,%rdx), %rdx
.L46:
movb $32, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L46
movq %r12, %rdi
call fclose@PLT
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 3(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $2, %eax
movl %eax, 12(%rsp)
movl $20, %edi
call malloc@PLT
movq %rax, (%rsp)
leaq 112(%rsp), %r15
movq %rax, %rcx
leaq 212(%rsp), %r14
movq %r15, %rdx
.L47:
movsbl 3(%rdx), %eax
sall $8, %eax
movsbl 2(%rdx), %esi
addl %esi, %eax
sall $8, %eax
movsbl 1(%rdx), %esi
addl %esi, %eax
sall $8, %eax
movsbl (%rdx), %esi
addl %esi, %eax
movl %eax, (%rcx)
addq $20, %rdx
addq $4, %rcx
cmpq %r14, %rdx
jne .L47
call clock@PLT
movq %rax, %rbp
leaq 80(%rsp), %r12
movl 12(%rsp), %r8d
movl $5, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq %r13, %rdi
call _Z16matchPattern_CPUPjS_Piii
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rbp
.L48:
movl (%r12), %ecx
movq %rbp, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r12
addq $20, %rbp
cmpq %r14, %rbp
jne .L48
movl $20, %edi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
movq %r13, %rdi
call strlen@PLT
movq %rax, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movq %r13, %rdi
call strlen@PLT
movq %rax, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
leal 127(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $7, %eax
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L49:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $162, %edx
leaq .LC12(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $20, %edx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $163, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %ebx
leaq .LC13(%rip), %r12
jmp .L51
.L62:
movl 12(%rsp), %r8d
movl $5, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii
jmp .L49
.L50:
addq $4, %rbx
cmpq $20, %rbx
je .L63
.L51:
movl 0(%rbp,%rbx), %ecx
cmpl %ecx, 80(%rsp,%rbx)
je .L50
leaq (%rbx,%rbx,4), %rdx
addq %r15, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L50
.L63:
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC15:
.string "_Z18matchPattern_gpu_1PjS_Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matchPattern_gpu_1PjS_Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*****************************************************************************
*
* String Pattern Matching - Serial Implementation
*
* Reference: http://people.maths.ox.ac.uk/~gilesm/cuda/
*
*****************************************************************************/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// Includes CUDA
#include <cuda_runtime.h>
#define LINEWIDTH 20
// citation: https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define checkCudaErrors(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void matchPattern_CPU(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
for (int l=0; l<length; l++)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[l];
else
word = (text[l]>>(8*offset)) + (text[l+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
matches[w] += (word==words[w]);
}
}
}
}
__global__ void matchPattern_gpu_1(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < length)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[idx];
else
word = (text[idx]>>(8*offset)) + (text[idx+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
if (word==words[w]){
atomicAdd(&matches[w],1);
}
}
}
}
}
int main(int argc, const char **argv)
{
int length, len, nwords=5, matches[nwords];
char *ctext, keywords[nwords][LINEWIDTH], *line;
line = (char*) malloc(sizeof(char)*LINEWIDTH);
unsigned int *text, *words;
memset(matches, 0, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile)
{ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = nwords;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--)
{
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen("./data/small.txt","r");
if (!fp)
{ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
ctext = (char *) malloc(length+4);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
printf("Length : %d\n", length );
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
words = (unsigned int *) malloc(nwords*sizeof(unsigned int));
for (int w=0; w<nwords; w++)
{
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
// CPU execution
const clock_t begin_time = clock();
matchPattern_CPU(text, words, matches, nwords, len);
float runTime = (float)( clock() - begin_time ) / CLOCKS_PER_SEC;
printf("Time for matching keywords: %fs\n\n", runTime);
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < nwords; ++i)
printf("%s\t |\t%d\n", keywords[i], matches[i]);
// GPU execution
unsigned int *d_text; unsigned int *d_words; int *d_matches;
int *h_matches;
h_matches = (int *)malloc(nwords*sizeof(int));
cudaMalloc((void**)&d_words, nwords*sizeof(unsigned int));
cudaMalloc((void**)&d_matches, nwords*sizeof(int));
cudaMalloc((void**)&d_text, sizeof(char)*strlen(ctext));
cudaMemcpy(d_text, text, sizeof(char)*strlen(ctext), cudaMemcpyHostToDevice);
cudaMemcpy(d_words, words, nwords*sizeof(unsigned int), cudaMemcpyHostToDevice);
matchPattern_gpu_1<<<len/32,32>>>(d_text, d_words, d_matches, nwords, len);
checkCudaErrors(cudaPeekAtLastError());
checkCudaErrors(cudaMemcpy(h_matches, d_matches, nwords*sizeof(int), cudaMemcpyDeviceToHost));
for(int i = 0; i<nwords; i++) {
if(matches[i] != h_matches[i]) {
printf("WRONG OUTPUT:\t %s\t|\t%d\n", keywords[i], h_matches[i]);
}
}
free(ctext);
free(words);
cudaFree(d_words);
cudaFree(d_matches);
cudaFree(d_text);
} | /*****************************************************************************
*
* String Pattern Matching - Serial Implementation
*
* Reference: http://people.maths.ox.ac.uk/~gilesm/cuda/
*
*****************************************************************************/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// Includes CUDA
#include <hip/hip_runtime.h>
#define LINEWIDTH 20
// citation: https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define checkCudaErrors(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void matchPattern_CPU(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
for (int l=0; l<length; l++)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[l];
else
word = (text[l]>>(8*offset)) + (text[l+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
matches[w] += (word==words[w]);
}
}
}
}
__global__ void matchPattern_gpu_1(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < length)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[idx];
else
word = (text[idx]>>(8*offset)) + (text[idx+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
if (word==words[w]){
atomicAdd(&matches[w],1);
}
}
}
}
}
int main(int argc, const char **argv)
{
int length, len, nwords=5, matches[nwords];
char *ctext, keywords[nwords][LINEWIDTH], *line;
line = (char*) malloc(sizeof(char)*LINEWIDTH);
unsigned int *text, *words;
memset(matches, 0, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile)
{ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = nwords;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--)
{
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen("./data/small.txt","r");
if (!fp)
{ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
ctext = (char *) malloc(length+4);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
printf("Length : %d\n", length );
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
words = (unsigned int *) malloc(nwords*sizeof(unsigned int));
for (int w=0; w<nwords; w++)
{
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
// CPU execution
const clock_t begin_time = clock();
matchPattern_CPU(text, words, matches, nwords, len);
float runTime = (float)( clock() - begin_time ) / CLOCKS_PER_SEC;
printf("Time for matching keywords: %fs\n\n", runTime);
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < nwords; ++i)
printf("%s\t |\t%d\n", keywords[i], matches[i]);
// GPU execution
unsigned int *d_text; unsigned int *d_words; int *d_matches;
int *h_matches;
h_matches = (int *)malloc(nwords*sizeof(int));
hipMalloc((void**)&d_words, nwords*sizeof(unsigned int));
hipMalloc((void**)&d_matches, nwords*sizeof(int));
hipMalloc((void**)&d_text, sizeof(char)*strlen(ctext));
hipMemcpy(d_text, text, sizeof(char)*strlen(ctext), hipMemcpyHostToDevice);
hipMemcpy(d_words, words, nwords*sizeof(unsigned int), hipMemcpyHostToDevice);
matchPattern_gpu_1<<<len/32,32>>>(d_text, d_words, d_matches, nwords, len);
checkCudaErrors(hipPeekAtLastError());
checkCudaErrors(hipMemcpy(h_matches, d_matches, nwords*sizeof(int), hipMemcpyDeviceToHost));
for(int i = 0; i<nwords; i++) {
if(matches[i] != h_matches[i]) {
printf("WRONG OUTPUT:\t %s\t|\t%d\n", keywords[i], h_matches[i]);
}
}
free(ctext);
free(words);
hipFree(d_words);
hipFree(d_matches);
hipFree(d_text);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*****************************************************************************
*
* String Pattern Matching - Serial Implementation
*
* Reference: http://people.maths.ox.ac.uk/~gilesm/cuda/
*
*****************************************************************************/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// Includes CUDA
#include <hip/hip_runtime.h>
#define LINEWIDTH 20
// citation: https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define checkCudaErrors(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void matchPattern_CPU(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
for (int l=0; l<length; l++)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[l];
else
word = (text[l]>>(8*offset)) + (text[l+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
matches[w] += (word==words[w]);
}
}
}
}
__global__ void matchPattern_gpu_1(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < length)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[idx];
else
word = (text[idx]>>(8*offset)) + (text[idx+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
if (word==words[w]){
atomicAdd(&matches[w],1);
}
}
}
}
}
int main(int argc, const char **argv)
{
int length, len, nwords=5, matches[nwords];
char *ctext, keywords[nwords][LINEWIDTH], *line;
line = (char*) malloc(sizeof(char)*LINEWIDTH);
unsigned int *text, *words;
memset(matches, 0, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile)
{ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = nwords;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--)
{
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen("./data/small.txt","r");
if (!fp)
{ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
ctext = (char *) malloc(length+4);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
printf("Length : %d\n", length );
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
words = (unsigned int *) malloc(nwords*sizeof(unsigned int));
for (int w=0; w<nwords; w++)
{
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
// CPU execution
const clock_t begin_time = clock();
matchPattern_CPU(text, words, matches, nwords, len);
float runTime = (float)( clock() - begin_time ) / CLOCKS_PER_SEC;
printf("Time for matching keywords: %fs\n\n", runTime);
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < nwords; ++i)
printf("%s\t |\t%d\n", keywords[i], matches[i]);
// GPU execution
unsigned int *d_text; unsigned int *d_words; int *d_matches;
int *h_matches;
h_matches = (int *)malloc(nwords*sizeof(int));
hipMalloc((void**)&d_words, nwords*sizeof(unsigned int));
hipMalloc((void**)&d_matches, nwords*sizeof(int));
hipMalloc((void**)&d_text, sizeof(char)*strlen(ctext));
hipMemcpy(d_text, text, sizeof(char)*strlen(ctext), hipMemcpyHostToDevice);
hipMemcpy(d_words, words, nwords*sizeof(unsigned int), hipMemcpyHostToDevice);
matchPattern_gpu_1<<<len/32,32>>>(d_text, d_words, d_matches, nwords, len);
checkCudaErrors(hipPeekAtLastError());
checkCudaErrors(hipMemcpy(h_matches, d_matches, nwords*sizeof(int), hipMemcpyDeviceToHost));
for(int i = 0; i<nwords; i++) {
if(matches[i] != h_matches[i]) {
printf("WRONG OUTPUT:\t %s\t|\t%d\n", keywords[i], h_matches[i]);
}
}
free(ctext);
free(words);
hipFree(d_words);
hipFree(d_matches);
hipFree(d_text);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matchPattern_gpu_1PjS_Piii
.globl _Z18matchPattern_gpu_1PjS_Piii
.p2align 8
.type _Z18matchPattern_gpu_1PjS_Piii,@function
_Z18matchPattern_gpu_1PjS_Piii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_12
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s8, 0
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_cselect_b32 s9, -1, 0
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, 4
s_cbranch_scc1 .LBB0_12
.LBB0_3:
s_cmp_lg_u32 s10, 0
s_cbranch_scc0 .LBB0_11
global_load_b64 v[3:4], v[0:1], off
s_lshl_b32 s2, s10, 3
s_waitcnt vmcnt(0)
v_lshrrev_b32_e32 v3, s2, v3
s_sub_i32 s2, 32, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_lshl_add_u32 v3, v4, s2, v3
s_cbranch_execnz .LBB0_6
.LBB0_5:
global_load_b32 v3, v[0:1], off
.LBB0_6:
s_mov_b64 s[2:3], s[0:1]
s_and_not1_b32 vcc_lo, exec_lo, s9
s_mov_b64 s[4:5], s[6:7]
s_mov_b32 s11, s8
s_cbranch_vccz .LBB0_8
s_branch .LBB0_2
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s12
s_add_i32 s11, s11, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s11, 0
s_cbranch_scc1 .LBB0_2
.LBB0_8:
global_load_b32 v4, v2, s[4:5]
s_mov_b32 s12, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v3, v4
s_cbranch_execz .LBB0_7
s_mov_b32 s13, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v4, s13, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_and_b32 s14, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s14
s_cbranch_execz .LBB0_7
s_bcnt1_i32_b32 s13, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v4, s13
global_atomic_add_u32 v2, v4, s[2:3]
s_branch .LBB0_7
.LBB0_11:
s_branch .LBB0_5
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18matchPattern_gpu_1PjS_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18matchPattern_gpu_1PjS_Piii, .Lfunc_end0-_Z18matchPattern_gpu_1PjS_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18matchPattern_gpu_1PjS_Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18matchPattern_gpu_1PjS_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*****************************************************************************
*
* String Pattern Matching - Serial Implementation
*
* Reference: http://people.maths.ox.ac.uk/~gilesm/cuda/
*
*****************************************************************************/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// Includes CUDA
#include <hip/hip_runtime.h>
#define LINEWIDTH 20
// citation: https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define checkCudaErrors(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void matchPattern_CPU(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
for (int l=0; l<length; l++)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[l];
else
word = (text[l]>>(8*offset)) + (text[l+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
matches[w] += (word==words[w]);
}
}
}
}
__global__ void matchPattern_gpu_1(unsigned int *text, unsigned int *words, int *matches, int nwords, int length)
{
unsigned int word;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < length)
{
for (int offset=0; offset<4; offset++)
{
if (offset==0)
word = text[idx];
else
word = (text[idx]>>(8*offset)) + (text[idx+1]<<(32-8*offset));
for (int w=0; w<nwords; w++){
if (word==words[w]){
atomicAdd(&matches[w],1);
}
}
}
}
}
int main(int argc, const char **argv)
{
int length, len, nwords=5, matches[nwords];
char *ctext, keywords[nwords][LINEWIDTH], *line;
line = (char*) malloc(sizeof(char)*LINEWIDTH);
unsigned int *text, *words;
memset(matches, 0, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile)
{ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = nwords;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--)
{
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen("./data/small.txt","r");
if (!fp)
{ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
ctext = (char *) malloc(length+4);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
printf("Length : %d\n", length );
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
words = (unsigned int *) malloc(nwords*sizeof(unsigned int));
for (int w=0; w<nwords; w++)
{
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
// CPU execution
const clock_t begin_time = clock();
matchPattern_CPU(text, words, matches, nwords, len);
float runTime = (float)( clock() - begin_time ) / CLOCKS_PER_SEC;
printf("Time for matching keywords: %fs\n\n", runTime);
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < nwords; ++i)
printf("%s\t |\t%d\n", keywords[i], matches[i]);
// GPU execution
unsigned int *d_text; unsigned int *d_words; int *d_matches;
int *h_matches;
h_matches = (int *)malloc(nwords*sizeof(int));
hipMalloc((void**)&d_words, nwords*sizeof(unsigned int));
hipMalloc((void**)&d_matches, nwords*sizeof(int));
hipMalloc((void**)&d_text, sizeof(char)*strlen(ctext));
hipMemcpy(d_text, text, sizeof(char)*strlen(ctext), hipMemcpyHostToDevice);
hipMemcpy(d_words, words, nwords*sizeof(unsigned int), hipMemcpyHostToDevice);
matchPattern_gpu_1<<<len/32,32>>>(d_text, d_words, d_matches, nwords, len);
checkCudaErrors(hipPeekAtLastError());
checkCudaErrors(hipMemcpy(h_matches, d_matches, nwords*sizeof(int), hipMemcpyDeviceToHost));
for(int i = 0; i<nwords; i++) {
if(matches[i] != h_matches[i]) {
printf("WRONG OUTPUT:\t %s\t|\t%d\n", keywords[i], h_matches[i]);
}
}
free(ctext);
free(words);
hipFree(d_words);
hipFree(d_matches);
hipFree(d_text);
} | .text
.file "pattern_CPU.hip"
.globl _Z16matchPattern_CPUPjS_Piii # -- Begin function _Z16matchPattern_CPUPjS_Piii
.p2align 4, 0x90
.type _Z16matchPattern_CPUPjS_Piii,@function
_Z16matchPattern_CPUPjS_Piii: # @_Z16matchPattern_CPUPjS_Piii
.cfi_startproc
# %bb.0:
testl %r8d, %r8d
jle .LBB0_12
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
movl %r8d, %r8d
movl %ecx, %r9d
xorl %r10d, %r10d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_10: # in Loop: Header=BB0_2 Depth=1
incq %r10
cmpq %r8, %r10
je .LBB0_11
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_8 Depth 3
xorl %r11d, %r11d
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_9: # %._crit_edge
# in Loop: Header=BB0_3 Depth=2
incl %r11d
cmpl $4, %r11d
je .LBB0_10
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_8 Depth 3
testl %r11d, %r11d
je .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=2
leal (,%r11,8), %ecx
movl (%rdi,%r10,4), %ebp
shrl %cl, %ebp
movl 4(%rdi,%r10,4), %ebx
negb %cl
# kill: def $cl killed $cl killed $ecx
shll %cl, %ebx
addl %ebp, %ebx
testl %eax, %eax
jg .LBB0_7
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_3 Depth=2
movl (%rdi,%r10,4), %ebx
testl %eax, %eax
jle .LBB0_9
.LBB0_7: # %.lr.ph.preheader
# in Loop: Header=BB0_3 Depth=2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_8: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
xorl %ebp, %ebp
cmpl (%rsi,%rcx,4), %ebx
sete %bpl
addl %ebp, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %r9
jne .LBB0_8
jmp .LBB0_9
.LBB0_11:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
.LBB0_12: # %._crit_edge27
retq
.Lfunc_end0:
.size _Z16matchPattern_CPUPjS_Piii, .Lfunc_end0-_Z16matchPattern_CPUPjS_Piii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__matchPattern_gpu_1PjS_Piii # -- Begin function _Z33__device_stub__matchPattern_gpu_1PjS_Piii
.p2align 4, 0x90
.type _Z33__device_stub__matchPattern_gpu_1PjS_Piii,@function
_Z33__device_stub__matchPattern_gpu_1PjS_Piii: # @_Z33__device_stub__matchPattern_gpu_1PjS_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18matchPattern_gpu_1PjS_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z33__device_stub__matchPattern_gpu_1PjS_Piii, .Lfunc_end1-_Z33__device_stub__matchPattern_gpu_1PjS_Piii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $20, %edi
callq malloc
movq %rax, 24(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movl $0, 64(%rsp)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB2_1
# %bb.3:
movq %rax, %rbx
movq $20, 40(%rsp)
leaq 24(%rsp), %rdi
leaq 40(%rsp), %rsi
movl $10, %edx
movq %rax, %rcx
callq __getdelim
cmpq $-1, %rax
je .LBB2_7
# %bb.4: # %.lr.ph.preheader
xorl %r12d, %r12d
leaq 24(%rsp), %r14
leaq 40(%rsp), %r15
.p2align 4, 0x90
.LBB2_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq (%rsp,%r12), %rdi
addq $192, %rdi
movq 24(%rsp), %rsi
movl $8, %edx
callq strncpy
movb $0, 196(%rsp,%r12)
movq %r14, %rdi
movq %r15, %rsi
movl $10, %edx
movq %rbx, %rcx
callq __getdelim
cmpq $-1, %rax
je .LBB2_7
# %bb.6: # %.lr.ph
# in Loop: Header=BB2_5 Depth=1
leaq 20(%r12), %rax
cmpl $80, %r12d
movq %rax, %r12
jne .LBB2_5
.LBB2_7: # %.critedge
movq %rbx, %rdi
callq fclose
movl $.L.str.3, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB2_38
# %bb.8: # %.preheader104.preheader
movq %rax, %r14
movq $-1, %r15
.p2align 4, 0x90
.LBB2_9: # %.preheader104
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq getc
incq %r15
cmpl $-1, %eax
jne .LBB2_9
# %bb.10:
leaq 4(%r15), %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq rewind
testl %r15d, %r15d
je .LBB2_13
# %bb.11: # %.lr.ph109.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_12: # %.lr.ph109
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq getc
movb %al, (%rbx,%r12)
incq %r12
cmpq %r12, %r15
jne .LBB2_12
.LBB2_13: # %.preheader
movl $538976288, (%rbx,%r15) # imm = 0x20202020
movq %r14, %rdi
callq fclose
xorl %r12d, %r12d
movl $.L.str.5, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $20, %edi
callq malloc
movq %rax, %r14
leaq 195(%rsp), %rax
.p2align 4, 0x90
.LBB2_14: # =>This Inner Loop Header: Depth=1
movsbl -3(%rax), %ecx
movsbl -2(%rax), %edx
shll $8, %edx
addl %ecx, %edx
movsbl -1(%rax), %ecx
shll $16, %ecx
movzbl (%rax), %esi
shll $24, %esi
addl %ecx, %esi
addl %edx, %esi
movl %esi, (%r14,%r12,4)
incq %r12
addq $20, %rax
cmpq $5, %r12
jne .LBB2_14
# %bb.15:
movl %r15d, %ebp
shrl $2, %ebp
callq clock
movq %rax, %r12
cmpl $4, %r15d
jb .LBB2_24
# %bb.16: # %.preheader.lr.ph.i
movl %ebp, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_17: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
# Child Loop BB2_21 Depth 3
movl (%rbx,%rdx,4), %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_18: # Parent Loop BB2_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_21 Depth 3
movl %esi, %r8d
testl %edi, %edi
je .LBB2_20
# %bb.19: # in Loop: Header=BB2_18 Depth=2
leal (,%rdi,8), %ecx
movl %esi, %r9d
shrl %cl, %r9d
movl 4(%rbx,%rdx,4), %r8d
negb %cl
# kill: def $cl killed $cl killed $ecx
shll %cl, %r8d
addl %r9d, %r8d
.LBB2_20: # in Loop: Header=BB2_18 Depth=2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_21: # %.lr.ph.i
# Parent Loop BB2_17 Depth=1
# Parent Loop BB2_18 Depth=2
# => This Inner Loop Header: Depth=3
xorl %r9d, %r9d
cmpl (%r14,%rcx,4), %r8d
sete %r9b
addl %r9d, 48(%rsp,%rcx,4)
incq %rcx
cmpq $5, %rcx
jne .LBB2_21
# %bb.22: # %._crit_edge.i
# in Loop: Header=BB2_18 Depth=2
incl %edi
cmpl $4, %edi
jne .LBB2_18
# %bb.23: # in Loop: Header=BB2_17 Depth=1
incq %rdx
cmpq %rax, %rdx
jne .LBB2_17
.LBB2_24: # %_Z16matchPattern_CPUPjS_Piii.exit
callq clock
subq %r12, %rax
cvtsi2ss %rax, %xmm0
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
leaq 192(%rsp), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_25: # =>This Inner Loop Header: Depth=1
movl 48(%rsp,%r13,4), %edx
movl $.L.str.9, %edi
movq %r12, %rsi
xorl %eax, %eax
callq printf
incq %r13
addq $20, %r12
cmpq $5, %r13
jne .LBB2_25
# %bb.26:
movl $20, %edi
callq malloc
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq %rsp, %rdi
movl $20, %esi
callq hipMalloc
movq %rbx, %rdi
callq strlen
leaq 16(%rsp), %rdi
movq %rax, %rsi
callq hipMalloc
movq 16(%rsp), %r13
movq %rbx, %rdi
callq strlen
movq %r13, %rdi
movq %rbx, %rsi
movq %rax, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $20, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
shrl $7, %r15d
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r15
orq $32, %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_28
# %bb.27:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $5, 36(%rsp)
movl %ebp, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z18matchPattern_gpu_1PjS_Piii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_28:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB2_29
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit
movq (%rsp), %rsi
movl $20, %edx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_37
# %bb.32: # %_Z9gpuAssert10hipError_tPKcib.exit99.preheader.preheader
leaq 192(%rsp), %r15
xorl %r13d, %r13d
jmp .LBB2_33
.p2align 4, 0x90
.LBB2_35: # %_Z9gpuAssert10hipError_tPKcib.exit99
# in Loop: Header=BB2_33 Depth=1
incq %r13
addq $20, %r15
cmpq $5, %r13
je .LBB2_36
.LBB2_33: # %_Z9gpuAssert10hipError_tPKcib.exit99.preheader
# =>This Inner Loop Header: Depth=1
movl (%r12,%r13,4), %edx
cmpl %edx, 48(%rsp,%r13,4)
je .LBB2_35
# %bb.34: # in Loop: Header=BB2_33 Depth=1
movl $.L.str.11, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
jmp .LBB2_35
.LBB2_36:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 352
movl $.Lstr, %edi
jmp .LBB2_2
.LBB2_38:
movl $.Lstr.1, %edi
.LBB2_2:
callq puts@PLT
xorl %edi, %edi
callq exit
.LBB2_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str.10, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $162, %r8d
jmp .LBB2_30
.LBB2_37:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str.10, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $163, %r8d
.LBB2_30:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matchPattern_gpu_1PjS_Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18matchPattern_gpu_1PjS_Piii,@object # @_Z18matchPattern_gpu_1PjS_Piii
.section .rodata,"a",@progbits
.globl _Z18matchPattern_gpu_1PjS_Piii
.p2align 3, 0x0
_Z18matchPattern_gpu_1PjS_Piii:
.quad _Z33__device_stub__matchPattern_gpu_1PjS_Piii
.size _Z18matchPattern_gpu_1PjS_Piii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "./data/keywords.txt"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "./data/small.txt"
.size .L.str.3, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Length : %d\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time for matching keywords: %fs\n\n"
.size .L.str.6, 34
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%s\t |\t%d\n"
.size .L.str.9, 11
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/sedflix/cuda_pattern_matching/master/pattern_CPU.hip"
.size .L.str.10, 110
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "WRONG OUTPUT:\t %s\t|\t%d\n"
.size .L.str.11, 24
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.12, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18matchPattern_gpu_1PjS_Piii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "keywords.txt: File not found."
.size .Lstr, 30
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Unable to open the file."
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing Matches:"
.size .Lstr.2, 18
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Word\t |\tNumber of Matches\n==================================="
.size .Lstr.3, 63
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matchPattern_gpu_1PjS_Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matchPattern_gpu_1PjS_Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00132190_00000000-6_pattern_CPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z16matchPattern_CPUPjS_Piii
.type _Z16matchPattern_CPUPjS_Piii, @function
_Z16matchPattern_CPUPjS_Piii:
.LFB2058:
.cfi_startproc
endbr64
testl %r8d, %r8d
jle .L24
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %r9
movl %ecx, %r11d
movq %rdi, %r10
movslq %r8d, %r8
leaq (%rdi,%r8,4), %rbx
movslq %ecx, %rdi
salq $2, %rdi
jmp .L13
.L29:
movl (%r10), %esi
testl %r11d, %r11d
jle .L27
.L15:
movl $0, %eax
.L18:
cmpl %esi, (%r9,%rax)
sete %cl
movzbl %cl, %ecx
addl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %rdi, %rax
jne .L18
.L17:
addl $1, %r8d
cmpl $4, %r8d
je .L28
.L20:
testl %r8d, %r8d
je .L29
movl %r8d, %eax
negl %eax
leal 32(,%rax,8), %ecx
movl 4(%r10), %esi
sall %cl, %esi
leal 0(,%r8,8), %ecx
movl (%r10), %eax
shrl %cl, %eax
addl %eax, %esi
testl %r11d, %r11d
jg .L15
jmp .L17
.L28:
addq $4, %r10
cmpq %rbx, %r10
je .L11
.L13:
movl $0, %r8d
jmp .L20
.L27:
addl $1, %r8d
jmp .L20
.L11:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore 3
ret
.cfi_endproc
.LFE2058:
.size _Z16matchPattern_CPUPjS_Piii, .-_Z16matchPattern_CPUPjS_Piii
.globl _Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii
.type _Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii, @function
_Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18matchPattern_gpu_1PjS_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii, .-_Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii
.globl _Z18matchPattern_gpu_1PjS_Piii
.type _Z18matchPattern_gpu_1PjS_Piii, @function
_Z18matchPattern_gpu_1PjS_Piii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18matchPattern_gpu_1PjS_Piii, .-_Z18matchPattern_gpu_1PjS_Piii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "./data/keywords.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "keywords.txt: File not found.\n"
.section .rodata.str1.1
.LC4:
.string "./data/small.txt"
.LC5:
.string "Unable to open the file.\n"
.LC6:
.string "Length : %d\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Time for matching keywords: %fs\n\n"
.section .rodata.str1.1
.LC9:
.string "Printing Matches:\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Word\t |\tNumber of Matches\n===================================\n"
.section .rodata.str1.1
.LC11:
.string "%s\t |\t%d\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "/home/ubuntu/Datasets/stackv2/train-structured/sedflix/cuda_pattern_matching/master/pattern_CPU.cu"
.section .rodata.str1.1
.LC13:
.string "WRONG OUTPUT:\t %s\t|\t%d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $232, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movl $20, %edi
call malloc@PLT
movq %rax, 16(%rsp)
pxor %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movl $0, 96(%rsp)
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L60
movq %rax, %rbp
movq $20, 24(%rsp)
movl $0, %ebx
leaq 24(%rsp), %r12
.L41:
leaq 16(%rsp), %rdi
movq %rbp, %rcx
movl $10, %edx
movq %r12, %rsi
call __getdelim@PLT
cmpq $-1, %rax
je .L40
cmpq $100, %rbx
je .L40
movl $100, %ecx
cmpq %rcx, %rbx
cmovnb %rbx, %rcx
subq %rbx, %rcx
leaq 112(%rsp,%rbx), %rdi
movl $8, %edx
movq 16(%rsp), %rsi
call __strncpy_chk@PLT
movb $0, 116(%rsp,%rbx)
addq $20, %rbx
jmp .L41
.L60:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L40:
movq %rbp, %rdi
call fclose@PLT
leaq .LC1(%rip), %rsi
leaq .LC4(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L61
movl $0, %ebx
jmp .L42
.L61:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L43:
addl $1, %ebx
.L42:
movq %r12, %rdi
call getc@PLT
cmpl $-1, %eax
jne .L43
leal 4(%rbx), %edi
movslq %edi, %rdi
call malloc@PLT
movq %rax, %r13
movq %r12, %rdi
call rewind@PLT
testl %ebx, %ebx
jle .L44
movq %r13, %rbp
movslq %ebx, %r14
addq %r13, %r14
.L45:
movq %r12, %rdi
call getc@PLT
movb %al, 0(%rbp)
addq $1, %rbp
cmpq %r14, %rbp
jne .L45
.L44:
movslq %ebx, %rdx
leaq 0(%r13,%rdx), %rax
leaq 4(%r13,%rdx), %rdx
.L46:
movb $32, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L46
movq %r12, %rdi
call fclose@PLT
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 3(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $2, %eax
movl %eax, 12(%rsp)
movl $20, %edi
call malloc@PLT
movq %rax, (%rsp)
leaq 112(%rsp), %r15
movq %rax, %rcx
leaq 212(%rsp), %r14
movq %r15, %rdx
.L47:
movsbl 3(%rdx), %eax
sall $8, %eax
movsbl 2(%rdx), %esi
addl %esi, %eax
sall $8, %eax
movsbl 1(%rdx), %esi
addl %esi, %eax
sall $8, %eax
movsbl (%rdx), %esi
addl %esi, %eax
movl %eax, (%rcx)
addq $20, %rdx
addq $4, %rcx
cmpq %r14, %rdx
jne .L47
call clock@PLT
movq %rax, %rbp
leaq 80(%rsp), %r12
movl 12(%rsp), %r8d
movl $5, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq %r13, %rdi
call _Z16matchPattern_CPUPjS_Piii
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rbp
.L48:
movl (%r12), %ecx
movq %rbp, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r12
addq $20, %rbp
cmpq %r14, %rbp
jne .L48
movl $20, %edi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
movq %r13, %rdi
call strlen@PLT
movq %rax, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movq %r13, %rdi
call strlen@PLT
movq %rax, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
leal 127(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $7, %eax
movl %eax, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L49:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $162, %edx
leaq .LC12(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $20, %edx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $163, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %ebx
leaq .LC13(%rip), %r12
jmp .L51
.L62:
movl 12(%rsp), %r8d
movl $5, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z44__device_stub__Z18matchPattern_gpu_1PjS_PiiiPjS_Piii
jmp .L49
.L50:
addq $4, %rbx
cmpq $20, %rbx
je .L63
.L51:
movl 0(%rbp,%rbx), %ecx
cmpl %ecx, 80(%rsp,%rbx)
je .L50
leaq (%rbx,%rbx,4), %rdx
addq %r15, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L50
.L63:
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC15:
.string "_Z18matchPattern_gpu_1PjS_Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matchPattern_gpu_1PjS_Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pattern_CPU.hip"
.globl _Z16matchPattern_CPUPjS_Piii # -- Begin function _Z16matchPattern_CPUPjS_Piii
.p2align 4, 0x90
.type _Z16matchPattern_CPUPjS_Piii,@function
_Z16matchPattern_CPUPjS_Piii: # @_Z16matchPattern_CPUPjS_Piii
.cfi_startproc
# %bb.0:
testl %r8d, %r8d
jle .LBB0_12
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
movl %r8d, %r8d
movl %ecx, %r9d
xorl %r10d, %r10d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_10: # in Loop: Header=BB0_2 Depth=1
incq %r10
cmpq %r8, %r10
je .LBB0_11
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_8 Depth 3
xorl %r11d, %r11d
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_9: # %._crit_edge
# in Loop: Header=BB0_3 Depth=2
incl %r11d
cmpl $4, %r11d
je .LBB0_10
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_8 Depth 3
testl %r11d, %r11d
je .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=2
leal (,%r11,8), %ecx
movl (%rdi,%r10,4), %ebp
shrl %cl, %ebp
movl 4(%rdi,%r10,4), %ebx
negb %cl
# kill: def $cl killed $cl killed $ecx
shll %cl, %ebx
addl %ebp, %ebx
testl %eax, %eax
jg .LBB0_7
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_3 Depth=2
movl (%rdi,%r10,4), %ebx
testl %eax, %eax
jle .LBB0_9
.LBB0_7: # %.lr.ph.preheader
# in Loop: Header=BB0_3 Depth=2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_8: # %.lr.ph
# Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
xorl %ebp, %ebp
cmpl (%rsi,%rcx,4), %ebx
sete %bpl
addl %ebp, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %r9
jne .LBB0_8
jmp .LBB0_9
.LBB0_11:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
.LBB0_12: # %._crit_edge27
retq
.Lfunc_end0:
.size _Z16matchPattern_CPUPjS_Piii, .Lfunc_end0-_Z16matchPattern_CPUPjS_Piii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__matchPattern_gpu_1PjS_Piii # -- Begin function _Z33__device_stub__matchPattern_gpu_1PjS_Piii
.p2align 4, 0x90
.type _Z33__device_stub__matchPattern_gpu_1PjS_Piii,@function
_Z33__device_stub__matchPattern_gpu_1PjS_Piii: # @_Z33__device_stub__matchPattern_gpu_1PjS_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18matchPattern_gpu_1PjS_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z33__device_stub__matchPattern_gpu_1PjS_Piii, .Lfunc_end1-_Z33__device_stub__matchPattern_gpu_1PjS_Piii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $20, %edi
callq malloc
movq %rax, 24(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movl $0, 64(%rsp)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB2_1
# %bb.3:
movq %rax, %rbx
movq $20, 40(%rsp)
leaq 24(%rsp), %rdi
leaq 40(%rsp), %rsi
movl $10, %edx
movq %rax, %rcx
callq __getdelim
cmpq $-1, %rax
je .LBB2_7
# %bb.4: # %.lr.ph.preheader
xorl %r12d, %r12d
leaq 24(%rsp), %r14
leaq 40(%rsp), %r15
.p2align 4, 0x90
.LBB2_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq (%rsp,%r12), %rdi
addq $192, %rdi
movq 24(%rsp), %rsi
movl $8, %edx
callq strncpy
movb $0, 196(%rsp,%r12)
movq %r14, %rdi
movq %r15, %rsi
movl $10, %edx
movq %rbx, %rcx
callq __getdelim
cmpq $-1, %rax
je .LBB2_7
# %bb.6: # %.lr.ph
# in Loop: Header=BB2_5 Depth=1
leaq 20(%r12), %rax
cmpl $80, %r12d
movq %rax, %r12
jne .LBB2_5
.LBB2_7: # %.critedge
movq %rbx, %rdi
callq fclose
movl $.L.str.3, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB2_38
# %bb.8: # %.preheader104.preheader
movq %rax, %r14
movq $-1, %r15
.p2align 4, 0x90
.LBB2_9: # %.preheader104
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq getc
incq %r15
cmpl $-1, %eax
jne .LBB2_9
# %bb.10:
leaq 4(%r15), %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq rewind
testl %r15d, %r15d
je .LBB2_13
# %bb.11: # %.lr.ph109.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_12: # %.lr.ph109
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq getc
movb %al, (%rbx,%r12)
incq %r12
cmpq %r12, %r15
jne .LBB2_12
.LBB2_13: # %.preheader
movl $538976288, (%rbx,%r15) # imm = 0x20202020
movq %r14, %rdi
callq fclose
xorl %r12d, %r12d
movl $.L.str.5, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $20, %edi
callq malloc
movq %rax, %r14
leaq 195(%rsp), %rax
.p2align 4, 0x90
.LBB2_14: # =>This Inner Loop Header: Depth=1
movsbl -3(%rax), %ecx
movsbl -2(%rax), %edx
shll $8, %edx
addl %ecx, %edx
movsbl -1(%rax), %ecx
shll $16, %ecx
movzbl (%rax), %esi
shll $24, %esi
addl %ecx, %esi
addl %edx, %esi
movl %esi, (%r14,%r12,4)
incq %r12
addq $20, %rax
cmpq $5, %r12
jne .LBB2_14
# %bb.15:
movl %r15d, %ebp
shrl $2, %ebp
callq clock
movq %rax, %r12
cmpl $4, %r15d
jb .LBB2_24
# %bb.16: # %.preheader.lr.ph.i
movl %ebp, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_17: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
# Child Loop BB2_21 Depth 3
movl (%rbx,%rdx,4), %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_18: # Parent Loop BB2_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_21 Depth 3
movl %esi, %r8d
testl %edi, %edi
je .LBB2_20
# %bb.19: # in Loop: Header=BB2_18 Depth=2
leal (,%rdi,8), %ecx
movl %esi, %r9d
shrl %cl, %r9d
movl 4(%rbx,%rdx,4), %r8d
negb %cl
# kill: def $cl killed $cl killed $ecx
shll %cl, %r8d
addl %r9d, %r8d
.LBB2_20: # in Loop: Header=BB2_18 Depth=2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_21: # %.lr.ph.i
# Parent Loop BB2_17 Depth=1
# Parent Loop BB2_18 Depth=2
# => This Inner Loop Header: Depth=3
xorl %r9d, %r9d
cmpl (%r14,%rcx,4), %r8d
sete %r9b
addl %r9d, 48(%rsp,%rcx,4)
incq %rcx
cmpq $5, %rcx
jne .LBB2_21
# %bb.22: # %._crit_edge.i
# in Loop: Header=BB2_18 Depth=2
incl %edi
cmpl $4, %edi
jne .LBB2_18
# %bb.23: # in Loop: Header=BB2_17 Depth=1
incq %rdx
cmpq %rax, %rdx
jne .LBB2_17
.LBB2_24: # %_Z16matchPattern_CPUPjS_Piii.exit
callq clock
subq %r12, %rax
cvtsi2ss %rax, %xmm0
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
leaq 192(%rsp), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_25: # =>This Inner Loop Header: Depth=1
movl 48(%rsp,%r13,4), %edx
movl $.L.str.9, %edi
movq %r12, %rsi
xorl %eax, %eax
callq printf
incq %r13
addq $20, %r12
cmpq $5, %r13
jne .LBB2_25
# %bb.26:
movl $20, %edi
callq malloc
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq %rsp, %rdi
movl $20, %esi
callq hipMalloc
movq %rbx, %rdi
callq strlen
leaq 16(%rsp), %rdi
movq %rax, %rsi
callq hipMalloc
movq 16(%rsp), %r13
movq %rbx, %rdi
callq strlen
movq %r13, %rdi
movq %rbx, %rsi
movq %rax, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $20, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
shrl $7, %r15d
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r15
orq $32, %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_28
# %bb.27:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $5, 36(%rsp)
movl %ebp, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z18matchPattern_gpu_1PjS_Piii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_28:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB2_29
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit
movq (%rsp), %rsi
movl $20, %edx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_37
# %bb.32: # %_Z9gpuAssert10hipError_tPKcib.exit99.preheader.preheader
leaq 192(%rsp), %r15
xorl %r13d, %r13d
jmp .LBB2_33
.p2align 4, 0x90
.LBB2_35: # %_Z9gpuAssert10hipError_tPKcib.exit99
# in Loop: Header=BB2_33 Depth=1
incq %r13
addq $20, %r15
cmpq $5, %r13
je .LBB2_36
.LBB2_33: # %_Z9gpuAssert10hipError_tPKcib.exit99.preheader
# =>This Inner Loop Header: Depth=1
movl (%r12,%r13,4), %edx
cmpl %edx, 48(%rsp,%r13,4)
je .LBB2_35
# %bb.34: # in Loop: Header=BB2_33 Depth=1
movl $.L.str.11, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
jmp .LBB2_35
.LBB2_36:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 352
movl $.Lstr, %edi
jmp .LBB2_2
.LBB2_38:
movl $.Lstr.1, %edi
.LBB2_2:
callq puts@PLT
xorl %edi, %edi
callq exit
.LBB2_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str.10, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $162, %r8d
jmp .LBB2_30
.LBB2_37:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str.10, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $163, %r8d
.LBB2_30:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matchPattern_gpu_1PjS_Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18matchPattern_gpu_1PjS_Piii,@object # @_Z18matchPattern_gpu_1PjS_Piii
.section .rodata,"a",@progbits
.globl _Z18matchPattern_gpu_1PjS_Piii
.p2align 3, 0x0
_Z18matchPattern_gpu_1PjS_Piii:
.quad _Z33__device_stub__matchPattern_gpu_1PjS_Piii
.size _Z18matchPattern_gpu_1PjS_Piii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "./data/keywords.txt"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "./data/small.txt"
.size .L.str.3, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Length : %d\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time for matching keywords: %fs\n\n"
.size .L.str.6, 34
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%s\t |\t%d\n"
.size .L.str.9, 11
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/sedflix/cuda_pattern_matching/master/pattern_CPU.hip"
.size .L.str.10, 110
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "WRONG OUTPUT:\t %s\t|\t%d\n"
.size .L.str.11, 24
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.12, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18matchPattern_gpu_1PjS_Piii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "keywords.txt: File not found."
.size .Lstr, 30
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Unable to open the file."
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing Matches:"
.size .Lstr.2, 18
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Word\t |\tNumber of Matches\n==================================="
.size .Lstr.3, 63
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matchPattern_gpu_1PjS_Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matchPattern_gpu_1PjS_Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright 2016 Alexander Terenin
*
* Licensed under the Apache License, Version 2.0 (the "License")
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* /
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand_kernel.h>
// utility script to print sizeof(curandState), which is nowhere to be found in JCuda
int main() {
curandState *states;
curandStatePhilox4_32_10_t *philox;
curandStateMRG32k3a *mrg;
cudaMalloc((void **)&states, 64 * 64 * sizeof(curandState));
cudaMalloc((void **)&philox, 64 * 64 * sizeof(curandStatePhilox4_32_10_t));
cudaMalloc((void **)&mrg, 64 * 64 * sizeof(curandStateMRG32k3a));
printf("sizeof(curandState) %lu\n",sizeof(curandState));
printf("sizeof(curandStatePhilox4_32_10_t) %lu\n",sizeof(curandStatePhilox4_32_10_t));
printf("sizeof(curandStateMRG32k3a) %lu\n",sizeof(curandStateMRG32k3a));
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 2016 Alexander Terenin
*
* Licensed under the Apache License, Version 2.0 (the "License")
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* /
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand_kernel.h>
// utility script to print sizeof(curandState), which is nowhere to be found in JCuda
int main() {
curandState *states;
curandStatePhilox4_32_10_t *philox;
curandStateMRG32k3a *mrg;
cudaMalloc((void **)&states, 64 * 64 * sizeof(curandState));
cudaMalloc((void **)&philox, 64 * 64 * sizeof(curandStatePhilox4_32_10_t));
cudaMalloc((void **)&mrg, 64 * 64 * sizeof(curandStateMRG32k3a));
printf("sizeof(curandState) %lu\n",sizeof(curandState));
printf("sizeof(curandStatePhilox4_32_10_t) %lu\n",sizeof(curandStatePhilox4_32_10_t));
printf("sizeof(curandStateMRG32k3a) %lu\n",sizeof(curandStateMRG32k3a));
} | .file "tmpxft_0015f7b2_00000000-6_sizeof_curandState.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sizeof(curandState) %lu\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "sizeof(curandStatePhilox4_32_10_t) %lu\n"
.align 8
.LC2:
.string "sizeof(curandStateMRG32k3a) %lu\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $196608, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $196608, %esi
call cudaMalloc@PLT
movl $48, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $64, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $48, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2297:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 2016 Alexander Terenin
*
* Licensed under the Apache License, Version 2.0 (the "License")
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* /
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand_kernel.h>
// utility script to print sizeof(curandState), which is nowhere to be found in JCuda
int main() {
curandState *states;
curandStatePhilox4_32_10_t *philox;
curandStateMRG32k3a *mrg;
cudaMalloc((void **)&states, 64 * 64 * sizeof(curandState));
cudaMalloc((void **)&philox, 64 * 64 * sizeof(curandStatePhilox4_32_10_t));
cudaMalloc((void **)&mrg, 64 * 64 * sizeof(curandStateMRG32k3a));
printf("sizeof(curandState) %lu\n",sizeof(curandState));
printf("sizeof(curandStatePhilox4_32_10_t) %lu\n",sizeof(curandStatePhilox4_32_10_t));
printf("sizeof(curandStateMRG32k3a) %lu\n",sizeof(curandStateMRG32k3a));
} | /*
* Copyright 2016 Alexander Terenin
*
* Licensed under the Apache License, Version 2.0 (the "License")
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* /
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
// utility script to print sizeof(curandState), which is nowhere to be found in JCuda
int main() {
hiprandState *states;
hiprandStatePhilox4_32_10_t *philox;
hiprandStateMRG32k3a *mrg;
hipMalloc((void **)&states, 64 * 64 * sizeof(hiprandState));
hipMalloc((void **)&philox, 64 * 64 * sizeof(hiprandStatePhilox4_32_10_t));
hipMalloc((void **)&mrg, 64 * 64 * sizeof(hiprandStateMRG32k3a));
printf("sizeof(curandState) %lu\n",sizeof(hiprandState));
printf("sizeof(curandStatePhilox4_32_10_t) %lu\n",sizeof(hiprandStatePhilox4_32_10_t));
printf("sizeof(curandStateMRG32k3a) %lu\n",sizeof(hiprandStateMRG32k3a));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Copyright 2016 Alexander Terenin
*
* Licensed under the Apache License, Version 2.0 (the "License")
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* /
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
// utility script to print sizeof(curandState), which is nowhere to be found in JCuda
int main() {
hiprandState *states;
hiprandStatePhilox4_32_10_t *philox;
hiprandStateMRG32k3a *mrg;
hipMalloc((void **)&states, 64 * 64 * sizeof(hiprandState));
hipMalloc((void **)&philox, 64 * 64 * sizeof(hiprandStatePhilox4_32_10_t));
hipMalloc((void **)&mrg, 64 * 64 * sizeof(hiprandStateMRG32k3a));
printf("sizeof(curandState) %lu\n",sizeof(hiprandState));
printf("sizeof(curandStatePhilox4_32_10_t) %lu\n",sizeof(hiprandStatePhilox4_32_10_t));
printf("sizeof(curandStateMRG32k3a) %lu\n",sizeof(hiprandStateMRG32k3a));
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright 2016 Alexander Terenin
*
* Licensed under the Apache License, Version 2.0 (the "License")
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* /
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
// utility script to print sizeof(curandState), which is nowhere to be found in JCuda
int main() {
hiprandState *states;
hiprandStatePhilox4_32_10_t *philox;
hiprandStateMRG32k3a *mrg;
hipMalloc((void **)&states, 64 * 64 * sizeof(hiprandState));
hipMalloc((void **)&philox, 64 * 64 * sizeof(hiprandStatePhilox4_32_10_t));
hipMalloc((void **)&mrg, 64 * 64 * sizeof(hiprandStateMRG32k3a));
printf("sizeof(curandState) %lu\n",sizeof(hiprandState));
printf("sizeof(curandStatePhilox4_32_10_t) %lu\n",sizeof(hiprandStatePhilox4_32_10_t));
printf("sizeof(curandStateMRG32k3a) %lu\n",sizeof(hiprandStateMRG32k3a));
} | .text
.file "sizeof_curandState.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 16(%rsp), %rdi
movl $196608, %esi # imm = 0x30000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq %rsp, %rdi
movl $196608, %esi # imm = 0x30000
callq hipMalloc
movl $.L.str, %edi
movl $48, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $64, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $48, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sizeof(curandState) %lu\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "sizeof(curandStatePhilox4_32_10_t) %lu\n"
.size .L.str.1, 40
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "sizeof(curandStateMRG32k3a) %lu\n"
.size .L.str.2, 33
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015f7b2_00000000-6_sizeof_curandState.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sizeof(curandState) %lu\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "sizeof(curandStatePhilox4_32_10_t) %lu\n"
.align 8
.LC2:
.string "sizeof(curandStateMRG32k3a) %lu\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $196608, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $196608, %esi
call cudaMalloc@PLT
movl $48, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $64, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $48, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2297:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sizeof_curandState.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 16(%rsp), %rdi
movl $196608, %esi # imm = 0x30000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq %rsp, %rdi
movl $196608, %esi # imm = 0x30000
callq hipMalloc
movl $.L.str, %edi
movl $48, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $64, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $48, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sizeof(curandState) %lu\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "sizeof(curandStatePhilox4_32_10_t) %lu\n"
.size .L.str.1, 40
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "sizeof(curandStateMRG32k3a) %lu\n"
.size .L.str.2, 33
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // pour compiler : nvcc vecAdd.cu -o vecAdd
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// CUDA kernel. Each thread takes care of one element of c
__global__ void vecAdd(float *a, float *b, float *c, int n){
// identifiant global du thread dans la grille 1D
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// on s'assure de ne pas sortir des limites des tableaux a,b,c
if (tid < n){
//on effectue une addition élémentaire par thread
c[tid] = a[tid] + b[tid];
}
}
int main( int argc, char* argv[] )
{
// Size of vectors
int n = 100000;
// Host input vectors
float *h_a;
float *h_b;
//Host output vector
float *h_c;
// Device input vectors
float *d_a;
float *d_b;
//Device output vector
float *d_c;
// Size, in bytes, of each vector
size_t size = n*sizeof(float);
//////////////////////////////////////////
// Allocate memory for each vector on host
h_a = (float*) malloc (size);
h_b = (float*) malloc (size);
h_c = (float*) malloc (size);
/////////////////////////////////////////
// Allocate memory for each vector on GPU
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
int i;
// Initialize vectors on host
for( i = 0; i < n; i++ ) {
h_a[i] = sin(i)*sin(i);
h_b[i] = cos(i)*cos(i);
}
/////////////////////////////////////////
// Copy host vectors to device
cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);
int blockSize, gridSize;
/////////////////////////////////////////
// Number of threads in each thread block
blockSize = 512;
////////////////////////////////////////
// Number of thread blocks in grid
gridSize = (n + blockSize - 1) / blockSize;;
///////////////////////////////////////
// Launch the kernel
vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);
///////////////////////////////////////
// Copy array back to host
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
// Sum up vector c and print result divided by n, this should equal 1 within error
float sum = 0;
for(i=0; i<n; i++)
sum += h_c[i];
printf("final result: %f\n", sum/n);
/////////////////////////////////////////
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
////////////////////////////////////////
// Release host memory
free(h_a);
free(h_b);
free(h_c);
return 0;
} | code for sm_80
Function : _Z6vecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // pour compiler : nvcc vecAdd.cu -o vecAdd
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// CUDA kernel. Each thread takes care of one element of c
__global__ void vecAdd(float *a, float *b, float *c, int n){
// identifiant global du thread dans la grille 1D
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// on s'assure de ne pas sortir des limites des tableaux a,b,c
if (tid < n){
//on effectue une addition élémentaire par thread
c[tid] = a[tid] + b[tid];
}
}
int main( int argc, char* argv[] )
{
// Size of vectors
int n = 100000;
// Host input vectors
float *h_a;
float *h_b;
//Host output vector
float *h_c;
// Device input vectors
float *d_a;
float *d_b;
//Device output vector
float *d_c;
// Size, in bytes, of each vector
size_t size = n*sizeof(float);
//////////////////////////////////////////
// Allocate memory for each vector on host
h_a = (float*) malloc (size);
h_b = (float*) malloc (size);
h_c = (float*) malloc (size);
/////////////////////////////////////////
// Allocate memory for each vector on GPU
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
int i;
// Initialize vectors on host
for( i = 0; i < n; i++ ) {
h_a[i] = sin(i)*sin(i);
h_b[i] = cos(i)*cos(i);
}
/////////////////////////////////////////
// Copy host vectors to device
cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);
int blockSize, gridSize;
/////////////////////////////////////////
// Number of threads in each thread block
blockSize = 512;
////////////////////////////////////////
// Number of thread blocks in grid
gridSize = (n + blockSize - 1) / blockSize;;
///////////////////////////////////////
// Launch the kernel
vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);
///////////////////////////////////////
// Copy array back to host
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
// Sum up vector c and print result divided by n, this should equal 1 within error
float sum = 0;
for(i=0; i<n; i++)
sum += h_c[i];
printf("final result: %f\n", sum/n);
/////////////////////////////////////////
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
////////////////////////////////////////
// Release host memory
free(h_a);
free(h_b);
free(h_c);
return 0;
} | .file "tmpxft_000c6cd8_00000000-6_vecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "final result: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $400000, %edi
call malloc@PLT
movq %rax, %r12
movl $400000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000, %edi
call malloc@PLT
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl $0, %ebx
leaq 8(%rsp), %r13
.L12:
movq %rsp, %rsi
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movq %r13, %rdi
call sincos@PLT
movsd (%rsp), %xmm0
movsd 8(%rsp), %xmm1
mulsd %xmm1, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%r12,%rbx,4)
mulsd %xmm0, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq $100000, %rbx
jne .L12
movl $1, %ecx
movl $400000, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $196, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $400000, %edx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r14, %rax
leaq 400000(%r14), %rdx
pxor %xmm0, %xmm0
.L14:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L14
divss .LC1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $100000, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6vecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1203982336
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // pour compiler : nvcc vecAdd.cu -o vecAdd
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// CUDA kernel. Each thread takes care of one element of c
__global__ void vecAdd(float *a, float *b, float *c, int n){
// identifiant global du thread dans la grille 1D
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// on s'assure de ne pas sortir des limites des tableaux a,b,c
if (tid < n){
//on effectue une addition élémentaire par thread
c[tid] = a[tid] + b[tid];
}
}
int main( int argc, char* argv[] )
{
// Size of vectors
int n = 100000;
// Host input vectors
float *h_a;
float *h_b;
//Host output vector
float *h_c;
// Device input vectors
float *d_a;
float *d_b;
//Device output vector
float *d_c;
// Size, in bytes, of each vector
size_t size = n*sizeof(float);
//////////////////////////////////////////
// Allocate memory for each vector on host
h_a = (float*) malloc (size);
h_b = (float*) malloc (size);
h_c = (float*) malloc (size);
/////////////////////////////////////////
// Allocate memory for each vector on GPU
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
int i;
// Initialize vectors on host
for( i = 0; i < n; i++ ) {
h_a[i] = sin(i)*sin(i);
h_b[i] = cos(i)*cos(i);
}
/////////////////////////////////////////
// Copy host vectors to device
cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);
int blockSize, gridSize;
/////////////////////////////////////////
// Number of threads in each thread block
blockSize = 512;
////////////////////////////////////////
// Number of thread blocks in grid
gridSize = (n + blockSize - 1) / blockSize;;
///////////////////////////////////////
// Launch the kernel
vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);
///////////////////////////////////////
// Copy array back to host
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
// Sum up vector c and print result divided by n, this should equal 1 within error
float sum = 0;
for(i=0; i<n; i++)
sum += h_c[i];
printf("final result: %f\n", sum/n);
/////////////////////////////////////////
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
////////////////////////////////////////
// Release host memory
free(h_a);
free(h_b);
free(h_c);
return 0;
} | // pour compiler : nvcc vecAdd.cu -o vecAdd
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// CUDA kernel. Each thread takes care of one element of c
__global__ void vecAdd(float *a, float *b, float *c, int n){
// identifiant global du thread dans la grille 1D
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// on s'assure de ne pas sortir des limites des tableaux a,b,c
if (tid < n){
//on effectue une addition élémentaire par thread
c[tid] = a[tid] + b[tid];
}
}
int main( int argc, char* argv[] )
{
// Size of vectors
int n = 100000;
// Host input vectors
float *h_a;
float *h_b;
//Host output vector
float *h_c;
// Device input vectors
float *d_a;
float *d_b;
//Device output vector
float *d_c;
// Size, in bytes, of each vector
size_t size = n*sizeof(float);
//////////////////////////////////////////
// Allocate memory for each vector on host
h_a = (float*) malloc (size);
h_b = (float*) malloc (size);
h_c = (float*) malloc (size);
/////////////////////////////////////////
// Allocate memory for each vector on GPU
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
int i;
// Initialize vectors on host
for( i = 0; i < n; i++ ) {
h_a[i] = sin(i)*sin(i);
h_b[i] = cos(i)*cos(i);
}
/////////////////////////////////////////
// Copy host vectors to device
hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);
int blockSize, gridSize;
/////////////////////////////////////////
// Number of threads in each thread block
blockSize = 512;
////////////////////////////////////////
// Number of thread blocks in grid
gridSize = (n + blockSize - 1) / blockSize;;
///////////////////////////////////////
// Launch the kernel
vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);
///////////////////////////////////////
// Copy array back to host
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
// Sum up vector c and print result divided by n, this should equal 1 within error
float sum = 0;
for(i=0; i<n; i++)
sum += h_c[i];
printf("final result: %f\n", sum/n);
/////////////////////////////////////////
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
////////////////////////////////////////
// Release host memory
free(h_a);
free(h_b);
free(h_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // pour compiler : nvcc vecAdd.cu -o vecAdd
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// CUDA kernel. Each thread takes care of one element of c
__global__ void vecAdd(float *a, float *b, float *c, int n){
// identifiant global du thread dans la grille 1D
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// on s'assure de ne pas sortir des limites des tableaux a,b,c
if (tid < n){
//on effectue une addition élémentaire par thread
c[tid] = a[tid] + b[tid];
}
}
int main( int argc, char* argv[] )
{
// Size of vectors
int n = 100000;
// Host input vectors
float *h_a;
float *h_b;
//Host output vector
float *h_c;
// Device input vectors
float *d_a;
float *d_b;
//Device output vector
float *d_c;
// Size, in bytes, of each vector
size_t size = n*sizeof(float);
//////////////////////////////////////////
// Allocate memory for each vector on host
h_a = (float*) malloc (size);
h_b = (float*) malloc (size);
h_c = (float*) malloc (size);
/////////////////////////////////////////
// Allocate memory for each vector on GPU
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
int i;
// Initialize vectors on host
for( i = 0; i < n; i++ ) {
h_a[i] = sin(i)*sin(i);
h_b[i] = cos(i)*cos(i);
}
/////////////////////////////////////////
// Copy host vectors to device
hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);
int blockSize, gridSize;
/////////////////////////////////////////
// Number of threads in each thread block
blockSize = 512;
////////////////////////////////////////
// Number of thread blocks in grid
gridSize = (n + blockSize - 1) / blockSize;;
///////////////////////////////////////
// Launch the kernel
vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);
///////////////////////////////////////
// Copy array back to host
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
// Sum up vector c and print result divided by n, this should equal 1 within error
float sum = 0;
for(i=0; i<n; i++)
sum += h_c[i];
printf("final result: %f\n", sum/n);
/////////////////////////////////////////
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
////////////////////////////////////////
// Release host memory
free(h_a);
free(h_b);
free(h_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_i
.globl _Z6vecAddPfS_S_i
.p2align 8
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_i, .Lfunc_end0-_Z6vecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // pour compiler : nvcc vecAdd.cu -o vecAdd
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// CUDA kernel. Each thread takes care of one element of c
__global__ void vecAdd(float *a, float *b, float *c, int n){
// identifiant global du thread dans la grille 1D
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// on s'assure de ne pas sortir des limites des tableaux a,b,c
if (tid < n){
//on effectue une addition élémentaire par thread
c[tid] = a[tid] + b[tid];
}
}
int main( int argc, char* argv[] )
{
// Size of vectors
int n = 100000;
// Host input vectors
float *h_a;
float *h_b;
//Host output vector
float *h_c;
// Device input vectors
float *d_a;
float *d_b;
//Device output vector
float *d_c;
// Size, in bytes, of each vector
size_t size = n*sizeof(float);
//////////////////////////////////////////
// Allocate memory for each vector on host
h_a = (float*) malloc (size);
h_b = (float*) malloc (size);
h_c = (float*) malloc (size);
/////////////////////////////////////////
// Allocate memory for each vector on GPU
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
int i;
// Initialize vectors on host
for( i = 0; i < n; i++ ) {
h_a[i] = sin(i)*sin(i);
h_b[i] = cos(i)*cos(i);
}
/////////////////////////////////////////
// Copy host vectors to device
hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);
int blockSize, gridSize;
/////////////////////////////////////////
// Number of threads in each thread block
blockSize = 512;
////////////////////////////////////////
// Number of thread blocks in grid
gridSize = (n + blockSize - 1) / blockSize;;
///////////////////////////////////////
// Launch the kernel
vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);
///////////////////////////////////////
// Copy array back to host
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
// Sum up vector c and print result divided by n, this should equal 1 within error
float sum = 0;
for(i=0; i<n; i++)
sum += h_c[i];
printf("final result: %f\n", sum/n);
/////////////////////////////////////////
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
////////////////////////////////////////
// Release host memory
free(h_a);
free(h_b);
free(h_c);
return 0;
} | .text
.file "vecAdd.hip"
.globl _Z21__device_stub__vecAddPfS_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_i,@function
_Z21__device_stub__vecAddPfS_S_i: # @_Z21__device_stub__vecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x47c35000 # float 1.0E+5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r14
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r15
leaq 40(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 32(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 24(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r12,4)
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $100000, %r12 # imm = 0x186A0
jne .LBB1_1
# %bb.2:
movq 40(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967492, %rdi # imm = 0x1000000C4
leaq 316(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $100000, 52(%rsp) # imm = 0x186A0
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 24(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
addss (%r15,%rax,4), %xmm0
incq %rax
cmpq $100000, %rax # imm = 0x186A0
jne .LBB1_5
# %bb.6:
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_i,@object # @_Z6vecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_i
.p2align 3, 0x0
_Z6vecAddPfS_S_i:
.quad _Z21__device_stub__vecAddPfS_S_i
.size _Z6vecAddPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "final result: %f\n"
.size .L.str, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_i
.globl _Z6vecAddPfS_S_i
.p2align 8
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_i, .Lfunc_end0-_Z6vecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c6cd8_00000000-6_vecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "final result: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $400000, %edi
call malloc@PLT
movq %rax, %r12
movl $400000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000, %edi
call malloc@PLT
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl $0, %ebx
leaq 8(%rsp), %r13
.L12:
movq %rsp, %rsi
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movq %r13, %rdi
call sincos@PLT
movsd (%rsp), %xmm0
movsd 8(%rsp), %xmm1
mulsd %xmm1, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%r12,%rbx,4)
mulsd %xmm0, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq $100000, %rbx
jne .L12
movl $1, %ecx
movl $400000, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $196, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $400000, %edx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r14, %rax
leaq 400000(%r14), %rdx
pxor %xmm0, %xmm0
.L14:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L14
divss .LC1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $100000, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6vecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1203982336
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecAdd.hip"
.globl _Z21__device_stub__vecAddPfS_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_i,@function
_Z21__device_stub__vecAddPfS_S_i: # @_Z21__device_stub__vecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x47c35000 # float 1.0E+5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r14
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r15
leaq 40(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 32(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 24(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r12,4)
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $100000, %r12 # imm = 0x186A0
jne .LBB1_1
# %bb.2:
movq 40(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967492, %rdi # imm = 0x1000000C4
leaq 316(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $100000, 52(%rsp) # imm = 0x186A0
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 24(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
addss (%r15,%rax,4), %xmm0
incq %rax
cmpq $100000, %rax # imm = 0x186A0
jne .LBB1_5
# %bb.6:
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_i,@object # @_Z6vecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_i
.p2align 3, 0x0
_Z6vecAddPfS_S_i:
.quad _Z21__device_stub__vecAddPfS_S_i
.size _Z6vecAddPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "final result: %f\n"
.size .L.str, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cassert>
#include <sys/time.h>
struct timeval tGS, tGF, tKS, tKF, tCS, tCF;
// Matrices are stored in row-major order:
// M(row, col) = M.elements[row * M.width + col]
typedef struct {
int width;
int height;
float* elements;
} Matrix;
// Matrix sum kernel, called by MatrixSum()
__global__ void MatSumKernel(Matrix A, Matrix B, Matrix C)
{
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
C.elements[idx+C.width*idy] =
A.elements[idx+A.width*idy] + B.elements[idx+B.width*idy];
}
// Host code
void MatSum(const Matrix A, const Matrix B, Matrix C)
{
// Allocate A, B and C in device memory
int size = A.width*A.height * sizeof(float);
Matrix d_A; Matrix d_B; Matrix d_C;
d_A.width = A.width; d_A.height = A.height;
d_B.width = B.width; d_B.height = B.height;
d_C.width = C.width; d_C.height = C.height;
cudaMalloc((void**)&(d_A.elements), size);
cudaMalloc((void**)&(d_B.elements), size);
cudaMalloc((void**)&(d_C.elements), size);
// Load A and B to device memory
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_C.elements, C.elements, size, cudaMemcpyHostToDevice);
// Invoke kernel
gettimeofday(&tKS, 0);
dim3 nThreads(16, 16, 1);
dim3 nBlocks(d_A.width/16, d_B.height/16, 1);
MatSumKernel<<<nBlocks, nThreads>>>(d_A, d_B, d_C);
cudaDeviceSynchronize();
gettimeofday(&tKF, 0);
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
int main(int argc, char **argv) {
if (argc < 3) {
printf ("Usage: %s nLines nColumns\n", argv[0]);
return -1;
}
int nLines = atoi (argv[1]);
int nColumns = atoi (argv[2]);
int i,j;
Matrix A, B, C;
A.width = nColumns; A.height = nLines;
B.width = nColumns; B.height = nLines;
C.width = nColumns; C.height = nLines;
A.elements = (float *)malloc(A.width*A.height * sizeof(float));
B.elements = (float *)malloc(B.width*B.height * sizeof(float));
C.elements = (float *)malloc(C.width*C.height * sizeof(float));
for (i=0; i<A.width*A.height; i++)
A.elements[i] = i % 10 + 1;
for (i=0; i<B.width*B.height; i++)
B.elements[i] = (i+1) % 11 + 1;
for (i=0; i<C.width*C.height; i++)
C.elements[i] = 0;
// Performs the sum
gettimeofday(&tGS, 0);
MatSum(A, B, C);
gettimeofday(&tGF, 0);
//Checks the result
gettimeofday(&tCS, 0);
for (i=0; i<nColumns; i++) {
for (j=0; j<nLines; j++) {
float ctmp = A.elements[j*nColumns+i] + B.elements[j*nColumns+i];
assert( fabs(ctmp - C.elements[j*nColumns+i]) < 0.001);
}
}
gettimeofday(&tCF, 0);
printf(" total=%8.2f\n", (tCF.tv_sec*1000. + tCF.tv_usec/1000.) - (tGS.tv_sec*1000. + tGS.tv_usec/1000.));
printf("kernel=%8.2f\n", (tKF.tv_sec*1000. + tKF.tv_usec/1000.) - (tKS.tv_sec*1000. + tKS.tv_usec/1000.));
printf(" gpu=%8.2f\n", (tGF.tv_sec*1000. + tGF.tv_usec/1000.) - (tGS.tv_sec*1000. + tGS.tv_usec/1000.));
printf(" cpu=%8.2f\n", (tCF.tv_sec*1000. + tCF.tv_usec/1000.) - (tCS.tv_sec*1000. + tCS.tv_usec/1000.));
return 0;
} | code for sm_80
Function : _Z12MatSumKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002200 */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R7, R2, c[0x0][0x4], R7 ; /* 0x0000010002077a24 */
/* 0x002fc800078e0207 */
/*0090*/ IMAD R2, R7.reuse, c[0x0][0x160], R0.reuse ; /* 0x0000580007027a24 */
/* 0x140fe400078e0200 */
/*00a0*/ IMAD R4, R7, c[0x0][0x170], R0 ; /* 0x00005c0007047a24 */
/* 0x000fe400078e0200 */
/*00b0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0209 */
/*00c0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe400078e0209 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R7, R7, c[0x0][0x180], R0 ; /* 0x0000600007077a24 */
/* 0x000fc800078e0200 */
/*0100*/ IMAD.WIDE R6, R7, R9, c[0x0][0x188] ; /* 0x0000620007067625 */
/* 0x000fc800078e0209 */
/*0110*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0120*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cassert>
#include <sys/time.h>
struct timeval tGS, tGF, tKS, tKF, tCS, tCF;
// Matrices are stored in row-major order:
// M(row, col) = M.elements[row * M.width + col]
typedef struct {
int width;
int height;
float* elements;
} Matrix;
// Matrix sum kernel, called by MatrixSum()
__global__ void MatSumKernel(Matrix A, Matrix B, Matrix C)
{
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
C.elements[idx+C.width*idy] =
A.elements[idx+A.width*idy] + B.elements[idx+B.width*idy];
}
// Host code
void MatSum(const Matrix A, const Matrix B, Matrix C)
{
// Allocate A, B and C in device memory
int size = A.width*A.height * sizeof(float);
Matrix d_A; Matrix d_B; Matrix d_C;
d_A.width = A.width; d_A.height = A.height;
d_B.width = B.width; d_B.height = B.height;
d_C.width = C.width; d_C.height = C.height;
cudaMalloc((void**)&(d_A.elements), size);
cudaMalloc((void**)&(d_B.elements), size);
cudaMalloc((void**)&(d_C.elements), size);
// Load A and B to device memory
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_C.elements, C.elements, size, cudaMemcpyHostToDevice);
// Invoke kernel
gettimeofday(&tKS, 0);
dim3 nThreads(16, 16, 1);
dim3 nBlocks(d_A.width/16, d_B.height/16, 1);
MatSumKernel<<<nBlocks, nThreads>>>(d_A, d_B, d_C);
cudaDeviceSynchronize();
gettimeofday(&tKF, 0);
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
int main(int argc, char **argv) {
if (argc < 3) {
printf ("Usage: %s nLines nColumns\n", argv[0]);
return -1;
}
int nLines = atoi (argv[1]);
int nColumns = atoi (argv[2]);
int i,j;
Matrix A, B, C;
A.width = nColumns; A.height = nLines;
B.width = nColumns; B.height = nLines;
C.width = nColumns; C.height = nLines;
A.elements = (float *)malloc(A.width*A.height * sizeof(float));
B.elements = (float *)malloc(B.width*B.height * sizeof(float));
C.elements = (float *)malloc(C.width*C.height * sizeof(float));
for (i=0; i<A.width*A.height; i++)
A.elements[i] = i % 10 + 1;
for (i=0; i<B.width*B.height; i++)
B.elements[i] = (i+1) % 11 + 1;
for (i=0; i<C.width*C.height; i++)
C.elements[i] = 0;
// Performs the sum
gettimeofday(&tGS, 0);
MatSum(A, B, C);
gettimeofday(&tGF, 0);
//Checks the result
gettimeofday(&tCS, 0);
for (i=0; i<nColumns; i++) {
for (j=0; j<nLines; j++) {
float ctmp = A.elements[j*nColumns+i] + B.elements[j*nColumns+i];
assert( fabs(ctmp - C.elements[j*nColumns+i]) < 0.001);
}
}
gettimeofday(&tCF, 0);
printf(" total=%8.2f\n", (tCF.tv_sec*1000. + tCF.tv_usec/1000.) - (tGS.tv_sec*1000. + tGS.tv_usec/1000.));
printf("kernel=%8.2f\n", (tKF.tv_sec*1000. + tKF.tv_usec/1000.) - (tKS.tv_sec*1000. + tKS.tv_usec/1000.));
printf(" gpu=%8.2f\n", (tGF.tv_sec*1000. + tGF.tv_usec/1000.) - (tGS.tv_sec*1000. + tGS.tv_usec/1000.));
printf(" cpu=%8.2f\n", (tCF.tv_sec*1000. + tCF.tv_usec/1000.) - (tCS.tv_sec*1000. + tCS.tv_usec/1000.));
return 0;
} | .file "tmpxft_0003a368_00000000-6_matrixSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatSumKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatSumKernel6MatrixS_S_
.type _Z12MatSumKernel6MatrixS_S_, @function
_Z12MatSumKernel6MatrixS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12MatSumKernel6MatrixS_S_, .-_Z12MatSumKernel6MatrixS_S_
.globl _Z6MatSum6MatrixS_S_
.type _Z6MatSum6MatrixS_S_, @function
_Z6MatSum6MatrixS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $152, %rsp
.cfi_def_cfa_offset 192
movq %rsi, %r13
movq %rcx, %r12
movq %r9, %rbp
movq %fs:40, %rcx
movq %rcx, 136(%rsp)
xorl %ecx, %ecx
movq %rdi, %rbx
sarq $32, %rbx
movl %edi, 32(%rsp)
movl %ebx, 36(%rsp)
movl %edx, 48(%rsp)
sarq $32, %rdx
movl %edx, 52(%rsp)
movl %r8d, 64(%rsp)
sarq $32, %r8
movl %r8d, 68(%rsp)
imull %edi, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
leaq tKS(%rip), %rdi
call gettimeofday@PLT
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl 52(%rsp), %edx
leal 15(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $4, %eax
movl 32(%rsp), %ecx
leal 15(%rcx), %edx
testl %ecx, %ecx
cmovns %ecx, %edx
sarl $4, %edx
movl %edx, 20(%rsp)
movl %eax, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %esi
leaq tKF(%rip), %rdi
call gettimeofday@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movdqa 32(%rsp), %xmm0
movaps %xmm0, 80(%rsp)
movdqa 48(%rsp), %xmm1
movaps %xmm1, 96(%rsp)
movdqa 64(%rsp), %xmm2
movaps %xmm2, 112(%rsp)
leaq 112(%rsp), %rdx
leaq 96(%rsp), %rsi
leaq 80(%rsp), %rdi
call _Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6MatSum6MatrixS_S_, .-_Z6MatSum6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s nLines nColumns\n"
.LC3:
.string " total=%8.2f\n"
.LC4:
.string "kernel=%8.2f\n"
.LC5:
.string " gpu=%8.2f\n"
.LC6:
.string " cpu=%8.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rsi, %rbp
cmpl $2, %edi
jle .L37
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq %rax, 24(%rsp)
movl %eax, %ebx
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r14d
movl %r13d, %eax
imull %r15d, %eax
movl %eax, 20(%rsp)
movslq %eax, %r13
leaq 0(,%r13,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r12
movq 8(%rsp), %rdi
call malloc@PLT
movq %rax, 8(%rsp)
cmpl $0, 20(%rsp)
jle .L20
movl $0, %edx
.L21:
movslq %edx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
leal (%rax,%rax,4), %ecx
addl %ecx, %ecx
movl %edx, %eax
subl %ecx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rdx,4)
movq %rdx, %rsi
addq $1, %rdx
cmpq %rdx, %r13
jne .L21
addq $2, %rsi
movl $1, %ecx
.L22:
movslq %ecx, %rax
imulq $780903145, %rax, %rax
sarq $33, %rax
movl %ecx, %edi
sarl $31, %edi
subl %edi, %eax
leal (%rax,%rax,4), %edi
leal (%rax,%rdi,2), %edi
movl %ecx, %eax
subl %edi, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%r12,%rcx,4)
addq $1, %rcx
cmpq %rsi, %rcx
jne .L22
movq 8(%rsp), %rsi
movq %rsi, %rax
leaq (%rsi,%rdx,4), %rdx
.L23:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L23
.L20:
movl $0, %esi
leaq tGS(%rip), %rdi
call gettimeofday@PLT
movq 24(%rsp), %r8
salq $32, %r8
movl %r15d, %edi
orq %r8, %rdi
movq %rdi, %rdx
movq %rdi, %r8
movq 8(%rsp), %r9
movq %r12, %rcx
movq %rbp, %rsi
call _Z6MatSum6MatrixS_S_
movl $0, %esi
leaq tGF(%rip), %rdi
call gettimeofday@PLT
movl $0, %esi
leaq tCS(%rip), %rdi
call gettimeofday@PLT
movl $0, %edx
testl %r15d, %r15d
jg .L24
.L25:
movl $0, %esi
leaq tCF(%rip), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq tCF(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8+tCF(%rip), %xmm1
divsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq tGS(%rip), %xmm1
mulsd .LC2(%rip), %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq 8+tGS(%rip), %xmm2
divsd .LC2(%rip), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq tKF(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8+tKF(%rip), %xmm1
divsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq tKS(%rip), %xmm1
mulsd .LC2(%rip), %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq 8+tKS(%rip), %xmm2
divsd .LC2(%rip), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq tGF(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8+tGF(%rip), %xmm1
divsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq tGS(%rip), %xmm1
mulsd .LC2(%rip), %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq 8+tGS(%rip), %xmm2
divsd .LC2(%rip), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq tCF(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8+tCF(%rip), %xmm1
divsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq tCS(%rip), %xmm1
mulsd .LC2(%rip), %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq 8+tCS(%rip), %xmm2
divsd .LC2(%rip), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
.L17:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L17
.L26:
addl $1, %eax
cmpl %ebx, %eax
jne .L26
.L27:
addl $1, %edx
cmpl %r14d, %edx
je .L25
.L24:
movl $0, %eax
testl %ebx, %ebx
jg .L26
jmp .L27
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12MatSumKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatSumKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl tCF
.bss
.align 16
.type tCF, @object
.size tCF, 16
tCF:
.zero 16
.globl tCS
.align 16
.type tCS, @object
.size tCS, 16
tCS:
.zero 16
.globl tKF
.align 16
.type tKF, @object
.size tKF, 16
tKF:
.zero 16
.globl tKS
.align 16
.type tKS, @object
.size tKS, 16
tKS:
.zero 16
.globl tGF
.align 16
.type tGF, @object
.size tGF, 16
tGF:
.zero 16
.globl tGS
.align 16
.type tGS, @object
.size tGS, 16
tGS:
.zero 16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cassert>
#include <sys/time.h>
struct timeval tGS, tGF, tKS, tKF, tCS, tCF;
// Matrices are stored in row-major order:
// M(row, col) = M.elements[row * M.width + col]
typedef struct {
int width;
int height;
float* elements;
} Matrix;
// Matrix sum kernel, called by MatrixSum()
__global__ void MatSumKernel(Matrix A, Matrix B, Matrix C)
{
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
C.elements[idx+C.width*idy] =
A.elements[idx+A.width*idy] + B.elements[idx+B.width*idy];
}
// Host code
void MatSum(const Matrix A, const Matrix B, Matrix C)
{
// Allocate A, B and C in device memory
int size = A.width*A.height * sizeof(float);
Matrix d_A; Matrix d_B; Matrix d_C;
d_A.width = A.width; d_A.height = A.height;
d_B.width = B.width; d_B.height = B.height;
d_C.width = C.width; d_C.height = C.height;
cudaMalloc((void**)&(d_A.elements), size);
cudaMalloc((void**)&(d_B.elements), size);
cudaMalloc((void**)&(d_C.elements), size);
// Load A and B to device memory
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_C.elements, C.elements, size, cudaMemcpyHostToDevice);
// Invoke kernel
gettimeofday(&tKS, 0);
dim3 nThreads(16, 16, 1);
dim3 nBlocks(d_A.width/16, d_B.height/16, 1);
MatSumKernel<<<nBlocks, nThreads>>>(d_A, d_B, d_C);
cudaDeviceSynchronize();
gettimeofday(&tKF, 0);
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
int main(int argc, char **argv) {
if (argc < 3) {
printf ("Usage: %s nLines nColumns\n", argv[0]);
return -1;
}
int nLines = atoi (argv[1]);
int nColumns = atoi (argv[2]);
int i,j;
Matrix A, B, C;
A.width = nColumns; A.height = nLines;
B.width = nColumns; B.height = nLines;
C.width = nColumns; C.height = nLines;
A.elements = (float *)malloc(A.width*A.height * sizeof(float));
B.elements = (float *)malloc(B.width*B.height * sizeof(float));
C.elements = (float *)malloc(C.width*C.height * sizeof(float));
for (i=0; i<A.width*A.height; i++)
A.elements[i] = i % 10 + 1;
for (i=0; i<B.width*B.height; i++)
B.elements[i] = (i+1) % 11 + 1;
for (i=0; i<C.width*C.height; i++)
C.elements[i] = 0;
// Performs the sum
gettimeofday(&tGS, 0);
MatSum(A, B, C);
gettimeofday(&tGF, 0);
//Checks the result
gettimeofday(&tCS, 0);
for (i=0; i<nColumns; i++) {
for (j=0; j<nLines; j++) {
float ctmp = A.elements[j*nColumns+i] + B.elements[j*nColumns+i];
assert( fabs(ctmp - C.elements[j*nColumns+i]) < 0.001);
}
}
gettimeofday(&tCF, 0);
printf(" total=%8.2f\n", (tCF.tv_sec*1000. + tCF.tv_usec/1000.) - (tGS.tv_sec*1000. + tGS.tv_usec/1000.));
printf("kernel=%8.2f\n", (tKF.tv_sec*1000. + tKF.tv_usec/1000.) - (tKS.tv_sec*1000. + tKS.tv_usec/1000.));
printf(" gpu=%8.2f\n", (tGF.tv_sec*1000. + tGF.tv_usec/1000.) - (tGS.tv_sec*1000. + tGS.tv_usec/1000.));
printf(" cpu=%8.2f\n", (tCF.tv_sec*1000. + tCF.tv_usec/1000.) - (tCS.tv_sec*1000. + tCS.tv_usec/1000.));
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cassert>
#include <sys/time.h>
struct timeval tGS, tGF, tKS, tKF, tCS, tCF;
// Matrices are stored in row-major order:
// M(row, col) = M.elements[row * M.width + col]
typedef struct {
int width;
int height;
float* elements;
} Matrix;
// Matrix sum kernel, called by MatrixSum()
__global__ void MatSumKernel(Matrix A, Matrix B, Matrix C)
{
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
C.elements[idx+C.width*idy] =
A.elements[idx+A.width*idy] + B.elements[idx+B.width*idy];
}
// Host code
void MatSum(const Matrix A, const Matrix B, Matrix C)
{
// Allocate A, B and C in device memory
int size = A.width*A.height * sizeof(float);
Matrix d_A; Matrix d_B; Matrix d_C;
d_A.width = A.width; d_A.height = A.height;
d_B.width = B.width; d_B.height = B.height;
d_C.width = C.width; d_C.height = C.height;
hipMalloc((void**)&(d_A.elements), size);
hipMalloc((void**)&(d_B.elements), size);
hipMalloc((void**)&(d_C.elements), size);
// Load A and B to device memory
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
hipMemcpy(d_C.elements, C.elements, size, hipMemcpyHostToDevice);
// Invoke kernel
gettimeofday(&tKS, 0);
dim3 nThreads(16, 16, 1);
dim3 nBlocks(d_A.width/16, d_B.height/16, 1);
MatSumKernel<<<nBlocks, nThreads>>>(d_A, d_B, d_C);
hipDeviceSynchronize();
gettimeofday(&tKF, 0);
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
int main(int argc, char **argv) {
if (argc < 3) {
printf ("Usage: %s nLines nColumns\n", argv[0]);
return -1;
}
int nLines = atoi (argv[1]);
int nColumns = atoi (argv[2]);
int i,j;
Matrix A, B, C;
A.width = nColumns; A.height = nLines;
B.width = nColumns; B.height = nLines;
C.width = nColumns; C.height = nLines;
A.elements = (float *)malloc(A.width*A.height * sizeof(float));
B.elements = (float *)malloc(B.width*B.height * sizeof(float));
C.elements = (float *)malloc(C.width*C.height * sizeof(float));
for (i=0; i<A.width*A.height; i++)
A.elements[i] = i % 10 + 1;
for (i=0; i<B.width*B.height; i++)
B.elements[i] = (i+1) % 11 + 1;
for (i=0; i<C.width*C.height; i++)
C.elements[i] = 0;
// Performs the sum
gettimeofday(&tGS, 0);
MatSum(A, B, C);
gettimeofday(&tGF, 0);
//Checks the result
gettimeofday(&tCS, 0);
for (i=0; i<nColumns; i++) {
for (j=0; j<nLines; j++) {
float ctmp = A.elements[j*nColumns+i] + B.elements[j*nColumns+i];
assert( fabs(ctmp - C.elements[j*nColumns+i]) < 0.001);
}
}
gettimeofday(&tCF, 0);
printf(" total=%8.2f\n", (tCF.tv_sec*1000. + tCF.tv_usec/1000.) - (tGS.tv_sec*1000. + tGS.tv_usec/1000.));
printf("kernel=%8.2f\n", (tKF.tv_sec*1000. + tKF.tv_usec/1000.) - (tKS.tv_sec*1000. + tKS.tv_usec/1000.));
printf(" gpu=%8.2f\n", (tGF.tv_sec*1000. + tGF.tv_usec/1000.) - (tGS.tv_sec*1000. + tGS.tv_usec/1000.));
printf(" cpu=%8.2f\n", (tCF.tv_sec*1000. + tCF.tv_usec/1000.) - (tCS.tv_sec*1000. + tCS.tv_usec/1000.));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cassert>
#include <sys/time.h>
struct timeval tGS, tGF, tKS, tKF, tCS, tCF;
// Matrices are stored in row-major order:
// M(row, col) = M.elements[row * M.width + col]
typedef struct {
int width;
int height;
float* elements;
} Matrix;
// Matrix sum kernel, called by MatrixSum()
__global__ void MatSumKernel(Matrix A, Matrix B, Matrix C)
{
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
C.elements[idx+C.width*idy] =
A.elements[idx+A.width*idy] + B.elements[idx+B.width*idy];
}
// Host code
void MatSum(const Matrix A, const Matrix B, Matrix C)
{
// Allocate A, B and C in device memory
int size = A.width*A.height * sizeof(float);
Matrix d_A; Matrix d_B; Matrix d_C;
d_A.width = A.width; d_A.height = A.height;
d_B.width = B.width; d_B.height = B.height;
d_C.width = C.width; d_C.height = C.height;
hipMalloc((void**)&(d_A.elements), size);
hipMalloc((void**)&(d_B.elements), size);
hipMalloc((void**)&(d_C.elements), size);
// Load A and B to device memory
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
hipMemcpy(d_C.elements, C.elements, size, hipMemcpyHostToDevice);
// Invoke kernel
gettimeofday(&tKS, 0);
dim3 nThreads(16, 16, 1);
dim3 nBlocks(d_A.width/16, d_B.height/16, 1);
MatSumKernel<<<nBlocks, nThreads>>>(d_A, d_B, d_C);
hipDeviceSynchronize();
gettimeofday(&tKF, 0);
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
int main(int argc, char **argv) {
if (argc < 3) {
printf ("Usage: %s nLines nColumns\n", argv[0]);
return -1;
}
int nLines = atoi (argv[1]);
int nColumns = atoi (argv[2]);
int i,j;
Matrix A, B, C;
A.width = nColumns; A.height = nLines;
B.width = nColumns; B.height = nLines;
C.width = nColumns; C.height = nLines;
A.elements = (float *)malloc(A.width*A.height * sizeof(float));
B.elements = (float *)malloc(B.width*B.height * sizeof(float));
C.elements = (float *)malloc(C.width*C.height * sizeof(float));
for (i=0; i<A.width*A.height; i++)
A.elements[i] = i % 10 + 1;
for (i=0; i<B.width*B.height; i++)
B.elements[i] = (i+1) % 11 + 1;
for (i=0; i<C.width*C.height; i++)
C.elements[i] = 0;
// Performs the sum
gettimeofday(&tGS, 0);
MatSum(A, B, C);
gettimeofday(&tGF, 0);
//Checks the result
gettimeofday(&tCS, 0);
for (i=0; i<nColumns; i++) {
for (j=0; j<nLines; j++) {
float ctmp = A.elements[j*nColumns+i] + B.elements[j*nColumns+i];
assert( fabs(ctmp - C.elements[j*nColumns+i]) < 0.001);
}
}
gettimeofday(&tCF, 0);
printf(" total=%8.2f\n", (tCF.tv_sec*1000. + tCF.tv_usec/1000.) - (tGS.tv_sec*1000. + tGS.tv_usec/1000.));
printf("kernel=%8.2f\n", (tKF.tv_sec*1000. + tKF.tv_usec/1000.) - (tKS.tv_sec*1000. + tKS.tv_usec/1000.));
printf(" gpu=%8.2f\n", (tGF.tv_sec*1000. + tGF.tv_usec/1000.) - (tGS.tv_sec*1000. + tGS.tv_usec/1000.));
printf(" cpu=%8.2f\n", (tCF.tv_sec*1000. + tCF.tv_usec/1000.) - (tCS.tv_sec*1000. + tCS.tv_usec/1000.));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatSumKernel6MatrixS_S_
.globl _Z12MatSumKernel6MatrixS_S_
.p2align 8
.type _Z12MatSumKernel6MatrixS_S_,@function
_Z12MatSumKernel6MatrixS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s6, s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, v3, s6, v[2:3]
v_mad_u64_u32 v[4:5], null, v3, s7, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v6, v[0:1], off
global_load_b32 v4, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v6, v4
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatSumKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatSumKernel6MatrixS_S_, .Lfunc_end0-_Z12MatSumKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatSumKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatSumKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cassert>
#include <sys/time.h>
struct timeval tGS, tGF, tKS, tKF, tCS, tCF;
// Matrices are stored in row-major order:
// M(row, col) = M.elements[row * M.width + col]
typedef struct {
int width;
int height;
float* elements;
} Matrix;
// Matrix sum kernel, called by MatrixSum()
__global__ void MatSumKernel(Matrix A, Matrix B, Matrix C)
{
int idx = threadIdx.x + blockDim.x * blockIdx.x;
int idy = threadIdx.y + blockDim.y * blockIdx.y;
C.elements[idx+C.width*idy] =
A.elements[idx+A.width*idy] + B.elements[idx+B.width*idy];
}
// Host code
void MatSum(const Matrix A, const Matrix B, Matrix C)
{
// Allocate A, B and C in device memory
int size = A.width*A.height * sizeof(float);
Matrix d_A; Matrix d_B; Matrix d_C;
d_A.width = A.width; d_A.height = A.height;
d_B.width = B.width; d_B.height = B.height;
d_C.width = C.width; d_C.height = C.height;
hipMalloc((void**)&(d_A.elements), size);
hipMalloc((void**)&(d_B.elements), size);
hipMalloc((void**)&(d_C.elements), size);
// Load A and B to device memory
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
hipMemcpy(d_C.elements, C.elements, size, hipMemcpyHostToDevice);
// Invoke kernel
gettimeofday(&tKS, 0);
dim3 nThreads(16, 16, 1);
dim3 nBlocks(d_A.width/16, d_B.height/16, 1);
MatSumKernel<<<nBlocks, nThreads>>>(d_A, d_B, d_C);
hipDeviceSynchronize();
gettimeofday(&tKF, 0);
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
int main(int argc, char **argv) {
if (argc < 3) {
printf ("Usage: %s nLines nColumns\n", argv[0]);
return -1;
}
int nLines = atoi (argv[1]);
int nColumns = atoi (argv[2]);
int i,j;
Matrix A, B, C;
A.width = nColumns; A.height = nLines;
B.width = nColumns; B.height = nLines;
C.width = nColumns; C.height = nLines;
A.elements = (float *)malloc(A.width*A.height * sizeof(float));
B.elements = (float *)malloc(B.width*B.height * sizeof(float));
C.elements = (float *)malloc(C.width*C.height * sizeof(float));
for (i=0; i<A.width*A.height; i++)
A.elements[i] = i % 10 + 1;
for (i=0; i<B.width*B.height; i++)
B.elements[i] = (i+1) % 11 + 1;
for (i=0; i<C.width*C.height; i++)
C.elements[i] = 0;
// Performs the sum
gettimeofday(&tGS, 0);
MatSum(A, B, C);
gettimeofday(&tGF, 0);
//Checks the result
gettimeofday(&tCS, 0);
for (i=0; i<nColumns; i++) {
for (j=0; j<nLines; j++) {
float ctmp = A.elements[j*nColumns+i] + B.elements[j*nColumns+i];
assert( fabs(ctmp - C.elements[j*nColumns+i]) < 0.001);
}
}
gettimeofday(&tCF, 0);
printf(" total=%8.2f\n", (tCF.tv_sec*1000. + tCF.tv_usec/1000.) - (tGS.tv_sec*1000. + tGS.tv_usec/1000.));
printf("kernel=%8.2f\n", (tKF.tv_sec*1000. + tKF.tv_usec/1000.) - (tKS.tv_sec*1000. + tKS.tv_usec/1000.));
printf(" gpu=%8.2f\n", (tGF.tv_sec*1000. + tGF.tv_usec/1000.) - (tGS.tv_sec*1000. + tGS.tv_usec/1000.));
printf(" cpu=%8.2f\n", (tCF.tv_sec*1000. + tCF.tv_usec/1000.) - (tCS.tv_sec*1000. + tCS.tv_usec/1000.));
return 0;
} | .text
.file "matrixSum.hip"
.globl _Z27__device_stub__MatSumKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatSumKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatSumKernel6MatrixS_S_,@function
_Z27__device_stub__MatSumKernel6MatrixS_S_: # @_Z27__device_stub__MatSumKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatSumKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__MatSumKernel6MatrixS_S_, .Lfunc_end0-_Z27__device_stub__MatSumKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z6MatSum6MatrixS_S_ # -- Begin function _Z6MatSum6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatSum6MatrixS_S_,@function
_Z6MatSum6MatrixS_S_: # @_Z6MatSum6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r9, %rbx
movq %rcx, %r15
movq %rsi, %r12
movq %rdi, %rax
shrq $32, %rax
movl %edx, 16(%rsp)
shrq $32, %rdx
movl %r8d, (%rsp)
shrq $32, %r8
imull %edi, %eax
shll $2, %eax
movq %rdi, 32(%rsp)
movl %edx, 20(%rsp)
movl %r8d, 4(%rsp)
leaq 40(%rsp), %rdi
movslq %eax, %r14
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $tKS, %edi
xorl %esi, %esi
callq gettimeofday
movl 32(%rsp), %eax
leal 15(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
movl 20(%rsp), %eax
leal 15(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $4, %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movups 32(%rsp), %xmm0
movups 16(%rsp), %xmm1
movups (%rsp), %xmm2
movups %xmm0, 152(%rsp)
movups %xmm1, 136(%rsp)
movups %xmm2, 120(%rsp)
leaq 152(%rsp), %rax
movq %rax, 96(%rsp)
leaq 136(%rsp), %rax
movq %rax, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatSumKernel6MatrixS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl $tKF, %edi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6MatSum6MatrixS_S_, .Lfunc_end1-_Z6MatSum6MatrixS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jg .LBB2_2
# %bb.1:
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $-1, %r14d
jmp .LBB2_11
.LBB2_2:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %ebx
movq %r14, (%rsp) # 8-byte Spill
movl %r14d, %ebp
imull %eax, %ebp
movslq %ebp, %r14
leaq (,%r14,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
callq malloc
movq %rax, %r12
movq %r13, %rdi
callq malloc
movq %rax, %r13
movl %ebp, %edx
testl %r14d, %r14d
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
movl $1, %eax
xorl %ecx, %ecx
movl $3435973837, %esi # imm = 0xCCCCCCCD
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, %edi
imulq %rsi, %rdi
shrq $35, %rdi
addl %edi, %edi
leal (%rdi,%rdi,4), %edi
movl %eax, %r8d
subl %edi, %r8d
xorps %xmm0, %xmm0
cvtsi2ss %r8d, %xmm0
movss %xmm0, (%r15,%rcx,4)
incq %rcx
incl %eax
cmpq %rcx, %rdx
jne .LBB2_4
.LBB2_5: # %.preheader67
movq (%rsp), %r11 # 8-byte Reload
shlq $32, %r11
testl %ebp, %ebp
jle .LBB2_8
# %bb.6: # %.lr.ph70.preheader
leaq (,%rdx,4), %rax
movl $2, %ecx
movl $1, %esi
xorl %edi, %edi
movl $3123612579, %r8d # imm = 0xBA2E8BA3
.p2align 4, 0x90
.LBB2_7: # %.lr.ph70
# =>This Inner Loop Header: Depth=1
movl %esi, %r9d
imulq %r8, %r9
shrq $35, %r9
leal (%r9,%r9,4), %r10d
leal (%r9,%r10,2), %r9d
movl %ecx, %r10d
subl %r9d, %r10d
xorps %xmm0, %xmm0
cvtsi2ss %r10d, %xmm0
movss %xmm0, (%r12,%rdi)
addq $4, %rdi
incl %ecx
incl %esi
cmpq %rdi, %rax
jne .LBB2_7
.LBB2_8: # %.preheader66
orq %r11, %rbx
testl %ebp, %ebp
jle .LBB2_10
# %bb.9: # %.lr.ph72.preheader
shlq $2, %rdx
movq %r13, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB2_10: # %._crit_edge
xorl %r14d, %r14d
movl $tGS, %edi
xorl %esi, %esi
callq gettimeofday
movq %rbx, %rdi
movq %r15, %rsi
movq %rbx, %rdx
movq %r12, %rcx
movq %rbx, %r8
movq %r13, %r9
callq _Z6MatSum6MatrixS_S_
movl $tGF, %edi
xorl %esi, %esi
callq gettimeofday
movl $tCS, %edi
xorl %esi, %esi
callq gettimeofday
movl $tCF, %edi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq tCF(%rip), %xmm1
movsd .LCPI2_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq tCF+8(%rip), %xmm0
divsd %xmm3, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq tGS(%rip), %xmm1
cvtsi2sdq tGS+8(%rip), %xmm2
mulsd %xmm3, %xmm1
divsd %xmm3, %xmm2
addsd %xmm1, %xmm2
subsd %xmm2, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorps %xmm1, %xmm1
cvtsi2sdq tKF(%rip), %xmm1
movsd .LCPI2_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq tKF+8(%rip), %xmm0
divsd %xmm3, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq tKS(%rip), %xmm1
xorps %xmm2, %xmm2
cvtsi2sdq tKS+8(%rip), %xmm2
mulsd %xmm3, %xmm1
divsd %xmm3, %xmm2
addsd %xmm1, %xmm2
subsd %xmm2, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorps %xmm1, %xmm1
cvtsi2sdq tGF(%rip), %xmm1
movsd .LCPI2_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq tGF+8(%rip), %xmm0
divsd %xmm3, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq tGS(%rip), %xmm1
xorps %xmm2, %xmm2
cvtsi2sdq tGS+8(%rip), %xmm2
mulsd %xmm3, %xmm1
divsd %xmm3, %xmm2
addsd %xmm1, %xmm2
subsd %xmm2, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorps %xmm1, %xmm1
cvtsi2sdq tCF(%rip), %xmm1
movsd .LCPI2_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq tCF+8(%rip), %xmm0
divsd %xmm3, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq tCS(%rip), %xmm1
xorps %xmm2, %xmm2
cvtsi2sdq tCS+8(%rip), %xmm2
mulsd %xmm3, %xmm1
divsd %xmm3, %xmm2
addsd %xmm1, %xmm2
subsd %xmm2, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
.LBB2_11:
movl %r14d, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatSumKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type tGS,@object # @tGS
.bss
.globl tGS
.p2align 3, 0x0
tGS:
.zero 16
.size tGS, 16
.type tGF,@object # @tGF
.globl tGF
.p2align 3, 0x0
tGF:
.zero 16
.size tGF, 16
.type tKS,@object # @tKS
.globl tKS
.p2align 3, 0x0
tKS:
.zero 16
.size tKS, 16
.type tKF,@object # @tKF
.globl tKF
.p2align 3, 0x0
tKF:
.zero 16
.size tKF, 16
.type tCS,@object # @tCS
.globl tCS
.p2align 3, 0x0
tCS:
.zero 16
.size tCS, 16
.type tCF,@object # @tCF
.globl tCF
.p2align 3, 0x0
tCF:
.zero 16
.size tCF, 16
.type _Z12MatSumKernel6MatrixS_S_,@object # @_Z12MatSumKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatSumKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatSumKernel6MatrixS_S_:
.quad _Z27__device_stub__MatSumKernel6MatrixS_S_
.size _Z12MatSumKernel6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s nLines nColumns\n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " total=%8.2f\n"
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "kernel=%8.2f\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " gpu=%8.2f\n"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " cpu=%8.2f\n"
.size .L.str.4, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatSumKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatSumKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym tGS
.addrsig_sym tGF
.addrsig_sym tKS
.addrsig_sym tKF
.addrsig_sym tCS
.addrsig_sym tCF
.addrsig_sym _Z12MatSumKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12MatSumKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002200 */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*0080*/ IMAD R7, R2, c[0x0][0x4], R7 ; /* 0x0000010002077a24 */
/* 0x002fc800078e0207 */
/*0090*/ IMAD R2, R7.reuse, c[0x0][0x160], R0.reuse ; /* 0x0000580007027a24 */
/* 0x140fe400078e0200 */
/*00a0*/ IMAD R4, R7, c[0x0][0x170], R0 ; /* 0x00005c0007047a24 */
/* 0x000fe400078e0200 */
/*00b0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0209 */
/*00c0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe400078e0209 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R7, R7, c[0x0][0x180], R0 ; /* 0x0000600007077a24 */
/* 0x000fc800078e0200 */
/*0100*/ IMAD.WIDE R6, R7, R9, c[0x0][0x188] ; /* 0x0000620007067625 */
/* 0x000fc800078e0209 */
/*0110*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0120*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatSumKernel6MatrixS_S_
.globl _Z12MatSumKernel6MatrixS_S_
.p2align 8
.type _Z12MatSumKernel6MatrixS_S_,@function
_Z12MatSumKernel6MatrixS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s6, s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, v3, s6, v[2:3]
v_mad_u64_u32 v[4:5], null, v3, s7, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v6, v[0:1], off
global_load_b32 v4, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v6, v4
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatSumKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatSumKernel6MatrixS_S_, .Lfunc_end0-_Z12MatSumKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatSumKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatSumKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003a368_00000000-6_matrixSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatSumKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatSumKernel6MatrixS_S_
.type _Z12MatSumKernel6MatrixS_S_, @function
_Z12MatSumKernel6MatrixS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12MatSumKernel6MatrixS_S_, .-_Z12MatSumKernel6MatrixS_S_
.globl _Z6MatSum6MatrixS_S_
.type _Z6MatSum6MatrixS_S_, @function
_Z6MatSum6MatrixS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $152, %rsp
.cfi_def_cfa_offset 192
movq %rsi, %r13
movq %rcx, %r12
movq %r9, %rbp
movq %fs:40, %rcx
movq %rcx, 136(%rsp)
xorl %ecx, %ecx
movq %rdi, %rbx
sarq $32, %rbx
movl %edi, 32(%rsp)
movl %ebx, 36(%rsp)
movl %edx, 48(%rsp)
sarq $32, %rdx
movl %edx, 52(%rsp)
movl %r8d, 64(%rsp)
sarq $32, %r8
movl %r8d, 68(%rsp)
imull %edi, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
leaq tKS(%rip), %rdi
call gettimeofday@PLT
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl 52(%rsp), %edx
leal 15(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $4, %eax
movl 32(%rsp), %ecx
leal 15(%rcx), %edx
testl %ecx, %ecx
cmovns %ecx, %edx
sarl $4, %edx
movl %edx, 20(%rsp)
movl %eax, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %esi
leaq tKF(%rip), %rdi
call gettimeofday@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movdqa 32(%rsp), %xmm0
movaps %xmm0, 80(%rsp)
movdqa 48(%rsp), %xmm1
movaps %xmm1, 96(%rsp)
movdqa 64(%rsp), %xmm2
movaps %xmm2, 112(%rsp)
leaq 112(%rsp), %rdx
leaq 96(%rsp), %rsi
leaq 80(%rsp), %rdi
call _Z41__device_stub__Z12MatSumKernel6MatrixS_S_R6MatrixS0_S0_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6MatSum6MatrixS_S_, .-_Z6MatSum6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s nLines nColumns\n"
.LC3:
.string " total=%8.2f\n"
.LC4:
.string "kernel=%8.2f\n"
.LC5:
.string " gpu=%8.2f\n"
.LC6:
.string " cpu=%8.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rsi, %rbp
cmpl $2, %edi
jle .L37
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq %rax, 24(%rsp)
movl %eax, %ebx
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r14d
movl %r13d, %eax
imull %r15d, %eax
movl %eax, 20(%rsp)
movslq %eax, %r13
leaq 0(,%r13,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r12
movq 8(%rsp), %rdi
call malloc@PLT
movq %rax, 8(%rsp)
cmpl $0, 20(%rsp)
jle .L20
movl $0, %edx
.L21:
movslq %edx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
leal (%rax,%rax,4), %ecx
addl %ecx, %ecx
movl %edx, %eax
subl %ecx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rdx,4)
movq %rdx, %rsi
addq $1, %rdx
cmpq %rdx, %r13
jne .L21
addq $2, %rsi
movl $1, %ecx
.L22:
movslq %ecx, %rax
imulq $780903145, %rax, %rax
sarq $33, %rax
movl %ecx, %edi
sarl $31, %edi
subl %edi, %eax
leal (%rax,%rax,4), %edi
leal (%rax,%rdi,2), %edi
movl %ecx, %eax
subl %edi, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%r12,%rcx,4)
addq $1, %rcx
cmpq %rsi, %rcx
jne .L22
movq 8(%rsp), %rsi
movq %rsi, %rax
leaq (%rsi,%rdx,4), %rdx
.L23:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L23
.L20:
movl $0, %esi
leaq tGS(%rip), %rdi
call gettimeofday@PLT
movq 24(%rsp), %r8
salq $32, %r8
movl %r15d, %edi
orq %r8, %rdi
movq %rdi, %rdx
movq %rdi, %r8
movq 8(%rsp), %r9
movq %r12, %rcx
movq %rbp, %rsi
call _Z6MatSum6MatrixS_S_
movl $0, %esi
leaq tGF(%rip), %rdi
call gettimeofday@PLT
movl $0, %esi
leaq tCS(%rip), %rdi
call gettimeofday@PLT
movl $0, %edx
testl %r15d, %r15d
jg .L24
.L25:
movl $0, %esi
leaq tCF(%rip), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq tCF(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8+tCF(%rip), %xmm1
divsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq tGS(%rip), %xmm1
mulsd .LC2(%rip), %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq 8+tGS(%rip), %xmm2
divsd .LC2(%rip), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq tKF(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8+tKF(%rip), %xmm1
divsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq tKS(%rip), %xmm1
mulsd .LC2(%rip), %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq 8+tKS(%rip), %xmm2
divsd .LC2(%rip), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq tGF(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8+tGF(%rip), %xmm1
divsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq tGS(%rip), %xmm1
mulsd .LC2(%rip), %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq 8+tGS(%rip), %xmm2
divsd .LC2(%rip), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq tCF(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8+tCF(%rip), %xmm1
divsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq tCS(%rip), %xmm1
mulsd .LC2(%rip), %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq 8+tCS(%rip), %xmm2
divsd .LC2(%rip), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
.L17:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L17
.L26:
addl $1, %eax
cmpl %ebx, %eax
jne .L26
.L27:
addl $1, %edx
cmpl %r14d, %edx
je .L25
.L24:
movl $0, %eax
testl %ebx, %ebx
jg .L26
jmp .L27
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12MatSumKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatSumKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl tCF
.bss
.align 16
.type tCF, @object
.size tCF, 16
tCF:
.zero 16
.globl tCS
.align 16
.type tCS, @object
.size tCS, 16
tCS:
.zero 16
.globl tKF
.align 16
.type tKF, @object
.size tKF, 16
tKF:
.zero 16
.globl tKS
.align 16
.type tKS, @object
.size tKS, 16
tKS:
.zero 16
.globl tGF
.align 16
.type tGF, @object
.size tGF, 16
tGF:
.zero 16
.globl tGS
.align 16
.type tGS, @object
.size tGS, 16
tGS:
.zero 16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixSum.hip"
.globl _Z27__device_stub__MatSumKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatSumKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatSumKernel6MatrixS_S_,@function
_Z27__device_stub__MatSumKernel6MatrixS_S_: # @_Z27__device_stub__MatSumKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatSumKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__MatSumKernel6MatrixS_S_, .Lfunc_end0-_Z27__device_stub__MatSumKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z6MatSum6MatrixS_S_ # -- Begin function _Z6MatSum6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatSum6MatrixS_S_,@function
_Z6MatSum6MatrixS_S_: # @_Z6MatSum6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r9, %rbx
movq %rcx, %r15
movq %rsi, %r12
movq %rdi, %rax
shrq $32, %rax
movl %edx, 16(%rsp)
shrq $32, %rdx
movl %r8d, (%rsp)
shrq $32, %r8
imull %edi, %eax
shll $2, %eax
movq %rdi, 32(%rsp)
movl %edx, 20(%rsp)
movl %r8d, 4(%rsp)
leaq 40(%rsp), %rdi
movslq %eax, %r14
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $tKS, %edi
xorl %esi, %esi
callq gettimeofday
movl 32(%rsp), %eax
leal 15(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
movl 20(%rsp), %eax
leal 15(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $4, %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movups 32(%rsp), %xmm0
movups 16(%rsp), %xmm1
movups (%rsp), %xmm2
movups %xmm0, 152(%rsp)
movups %xmm1, 136(%rsp)
movups %xmm2, 120(%rsp)
leaq 152(%rsp), %rax
movq %rax, 96(%rsp)
leaq 136(%rsp), %rax
movq %rax, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatSumKernel6MatrixS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl $tKF, %edi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6MatSum6MatrixS_S_, .Lfunc_end1-_Z6MatSum6MatrixS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jg .LBB2_2
# %bb.1:
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $-1, %r14d
jmp .LBB2_11
.LBB2_2:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %ebx
movq %r14, (%rsp) # 8-byte Spill
movl %r14d, %ebp
imull %eax, %ebp
movslq %ebp, %r14
leaq (,%r14,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
callq malloc
movq %rax, %r12
movq %r13, %rdi
callq malloc
movq %rax, %r13
movl %ebp, %edx
testl %r14d, %r14d
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
movl $1, %eax
xorl %ecx, %ecx
movl $3435973837, %esi # imm = 0xCCCCCCCD
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, %edi
imulq %rsi, %rdi
shrq $35, %rdi
addl %edi, %edi
leal (%rdi,%rdi,4), %edi
movl %eax, %r8d
subl %edi, %r8d
xorps %xmm0, %xmm0
cvtsi2ss %r8d, %xmm0
movss %xmm0, (%r15,%rcx,4)
incq %rcx
incl %eax
cmpq %rcx, %rdx
jne .LBB2_4
.LBB2_5: # %.preheader67
movq (%rsp), %r11 # 8-byte Reload
shlq $32, %r11
testl %ebp, %ebp
jle .LBB2_8
# %bb.6: # %.lr.ph70.preheader
leaq (,%rdx,4), %rax
movl $2, %ecx
movl $1, %esi
xorl %edi, %edi
movl $3123612579, %r8d # imm = 0xBA2E8BA3
.p2align 4, 0x90
.LBB2_7: # %.lr.ph70
# =>This Inner Loop Header: Depth=1
movl %esi, %r9d
imulq %r8, %r9
shrq $35, %r9
leal (%r9,%r9,4), %r10d
leal (%r9,%r10,2), %r9d
movl %ecx, %r10d
subl %r9d, %r10d
xorps %xmm0, %xmm0
cvtsi2ss %r10d, %xmm0
movss %xmm0, (%r12,%rdi)
addq $4, %rdi
incl %ecx
incl %esi
cmpq %rdi, %rax
jne .LBB2_7
.LBB2_8: # %.preheader66
orq %r11, %rbx
testl %ebp, %ebp
jle .LBB2_10
# %bb.9: # %.lr.ph72.preheader
shlq $2, %rdx
movq %r13, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB2_10: # %._crit_edge
xorl %r14d, %r14d
movl $tGS, %edi
xorl %esi, %esi
callq gettimeofday
movq %rbx, %rdi
movq %r15, %rsi
movq %rbx, %rdx
movq %r12, %rcx
movq %rbx, %r8
movq %r13, %r9
callq _Z6MatSum6MatrixS_S_
movl $tGF, %edi
xorl %esi, %esi
callq gettimeofday
movl $tCS, %edi
xorl %esi, %esi
callq gettimeofday
movl $tCF, %edi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq tCF(%rip), %xmm1
movsd .LCPI2_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq tCF+8(%rip), %xmm0
divsd %xmm3, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq tGS(%rip), %xmm1
cvtsi2sdq tGS+8(%rip), %xmm2
mulsd %xmm3, %xmm1
divsd %xmm3, %xmm2
addsd %xmm1, %xmm2
subsd %xmm2, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorps %xmm1, %xmm1
cvtsi2sdq tKF(%rip), %xmm1
movsd .LCPI2_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq tKF+8(%rip), %xmm0
divsd %xmm3, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq tKS(%rip), %xmm1
xorps %xmm2, %xmm2
cvtsi2sdq tKS+8(%rip), %xmm2
mulsd %xmm3, %xmm1
divsd %xmm3, %xmm2
addsd %xmm1, %xmm2
subsd %xmm2, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorps %xmm1, %xmm1
cvtsi2sdq tGF(%rip), %xmm1
movsd .LCPI2_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq tGF+8(%rip), %xmm0
divsd %xmm3, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq tGS(%rip), %xmm1
xorps %xmm2, %xmm2
cvtsi2sdq tGS+8(%rip), %xmm2
mulsd %xmm3, %xmm1
divsd %xmm3, %xmm2
addsd %xmm1, %xmm2
subsd %xmm2, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorps %xmm1, %xmm1
cvtsi2sdq tCF(%rip), %xmm1
movsd .LCPI2_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq tCF+8(%rip), %xmm0
divsd %xmm3, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq tCS(%rip), %xmm1
xorps %xmm2, %xmm2
cvtsi2sdq tCS+8(%rip), %xmm2
mulsd %xmm3, %xmm1
divsd %xmm3, %xmm2
addsd %xmm1, %xmm2
subsd %xmm2, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
.LBB2_11:
movl %r14d, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatSumKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type tGS,@object # @tGS
.bss
.globl tGS
.p2align 3, 0x0
tGS:
.zero 16
.size tGS, 16
.type tGF,@object # @tGF
.globl tGF
.p2align 3, 0x0
tGF:
.zero 16
.size tGF, 16
.type tKS,@object # @tKS
.globl tKS
.p2align 3, 0x0
tKS:
.zero 16
.size tKS, 16
.type tKF,@object # @tKF
.globl tKF
.p2align 3, 0x0
tKF:
.zero 16
.size tKF, 16
.type tCS,@object # @tCS
.globl tCS
.p2align 3, 0x0
tCS:
.zero 16
.size tCS, 16
.type tCF,@object # @tCF
.globl tCF
.p2align 3, 0x0
tCF:
.zero 16
.size tCF, 16
.type _Z12MatSumKernel6MatrixS_S_,@object # @_Z12MatSumKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatSumKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatSumKernel6MatrixS_S_:
.quad _Z27__device_stub__MatSumKernel6MatrixS_S_
.size _Z12MatSumKernel6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s nLines nColumns\n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " total=%8.2f\n"
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "kernel=%8.2f\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " gpu=%8.2f\n"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " cpu=%8.2f\n"
.size .L.str.4, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatSumKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatSumKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym tGS
.addrsig_sym tGF
.addrsig_sym tKS
.addrsig_sym tKF
.addrsig_sym tCS
.addrsig_sym tCF
.addrsig_sym _Z12MatSumKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // iamgroot42
// Code for reading files and loading into memory used from the CPU template provided with the assignment
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
#define LINEWIDTH 20
#define KEYWORD 32
#define CHUNKSIZE 4
__global__ void matchPattern(unsigned int *text, unsigned int *words, int *matches, int length){
__shared__ unsigned int shared_words[CHUNKSIZE+1];
__shared__ unsigned int keywords[KEYWORD];
__shared__ int frequencies[KEYWORD];
unsigned int word, next_word, offset1, offset2, offset3;
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int match_count = 0;
if(i<length){
// Load keywords, initialize blockwise frequencies
if(threadIdx.x==0){
keywords[threadIdx.y] = words[threadIdx.y];
frequencies[threadIdx.y] = 0;
}
// Load text
if(threadIdx.y==0){
shared_words[threadIdx.x] = text[i];
if(threadIdx.x+1==CHUNKSIZE){
shared_words[CHUNKSIZE] = text[i+1];
}
}
__syncthreads();
// Matching logic
word = shared_words[threadIdx.x];
next_word = shared_words[threadIdx.x+1];
offset1 = (word>>8) + (next_word<<24);
offset2 = (word>>16) + (next_word<<16);
offset3 = (word>>24) + (next_word<<8);
match_count += (word==keywords[threadIdx.y]);
match_count += (offset1==keywords[threadIdx.y]);
match_count += (offset2==keywords[threadIdx.y]);
match_count += (offset3==keywords[threadIdx.y]);
// Increment shared counters
atomicAdd(&frequencies[threadIdx.y], match_count);
__syncthreads();
// Incrememnt global histogram
if(threadIdx.x == 0){
atomicAdd(&matches[threadIdx.y], frequencies[threadIdx.y]);
}
}
}
int main(){
int length, len, matches[KEYWORD];
int* cuda_matches;
char *ctext, keywords[KEYWORD][LINEWIDTH], *line;
cudaMallocHost(&line, sizeof(char)*LINEWIDTH);
unsigned int *text, *words;
unsigned int *cuda_text, *cuda_words;
memset(matches, -1, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile){ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = KEYWORD;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--){
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen("./data/large.txt","r");
if (!fp){ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
cudaMallocHost(&ctext, length+4);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
cudaMallocHost(&words, KEYWORD*sizeof(unsigned int));
for (int w=0; w<KEYWORD; w++){
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
cudaMalloc((void**) &cuda_text, length+4);
cudaMalloc((void**) &cuda_words, KEYWORD*sizeof(unsigned int));
cudaMalloc((void**) &cuda_matches, sizeof(matches));
cudaMemcpy(cuda_text, text, length+4, cudaMemcpyHostToDevice);
cudaMemcpy(cuda_words, words, KEYWORD*sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaMemset(cuda_matches, 0, sizeof(matches));
cudaMemset(cuda_matches, 0, sizeof(matches));
dim3 threadsPerBlock(CHUNKSIZE, KEYWORD);
dim3 numBlocks(len/CHUNKSIZE);
matchPattern<<<numBlocks, threadsPerBlock>>>(cuda_text, cuda_words, cuda_matches, len);
cudaMemcpy(matches, cuda_matches, sizeof(matches), cudaMemcpyDeviceToHost);
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < KEYWORD; ++i)
printf("%s\t |\t%d\n", keywords[i], matches[i]);
cudaFree(ctext);
cudaFree(words);
cudaFree(line);
cudaFree(cuda_text);
cudaFree(cuda_words);
cudaFree(cuda_matches);
return 0;
} | code for sm_80
Function : _Z12matchPatternPjS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0207 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0070*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ BSSY B0, 0x120 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*00a0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x001fd40003f25270 */
/*00b0*/ @P0 BRA 0x110 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE.U32 R2, R9, R2, c[0x0][0x168] ; /* 0x00005a0009027625 */
/* 0x000fcc00078e0002 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STS [R9.X4+0x94], RZ ; /* 0x000094ff09007388 */
/* 0x0001e80000004800 */
/*0100*/ STS [R9.X4+0x14], R2 ; /* 0x0000140209007388 */
/* 0x0041e40000004800 */
/*0110*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0120*/ BSSY B0, 0x1c0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0130*/ @P1 BRA 0x1b0 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.NE.AND P1, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe20003f25270 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0203 */
/*0170*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0180*/ @!P1 LDG.E R4, [R2.64+0x4] ; /* 0x0000040402049981 */
/* 0x000ee8000c1e1900 */
/*0190*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0041e80000004800 */
/*01a0*/ @!P1 STS [0x10], R4 ; /* 0x00001004ff009388 */
/* 0x0081e40000000800 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x2 ; /* 0x00000002ff067424 */
/* 0x000fca00078e00ff */
/*01e0*/ LDS R0, [R7.X4] ; /* 0x0000000007007984 */
/* 0x001fe80000004800 */
/*01f0*/ LDS R5, [R9.X4+0x14] ; /* 0x0000140009057984 */
/* 0x000e280000004800 */
/*0200*/ LDS R3, [R7.X4+0x4] ; /* 0x0000040007037984 */
/* 0x000e620000004800 */
/*0210*/ ISETP.NE.AND P2, PT, R0.reuse, R5, PT ; /* 0x000000050000720c */
/* 0x041fe40003f45270 */
/*0220*/ SHF.L.U32.HI R2, R0, 0x18, R3 ; /* 0x0000001800027819 */
/* 0x002fc40000010603 */
/*0230*/ SEL R4, RZ, 0x1, P2 ; /* 0x00000001ff047807 */
/* 0x000fe40001000000 */
/*0240*/ ISETP.NE.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f25270 */
/*0250*/ SHF.L.U32.HI R2, R0.reuse, 0x10, R3.reuse ; /* 0x0000001000027819 */
/* 0x140fe40000010603 */
/*0260*/ SHF.L.U32.HI R0, R0, 0x8, R3 ; /* 0x0000000800007819 */
/* 0x000fc60000010603 */
/*0270*/ @P2 IMAD.MOV R6, RZ, RZ, 0x1 ; /* 0x00000001ff062424 */
/* 0x000fe200078e02ff */
/*0280*/ ISETP.NE.AND P2, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fca0003f45270 */
/*0290*/ @P1 IMAD.MOV R6, RZ, RZ, R4 ; /* 0x000000ffff061224 */
/* 0x000fe200078e0204 */
/*02a0*/ ISETP.NE.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fc80003f25270 */
/*02b0*/ IADD3 R2, R6, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x000fc60007ffe0ff */
/*02c0*/ @P2 IMAD.MOV R2, RZ, RZ, R6 ; /* 0x000000ffff022224 */
/* 0x000fca00078e0206 */
/*02d0*/ IADD3 R0, R2, 0x1, RZ ; /* 0x0000000102007810 */
/* 0x000fe20007ffe0ff */
/*02e0*/ @P1 IMAD.MOV R0, RZ, RZ, R2 ; /* 0x000000ffff001224 */
/* 0x000fca00078e0202 */
/*02f0*/ ATOMS.ADD RZ, [R9.X4+0x94], R0 ; /* 0x0000940009ff738c */
/* 0x0001e80000004000 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0320*/ LDS R5, [R9.X4+0x94] ; /* 0x0000940009057984 */
/* 0x001e220000004800 */
/*0330*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0340*/ IMAD.WIDE.U32 R2, R9, R2, c[0x0][0x170] ; /* 0x00005c0009027625 */
/* 0x000fca00078e0002 */
/*0350*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ BRA 0x370; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // iamgroot42
// Code for reading files and loading into memory used from the CPU template provided with the assignment
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
#define LINEWIDTH 20
#define KEYWORD 32
#define CHUNKSIZE 4
__global__ void matchPattern(unsigned int *text, unsigned int *words, int *matches, int length){
__shared__ unsigned int shared_words[CHUNKSIZE+1];
__shared__ unsigned int keywords[KEYWORD];
__shared__ int frequencies[KEYWORD];
unsigned int word, next_word, offset1, offset2, offset3;
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int match_count = 0;
if(i<length){
// Load keywords, initialize blockwise frequencies
if(threadIdx.x==0){
keywords[threadIdx.y] = words[threadIdx.y];
frequencies[threadIdx.y] = 0;
}
// Load text
if(threadIdx.y==0){
shared_words[threadIdx.x] = text[i];
if(threadIdx.x+1==CHUNKSIZE){
shared_words[CHUNKSIZE] = text[i+1];
}
}
__syncthreads();
// Matching logic
word = shared_words[threadIdx.x];
next_word = shared_words[threadIdx.x+1];
offset1 = (word>>8) + (next_word<<24);
offset2 = (word>>16) + (next_word<<16);
offset3 = (word>>24) + (next_word<<8);
match_count += (word==keywords[threadIdx.y]);
match_count += (offset1==keywords[threadIdx.y]);
match_count += (offset2==keywords[threadIdx.y]);
match_count += (offset3==keywords[threadIdx.y]);
// Increment shared counters
atomicAdd(&frequencies[threadIdx.y], match_count);
__syncthreads();
// Incrememnt global histogram
if(threadIdx.x == 0){
atomicAdd(&matches[threadIdx.y], frequencies[threadIdx.y]);
}
}
}
int main(){
int length, len, matches[KEYWORD];
int* cuda_matches;
char *ctext, keywords[KEYWORD][LINEWIDTH], *line;
cudaMallocHost(&line, sizeof(char)*LINEWIDTH);
unsigned int *text, *words;
unsigned int *cuda_text, *cuda_words;
memset(matches, -1, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile){ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = KEYWORD;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--){
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen("./data/large.txt","r");
if (!fp){ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
cudaMallocHost(&ctext, length+4);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
cudaMallocHost(&words, KEYWORD*sizeof(unsigned int));
for (int w=0; w<KEYWORD; w++){
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
cudaMalloc((void**) &cuda_text, length+4);
cudaMalloc((void**) &cuda_words, KEYWORD*sizeof(unsigned int));
cudaMalloc((void**) &cuda_matches, sizeof(matches));
cudaMemcpy(cuda_text, text, length+4, cudaMemcpyHostToDevice);
cudaMemcpy(cuda_words, words, KEYWORD*sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaMemset(cuda_matches, 0, sizeof(matches));
cudaMemset(cuda_matches, 0, sizeof(matches));
dim3 threadsPerBlock(CHUNKSIZE, KEYWORD);
dim3 numBlocks(len/CHUNKSIZE);
matchPattern<<<numBlocks, threadsPerBlock>>>(cuda_text, cuda_words, cuda_matches, len);
cudaMemcpy(matches, cuda_matches, sizeof(matches), cudaMemcpyDeviceToHost);
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < KEYWORD; ++i)
printf("%s\t |\t%d\n", keywords[i], matches[i]);
cudaFree(ctext);
cudaFree(words);
cudaFree(line);
cudaFree(cuda_text);
cudaFree(cuda_words);
cudaFree(cuda_matches);
return 0;
} | .file "tmpxft_001b82bd_00000000-6_pattern_GPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii
.type _Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii, @function
_Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matchPatternPjS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii, .-_Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii
.globl _Z12matchPatternPjS_Pii
.type _Z12matchPatternPjS_Pii, @function
_Z12matchPatternPjS_Pii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12matchPatternPjS_Pii, .-_Z12matchPatternPjS_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "./data/keywords.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "keywords.txt: File not found.\n"
.section .rodata.str1.1
.LC3:
.string "./data/large.txt"
.LC4:
.string "Unable to open the file.\n"
.LC5:
.string "Printing Matches:\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Word\t |\tNumber of Matches\n===================================\n"
.section .rodata.str1.1
.LC7:
.string "%s\t |\t%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $864, %rsp
.cfi_def_cfa_offset 912
movq %fs:40, %rax
movq %rax, 856(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $0, %edx
movl $20, %esi
call cudaHostAlloc@PLT
pcmpeqd %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movaps %xmm0, 96(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm0, 144(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 192(%rsp)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L30
movq %rax, %rbp
movq $20, 48(%rsp)
movl $0, %ebx
leaq 48(%rsp), %r12
.L14:
leaq 16(%rsp), %rdi
movq %rbp, %rcx
movl $10, %edx
movq %r12, %rsi
call __getdelim@PLT
cmpq $-1, %rax
je .L13
cmpq $640, %rbx
je .L13
movl $640, %ecx
cmpq %rcx, %rbx
cmovnb %rbx, %rcx
subq %rbx, %rcx
leaq 208(%rsp,%rbx), %rdi
movl $8, %edx
movq 16(%rsp), %rsi
call __strncpy_chk@PLT
movb $0, 212(%rsp,%rbx)
addq $20, %rbx
jmp .L14
.L30:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L13:
movq %rbp, %rdi
call fclose@PLT
leaq .LC0(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L31
movl $0, %r12d
.L15:
movq %rbp, %rdi
call getc@PLT
cmpl $-1, %eax
je .L32
addl $1, %r12d
jmp .L15
.L31:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L32:
leal 4(%r12), %r13d
movslq %r13d, %r13
leaq 8(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
movq %rbp, %rdi
call rewind@PLT
testl %r12d, %r12d
jle .L17
movslq %r12d, %r14
movl $0, %ebx
.L18:
movq %rbp, %rdi
call getc@PLT
movq 8(%rsp), %rdx
movb %al, (%rdx,%rbx)
addq $1, %rbx
cmpq %r14, %rbx
jne .L18
.L17:
movslq %r12d, %rax
leaq 4(%rax), %rcx
.L19:
movq 8(%rsp), %rdx
movb $32, (%rdx,%rax)
addq $1, %rax
cmpq %rcx, %rax
jne .L19
movq %rbp, %rdi
call fclose@PLT
movq 8(%rsp), %r14
leaq 24(%rsp), %rdi
movl $0, %edx
movl $128, %esi
call cudaHostAlloc@PLT
leaq 208(%rsp), %rbx
leaq 848(%rsp), %rbp
movq %rbx, %rax
movl $0, %ecx
.L20:
movsbl 3(%rax), %edx
sall $8, %edx
movsbl 2(%rax), %esi
addl %esi, %edx
sall $8, %edx
movsbl 1(%rax), %esi
addl %esi, %edx
sall $8, %edx
movsbl (%rax), %esi
addl %esi, %edx
movq 24(%rsp), %rsi
movl %edx, (%rsi,%rcx)
addq $20, %rax
addq $4, %rcx
cmpq %rbp, %rax
jne .L20
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movq %rsp, %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, %edx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $128, %edx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $4, 56(%rsp)
movl $32, 60(%rsp)
movl $1, 64(%rsp)
leal 15(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $4, %eax
movl %eax, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L21:
leaq 80(%rsp), %r12
movl $2, %ecx
movl $128, %edx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %r13
.L22:
movl (%r12), %ecx
movq %rbx, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r12
addq $20, %rbx
cmpq %rbp, %rbx
jne .L22
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 856(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $864, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl $4, %ecx
movl %r12d, %eax
cltd
idivl %ecx
movl %eax, %ecx
movq (%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii
jmp .L21
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z12matchPatternPjS_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matchPatternPjS_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // iamgroot42
// Code for reading files and loading into memory used from the CPU template provided with the assignment
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
#define LINEWIDTH 20
#define KEYWORD 32
#define CHUNKSIZE 4
__global__ void matchPattern(unsigned int *text, unsigned int *words, int *matches, int length){
__shared__ unsigned int shared_words[CHUNKSIZE+1];
__shared__ unsigned int keywords[KEYWORD];
__shared__ int frequencies[KEYWORD];
unsigned int word, next_word, offset1, offset2, offset3;
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int match_count = 0;
if(i<length){
// Load keywords, initialize blockwise frequencies
if(threadIdx.x==0){
keywords[threadIdx.y] = words[threadIdx.y];
frequencies[threadIdx.y] = 0;
}
// Load text
if(threadIdx.y==0){
shared_words[threadIdx.x] = text[i];
if(threadIdx.x+1==CHUNKSIZE){
shared_words[CHUNKSIZE] = text[i+1];
}
}
__syncthreads();
// Matching logic
word = shared_words[threadIdx.x];
next_word = shared_words[threadIdx.x+1];
offset1 = (word>>8) + (next_word<<24);
offset2 = (word>>16) + (next_word<<16);
offset3 = (word>>24) + (next_word<<8);
match_count += (word==keywords[threadIdx.y]);
match_count += (offset1==keywords[threadIdx.y]);
match_count += (offset2==keywords[threadIdx.y]);
match_count += (offset3==keywords[threadIdx.y]);
// Increment shared counters
atomicAdd(&frequencies[threadIdx.y], match_count);
__syncthreads();
// Incrememnt global histogram
if(threadIdx.x == 0){
atomicAdd(&matches[threadIdx.y], frequencies[threadIdx.y]);
}
}
}
int main(){
int length, len, matches[KEYWORD];
int* cuda_matches;
char *ctext, keywords[KEYWORD][LINEWIDTH], *line;
cudaMallocHost(&line, sizeof(char)*LINEWIDTH);
unsigned int *text, *words;
unsigned int *cuda_text, *cuda_words;
memset(matches, -1, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile){ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = KEYWORD;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--){
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen("./data/large.txt","r");
if (!fp){ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
cudaMallocHost(&ctext, length+4);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
cudaMallocHost(&words, KEYWORD*sizeof(unsigned int));
for (int w=0; w<KEYWORD; w++){
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
cudaMalloc((void**) &cuda_text, length+4);
cudaMalloc((void**) &cuda_words, KEYWORD*sizeof(unsigned int));
cudaMalloc((void**) &cuda_matches, sizeof(matches));
cudaMemcpy(cuda_text, text, length+4, cudaMemcpyHostToDevice);
cudaMemcpy(cuda_words, words, KEYWORD*sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaMemset(cuda_matches, 0, sizeof(matches));
cudaMemset(cuda_matches, 0, sizeof(matches));
dim3 threadsPerBlock(CHUNKSIZE, KEYWORD);
dim3 numBlocks(len/CHUNKSIZE);
matchPattern<<<numBlocks, threadsPerBlock>>>(cuda_text, cuda_words, cuda_matches, len);
cudaMemcpy(matches, cuda_matches, sizeof(matches), cudaMemcpyDeviceToHost);
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < KEYWORD; ++i)
printf("%s\t |\t%d\n", keywords[i], matches[i]);
cudaFree(ctext);
cudaFree(words);
cudaFree(line);
cudaFree(cuda_text);
cudaFree(cuda_words);
cudaFree(cuda_matches);
return 0;
} | // iamgroot42
// Code for reading files and loading into memory used from the CPU template provided with the assignment
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
#define LINEWIDTH 20
#define KEYWORD 32
#define CHUNKSIZE 4
__global__ void matchPattern(unsigned int *text, unsigned int *words, int *matches, int length){
__shared__ unsigned int shared_words[CHUNKSIZE+1];
__shared__ unsigned int keywords[KEYWORD];
__shared__ int frequencies[KEYWORD];
unsigned int word, next_word, offset1, offset2, offset3;
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int match_count = 0;
if(i<length){
// Load keywords, initialize blockwise frequencies
if(threadIdx.x==0){
keywords[threadIdx.y] = words[threadIdx.y];
frequencies[threadIdx.y] = 0;
}
// Load text
if(threadIdx.y==0){
shared_words[threadIdx.x] = text[i];
if(threadIdx.x+1==CHUNKSIZE){
shared_words[CHUNKSIZE] = text[i+1];
}
}
__syncthreads();
// Matching logic
word = shared_words[threadIdx.x];
next_word = shared_words[threadIdx.x+1];
offset1 = (word>>8) + (next_word<<24);
offset2 = (word>>16) + (next_word<<16);
offset3 = (word>>24) + (next_word<<8);
match_count += (word==keywords[threadIdx.y]);
match_count += (offset1==keywords[threadIdx.y]);
match_count += (offset2==keywords[threadIdx.y]);
match_count += (offset3==keywords[threadIdx.y]);
// Increment shared counters
atomicAdd(&frequencies[threadIdx.y], match_count);
__syncthreads();
// Incrememnt global histogram
if(threadIdx.x == 0){
atomicAdd(&matches[threadIdx.y], frequencies[threadIdx.y]);
}
}
}
int main(){
int length, len, matches[KEYWORD];
int* cuda_matches;
char *ctext, keywords[KEYWORD][LINEWIDTH], *line;
hipHostMalloc(&line, sizeof(char)*LINEWIDTH, hipHostMallocDefault);
unsigned int *text, *words;
unsigned int *cuda_text, *cuda_words;
memset(matches, -1, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile){ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = KEYWORD;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--){
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen("./data/large.txt","r");
if (!fp){ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
hipHostMalloc(&ctext, length+4, hipHostMallocDefault);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
hipHostMalloc(&words, KEYWORD*sizeof(unsigned int), hipHostMallocDefault);
for (int w=0; w<KEYWORD; w++){
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
hipMalloc((void**) &cuda_text, length+4);
hipMalloc((void**) &cuda_words, KEYWORD*sizeof(unsigned int));
hipMalloc((void**) &cuda_matches, sizeof(matches));
hipMemcpy(cuda_text, text, length+4, hipMemcpyHostToDevice);
hipMemcpy(cuda_words, words, KEYWORD*sizeof(unsigned int), hipMemcpyHostToDevice);
hipMemset(cuda_matches, 0, sizeof(matches));
hipMemset(cuda_matches, 0, sizeof(matches));
dim3 threadsPerBlock(CHUNKSIZE, KEYWORD);
dim3 numBlocks(len/CHUNKSIZE);
matchPattern<<<numBlocks, threadsPerBlock>>>(cuda_text, cuda_words, cuda_matches, len);
hipMemcpy(matches, cuda_matches, sizeof(matches), hipMemcpyDeviceToHost);
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < KEYWORD; ++i)
printf("%s\t |\t%d\n", keywords[i], matches[i]);
hipFree(ctext);
hipFree(words);
hipFree(line);
hipFree(cuda_text);
hipFree(cuda_words);
hipFree(cuda_matches);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // iamgroot42
// Code for reading files and loading into memory used from the CPU template provided with the assignment
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
#define LINEWIDTH 20
#define KEYWORD 32
#define CHUNKSIZE 4
__global__ void matchPattern(unsigned int *text, unsigned int *words, int *matches, int length){
__shared__ unsigned int shared_words[CHUNKSIZE+1];
__shared__ unsigned int keywords[KEYWORD];
__shared__ int frequencies[KEYWORD];
unsigned int word, next_word, offset1, offset2, offset3;
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int match_count = 0;
if(i<length){
// Load keywords, initialize blockwise frequencies
if(threadIdx.x==0){
keywords[threadIdx.y] = words[threadIdx.y];
frequencies[threadIdx.y] = 0;
}
// Load text
if(threadIdx.y==0){
shared_words[threadIdx.x] = text[i];
if(threadIdx.x+1==CHUNKSIZE){
shared_words[CHUNKSIZE] = text[i+1];
}
}
__syncthreads();
// Matching logic
word = shared_words[threadIdx.x];
next_word = shared_words[threadIdx.x+1];
offset1 = (word>>8) + (next_word<<24);
offset2 = (word>>16) + (next_word<<16);
offset3 = (word>>24) + (next_word<<8);
match_count += (word==keywords[threadIdx.y]);
match_count += (offset1==keywords[threadIdx.y]);
match_count += (offset2==keywords[threadIdx.y]);
match_count += (offset3==keywords[threadIdx.y]);
// Increment shared counters
atomicAdd(&frequencies[threadIdx.y], match_count);
__syncthreads();
// Incrememnt global histogram
if(threadIdx.x == 0){
atomicAdd(&matches[threadIdx.y], frequencies[threadIdx.y]);
}
}
}
int main(){
int length, len, matches[KEYWORD];
int* cuda_matches;
char *ctext, keywords[KEYWORD][LINEWIDTH], *line;
hipHostMalloc(&line, sizeof(char)*LINEWIDTH, hipHostMallocDefault);
unsigned int *text, *words;
unsigned int *cuda_text, *cuda_words;
memset(matches, -1, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile){ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = KEYWORD;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--){
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen("./data/large.txt","r");
if (!fp){ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
hipHostMalloc(&ctext, length+4, hipHostMallocDefault);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
hipHostMalloc(&words, KEYWORD*sizeof(unsigned int), hipHostMallocDefault);
for (int w=0; w<KEYWORD; w++){
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
hipMalloc((void**) &cuda_text, length+4);
hipMalloc((void**) &cuda_words, KEYWORD*sizeof(unsigned int));
hipMalloc((void**) &cuda_matches, sizeof(matches));
hipMemcpy(cuda_text, text, length+4, hipMemcpyHostToDevice);
hipMemcpy(cuda_words, words, KEYWORD*sizeof(unsigned int), hipMemcpyHostToDevice);
hipMemset(cuda_matches, 0, sizeof(matches));
hipMemset(cuda_matches, 0, sizeof(matches));
dim3 threadsPerBlock(CHUNKSIZE, KEYWORD);
dim3 numBlocks(len/CHUNKSIZE);
matchPattern<<<numBlocks, threadsPerBlock>>>(cuda_text, cuda_words, cuda_matches, len);
hipMemcpy(matches, cuda_matches, sizeof(matches), hipMemcpyDeviceToHost);
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < KEYWORD; ++i)
printf("%s\t |\t%d\n", keywords[i], matches[i]);
hipFree(ctext);
hipFree(words);
hipFree(line);
hipFree(cuda_text);
hipFree(cuda_words);
hipFree(cuda_matches);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matchPatternPjS_Pii
.globl _Z12matchPatternPjS_Pii
.p2align 8
.type _Z12matchPatternPjS_Pii,@function
_Z12matchPatternPjS_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_8
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
v_lshrrev_b32_e32 v3, 8, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2)
v_and_b32_e32 v3, 0xffc, v3
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[4:5]
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v3, v5, v4 offset1:32
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v5, 2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s2, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s2, s5, v3, s2
v_cmp_eq_u32_e64 s2, 3, v1
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:256
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_6
global_load_b32 v2, v[2:3], off offset:4
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2 offset:272
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v1, 2, v1
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[1:2], v1 offset0:64 offset1:65
ds_load_b32 v3, v0 offset:128
s_waitcnt lgkmcnt(1)
v_perm_b32 v4, v1, v2, 0x70605
v_perm_b32 v5, v1, v2, 0x1000706
v_perm_b32 v2, v1, v2, 0x2010007
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, v4, v3
v_cndmask_b32_e64 v4, 0, 1, s2
v_cmp_eq_u32_e64 s2, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s2, 0, v4, s2
v_cmp_eq_u32_e64 s2, v5, v3
v_cndmask_b32_e64 v4, 0, 1, s2
v_cmp_eq_u32_e64 s2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s2, v1, v4, s2
ds_add_u32 v0, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matchPatternPjS_Pii
.amdhsa_group_segment_fixed_size 276
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matchPatternPjS_Pii, .Lfunc_end0-_Z12matchPatternPjS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 276
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matchPatternPjS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matchPatternPjS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // iamgroot42
// Code for reading files and loading into memory used from the CPU template provided with the assignment
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
#define LINEWIDTH 20
#define KEYWORD 32
#define CHUNKSIZE 4
__global__ void matchPattern(unsigned int *text, unsigned int *words, int *matches, int length){
__shared__ unsigned int shared_words[CHUNKSIZE+1];
__shared__ unsigned int keywords[KEYWORD];
__shared__ int frequencies[KEYWORD];
unsigned int word, next_word, offset1, offset2, offset3;
int i = (blockIdx.x * blockDim.x) + threadIdx.x;
int match_count = 0;
if(i<length){
// Load keywords, initialize blockwise frequencies
if(threadIdx.x==0){
keywords[threadIdx.y] = words[threadIdx.y];
frequencies[threadIdx.y] = 0;
}
// Load text
if(threadIdx.y==0){
shared_words[threadIdx.x] = text[i];
if(threadIdx.x+1==CHUNKSIZE){
shared_words[CHUNKSIZE] = text[i+1];
}
}
__syncthreads();
// Matching logic
word = shared_words[threadIdx.x];
next_word = shared_words[threadIdx.x+1];
offset1 = (word>>8) + (next_word<<24);
offset2 = (word>>16) + (next_word<<16);
offset3 = (word>>24) + (next_word<<8);
match_count += (word==keywords[threadIdx.y]);
match_count += (offset1==keywords[threadIdx.y]);
match_count += (offset2==keywords[threadIdx.y]);
match_count += (offset3==keywords[threadIdx.y]);
// Increment shared counters
atomicAdd(&frequencies[threadIdx.y], match_count);
__syncthreads();
// Incrememnt global histogram
if(threadIdx.x == 0){
atomicAdd(&matches[threadIdx.y], frequencies[threadIdx.y]);
}
}
}
int main(){
int length, len, matches[KEYWORD];
int* cuda_matches;
char *ctext, keywords[KEYWORD][LINEWIDTH], *line;
hipHostMalloc(&line, sizeof(char)*LINEWIDTH, hipHostMallocDefault);
unsigned int *text, *words;
unsigned int *cuda_text, *cuda_words;
memset(matches, -1, sizeof(matches));
// read in text and keywords for processing
FILE *fp, *wfile;
wfile = fopen("./data/keywords.txt","r");
if (!wfile){ printf("keywords.txt: File not found.\n"); exit(0);}
int k=0, cnt = KEYWORD;
size_t read, linelen = LINEWIDTH;
while((read = getline(&line, &linelen, wfile)) != -1 && cnt--){
strncpy(keywords[k], line, sizeof(line));
keywords[k][4] = '\0';
k++;
}
fclose(wfile);
fp = fopen("./data/large.txt","r");
if (!fp){ printf("Unable to open the file.\n"); exit(0);}
length = 0;
while (getc(fp) != EOF) length++;
hipHostMalloc(&ctext, length+4, hipHostMallocDefault);
rewind(fp);
for (int l=0; l<length; l++) ctext[l] = getc(fp);
for (int l=length; l<length+4; l++) ctext[l] = ' ';
fclose(fp);
// define number of words of text, and set pointers
len = length/4;
text = (unsigned int *) ctext;
// define words for matching
hipHostMalloc(&words, KEYWORD*sizeof(unsigned int), hipHostMallocDefault);
for (int w=0; w<KEYWORD; w++){
words[w] = ((unsigned int) keywords[w][0])
+ ((unsigned int) keywords[w][1])*(1<<8)
+ ((unsigned int) keywords[w][2])*(1<<16)
+ ((unsigned int) keywords[w][3])*(1<<24);
}
hipMalloc((void**) &cuda_text, length+4);
hipMalloc((void**) &cuda_words, KEYWORD*sizeof(unsigned int));
hipMalloc((void**) &cuda_matches, sizeof(matches));
hipMemcpy(cuda_text, text, length+4, hipMemcpyHostToDevice);
hipMemcpy(cuda_words, words, KEYWORD*sizeof(unsigned int), hipMemcpyHostToDevice);
hipMemset(cuda_matches, 0, sizeof(matches));
hipMemset(cuda_matches, 0, sizeof(matches));
dim3 threadsPerBlock(CHUNKSIZE, KEYWORD);
dim3 numBlocks(len/CHUNKSIZE);
matchPattern<<<numBlocks, threadsPerBlock>>>(cuda_text, cuda_words, cuda_matches, len);
hipMemcpy(matches, cuda_matches, sizeof(matches), hipMemcpyDeviceToHost);
printf("Printing Matches:\n");
printf("Word\t |\tNumber of Matches\n===================================\n");
for (int i = 0; i < KEYWORD; ++i)
printf("%s\t |\t%d\n", keywords[i], matches[i]);
hipFree(ctext);
hipFree(words);
hipFree(line);
hipFree(cuda_text);
hipFree(cuda_words);
hipFree(cuda_matches);
return 0;
} | .text
.file "pattern_GPU.hip"
.globl _Z27__device_stub__matchPatternPjS_Pii # -- Begin function _Z27__device_stub__matchPatternPjS_Pii
.p2align 4, 0x90
.type _Z27__device_stub__matchPatternPjS_Pii,@function
_Z27__device_stub__matchPatternPjS_Pii: # @_Z27__device_stub__matchPatternPjS_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matchPatternPjS_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__matchPatternPjS_Pii, .Lfunc_end0-_Z27__device_stub__matchPatternPjS_Pii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $952, %rsp # imm = 0x3B8
.cfi_def_cfa_offset 992
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $20, %esi
xorl %edx, %edx
callq hipHostMalloc
pcmpeqd %xmm0, %xmm0
movdqa %xmm0, 176(%rsp)
movdqa %xmm0, 192(%rsp)
movdqa %xmm0, 208(%rsp)
movdqa %xmm0, 224(%rsp)
movdqa %xmm0, 240(%rsp)
movdqa %xmm0, 256(%rsp)
movdqa %xmm0, 272(%rsp)
movdqa %xmm0, 288(%rsp)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB1_1
# %bb.3:
movq %rax, %rbx
movq $20, 64(%rsp)
leaq 16(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $10, %edx
movq %rax, %rcx
callq __getdelim
cmpq $-1, %rax
je .LBB1_7
# %bb.4: # %.lr.ph.preheader
xorl %r12d, %r12d
leaq 16(%rsp), %r14
leaq 64(%rsp), %r15
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq (%rsp,%r12), %rdi
addq $304, %rdi # imm = 0x130
movq 16(%rsp), %rsi
movl $8, %edx
callq strncpy
movb $0, 308(%rsp,%r12)
movq %r14, %rdi
movq %r15, %rsi
movl $10, %edx
movq %rbx, %rcx
callq __getdelim
cmpq $-1, %rax
je .LBB1_7
# %bb.6: # %.lr.ph
# in Loop: Header=BB1_5 Depth=1
leaq 20(%r12), %rax
cmpl $620, %r12d # imm = 0x26C
movq %rax, %r12
jne .LBB1_5
.LBB1_7: # %.critedge
movq %rbx, %rdi
callq fclose
movl $.L.str.3, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB1_22
# %bb.8: # %.preheader63.preheader
movq %rax, %r14
movl $3, %ebx
movq $-1, %r15
.p2align 4, 0x90
.LBB1_9: # %.preheader63
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq getc
incl %ebx
incq %r15
cmpl $-1, %eax
jne .LBB1_9
# %bb.10:
movl %ebx, %ebx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
movq %r14, %rdi
callq rewind
testl %r15d, %r15d
je .LBB1_13
# %bb.11: # %.lr.ph68.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_12: # %.lr.ph68
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq getc
movq 24(%rsp), %rcx
movb %al, (%rcx,%r12)
incq %r12
cmpq %r12, %r15
jne .LBB1_12
.LBB1_13: # %.preheader
movq %r15, %rax
.p2align 4, 0x90
.LBB1_14: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rcx
movb $32, (%rcx,%rax)
incq %rax
cmpq %rax, %rbx
jne .LBB1_14
# %bb.15:
movq %r14, %rdi
callq fclose
movq 24(%rsp), %r14
leaq 48(%rsp), %rdi
movl $128, %esi
xorl %edx, %edx
callq hipHostMalloc
movl $3, %eax
movq 48(%rsp), %rcx
.p2align 4, 0x90
.LBB1_16: # =>This Inner Loop Header: Depth=1
movsbl 301(%rsp,%rax), %edx
movsbl 302(%rsp,%rax), %esi
shll $8, %esi
addl %edx, %esi
movsbl 303(%rsp,%rax), %edx
shll $16, %edx
movzbl 304(%rsp,%rax), %edi
shll $24, %edi
addl %edx, %edi
addl %esi, %edi
movl %edi, (%rcx)
addq $4, %rcx
addq $20, %rax
cmpq $643, %rax # imm = 0x283
jne .LBB1_16
# %bb.17:
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 48(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $128, %edx
xorl %esi, %esi
callq hipMemset
movq 8(%rsp), %rdi
movl $128, %edx
xorl %esi, %esi
callq hipMemset
movl %r15d, %eax
shrl $4, %eax
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rax, %rdi
movabsq $137438953476, %rdx # imm = 0x2000000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_19
# %bb.18:
shrl $2, %r15d
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r15d, 60(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z12matchPatternPjS_Pii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_19:
movq 8(%rsp), %rsi
leaq 176(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
leaq 304(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_20: # =>This Inner Loop Header: Depth=1
movl 176(%rsp,%r14,4), %edx
movl $.L.str.7, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
incq %r14
addq $20, %rbx
cmpq $32, %r14
jne .LBB1_20
# %bb.21:
movq 24(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $952, %rsp # imm = 0x3B8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 992
movl $.Lstr, %edi
jmp .LBB1_2
.LBB1_22:
movl $.Lstr.1, %edi
.LBB1_2:
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matchPatternPjS_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matchPatternPjS_Pii,@object # @_Z12matchPatternPjS_Pii
.section .rodata,"a",@progbits
.globl _Z12matchPatternPjS_Pii
.p2align 3, 0x0
_Z12matchPatternPjS_Pii:
.quad _Z27__device_stub__matchPatternPjS_Pii
.size _Z12matchPatternPjS_Pii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "./data/keywords.txt"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "./data/large.txt"
.size .L.str.3, 17
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s\t |\t%d\n"
.size .L.str.7, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12matchPatternPjS_Pii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "keywords.txt: File not found."
.size .Lstr, 30
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Unable to open the file."
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing Matches:"
.size .Lstr.2, 18
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Word\t |\tNumber of Matches\n==================================="
.size .Lstr.3, 63
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matchPatternPjS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matchPatternPjS_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12matchPatternPjS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0207 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0070*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ BSSY B0, 0x120 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*00a0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x001fd40003f25270 */
/*00b0*/ @P0 BRA 0x110 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE.U32 R2, R9, R2, c[0x0][0x168] ; /* 0x00005a0009027625 */
/* 0x000fcc00078e0002 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STS [R9.X4+0x94], RZ ; /* 0x000094ff09007388 */
/* 0x0001e80000004800 */
/*0100*/ STS [R9.X4+0x14], R2 ; /* 0x0000140209007388 */
/* 0x0041e40000004800 */
/*0110*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0120*/ BSSY B0, 0x1c0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0130*/ @P1 BRA 0x1b0 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.NE.AND P1, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe20003f25270 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0203 */
/*0170*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0180*/ @!P1 LDG.E R4, [R2.64+0x4] ; /* 0x0000040402049981 */
/* 0x000ee8000c1e1900 */
/*0190*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0041e80000004800 */
/*01a0*/ @!P1 STS [0x10], R4 ; /* 0x00001004ff009388 */
/* 0x0081e40000000800 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x2 ; /* 0x00000002ff067424 */
/* 0x000fca00078e00ff */
/*01e0*/ LDS R0, [R7.X4] ; /* 0x0000000007007984 */
/* 0x001fe80000004800 */
/*01f0*/ LDS R5, [R9.X4+0x14] ; /* 0x0000140009057984 */
/* 0x000e280000004800 */
/*0200*/ LDS R3, [R7.X4+0x4] ; /* 0x0000040007037984 */
/* 0x000e620000004800 */
/*0210*/ ISETP.NE.AND P2, PT, R0.reuse, R5, PT ; /* 0x000000050000720c */
/* 0x041fe40003f45270 */
/*0220*/ SHF.L.U32.HI R2, R0, 0x18, R3 ; /* 0x0000001800027819 */
/* 0x002fc40000010603 */
/*0230*/ SEL R4, RZ, 0x1, P2 ; /* 0x00000001ff047807 */
/* 0x000fe40001000000 */
/*0240*/ ISETP.NE.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f25270 */
/*0250*/ SHF.L.U32.HI R2, R0.reuse, 0x10, R3.reuse ; /* 0x0000001000027819 */
/* 0x140fe40000010603 */
/*0260*/ SHF.L.U32.HI R0, R0, 0x8, R3 ; /* 0x0000000800007819 */
/* 0x000fc60000010603 */
/*0270*/ @P2 IMAD.MOV R6, RZ, RZ, 0x1 ; /* 0x00000001ff062424 */
/* 0x000fe200078e02ff */
/*0280*/ ISETP.NE.AND P2, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fca0003f45270 */
/*0290*/ @P1 IMAD.MOV R6, RZ, RZ, R4 ; /* 0x000000ffff061224 */
/* 0x000fe200078e0204 */
/*02a0*/ ISETP.NE.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fc80003f25270 */
/*02b0*/ IADD3 R2, R6, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x000fc60007ffe0ff */
/*02c0*/ @P2 IMAD.MOV R2, RZ, RZ, R6 ; /* 0x000000ffff022224 */
/* 0x000fca00078e0206 */
/*02d0*/ IADD3 R0, R2, 0x1, RZ ; /* 0x0000000102007810 */
/* 0x000fe20007ffe0ff */
/*02e0*/ @P1 IMAD.MOV R0, RZ, RZ, R2 ; /* 0x000000ffff001224 */
/* 0x000fca00078e0202 */
/*02f0*/ ATOMS.ADD RZ, [R9.X4+0x94], R0 ; /* 0x0000940009ff738c */
/* 0x0001e80000004000 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0320*/ LDS R5, [R9.X4+0x94] ; /* 0x0000940009057984 */
/* 0x001e220000004800 */
/*0330*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0340*/ IMAD.WIDE.U32 R2, R9, R2, c[0x0][0x170] ; /* 0x00005c0009027625 */
/* 0x000fca00078e0002 */
/*0350*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ BRA 0x370; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matchPatternPjS_Pii
.globl _Z12matchPatternPjS_Pii
.p2align 8
.type _Z12matchPatternPjS_Pii,@function
_Z12matchPatternPjS_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_8
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
v_lshrrev_b32_e32 v3, 8, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2)
v_and_b32_e32 v3, 0xffc, v3
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[4:5]
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v3, v5, v4 offset1:32
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v5, 2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s2, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s2, s5, v3, s2
v_cmp_eq_u32_e64 s2, 3, v1
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:256
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_6
global_load_b32 v2, v[2:3], off offset:4
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2 offset:272
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v1, 2, v1
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[1:2], v1 offset0:64 offset1:65
ds_load_b32 v3, v0 offset:128
s_waitcnt lgkmcnt(1)
v_perm_b32 v4, v1, v2, 0x70605
v_perm_b32 v5, v1, v2, 0x1000706
v_perm_b32 v2, v1, v2, 0x2010007
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, v4, v3
v_cndmask_b32_e64 v4, 0, 1, s2
v_cmp_eq_u32_e64 s2, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s2, 0, v4, s2
v_cmp_eq_u32_e64 s2, v5, v3
v_cndmask_b32_e64 v4, 0, 1, s2
v_cmp_eq_u32_e64 s2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s2, v1, v4, s2
ds_add_u32 v0, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x10
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matchPatternPjS_Pii
.amdhsa_group_segment_fixed_size 276
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matchPatternPjS_Pii, .Lfunc_end0-_Z12matchPatternPjS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 276
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matchPatternPjS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matchPatternPjS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b82bd_00000000-6_pattern_GPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii
.type _Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii, @function
_Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matchPatternPjS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii, .-_Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii
.globl _Z12matchPatternPjS_Pii
.type _Z12matchPatternPjS_Pii, @function
_Z12matchPatternPjS_Pii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12matchPatternPjS_Pii, .-_Z12matchPatternPjS_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "./data/keywords.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "keywords.txt: File not found.\n"
.section .rodata.str1.1
.LC3:
.string "./data/large.txt"
.LC4:
.string "Unable to open the file.\n"
.LC5:
.string "Printing Matches:\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Word\t |\tNumber of Matches\n===================================\n"
.section .rodata.str1.1
.LC7:
.string "%s\t |\t%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $864, %rsp
.cfi_def_cfa_offset 912
movq %fs:40, %rax
movq %rax, 856(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $0, %edx
movl $20, %esi
call cudaHostAlloc@PLT
pcmpeqd %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movaps %xmm0, 96(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm0, 144(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 192(%rsp)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L30
movq %rax, %rbp
movq $20, 48(%rsp)
movl $0, %ebx
leaq 48(%rsp), %r12
.L14:
leaq 16(%rsp), %rdi
movq %rbp, %rcx
movl $10, %edx
movq %r12, %rsi
call __getdelim@PLT
cmpq $-1, %rax
je .L13
cmpq $640, %rbx
je .L13
movl $640, %ecx
cmpq %rcx, %rbx
cmovnb %rbx, %rcx
subq %rbx, %rcx
leaq 208(%rsp,%rbx), %rdi
movl $8, %edx
movq 16(%rsp), %rsi
call __strncpy_chk@PLT
movb $0, 212(%rsp,%rbx)
addq $20, %rbx
jmp .L14
.L30:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L13:
movq %rbp, %rdi
call fclose@PLT
leaq .LC0(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L31
movl $0, %r12d
.L15:
movq %rbp, %rdi
call getc@PLT
cmpl $-1, %eax
je .L32
addl $1, %r12d
jmp .L15
.L31:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L32:
leal 4(%r12), %r13d
movslq %r13d, %r13
leaq 8(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
movq %rbp, %rdi
call rewind@PLT
testl %r12d, %r12d
jle .L17
movslq %r12d, %r14
movl $0, %ebx
.L18:
movq %rbp, %rdi
call getc@PLT
movq 8(%rsp), %rdx
movb %al, (%rdx,%rbx)
addq $1, %rbx
cmpq %r14, %rbx
jne .L18
.L17:
movslq %r12d, %rax
leaq 4(%rax), %rcx
.L19:
movq 8(%rsp), %rdx
movb $32, (%rdx,%rax)
addq $1, %rax
cmpq %rcx, %rax
jne .L19
movq %rbp, %rdi
call fclose@PLT
movq 8(%rsp), %r14
leaq 24(%rsp), %rdi
movl $0, %edx
movl $128, %esi
call cudaHostAlloc@PLT
leaq 208(%rsp), %rbx
leaq 848(%rsp), %rbp
movq %rbx, %rax
movl $0, %ecx
.L20:
movsbl 3(%rax), %edx
sall $8, %edx
movsbl 2(%rax), %esi
addl %esi, %edx
sall $8, %edx
movsbl 1(%rax), %esi
addl %esi, %edx
sall $8, %edx
movsbl (%rax), %esi
addl %esi, %edx
movq 24(%rsp), %rsi
movl %edx, (%rsi,%rcx)
addq $20, %rax
addq $4, %rcx
cmpq %rbp, %rax
jne .L20
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movq %rsp, %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, %edx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $128, %edx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $4, 56(%rsp)
movl $32, 60(%rsp)
movl $1, 64(%rsp)
leal 15(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $4, %eax
movl %eax, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L21:
leaq 80(%rsp), %r12
movl $2, %ecx
movl $128, %edx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %r13
.L22:
movl (%r12), %ecx
movq %rbx, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r12
addq $20, %rbx
cmpq %rbp, %rbx
jne .L22
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 856(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $864, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl $4, %ecx
movl %r12d, %eax
cltd
idivl %ecx
movl %eax, %ecx
movq (%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z37__device_stub__Z12matchPatternPjS_PiiPjS_Pii
jmp .L21
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z12matchPatternPjS_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matchPatternPjS_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pattern_GPU.hip"
.globl _Z27__device_stub__matchPatternPjS_Pii # -- Begin function _Z27__device_stub__matchPatternPjS_Pii
.p2align 4, 0x90
.type _Z27__device_stub__matchPatternPjS_Pii,@function
_Z27__device_stub__matchPatternPjS_Pii: # @_Z27__device_stub__matchPatternPjS_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matchPatternPjS_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__matchPatternPjS_Pii, .Lfunc_end0-_Z27__device_stub__matchPatternPjS_Pii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $952, %rsp # imm = 0x3B8
.cfi_def_cfa_offset 992
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $20, %esi
xorl %edx, %edx
callq hipHostMalloc
pcmpeqd %xmm0, %xmm0
movdqa %xmm0, 176(%rsp)
movdqa %xmm0, 192(%rsp)
movdqa %xmm0, 208(%rsp)
movdqa %xmm0, 224(%rsp)
movdqa %xmm0, 240(%rsp)
movdqa %xmm0, 256(%rsp)
movdqa %xmm0, 272(%rsp)
movdqa %xmm0, 288(%rsp)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB1_1
# %bb.3:
movq %rax, %rbx
movq $20, 64(%rsp)
leaq 16(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $10, %edx
movq %rax, %rcx
callq __getdelim
cmpq $-1, %rax
je .LBB1_7
# %bb.4: # %.lr.ph.preheader
xorl %r12d, %r12d
leaq 16(%rsp), %r14
leaq 64(%rsp), %r15
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq (%rsp,%r12), %rdi
addq $304, %rdi # imm = 0x130
movq 16(%rsp), %rsi
movl $8, %edx
callq strncpy
movb $0, 308(%rsp,%r12)
movq %r14, %rdi
movq %r15, %rsi
movl $10, %edx
movq %rbx, %rcx
callq __getdelim
cmpq $-1, %rax
je .LBB1_7
# %bb.6: # %.lr.ph
# in Loop: Header=BB1_5 Depth=1
leaq 20(%r12), %rax
cmpl $620, %r12d # imm = 0x26C
movq %rax, %r12
jne .LBB1_5
.LBB1_7: # %.critedge
movq %rbx, %rdi
callq fclose
movl $.L.str.3, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB1_22
# %bb.8: # %.preheader63.preheader
movq %rax, %r14
movl $3, %ebx
movq $-1, %r15
.p2align 4, 0x90
.LBB1_9: # %.preheader63
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq getc
incl %ebx
incq %r15
cmpl $-1, %eax
jne .LBB1_9
# %bb.10:
movl %ebx, %ebx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
movq %r14, %rdi
callq rewind
testl %r15d, %r15d
je .LBB1_13
# %bb.11: # %.lr.ph68.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_12: # %.lr.ph68
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq getc
movq 24(%rsp), %rcx
movb %al, (%rcx,%r12)
incq %r12
cmpq %r12, %r15
jne .LBB1_12
.LBB1_13: # %.preheader
movq %r15, %rax
.p2align 4, 0x90
.LBB1_14: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rcx
movb $32, (%rcx,%rax)
incq %rax
cmpq %rax, %rbx
jne .LBB1_14
# %bb.15:
movq %r14, %rdi
callq fclose
movq 24(%rsp), %r14
leaq 48(%rsp), %rdi
movl $128, %esi
xorl %edx, %edx
callq hipHostMalloc
movl $3, %eax
movq 48(%rsp), %rcx
.p2align 4, 0x90
.LBB1_16: # =>This Inner Loop Header: Depth=1
movsbl 301(%rsp,%rax), %edx
movsbl 302(%rsp,%rax), %esi
shll $8, %esi
addl %edx, %esi
movsbl 303(%rsp,%rax), %edx
shll $16, %edx
movzbl 304(%rsp,%rax), %edi
shll $24, %edi
addl %edx, %edi
addl %esi, %edi
movl %edi, (%rcx)
addq $4, %rcx
addq $20, %rax
cmpq $643, %rax # imm = 0x283
jne .LBB1_16
# %bb.17:
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 48(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $128, %edx
xorl %esi, %esi
callq hipMemset
movq 8(%rsp), %rdi
movl $128, %edx
xorl %esi, %esi
callq hipMemset
movl %r15d, %eax
shrl $4, %eax
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rax, %rdi
movabsq $137438953476, %rdx # imm = 0x2000000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_19
# %bb.18:
shrl $2, %r15d
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r15d, 60(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z12matchPatternPjS_Pii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_19:
movq 8(%rsp), %rsi
leaq 176(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
leaq 304(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_20: # =>This Inner Loop Header: Depth=1
movl 176(%rsp,%r14,4), %edx
movl $.L.str.7, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
incq %r14
addq $20, %rbx
cmpq $32, %r14
jne .LBB1_20
# %bb.21:
movq 24(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $952, %rsp # imm = 0x3B8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 992
movl $.Lstr, %edi
jmp .LBB1_2
.LBB1_22:
movl $.Lstr.1, %edi
.LBB1_2:
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matchPatternPjS_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matchPatternPjS_Pii,@object # @_Z12matchPatternPjS_Pii
.section .rodata,"a",@progbits
.globl _Z12matchPatternPjS_Pii
.p2align 3, 0x0
_Z12matchPatternPjS_Pii:
.quad _Z27__device_stub__matchPatternPjS_Pii
.size _Z12matchPatternPjS_Pii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "./data/keywords.txt"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "./data/large.txt"
.size .L.str.3, 17
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%s\t |\t%d\n"
.size .L.str.7, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12matchPatternPjS_Pii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "keywords.txt: File not found."
.size .Lstr, 30
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Unable to open the file."
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing Matches:"
.size .Lstr.2, 18
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Word\t |\tNumber of Matches\n==================================="
.size .Lstr.3, 63
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matchPatternPjS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matchPatternPjS_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ForwardSigmoid(float* Z, int nRowsZ, int nColsZ, float* A)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < nRowsZ * nColsZ)
{
A[index] = 1 / (1 + exp(-Z[index]));
}
} | code for sm_80
Function : _Z14ForwardSigmoidPfiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff057424 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x230 ; /* 0x0000014000007945 */
/* 0x000fe60003800000 */
/*00f0*/ FFMA.SAT R4, -R2, R5, 0.5 ; /* 0x3f00000002047423 */
/* 0x004fca0000002105 */
/*0100*/ FFMA.RM R4, R4, R7, 12582913 ; /* 0x4b40000104047423 */
/* 0x000fc80000004007 */
/*0110*/ FADD R5, R4.reuse, -12583039 ; /* 0xcb40007f04057421 */
/* 0x040fe40000000000 */
/*0120*/ IMAD.SHL.U32 R4, R4, 0x800000, RZ ; /* 0x0080000004047824 */
/* 0x000fe400078e00ff */
/*0130*/ FFMA R5, -R2, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b02057823 */
/* 0x000fc80000000905 */
/*0140*/ FFMA R5, -R2, 1.925963033500011079e-08, R5 ; /* 0x32a5706002057823 */
/* 0x000fcc0000000105 */
/*0150*/ MUFU.EX2 R5, R5 ; /* 0x0000000500057308 */
/* 0x000e240000000800 */
/*0160*/ FFMA R4, R4, R5, 1 ; /* 0x3f80000004047423 */
/* 0x001fca0000000005 */
/*0170*/ IADD3 R2, R4, 0x1800000, RZ ; /* 0x0180000004027810 */
/* 0x000fc80007ffe0ff */
/*0180*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000002027812 */
/* 0x000fc800078ec0ff */
/*0190*/ ISETP.GT.U32.AND P0, PT, R2, 0x1ffffff, PT ; /* 0x01ffffff0200780c */
/* 0x000fda0003f04070 */
/*01a0*/ @P0 BRA 0x1e0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*01b0*/ MOV R2, 0x1d0 ; /* 0x000001d000027802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x270 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ BRA 0x220 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*01e0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x000e240000001000 */
/*01f0*/ FFMA R2, R4, R5, -1 ; /* 0xbf80000004027423 */
/* 0x001fc80000000005 */
/*0200*/ FADD.FTZ R2, -R2, -RZ ; /* 0x800000ff02027221 */
/* 0x000fc80000010100 */
/*0210*/ FFMA R5, R5, R2, R5 ; /* 0x0000000205057223 */
/* 0x000fe40000000005 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ SHF.L.U32 R3, R4, 0x1, RZ ; /* 0x0000000104037819 */
/* 0x000fe200000006ff */
/*0280*/ BSSY B1, 0x590 ; /* 0x0000030000017945 */
/* 0x000fe60003800000 */
/*0290*/ SHF.R.U32.HI R3, RZ, 0x18, R3 ; /* 0x00000018ff037819 */
/* 0x000fc80000011603 */
/*02a0*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05070 */
/*02b0*/ @P0 BRA 0x360 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.SHL.U32 R3, R4, 0x2, RZ ; /* 0x0000000204037824 */
/* 0x000fca00078e00ff */
/*02d0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*02e0*/ @P0 FFMA R5, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004050823 */
/* 0x000fe200000000ff */
/*02f0*/ @!P0 MUFU.RCP R3, R4 ; /* 0x0000000400038308 */
/* 0x000ff00000001000 */
/*0300*/ @P0 MUFU.RCP R6, R5 ; /* 0x0000000500060308 */
/* 0x000e240000001000 */
/*0310*/ @P0 FFMA R7, R5, R6, -1 ; /* 0xbf80000005070423 */
/* 0x001fc80000000006 */
/*0320*/ @P0 FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07070221 */
/* 0x000fc80000010100 */
/*0330*/ @P0 FFMA R7, R6, R7, R6 ; /* 0x0000000706070223 */
/* 0x000fc80000000006 */
/*0340*/ @P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007030823 */
/* 0x000fe200000000ff */
/*0350*/ BRA 0x580 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0360*/ IADD3 R5, R3, -0xfd, RZ ; /* 0xffffff0303057810 */
/* 0x000fc80007ffe0ff */
/*0370*/ ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f04070 */
/*0380*/ @P0 BRA 0x570 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0390*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*03a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3 ; /* 0x00000003ff0a7424 */
/* 0x000fe200078e00ff */
/*03b0*/ IADD3 R3, R3, -0xfc, RZ ; /* 0xffffff0403037810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ LOP3.LUT R6, R6, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000006067812 */
/* 0x000fe400078efcff */
/*03d0*/ SHF.L.U32 R11, R10, R5, RZ ; /* 0x000000050a0b7219 */
/* 0x000fe400000006ff */
/*03e0*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x000e240000001000 */
/*03f0*/ FFMA R8, R6, R7, -1 ; /* 0xbf80000006087423 */
/* 0x001fc80000000007 */
/*0400*/ FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08087221 */
/* 0x000fc80000010100 */
/*0410*/ FFMA.RM R9, R7.reuse, R8.reuse, R7.reuse ; /* 0x0000000807097223 */
/* 0x1c0fe40000004007 */
/*0420*/ FFMA.RP R8, R7, R8, R7 ; /* 0x0000000807087223 */
/* 0x000fc60000008007 */
/*0430*/ LOP3.LUT R7, R9.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff09077812 */
/* 0x040fe400078ec0ff */
/*0440*/ FSETP.NEU.FTZ.AND P0, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x000fe40003f1d000 */
/*0450*/ LOP3.LUT R8, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007087812 */
/* 0x000fe400078efcff */
/*0460*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */
/* 0x000fe40004000000 */
/*0470*/ LOP3.LUT R6, R11, R8, RZ, 0xc0, !PT ; /* 0x000000080b067212 */
/* 0x000fe400078ec0ff */
/*0480*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fc40007ffe1ff */
/*0490*/ SHF.R.U32.HI R6, RZ, R5.reuse, R6 ; /* 0x00000005ff067219 */
/* 0x080fe40000011606 */
/*04a0*/ LOP3.LUT P1, RZ, R7, R5, R8.reuse, 0xf8, !PT ; /* 0x0000000507ff7212 */
/* 0x100fe4000782f808 */
/*04b0*/ LOP3.LUT P0, RZ, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106ff7812 */
/* 0x040fe4000780c0ff */
/*04c0*/ LOP3.LUT P2, RZ, R6, 0x2, RZ, 0xc0, !PT ; /* 0x0000000206ff7812 */
/* 0x000fe4000784c0ff */
/*04d0*/ SHF.R.U32.HI R3, RZ, R3, R8 ; /* 0x00000003ff037219 */
/* 0x000fe40000011608 */
/*04e0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703c20 */
/*04f0*/ LOP3.LUT P1, RZ, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04ff7812 */
/* 0x000fe4000782c0ff */
/*0500*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0510*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a05 */
/*0520*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f06270 */
/*0530*/ @!P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103038810 */
/* 0x000fca0007ffe0ff */
/*0540*/ @!P1 IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203039824 */
/* 0x000fca00078e00ff */
/*0550*/ LOP3.LUT R3, R3, 0x80000000, R4, 0xf8, !PT ; /* 0x8000000003037812 */
/* 0x000fe200078ef804 */
/*0560*/ BRA 0x580 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0570*/ MUFU.RCP R3, R4 ; /* 0x0000000400037308 */
/* 0x0000640000001000 */
/*0580*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0590*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x002fe20000000f00 */
/*05a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*05b0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa4002007950 */
/* 0x000fea0003c3ffff */
/*05c0*/ BRA 0x5c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ForwardSigmoid(float* Z, int nRowsZ, int nColsZ, float* A)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < nRowsZ * nColsZ)
{
A[index] = 1 / (1 + exp(-Z[index]));
}
} | .file "tmpxft_0004cf56_00000000-6_ForwardSigmoid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14ForwardSigmoidPfiiS_PfiiS_
.type _Z38__device_stub__Z14ForwardSigmoidPfiiS_PfiiS_, @function
_Z38__device_stub__Z14ForwardSigmoidPfiiS_PfiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14ForwardSigmoidPfiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14ForwardSigmoidPfiiS_PfiiS_, .-_Z38__device_stub__Z14ForwardSigmoidPfiiS_PfiiS_
.globl _Z14ForwardSigmoidPfiiS_
.type _Z14ForwardSigmoidPfiiS_, @function
_Z14ForwardSigmoidPfiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14ForwardSigmoidPfiiS_PfiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14ForwardSigmoidPfiiS_, .-_Z14ForwardSigmoidPfiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14ForwardSigmoidPfiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14ForwardSigmoidPfiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ForwardSigmoid(float* Z, int nRowsZ, int nColsZ, float* A)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < nRowsZ * nColsZ)
{
A[index] = 1 / (1 + exp(-Z[index]));
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ForwardSigmoid(float* Z, int nRowsZ, int nColsZ, float* A)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < nRowsZ * nColsZ)
{
A[index] = 1 / (1 + exp(-Z[index]));
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ForwardSigmoid(float* Z, int nRowsZ, int nColsZ, float* A)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < nRowsZ * nColsZ)
{
A[index] = 1 / (1 + exp(-Z[index]));
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14ForwardSigmoidPfiiS_
.globl _Z14ForwardSigmoidPfiiS_
.p2align 8
.type _Z14ForwardSigmoidPfiiS_,@function
_Z14ForwardSigmoidPfiiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0xbfb8aa3b, v2
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v2
v_fma_f32 v4, v2, 0xbfb8aa3b, -v3
v_rndne_f32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v4, v2, 0xb2a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
v_add_f32_e32 v2, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v2, v2, 1.0
v_div_scale_f32 v6, vcc_lo, 1.0, v2, 1.0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f32 v2, v3, v2, 1.0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14ForwardSigmoidPfiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14ForwardSigmoidPfiiS_, .Lfunc_end0-_Z14ForwardSigmoidPfiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14ForwardSigmoidPfiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14ForwardSigmoidPfiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ForwardSigmoid(float* Z, int nRowsZ, int nColsZ, float* A)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < nRowsZ * nColsZ)
{
A[index] = 1 / (1 + exp(-Z[index]));
}
} | .text
.file "ForwardSigmoid.hip"
.globl _Z29__device_stub__ForwardSigmoidPfiiS_ # -- Begin function _Z29__device_stub__ForwardSigmoidPfiiS_
.p2align 4, 0x90
.type _Z29__device_stub__ForwardSigmoidPfiiS_,@function
_Z29__device_stub__ForwardSigmoidPfiiS_: # @_Z29__device_stub__ForwardSigmoidPfiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14ForwardSigmoidPfiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__ForwardSigmoidPfiiS_, .Lfunc_end0-_Z29__device_stub__ForwardSigmoidPfiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14ForwardSigmoidPfiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14ForwardSigmoidPfiiS_,@object # @_Z14ForwardSigmoidPfiiS_
.section .rodata,"a",@progbits
.globl _Z14ForwardSigmoidPfiiS_
.p2align 3, 0x0
_Z14ForwardSigmoidPfiiS_:
.quad _Z29__device_stub__ForwardSigmoidPfiiS_
.size _Z14ForwardSigmoidPfiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14ForwardSigmoidPfiiS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__ForwardSigmoidPfiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14ForwardSigmoidPfiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14ForwardSigmoidPfiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff057424 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x230 ; /* 0x0000014000007945 */
/* 0x000fe60003800000 */
/*00f0*/ FFMA.SAT R4, -R2, R5, 0.5 ; /* 0x3f00000002047423 */
/* 0x004fca0000002105 */
/*0100*/ FFMA.RM R4, R4, R7, 12582913 ; /* 0x4b40000104047423 */
/* 0x000fc80000004007 */
/*0110*/ FADD R5, R4.reuse, -12583039 ; /* 0xcb40007f04057421 */
/* 0x040fe40000000000 */
/*0120*/ IMAD.SHL.U32 R4, R4, 0x800000, RZ ; /* 0x0080000004047824 */
/* 0x000fe400078e00ff */
/*0130*/ FFMA R5, -R2, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b02057823 */
/* 0x000fc80000000905 */
/*0140*/ FFMA R5, -R2, 1.925963033500011079e-08, R5 ; /* 0x32a5706002057823 */
/* 0x000fcc0000000105 */
/*0150*/ MUFU.EX2 R5, R5 ; /* 0x0000000500057308 */
/* 0x000e240000000800 */
/*0160*/ FFMA R4, R4, R5, 1 ; /* 0x3f80000004047423 */
/* 0x001fca0000000005 */
/*0170*/ IADD3 R2, R4, 0x1800000, RZ ; /* 0x0180000004027810 */
/* 0x000fc80007ffe0ff */
/*0180*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000002027812 */
/* 0x000fc800078ec0ff */
/*0190*/ ISETP.GT.U32.AND P0, PT, R2, 0x1ffffff, PT ; /* 0x01ffffff0200780c */
/* 0x000fda0003f04070 */
/*01a0*/ @P0 BRA 0x1e0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*01b0*/ MOV R2, 0x1d0 ; /* 0x000001d000027802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x270 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ BRA 0x220 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*01e0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x000e240000001000 */
/*01f0*/ FFMA R2, R4, R5, -1 ; /* 0xbf80000004027423 */
/* 0x001fc80000000005 */
/*0200*/ FADD.FTZ R2, -R2, -RZ ; /* 0x800000ff02027221 */
/* 0x000fc80000010100 */
/*0210*/ FFMA R5, R5, R2, R5 ; /* 0x0000000205057223 */
/* 0x000fe40000000005 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ SHF.L.U32 R3, R4, 0x1, RZ ; /* 0x0000000104037819 */
/* 0x000fe200000006ff */
/*0280*/ BSSY B1, 0x590 ; /* 0x0000030000017945 */
/* 0x000fe60003800000 */
/*0290*/ SHF.R.U32.HI R3, RZ, 0x18, R3 ; /* 0x00000018ff037819 */
/* 0x000fc80000011603 */
/*02a0*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05070 */
/*02b0*/ @P0 BRA 0x360 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.SHL.U32 R3, R4, 0x2, RZ ; /* 0x0000000204037824 */
/* 0x000fca00078e00ff */
/*02d0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*02e0*/ @P0 FFMA R5, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004050823 */
/* 0x000fe200000000ff */
/*02f0*/ @!P0 MUFU.RCP R3, R4 ; /* 0x0000000400038308 */
/* 0x000ff00000001000 */
/*0300*/ @P0 MUFU.RCP R6, R5 ; /* 0x0000000500060308 */
/* 0x000e240000001000 */
/*0310*/ @P0 FFMA R7, R5, R6, -1 ; /* 0xbf80000005070423 */
/* 0x001fc80000000006 */
/*0320*/ @P0 FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07070221 */
/* 0x000fc80000010100 */
/*0330*/ @P0 FFMA R7, R6, R7, R6 ; /* 0x0000000706070223 */
/* 0x000fc80000000006 */
/*0340*/ @P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007030823 */
/* 0x000fe200000000ff */
/*0350*/ BRA 0x580 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0360*/ IADD3 R5, R3, -0xfd, RZ ; /* 0xffffff0303057810 */
/* 0x000fc80007ffe0ff */
/*0370*/ ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f04070 */
/*0380*/ @P0 BRA 0x570 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0390*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*03a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3 ; /* 0x00000003ff0a7424 */
/* 0x000fe200078e00ff */
/*03b0*/ IADD3 R3, R3, -0xfc, RZ ; /* 0xffffff0403037810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ LOP3.LUT R6, R6, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000006067812 */
/* 0x000fe400078efcff */
/*03d0*/ SHF.L.U32 R11, R10, R5, RZ ; /* 0x000000050a0b7219 */
/* 0x000fe400000006ff */
/*03e0*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x000e240000001000 */
/*03f0*/ FFMA R8, R6, R7, -1 ; /* 0xbf80000006087423 */
/* 0x001fc80000000007 */
/*0400*/ FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08087221 */
/* 0x000fc80000010100 */
/*0410*/ FFMA.RM R9, R7.reuse, R8.reuse, R7.reuse ; /* 0x0000000807097223 */
/* 0x1c0fe40000004007 */
/*0420*/ FFMA.RP R8, R7, R8, R7 ; /* 0x0000000807087223 */
/* 0x000fc60000008007 */
/*0430*/ LOP3.LUT R7, R9.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff09077812 */
/* 0x040fe400078ec0ff */
/*0440*/ FSETP.NEU.FTZ.AND P0, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x000fe40003f1d000 */
/*0450*/ LOP3.LUT R8, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007087812 */
/* 0x000fe400078efcff */
/*0460*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */
/* 0x000fe40004000000 */
/*0470*/ LOP3.LUT R6, R11, R8, RZ, 0xc0, !PT ; /* 0x000000080b067212 */
/* 0x000fe400078ec0ff */
/*0480*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fc40007ffe1ff */
/*0490*/ SHF.R.U32.HI R6, RZ, R5.reuse, R6 ; /* 0x00000005ff067219 */
/* 0x080fe40000011606 */
/*04a0*/ LOP3.LUT P1, RZ, R7, R5, R8.reuse, 0xf8, !PT ; /* 0x0000000507ff7212 */
/* 0x100fe4000782f808 */
/*04b0*/ LOP3.LUT P0, RZ, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106ff7812 */
/* 0x040fe4000780c0ff */
/*04c0*/ LOP3.LUT P2, RZ, R6, 0x2, RZ, 0xc0, !PT ; /* 0x0000000206ff7812 */
/* 0x000fe4000784c0ff */
/*04d0*/ SHF.R.U32.HI R3, RZ, R3, R8 ; /* 0x00000003ff037219 */
/* 0x000fe40000011608 */
/*04e0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703c20 */
/*04f0*/ LOP3.LUT P1, RZ, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04ff7812 */
/* 0x000fe4000782c0ff */
/*0500*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0510*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a05 */
/*0520*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f06270 */
/*0530*/ @!P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103038810 */
/* 0x000fca0007ffe0ff */
/*0540*/ @!P1 IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203039824 */
/* 0x000fca00078e00ff */
/*0550*/ LOP3.LUT R3, R3, 0x80000000, R4, 0xf8, !PT ; /* 0x8000000003037812 */
/* 0x000fe200078ef804 */
/*0560*/ BRA 0x580 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0570*/ MUFU.RCP R3, R4 ; /* 0x0000000400037308 */
/* 0x0000640000001000 */
/*0580*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0590*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x002fe20000000f00 */
/*05a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*05b0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa4002007950 */
/* 0x000fea0003c3ffff */
/*05c0*/ BRA 0x5c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14ForwardSigmoidPfiiS_
.globl _Z14ForwardSigmoidPfiiS_
.p2align 8
.type _Z14ForwardSigmoidPfiiS_,@function
_Z14ForwardSigmoidPfiiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0xbfb8aa3b, v2
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v2
v_fma_f32 v4, v2, 0xbfb8aa3b, -v3
v_rndne_f32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v4, v2, 0xb2a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
v_add_f32_e32 v2, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v2, v2, 1.0
v_div_scale_f32 v6, vcc_lo, 1.0, v2, 1.0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f32 v2, v3, v2, 1.0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14ForwardSigmoidPfiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14ForwardSigmoidPfiiS_, .Lfunc_end0-_Z14ForwardSigmoidPfiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14ForwardSigmoidPfiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14ForwardSigmoidPfiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004cf56_00000000-6_ForwardSigmoid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14ForwardSigmoidPfiiS_PfiiS_
.type _Z38__device_stub__Z14ForwardSigmoidPfiiS_PfiiS_, @function
_Z38__device_stub__Z14ForwardSigmoidPfiiS_PfiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14ForwardSigmoidPfiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14ForwardSigmoidPfiiS_PfiiS_, .-_Z38__device_stub__Z14ForwardSigmoidPfiiS_PfiiS_
.globl _Z14ForwardSigmoidPfiiS_
.type _Z14ForwardSigmoidPfiiS_, @function
_Z14ForwardSigmoidPfiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14ForwardSigmoidPfiiS_PfiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14ForwardSigmoidPfiiS_, .-_Z14ForwardSigmoidPfiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14ForwardSigmoidPfiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14ForwardSigmoidPfiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ForwardSigmoid.hip"
.globl _Z29__device_stub__ForwardSigmoidPfiiS_ # -- Begin function _Z29__device_stub__ForwardSigmoidPfiiS_
.p2align 4, 0x90
.type _Z29__device_stub__ForwardSigmoidPfiiS_,@function
_Z29__device_stub__ForwardSigmoidPfiiS_: # @_Z29__device_stub__ForwardSigmoidPfiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14ForwardSigmoidPfiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__ForwardSigmoidPfiiS_, .Lfunc_end0-_Z29__device_stub__ForwardSigmoidPfiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14ForwardSigmoidPfiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14ForwardSigmoidPfiiS_,@object # @_Z14ForwardSigmoidPfiiS_
.section .rodata,"a",@progbits
.globl _Z14ForwardSigmoidPfiiS_
.p2align 3, 0x0
_Z14ForwardSigmoidPfiiS_:
.quad _Z29__device_stub__ForwardSigmoidPfiiS_
.size _Z14ForwardSigmoidPfiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14ForwardSigmoidPfiiS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__ForwardSigmoidPfiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14ForwardSigmoidPfiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void K1() {
unsigned num = 0;
for (unsigned ii = 0; ii < threadIdx.x; ++ii)
num += ii;
printf("K1: %d\n", threadIdx.x);
}
__global__ void K2() {
printf("K2\n");
}
int main() {
cudaStream_t s1, s2;
cudaStreamCreate(&s1);
cudaStreamCreate(&s2);
K1<<<1, 1024, 0, s1>>>();
K2<<<1, 32, 0, s2>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z2K2v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z2K1v
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void K1() {
unsigned num = 0;
for (unsigned ii = 0; ii < threadIdx.x; ++ii)
num += ii;
printf("K1: %d\n", threadIdx.x);
}
__global__ void K2() {
printf("K2\n");
}
int main() {
cudaStream_t s1, s2;
cudaStreamCreate(&s1);
cudaStreamCreate(&s2);
K1<<<1, 1024, 0, s1>>>();
K2<<<1, 32, 0, s2>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0007e904_00000000-6_stream.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20__device_stub__Z2K1vv
.type _Z20__device_stub__Z2K1vv, @function
_Z20__device_stub__Z2K1vv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z2K1v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z20__device_stub__Z2K1vv, .-_Z20__device_stub__Z2K1vv
.globl _Z2K1v
.type _Z2K1v, @function
_Z2K1v:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z2K1vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2K1v, .-_Z2K1v
.globl _Z20__device_stub__Z2K2vv
.type _Z20__device_stub__Z2K2vv, @function
_Z20__device_stub__Z2K2vv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z2K2v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z20__device_stub__Z2K2vv, .-_Z20__device_stub__Z2K2vv
.globl _Z2K2v
.type _Z2K2v, @function
_Z2K2v:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z2K2vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z2K2v, .-_Z2K2v
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaStreamCreate@PLT
leaq 8(%rsp), %rdi
call cudaStreamCreate@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movq (%rsp), %r9
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movq 8(%rsp), %r9
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call _Z20__device_stub__Z2K1vv
jmp .L20
.L25:
call _Z20__device_stub__Z2K2vv
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2K2v"
.LC1:
.string "_Z2K1v"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2K2v(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z2K1v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
__global__ void K1() {
unsigned num = 0;
for (unsigned ii = 0; ii < threadIdx.x; ++ii)
num += ii;
printf("K1: %d\n", threadIdx.x);
}
__global__ void K2() {
printf("K2\n");
}
int main() {
cudaStream_t s1, s2;
cudaStreamCreate(&s1);
cudaStreamCreate(&s2);
K1<<<1, 1024, 0, s1>>>();
K2<<<1, 32, 0, s2>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void K1() {
unsigned num = 0;
for (unsigned ii = 0; ii < threadIdx.x; ++ii)
num += ii;
printf("K1: %d\n", threadIdx.x);
}
__global__ void K2() {
printf("K2\n");
}
int main() {
hipStream_t s1, s2;
hipStreamCreate(&s1);
hipStreamCreate(&s2);
K1<<<1, 1024, 0, s1>>>();
K2<<<1, 32, 0, s2>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void K1() {
unsigned num = 0;
for (unsigned ii = 0; ii < threadIdx.x; ++ii)
num += ii;
printf("K1: %d\n", threadIdx.x);
}
__global__ void K2() {
printf("K2\n");
}
int main() {
hipStream_t s1, s2;
hipStreamCreate(&s1);
hipStreamCreate(&s2);
K1<<<1, 1024, 0, s1>>>();
K2<<<1, 32, 0, s2>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "stream.hip"
.globl _Z17__device_stub__K1v # -- Begin function _Z17__device_stub__K1v
.p2align 4, 0x90
.type _Z17__device_stub__K1v,@function
_Z17__device_stub__K1v: # @_Z17__device_stub__K1v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K1v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z17__device_stub__K1v, .Lfunc_end0-_Z17__device_stub__K1v
.cfi_endproc
# -- End function
.globl _Z17__device_stub__K2v # -- Begin function _Z17__device_stub__K2v
.p2align 4, 0x90
.type _Z17__device_stub__K2v,@function
_Z17__device_stub__K2v: # @_Z17__device_stub__K2v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K2v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z17__device_stub__K2v, .Lfunc_end1-_Z17__device_stub__K2v
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 72(%rsp), %rdi
callq hipStreamCreate
leaq 64(%rsp), %rdi
callq hipStreamCreate
movq 72(%rsp), %r9
leaq 1023(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K1v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 64(%rsp), %r9
leaq 31(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K2v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2K1v, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2K2v, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2K1v,@object # @_Z2K1v
.section .rodata,"a",@progbits
.globl _Z2K1v
.p2align 3, 0x0
_Z2K1v:
.quad _Z17__device_stub__K1v
.size _Z2K1v, 8
.type _Z2K2v,@object # @_Z2K2v
.globl _Z2K2v
.p2align 3, 0x0
_Z2K2v:
.quad _Z17__device_stub__K2v
.size _Z2K2v, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2K1v"
.size .L__unnamed_1, 7
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z2K2v"
.size .L__unnamed_2, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__K1v
.addrsig_sym _Z17__device_stub__K2v
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2K1v
.addrsig_sym _Z2K2v
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007e904_00000000-6_stream.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20__device_stub__Z2K1vv
.type _Z20__device_stub__Z2K1vv, @function
_Z20__device_stub__Z2K1vv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z2K1v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z20__device_stub__Z2K1vv, .-_Z20__device_stub__Z2K1vv
.globl _Z2K1v
.type _Z2K1v, @function
_Z2K1v:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z2K1vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2K1v, .-_Z2K1v
.globl _Z20__device_stub__Z2K2vv
.type _Z20__device_stub__Z2K2vv, @function
_Z20__device_stub__Z2K2vv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z2K2v(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z20__device_stub__Z2K2vv, .-_Z20__device_stub__Z2K2vv
.globl _Z2K2v
.type _Z2K2v, @function
_Z2K2v:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z2K2vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z2K2v, .-_Z2K2v
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaStreamCreate@PLT
leaq 8(%rsp), %rdi
call cudaStreamCreate@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movq (%rsp), %r9
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movq 8(%rsp), %r9
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call _Z20__device_stub__Z2K1vv
jmp .L20
.L25:
call _Z20__device_stub__Z2K2vv
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2K2v"
.LC1:
.string "_Z2K1v"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2K2v(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z2K1v(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stream.hip"
.globl _Z17__device_stub__K1v # -- Begin function _Z17__device_stub__K1v
.p2align 4, 0x90
.type _Z17__device_stub__K1v,@function
_Z17__device_stub__K1v: # @_Z17__device_stub__K1v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K1v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z17__device_stub__K1v, .Lfunc_end0-_Z17__device_stub__K1v
.cfi_endproc
# -- End function
.globl _Z17__device_stub__K2v # -- Begin function _Z17__device_stub__K2v
.p2align 4, 0x90
.type _Z17__device_stub__K2v,@function
_Z17__device_stub__K2v: # @_Z17__device_stub__K2v
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K2v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z17__device_stub__K2v, .Lfunc_end1-_Z17__device_stub__K2v
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 72(%rsp), %rdi
callq hipStreamCreate
leaq 64(%rsp), %rdi
callq hipStreamCreate
movq 72(%rsp), %r9
leaq 1023(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K1v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 64(%rsp), %r9
leaq 31(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z2K2v, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2K1v, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2K2v, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2K1v,@object # @_Z2K1v
.section .rodata,"a",@progbits
.globl _Z2K1v
.p2align 3, 0x0
_Z2K1v:
.quad _Z17__device_stub__K1v
.size _Z2K1v, 8
.type _Z2K2v,@object # @_Z2K2v
.globl _Z2K2v
.p2align 3, 0x0
_Z2K2v:
.quad _Z17__device_stub__K2v
.size _Z2K2v, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2K1v"
.size .L__unnamed_1, 7
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z2K2v"
.size .L__unnamed_2, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__K1v
.addrsig_sym _Z17__device_stub__K2v
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2K1v
.addrsig_sym _Z2K2v
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
namespace ann {
// CUDA2
}
__global__ void kernel_feedforward( int layer_id, int *l, int *s, int *sw, float *z_arr, float *a_arr, float *w_arr ){
volatile int idx = threadIdx.x + blockDim.x*blockIdx.x;
int neuron_count = l[layer_id];
int neuron_count_prev = l[layer_id-1];
//printf("layer = %d idx = %d count = %d\n", layer_id, idx, neuron_count-1);
if(idx >= neuron_count-1) return;
float z = 0;
for(int k = 0; k < neuron_count_prev; k++){
z += w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k];
// printf("w_arr[%d] * a_arr[%d] = %.20f\n",
// sw[layer_id-1] + k*(neuron_count - 1) + idx ,
// s[layer_id-1] + k,
// w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k]);
// printf("%.10f * %.10f = %.10f\n", w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx ],
// a_arr[s[layer_id-1] + k],
// w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k]
// );
}
z_arr[s[layer_id] + idx] = z;
float a = 1.0 / (1.0 + expf(-z));
a_arr[s[layer_id] + idx] = a;
// printf("index = %d z = %.5f\n", s[layer_id] + idx, z);
// printf("a = %.20f\n", a);
} | .file "tmpxft_000f0662_00000000-6_kernel_feedforward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z18kernel_feedforwardiPiS_S_PfS0_S0_iPiS_S_PfS0_S0_
.type _Z51__device_stub__Z18kernel_feedforwardiPiS_S_PfS0_S0_iPiS_S_PfS0_S0_, @function
_Z51__device_stub__Z18kernel_feedforwardiPiS_S_PfS0_S0_iPiS_S_PfS0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 60(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z18kernel_feedforwardiPiS_S_PfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z18kernel_feedforwardiPiS_S_PfS0_S0_iPiS_S_PfS0_S0_, .-_Z51__device_stub__Z18kernel_feedforwardiPiS_S_PfS0_S0_iPiS_S_PfS0_S0_
.globl _Z18kernel_feedforwardiPiS_S_PfS0_S0_
.type _Z18kernel_feedforwardiPiS_S_PfS0_S0_, @function
_Z18kernel_feedforwardiPiS_S_PfS0_S0_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z18kernel_feedforwardiPiS_S_PfS0_S0_iPiS_S_PfS0_S0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernel_feedforwardiPiS_S_PfS0_S0_, .-_Z18kernel_feedforwardiPiS_S_PfS0_S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18kernel_feedforwardiPiS_S_PfS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernel_feedforwardiPiS_S_PfS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
namespace ann {
// CUDA2
}
__global__ void kernel_feedforward( int layer_id, int *l, int *s, int *sw, float *z_arr, float *a_arr, float *w_arr ){
volatile int idx = threadIdx.x + blockDim.x*blockIdx.x;
int neuron_count = l[layer_id];
int neuron_count_prev = l[layer_id-1];
//printf("layer = %d idx = %d count = %d\n", layer_id, idx, neuron_count-1);
if(idx >= neuron_count-1) return;
float z = 0;
for(int k = 0; k < neuron_count_prev; k++){
z += w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k];
// printf("w_arr[%d] * a_arr[%d] = %.20f\n",
// sw[layer_id-1] + k*(neuron_count - 1) + idx ,
// s[layer_id-1] + k,
// w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k]);
// printf("%.10f * %.10f = %.10f\n", w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx ],
// a_arr[s[layer_id-1] + k],
// w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k]
// );
}
z_arr[s[layer_id] + idx] = z;
float a = 1.0 / (1.0 + expf(-z));
a_arr[s[layer_id] + idx] = a;
// printf("index = %d z = %.5f\n", s[layer_id] + idx, z);
// printf("a = %.20f\n", a);
} | #include <hip/hip_runtime.h>
#include "includes.h"
namespace ann {
// CUDA2
}
__global__ void kernel_feedforward( int layer_id, int *l, int *s, int *sw, float *z_arr, float *a_arr, float *w_arr ){
volatile int idx = threadIdx.x + blockDim.x*blockIdx.x;
int neuron_count = l[layer_id];
int neuron_count_prev = l[layer_id-1];
//printf("layer = %d idx = %d count = %d\n", layer_id, idx, neuron_count-1);
if(idx >= neuron_count-1) return;
float z = 0;
for(int k = 0; k < neuron_count_prev; k++){
z += w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k];
// printf("w_arr[%d] * a_arr[%d] = %.20f\n",
// sw[layer_id-1] + k*(neuron_count - 1) + idx ,
// s[layer_id-1] + k,
// w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k]);
// printf("%.10f * %.10f = %.10f\n", w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx ],
// a_arr[s[layer_id-1] + k],
// w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k]
// );
}
z_arr[s[layer_id] + idx] = z;
float a = 1.0 / (1.0 + expf(-z));
a_arr[s[layer_id] + idx] = a;
// printf("index = %d z = %.5f\n", s[layer_id] + idx, z);
// printf("a = %.20f\n", a);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
namespace ann {
// CUDA2
}
__global__ void kernel_feedforward( int layer_id, int *l, int *s, int *sw, float *z_arr, float *a_arr, float *w_arr ){
volatile int idx = threadIdx.x + blockDim.x*blockIdx.x;
int neuron_count = l[layer_id];
int neuron_count_prev = l[layer_id-1];
//printf("layer = %d idx = %d count = %d\n", layer_id, idx, neuron_count-1);
if(idx >= neuron_count-1) return;
float z = 0;
for(int k = 0; k < neuron_count_prev; k++){
z += w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k];
// printf("w_arr[%d] * a_arr[%d] = %.20f\n",
// sw[layer_id-1] + k*(neuron_count - 1) + idx ,
// s[layer_id-1] + k,
// w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k]);
// printf("%.10f * %.10f = %.10f\n", w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx ],
// a_arr[s[layer_id-1] + k],
// w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k]
// );
}
z_arr[s[layer_id] + idx] = z;
float a = 1.0 / (1.0 + expf(-z));
a_arr[s[layer_id] + idx] = a;
// printf("index = %d z = %.5f\n", s[layer_id] + idx, z);
// printf("a = %.20f\n", a);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernel_feedforwardiPiS_S_PfS0_S0_
.globl _Z18kernel_feedforwardiPiS_S_PfS0_S0_
.p2align 8
.type _Z18kernel_feedforwardiPiS_S_PfS0_S0_,@function
_Z18kernel_feedforwardiPiS_S_PfS0_S0_:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x44
s_load_b32 s4, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
s_mov_b64 s[6:7], src_private_base
s_mov_b32 s6, 4
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_ashr_i32 s5, s4, 31
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
s_lshl_b64 s[6:7], s[4:5], 2
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
flat_store_b32 v[2:3], v1 dlc
s_waitcnt_vscnt null, 0x0
s_load_b32 s15, s[6:7], 0x0
flat_load_b32 v0, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
s_add_i32 s6, s15, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_6
s_add_i32 s8, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[6:7], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s2, s6
s_addc_u32 s3, s3, s7
s_load_b32 s12, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[10:11], s[0:1], 0x18
s_lshl_b64 s[16:17], s[8:9], 2
s_load_b64 s[8:9], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_add_u32 s10, s10, s16
s_addc_u32 s11, s11, s17
s_load_b32 s13, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s14, s13, 31
s_add_u32 s10, s6, s16
s_addc_u32 s11, s7, s17
s_mov_b64 s[16:17], src_private_base
s_load_b32 s10, s[10:11], 0x0
s_mov_b32 s16, 4
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
s_waitcnt lgkmcnt(0)
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[10:11], 2
s_add_u32 s10, s2, s10
s_addc_u32 s11, s3, s11
s_ashr_i32 s16, s15, 31
s_add_u32 s15, s15, -1
s_addc_u32 s16, s16, -1
.p2align 6
.LBB0_3:
flat_load_b32 v3, v[0:1] glc dlc
s_waitcnt vmcnt(0)
s_load_b32 s17, s[10:11], 0x0
s_add_i32 s12, s12, -1
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v3, vcc_lo, s13, v3
s_add_u32 s13, s13, s15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s14, v4, vcc_lo
s_addc_u32 s14, s14, s16
s_cmp_eq_u32 s12, 0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, s17, v3
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_mov_b64 s[8:9], src_private_base
s_mov_b32 s8, 4
s_lshl_b64 s[4:5], s[4:5], 2
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s8
v_mov_b32_e32 v1, s9
s_add_u32 s4, s6, s4
s_addc_u32 s5, s7, s5
global_load_b32 v11, v3, s[4:5]
flat_load_b32 v9, v[0:1] glc dlc
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0xbfb8aa3b, v2
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v2
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rndne_f32_e32 v4, v3
v_fma_f32 v5, v2, 0xbfb8aa3b, -v3
v_sub_f32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v5, v2, 0xb2a5705f, v5
v_cvt_i32_f32_e32 v4, v4
v_add_f32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, 0x7f800000, v3, vcc_lo
v_cvt_f64_f32_e32 v[3:4], v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], 1.0
v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[7:8], v[5:6]
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v9, v9, v11
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s0, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
global_store_b32 v[9:10], v2, off
flat_load_b32 v2, v[0:1] glc dlc
s_waitcnt vmcnt(0)
v_fma_f64 v[0:1], -v[5:6], v[7:8], 1.0
v_div_scale_f64 v[9:10], vcc_lo, 1.0, v[3:4], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[7:8], v[0:1], v[7:8]
v_fma_f64 v[7:8], -v[5:6], v[0:1], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[0:1], v[7:8], v[0:1]
v_mul_f64 v[7:8], v[9:10], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], -v[5:6], v[7:8], v[9:10]
v_div_fmas_f64 v[0:1], v[5:6], v[0:1], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[0:1], v[3:4], 1.0
v_cvt_f32_f64_e32 v3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v2, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernel_feedforwardiPiS_S_PfS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 8
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernel_feedforwardiPiS_S_PfS0_S0_, .Lfunc_end0-_Z18kernel_feedforwardiPiS_S_PfS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernel_feedforwardiPiS_S_PfS0_S0_
.private_segment_fixed_size: 8
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z18kernel_feedforwardiPiS_S_PfS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
namespace ann {
// CUDA2
}
__global__ void kernel_feedforward( int layer_id, int *l, int *s, int *sw, float *z_arr, float *a_arr, float *w_arr ){
volatile int idx = threadIdx.x + blockDim.x*blockIdx.x;
int neuron_count = l[layer_id];
int neuron_count_prev = l[layer_id-1];
//printf("layer = %d idx = %d count = %d\n", layer_id, idx, neuron_count-1);
if(idx >= neuron_count-1) return;
float z = 0;
for(int k = 0; k < neuron_count_prev; k++){
z += w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k];
// printf("w_arr[%d] * a_arr[%d] = %.20f\n",
// sw[layer_id-1] + k*(neuron_count - 1) + idx ,
// s[layer_id-1] + k,
// w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k]);
// printf("%.10f * %.10f = %.10f\n", w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx ],
// a_arr[s[layer_id-1] + k],
// w_arr[sw[layer_id-1] + k*(neuron_count - 1) + idx]*a_arr[s[layer_id-1] + k]
// );
}
z_arr[s[layer_id] + idx] = z;
float a = 1.0 / (1.0 + expf(-z));
a_arr[s[layer_id] + idx] = a;
// printf("index = %d z = %.5f\n", s[layer_id] + idx, z);
// printf("a = %.20f\n", a);
} | .text
.file "kernel_feedforward.hip"
.globl _Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_ # -- Begin function _Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_
.p2align 4, 0x90
.type _Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_,@function
_Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_: # @_Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18kernel_feedforwardiPiS_S_PfS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_, .Lfunc_end0-_Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernel_feedforwardiPiS_S_PfS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernel_feedforwardiPiS_S_PfS0_S0_,@object # @_Z18kernel_feedforwardiPiS_S_PfS0_S0_
.section .rodata,"a",@progbits
.globl _Z18kernel_feedforwardiPiS_S_PfS0_S0_
.p2align 3, 0x0
_Z18kernel_feedforwardiPiS_S_PfS0_S0_:
.quad _Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_
.size _Z18kernel_feedforwardiPiS_S_PfS0_S0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernel_feedforwardiPiS_S_PfS0_S0_"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernel_feedforwardiPiS_S_PfS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f0662_00000000-6_kernel_feedforward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z18kernel_feedforwardiPiS_S_PfS0_S0_iPiS_S_PfS0_S0_
.type _Z51__device_stub__Z18kernel_feedforwardiPiS_S_PfS0_S0_iPiS_S_PfS0_S0_, @function
_Z51__device_stub__Z18kernel_feedforwardiPiS_S_PfS0_S0_iPiS_S_PfS0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 60(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z18kernel_feedforwardiPiS_S_PfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z18kernel_feedforwardiPiS_S_PfS0_S0_iPiS_S_PfS0_S0_, .-_Z51__device_stub__Z18kernel_feedforwardiPiS_S_PfS0_S0_iPiS_S_PfS0_S0_
.globl _Z18kernel_feedforwardiPiS_S_PfS0_S0_
.type _Z18kernel_feedforwardiPiS_S_PfS0_S0_, @function
_Z18kernel_feedforwardiPiS_S_PfS0_S0_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z18kernel_feedforwardiPiS_S_PfS0_S0_iPiS_S_PfS0_S0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernel_feedforwardiPiS_S_PfS0_S0_, .-_Z18kernel_feedforwardiPiS_S_PfS0_S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18kernel_feedforwardiPiS_S_PfS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernel_feedforwardiPiS_S_PfS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_feedforward.hip"
.globl _Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_ # -- Begin function _Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_
.p2align 4, 0x90
.type _Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_,@function
_Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_: # @_Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18kernel_feedforwardiPiS_S_PfS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_, .Lfunc_end0-_Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernel_feedforwardiPiS_S_PfS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernel_feedforwardiPiS_S_PfS0_S0_,@object # @_Z18kernel_feedforwardiPiS_S_PfS0_S0_
.section .rodata,"a",@progbits
.globl _Z18kernel_feedforwardiPiS_S_PfS0_S0_
.p2align 3, 0x0
_Z18kernel_feedforwardiPiS_S_PfS0_S0_:
.quad _Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_
.size _Z18kernel_feedforwardiPiS_S_PfS0_S0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernel_feedforwardiPiS_S_PfS0_S0_"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernel_feedforwardiPiS_S_PfS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernel_feedforwardiPiS_S_PfS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void tanh_kernel(float* Y,
int batch_size,
int num){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float tp;
// load to register and then do tanh
tp = Y[idx];
Y[idx] = tanh(tp);
}
void launch_tanh(float* Y,
int batch_size,
int num){
dim3 gridSize((batch_size * num + 1023)/ 1024);
dim3 blockSize(1024);
tanh_kernel<<<gridSize, blockSize>>>(Y, batch_size, num);
} | code for sm_80
Function : _Z11tanh_kernelPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 1.125, -9232 ; /* 0x3c80f082ff077435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R6, 0x3f800000 ; /* 0x3f80000000067802 */
/* 0x000fe20000000f00 */
/*00a0*/ FMUL R4, |R0|.reuse, 2.8853900432586669922 ; /* 0x4038aa3b00047820 */
/* 0x044fe20000400200 */
/*00b0*/ FSETP.GE.AND P1, PT, |R0|.reuse, 0.60000002384185791016, PT ; /* 0x3f19999a0000780b */
/* 0x040fe20003f26200 */
/*00c0*/ FMUL R8, R0.reuse, R0 ; /* 0x0000000000087220 */
/* 0x040fe20000400000 */
/*00d0*/ FSETP.GE.AND P0, PT, |R0|, 9.010913848876953125, PT ; /* 0x41102cb40000780b */
/* 0x000fc60003f06200 */
/*00e0*/ MUFU.EX2 R4, R4 ; /* 0x0000000400047308 */
/* 0x000e240000000800 */
/*00f0*/ FFMA R7, R8, R7, -0.052303962409496307373 ; /* 0xbd563cae08077423 */
/* 0x000fc80000000007 */
/*0100*/ FFMA R9, R8, R7, 0.1331529766321182251 ; /* 0x3e08594108097423 */
/* 0x000fc80000000007 */
/*0110*/ FFMA R9, R8, R9, -0.33332768082618713379 ; /* 0xbeaaa9ed08097423 */
/* 0x000fc80000000009 */
/*0120*/ FFMA R9, R8, R9, RZ ; /* 0x0000000908097223 */
/* 0x000fe400000000ff */
/*0130*/ FADD R5, R4, 1 ; /* 0x3f80000004057421 */
/* 0x001fcc0000000000 */
/*0140*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x000e240000001000 */
/*0150*/ FFMA R6, R5, -2, R6 ; /* 0xc000000005067823 */
/* 0x001fca0000000006 */
/*0160*/ FSEL R7, R6, 1, !P0 ; /* 0x3f80000006077808 */
/* 0x000fc80004000000 */
/*0170*/ LOP3.LUT R7, R7, 0x80000000, R0.reuse, 0xf8, !PT ; /* 0x8000000007077812 */
/* 0x100fe200078ef800 */
/*0180*/ @!P1 FFMA R7, R0, R9, R0 ; /* 0x0000000900079223 */
/* 0x000fca0000000000 */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void tanh_kernel(float* Y,
int batch_size,
int num){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float tp;
// load to register and then do tanh
tp = Y[idx];
Y[idx] = tanh(tp);
}
void launch_tanh(float* Y,
int batch_size,
int num){
dim3 gridSize((batch_size * num + 1023)/ 1024);
dim3 blockSize(1024);
tanh_kernel<<<gridSize, blockSize>>>(Y, batch_size, num);
} | .file "tmpxft_000a4fc5_00000000-6_tanh_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11tanh_kernelPfiiPfii
.type _Z33__device_stub__Z11tanh_kernelPfiiPfii, @function
_Z33__device_stub__Z11tanh_kernelPfiiPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11tanh_kernelPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z33__device_stub__Z11tanh_kernelPfiiPfii, .-_Z33__device_stub__Z11tanh_kernelPfiiPfii
.globl _Z11tanh_kernelPfii
.type _Z11tanh_kernelPfii, @function
_Z11tanh_kernelPfii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11tanh_kernelPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z11tanh_kernelPfii, .-_Z11tanh_kernelPfii
.globl _Z11launch_tanhPfii
.type _Z11launch_tanhPfii, @function
_Z11launch_tanhPfii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl %esi, %ebx
movl %edx, %ebp
movl %esi, %edx
imull %ebp, %edx
leal 2046(%rdx), %eax
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebp, %edx
movl %ebx, %esi
movq %r12, %rdi
call _Z33__device_stub__Z11tanh_kernelPfiiPfii
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z11launch_tanhPfii, .-_Z11launch_tanhPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11tanh_kernelPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11tanh_kernelPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void tanh_kernel(float* Y,
int batch_size,
int num){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float tp;
// load to register and then do tanh
tp = Y[idx];
Y[idx] = tanh(tp);
}
void launch_tanh(float* Y,
int batch_size,
int num){
dim3 gridSize((batch_size * num + 1023)/ 1024);
dim3 blockSize(1024);
tanh_kernel<<<gridSize, blockSize>>>(Y, batch_size, num);
} | #include <hip/hip_runtime.h>
__global__ void tanh_kernel(float* Y,
int batch_size,
int num){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float tp;
// load to register and then do tanh
tp = Y[idx];
Y[idx] = tanh(tp);
}
void launch_tanh(float* Y,
int batch_size,
int num){
dim3 gridSize((batch_size * num + 1023)/ 1024);
dim3 blockSize(1024);
tanh_kernel<<<gridSize, blockSize>>>(Y, batch_size, num);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void tanh_kernel(float* Y,
int batch_size,
int num){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float tp;
// load to register and then do tanh
tp = Y[idx];
Y[idx] = tanh(tp);
}
void launch_tanh(float* Y,
int batch_size,
int num){
dim3 gridSize((batch_size * num + 1023)/ 1024);
dim3 blockSize(1024);
tanh_kernel<<<gridSize, blockSize>>>(Y, batch_size, num);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11tanh_kernelPfii
.globl _Z11tanh_kernelPfii
.p2align 8
.type _Z11tanh_kernelPfii,@function
_Z11tanh_kernelPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e64 s0, 0x3f200000, |v2|
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB0_2
v_add_f32_e64 v3, |v2|, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v4, 0x3fb8aa3b, v3
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
v_rndne_f32_e32 v5, v4
v_fma_f32 v6, v3, 0x3fb8aa3b, -v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v4, v5
v_fmamk_f32 v6, v3, 0x32a5705f, v6
v_cvt_i32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v4, v6
v_exp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
v_cndmask_b32_e32 v3, 0x7f800000, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, 1.0, v3
v_rcp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v3, v3, -2.0, 1.0
.LBB0_2:
s_and_not1_saveexec_b32 s0, s0
v_mul_f32_e32 v3, v2, v2
s_mov_b32 s1, 0xbbbac73d
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fmaak_f32 v4, s1, v3, 0x3ca908c9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v4, v3, v4, 0xbd5c1c4e
v_fmaak_f32 v4, v3, v4, 0x3e088382
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v4, v3, v4, 0xbeaaaa99
v_mul_f32_e64 v4, |v2|, v4
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v3, v3, v4, |v2|
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1)
v_bfi_b32 v2, 0x7fffffff, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11tanh_kernelPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11tanh_kernelPfii, .Lfunc_end0-_Z11tanh_kernelPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11tanh_kernelPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11tanh_kernelPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void tanh_kernel(float* Y,
int batch_size,
int num){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
float tp;
// load to register and then do tanh
tp = Y[idx];
Y[idx] = tanh(tp);
}
void launch_tanh(float* Y,
int batch_size,
int num){
dim3 gridSize((batch_size * num + 1023)/ 1024);
dim3 blockSize(1024);
tanh_kernel<<<gridSize, blockSize>>>(Y, batch_size, num);
} | .text
.file "tanh_kernel.hip"
.globl _Z26__device_stub__tanh_kernelPfii # -- Begin function _Z26__device_stub__tanh_kernelPfii
.p2align 4, 0x90
.type _Z26__device_stub__tanh_kernelPfii,@function
_Z26__device_stub__tanh_kernelPfii: # @_Z26__device_stub__tanh_kernelPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11tanh_kernelPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__tanh_kernelPfii, .Lfunc_end0-_Z26__device_stub__tanh_kernelPfii
.cfi_endproc
# -- End function
.globl _Z11launch_tanhPfii # -- Begin function _Z11launch_tanhPfii
.p2align 4, 0x90
.type _Z11launch_tanhPfii,@function
_Z11launch_tanhPfii: # @_Z11launch_tanhPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl %edx, %edi
imull %esi, %edi
leal 1023(%rdi), %eax
addl $2046, %edi # imm = 0x7FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r14, 56(%rsp)
movl %ebp, 4(%rsp)
movl %ebx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11tanh_kernelPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11launch_tanhPfii, .Lfunc_end1-_Z11launch_tanhPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11tanh_kernelPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11tanh_kernelPfii,@object # @_Z11tanh_kernelPfii
.section .rodata,"a",@progbits
.globl _Z11tanh_kernelPfii
.p2align 3, 0x0
_Z11tanh_kernelPfii:
.quad _Z26__device_stub__tanh_kernelPfii
.size _Z11tanh_kernelPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11tanh_kernelPfii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__tanh_kernelPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11tanh_kernelPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11tanh_kernelPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 1.125, -9232 ; /* 0x3c80f082ff077435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R6, 0x3f800000 ; /* 0x3f80000000067802 */
/* 0x000fe20000000f00 */
/*00a0*/ FMUL R4, |R0|.reuse, 2.8853900432586669922 ; /* 0x4038aa3b00047820 */
/* 0x044fe20000400200 */
/*00b0*/ FSETP.GE.AND P1, PT, |R0|.reuse, 0.60000002384185791016, PT ; /* 0x3f19999a0000780b */
/* 0x040fe20003f26200 */
/*00c0*/ FMUL R8, R0.reuse, R0 ; /* 0x0000000000087220 */
/* 0x040fe20000400000 */
/*00d0*/ FSETP.GE.AND P0, PT, |R0|, 9.010913848876953125, PT ; /* 0x41102cb40000780b */
/* 0x000fc60003f06200 */
/*00e0*/ MUFU.EX2 R4, R4 ; /* 0x0000000400047308 */
/* 0x000e240000000800 */
/*00f0*/ FFMA R7, R8, R7, -0.052303962409496307373 ; /* 0xbd563cae08077423 */
/* 0x000fc80000000007 */
/*0100*/ FFMA R9, R8, R7, 0.1331529766321182251 ; /* 0x3e08594108097423 */
/* 0x000fc80000000007 */
/*0110*/ FFMA R9, R8, R9, -0.33332768082618713379 ; /* 0xbeaaa9ed08097423 */
/* 0x000fc80000000009 */
/*0120*/ FFMA R9, R8, R9, RZ ; /* 0x0000000908097223 */
/* 0x000fe400000000ff */
/*0130*/ FADD R5, R4, 1 ; /* 0x3f80000004057421 */
/* 0x001fcc0000000000 */
/*0140*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x000e240000001000 */
/*0150*/ FFMA R6, R5, -2, R6 ; /* 0xc000000005067823 */
/* 0x001fca0000000006 */
/*0160*/ FSEL R7, R6, 1, !P0 ; /* 0x3f80000006077808 */
/* 0x000fc80004000000 */
/*0170*/ LOP3.LUT R7, R7, 0x80000000, R0.reuse, 0xf8, !PT ; /* 0x8000000007077812 */
/* 0x100fe200078ef800 */
/*0180*/ @!P1 FFMA R7, R0, R9, R0 ; /* 0x0000000900079223 */
/* 0x000fca0000000000 */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11tanh_kernelPfii
.globl _Z11tanh_kernelPfii
.p2align 8
.type _Z11tanh_kernelPfii,@function
_Z11tanh_kernelPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e64 s0, 0x3f200000, |v2|
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB0_2
v_add_f32_e64 v3, |v2|, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v4, 0x3fb8aa3b, v3
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
v_rndne_f32_e32 v5, v4
v_fma_f32 v6, v3, 0x3fb8aa3b, -v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v4, v5
v_fmamk_f32 v6, v3, 0x32a5705f, v6
v_cvt_i32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v4, v6
v_exp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
v_cndmask_b32_e32 v3, 0x7f800000, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, 1.0, v3
v_rcp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v3, v3, -2.0, 1.0
.LBB0_2:
s_and_not1_saveexec_b32 s0, s0
v_mul_f32_e32 v3, v2, v2
s_mov_b32 s1, 0xbbbac73d
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fmaak_f32 v4, s1, v3, 0x3ca908c9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v4, v3, v4, 0xbd5c1c4e
v_fmaak_f32 v4, v3, v4, 0x3e088382
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v4, v3, v4, 0xbeaaaa99
v_mul_f32_e64 v4, |v2|, v4
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v3, v3, v4, |v2|
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1)
v_bfi_b32 v2, 0x7fffffff, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11tanh_kernelPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11tanh_kernelPfii, .Lfunc_end0-_Z11tanh_kernelPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11tanh_kernelPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11tanh_kernelPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a4fc5_00000000-6_tanh_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11tanh_kernelPfiiPfii
.type _Z33__device_stub__Z11tanh_kernelPfiiPfii, @function
_Z33__device_stub__Z11tanh_kernelPfiiPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11tanh_kernelPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z33__device_stub__Z11tanh_kernelPfiiPfii, .-_Z33__device_stub__Z11tanh_kernelPfiiPfii
.globl _Z11tanh_kernelPfii
.type _Z11tanh_kernelPfii, @function
_Z11tanh_kernelPfii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11tanh_kernelPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z11tanh_kernelPfii, .-_Z11tanh_kernelPfii
.globl _Z11launch_tanhPfii
.type _Z11launch_tanhPfii, @function
_Z11launch_tanhPfii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl %esi, %ebx
movl %edx, %ebp
movl %esi, %edx
imull %ebp, %edx
leal 2046(%rdx), %eax
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebp, %edx
movl %ebx, %esi
movq %r12, %rdi
call _Z33__device_stub__Z11tanh_kernelPfiiPfii
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z11launch_tanhPfii, .-_Z11launch_tanhPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11tanh_kernelPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11tanh_kernelPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tanh_kernel.hip"
.globl _Z26__device_stub__tanh_kernelPfii # -- Begin function _Z26__device_stub__tanh_kernelPfii
.p2align 4, 0x90
.type _Z26__device_stub__tanh_kernelPfii,@function
_Z26__device_stub__tanh_kernelPfii: # @_Z26__device_stub__tanh_kernelPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11tanh_kernelPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__tanh_kernelPfii, .Lfunc_end0-_Z26__device_stub__tanh_kernelPfii
.cfi_endproc
# -- End function
.globl _Z11launch_tanhPfii # -- Begin function _Z11launch_tanhPfii
.p2align 4, 0x90
.type _Z11launch_tanhPfii,@function
_Z11launch_tanhPfii: # @_Z11launch_tanhPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl %edx, %edi
imull %esi, %edi
leal 1023(%rdi), %eax
addl $2046, %edi # imm = 0x7FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r14, 56(%rsp)
movl %ebp, 4(%rsp)
movl %ebx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11tanh_kernelPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11launch_tanhPfii, .Lfunc_end1-_Z11launch_tanhPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11tanh_kernelPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11tanh_kernelPfii,@object # @_Z11tanh_kernelPfii
.section .rodata,"a",@progbits
.globl _Z11tanh_kernelPfii
.p2align 3, 0x0
_Z11tanh_kernelPfii:
.quad _Z26__device_stub__tanh_kernelPfii
.size _Z11tanh_kernelPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11tanh_kernelPfii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__tanh_kernelPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11tanh_kernelPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <chrono>
using namespace std;
__global__
void addKernel( int* a, int* b, int* c )
{
int idx = threadIdx.x;
c[idx] = a[idx] + b[idx];
}
void testCudaAdd() {
const int COUNT = 10;
int* a = new int[COUNT];
int* b = new int[COUNT];
int* c = new int[COUNT];
for( int i=0;i<COUNT;++i) {
a[i] = i;
b[i] = i*100;
}
int *devArrayA = 0, *devArrayB = 0, *devArrayC = 0;
cudaMalloc( &devArrayA, sizeof(int) * COUNT );
cudaMalloc( &devArrayB, sizeof(int) * COUNT );
cudaMalloc( &devArrayC, sizeof(int) * COUNT );
// üÍf[^Ì].
cudaMemcpy( devArrayA, a, sizeof(int)*COUNT, cudaMemcpyHostToDevice );
cudaMemcpy( devArrayB, b, sizeof(int)*COUNT, cudaMemcpyHostToDevice );
// Às.
addKernel<<<1, COUNT>>>(devArrayA, devArrayB, devArrayC );
cudaDeviceSynchronize();
// ÊÌÇÝßµ.
cudaMemcpy( c, devArrayC, sizeof(int)*COUNT, cudaMemcpyDeviceToHost );
for(int i=0;i<COUNT;++i) {
printf( "%d ", c[i] );
}
printf( "\n" );
cudaFree( devArrayC );
cudaFree( devArrayB );
cudaFree( devArrayA );
delete[] a;
delete[] b;
delete[] c;
}
__global__
void multMatrix( float* a, float* b, float* c, int COUNT )
{
int idx = blockDim.x * threadIdx.y + threadIdx.x;
int idxCol = blockDim.x * blockIdx.x + threadIdx.x;
int idxRow = blockDim.y * blockIdx.y + threadIdx.y;
float scanSum = 0;
for( int i=0;i<COUNT;++i) {
if( idxCol >= COUNT || idxRow >= COUNT ) {
continue;
}
#if 01
scanSum += a[ idxRow*COUNT + i ] * b[ idxCol + i*COUNT ];
#else
// §xÌâèªo½ç.
scanSum = __fadd_rn( scanSum, __fmul_rn( a[idxRow*COUNT+i], b[idxCol+i*COUNT] ) );
#endif
}
if( idxCol < COUNT && idxRow < COUNT ) {
c[idxCol+idxRow*COUNT] = scanSum;
}
}
void testCudaMult() {
const int COUNT = 1024;
const int SIZE = COUNT*COUNT; // sñTCY
float* a = new float[SIZE];
float* b = new float[SIZE];
float* c = new float[SIZE];
for( int i=0;i<SIZE;++i) {
a[i] = float(0.001f * i );
b[i] = float(0.005f * i );
}
chrono::high_resolution_clock::time_point start, stop;
start = chrono::high_resolution_clock::now();
for( int i=0;i<COUNT;++i ) {
for( int j=0;j<COUNT;++j ) {
float tmp = float(0);
for(int t=0;t<COUNT;++t) {
tmp += a[t+i*COUNT] * b[j+COUNT*t];
}
c[i*COUNT+j] = tmp;
}
}
stop = chrono::high_resolution_clock::now();
#if 0
for(int i=0;i<COUNT;++i) {
for(int j=0;j<COUNT;++j) {
printf( "%f ", c[i*COUNT+j] );
}
printf( "\n" );
}
#endif
chrono::microseconds cpuTime = chrono::duration_cast<chrono::microseconds>(stop-start);
printf( "CPU: %d (us)\n", cpuTime.count() );
printf( "\n" );
float* gpuC = new float[SIZE];
for( int i=0;i<SIZE;++i) {
a[i] = float(0.001f * i );
b[i] = float(0.005f * i );
gpuC[i] = 0.0f;
}
float *devA, *devB, *devC;
cudaMalloc( &devA, sizeof(float) * SIZE );
cudaMalloc( &devB, sizeof(float) * SIZE );
cudaMalloc( &devC, sizeof(float) * SIZE );
cudaMemcpy( devA, a, sizeof(float)*SIZE, cudaMemcpyHostToDevice );
cudaMemcpy( devB, b, sizeof(float)*SIZE, cudaMemcpyHostToDevice );
start = chrono::high_resolution_clock::now();
const int thrCount=32;
int blockXY = ( COUNT + (thrCount-1) ) / thrCount;
dim3 blk( blockXY,blockXY);
dim3 thr( thrCount,thrCount);
multMatrix<<<blk,thr>>>( devA, devB, devC, COUNT );
cudaDeviceSynchronize();
stop = chrono::high_resolution_clock::now();
cudaMemcpy( gpuC, devC, sizeof(float)*SIZE, cudaMemcpyDeviceToHost );
#if 0
for(int i=0;i<COUNT;++i) {
for(int j=0;j<COUNT;++j) {
printf( "%.2f(%.2f) ", gpuC[i*COUNT+j], c[i*COUNT+j] );
}
printf( "\n" );
}
#endif
int mismatchCount = 0;
for(int i=0;i<SIZE;++i) {
if( c[i] != gpuC[i] ) {
mismatchCount++;
}
}
if( mismatchCount > 0 ) {
printf( "mismatchCount= %d (%d)\n", mismatchCount, SIZE );
}
chrono::microseconds gpuTime = chrono::duration_cast<chrono::microseconds>(stop-start);
printf( "GPU: %d (us)\n", gpuTime.count() );
printf( "\n" );
printf( "rate = %.4f (%dx%d matrix)\n", cpuTime.count() / (double)gpuTime.count(), COUNT, COUNT );
cudaFree( devA );
cudaFree( devB );
cudaFree( devC );
}
int main() {
printf( "Hello,CUDA\n" );
testCudaAdd();
testCudaMult();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z10multMatrixPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff107624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe40003f06270 */
/*0070*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e680000002500 */
/*0080*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc400078e0203 */
/*00a0*/ IMAD R5, R8, c[0x0][0x0], R7 ; /* 0x0000000008057a24 */
/* 0x002fc800078e0207 */
/*00b0*/ @!P0 BRA 0x550 ; /* 0x0000049000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R16.reuse, -0x1, RZ ; /* 0xffffffff10027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00e0*/ LOP3.LUT R4, R16, 0x3, RZ, 0xc0, !PT ; /* 0x0000000310047812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P2, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f46070 */
/*0100*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe40003f06270 */
/*0110*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0120*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fc40000000f00 */
/*0130*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fca0000706670 */
/*0140*/ @!P2 BRA 0x430 ; /* 0x000002e00000a947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD R2, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a24 */
/* 0x000fe200078e02ff */
/*0180*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe200000001ff */
/*0190*/ IMAD R15, R16.reuse, 0x3, R5 ; /* 0x00000003100f7824 */
/* 0x040fe200078e0205 */
/*01a0*/ LEA R16, R16, R5, 0x1 ; /* 0x0000000510107211 */
/* 0x000fe200078e08ff */
/*01b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*01c0*/ IADD3 R17, R4, -c[0x0][0x178], RZ ; /* 0x80005e0004117a10 */
/* 0x000fc60007ffe0ff */
/*01d0*/ IMAD R7, R8, c[0x0][0x0], R7 ; /* 0x0000000008077a24 */
/* 0x000fe200078e0207 */
/*01e0*/ MOV R10, R2 ; /* 0x00000002000a7202 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0003 */
/*0200*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.MOV.U32 R18, RZ, RZ, R5 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0005 */
/*0220*/ @!P0 MOV R3, 0x4 ; /* 0x0000000400038802 */
/* 0x000fe20000000f00 */
/*0230*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff088424 */
/* 0x000fe200078e00ff */
/*0240*/ @!P0 MOV R13, 0x4 ; /* 0x00000004000d8802 */
/* 0x000fc60000000f00 */
/*0250*/ @!P0 IMAD.WIDE R2, R18, R3, c[0x0][0x168] ; /* 0x00005a0012028625 */
/* 0x000fc800078e0203 */
/*0260*/ @!P0 IMAD.WIDE R8, R7, R8, c[0x0][0x168] ; /* 0x00005a0007088625 */
/* 0x000fe200078e0208 */
/*0270*/ @!P0 LDG.E R19, [R2.64] ; /* 0x0000000402138981 */
/* 0x0000a6000c1e1900 */
/*0280*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, 0x4 ; /* 0x00000004ff0c8424 */
/* 0x000fe400078e00ff */
/*0290*/ @!P0 LDG.E R9, [R8.64] ; /* 0x0000000408098981 */
/* 0x0002e2000c1e1900 */
/*02a0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x001fe200078e000a */
/*02b0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe20000000f00 */
/*02c0*/ @!P0 IMAD.WIDE R10, R16, R13, c[0x0][0x168] ; /* 0x00005a00100a8625 */
/* 0x000fc800078e020d */
/*02d0*/ @!P0 LDG.E R20, [R2.64] ; /* 0x0000000402148981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ @!P0 IMAD.WIDE R12, R15, R12, c[0x0][0x168] ; /* 0x00005a000f0c8625 */
/* 0x000fc600078e020c */
/*02f0*/ @!P0 LDG.E R21, [R2.64+0x4] ; /* 0x0000040402158981 */
/* 0x000ee8000c1e1900 */
/*0300*/ @!P0 LDG.E R11, [R10.64] ; /* 0x000000040a0b8981 */
/* 0x000128000c1e1900 */
/*0310*/ @!P0 LDG.E R22, [R2.64+0x8] ; /* 0x0000080402168981 */
/* 0x000f28000c1e1900 */
/*0320*/ @!P0 LDG.E R13, [R12.64] ; /* 0x000000040c0d8981 */
/* 0x000f68000c1e1900 */
/*0330*/ @!P0 LDG.E R23, [R2.64+0xc] ; /* 0x00000c0402178981 */
/* 0x000f62000c1e1900 */
/*0340*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fc80007ffe0ff */
/*0350*/ IADD3 R8, R17, R14, RZ ; /* 0x0000000e11087210 */
/* 0x002fc80007ffe0ff */
/*0360*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*0370*/ IADD3 R10, P3, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x001fe20007f7e0ff */
/*0380*/ @!P0 FFMA R6, R20, R19, R6 ; /* 0x0000001314068223 */
/* 0x004fc80000000006 */
/*0390*/ @!P0 FFMA R6, R9, R21, R6 ; /* 0x0000001509068223 */
/* 0x008fe40000000006 */
/*03a0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff097624 */
/* 0x000fe400078e00ff */
/*03b0*/ @!P0 FFMA R6, R11, R22, R6 ; /* 0x000000160b068223 */
/* 0x010fc60000000006 */
/*03c0*/ LEA R15, R9.reuse, R15, 0x2 ; /* 0x0000000f090f7211 */
/* 0x040fe200078e10ff */
/*03d0*/ IMAD R16, R9.reuse, 0x4, R16 ; /* 0x0000000409107824 */
/* 0x040fe200078e0210 */
/*03e0*/ LEA R7, R9.reuse, R7, 0x2 ; /* 0x0000000709077211 */
/* 0x040fe200078e10ff */
/*03f0*/ IMAD R18, R9, 0x4, R18 ; /* 0x0000000409127824 */
/* 0x000fe200078e0212 */
/*0400*/ IADD3.X R11, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff0b7210 */
/* 0x000fe20001ffe4ff */
/*0410*/ @!P0 FFMA R6, R13, R23, R6 ; /* 0x000000170d068223 */
/* 0x020fe20000000006 */
/*0420*/ @P2 BRA 0x220 ; /* 0xfffffdf000002947 */
/* 0x000fea000383ffff */
/*0430*/ @!P1 BRA 0x550 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0450*/ IMAD R2, R0, c[0x0][0x178], R14 ; /* 0x00005e0000027a24 */
/* 0x000fe400078e020e */
/*0460*/ IMAD R14, R14, c[0x0][0x178], R5 ; /* 0x00005e000e0e7a24 */
/* 0x000fc400078e0205 */
/*0470*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0480*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fe40000000f00 */
/*0490*/ MOV R9, R3 ; /* 0x0000000300097202 */
/* 0x000fc80000000f00 */
/*04a0*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fe200078e00ff */
/*04b0*/ @!P0 LDG.E R7, [R8.64] ; /* 0x0000000408078981 */
/* 0x0000a6000c1e1900 */
/*04c0*/ @!P0 IMAD.WIDE R2, R14, R3, c[0x0][0x168] ; /* 0x00005a000e028625 */
/* 0x000fcc00078e0203 */
/*04d0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000402028981 */
/* 0x000ea2000c1e1900 */
/*04e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0500*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x001fe40007f5e0ff */
/*0510*/ IADD3 R14, R14, c[0x0][0x178], RZ ; /* 0x00005e000e0e7a10 */
/* 0x000fe40007ffe0ff */
/*0520*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x000fe200017fe4ff */
/*0530*/ @!P0 FFMA R6, R7, R2, R6 ; /* 0x0000000207068223 */
/* 0x004fcc0000000006 */
/*0540*/ @P1 BRA 0x4a0 ; /* 0xffffff5000001947 */
/* 0x000fea000383ffff */
/*0550*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06270 */
/*0560*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fda0000706670 */
/*0570*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0580*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0590*/ IMAD R2, R0, c[0x0][0x178], R5 ; /* 0x00005e0000027a24 */
/* 0x000fd200078e0205 */
/*05a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*05b0*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101904 */
/*05c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05d0*/ BRA 0x5d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9addKernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <chrono>
using namespace std;
__global__
void addKernel( int* a, int* b, int* c )
{
int idx = threadIdx.x;
c[idx] = a[idx] + b[idx];
}
void testCudaAdd() {
const int COUNT = 10;
int* a = new int[COUNT];
int* b = new int[COUNT];
int* c = new int[COUNT];
for( int i=0;i<COUNT;++i) {
a[i] = i;
b[i] = i*100;
}
int *devArrayA = 0, *devArrayB = 0, *devArrayC = 0;
cudaMalloc( &devArrayA, sizeof(int) * COUNT );
cudaMalloc( &devArrayB, sizeof(int) * COUNT );
cudaMalloc( &devArrayC, sizeof(int) * COUNT );
// üÍf[^Ì].
cudaMemcpy( devArrayA, a, sizeof(int)*COUNT, cudaMemcpyHostToDevice );
cudaMemcpy( devArrayB, b, sizeof(int)*COUNT, cudaMemcpyHostToDevice );
// Às.
addKernel<<<1, COUNT>>>(devArrayA, devArrayB, devArrayC );
cudaDeviceSynchronize();
// ÊÌÇÝßµ.
cudaMemcpy( c, devArrayC, sizeof(int)*COUNT, cudaMemcpyDeviceToHost );
for(int i=0;i<COUNT;++i) {
printf( "%d ", c[i] );
}
printf( "\n" );
cudaFree( devArrayC );
cudaFree( devArrayB );
cudaFree( devArrayA );
delete[] a;
delete[] b;
delete[] c;
}
__global__
void multMatrix( float* a, float* b, float* c, int COUNT )
{
int idx = blockDim.x * threadIdx.y + threadIdx.x;
int idxCol = blockDim.x * blockIdx.x + threadIdx.x;
int idxRow = blockDim.y * blockIdx.y + threadIdx.y;
float scanSum = 0;
for( int i=0;i<COUNT;++i) {
if( idxCol >= COUNT || idxRow >= COUNT ) {
continue;
}
#if 01
scanSum += a[ idxRow*COUNT + i ] * b[ idxCol + i*COUNT ];
#else
// §xÌâèªo½ç.
scanSum = __fadd_rn( scanSum, __fmul_rn( a[idxRow*COUNT+i], b[idxCol+i*COUNT] ) );
#endif
}
if( idxCol < COUNT && idxRow < COUNT ) {
c[idxCol+idxRow*COUNT] = scanSum;
}
}
void testCudaMult() {
const int COUNT = 1024;
const int SIZE = COUNT*COUNT; // sñTCY
float* a = new float[SIZE];
float* b = new float[SIZE];
float* c = new float[SIZE];
for( int i=0;i<SIZE;++i) {
a[i] = float(0.001f * i );
b[i] = float(0.005f * i );
}
chrono::high_resolution_clock::time_point start, stop;
start = chrono::high_resolution_clock::now();
for( int i=0;i<COUNT;++i ) {
for( int j=0;j<COUNT;++j ) {
float tmp = float(0);
for(int t=0;t<COUNT;++t) {
tmp += a[t+i*COUNT] * b[j+COUNT*t];
}
c[i*COUNT+j] = tmp;
}
}
stop = chrono::high_resolution_clock::now();
#if 0
for(int i=0;i<COUNT;++i) {
for(int j=0;j<COUNT;++j) {
printf( "%f ", c[i*COUNT+j] );
}
printf( "\n" );
}
#endif
chrono::microseconds cpuTime = chrono::duration_cast<chrono::microseconds>(stop-start);
printf( "CPU: %d (us)\n", cpuTime.count() );
printf( "\n" );
float* gpuC = new float[SIZE];
for( int i=0;i<SIZE;++i) {
a[i] = float(0.001f * i );
b[i] = float(0.005f * i );
gpuC[i] = 0.0f;
}
float *devA, *devB, *devC;
cudaMalloc( &devA, sizeof(float) * SIZE );
cudaMalloc( &devB, sizeof(float) * SIZE );
cudaMalloc( &devC, sizeof(float) * SIZE );
cudaMemcpy( devA, a, sizeof(float)*SIZE, cudaMemcpyHostToDevice );
cudaMemcpy( devB, b, sizeof(float)*SIZE, cudaMemcpyHostToDevice );
start = chrono::high_resolution_clock::now();
const int thrCount=32;
int blockXY = ( COUNT + (thrCount-1) ) / thrCount;
dim3 blk( blockXY,blockXY);
dim3 thr( thrCount,thrCount);
multMatrix<<<blk,thr>>>( devA, devB, devC, COUNT );
cudaDeviceSynchronize();
stop = chrono::high_resolution_clock::now();
cudaMemcpy( gpuC, devC, sizeof(float)*SIZE, cudaMemcpyDeviceToHost );
#if 0
for(int i=0;i<COUNT;++i) {
for(int j=0;j<COUNT;++j) {
printf( "%.2f(%.2f) ", gpuC[i*COUNT+j], c[i*COUNT+j] );
}
printf( "\n" );
}
#endif
int mismatchCount = 0;
for(int i=0;i<SIZE;++i) {
if( c[i] != gpuC[i] ) {
mismatchCount++;
}
}
if( mismatchCount > 0 ) {
printf( "mismatchCount= %d (%d)\n", mismatchCount, SIZE );
}
chrono::microseconds gpuTime = chrono::duration_cast<chrono::microseconds>(stop-start);
printf( "GPU: %d (us)\n", gpuTime.count() );
printf( "\n" );
printf( "rate = %.4f (%dx%d matrix)\n", cpuTime.count() / (double)gpuTime.count(), COUNT, COUNT );
cudaFree( devA );
cudaFree( devB );
cudaFree( devC );
}
int main() {
printf( "Hello,CUDA\n" );
testCudaAdd();
testCudaMult();
cudaDeviceReset();
return 0;
} | .file "tmpxft_001a7e99_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2168:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2168:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
.type _Z32__device_stub__Z9addKernelPiS_S_PiS_S_, @function
_Z32__device_stub__Z9addKernelPiS_S_PiS_S_:
.LFB2190:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2190:
.size _Z32__device_stub__Z9addKernelPiS_S_PiS_S_, .-_Z32__device_stub__Z9addKernelPiS_S_PiS_S_
.globl _Z9addKernelPiS_S_
.type _Z9addKernelPiS_S_, @function
_Z9addKernelPiS_S_:
.LFB2191:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2191:
.size _Z9addKernelPiS_S_, .-_Z9addKernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z11testCudaAddv
.type _Z11testCudaAddv, @function
_Z11testCudaAddv:
.LFB2156:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, %edi
call _Znam@PLT
movq %rax, %r12
movl $40, %edi
call _Znam@PLT
movq %rax, %rbp
movl $40, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %edx
movl $0, %eax
.L12:
movl %eax, (%r12,%rax,4)
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
addl $100, %edx
cmpq $10, %rax
jne .L12
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 40(%r13), %r15
leaq .LC0(%rip), %r14
.L14:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2156:
.size _Z11testCudaAddv, .-_Z11testCudaAddv
.globl _Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i:
.LFB2192:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10multMatrixPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2192:
.size _Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i
.globl _Z10multMatrixPfS_S_i
.type _Z10multMatrixPfS_S_i, @function
_Z10multMatrixPfS_S_i:
.LFB2193:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2193:
.size _Z10multMatrixPfS_S_i, .-_Z10multMatrixPfS_S_i
.section .rodata.str1.1
.LC5:
.string "CPU: %d (us)\n"
.LC6:
.string "mismatchCount= %d (%d)\n"
.LC7:
.string "GPU: %d (us)\n"
.LC8:
.string "rate = %.4f (%dx%d matrix)\n"
.text
.globl _Z12testCudaMultv
.type _Z12testCudaMultv, @function
_Z12testCudaMultv:
.LFB2157:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbp
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbx
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
.L30:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss .LC3(%rip), %xmm1
mulss %xmm0, %xmm1
movss %xmm1, 0(%rbp,%rax,4)
mulss .LC4(%rip), %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L30
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movl $0, %r9d
jmp .L31
.L49:
movss %xmm1, (%rdi,%rsi,4)
addq $1, %rsi
addq $4, %rcx
cmpq $1024, %rsi
je .L33
.L35:
leaq -4194304(%rcx), %rax
movq %r8, %rdx
pxor %xmm1, %xmm1
.L32:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rdx
addq $4096, %rax
cmpq %rcx, %rax
jne .L32
jmp .L49
.L33:
addq $1, %r9
cmpq $1024, %r9
je .L34
.L31:
leaq 4194304(%rbx), %rcx
movq %r9, %rdi
salq $12, %rdi
leaq 0(%rbp,%rdi), %r8
addq %r12, %rdi
movl $0, %esi
jmp .L35
.L34:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r13, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %r14
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %eax
.L36:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss .LC3(%rip), %xmm1
mulss %xmm0, %xmm1
movss %xmm1, 0(%rbp,%rax,4)
mulss .LC4(%rip), %xmm0
movss %xmm0, (%rbx,%rax,4)
movl $0x00000000, 0(%r13,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L36
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L37:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %eax
movl $0, %edx
jmp .L40
.L50:
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i
jmp .L37
.L43:
addl $1, %edx
.L38:
addq $4, %rax
cmpq $4194304, %rax
je .L51
.L40:
movss (%r12,%rax), %xmm0
ucomiss 0(%r13,%rax), %xmm0
jp .L43
je .L38
jmp .L43
.L51:
testl %edx, %edx
jg .L52
.L41:
movq %rbp, %rcx
subq %rbx, %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rbx
subq %rcx, %rbx
movq %rbx, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rbx, %xmm1
divsd %xmm1, %xmm0
movl $1024, %ecx
movl $1024, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl $1048576, %ecx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L41
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2157:
.size _Z12testCudaMultv, .-_Z12testCudaMultv
.section .rodata.str1.1
.LC9:
.string "Hello,CUDA\n"
.text
.globl main
.type main, @function
main:
.LFB2165:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z11testCudaAddv
call _Z12testCudaMultv
call cudaDeviceReset@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2165:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z10multMatrixPfS_S_i"
.LC11:
.string "_Z9addKernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2195:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10multMatrixPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2195:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 981668463
.align 4
.LC4:
.long 1000593162
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <chrono>
using namespace std;
__global__
void addKernel( int* a, int* b, int* c )
{
int idx = threadIdx.x;
c[idx] = a[idx] + b[idx];
}
void testCudaAdd() {
const int COUNT = 10;
int* a = new int[COUNT];
int* b = new int[COUNT];
int* c = new int[COUNT];
for( int i=0;i<COUNT;++i) {
a[i] = i;
b[i] = i*100;
}
int *devArrayA = 0, *devArrayB = 0, *devArrayC = 0;
cudaMalloc( &devArrayA, sizeof(int) * COUNT );
cudaMalloc( &devArrayB, sizeof(int) * COUNT );
cudaMalloc( &devArrayC, sizeof(int) * COUNT );
// üÍf[^Ì].
cudaMemcpy( devArrayA, a, sizeof(int)*COUNT, cudaMemcpyHostToDevice );
cudaMemcpy( devArrayB, b, sizeof(int)*COUNT, cudaMemcpyHostToDevice );
// Às.
addKernel<<<1, COUNT>>>(devArrayA, devArrayB, devArrayC );
cudaDeviceSynchronize();
// ÊÌÇÝßµ.
cudaMemcpy( c, devArrayC, sizeof(int)*COUNT, cudaMemcpyDeviceToHost );
for(int i=0;i<COUNT;++i) {
printf( "%d ", c[i] );
}
printf( "\n" );
cudaFree( devArrayC );
cudaFree( devArrayB );
cudaFree( devArrayA );
delete[] a;
delete[] b;
delete[] c;
}
__global__
void multMatrix( float* a, float* b, float* c, int COUNT )
{
int idx = blockDim.x * threadIdx.y + threadIdx.x;
int idxCol = blockDim.x * blockIdx.x + threadIdx.x;
int idxRow = blockDim.y * blockIdx.y + threadIdx.y;
float scanSum = 0;
for( int i=0;i<COUNT;++i) {
if( idxCol >= COUNT || idxRow >= COUNT ) {
continue;
}
#if 01
scanSum += a[ idxRow*COUNT + i ] * b[ idxCol + i*COUNT ];
#else
// §xÌâèªo½ç.
scanSum = __fadd_rn( scanSum, __fmul_rn( a[idxRow*COUNT+i], b[idxCol+i*COUNT] ) );
#endif
}
if( idxCol < COUNT && idxRow < COUNT ) {
c[idxCol+idxRow*COUNT] = scanSum;
}
}
void testCudaMult() {
const int COUNT = 1024;
const int SIZE = COUNT*COUNT; // sñTCY
float* a = new float[SIZE];
float* b = new float[SIZE];
float* c = new float[SIZE];
for( int i=0;i<SIZE;++i) {
a[i] = float(0.001f * i );
b[i] = float(0.005f * i );
}
chrono::high_resolution_clock::time_point start, stop;
start = chrono::high_resolution_clock::now();
for( int i=0;i<COUNT;++i ) {
for( int j=0;j<COUNT;++j ) {
float tmp = float(0);
for(int t=0;t<COUNT;++t) {
tmp += a[t+i*COUNT] * b[j+COUNT*t];
}
c[i*COUNT+j] = tmp;
}
}
stop = chrono::high_resolution_clock::now();
#if 0
for(int i=0;i<COUNT;++i) {
for(int j=0;j<COUNT;++j) {
printf( "%f ", c[i*COUNT+j] );
}
printf( "\n" );
}
#endif
chrono::microseconds cpuTime = chrono::duration_cast<chrono::microseconds>(stop-start);
printf( "CPU: %d (us)\n", cpuTime.count() );
printf( "\n" );
float* gpuC = new float[SIZE];
for( int i=0;i<SIZE;++i) {
a[i] = float(0.001f * i );
b[i] = float(0.005f * i );
gpuC[i] = 0.0f;
}
float *devA, *devB, *devC;
cudaMalloc( &devA, sizeof(float) * SIZE );
cudaMalloc( &devB, sizeof(float) * SIZE );
cudaMalloc( &devC, sizeof(float) * SIZE );
cudaMemcpy( devA, a, sizeof(float)*SIZE, cudaMemcpyHostToDevice );
cudaMemcpy( devB, b, sizeof(float)*SIZE, cudaMemcpyHostToDevice );
start = chrono::high_resolution_clock::now();
const int thrCount=32;
int blockXY = ( COUNT + (thrCount-1) ) / thrCount;
dim3 blk( blockXY,blockXY);
dim3 thr( thrCount,thrCount);
multMatrix<<<blk,thr>>>( devA, devB, devC, COUNT );
cudaDeviceSynchronize();
stop = chrono::high_resolution_clock::now();
cudaMemcpy( gpuC, devC, sizeof(float)*SIZE, cudaMemcpyDeviceToHost );
#if 0
for(int i=0;i<COUNT;++i) {
for(int j=0;j<COUNT;++j) {
printf( "%.2f(%.2f) ", gpuC[i*COUNT+j], c[i*COUNT+j] );
}
printf( "\n" );
}
#endif
int mismatchCount = 0;
for(int i=0;i<SIZE;++i) {
if( c[i] != gpuC[i] ) {
mismatchCount++;
}
}
if( mismatchCount > 0 ) {
printf( "mismatchCount= %d (%d)\n", mismatchCount, SIZE );
}
chrono::microseconds gpuTime = chrono::duration_cast<chrono::microseconds>(stop-start);
printf( "GPU: %d (us)\n", gpuTime.count() );
printf( "\n" );
printf( "rate = %.4f (%dx%d matrix)\n", cpuTime.count() / (double)gpuTime.count(), COUNT, COUNT );
cudaFree( devA );
cudaFree( devB );
cudaFree( devC );
}
int main() {
printf( "Hello,CUDA\n" );
testCudaAdd();
testCudaMult();
cudaDeviceReset();
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <chrono>
using namespace std;
__global__
void addKernel( int* a, int* b, int* c )
{
int idx = threadIdx.x;
c[idx] = a[idx] + b[idx];
}
void testCudaAdd() {
const int COUNT = 10;
int* a = new int[COUNT];
int* b = new int[COUNT];
int* c = new int[COUNT];
for( int i=0;i<COUNT;++i) {
a[i] = i;
b[i] = i*100;
}
int *devArrayA = 0, *devArrayB = 0, *devArrayC = 0;
hipMalloc( &devArrayA, sizeof(int) * COUNT );
hipMalloc( &devArrayB, sizeof(int) * COUNT );
hipMalloc( &devArrayC, sizeof(int) * COUNT );
// üÍf[^Ì].
hipMemcpy( devArrayA, a, sizeof(int)*COUNT, hipMemcpyHostToDevice );
hipMemcpy( devArrayB, b, sizeof(int)*COUNT, hipMemcpyHostToDevice );
// Às.
addKernel<<<1, COUNT>>>(devArrayA, devArrayB, devArrayC );
hipDeviceSynchronize();
// ÊÌÇÝßµ.
hipMemcpy( c, devArrayC, sizeof(int)*COUNT, hipMemcpyDeviceToHost );
for(int i=0;i<COUNT;++i) {
printf( "%d ", c[i] );
}
printf( "\n" );
hipFree( devArrayC );
hipFree( devArrayB );
hipFree( devArrayA );
delete[] a;
delete[] b;
delete[] c;
}
__global__
void multMatrix( float* a, float* b, float* c, int COUNT )
{
int idx = blockDim.x * threadIdx.y + threadIdx.x;
int idxCol = blockDim.x * blockIdx.x + threadIdx.x;
int idxRow = blockDim.y * blockIdx.y + threadIdx.y;
float scanSum = 0;
for( int i=0;i<COUNT;++i) {
if( idxCol >= COUNT || idxRow >= COUNT ) {
continue;
}
#if 01
scanSum += a[ idxRow*COUNT + i ] * b[ idxCol + i*COUNT ];
#else
// §xÌâèªo½ç.
scanSum = __fadd_rn( scanSum, __fmul_rn( a[idxRow*COUNT+i], b[idxCol+i*COUNT] ) );
#endif
}
if( idxCol < COUNT && idxRow < COUNT ) {
c[idxCol+idxRow*COUNT] = scanSum;
}
}
void testCudaMult() {
const int COUNT = 1024;
const int SIZE = COUNT*COUNT; // sñTCY
float* a = new float[SIZE];
float* b = new float[SIZE];
float* c = new float[SIZE];
for( int i=0;i<SIZE;++i) {
a[i] = float(0.001f * i );
b[i] = float(0.005f * i );
}
chrono::high_resolution_clock::time_point start, stop;
start = chrono::high_resolution_clock::now();
for( int i=0;i<COUNT;++i ) {
for( int j=0;j<COUNT;++j ) {
float tmp = float(0);
for(int t=0;t<COUNT;++t) {
tmp += a[t+i*COUNT] * b[j+COUNT*t];
}
c[i*COUNT+j] = tmp;
}
}
stop = chrono::high_resolution_clock::now();
#if 0
for(int i=0;i<COUNT;++i) {
for(int j=0;j<COUNT;++j) {
printf( "%f ", c[i*COUNT+j] );
}
printf( "\n" );
}
#endif
chrono::microseconds cpuTime = chrono::duration_cast<chrono::microseconds>(stop-start);
printf( "CPU: %d (us)\n", cpuTime.count() );
printf( "\n" );
float* gpuC = new float[SIZE];
for( int i=0;i<SIZE;++i) {
a[i] = float(0.001f * i );
b[i] = float(0.005f * i );
gpuC[i] = 0.0f;
}
float *devA, *devB, *devC;
hipMalloc( &devA, sizeof(float) * SIZE );
hipMalloc( &devB, sizeof(float) * SIZE );
hipMalloc( &devC, sizeof(float) * SIZE );
hipMemcpy( devA, a, sizeof(float)*SIZE, hipMemcpyHostToDevice );
hipMemcpy( devB, b, sizeof(float)*SIZE, hipMemcpyHostToDevice );
start = chrono::high_resolution_clock::now();
const int thrCount=32;
int blockXY = ( COUNT + (thrCount-1) ) / thrCount;
dim3 blk( blockXY,blockXY);
dim3 thr( thrCount,thrCount);
multMatrix<<<blk,thr>>>( devA, devB, devC, COUNT );
hipDeviceSynchronize();
stop = chrono::high_resolution_clock::now();
hipMemcpy( gpuC, devC, sizeof(float)*SIZE, hipMemcpyDeviceToHost );
#if 0
for(int i=0;i<COUNT;++i) {
for(int j=0;j<COUNT;++j) {
printf( "%.2f(%.2f) ", gpuC[i*COUNT+j], c[i*COUNT+j] );
}
printf( "\n" );
}
#endif
int mismatchCount = 0;
for(int i=0;i<SIZE;++i) {
if( c[i] != gpuC[i] ) {
mismatchCount++;
}
}
if( mismatchCount > 0 ) {
printf( "mismatchCount= %d (%d)\n", mismatchCount, SIZE );
}
chrono::microseconds gpuTime = chrono::duration_cast<chrono::microseconds>(stop-start);
printf( "GPU: %d (us)\n", gpuTime.count() );
printf( "\n" );
printf( "rate = %.4f (%dx%d matrix)\n", cpuTime.count() / (double)gpuTime.count(), COUNT, COUNT );
hipFree( devA );
hipFree( devB );
hipFree( devC );
}
int main() {
printf( "Hello,CUDA\n" );
testCudaAdd();
testCudaMult();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <chrono>
using namespace std;
__global__
void addKernel( int* a, int* b, int* c )
{
int idx = threadIdx.x;
c[idx] = a[idx] + b[idx];
}
void testCudaAdd() {
const int COUNT = 10;
int* a = new int[COUNT];
int* b = new int[COUNT];
int* c = new int[COUNT];
for( int i=0;i<COUNT;++i) {
a[i] = i;
b[i] = i*100;
}
int *devArrayA = 0, *devArrayB = 0, *devArrayC = 0;
hipMalloc( &devArrayA, sizeof(int) * COUNT );
hipMalloc( &devArrayB, sizeof(int) * COUNT );
hipMalloc( &devArrayC, sizeof(int) * COUNT );
// üÍf[^Ì].
hipMemcpy( devArrayA, a, sizeof(int)*COUNT, hipMemcpyHostToDevice );
hipMemcpy( devArrayB, b, sizeof(int)*COUNT, hipMemcpyHostToDevice );
// Às.
addKernel<<<1, COUNT>>>(devArrayA, devArrayB, devArrayC );
hipDeviceSynchronize();
// ÊÌÇÝßµ.
hipMemcpy( c, devArrayC, sizeof(int)*COUNT, hipMemcpyDeviceToHost );
for(int i=0;i<COUNT;++i) {
printf( "%d ", c[i] );
}
printf( "\n" );
hipFree( devArrayC );
hipFree( devArrayB );
hipFree( devArrayA );
delete[] a;
delete[] b;
delete[] c;
}
__global__
void multMatrix( float* a, float* b, float* c, int COUNT )
{
int idx = blockDim.x * threadIdx.y + threadIdx.x;
int idxCol = blockDim.x * blockIdx.x + threadIdx.x;
int idxRow = blockDim.y * blockIdx.y + threadIdx.y;
float scanSum = 0;
for( int i=0;i<COUNT;++i) {
if( idxCol >= COUNT || idxRow >= COUNT ) {
continue;
}
#if 01
scanSum += a[ idxRow*COUNT + i ] * b[ idxCol + i*COUNT ];
#else
// §xÌâèªo½ç.
scanSum = __fadd_rn( scanSum, __fmul_rn( a[idxRow*COUNT+i], b[idxCol+i*COUNT] ) );
#endif
}
if( idxCol < COUNT && idxRow < COUNT ) {
c[idxCol+idxRow*COUNT] = scanSum;
}
}
void testCudaMult() {
const int COUNT = 1024;
const int SIZE = COUNT*COUNT; // sñTCY
float* a = new float[SIZE];
float* b = new float[SIZE];
float* c = new float[SIZE];
for( int i=0;i<SIZE;++i) {
a[i] = float(0.001f * i );
b[i] = float(0.005f * i );
}
chrono::high_resolution_clock::time_point start, stop;
start = chrono::high_resolution_clock::now();
for( int i=0;i<COUNT;++i ) {
for( int j=0;j<COUNT;++j ) {
float tmp = float(0);
for(int t=0;t<COUNT;++t) {
tmp += a[t+i*COUNT] * b[j+COUNT*t];
}
c[i*COUNT+j] = tmp;
}
}
stop = chrono::high_resolution_clock::now();
#if 0
for(int i=0;i<COUNT;++i) {
for(int j=0;j<COUNT;++j) {
printf( "%f ", c[i*COUNT+j] );
}
printf( "\n" );
}
#endif
chrono::microseconds cpuTime = chrono::duration_cast<chrono::microseconds>(stop-start);
printf( "CPU: %d (us)\n", cpuTime.count() );
printf( "\n" );
float* gpuC = new float[SIZE];
for( int i=0;i<SIZE;++i) {
a[i] = float(0.001f * i );
b[i] = float(0.005f * i );
gpuC[i] = 0.0f;
}
float *devA, *devB, *devC;
hipMalloc( &devA, sizeof(float) * SIZE );
hipMalloc( &devB, sizeof(float) * SIZE );
hipMalloc( &devC, sizeof(float) * SIZE );
hipMemcpy( devA, a, sizeof(float)*SIZE, hipMemcpyHostToDevice );
hipMemcpy( devB, b, sizeof(float)*SIZE, hipMemcpyHostToDevice );
start = chrono::high_resolution_clock::now();
const int thrCount=32;
int blockXY = ( COUNT + (thrCount-1) ) / thrCount;
dim3 blk( blockXY,blockXY);
dim3 thr( thrCount,thrCount);
multMatrix<<<blk,thr>>>( devA, devB, devC, COUNT );
hipDeviceSynchronize();
stop = chrono::high_resolution_clock::now();
hipMemcpy( gpuC, devC, sizeof(float)*SIZE, hipMemcpyDeviceToHost );
#if 0
for(int i=0;i<COUNT;++i) {
for(int j=0;j<COUNT;++j) {
printf( "%.2f(%.2f) ", gpuC[i*COUNT+j], c[i*COUNT+j] );
}
printf( "\n" );
}
#endif
int mismatchCount = 0;
for(int i=0;i<SIZE;++i) {
if( c[i] != gpuC[i] ) {
mismatchCount++;
}
}
if( mismatchCount > 0 ) {
printf( "mismatchCount= %d (%d)\n", mismatchCount, SIZE );
}
chrono::microseconds gpuTime = chrono::duration_cast<chrono::microseconds>(stop-start);
printf( "GPU: %d (us)\n", gpuTime.count() );
printf( "\n" );
printf( "rate = %.4f (%dx%d matrix)\n", cpuTime.count() / (double)gpuTime.count(), COUNT, COUNT );
hipFree( devA );
hipFree( devB );
hipFree( devC );
}
int main() {
printf( "Hello,CUDA\n" );
testCudaAdd();
testCudaMult();
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiS_S_
.globl _Z9addKernelPiS_S_
.p2align 8
.type _Z9addKernelPiS_S_,@function
_Z9addKernelPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiS_S_, .Lfunc_end0-_Z9addKernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10multMatrixPfS_S_i
.globl _Z10multMatrixPfS_S_i
.p2align 8
.type _Z10multMatrixPfS_S_i,@function
_Z10multMatrixPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_cmp_lt_i32 s3, 1
v_max_i32_e32 v7, v0, v1
s_cbranch_scc1 .LBB1_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s3
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v7
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s8, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v4, s3, v4
v_add_nc_u32_e32 v2, 1, v2
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB1_6
.LBB1_3:
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_lshlrev_b64 v[10:11], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s2, s4, v8
v_add_co_ci_u32_e64 v9, s2, s5, v9, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s2, s6, v10
v_add_co_ci_u32_e64 v11, s2, s7, v11, s2
global_load_b32 v3, v[8:9], off
global_load_b32 v5, v[10:11], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v5
s_branch .LBB1_2
.LBB1_5:
v_mov_b32_e32 v6, 0
.LBB1_6:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v7
s_cbranch_execz .LBB1_8
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10multMatrixPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10multMatrixPfS_S_i, .Lfunc_end1-_Z10multMatrixPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10multMatrixPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10multMatrixPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <chrono>
using namespace std;
__global__
void addKernel( int* a, int* b, int* c )
{
int idx = threadIdx.x;
c[idx] = a[idx] + b[idx];
}
void testCudaAdd() {
const int COUNT = 10;
int* a = new int[COUNT];
int* b = new int[COUNT];
int* c = new int[COUNT];
for( int i=0;i<COUNT;++i) {
a[i] = i;
b[i] = i*100;
}
int *devArrayA = 0, *devArrayB = 0, *devArrayC = 0;
hipMalloc( &devArrayA, sizeof(int) * COUNT );
hipMalloc( &devArrayB, sizeof(int) * COUNT );
hipMalloc( &devArrayC, sizeof(int) * COUNT );
// üÍf[^Ì].
hipMemcpy( devArrayA, a, sizeof(int)*COUNT, hipMemcpyHostToDevice );
hipMemcpy( devArrayB, b, sizeof(int)*COUNT, hipMemcpyHostToDevice );
// Às.
addKernel<<<1, COUNT>>>(devArrayA, devArrayB, devArrayC );
hipDeviceSynchronize();
// ÊÌÇÝßµ.
hipMemcpy( c, devArrayC, sizeof(int)*COUNT, hipMemcpyDeviceToHost );
for(int i=0;i<COUNT;++i) {
printf( "%d ", c[i] );
}
printf( "\n" );
hipFree( devArrayC );
hipFree( devArrayB );
hipFree( devArrayA );
delete[] a;
delete[] b;
delete[] c;
}
__global__
void multMatrix( float* a, float* b, float* c, int COUNT )
{
int idx = blockDim.x * threadIdx.y + threadIdx.x;
int idxCol = blockDim.x * blockIdx.x + threadIdx.x;
int idxRow = blockDim.y * blockIdx.y + threadIdx.y;
float scanSum = 0;
for( int i=0;i<COUNT;++i) {
if( idxCol >= COUNT || idxRow >= COUNT ) {
continue;
}
#if 01
scanSum += a[ idxRow*COUNT + i ] * b[ idxCol + i*COUNT ];
#else
// §xÌâèªo½ç.
scanSum = __fadd_rn( scanSum, __fmul_rn( a[idxRow*COUNT+i], b[idxCol+i*COUNT] ) );
#endif
}
if( idxCol < COUNT && idxRow < COUNT ) {
c[idxCol+idxRow*COUNT] = scanSum;
}
}
void testCudaMult() {
const int COUNT = 1024;
const int SIZE = COUNT*COUNT; // sñTCY
float* a = new float[SIZE];
float* b = new float[SIZE];
float* c = new float[SIZE];
for( int i=0;i<SIZE;++i) {
a[i] = float(0.001f * i );
b[i] = float(0.005f * i );
}
chrono::high_resolution_clock::time_point start, stop;
start = chrono::high_resolution_clock::now();
for( int i=0;i<COUNT;++i ) {
for( int j=0;j<COUNT;++j ) {
float tmp = float(0);
for(int t=0;t<COUNT;++t) {
tmp += a[t+i*COUNT] * b[j+COUNT*t];
}
c[i*COUNT+j] = tmp;
}
}
stop = chrono::high_resolution_clock::now();
#if 0
for(int i=0;i<COUNT;++i) {
for(int j=0;j<COUNT;++j) {
printf( "%f ", c[i*COUNT+j] );
}
printf( "\n" );
}
#endif
chrono::microseconds cpuTime = chrono::duration_cast<chrono::microseconds>(stop-start);
printf( "CPU: %d (us)\n", cpuTime.count() );
printf( "\n" );
float* gpuC = new float[SIZE];
for( int i=0;i<SIZE;++i) {
a[i] = float(0.001f * i );
b[i] = float(0.005f * i );
gpuC[i] = 0.0f;
}
float *devA, *devB, *devC;
hipMalloc( &devA, sizeof(float) * SIZE );
hipMalloc( &devB, sizeof(float) * SIZE );
hipMalloc( &devC, sizeof(float) * SIZE );
hipMemcpy( devA, a, sizeof(float)*SIZE, hipMemcpyHostToDevice );
hipMemcpy( devB, b, sizeof(float)*SIZE, hipMemcpyHostToDevice );
start = chrono::high_resolution_clock::now();
const int thrCount=32;
int blockXY = ( COUNT + (thrCount-1) ) / thrCount;
dim3 blk( blockXY,blockXY);
dim3 thr( thrCount,thrCount);
multMatrix<<<blk,thr>>>( devA, devB, devC, COUNT );
hipDeviceSynchronize();
stop = chrono::high_resolution_clock::now();
hipMemcpy( gpuC, devC, sizeof(float)*SIZE, hipMemcpyDeviceToHost );
#if 0
for(int i=0;i<COUNT;++i) {
for(int j=0;j<COUNT;++j) {
printf( "%.2f(%.2f) ", gpuC[i*COUNT+j], c[i*COUNT+j] );
}
printf( "\n" );
}
#endif
int mismatchCount = 0;
for(int i=0;i<SIZE;++i) {
if( c[i] != gpuC[i] ) {
mismatchCount++;
}
}
if( mismatchCount > 0 ) {
printf( "mismatchCount= %d (%d)\n", mismatchCount, SIZE );
}
chrono::microseconds gpuTime = chrono::duration_cast<chrono::microseconds>(stop-start);
printf( "GPU: %d (us)\n", gpuTime.count() );
printf( "\n" );
printf( "rate = %.4f (%dx%d matrix)\n", cpuTime.count() / (double)gpuTime.count(), COUNT, COUNT );
hipFree( devA );
hipFree( devB );
hipFree( devC );
}
int main() {
printf( "Hello,CUDA\n" );
testCudaAdd();
testCudaMult();
hipDeviceReset();
return 0;
} | .text
.file "kernel.hip"
.globl _Z24__device_stub__addKernelPiS_S_ # -- Begin function _Z24__device_stub__addKernelPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiS_S_,@function
_Z24__device_stub__addKernelPiS_S_: # @_Z24__device_stub__addKernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiS_S_, .Lfunc_end0-_Z24__device_stub__addKernelPiS_S_
.cfi_endproc
# -- End function
.globl _Z11testCudaAddv # -- Begin function _Z11testCudaAddv
.p2align 4, 0x90
.type _Z11testCudaAddv,@function
_Z11testCudaAddv: # @_Z11testCudaAddv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq _Znam
movq %rax, %rbx
movl $40, %edi
callq _Znam
movq %rax, %r14
movl $40, %edi
callq _Znam
movq %rax, %r15
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%rbx,%rcx,4)
movl %eax, (%r14,%rcx,4)
incq %rcx
addl $100, %eax
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11testCudaAddv, .Lfunc_end1-_Z11testCudaAddv
.cfi_endproc
# -- End function
.globl _Z25__device_stub__multMatrixPfS_S_i # -- Begin function _Z25__device_stub__multMatrixPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__multMatrixPfS_S_i,@function
_Z25__device_stub__multMatrixPfS_S_i: # @_Z25__device_stub__multMatrixPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10multMatrixPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__multMatrixPfS_S_i, .Lfunc_end2-_Z25__device_stub__multMatrixPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12testCudaMultv
.LCPI3_0:
.long 0x3a83126f # float 0.00100000005
.LCPI3_1:
.long 0x3ba3d70a # float 0.00499999989
.text
.globl _Z12testCudaMultv
.p2align 4, 0x90
.type _Z12testCudaMultv,@function
_Z12testCudaMultv: # @_Z12testCudaMultv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r12
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movaps %xmm0, %xmm1
mulss .LCPI3_0(%rip), %xmm1
movss %xmm1, (%r12,%rax,4)
mulss .LCPI3_1(%rip), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB3_1
# %bb.2:
xorl %r13d, %r13d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq %r12, %rax
.p2align 4, 0x90
.LBB3_3: # %.preheader80
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_5 Depth 3
movq %r13, %rcx
shlq $12, %rcx
addq %rbx, %rcx
movq %r15, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_4: # %.preheader
# Parent Loop BB3_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_5 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_3 Depth=1
# Parent Loop BB3_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $4096, %rdi # imm = 0x1000
cmpq $1024, %r8 # imm = 0x400
jne .LBB3_5
# %bb.6: # in Loop: Header=BB3_4 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB3_4
# %bb.7: # in Loop: Header=BB3_3 Depth=1
incq %r13
addq $4096, %rax # imm = 0x1000
cmpq $1024, %r13 # imm = 0x400
jne .LBB3_3
# %bb.8:
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r14
movq %rdx, %rax
shrq $63, %rax
sarq $7, %r14
addq %rax, %r14
xorl %ebp, %ebp
movl $.L.str.2, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r13
movl $4194304, %edx # imm = 0x400000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movss .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_9: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
movaps %xmm0, %xmm1
mulss %xmm2, %xmm1
movss %xmm1, (%r12,%rbp,4)
mulss %xmm3, %xmm0
movss %xmm0, (%r15,%rbp,4)
incq %rbp
cmpq $1048576, %rbp # imm = 0x100000
jne .LBB3_9
# %bb.10:
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
xorl %r12d, %r12d
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_12
# %bb.11:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10multMatrixPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_12:
callq hipDeviceSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbp
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_13: # =>This Inner Loop Header: Depth=1
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpneqss (%rbx,%rax,4), %xmm0
movd %xmm0, %ecx
subl %ecx, %r12d
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB3_13
# %bb.14:
testl %r12d, %r12d
je .LBB3_16
# %bb.15:
movl $.L.str.3, %edi
movl %r12d, %esi
movl $1048576, %edx # imm = 0x100000
xorl %eax, %eax
callq printf
.LBB3_16:
subq %r15, %rbp
movq %rbp, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rbx
movq %rdx, %rax
shrq $63, %rax
sarq $7, %rbx
addq %rax, %rbx
movl $.L.str.4, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
cvtsi2sd %rbx, %xmm1
divsd %xmm1, %xmm0
movl $.L.str.5, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12testCudaMultv, .Lfunc_end3-_Z12testCudaMultv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
callq _Z11testCudaAddv
callq _Z12testCudaMultv
callq hipDeviceReset
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10multMatrixPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiS_S_,@object # @_Z9addKernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiS_S_
.p2align 3, 0x0
_Z9addKernelPiS_S_:
.quad _Z24__device_stub__addKernelPiS_S_
.size _Z9addKernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type _Z10multMatrixPfS_S_i,@object # @_Z10multMatrixPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10multMatrixPfS_S_i
.p2align 3, 0x0
_Z10multMatrixPfS_S_i:
.quad _Z25__device_stub__multMatrixPfS_S_i
.size _Z10multMatrixPfS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "CPU: %d (us)\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "mismatchCount= %d (%d)\n"
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU: %d (us)\n"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "rate = %.4f (%dx%d matrix)\n"
.size .L.str.5, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiS_S_"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10multMatrixPfS_S_i"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello,CUDA"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiS_S_
.addrsig_sym _Z25__device_stub__multMatrixPfS_S_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiS_S_
.addrsig_sym _Z10multMatrixPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10multMatrixPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff107624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe40003f06270 */
/*0070*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e680000002500 */
/*0080*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc400078e0203 */
/*00a0*/ IMAD R5, R8, c[0x0][0x0], R7 ; /* 0x0000000008057a24 */
/* 0x002fc800078e0207 */
/*00b0*/ @!P0 BRA 0x550 ; /* 0x0000049000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R16.reuse, -0x1, RZ ; /* 0xffffffff10027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00e0*/ LOP3.LUT R4, R16, 0x3, RZ, 0xc0, !PT ; /* 0x0000000310047812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P2, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f46070 */
/*0100*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe40003f06270 */
/*0110*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0120*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fc40000000f00 */
/*0130*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fca0000706670 */
/*0140*/ @!P2 BRA 0x430 ; /* 0x000002e00000a947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD R2, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a24 */
/* 0x000fe200078e02ff */
/*0180*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe200000001ff */
/*0190*/ IMAD R15, R16.reuse, 0x3, R5 ; /* 0x00000003100f7824 */
/* 0x040fe200078e0205 */
/*01a0*/ LEA R16, R16, R5, 0x1 ; /* 0x0000000510107211 */
/* 0x000fe200078e08ff */
/*01b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*01c0*/ IADD3 R17, R4, -c[0x0][0x178], RZ ; /* 0x80005e0004117a10 */
/* 0x000fc60007ffe0ff */
/*01d0*/ IMAD R7, R8, c[0x0][0x0], R7 ; /* 0x0000000008077a24 */
/* 0x000fe200078e0207 */
/*01e0*/ MOV R10, R2 ; /* 0x00000002000a7202 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0003 */
/*0200*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.MOV.U32 R18, RZ, RZ, R5 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0005 */
/*0220*/ @!P0 MOV R3, 0x4 ; /* 0x0000000400038802 */
/* 0x000fe20000000f00 */
/*0230*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff088424 */
/* 0x000fe200078e00ff */
/*0240*/ @!P0 MOV R13, 0x4 ; /* 0x00000004000d8802 */
/* 0x000fc60000000f00 */
/*0250*/ @!P0 IMAD.WIDE R2, R18, R3, c[0x0][0x168] ; /* 0x00005a0012028625 */
/* 0x000fc800078e0203 */
/*0260*/ @!P0 IMAD.WIDE R8, R7, R8, c[0x0][0x168] ; /* 0x00005a0007088625 */
/* 0x000fe200078e0208 */
/*0270*/ @!P0 LDG.E R19, [R2.64] ; /* 0x0000000402138981 */
/* 0x0000a6000c1e1900 */
/*0280*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, 0x4 ; /* 0x00000004ff0c8424 */
/* 0x000fe400078e00ff */
/*0290*/ @!P0 LDG.E R9, [R8.64] ; /* 0x0000000408098981 */
/* 0x0002e2000c1e1900 */
/*02a0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x001fe200078e000a */
/*02b0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe20000000f00 */
/*02c0*/ @!P0 IMAD.WIDE R10, R16, R13, c[0x0][0x168] ; /* 0x00005a00100a8625 */
/* 0x000fc800078e020d */
/*02d0*/ @!P0 LDG.E R20, [R2.64] ; /* 0x0000000402148981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ @!P0 IMAD.WIDE R12, R15, R12, c[0x0][0x168] ; /* 0x00005a000f0c8625 */
/* 0x000fc600078e020c */
/*02f0*/ @!P0 LDG.E R21, [R2.64+0x4] ; /* 0x0000040402158981 */
/* 0x000ee8000c1e1900 */
/*0300*/ @!P0 LDG.E R11, [R10.64] ; /* 0x000000040a0b8981 */
/* 0x000128000c1e1900 */
/*0310*/ @!P0 LDG.E R22, [R2.64+0x8] ; /* 0x0000080402168981 */
/* 0x000f28000c1e1900 */
/*0320*/ @!P0 LDG.E R13, [R12.64] ; /* 0x000000040c0d8981 */
/* 0x000f68000c1e1900 */
/*0330*/ @!P0 LDG.E R23, [R2.64+0xc] ; /* 0x00000c0402178981 */
/* 0x000f62000c1e1900 */
/*0340*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fc80007ffe0ff */
/*0350*/ IADD3 R8, R17, R14, RZ ; /* 0x0000000e11087210 */
/* 0x002fc80007ffe0ff */
/*0360*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*0370*/ IADD3 R10, P3, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x001fe20007f7e0ff */
/*0380*/ @!P0 FFMA R6, R20, R19, R6 ; /* 0x0000001314068223 */
/* 0x004fc80000000006 */
/*0390*/ @!P0 FFMA R6, R9, R21, R6 ; /* 0x0000001509068223 */
/* 0x008fe40000000006 */
/*03a0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff097624 */
/* 0x000fe400078e00ff */
/*03b0*/ @!P0 FFMA R6, R11, R22, R6 ; /* 0x000000160b068223 */
/* 0x010fc60000000006 */
/*03c0*/ LEA R15, R9.reuse, R15, 0x2 ; /* 0x0000000f090f7211 */
/* 0x040fe200078e10ff */
/*03d0*/ IMAD R16, R9.reuse, 0x4, R16 ; /* 0x0000000409107824 */
/* 0x040fe200078e0210 */
/*03e0*/ LEA R7, R9.reuse, R7, 0x2 ; /* 0x0000000709077211 */
/* 0x040fe200078e10ff */
/*03f0*/ IMAD R18, R9, 0x4, R18 ; /* 0x0000000409127824 */
/* 0x000fe200078e0212 */
/*0400*/ IADD3.X R11, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff0b7210 */
/* 0x000fe20001ffe4ff */
/*0410*/ @!P0 FFMA R6, R13, R23, R6 ; /* 0x000000170d068223 */
/* 0x020fe20000000006 */
/*0420*/ @P2 BRA 0x220 ; /* 0xfffffdf000002947 */
/* 0x000fea000383ffff */
/*0430*/ @!P1 BRA 0x550 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0450*/ IMAD R2, R0, c[0x0][0x178], R14 ; /* 0x00005e0000027a24 */
/* 0x000fe400078e020e */
/*0460*/ IMAD R14, R14, c[0x0][0x178], R5 ; /* 0x00005e000e0e7a24 */
/* 0x000fc400078e0205 */
/*0470*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0480*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fe40000000f00 */
/*0490*/ MOV R9, R3 ; /* 0x0000000300097202 */
/* 0x000fc80000000f00 */
/*04a0*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fe200078e00ff */
/*04b0*/ @!P0 LDG.E R7, [R8.64] ; /* 0x0000000408078981 */
/* 0x0000a6000c1e1900 */
/*04c0*/ @!P0 IMAD.WIDE R2, R14, R3, c[0x0][0x168] ; /* 0x00005a000e028625 */
/* 0x000fcc00078e0203 */
/*04d0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000402028981 */
/* 0x000ea2000c1e1900 */
/*04e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0500*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x001fe40007f5e0ff */
/*0510*/ IADD3 R14, R14, c[0x0][0x178], RZ ; /* 0x00005e000e0e7a10 */
/* 0x000fe40007ffe0ff */
/*0520*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x000fe200017fe4ff */
/*0530*/ @!P0 FFMA R6, R7, R2, R6 ; /* 0x0000000207068223 */
/* 0x004fcc0000000006 */
/*0540*/ @P1 BRA 0x4a0 ; /* 0xffffff5000001947 */
/* 0x000fea000383ffff */
/*0550*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06270 */
/*0560*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fda0000706670 */
/*0570*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0580*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0590*/ IMAD R2, R0, c[0x0][0x178], R5 ; /* 0x00005e0000027a24 */
/* 0x000fd200078e0205 */
/*05a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*05b0*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101904 */
/*05c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05d0*/ BRA 0x5d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9addKernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiS_S_
.globl _Z9addKernelPiS_S_
.p2align 8
.type _Z9addKernelPiS_S_,@function
_Z9addKernelPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiS_S_, .Lfunc_end0-_Z9addKernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10multMatrixPfS_S_i
.globl _Z10multMatrixPfS_S_i
.p2align 8
.type _Z10multMatrixPfS_S_i,@function
_Z10multMatrixPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_cmp_lt_i32 s3, 1
v_max_i32_e32 v7, v0, v1
s_cbranch_scc1 .LBB1_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s3
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v7
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s8, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v4, s3, v4
v_add_nc_u32_e32 v2, 1, v2
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB1_6
.LBB1_3:
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_lshlrev_b64 v[10:11], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s2, s4, v8
v_add_co_ci_u32_e64 v9, s2, s5, v9, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s2, s6, v10
v_add_co_ci_u32_e64 v11, s2, s7, v11, s2
global_load_b32 v3, v[8:9], off
global_load_b32 v5, v[10:11], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v5
s_branch .LBB1_2
.LBB1_5:
v_mov_b32_e32 v6, 0
.LBB1_6:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v7
s_cbranch_execz .LBB1_8
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10multMatrixPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10multMatrixPfS_S_i, .Lfunc_end1-_Z10multMatrixPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10multMatrixPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10multMatrixPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a7e99_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2168:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2168:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
.type _Z32__device_stub__Z9addKernelPiS_S_PiS_S_, @function
_Z32__device_stub__Z9addKernelPiS_S_PiS_S_:
.LFB2190:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2190:
.size _Z32__device_stub__Z9addKernelPiS_S_PiS_S_, .-_Z32__device_stub__Z9addKernelPiS_S_PiS_S_
.globl _Z9addKernelPiS_S_
.type _Z9addKernelPiS_S_, @function
_Z9addKernelPiS_S_:
.LFB2191:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2191:
.size _Z9addKernelPiS_S_, .-_Z9addKernelPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z11testCudaAddv
.type _Z11testCudaAddv, @function
_Z11testCudaAddv:
.LFB2156:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, %edi
call _Znam@PLT
movq %rax, %r12
movl $40, %edi
call _Znam@PLT
movq %rax, %rbp
movl $40, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %edx
movl $0, %eax
.L12:
movl %eax, (%r12,%rax,4)
movl %edx, 0(%rbp,%rax,4)
addq $1, %rax
addl $100, %edx
cmpq $10, %rax
jne .L12
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
leaq 40(%r13), %r15
leaq .LC0(%rip), %r14
.L14:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9addKernelPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2156:
.size _Z11testCudaAddv, .-_Z11testCudaAddv
.globl _Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i:
.LFB2192:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10multMatrixPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2192:
.size _Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i
.globl _Z10multMatrixPfS_S_i
.type _Z10multMatrixPfS_S_i, @function
_Z10multMatrixPfS_S_i:
.LFB2193:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2193:
.size _Z10multMatrixPfS_S_i, .-_Z10multMatrixPfS_S_i
.section .rodata.str1.1
.LC5:
.string "CPU: %d (us)\n"
.LC6:
.string "mismatchCount= %d (%d)\n"
.LC7:
.string "GPU: %d (us)\n"
.LC8:
.string "rate = %.4f (%dx%d matrix)\n"
.text
.globl _Z12testCudaMultv
.type _Z12testCudaMultv, @function
_Z12testCudaMultv:
.LFB2157:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbp
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbx
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
.L30:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss .LC3(%rip), %xmm1
mulss %xmm0, %xmm1
movss %xmm1, 0(%rbp,%rax,4)
mulss .LC4(%rip), %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L30
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movl $0, %r9d
jmp .L31
.L49:
movss %xmm1, (%rdi,%rsi,4)
addq $1, %rsi
addq $4, %rcx
cmpq $1024, %rsi
je .L33
.L35:
leaq -4194304(%rcx), %rax
movq %r8, %rdx
pxor %xmm1, %xmm1
.L32:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rdx
addq $4096, %rax
cmpq %rcx, %rax
jne .L32
jmp .L49
.L33:
addq $1, %r9
cmpq $1024, %r9
je .L34
.L31:
leaq 4194304(%rbx), %rcx
movq %r9, %rdi
salq $12, %rdi
leaq 0(%rbp,%rdi), %r8
addq %r12, %rdi
movl $0, %esi
jmp .L35
.L34:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r13, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %r14
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %eax
.L36:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss .LC3(%rip), %xmm1
mulss %xmm0, %xmm1
movss %xmm1, 0(%rbp,%rax,4)
mulss .LC4(%rip), %xmm0
movss %xmm0, (%rbx,%rax,4)
movl $0x00000000, 0(%r13,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L36
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L37:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %eax
movl $0, %edx
jmp .L40
.L50:
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10multMatrixPfS_S_iPfS_S_i
jmp .L37
.L43:
addl $1, %edx
.L38:
addq $4, %rax
cmpq $4194304, %rax
je .L51
.L40:
movss (%r12,%rax), %xmm0
ucomiss 0(%r13,%rax), %xmm0
jp .L43
je .L38
jmp .L43
.L51:
testl %edx, %edx
jg .L52
.L41:
movq %rbp, %rcx
subq %rbx, %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rbx
subq %rcx, %rbx
movq %rbx, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rbx, %xmm1
divsd %xmm1, %xmm0
movl $1024, %ecx
movl $1024, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl $1048576, %ecx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L41
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2157:
.size _Z12testCudaMultv, .-_Z12testCudaMultv
.section .rodata.str1.1
.LC9:
.string "Hello,CUDA\n"
.text
.globl main
.type main, @function
main:
.LFB2165:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z11testCudaAddv
call _Z12testCudaMultv
call cudaDeviceReset@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2165:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z10multMatrixPfS_S_i"
.LC11:
.string "_Z9addKernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2195:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10multMatrixPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2195:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 981668463
.align 4
.LC4:
.long 1000593162
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z24__device_stub__addKernelPiS_S_ # -- Begin function _Z24__device_stub__addKernelPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiS_S_,@function
_Z24__device_stub__addKernelPiS_S_: # @_Z24__device_stub__addKernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiS_S_, .Lfunc_end0-_Z24__device_stub__addKernelPiS_S_
.cfi_endproc
# -- End function
.globl _Z11testCudaAddv # -- Begin function _Z11testCudaAddv
.p2align 4, 0x90
.type _Z11testCudaAddv,@function
_Z11testCudaAddv: # @_Z11testCudaAddv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq _Znam
movq %rax, %rbx
movl $40, %edi
callq _Znam
movq %rax, %r14
movl $40, %edi
callq _Znam
movq %rax, %r15
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%rbx,%rcx,4)
movl %eax, (%r14,%rcx,4)
incq %rcx
addl $100, %eax
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11testCudaAddv, .Lfunc_end1-_Z11testCudaAddv
.cfi_endproc
# -- End function
.globl _Z25__device_stub__multMatrixPfS_S_i # -- Begin function _Z25__device_stub__multMatrixPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__multMatrixPfS_S_i,@function
_Z25__device_stub__multMatrixPfS_S_i: # @_Z25__device_stub__multMatrixPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10multMatrixPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__multMatrixPfS_S_i, .Lfunc_end2-_Z25__device_stub__multMatrixPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12testCudaMultv
.LCPI3_0:
.long 0x3a83126f # float 0.00100000005
.LCPI3_1:
.long 0x3ba3d70a # float 0.00499999989
.text
.globl _Z12testCudaMultv
.p2align 4, 0x90
.type _Z12testCudaMultv,@function
_Z12testCudaMultv: # @_Z12testCudaMultv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r12
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movaps %xmm0, %xmm1
mulss .LCPI3_0(%rip), %xmm1
movss %xmm1, (%r12,%rax,4)
mulss .LCPI3_1(%rip), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB3_1
# %bb.2:
xorl %r13d, %r13d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq %r12, %rax
.p2align 4, 0x90
.LBB3_3: # %.preheader80
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_5 Depth 3
movq %r13, %rcx
shlq $12, %rcx
addq %rbx, %rcx
movq %r15, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_4: # %.preheader
# Parent Loop BB3_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_5 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_3 Depth=1
# Parent Loop BB3_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $4096, %rdi # imm = 0x1000
cmpq $1024, %r8 # imm = 0x400
jne .LBB3_5
# %bb.6: # in Loop: Header=BB3_4 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB3_4
# %bb.7: # in Loop: Header=BB3_3 Depth=1
incq %r13
addq $4096, %rax # imm = 0x1000
cmpq $1024, %r13 # imm = 0x400
jne .LBB3_3
# %bb.8:
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r14
movq %rdx, %rax
shrq $63, %rax
sarq $7, %r14
addq %rax, %r14
xorl %ebp, %ebp
movl $.L.str.2, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r13
movl $4194304, %edx # imm = 0x400000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movss .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_9: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
movaps %xmm0, %xmm1
mulss %xmm2, %xmm1
movss %xmm1, (%r12,%rbp,4)
mulss %xmm3, %xmm0
movss %xmm0, (%r15,%rbp,4)
incq %rbp
cmpq $1048576, %rbp # imm = 0x100000
jne .LBB3_9
# %bb.10:
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
xorl %r12d, %r12d
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_12
# %bb.11:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10multMatrixPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_12:
callq hipDeviceSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbp
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_13: # =>This Inner Loop Header: Depth=1
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpneqss (%rbx,%rax,4), %xmm0
movd %xmm0, %ecx
subl %ecx, %r12d
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB3_13
# %bb.14:
testl %r12d, %r12d
je .LBB3_16
# %bb.15:
movl $.L.str.3, %edi
movl %r12d, %esi
movl $1048576, %edx # imm = 0x100000
xorl %eax, %eax
callq printf
.LBB3_16:
subq %r15, %rbp
movq %rbp, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rbx
movq %rdx, %rax
shrq $63, %rax
sarq $7, %rbx
addq %rax, %rbx
movl $.L.str.4, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
cvtsi2sd %rbx, %xmm1
divsd %xmm1, %xmm0
movl $.L.str.5, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12testCudaMultv, .Lfunc_end3-_Z12testCudaMultv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
callq _Z11testCudaAddv
callq _Z12testCudaMultv
callq hipDeviceReset
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10multMatrixPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiS_S_,@object # @_Z9addKernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiS_S_
.p2align 3, 0x0
_Z9addKernelPiS_S_:
.quad _Z24__device_stub__addKernelPiS_S_
.size _Z9addKernelPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type _Z10multMatrixPfS_S_i,@object # @_Z10multMatrixPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10multMatrixPfS_S_i
.p2align 3, 0x0
_Z10multMatrixPfS_S_i:
.quad _Z25__device_stub__multMatrixPfS_S_i
.size _Z10multMatrixPfS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "CPU: %d (us)\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "mismatchCount= %d (%d)\n"
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU: %d (us)\n"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "rate = %.4f (%dx%d matrix)\n"
.size .L.str.5, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiS_S_"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10multMatrixPfS_S_i"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello,CUDA"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiS_S_
.addrsig_sym _Z25__device_stub__multMatrixPfS_S_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiS_S_
.addrsig_sym _Z10multMatrixPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ unsigned int concatenate(float* array)
{
unsigned int rvalue=0;
unsigned int sign;
for (int i = 0; i < 32; i++)
{
sign = (array[i]>=0);
rvalue = rvalue | (sign<<i);
}
return rvalue;
}
__global__ void concatenate_cols_kernel(float *a, unsigned int *b, int m, int n)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
if(j<n){
float * array = new float[32];
for(int i=0; i<m; i+=32){
for(int k=0; k<32;k++) array[k] = a[j + n*(i+k)];
b[j+n*i/32]=concatenate(array);
}
delete[] array;
}
} | code for sm_80
Function : _Z23concatenate_cols_kernelPfPjii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R16, SR_CTAID.X ; /* 0x0000000000107919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R16, R16, c[0x0][0x0], R3 ; /* 0x0000000010107a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R16, c[0x0][0x174], PT ; /* 0x00005d0010007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, 0x80 ; /* 0x00000080ff047424 */
/* 0x000fe400078e00ff */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0090*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*00a0*/ LEPC R6 ; /* 0x000000000006734e */
/* 0x000fe20000000000 */
/*00b0*/ MOV R9, 0x120 ; /* 0x0000012000097802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R9, R6 ; /* 0x0000000914147210 */
/* 0x000fc8000791e106 */
/*0100*/ IADD3.X R21, ~R0, R21, R7, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2507 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0120*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fca00078e00ff */
/*0140*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e220000000a00 */
/*0150*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0160*/ @!P0 BRA 0xd90 ; /* 0x00000c2000008947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0180*/ BSSY B0, 0xd90 ; /* 0x00000c0000007945 */
/* 0x000fe20003800000 */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.WIDE R24, R16, R7, c[0x0][0x160] ; /* 0x0000580010187625 */
/* 0x000fc800078e0207 */
/*01c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*01d0*/ LDG.E R17, [R24.64] ; /* 0x0000000418117981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IMAD.WIDE R8, R7, c[0x0][0x174], R24 ; /* 0x00005d0007087a25 */
/* 0x002fc600078e0218 */
/*01f0*/ ST.E [R4.64], R17 ; /* 0x0000001104007985 */
/* 0x0043e8000c101904 */
/*0200*/ LDG.E R15, [R8.64] ; /* 0x00000004080f7981 */
/* 0x000ea2000c1e1900 */
/*0210*/ IMAD.WIDE R12, R7, c[0x0][0x174], R8 ; /* 0x00005d00070c7a25 */
/* 0x000fc600078e0208 */
/*0220*/ ST.E [R4.64+0x4], R15 ; /* 0x0000040f04007985 */
/* 0x0045e8000c101904 */
/*0230*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ee2000c1e1900 */
/*0240*/ IMAD.WIDE R26, R7, c[0x0][0x174], R12 ; /* 0x00005d00071a7a25 */
/* 0x000fc600078e020c */
/*0250*/ ST.E [R4.64+0x8], R19 ; /* 0x0000081304007985 */
/* 0x008fe8000c101904 */
/*0260*/ LDG.E R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x000ee2000c1e1900 */
/*0270*/ IMAD.WIDE R28, R7, c[0x0][0x174], R26 ; /* 0x00005d00071c7a25 */
/* 0x000fc600078e021a */
/*0280*/ ST.E [R4.64+0xc], R10 ; /* 0x00000c0a04007985 */
/* 0x0087e8000c101904 */
/*0290*/ LDG.E R21, [R28.64] ; /* 0x000000041c157981 */
/* 0x000f22000c1e1900 */
/*02a0*/ IMAD.WIDE R26, R7, c[0x0][0x174], R28 ; /* 0x00005d00071a7a25 */
/* 0x000fc600078e021c */
/*02b0*/ ST.E [R4.64+0x10], R21 ; /* 0x0000101504007985 */
/* 0x0109e8000c101904 */
/*02c0*/ LDG.E R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x000f62000c1e1900 */
/*02d0*/ IMAD.WIDE R24, R7, c[0x0][0x174], R26 ; /* 0x00005d0007187a25 */
/* 0x000fc600078e021a */
/*02e0*/ ST.E [R4.64+0x14], R22 ; /* 0x0000141604007985 */
/* 0x020fe8000c101904 */
/*02f0*/ LDG.E R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000aa4000c1e1900 */
/*0300*/ IMAD.WIDE R24, R7.reuse, c[0x0][0x174], R24 ; /* 0x00005d0007187a25 */
/* 0x060fe400078e0218 */
/*0310*/ ST.E [R4.64+0x18], R8 ; /* 0x0000180804007985 */
/* 0x0045e8000c101904 */
/*0320*/ LDG.E R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000aa4000c1e1900 */
/*0330*/ IMAD.WIDE R24, R7, c[0x0][0x174], R24 ; /* 0x00005d0007187a25 */
/* 0x020fc400078e0218 */
/*0340*/ ST.E [R4.64+0x1c], R18 ; /* 0x00001c1204007985 */
/* 0x0045e8000c101904 */
/*0350*/ LDG.E R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R28, R7, c[0x0][0x174], R24 ; /* 0x00005d00071c7a25 */
/* 0x000fc600078e0218 */
/*0370*/ ST.E [R4.64+0x20], R12 ; /* 0x0000200c04007985 */
/* 0x020be8000c101904 */
/*0380*/ LDG.E R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x0000a4000c1e1900 */
/*0390*/ IMAD.WIDE R28, R7.reuse, c[0x0][0x174], R28 ; /* 0x00005d00071c7a25 */
/* 0x041fe400078e021c */
/*03a0*/ ST.E [R4.64+0x24], R14 ; /* 0x0000240e04007985 */
/* 0x0041e8000c101904 */
/*03b0*/ LDG.E R23, [R28.64] ; /* 0x000000041c177981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ IMAD.WIDE R26, R7, c[0x0][0x174], R28 ; /* 0x00005d00071a7a25 */
/* 0x000fc600078e021c */
/*03d0*/ ST.E [R4.64+0x28], R23 ; /* 0x0000281704007985 */
/* 0x0045e8000c101904 */
/*03e0*/ LDG.E R20, [R26.64] ; /* 0x000000041a147981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ IMAD.WIDE R24, R7, c[0x0][0x174], R26 ; /* 0x00005d0007187a25 */
/* 0x000fc600078e021a */
/*0400*/ ST.E [R4.64+0x2c], R20 ; /* 0x00002c1404007985 */
/* 0x0045e8000c101904 */
/*0410*/ LDG.E R27, [R24.64] ; /* 0x00000004181b7981 */
/* 0x0000a4000c1e1900 */
/*0420*/ IMAD.WIDE R24, R7.reuse, c[0x0][0x174], R24 ; /* 0x00005d0007187a25 */
/* 0x041fe400078e0218 */
/*0430*/ ST.E [R4.64+0x30], R27 ; /* 0x0000301b04007985 */
/* 0x0041e8000c101904 */
/*0440*/ LDG.E R9, [R24.64] ; /* 0x0000000418097981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R28, R7, c[0x0][0x174], R24 ; /* 0x00005d00071c7a25 */
/* 0x000fc600078e0218 */
/*0460*/ ST.E [R4.64+0x34], R9 ; /* 0x0000340904007985 */
/* 0x004fe8000c101904 */
/*0470*/ LDG.E R11, [R28.64] ; /* 0x000000041c0b7981 */
/* 0x0004e4000c1e1900 */
/*0480*/ IMAD.WIDE R28, R7.reuse, c[0x0][0x174], R28 ; /* 0x00005d00071c7a25 */
/* 0x044fe400078e021c */
/*0490*/ ST.E [R4.64+0x38], R11 ; /* 0x0000380b04007985 */
/* 0x0085e8000c101904 */
/*04a0*/ LDG.E R13, [R28.64] ; /* 0x000000041c0d7981 */
/* 0x000ee2000c1e1900 */
/*04b0*/ IMAD.WIDE R24, R7, c[0x0][0x174], R28 ; /* 0x00005d0007187a25 */
/* 0x000fe200078e021c */
/*04c0*/ FSETP.GE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720b */
/* 0x000fc40003f26000 */
/*04d0*/ FSETP.GE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720b */
/* 0x000fe40003f06000 */
/*04e0*/ SEL R17, RZ, 0xffffffff, !P1 ; /* 0xffffffffff117807 */
/* 0x002fe40004800000 */
/*04f0*/ FSETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fe20003f26000 */
/*0500*/ ST.E [R4.64+0x3c], R13 ; /* 0x00003c0d04007985 */
/* 0x0083e8000c101904 */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x000ee2000c1e1900 */
/*0520*/ IMAD.SHL.U32 R17, R17, 0x2, RZ ; /* 0x0000000211117824 */
/* 0x000fe200078e00ff */
/*0530*/ SEL R10, RZ, 0x1, !P0 ; /* 0x00000001ff0a7807 */
/* 0x000fe20004000000 */
/*0540*/ IMAD.WIDE R28, R7, c[0x0][0x174], R24 ; /* 0x00005d00071c7a25 */
/* 0x000fe200078e0218 */
/*0550*/ FSETP.GE.AND P2, PT, R19, RZ, PT ; /* 0x000000ff1300720b */
/* 0x000fc40003f46000 */
/*0560*/ LOP3.LUT R10, R17, 0x2, R10, 0xe2, !PT ; /* 0x00000002110a7812 */
/* 0x000fe400078ee20a */
/*0570*/ SEL R17, RZ, 0x4, !P2 ; /* 0x00000004ff117807 */
/* 0x000fe40005000000 */
/*0580*/ SEL R19, RZ, 0x8, !P1 ; /* 0x00000008ff137807 */
/* 0x000fc80004800000 */
/*0590*/ LOP3.LUT R10, R19, R17, R10, 0xfe, !PT ; /* 0x00000011130a7212 */
/* 0x000fe200078efe0a */
/*05a0*/ ST.E [R4.64+0x40], R15 ; /* 0x0000400f04007985 */
/* 0x008fe8000c101904 */
/*05b0*/ LDG.E R17, [R28.64] ; /* 0x000000041c117981 */
/* 0x000ee2000c1e1900 */
/*05c0*/ IMAD.WIDE R24, R7, c[0x0][0x174], R28 ; /* 0x00005d0007187a25 */
/* 0x000fc600078e021c */
/*05d0*/ ST.E [R4.64+0x44], R17 ; /* 0x0000441104007985 */
/* 0x0087e8000c101904 */
/*05e0*/ LDG.E R19, [R24.64] ; /* 0x0000000418137981 */
/* 0x000ea2000c1e1900 */
/*05f0*/ IMAD.WIDE R28, R7, c[0x0][0x174], R24 ; /* 0x00005d00071c7a25 */
/* 0x000fe200078e0218 */
/*0600*/ FSETP.GE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720b */
/* 0x000fe40003f06000 */
/*0610*/ ST.E [R4.64+0x48], R19 ; /* 0x0000481304007985 */
/* 0x004fe8000c101904 */
/*0620*/ LDG.E R21, [R28.64] ; /* 0x000000041c157981 */
/* 0x010ea2000c1e1900 */
/*0630*/ IMAD.WIDE R24, R7, c[0x0][0x174], R28 ; /* 0x00005d0007187a25 */
/* 0x000fe200078e021c */
/*0640*/ FSETP.GE.AND P1, PT, R22, RZ, PT ; /* 0x000000ff1600720b */
/* 0x000fc40003f26000 */
/*0650*/ FSETP.GE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fe40003f46000 */
/*0660*/ FSETP.GE.AND P3, PT, R18, RZ, PT ; /* 0x000000ff1200720b */
/* 0x000fe40003f66000 */
/*0670*/ SEL R8, RZ, 0x10, !P0 ; /* 0x00000010ff087807 */
/* 0x000fe20004000000 */
/*0680*/ ST.E [R4.64+0x4c], R21 ; /* 0x00004c1504007985 */
/* 0x004fe8000c101904 */
/*0690*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000522000c1e1900 */
/*06a0*/ SEL R18, RZ, 0x20, !P1 ; /* 0x00000020ff127807 */
/* 0x000fc80004800000 */
/*06b0*/ LOP3.LUT R18, R18, R8, R10, 0xfe, !PT ; /* 0x0000000812127212 */
/* 0x000fe400078efe0a */
/*06c0*/ SEL R8, RZ, 0x40, !P2 ; /* 0x00000040ff087807 */
/* 0x000fe40005000000 */
/*06d0*/ SEL R10, RZ, 0x80, !P3 ; /* 0x00000080ff0a7807 */
/* 0x000fe20005800000 */
/*06e0*/ IMAD.WIDE R24, R7, c[0x0][0x174], R24 ; /* 0x00005d0007187a25 */
/* 0x004fc600078e0218 */
/*06f0*/ LOP3.LUT R18, R10, R8, R18, 0xfe, !PT ; /* 0x000000080a127212 */
/* 0x000fe200078efe12 */
/*0700*/ ST.E [R4.64+0x50], R29 ; /* 0x0000501d04007985 */
/* 0x010fe8000c101904 */
/*0710*/ LDG.E R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000524000c1e1900 */
/*0720*/ IMAD.WIDE R24, R7.reuse, c[0x0][0x174], R24 ; /* 0x00005d0007187a25 */
/* 0x044fe400078e0218 */
/*0730*/ ST.E [R4.64+0x54], R8 ; /* 0x0000540804007985 */
/* 0x0105e8000c101904 */
/*0740*/ LDG.E R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x0008a2000c1e1900 */
/*0750*/ FSETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720b */
/* 0x000fe20003f06000 */
/*0760*/ IMAD.WIDE R24, R7, c[0x0][0x174], R24 ; /* 0x00005d0007187a25 */
/* 0x010fc400078e0218 */
/*0770*/ ST.E [R4.64+0x58], R10 ; /* 0x0000580a04007985 */
/* 0x0045e8000c101904 */
/*0780*/ LDG.E R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x020962000c1e1900 */
/*0790*/ FSETP.GE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720b */
/* 0x000fe20003f26000 */
/*07a0*/ IMAD.WIDE R24, R7, c[0x0][0x174], R24 ; /* 0x00005d0007187a25 */
/* 0x010fe400078e0218 */
/*07b0*/ ST.E [R4.64+0x5c], R12 ; /* 0x00005c0c04007985 */
/* 0x020fe8000c101904 */
/*07c0*/ LDG.E R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000f22000c1e1900 */
/*07d0*/ FSETP.GE.AND P2, PT, R23, RZ, PT ; /* 0x000000ff1700720b */
/* 0x000fc40003f46000 */
/*07e0*/ FSETP.GE.AND P3, PT, R20, RZ, PT ; /* 0x000000ff1400720b */
/* 0x000fe40003f66000 */
/*07f0*/ SEL R23, RZ, 0x100, !P0 ; /* 0x00000100ff177807 */
/* 0x000fe40004000000 */
/*0800*/ SEL R20, RZ, 0x200, !P1 ; /* 0x00000200ff147807 */
/* 0x000fe40004800000 */
/*0810*/ SEL R26, RZ, 0x800, !P3 ; /* 0x00000800ff1a7807 */
/* 0x000fe40005800000 */
/*0820*/ LOP3.LUT R18, R20, R23, R18, 0xfe, !PT ; /* 0x0000001714127212 */
/* 0x000fe200078efe12 */
/*0830*/ IMAD.WIDE R22, R7, c[0x0][0x174], R24 ; /* 0x00005d0007167a25 */
/* 0x000fe200078e0218 */
/*0840*/ SEL R20, RZ, 0x400, !P2 ; /* 0x00000400ff147807 */
/* 0x000fc80005000000 */
/*0850*/ LOP3.LUT R18, R26, R20, R18, 0xfe, !PT ; /* 0x000000141a127212 */
/* 0x000fe200078efe12 */
/*0860*/ ST.E [R4.64+0x60], R14 ; /* 0x0000600e04007985 */
/* 0x010fe8000c101904 */
/*0870*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000964000c1e1900 */
/*0880*/ IMAD.WIDE R22, R7.reuse, c[0x0][0x174], R22 ; /* 0x00005d0007167a25 */
/* 0x050fe400078e0216 */
/*0890*/ ST.E [R4.64+0x64], R20 ; /* 0x0000641404007985 */
/* 0x020fe8000c101904 */
/*08a0*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x000f22000c1e1900 */
/*08b0*/ IMAD.WIDE R24, R7, c[0x0][0x174], R22 ; /* 0x00005d0007187a25 */
/* 0x000fe200078e0216 */
/*08c0*/ FSETP.GE.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720b */
/* 0x000fc40003f06000 */
/*08d0*/ ST.E [R4.64+0x68], R28 ; /* 0x0000681c04007985 */
/* 0x010fe8000c101904 */
/*08e0*/ LDG.E R23, [R24.64] ; /* 0x0000000418177981 */
/* 0x000f22000c1e1900 */
/*08f0*/ IMAD.WIDE R26, R7, c[0x0][0x174], R24 ; /* 0x00005d00071a7a25 */
/* 0x001fe200078e0218 */
/*0900*/ FSETP.GE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fe40003f26000 */
/*0910*/ FSETP.GE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x000fe40003f46000 */
/*0920*/ FSETP.GE.AND P3, PT, R13, RZ, PT ; /* 0x000000ff0d00720b */
/* 0x000fc40003f66000 */
/*0930*/ SEL R11, RZ, 0x1000, !P0 ; /* 0x00001000ff0b7807 */
/* 0x000fe20004000000 */
/*0940*/ ST.E [R4.64+0x6c], R23 ; /* 0x00006c1704007985 */
/* 0x010fe8000c101904 */
/*0950*/ LDG.E R9, [R26.64] ; /* 0x000000041a097981 */
/* 0x000122000c1e1900 */
/*0960*/ SEL R13, RZ, 0x2000, !P1 ; /* 0x00002000ff0d7807 */
/* 0x002fc80004800000 */
/*0970*/ LOP3.LUT R13, R13, R11, R18, 0xfe, !PT ; /* 0x0000000b0d0d7212 */
/* 0x000fe400078efe12 */
/*0980*/ SEL R11, RZ, 0x8000, !P3 ; /* 0x00008000ff0b7807 */
/* 0x000fe40005800000 */
/*0990*/ SEL R18, RZ, 0x4000, !P2 ; /* 0x00004000ff127807 */
/* 0x000fe20005000000 */
/*09a0*/ IMAD.WIDE R26, R7, c[0x0][0x174], R26 ; /* 0x00005d00071a7a25 */
/* 0x001fc600078e021a */
/*09b0*/ LOP3.LUT R13, R11, R18, R13, 0xfe, !PT ; /* 0x000000120b0d7212 */
/* 0x000fe200078efe0d */
/*09c0*/ ST.E [R4.64+0x70], R9 ; /* 0x0000700904007985 */
/* 0x010fe8000c101904 */
/*09d0*/ LDG.E R11, [R26.64] ; /* 0x000000041a0b7981 */
/* 0x000124000c1e1900 */
/*09e0*/ IMAD.WIDE R26, R7.reuse, c[0x0][0x174], R26 ; /* 0x00005d00071a7a25 */
/* 0x041fe400078e021a */
/*09f0*/ ST.E [R4.64+0x74], R11 ; /* 0x0000740b04007985 */
/* 0x0101e8000c101904 */
/*0a00*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000f22000c1e1900 */
/*0a10*/ IMAD.WIDE R24, R7, c[0x0][0x174], R26 ; /* 0x00005d0007187a25 */
/* 0x000fe200078e021a */
/*0a20*/ FSETP.GE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00720b */
/* 0x000fc40003f46000 */
/*0a30*/ FSETP.GE.AND P3, PT, R17, RZ, PT ; /* 0x000000ff1100720b */
/* 0x000fe40003f66000 */
/*0a40*/ SEL R22, RZ, 0x10000, !P2 ; /* 0x00010000ff167807 */
/* 0x000fe40005000000 */
/*0a50*/ SEL R17, RZ, 0x20000, !P3 ; /* 0x00020000ff117807 */
/* 0x008fe40005800000 */
/*0a60*/ FSETP.GE.AND P1, PT, R19, RZ, PT ; /* 0x000000ff1300720b */
/* 0x000fe40003f26000 */
/*0a70*/ FSETP.GE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720b */
/* 0x000fe40003f06000 */
/*0a80*/ LOP3.LUT R13, R17, R22, R13, 0xfe, !PT ; /* 0x00000016110d7212 */
/* 0x000fc400078efe0d */
/*0a90*/ SEL R22, RZ, 0x40000, !P1 ; /* 0x00040000ff167807 */
/* 0x000fe40004800000 */
/*0aa0*/ SEL R17, RZ, 0x80000, !P0 ; /* 0x00080000ff117807 */
/* 0x000fe40004000000 */
/*0ab0*/ FSETP.GE.AND P2, PT, R29, RZ, PT ; /* 0x000000ff1d00720b */
/* 0x000fe40003f46000 */
/*0ac0*/ FSETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fe40003f06000 */
/*0ad0*/ LOP3.LUT R13, R17, R22, R13, 0xfe, !PT ; /* 0x00000016110d7212 */
/* 0x000fe200078efe0d */
/*0ae0*/ ST.E [R4.64+0x78], R18 ; /* 0x0000781204007985 */
/* 0x0103e8000c101904 */
/*0af0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x000722000c1e1900 */
/*0b00*/ SEL R8, RZ, 0x100000, !P2 ; /* 0x00100000ff087807 */
/* 0x000fc40005000000 */
/*0b10*/ SEL R17, RZ, 0x200000, !P0 ; /* 0x00200000ff117807 */
/* 0x000fe40004000000 */
/*0b20*/ FSETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fe40003f06000 */
/*0b30*/ FSETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720b */
/* 0x000fe40003f26000 */
/*0b40*/ LOP3.LUT R8, R17, R8, R13, 0xfe, !PT ; /* 0x0000000811087212 */
/* 0x000fe200078efe0d */
/*0b50*/ IMAD.WIDE R24, R7, c[0x0][0x174], R24 ; /* 0x00005d0007187a25 */
/* 0x008fe200078e0218 */
/*0b60*/ SEL R13, RZ, 0x400000, !P0 ; /* 0x00400000ff0d7807 */
/* 0x000fe40004000000 */
/*0b70*/ SEL R10, RZ, 0x800000, !P1 ; /* 0x00800000ff0a7807 */
/* 0x004fc40004800000 */
/*0b80*/ FSETP.GE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720b */
/* 0x000fe40003f06000 */
/*0b90*/ FSETP.GE.AND P1, PT, R20, RZ, PT ; /* 0x000000ff1400720b */
/* 0x000fe40003f26000 */
/*0ba0*/ LOP3.LUT R8, R10, R13, R8, 0xfe, !PT ; /* 0x0000000d0a087212 */
/* 0x000fe400078efe08 */
/*0bb0*/ SEL R13, RZ, 0x1000000, !P0 ; /* 0x01000000ff0d7807 */
/* 0x000fe40004000000 */
/*0bc0*/ SEL R10, RZ, 0x2000000, !P1 ; /* 0x02000000ff0a7807 */
/* 0x000fe40004800000 */
/*0bd0*/ FSETP.GE.AND P0, PT, R28, RZ, PT ; /* 0x000000ff1c00720b */
/* 0x000fc40003f06000 */
/*0be0*/ FSETP.GE.AND P1, PT, R23, RZ, PT ; /* 0x000000ff1700720b */
/* 0x000fe40003f26000 */
/*0bf0*/ LOP3.LUT R8, R10, R13, R8, 0xfe, !PT ; /* 0x0000000d0a087212 */
/* 0x000fe400078efe08 */
/*0c00*/ SEL R13, RZ, 0x4000000, !P0 ; /* 0x04000000ff0d7807 */
/* 0x000fe40004000000 */
/*0c10*/ SEL R10, RZ, 0x8000000, !P1 ; /* 0x08000000ff0a7807 */
/* 0x000fe40004800000 */
/*0c20*/ FSETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fe40003f06000 */
/*0c30*/ FSETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x000fc40003f26000 */
/*0c40*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x001fe40000011400 */
/*0c50*/ LOP3.LUT R8, R10, R13, R8, 0xfe, !PT ; /* 0x0000000d0a087212 */
/* 0x000fe200078efe08 */
/*0c60*/ IMAD.MOV.U32 R13, RZ, RZ, 0x20 ; /* 0x00000020ff0d7424 */
/* 0x000fe200078e00ff */
/*0c70*/ SEL R9, RZ, 0x10000000, !P0 ; /* 0x10000000ff097807 */
/* 0x000fe40004000000 */
/*0c80*/ SEL R10, RZ, 0x20000000, !P1 ; /* 0x20000000ff0a7807 */
/* 0x000fe40004800000 */
/*0c90*/ LEA.HI R11, R11, R0, RZ, 0x5 ; /* 0x000000000b0b7211 */
/* 0x000fe200078f28ff */
/*0ca0*/ IMAD R0, R13, c[0x0][0x174], R0 ; /* 0x00005d000d007a24 */
/* 0x000fe200078e0200 */
/*0cb0*/ FSETP.GE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720b */
/* 0x000fc40003f06000 */
/*0cc0*/ IADD3 R6, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x000fe40007ffe0ff */
/*0cd0*/ LOP3.LUT R10, R10, R9, R8, 0xfe, !PT ; /* 0x000000090a0a7212 */
/* 0x000fe400078efe08 */
/*0ce0*/ LEA.HI.SX32 R8, R11, R16, 0x1b ; /* 0x000000100b087211 */
/* 0x000fe400078fdaff */
/*0cf0*/ SEL R11, RZ, 0x40000000, !P0 ; /* 0x40000000ff0b7807 */
/* 0x000fe40004000000 */
/*0d00*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe20003f06270 */
/*0d10*/ IMAD.WIDE R8, R8, R7, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe200078e0207 */
/*0d20*/ FSETP.GE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720b */
/* 0x010fe20003f26000 */
/*0d30*/ ST.E [R4.64+0x7c], R15 ; /* 0x00007c0f04007985 */
/* 0x0003e6000c101904 */
/*0d40*/ SEL R12, RZ, 0x80000000, !P1 ; /* 0x80000000ff0c7807 */
/* 0x000fc80004800000 */
/*0d50*/ LOP3.LUT R11, R12, R11, R10, 0xfe, !PT ; /* 0x0000000b0c0b7212 */
/* 0x000fca00078efe0a */
/*0d60*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0003e2000c101904 */
/*0d70*/ @!P0 BRA 0x1c0 ; /* 0xfffff44000008947 */
/* 0x000fea000383ffff */
/*0d80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d90*/ LEPC R6 ; /* 0x000000000006734e */
/* 0x000fe20000000000 */
/*0da0*/ MOV R9, 0xe10 ; /* 0x00000e1000097802 */
/* 0x002fe40000000f00 */
/*0db0*/ MOV R20, 0xd90 ; /* 0x00000d9000147802 */
/* 0x000fe40000000f00 */
/*0dc0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0dd0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0de0*/ IADD3 R20, P0, P1, -R20, R9, R6 ; /* 0x0000000914147210 */
/* 0x000fc8000791e106 */
/*0df0*/ IADD3.X R21, ~R0, R21, R7, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2507 */
/*0e00*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0e10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ unsigned int concatenate(float* array)
{
unsigned int rvalue=0;
unsigned int sign;
for (int i = 0; i < 32; i++)
{
sign = (array[i]>=0);
rvalue = rvalue | (sign<<i);
}
return rvalue;
}
__global__ void concatenate_cols_kernel(float *a, unsigned int *b, int m, int n)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
if(j<n){
float * array = new float[32];
for(int i=0; i<m; i+=32){
for(int k=0; k<32;k++) array[k] = a[j + n*(i+k)];
b[j+n*i/32]=concatenate(array);
}
delete[] array;
}
} | .file "tmpxft_0000270f_00000000-6_concatenate_cols_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11concatenatePf
.type _Z11concatenatePf, @function
_Z11concatenatePf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z11concatenatePf, .-_Z11concatenatePf
.globl _Z47__device_stub__Z23concatenate_cols_kernelPfPjiiPfPjii
.type _Z47__device_stub__Z23concatenate_cols_kernelPfPjiiPfPjii, @function
_Z47__device_stub__Z23concatenate_cols_kernelPfPjiiPfPjii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23concatenate_cols_kernelPfPjii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z47__device_stub__Z23concatenate_cols_kernelPfPjiiPfPjii, .-_Z47__device_stub__Z23concatenate_cols_kernelPfPjiiPfPjii
.globl _Z23concatenate_cols_kernelPfPjii
.type _Z23concatenate_cols_kernelPfPjii, @function
_Z23concatenate_cols_kernelPfPjii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23concatenate_cols_kernelPfPjiiPfPjii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z23concatenate_cols_kernelPfPjii, .-_Z23concatenate_cols_kernelPfPjii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23concatenate_cols_kernelPfPjii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23concatenate_cols_kernelPfPjii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ unsigned int concatenate(float* array)
{
unsigned int rvalue=0;
unsigned int sign;
for (int i = 0; i < 32; i++)
{
sign = (array[i]>=0);
rvalue = rvalue | (sign<<i);
}
return rvalue;
}
__global__ void concatenate_cols_kernel(float *a, unsigned int *b, int m, int n)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
if(j<n){
float * array = new float[32];
for(int i=0; i<m; i+=32){
for(int k=0; k<32;k++) array[k] = a[j + n*(i+k)];
b[j+n*i/32]=concatenate(array);
}
delete[] array;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int concatenate(float* array)
{
unsigned int rvalue=0;
unsigned int sign;
for (int i = 0; i < 32; i++)
{
sign = (array[i]>=0);
rvalue = rvalue | (sign<<i);
}
return rvalue;
}
__global__ void concatenate_cols_kernel(float *a, unsigned int *b, int m, int n)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
if(j<n){
float * array = new float[32];
for(int i=0; i<m; i+=32){
for(int k=0; k<32;k++) array[k] = a[j + n*(i+k)];
b[j+n*i/32]=concatenate(array);
}
delete[] array;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int concatenate(float* array)
{
unsigned int rvalue=0;
unsigned int sign;
for (int i = 0; i < 32; i++)
{
sign = (array[i]>=0);
rvalue = rvalue | (sign<<i);
}
return rvalue;
}
__global__ void concatenate_cols_kernel(float *a, unsigned int *b, int m, int n)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
if(j<n){
float * array = new float[32];
for(int i=0; i<m; i+=32){
for(int k=0; k<32;k++) array[k] = a[j + n*(i+k)];
b[j+n*i/32]=concatenate(array);
}
delete[] array;
}
} | .text
.file "concatenate_cols_kernel.hip"
.globl _Z38__device_stub__concatenate_cols_kernelPfPjii # -- Begin function _Z38__device_stub__concatenate_cols_kernelPfPjii
.p2align 4, 0x90
.type _Z38__device_stub__concatenate_cols_kernelPfPjii,@function
_Z38__device_stub__concatenate_cols_kernelPfPjii: # @_Z38__device_stub__concatenate_cols_kernelPfPjii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23concatenate_cols_kernelPfPjii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__concatenate_cols_kernelPfPjii, .Lfunc_end0-_Z38__device_stub__concatenate_cols_kernelPfPjii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23concatenate_cols_kernelPfPjii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23concatenate_cols_kernelPfPjii,@object # @_Z23concatenate_cols_kernelPfPjii
.section .rodata,"a",@progbits
.globl _Z23concatenate_cols_kernelPfPjii
.p2align 3, 0x0
_Z23concatenate_cols_kernelPfPjii:
.quad _Z38__device_stub__concatenate_cols_kernelPfPjii
.size _Z23concatenate_cols_kernelPfPjii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23concatenate_cols_kernelPfPjii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__concatenate_cols_kernelPfPjii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23concatenate_cols_kernelPfPjii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000270f_00000000-6_concatenate_cols_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11concatenatePf
.type _Z11concatenatePf, @function
_Z11concatenatePf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z11concatenatePf, .-_Z11concatenatePf
.globl _Z47__device_stub__Z23concatenate_cols_kernelPfPjiiPfPjii
.type _Z47__device_stub__Z23concatenate_cols_kernelPfPjiiPfPjii, @function
_Z47__device_stub__Z23concatenate_cols_kernelPfPjiiPfPjii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23concatenate_cols_kernelPfPjii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z47__device_stub__Z23concatenate_cols_kernelPfPjiiPfPjii, .-_Z47__device_stub__Z23concatenate_cols_kernelPfPjiiPfPjii
.globl _Z23concatenate_cols_kernelPfPjii
.type _Z23concatenate_cols_kernelPfPjii, @function
_Z23concatenate_cols_kernelPfPjii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23concatenate_cols_kernelPfPjiiPfPjii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z23concatenate_cols_kernelPfPjii, .-_Z23concatenate_cols_kernelPfPjii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23concatenate_cols_kernelPfPjii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23concatenate_cols_kernelPfPjii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "concatenate_cols_kernel.hip"
.globl _Z38__device_stub__concatenate_cols_kernelPfPjii # -- Begin function _Z38__device_stub__concatenate_cols_kernelPfPjii
.p2align 4, 0x90
.type _Z38__device_stub__concatenate_cols_kernelPfPjii,@function
_Z38__device_stub__concatenate_cols_kernelPfPjii: # @_Z38__device_stub__concatenate_cols_kernelPfPjii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23concatenate_cols_kernelPfPjii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__concatenate_cols_kernelPfPjii, .Lfunc_end0-_Z38__device_stub__concatenate_cols_kernelPfPjii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23concatenate_cols_kernelPfPjii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23concatenate_cols_kernelPfPjii,@object # @_Z23concatenate_cols_kernelPfPjii
.section .rodata,"a",@progbits
.globl _Z23concatenate_cols_kernelPfPjii
.p2align 3, 0x0
_Z23concatenate_cols_kernelPfPjii:
.quad _Z38__device_stub__concatenate_cols_kernelPfPjii
.size _Z23concatenate_cols_kernelPfPjii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23concatenate_cols_kernelPfPjii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__concatenate_cols_kernelPfPjii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23concatenate_cols_kernelPfPjii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void smooth(float * v_new, const float * v) {
int myIdx = threadIdx.x * gridDim.x + blockIdx.x;
int numThreads = blockDim.x * gridDim.x;
int myLeftIdx = (myIdx == 0) ? 0 : myIdx - 1;
int myRightIdx = (myIdx == (numThreads - 1)) ? numThreads - 1 : myIdx + 1;
float myElt = v[myIdx];
float myLeftElt = v[myLeftIdx];
float myRightElt = v[myRightIdx];
v_new[myIdx] = 0.25f * myLeftElt + 0.5f * myElt + 0.25f * myRightElt;
} | code for sm_80
Function : _Z6smoothPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0040*/ MOV R0, c[0x0][0xc] ; /* 0x0000030000007a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ IMAD R7, R7, R0, -0x1 ; /* 0xffffffff07077424 */
/* 0x000fe400078e0200 */
/*0080*/ IMAD R8, R8, c[0x0][0xc], R3 ; /* 0x0000030008087a24 */
/* 0x001fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R13, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x040fe200078e020d */
/*00a0*/ ISETP.NE.AND P1, PT, R8.reuse, R7, PT ; /* 0x000000070800720c */
/* 0x040fe40003f25270 */
/*00b0*/ ISETP.NE.AND P0, PT, R8.reuse, RZ, PT ; /* 0x000000ff0800720c */
/* 0x040fe40003f05270 */
/*00c0*/ IADD3 R0, R8, -0x1, RZ ; /* 0xffffffff08007810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea6000c1e1900 */
/*00e0*/ SEL R0, R0, RZ, P0 ; /* 0x000000ff00007207 */
/* 0x000fca0000000000 */
/*00f0*/ IMAD.WIDE R4, R0, R13, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e020d */
/*0100*/ @P1 IADD3 R7, R8, 0x1, RZ ; /* 0x0000000108071810 */
/* 0x000fca0007ffe0ff */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R7, R13, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fcc00078e020d */
/*0130*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*0140*/ FMUL R9, R4, 0.25 ; /* 0x3e80000004097820 */
/* 0x008fc80000400000 */
/*0150*/ FFMA R11, R2, 0.5, R9 ; /* 0x3f000000020b7823 */
/* 0x004fe40000000009 */
/*0160*/ IMAD.WIDE R8, R8, R13, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e020d */
/*0170*/ FFMA R11, R6, 0.25, R11 ; /* 0x3e800000060b7823 */
/* 0x010fca000000000b */
/*0180*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void smooth(float * v_new, const float * v) {
int myIdx = threadIdx.x * gridDim.x + blockIdx.x;
int numThreads = blockDim.x * gridDim.x;
int myLeftIdx = (myIdx == 0) ? 0 : myIdx - 1;
int myRightIdx = (myIdx == (numThreads - 1)) ? numThreads - 1 : myIdx + 1;
float myElt = v[myIdx];
float myLeftElt = v[myLeftIdx];
float myRightElt = v[myRightIdx];
v_new[myIdx] = 0.25f * myLeftElt + 0.5f * myElt + 0.25f * myRightElt;
} | .file "tmpxft_00199e9e_00000000-6_smooth.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6smoothPfPKfPfPKf
.type _Z28__device_stub__Z6smoothPfPKfPfPKf, @function
_Z28__device_stub__Z6smoothPfPKfPfPKf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6smoothPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z6smoothPfPKfPfPKf, .-_Z28__device_stub__Z6smoothPfPKfPfPKf
.globl _Z6smoothPfPKf
.type _Z6smoothPfPKf, @function
_Z6smoothPfPKf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6smoothPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6smoothPfPKf, .-_Z6smoothPfPKf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6smoothPfPKf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6smoothPfPKf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void smooth(float * v_new, const float * v) {
int myIdx = threadIdx.x * gridDim.x + blockIdx.x;
int numThreads = blockDim.x * gridDim.x;
int myLeftIdx = (myIdx == 0) ? 0 : myIdx - 1;
int myRightIdx = (myIdx == (numThreads - 1)) ? numThreads - 1 : myIdx + 1;
float myElt = v[myIdx];
float myLeftElt = v[myLeftIdx];
float myRightElt = v[myRightIdx];
v_new[myIdx] = 0.25f * myLeftElt + 0.5f * myElt + 0.25f * myRightElt;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void smooth(float * v_new, const float * v) {
int myIdx = threadIdx.x * gridDim.x + blockIdx.x;
int numThreads = blockDim.x * gridDim.x;
int myLeftIdx = (myIdx == 0) ? 0 : myIdx - 1;
int myRightIdx = (myIdx == (numThreads - 1)) ? numThreads - 1 : myIdx + 1;
float myElt = v[myIdx];
float myLeftElt = v[myLeftIdx];
float myRightElt = v[myRightIdx];
v_new[myIdx] = 0.25f * myLeftElt + 0.5f * myElt + 0.25f * myRightElt;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void smooth(float * v_new, const float * v) {
int myIdx = threadIdx.x * gridDim.x + blockIdx.x;
int numThreads = blockDim.x * gridDim.x;
int myLeftIdx = (myIdx == 0) ? 0 : myIdx - 1;
int myRightIdx = (myIdx == (numThreads - 1)) ? numThreads - 1 : myIdx + 1;
float myElt = v[myIdx];
float myLeftElt = v[myLeftIdx];
float myRightElt = v[myRightIdx];
v_new[myIdx] = 0.25f * myLeftElt + 0.5f * myElt + 0.25f * myRightElt;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6smoothPfPKf
.globl _Z6smoothPfPKf
.p2align 8
.type _Z6smoothPfPKf,@function
_Z6smoothPfPKf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x1c
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s4, v0, s[2:3]
s_load_b128 s[0:3], s[0:1], 0x0
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s4, s5
s_add_i32 s4, s4, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_sub_nc_u32_e64 v3, v1, 1 clamp
v_add_nc_u32_e32 v0, 1, v1
v_cmp_eq_u32_e32 vcc_lo, s4, v1
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v0, v0, s4, vcc_lo
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[7:8], off
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v2, 0x3e800000, v2
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, 0.5, v3
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, 0x3e800000, v0
v_add_co_u32 v0, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v6, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6smoothPfPKf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6smoothPfPKf, .Lfunc_end0-_Z6smoothPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6smoothPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6smoothPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void smooth(float * v_new, const float * v) {
int myIdx = threadIdx.x * gridDim.x + blockIdx.x;
int numThreads = blockDim.x * gridDim.x;
int myLeftIdx = (myIdx == 0) ? 0 : myIdx - 1;
int myRightIdx = (myIdx == (numThreads - 1)) ? numThreads - 1 : myIdx + 1;
float myElt = v[myIdx];
float myLeftElt = v[myLeftIdx];
float myRightElt = v[myRightIdx];
v_new[myIdx] = 0.25f * myLeftElt + 0.5f * myElt + 0.25f * myRightElt;
} | .text
.file "smooth.hip"
.globl _Z21__device_stub__smoothPfPKf # -- Begin function _Z21__device_stub__smoothPfPKf
.p2align 4, 0x90
.type _Z21__device_stub__smoothPfPKf,@function
_Z21__device_stub__smoothPfPKf: # @_Z21__device_stub__smoothPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6smoothPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__smoothPfPKf, .Lfunc_end0-_Z21__device_stub__smoothPfPKf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6smoothPfPKf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6smoothPfPKf,@object # @_Z6smoothPfPKf
.section .rodata,"a",@progbits
.globl _Z6smoothPfPKf
.p2align 3, 0x0
_Z6smoothPfPKf:
.quad _Z21__device_stub__smoothPfPKf
.size _Z6smoothPfPKf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6smoothPfPKf"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__smoothPfPKf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6smoothPfPKf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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