system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 9
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000d503_00000000-6_example1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[%d] -> %d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
leal 1(%rax), %edx
movl %edx, 96(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 144(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 48(%rsp,%rbx,4), %ecx
movl 144(%rsp,%rbx,4), %r9d
movl 96(%rsp,%rbx,4), %r8d
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "example1.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $240, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 192(%rsp,%rax,4)
leaq 1(%rax), %rcx
movl %ecx, 144(%rsp,%rax,4)
movq %rcx, %rax
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 192(%rsp,%rbx,4), %edx
movl 144(%rsp,%rbx,4), %ecx
movl 96(%rsp,%rbx,4), %r8d
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[%d] -> %d + %d = %d\n"
.size .L.str, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <sys/time.h>
#define N 512
#define TILE_WIDTH 16
__global__ void matrixMult (int *a, int *b, int *c, int width);
void matrixMultCPU (int a[N][N], int b[N][N], int c[N][N], int width);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_start = (double)(start.tv_sec + start.tv_usec/1000000.0);
d_end = (double)(end.tv_sec + end.tv_usec/1000000.0);
return (d_end - d_start);
}
int main()
{
int a[N][N], b[N][N], c[N][N], g[N][N];
timeval start, end;
int *dev_a, *dev_b, *dev_c;
int size = N * N * sizeof(int);
// initialize matrices a and b with appropriate values
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
a[i][j] = i*N + j;
b[i][j] = i + j;
}
}
// initialize a and b matrices here
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_b, size);
cudaMalloc((void **) &dev_c, size);
gettimeofday(&start, NULL);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid((int)ceil(N/dimBlock.x), (int)ceil(N/dimBlock.y));
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
cudaDeviceSynchronize();
cudaMemcpy(g, dev_c, size, cudaMemcpyDeviceToHost);
gettimeofday(&end, NULL);
printf("GPU Time for %i additions: %f\n", N, myDiffTime(start, end));
gettimeofday(&start, NULL);
matrixMultCPU(a, b, c, N);
gettimeofday(&end, NULL);
printf("CPU Time for %i additions: %f\n", N, myDiffTime(start, end));
cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c);
// print verification
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
if (c[i][j] != g[i][j])
{
printf("Results do not match! %i, %i, c=%i, g=%i\n", i, j, c[i][j], g[i][j]);
exit(1);
}
}
}
}
__global__ void matrixMult(int* A, int* B, int* C, int width)
{
int k, sum = 0;
int col = blockIdx.x*TILE_WIDTH + threadIdx.x;
int row = blockIdx.y*TILE_WIDTH + threadIdx.y;
if(col < width && row < width)
{
for (k = 0; k < width; k++)
sum += A[row * width + k] * B[k * width + col];
C[row * width + col] = sum;
}
}
void matrixMultCPU (int a[N][N], int b[N][N], int c[N][N], int width)
{
for (int i = 0; i < width; i++)
{
for (int j = 0; j < width; j++)
{
int sum = 0;
for (int k = 0; k < width; k++)
{
int m = a[i][k];
int n = b[k][j];
sum += m * n;
}
c[i][j] = sum;
}
}
} | code for sm_80
Function : _Z10matrixMultPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ LEA R5, R5, R2, 0x4 ; /* 0x0000000205057211 */
/* 0x001fc800078e20ff */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe40003f06270 */
/*0070*/ LEA R2, R0, R3, 0x4 ; /* 0x0000000300027211 */
/* 0x002fc800078e20ff */
/*0080*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x178], P0 ; /* 0x00005e0002007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc30 ; /* 0x00000b3000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R6, R4.reuse, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R8, -R7, c[0x0][0x178], RZ ; /* 0x00005e0007087a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R19, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff137435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R18, R2, R19, c[0x0][0x168] ; /* 0x00005a0002127625 */
/* 0x000fce00078e0213 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R5, 0x4, R12 ; /* 0x00000004050c7825 */
/* 0x000fc800078e020c */
/*0250*/ IMAD.WIDE R22, R4.reuse, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x040fe200078e0212 */
/*0260*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R11, [R12.64+0x4] ; /* 0x000004040c0b7981 */
/* 0x000ee8000c1e1900 */
/*0290*/ LDG.E R14, [R12.64+0x8] ; /* 0x000008040c0e7981 */
/* 0x000f22000c1e1900 */
/*02a0*/ IMAD.WIDE R22, R4, 0x4, R22 ; /* 0x0000000404167825 */
/* 0x002fc600078e0216 */
/*02b0*/ LDG.E R19, [R12.64+0x10] ; /* 0x000010040c137981 */
/* 0x001f68000c1e1900 */
/*02c0*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000122000c1e1900 */
/*02d0*/ IMAD.WIDE R16, R4, 0x4, R22 ; /* 0x0000000404107825 */
/* 0x000fc600078e0216 */
/*02e0*/ LDG.E R9, [R12.64+0x14] ; /* 0x000014040c097981 */
/* 0x000f66000c1e1900 */
/*02f0*/ IMAD.WIDE R26, R4.reuse, 0x4, R16 ; /* 0x00000004041a7825 */
/* 0x040fe400078e0210 */
/*0300*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000368000c1e1900 */
/*0310*/ IMAD.WIDE R28, R4.reuse, 0x4, R26 ; /* 0x00000004041c7825 */
/* 0x040fe200078e021a */
/*0320*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000968000c1e1900 */
/*0340*/ LDG.E R17, [R12.64+0xc] ; /* 0x00000c040c117981 */
/* 0x002f62000c1e1900 */
/*0350*/ IMAD.WIDE R22, R4, 0x4, R28 ; /* 0x0000000404167825 */
/* 0x001fc600078e021c */
/*0360*/ LDG.E R26, [R12.64+0x1c] ; /* 0x00001c040c1a7981 */
/* 0x000f62000c1e1900 */
/*0370*/ IMAD R25, R10, R25, R21 ; /* 0x000000190a197224 */
/* 0x004fc600078e0215 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x0000a8000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R22, R4, 0x4, R22 ; /* 0x0000000404167825 */
/* 0x001fc800078e0216 */
/*03b0*/ IMAD R27, R24, R11, R25 ; /* 0x0000000b181b7224 */
/* 0x008fe400078e0219 */
/*03c0*/ IMAD.WIDE R24, R4.reuse, 0x4, R22 ; /* 0x0000000404187825 */
/* 0x040fe200078e0216 */
/*03d0*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x0000e6000c1e1900 */
/*03e0*/ IMAD R29, R15, R14, R27 ; /* 0x0000000e0f1d7224 */
/* 0x010fe200078e021b */
/*03f0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x000328000c1e1900 */
/*0400*/ LDG.E R27, [R12.64+0x20] ; /* 0x000020040c1b7981 */
/* 0x000f22000c1e1900 */
/*0410*/ IMAD.WIDE R14, R4, 0x4, R24 ; /* 0x00000004040e7825 */
/* 0x000fc600078e0218 */
/*0420*/ LDG.E R25, [R12.64+0x28] ; /* 0x000028040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x020fe400078e021d */
/*0440*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fe400078e020e */
/*0450*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000364000c1e1900 */
/*0460*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x000fe400078e021d */
/*0470*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x000fe400078e0210 */
/*0480*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000364000c1e1900 */
/*0490*/ IMAD R20, R20, R9, R29 ; /* 0x0000000914147224 */
/* 0x000fc400078e021d */
/*04a0*/ LDG.E R9, [R12.64+0x24] ; /* 0x000024040c097981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD.WIDE R22, R4, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x001fc600078e0212 */
/*04c0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000768000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x002f68000c1e1900 */
/*04e0*/ LDG.E R29, [R22.64] ; /* 0x00000004161d7981 */
/* 0x000162000c1e1900 */
/*04f0*/ IMAD R10, R10, R21, R20 ; /* 0x000000150a0a7224 */
/* 0x004fe400078e0214 */
/*0500*/ IMAD.WIDE R20, R4, 0x4, R22 ; /* 0x0000000404147825 */
/* 0x000fc400078e0216 */
/*0510*/ LDG.E R22, [R12.64+0x38] ; /* 0x000038040c167981 */
/* 0x001ea8000c1e1900 */
/*0520*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x0008a2000c1e1900 */
/*0530*/ IMAD R18, R11, R26, R10 ; /* 0x0000001a0b127224 */
/* 0x008fc600078e020a */
/*0540*/ LDG.E R26, [R12.64+0x30] ; /* 0x000030040c1a7981 */
/* 0x000ee2000c1e1900 */
/*0550*/ IMAD.WIDE R10, R4, 0x4, R20 ; /* 0x00000004040a7825 */
/* 0x000fc800078e0214 */
/*0560*/ IMAD R20, R28, R27, R18 ; /* 0x0000001b1c147224 */
/* 0x010fe400078e0212 */
/*0570*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IMAD.WIDE R18, R4, 0x4, R10 ; /* 0x0000000404127825 */
/* 0x000fc600078e020a */
/*0590*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x000128000c1e1900 */
/*05a0*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000328000c1e1900 */
/*05b0*/ LDG.E R10, [R12.64+0x3c] ; /* 0x00003c040c0a7981 */
/* 0x001f22000c1e1900 */
/*05c0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*05d0*/ IMAD R9, R14, R9, R20 ; /* 0x000000090e097224 */
/* 0x020fc800078e0214 */
/*05e0*/ IMAD R9, R16, R25, R9 ; /* 0x0000001910097224 */
/* 0x000fe200078e0209 */
/*05f0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*0600*/ IMAD R9, R24, R15, R9 ; /* 0x0000000f18097224 */
/* 0x000fe200078e0209 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD.WIDE R18, R4, 0x4, R18 ; /* 0x0000000404127825 */
/* 0x002fc800078e0212 */
/*0650*/ IMAD R9, R29, R26, R9 ; /* 0x0000001a1d097224 */
/* 0x008fc800078e0209 */
/*0660*/ IMAD R9, R17, R28, R9 ; /* 0x0000001c11097224 */
/* 0x004fc800078e0209 */
/*0670*/ IMAD R9, R27, R22, R9 ; /* 0x000000161b097224 */
/* 0x010fc800078e0209 */
/*0680*/ IMAD R21, R23, R10, R9 ; /* 0x0000000a17157224 */
/* 0x000fe200078e0209 */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*06d0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x0000a2000c1e1900 */
/*06e0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*06f0*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fca00078e020a */
/*0700*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea2000c1e1900 */
/*0710*/ IMAD.WIDE R22, R4, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x000fc600078e0212 */
/*0720*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0730*/ IMAD.WIDE R12, R4.reuse, 0x4, R22 ; /* 0x00000004040c7825 */
/* 0x040fe200078e0216 */
/*0740*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002e8000c1e1900 */
/*0750*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000962000c1e1900 */
/*0760*/ IMAD.WIDE R14, R4, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x000fc600078e020c */
/*0770*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f66000c1e1900 */
/*0780*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x040fe200078e020e */
/*0790*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f68000c1e1900 */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000962000c1e1900 */
/*07b0*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x001fc600078e0210 */
/*07c0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000166000c1e1900 */
/*07d0*/ IMAD.WIDE R22, R4.reuse, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x042fe200078e0212 */
/*07e0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R15, [R10.64+0x10] ; /* 0x000010040a0f7981 */
/* 0x010f22000c1e1900 */
/*0800*/ IMAD.WIDE R12, R4, 0x4, R22 ; /* 0x00000004040c7825 */
/* 0x000fc600078e0216 */
/*0810*/ LDG.E R18, [R10.64+0x1c] ; /* 0x00001c040a127981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x001f22000c1e1900 */
/*0830*/ IMAD R19, R20, R9, R21 ; /* 0x0000000914137224 */
/* 0x004fc600078e0215 */
/*0840*/ LDG.E R21, [R10.64+0x14] ; /* 0x000014040a157981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R20, [R10.64+0x18] ; /* 0x000018040a147981 */
/* 0x000ea2000c1e1900 */
/*0870*/ IMAD R24, R24, R25, R19 ; /* 0x0000001918187224 */
/* 0x008fc800078e0213 */
/*0880*/ IMAD R24, R26, R27, R24 ; /* 0x0000001b1a187224 */
/* 0x020fc800078e0218 */
/*0890*/ IMAD R14, R14, R29, R24 ; /* 0x0000001d0e0e7224 */
/* 0x000fc800078e0218 */
/*08a0*/ IMAD R14, R16, R15, R14 ; /* 0x0000000f100e7224 */
/* 0x010fe200078e020e */
/*08b0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08d0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*08e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0900*/ IMAD R14, R28, R21, R14 ; /* 0x000000151c0e7224 */
/* 0x004fc800078e020e */
/*0910*/ IMAD R9, R9, R20, R14 ; /* 0x0000001409097224 */
/* 0x000fc800078e020e */
/*0920*/ IMAD R21, R17, R18, R9 ; /* 0x0000001211157224 */
/* 0x000fe400078e0209 */
/*0930*/ IMAD.WIDE R18, R4, 0x4, R12 ; /* 0x0000000404127825 */
/* 0x000fc800078e020c */
/*0940*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R12, R4, 0x4, R18 ; /* 0x00000004040c7825 */
/* 0x000fe200078e0212 */
/*0980*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fc800078e020a */
/*09b0*/ IMAD.WIDE R14, R4.reuse, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x040fe200078e020c */
/*09c0*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fc600078e020e */
/*09f0*/ LDG.E R20, [R10.64+0x4] ; /* 0x000004040a147981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R23, [R10.64+0x8] ; /* 0x000008040a177981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R25, [R10.64+0xc] ; /* 0x00000c040a197981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R9, R18, R9, R21 ; /* 0x0000000912097224 */
/* 0x004fc800078e0215 */
/*0aa0*/ IMAD R9, R12, R20, R9 ; /* 0x000000140c097224 */
/* 0x008fe400078e0209 */
/*0ab0*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x000fc800078e0210 */
/*0ac0*/ IMAD R9, R22, R23, R9 ; /* 0x0000001716097224 */
/* 0x010fc800078e0209 */
/*0ad0*/ IMAD R21, R24, R25, R9 ; /* 0x0000001918157224 */
/* 0x020fe200078e0209 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xc30 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R8, R5, R6, RZ ; /* 0x0000000605087210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R3, R6, c[0x0][0x178], R3 ; /* 0x00005e0006037a24 */
/* 0x000fca00078e0203 */
/*0b40*/ LEA R3, R0, R3, 0x4 ; /* 0x0000000300037211 */
/* 0x000fc600078e20ff */
/*0b50*/ IMAD.WIDE R8, R8, R10, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e020a */
/*0b60*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fe40000000f00 */
/*0b70*/ MOV R11, R9 ; /* 0x00000009000b7202 */
/* 0x000fe20000000f00 */
/*0b80*/ IMAD.WIDE R8, R3, R10, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e020a */
/*0b90*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fe20000000f00 */
/*0ba0*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc40007f3e0ff */
/*0be0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0bf0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x002fc60000ffe4ff */
/*0c10*/ IMAD R21, R0, R3, R21 ; /* 0x0000000300157224 */
/* 0x004fd000078e0215 */
/*0c20*/ @P0 BRA 0xb90 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c30*/ IADD3 R2, R2, R5, RZ ; /* 0x0000000502027210 */
/* 0x000fe40007ffe0ff */
/*0c40*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c50*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c60*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101904 */
/*0c70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c80*/ BRA 0xc80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <sys/time.h>
#define N 512
#define TILE_WIDTH 16
__global__ void matrixMult (int *a, int *b, int *c, int width);
void matrixMultCPU (int a[N][N], int b[N][N], int c[N][N], int width);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_start = (double)(start.tv_sec + start.tv_usec/1000000.0);
d_end = (double)(end.tv_sec + end.tv_usec/1000000.0);
return (d_end - d_start);
}
int main()
{
int a[N][N], b[N][N], c[N][N], g[N][N];
timeval start, end;
int *dev_a, *dev_b, *dev_c;
int size = N * N * sizeof(int);
// initialize matrices a and b with appropriate values
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
a[i][j] = i*N + j;
b[i][j] = i + j;
}
}
// initialize a and b matrices here
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_b, size);
cudaMalloc((void **) &dev_c, size);
gettimeofday(&start, NULL);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid((int)ceil(N/dimBlock.x), (int)ceil(N/dimBlock.y));
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
cudaDeviceSynchronize();
cudaMemcpy(g, dev_c, size, cudaMemcpyDeviceToHost);
gettimeofday(&end, NULL);
printf("GPU Time for %i additions: %f\n", N, myDiffTime(start, end));
gettimeofday(&start, NULL);
matrixMultCPU(a, b, c, N);
gettimeofday(&end, NULL);
printf("CPU Time for %i additions: %f\n", N, myDiffTime(start, end));
cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c);
// print verification
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
if (c[i][j] != g[i][j])
{
printf("Results do not match! %i, %i, c=%i, g=%i\n", i, j, c[i][j], g[i][j]);
exit(1);
}
}
}
}
__global__ void matrixMult(int* A, int* B, int* C, int width)
{
int k, sum = 0;
int col = blockIdx.x*TILE_WIDTH + threadIdx.x;
int row = blockIdx.y*TILE_WIDTH + threadIdx.y;
if(col < width && row < width)
{
for (k = 0; k < width; k++)
sum += A[row * width + k] * B[k * width + col];
C[row * width + col] = sum;
}
}
void matrixMultCPU (int a[N][N], int b[N][N], int c[N][N], int width)
{
for (int i = 0; i < width; i++)
{
for (int j = 0; j < width; j++)
{
int sum = 0;
for (int k = 0; k < width; k++)
{
int m = a[i][k];
int n = b[k][j];
sum += m * n;
}
c[i][j] = sum;
}
}
} | .file "tmpxft_000110f6_00000000-6_m_multTile.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10myDiffTimeR7timevalS0_
.type _Z10myDiffTimeR7timevalS0_, @function
_Z10myDiffTimeR7timevalS0_:
.LFB2057:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsi), %xmm0
movsd .LC0(%rip), %xmm2
divsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsi), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8(%rdi), %xmm1
divsd %xmm2, %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq (%rdi), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z10myDiffTimeR7timevalS0_, .-_Z10myDiffTimeR7timevalS0_
.globl _Z13matrixMultCPUPA512_iS0_S0_i
.type _Z13matrixMultCPUPA512_iS0_S0_i, @function
_Z13matrixMultCPUPA512_iS0_S0_i:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L12
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %r11
movq %rdx, %rbp
movl %ecx, %eax
movq %rdi, %r9
cltq
leaq 0(,%rax,4), %rbx
leaq (%rdi,%rbx), %rdi
salq $11, %rax
addq %rax, %r12
.L6:
movq %rbp, %r10
movl $0, %r8d
.L9:
leaq (%r11,%r8), %rcx
movq %r9, %rax
movl $0, %esi
.L7:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, %esi
addq $4, %rax
addq $2048, %rcx
cmpq %rdi, %rax
jne .L7
movl %esi, (%r10,%r8)
addq $4, %r8
cmpq %rbx, %r8
jne .L9
addq $2048, %rbp
addq $2048, %r9
addq $2048, %rdi
cmpq %r12, %r9
jne .L6
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2059:
.size _Z13matrixMultCPUPA512_iS0_S0_i, .-_Z13matrixMultCPUPA512_iS0_S0_i
.globl _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixMultPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.globl _Z10matrixMultPiS_S_i
.type _Z10matrixMultPiS_S_i, @function
_Z10matrixMultPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10matrixMultPiS_S_i, .-_Z10matrixMultPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "GPU Time for %i additions: %f\n"
.align 8
.LC2:
.string "CPU Time for %i additions: %f\n"
.align 8
.LC3:
.string "Results do not match! %i, %i, c=%i, g=%i\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -4194304(%rsp), %r11
.cfi_def_cfa 11, 4194344
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $104, %rsp
.cfi_def_cfa_offset 4194448
movq %fs:40, %rax
movq %rax, 4194392(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %r8
leaq 1048656(%rsp), %rdi
movl $0, %esi
movl $0, %ecx
.L24:
movl $0, %eax
.L25:
leal (%rsi,%rax), %edx
movl %edx, (%r8,%rax,4)
leal (%rcx,%rax), %edx
movl %edx, (%rdi,%rax,4)
addq $1, %rax
cmpq $512, %rax
jne .L25
addl $1, %ecx
addl $512, %esi
addq $2048, %r8
addq $2048, %rdi
cmpl $512, %ecx
jne .L24
movq %rsp, %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $1048576, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 1048656(%rsp), %rsi
movl $1, %ecx
movl $1048576, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $32, 36(%rsp)
movl $32, 40(%rsp)
movl $1, 44(%rsp)
movl $16, 24(%rsp)
movl $16, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L27:
call cudaDeviceSynchronize@PLT
leaq 3145808(%rsp), %rbx
movl $2, %ecx
movl $1048576, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %r12
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
leaq 48(%rsp), %r13
movq %r12, %rsi
movq %r13, %rdi
call _Z10myDiffTimeR7timevalS0_
movl $512, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq %r13, %rdi
call gettimeofday@PLT
leaq 2097232(%rsp), %rbp
leaq 1048656(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $512, %ecx
movq %rbp, %rdx
call _Z13matrixMultCPUPA512_iS0_S0_i
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
movq %r12, %rsi
movq %r13, %rdi
call _Z10myDiffTimeR7timevalS0_
movl $512, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rcx
movq %rbx, %rdx
movl $0, %esi
jmp .L28
.L36:
movl $512, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
jmp .L27
.L37:
movl %eax, %ecx
movl %esi, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
addl $1, %esi
addq $2048, %rcx
addq $2048, %rdx
cmpl $512, %esi
je .L31
.L28:
movl $0, %eax
.L30:
movl (%rcx,%rax,4), %r8d
movl (%rdx,%rax,4), %r9d
cmpl %r9d, %r8d
jne .L37
addq $1, %rax
cmpq $512, %rax
jne .L30
jmp .L38
.L31:
movq 4194392(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $4194408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z10matrixMultPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixMultPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <sys/time.h>
#define N 512
#define TILE_WIDTH 16
__global__ void matrixMult (int *a, int *b, int *c, int width);
void matrixMultCPU (int a[N][N], int b[N][N], int c[N][N], int width);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_start = (double)(start.tv_sec + start.tv_usec/1000000.0);
d_end = (double)(end.tv_sec + end.tv_usec/1000000.0);
return (d_end - d_start);
}
int main()
{
int a[N][N], b[N][N], c[N][N], g[N][N];
timeval start, end;
int *dev_a, *dev_b, *dev_c;
int size = N * N * sizeof(int);
// initialize matrices a and b with appropriate values
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
a[i][j] = i*N + j;
b[i][j] = i + j;
}
}
// initialize a and b matrices here
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_b, size);
cudaMalloc((void **) &dev_c, size);
gettimeofday(&start, NULL);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid((int)ceil(N/dimBlock.x), (int)ceil(N/dimBlock.y));
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
cudaDeviceSynchronize();
cudaMemcpy(g, dev_c, size, cudaMemcpyDeviceToHost);
gettimeofday(&end, NULL);
printf("GPU Time for %i additions: %f\n", N, myDiffTime(start, end));
gettimeofday(&start, NULL);
matrixMultCPU(a, b, c, N);
gettimeofday(&end, NULL);
printf("CPU Time for %i additions: %f\n", N, myDiffTime(start, end));
cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c);
// print verification
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
if (c[i][j] != g[i][j])
{
printf("Results do not match! %i, %i, c=%i, g=%i\n", i, j, c[i][j], g[i][j]);
exit(1);
}
}
}
}
__global__ void matrixMult(int* A, int* B, int* C, int width)
{
int k, sum = 0;
int col = blockIdx.x*TILE_WIDTH + threadIdx.x;
int row = blockIdx.y*TILE_WIDTH + threadIdx.y;
if(col < width && row < width)
{
for (k = 0; k < width; k++)
sum += A[row * width + k] * B[k * width + col];
C[row * width + col] = sum;
}
}
void matrixMultCPU (int a[N][N], int b[N][N], int c[N][N], int width)
{
for (int i = 0; i < width; i++)
{
for (int j = 0; j < width; j++)
{
int sum = 0;
for (int k = 0; k < width; k++)
{
int m = a[i][k];
int n = b[k][j];
sum += m * n;
}
c[i][j] = sum;
}
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define N 512
#define TILE_WIDTH 16
__global__ void matrixMult (int *a, int *b, int *c, int width);
void matrixMultCPU (int a[N][N], int b[N][N], int c[N][N], int width);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_start = (double)(start.tv_sec + start.tv_usec/1000000.0);
d_end = (double)(end.tv_sec + end.tv_usec/1000000.0);
return (d_end - d_start);
}
int main()
{
int a[N][N], b[N][N], c[N][N], g[N][N];
timeval start, end;
int *dev_a, *dev_b, *dev_c;
int size = N * N * sizeof(int);
// initialize matrices a and b with appropriate values
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
a[i][j] = i*N + j;
b[i][j] = i + j;
}
}
// initialize a and b matrices here
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_b, size);
hipMalloc((void **) &dev_c, size);
gettimeofday(&start, NULL);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid((int)ceil(N/dimBlock.x), (int)ceil(N/dimBlock.y));
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
hipDeviceSynchronize();
hipMemcpy(g, dev_c, size, hipMemcpyDeviceToHost);
gettimeofday(&end, NULL);
printf("GPU Time for %i additions: %f\n", N, myDiffTime(start, end));
gettimeofday(&start, NULL);
matrixMultCPU(a, b, c, N);
gettimeofday(&end, NULL);
printf("CPU Time for %i additions: %f\n", N, myDiffTime(start, end));
hipFree(dev_a); hipFree(dev_b); hipFree(dev_c);
// print verification
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
if (c[i][j] != g[i][j])
{
printf("Results do not match! %i, %i, c=%i, g=%i\n", i, j, c[i][j], g[i][j]);
exit(1);
}
}
}
}
__global__ void matrixMult(int* A, int* B, int* C, int width)
{
int k, sum = 0;
int col = blockIdx.x*TILE_WIDTH + threadIdx.x;
int row = blockIdx.y*TILE_WIDTH + threadIdx.y;
if(col < width && row < width)
{
for (k = 0; k < width; k++)
sum += A[row * width + k] * B[k * width + col];
C[row * width + col] = sum;
}
}
void matrixMultCPU (int a[N][N], int b[N][N], int c[N][N], int width)
{
for (int i = 0; i < width; i++)
{
for (int j = 0; j < width; j++)
{
int sum = 0;
for (int k = 0; k < width; k++)
{
int m = a[i][k];
int n = b[k][j];
sum += m * n;
}
c[i][j] = sum;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define N 512
#define TILE_WIDTH 16
__global__ void matrixMult (int *a, int *b, int *c, int width);
void matrixMultCPU (int a[N][N], int b[N][N], int c[N][N], int width);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_start = (double)(start.tv_sec + start.tv_usec/1000000.0);
d_end = (double)(end.tv_sec + end.tv_usec/1000000.0);
return (d_end - d_start);
}
int main()
{
int a[N][N], b[N][N], c[N][N], g[N][N];
timeval start, end;
int *dev_a, *dev_b, *dev_c;
int size = N * N * sizeof(int);
// initialize matrices a and b with appropriate values
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
a[i][j] = i*N + j;
b[i][j] = i + j;
}
}
// initialize a and b matrices here
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_b, size);
hipMalloc((void **) &dev_c, size);
gettimeofday(&start, NULL);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid((int)ceil(N/dimBlock.x), (int)ceil(N/dimBlock.y));
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
hipDeviceSynchronize();
hipMemcpy(g, dev_c, size, hipMemcpyDeviceToHost);
gettimeofday(&end, NULL);
printf("GPU Time for %i additions: %f\n", N, myDiffTime(start, end));
gettimeofday(&start, NULL);
matrixMultCPU(a, b, c, N);
gettimeofday(&end, NULL);
printf("CPU Time for %i additions: %f\n", N, myDiffTime(start, end));
hipFree(dev_a); hipFree(dev_b); hipFree(dev_c);
// print verification
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
if (c[i][j] != g[i][j])
{
printf("Results do not match! %i, %i, c=%i, g=%i\n", i, j, c[i][j], g[i][j]);
exit(1);
}
}
}
}
__global__ void matrixMult(int* A, int* B, int* C, int width)
{
int k, sum = 0;
int col = blockIdx.x*TILE_WIDTH + threadIdx.x;
int row = blockIdx.y*TILE_WIDTH + threadIdx.y;
if(col < width && row < width)
{
for (k = 0; k < width; k++)
sum += A[row * width + k] * B[k * width + col];
C[row * width + col] = sum;
}
}
void matrixMultCPU (int a[N][N], int b[N][N], int c[N][N], int width)
{
for (int i = 0; i < width; i++)
{
for (int j = 0; j < width; j++)
{
int sum = 0;
for (int k = 0; k < width; k++)
{
int m = a[i][k];
int n = b[k][j];
sum += m * n;
}
c[i][j] = sum;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixMultPiS_S_i
.globl _Z10matrixMultPiS_S_i
.p2align 8
.type _Z10matrixMultPiS_S_i,@function
_Z10matrixMultPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 4, v1
v_lshl_add_u32 v6, s15, 4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v0, v6
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v1, v6, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v9, v[7:8], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, v5, v[1:2]
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v1, v7 :: v_dual_add_nc_u32 v4, s2, v4
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v1, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v6, s2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixMultPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixMultPiS_S_i, .Lfunc_end0-_Z10matrixMultPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixMultPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixMultPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define N 512
#define TILE_WIDTH 16
__global__ void matrixMult (int *a, int *b, int *c, int width);
void matrixMultCPU (int a[N][N], int b[N][N], int c[N][N], int width);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_start = (double)(start.tv_sec + start.tv_usec/1000000.0);
d_end = (double)(end.tv_sec + end.tv_usec/1000000.0);
return (d_end - d_start);
}
int main()
{
int a[N][N], b[N][N], c[N][N], g[N][N];
timeval start, end;
int *dev_a, *dev_b, *dev_c;
int size = N * N * sizeof(int);
// initialize matrices a and b with appropriate values
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
a[i][j] = i*N + j;
b[i][j] = i + j;
}
}
// initialize a and b matrices here
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_b, size);
hipMalloc((void **) &dev_c, size);
gettimeofday(&start, NULL);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid((int)ceil(N/dimBlock.x), (int)ceil(N/dimBlock.y));
matrixMult<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, N);
hipDeviceSynchronize();
hipMemcpy(g, dev_c, size, hipMemcpyDeviceToHost);
gettimeofday(&end, NULL);
printf("GPU Time for %i additions: %f\n", N, myDiffTime(start, end));
gettimeofday(&start, NULL);
matrixMultCPU(a, b, c, N);
gettimeofday(&end, NULL);
printf("CPU Time for %i additions: %f\n", N, myDiffTime(start, end));
hipFree(dev_a); hipFree(dev_b); hipFree(dev_c);
// print verification
for (int i = 0; i < N; i++)
{
for (int j = 0; j < N; j++)
{
if (c[i][j] != g[i][j])
{
printf("Results do not match! %i, %i, c=%i, g=%i\n", i, j, c[i][j], g[i][j]);
exit(1);
}
}
}
}
__global__ void matrixMult(int* A, int* B, int* C, int width)
{
int k, sum = 0;
int col = blockIdx.x*TILE_WIDTH + threadIdx.x;
int row = blockIdx.y*TILE_WIDTH + threadIdx.y;
if(col < width && row < width)
{
for (k = 0; k < width; k++)
sum += A[row * width + k] * B[k * width + col];
C[row * width + col] = sum;
}
}
void matrixMultCPU (int a[N][N], int b[N][N], int c[N][N], int width)
{
for (int i = 0; i < width; i++)
{
for (int j = 0; j < width; j++)
{
int sum = 0;
for (int k = 0; k < width; k++)
{
int m = a[i][k];
int n = b[k][j];
sum += m * n;
}
c[i][j] = sum;
}
}
} | .text
.file "m_multTile.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10myDiffTimeR7timevalS0_
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z10myDiffTimeR7timevalS0_
.p2align 4, 0x90
.type _Z10myDiffTimeR7timevalS0_,@function
_Z10myDiffTimeR7timevalS0_: # @_Z10myDiffTimeR7timevalS0_
.cfi_startproc
# %bb.0:
cvtsi2sdq (%rdi), %xmm0
cvtsi2sdq 8(%rdi), %xmm1
movsd .LCPI0_0(%rip), %xmm2 # xmm2 = mem[0],zero
divsd %xmm2, %xmm1
addsd %xmm0, %xmm1
cvtsi2sdq (%rsi), %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsi), %xmm0
divsd %xmm2, %xmm0
addsd %xmm3, %xmm0
subsd %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z10myDiffTimeR7timevalS0_, .Lfunc_end0-_Z10myDiffTimeR7timevalS0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $4194424, %rsp # imm = 0x400078
.cfi_def_cfa_offset 4194464
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # %.preheader47
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl $512, %edx # imm = 0x200
movq %rax, %rsi
movl %ecx, %edi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %esi, 3145840(%rsp,%rsi,4)
movl %edi, 2097264(%rsp,%rsi,4)
incl %edi
incq %rsi
decq %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $512, %rax # imm = 0x200
cmpq $512, %rcx # imm = 0x200
jne .LBB1_1
# %bb.4:
leaq 40(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %rdi
leaq 3145840(%rsp), %rbx
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
leaq 2097264(%rsp), %r15
movl $1048576, %edx # imm = 0x100000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $137438953504, %rdi # imm = 0x2000000020
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $512, 52(%rsp) # imm = 0x200
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 1048688(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 1048688(%rsp), %rsi
movl 1048696(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10matrixMultPiS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
leaq 1048688(%rsp), %r14
movl $1048576, %edx # imm = 0x100000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 56(%rsp), %xmm1
cvtsi2sdq 64(%rsp), %xmm2
movsd .LCPI1_0(%rip), %xmm4 # xmm4 = mem[0],zero
divsd %xmm4, %xmm2
cvtsi2sdq 8(%rsp), %xmm3
cvtsi2sdq 16(%rsp), %xmm0
addsd %xmm1, %xmm2
divsd %xmm4, %xmm0
addsd %xmm3, %xmm0
subsd %xmm2, %xmm0
movl $.L.str, %edi
movl $512, %esi # imm = 0x200
movb $1, %al
callq printf
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
.p2align 4, 0x90
.LBB1_7: # %.preheader25.i
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
# Child Loop BB1_9 Depth 3
movq %r12, %rax
shlq $11, %rax
addq %rsp, %rax
addq $112, %rax
movq %r15, %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_8: # %.preheader.i
# Parent Loop BB1_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_9 Depth 3
xorl %esi, %esi
movq %rcx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_9: # Parent Loop BB1_7 Depth=1
# Parent Loop BB1_8 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rdi), %r9d
imull (%rbx,%rsi,4), %r9d
addl %r9d, %r8d
incq %rsi
addq $2048, %rdi # imm = 0x800
cmpq $512, %rsi # imm = 0x200
jne .LBB1_9
# %bb.10: # %._crit_edge.i
# in Loop: Header=BB1_8 Depth=2
movl %r8d, (%rax,%rdx,4)
incq %rdx
addq $4, %rcx
cmpq $512, %rdx # imm = 0x200
jne .LBB1_8
# %bb.11: # %._crit_edge29.i
# in Loop: Header=BB1_7 Depth=1
incq %r12
addq $2048, %rbx # imm = 0x800
cmpq $512, %r12 # imm = 0x200
jne .LBB1_7
# %bb.12: # %_Z13matrixMultCPUPA512_iS0_S0_i.exit
xorl %ebx, %ebx
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 56(%rsp), %xmm1
xorps %xmm2, %xmm2
cvtsi2sdq 64(%rsp), %xmm2
movsd .LCPI1_0(%rip), %xmm4 # xmm4 = mem[0],zero
divsd %xmm4, %xmm2
xorps %xmm3, %xmm3
cvtsi2sdq 8(%rsp), %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
addsd %xmm1, %xmm2
divsd %xmm4, %xmm0
addsd %xmm3, %xmm0
subsd %xmm2, %xmm0
movl $.L.str.1, %edi
movl $512, %esi # imm = 0x200
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
leaq 112(%rsp), %rax
.p2align 4, 0x90
.LBB1_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_14 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_14: # Parent Loop BB1_13 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rax,%rdx,4), %ecx
movl (%r14,%rdx,4), %r8d
cmpl %r8d, %ecx
jne .LBB1_18
# %bb.15: # in Loop: Header=BB1_14 Depth=2
incq %rdx
cmpq $512, %rdx # imm = 0x200
jne .LBB1_14
# %bb.16: # in Loop: Header=BB1_13 Depth=1
incq %rbx
addq $2048, %rax # imm = 0x800
addq $2048, %r14 # imm = 0x800
cmpq $512, %rbx # imm = 0x200
jne .LBB1_13
# %bb.17:
xorl %eax, %eax
addq $4194424, %rsp # imm = 0x400078
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 4194464
movl $.L.str.2, %edi
movl %ebx, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matrixMultPiS_S_i # -- Begin function _Z25__device_stub__matrixMultPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixMultPiS_S_i,@function
_Z25__device_stub__matrixMultPiS_S_i: # @_Z25__device_stub__matrixMultPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixMultPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__matrixMultPiS_S_i, .Lfunc_end2-_Z25__device_stub__matrixMultPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13matrixMultCPUPA512_iS0_S0_i # -- Begin function _Z13matrixMultCPUPA512_iS0_S0_i
.p2align 4, 0x90
.type _Z13matrixMultCPUPA512_iS0_S0_i,@function
_Z13matrixMultCPUPA512_iS0_S0_i: # @_Z13matrixMultCPUPA512_iS0_S0_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB3_8
# %bb.1: # %.preheader25.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.preheader25
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_4 Depth 3
movq %rcx, %r8
shlq $11, %r8
addq %rdx, %r8
movq %rsi, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_3: # %.preheader
# Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
xorl %r11d, %r11d
movq %r9, %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rbx), %r14d
imull (%rdi,%r11,4), %r14d
addl %r14d, %ebp
incq %r11
addq $2048, %rbx # imm = 0x800
cmpq %r11, %rax
jne .LBB3_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB3_3 Depth=2
movl %ebp, (%r8,%r10,4)
incq %r10
addq $4, %r9
cmpq %rax, %r10
jne .LBB3_3
# %bb.6: # %._crit_edge29
# in Loop: Header=BB3_2 Depth=1
incq %rcx
addq $2048, %rdi # imm = 0x800
cmpq %rax, %rcx
jne .LBB3_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %rbp
.LBB3_8: # %._crit_edge31
retq
.Lfunc_end3:
.size _Z13matrixMultCPUPA512_iS0_S0_i, .Lfunc_end3-_Z13matrixMultCPUPA512_iS0_S0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixMultPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixMultPiS_S_i,@object # @_Z10matrixMultPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10matrixMultPiS_S_i
.p2align 3, 0x0
_Z10matrixMultPiS_S_i:
.quad _Z25__device_stub__matrixMultPiS_S_i
.size _Z10matrixMultPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU Time for %i additions: %f\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU Time for %i additions: %f\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Results do not match! %i, %i, c=%i, g=%i\n"
.size .L.str.2, 42
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixMultPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixMultPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixMultPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10matrixMultPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ LEA R5, R5, R2, 0x4 ; /* 0x0000000205057211 */
/* 0x001fc800078e20ff */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe40003f06270 */
/*0070*/ LEA R2, R0, R3, 0x4 ; /* 0x0000000300027211 */
/* 0x002fc800078e20ff */
/*0080*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x178], P0 ; /* 0x00005e0002007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc30 ; /* 0x00000b3000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R6, R4.reuse, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R8, -R7, c[0x0][0x178], RZ ; /* 0x00005e0007087a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R19, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff137435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R18, R2, R19, c[0x0][0x168] ; /* 0x00005a0002127625 */
/* 0x000fce00078e0213 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R5, 0x4, R12 ; /* 0x00000004050c7825 */
/* 0x000fc800078e020c */
/*0250*/ IMAD.WIDE R22, R4.reuse, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x040fe200078e0212 */
/*0260*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002e8000c1e1900 */
/*0280*/ LDG.E R11, [R12.64+0x4] ; /* 0x000004040c0b7981 */
/* 0x000ee8000c1e1900 */
/*0290*/ LDG.E R14, [R12.64+0x8] ; /* 0x000008040c0e7981 */
/* 0x000f22000c1e1900 */
/*02a0*/ IMAD.WIDE R22, R4, 0x4, R22 ; /* 0x0000000404167825 */
/* 0x002fc600078e0216 */
/*02b0*/ LDG.E R19, [R12.64+0x10] ; /* 0x000010040c137981 */
/* 0x001f68000c1e1900 */
/*02c0*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000122000c1e1900 */
/*02d0*/ IMAD.WIDE R16, R4, 0x4, R22 ; /* 0x0000000404107825 */
/* 0x000fc600078e0216 */
/*02e0*/ LDG.E R9, [R12.64+0x14] ; /* 0x000014040c097981 */
/* 0x000f66000c1e1900 */
/*02f0*/ IMAD.WIDE R26, R4.reuse, 0x4, R16 ; /* 0x00000004041a7825 */
/* 0x040fe400078e0210 */
/*0300*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000368000c1e1900 */
/*0310*/ IMAD.WIDE R28, R4.reuse, 0x4, R26 ; /* 0x00000004041c7825 */
/* 0x040fe200078e021a */
/*0320*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000168000c1e1900 */
/*0330*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000968000c1e1900 */
/*0340*/ LDG.E R17, [R12.64+0xc] ; /* 0x00000c040c117981 */
/* 0x002f62000c1e1900 */
/*0350*/ IMAD.WIDE R22, R4, 0x4, R28 ; /* 0x0000000404167825 */
/* 0x001fc600078e021c */
/*0360*/ LDG.E R26, [R12.64+0x1c] ; /* 0x00001c040c1a7981 */
/* 0x000f62000c1e1900 */
/*0370*/ IMAD R25, R10, R25, R21 ; /* 0x000000190a197224 */
/* 0x004fc600078e0215 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x0000a8000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R22, R4, 0x4, R22 ; /* 0x0000000404167825 */
/* 0x001fc800078e0216 */
/*03b0*/ IMAD R27, R24, R11, R25 ; /* 0x0000000b181b7224 */
/* 0x008fe400078e0219 */
/*03c0*/ IMAD.WIDE R24, R4.reuse, 0x4, R22 ; /* 0x0000000404187825 */
/* 0x040fe200078e0216 */
/*03d0*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x0000e6000c1e1900 */
/*03e0*/ IMAD R29, R15, R14, R27 ; /* 0x0000000e0f1d7224 */
/* 0x010fe200078e021b */
/*03f0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x000328000c1e1900 */
/*0400*/ LDG.E R27, [R12.64+0x20] ; /* 0x000020040c1b7981 */
/* 0x000f22000c1e1900 */
/*0410*/ IMAD.WIDE R14, R4, 0x4, R24 ; /* 0x00000004040e7825 */
/* 0x000fc600078e0218 */
/*0420*/ LDG.E R25, [R12.64+0x28] ; /* 0x000028040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x020fe400078e021d */
/*0440*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fe400078e020e */
/*0450*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000364000c1e1900 */
/*0460*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x000fe400078e021d */
/*0470*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x000fe400078e0210 */
/*0480*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000364000c1e1900 */
/*0490*/ IMAD R20, R20, R9, R29 ; /* 0x0000000914147224 */
/* 0x000fc400078e021d */
/*04a0*/ LDG.E R9, [R12.64+0x24] ; /* 0x000024040c097981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD.WIDE R22, R4, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x001fc600078e0212 */
/*04c0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000768000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x002f68000c1e1900 */
/*04e0*/ LDG.E R29, [R22.64] ; /* 0x00000004161d7981 */
/* 0x000162000c1e1900 */
/*04f0*/ IMAD R10, R10, R21, R20 ; /* 0x000000150a0a7224 */
/* 0x004fe400078e0214 */
/*0500*/ IMAD.WIDE R20, R4, 0x4, R22 ; /* 0x0000000404147825 */
/* 0x000fc400078e0216 */
/*0510*/ LDG.E R22, [R12.64+0x38] ; /* 0x000038040c167981 */
/* 0x001ea8000c1e1900 */
/*0520*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x0008a2000c1e1900 */
/*0530*/ IMAD R18, R11, R26, R10 ; /* 0x0000001a0b127224 */
/* 0x008fc600078e020a */
/*0540*/ LDG.E R26, [R12.64+0x30] ; /* 0x000030040c1a7981 */
/* 0x000ee2000c1e1900 */
/*0550*/ IMAD.WIDE R10, R4, 0x4, R20 ; /* 0x00000004040a7825 */
/* 0x000fc800078e0214 */
/*0560*/ IMAD R20, R28, R27, R18 ; /* 0x0000001b1c147224 */
/* 0x010fe400078e0212 */
/*0570*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IMAD.WIDE R18, R4, 0x4, R10 ; /* 0x0000000404127825 */
/* 0x000fc600078e020a */
/*0590*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x000128000c1e1900 */
/*05a0*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000328000c1e1900 */
/*05b0*/ LDG.E R10, [R12.64+0x3c] ; /* 0x00003c040c0a7981 */
/* 0x001f22000c1e1900 */
/*05c0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*05d0*/ IMAD R9, R14, R9, R20 ; /* 0x000000090e097224 */
/* 0x020fc800078e0214 */
/*05e0*/ IMAD R9, R16, R25, R9 ; /* 0x0000001910097224 */
/* 0x000fe200078e0209 */
/*05f0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*0600*/ IMAD R9, R24, R15, R9 ; /* 0x0000000f18097224 */
/* 0x000fe200078e0209 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD.WIDE R18, R4, 0x4, R18 ; /* 0x0000000404127825 */
/* 0x002fc800078e0212 */
/*0650*/ IMAD R9, R29, R26, R9 ; /* 0x0000001a1d097224 */
/* 0x008fc800078e0209 */
/*0660*/ IMAD R9, R17, R28, R9 ; /* 0x0000001c11097224 */
/* 0x004fc800078e0209 */
/*0670*/ IMAD R9, R27, R22, R9 ; /* 0x000000161b097224 */
/* 0x010fc800078e0209 */
/*0680*/ IMAD R21, R23, R10, R9 ; /* 0x0000000a17157224 */
/* 0x000fe200078e0209 */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*06d0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x0000a2000c1e1900 */
/*06e0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*06f0*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fca00078e020a */
/*0700*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea2000c1e1900 */
/*0710*/ IMAD.WIDE R22, R4, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x000fc600078e0212 */
/*0720*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0730*/ IMAD.WIDE R12, R4.reuse, 0x4, R22 ; /* 0x00000004040c7825 */
/* 0x040fe200078e0216 */
/*0740*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002e8000c1e1900 */
/*0750*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000962000c1e1900 */
/*0760*/ IMAD.WIDE R14, R4, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x000fc600078e020c */
/*0770*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f66000c1e1900 */
/*0780*/ IMAD.WIDE R16, R4.reuse, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x040fe200078e020e */
/*0790*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f68000c1e1900 */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000962000c1e1900 */
/*07b0*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x001fc600078e0210 */
/*07c0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000166000c1e1900 */
/*07d0*/ IMAD.WIDE R22, R4.reuse, 0x4, R18 ; /* 0x0000000404167825 */
/* 0x042fe200078e0212 */
/*07e0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R15, [R10.64+0x10] ; /* 0x000010040a0f7981 */
/* 0x010f22000c1e1900 */
/*0800*/ IMAD.WIDE R12, R4, 0x4, R22 ; /* 0x00000004040c7825 */
/* 0x000fc600078e0216 */
/*0810*/ LDG.E R18, [R10.64+0x1c] ; /* 0x00001c040a127981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x001f22000c1e1900 */
/*0830*/ IMAD R19, R20, R9, R21 ; /* 0x0000000914137224 */
/* 0x004fc600078e0215 */
/*0840*/ LDG.E R21, [R10.64+0x14] ; /* 0x000014040a157981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R20, [R10.64+0x18] ; /* 0x000018040a147981 */
/* 0x000ea2000c1e1900 */
/*0870*/ IMAD R24, R24, R25, R19 ; /* 0x0000001918187224 */
/* 0x008fc800078e0213 */
/*0880*/ IMAD R24, R26, R27, R24 ; /* 0x0000001b1a187224 */
/* 0x020fc800078e0218 */
/*0890*/ IMAD R14, R14, R29, R24 ; /* 0x0000001d0e0e7224 */
/* 0x000fc800078e0218 */
/*08a0*/ IMAD R14, R16, R15, R14 ; /* 0x0000000f100e7224 */
/* 0x010fe200078e020e */
/*08b0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08d0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*08e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0900*/ IMAD R14, R28, R21, R14 ; /* 0x000000151c0e7224 */
/* 0x004fc800078e020e */
/*0910*/ IMAD R9, R9, R20, R14 ; /* 0x0000001409097224 */
/* 0x000fc800078e020e */
/*0920*/ IMAD R21, R17, R18, R9 ; /* 0x0000001211157224 */
/* 0x000fe400078e0209 */
/*0930*/ IMAD.WIDE R18, R4, 0x4, R12 ; /* 0x0000000404127825 */
/* 0x000fc800078e020c */
/*0940*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R12, R4, 0x4, R18 ; /* 0x00000004040c7825 */
/* 0x000fe200078e0212 */
/*0980*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fc800078e020a */
/*09b0*/ IMAD.WIDE R14, R4.reuse, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x040fe200078e020c */
/*09c0*/ LDG.E R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fc600078e020e */
/*09f0*/ LDG.E R20, [R10.64+0x4] ; /* 0x000004040a147981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R23, [R10.64+0x8] ; /* 0x000008040a177981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R25, [R10.64+0xc] ; /* 0x00000c040a197981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R9, R18, R9, R21 ; /* 0x0000000912097224 */
/* 0x004fc800078e0215 */
/*0aa0*/ IMAD R9, R12, R20, R9 ; /* 0x000000140c097224 */
/* 0x008fe400078e0209 */
/*0ab0*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x000fc800078e0210 */
/*0ac0*/ IMAD R9, R22, R23, R9 ; /* 0x0000001716097224 */
/* 0x010fc800078e0209 */
/*0ad0*/ IMAD R21, R24, R25, R9 ; /* 0x0000001918157224 */
/* 0x020fe200078e0209 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xc30 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R8, R5, R6, RZ ; /* 0x0000000605087210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R3, R6, c[0x0][0x178], R3 ; /* 0x00005e0006037a24 */
/* 0x000fca00078e0203 */
/*0b40*/ LEA R3, R0, R3, 0x4 ; /* 0x0000000300037211 */
/* 0x000fc600078e20ff */
/*0b50*/ IMAD.WIDE R8, R8, R10, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e020a */
/*0b60*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fe40000000f00 */
/*0b70*/ MOV R11, R9 ; /* 0x00000009000b7202 */
/* 0x000fe20000000f00 */
/*0b80*/ IMAD.WIDE R8, R3, R10, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e020a */
/*0b90*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fe20000000f00 */
/*0ba0*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc40007f3e0ff */
/*0be0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0bf0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x002fc60000ffe4ff */
/*0c10*/ IMAD R21, R0, R3, R21 ; /* 0x0000000300157224 */
/* 0x004fd000078e0215 */
/*0c20*/ @P0 BRA 0xb90 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c30*/ IADD3 R2, R2, R5, RZ ; /* 0x0000000502027210 */
/* 0x000fe40007ffe0ff */
/*0c40*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c50*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c60*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101904 */
/*0c70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c80*/ BRA 0xc80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixMultPiS_S_i
.globl _Z10matrixMultPiS_S_i
.p2align 8
.type _Z10matrixMultPiS_S_i,@function
_Z10matrixMultPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 4, v1
v_lshl_add_u32 v6, s15, 4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v0, v6
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v1, v6, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v9, v[7:8], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, v5, v[1:2]
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v1, v7 :: v_dual_add_nc_u32 v4, s2, v4
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v1, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v6, s2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixMultPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixMultPiS_S_i, .Lfunc_end0-_Z10matrixMultPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixMultPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixMultPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000110f6_00000000-6_m_multTile.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10myDiffTimeR7timevalS0_
.type _Z10myDiffTimeR7timevalS0_, @function
_Z10myDiffTimeR7timevalS0_:
.LFB2057:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsi), %xmm0
movsd .LC0(%rip), %xmm2
divsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsi), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8(%rdi), %xmm1
divsd %xmm2, %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq (%rdi), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z10myDiffTimeR7timevalS0_, .-_Z10myDiffTimeR7timevalS0_
.globl _Z13matrixMultCPUPA512_iS0_S0_i
.type _Z13matrixMultCPUPA512_iS0_S0_i, @function
_Z13matrixMultCPUPA512_iS0_S0_i:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L12
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %r11
movq %rdx, %rbp
movl %ecx, %eax
movq %rdi, %r9
cltq
leaq 0(,%rax,4), %rbx
leaq (%rdi,%rbx), %rdi
salq $11, %rax
addq %rax, %r12
.L6:
movq %rbp, %r10
movl $0, %r8d
.L9:
leaq (%r11,%r8), %rcx
movq %r9, %rax
movl $0, %esi
.L7:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, %esi
addq $4, %rax
addq $2048, %rcx
cmpq %rdi, %rax
jne .L7
movl %esi, (%r10,%r8)
addq $4, %r8
cmpq %rbx, %r8
jne .L9
addq $2048, %rbp
addq $2048, %r9
addq $2048, %rdi
cmpq %r12, %r9
jne .L6
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2059:
.size _Z13matrixMultCPUPA512_iS0_S0_i, .-_Z13matrixMultCPUPA512_iS0_S0_i
.globl _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixMultPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.globl _Z10matrixMultPiS_S_i
.type _Z10matrixMultPiS_S_i, @function
_Z10matrixMultPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10matrixMultPiS_S_i, .-_Z10matrixMultPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "GPU Time for %i additions: %f\n"
.align 8
.LC2:
.string "CPU Time for %i additions: %f\n"
.align 8
.LC3:
.string "Results do not match! %i, %i, c=%i, g=%i\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -4194304(%rsp), %r11
.cfi_def_cfa 11, 4194344
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $104, %rsp
.cfi_def_cfa_offset 4194448
movq %fs:40, %rax
movq %rax, 4194392(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %r8
leaq 1048656(%rsp), %rdi
movl $0, %esi
movl $0, %ecx
.L24:
movl $0, %eax
.L25:
leal (%rsi,%rax), %edx
movl %edx, (%r8,%rax,4)
leal (%rcx,%rax), %edx
movl %edx, (%rdi,%rax,4)
addq $1, %rax
cmpq $512, %rax
jne .L25
addl $1, %ecx
addl $512, %esi
addq $2048, %r8
addq $2048, %rdi
cmpl $512, %ecx
jne .L24
movq %rsp, %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $1048576, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 1048656(%rsp), %rsi
movl $1, %ecx
movl $1048576, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $32, 36(%rsp)
movl $32, 40(%rsp)
movl $1, 44(%rsp)
movl $16, 24(%rsp)
movl $16, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L27:
call cudaDeviceSynchronize@PLT
leaq 3145808(%rsp), %rbx
movl $2, %ecx
movl $1048576, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %r12
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
leaq 48(%rsp), %r13
movq %r12, %rsi
movq %r13, %rdi
call _Z10myDiffTimeR7timevalS0_
movl $512, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq %r13, %rdi
call gettimeofday@PLT
leaq 2097232(%rsp), %rbp
leaq 1048656(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $512, %ecx
movq %rbp, %rdx
call _Z13matrixMultCPUPA512_iS0_S0_i
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
movq %r12, %rsi
movq %r13, %rdi
call _Z10myDiffTimeR7timevalS0_
movl $512, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rcx
movq %rbx, %rdx
movl $0, %esi
jmp .L28
.L36:
movl $512, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
jmp .L27
.L37:
movl %eax, %ecx
movl %esi, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
addl $1, %esi
addq $2048, %rcx
addq $2048, %rdx
cmpl $512, %esi
je .L31
.L28:
movl $0, %eax
.L30:
movl (%rcx,%rax,4), %r8d
movl (%rdx,%rax,4), %r9d
cmpl %r9d, %r8d
jne .L37
addq $1, %rax
cmpq $512, %rax
jne .L30
jmp .L38
.L31:
movq 4194392(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $4194408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z10matrixMultPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixMultPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "m_multTile.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10myDiffTimeR7timevalS0_
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z10myDiffTimeR7timevalS0_
.p2align 4, 0x90
.type _Z10myDiffTimeR7timevalS0_,@function
_Z10myDiffTimeR7timevalS0_: # @_Z10myDiffTimeR7timevalS0_
.cfi_startproc
# %bb.0:
cvtsi2sdq (%rdi), %xmm0
cvtsi2sdq 8(%rdi), %xmm1
movsd .LCPI0_0(%rip), %xmm2 # xmm2 = mem[0],zero
divsd %xmm2, %xmm1
addsd %xmm0, %xmm1
cvtsi2sdq (%rsi), %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsi), %xmm0
divsd %xmm2, %xmm0
addsd %xmm3, %xmm0
subsd %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z10myDiffTimeR7timevalS0_, .Lfunc_end0-_Z10myDiffTimeR7timevalS0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $4194424, %rsp # imm = 0x400078
.cfi_def_cfa_offset 4194464
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # %.preheader47
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl $512, %edx # imm = 0x200
movq %rax, %rsi
movl %ecx, %edi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %esi, 3145840(%rsp,%rsi,4)
movl %edi, 2097264(%rsp,%rsi,4)
incl %edi
incq %rsi
decq %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $512, %rax # imm = 0x200
cmpq $512, %rcx # imm = 0x200
jne .LBB1_1
# %bb.4:
leaq 40(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %rdi
leaq 3145840(%rsp), %rbx
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
leaq 2097264(%rsp), %r15
movl $1048576, %edx # imm = 0x100000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $137438953504, %rdi # imm = 0x2000000020
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $512, 52(%rsp) # imm = 0x200
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 1048688(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 1048688(%rsp), %rsi
movl 1048696(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10matrixMultPiS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
leaq 1048688(%rsp), %r14
movl $1048576, %edx # imm = 0x100000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 56(%rsp), %xmm1
cvtsi2sdq 64(%rsp), %xmm2
movsd .LCPI1_0(%rip), %xmm4 # xmm4 = mem[0],zero
divsd %xmm4, %xmm2
cvtsi2sdq 8(%rsp), %xmm3
cvtsi2sdq 16(%rsp), %xmm0
addsd %xmm1, %xmm2
divsd %xmm4, %xmm0
addsd %xmm3, %xmm0
subsd %xmm2, %xmm0
movl $.L.str, %edi
movl $512, %esi # imm = 0x200
movb $1, %al
callq printf
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
.p2align 4, 0x90
.LBB1_7: # %.preheader25.i
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
# Child Loop BB1_9 Depth 3
movq %r12, %rax
shlq $11, %rax
addq %rsp, %rax
addq $112, %rax
movq %r15, %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_8: # %.preheader.i
# Parent Loop BB1_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_9 Depth 3
xorl %esi, %esi
movq %rcx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_9: # Parent Loop BB1_7 Depth=1
# Parent Loop BB1_8 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rdi), %r9d
imull (%rbx,%rsi,4), %r9d
addl %r9d, %r8d
incq %rsi
addq $2048, %rdi # imm = 0x800
cmpq $512, %rsi # imm = 0x200
jne .LBB1_9
# %bb.10: # %._crit_edge.i
# in Loop: Header=BB1_8 Depth=2
movl %r8d, (%rax,%rdx,4)
incq %rdx
addq $4, %rcx
cmpq $512, %rdx # imm = 0x200
jne .LBB1_8
# %bb.11: # %._crit_edge29.i
# in Loop: Header=BB1_7 Depth=1
incq %r12
addq $2048, %rbx # imm = 0x800
cmpq $512, %r12 # imm = 0x200
jne .LBB1_7
# %bb.12: # %_Z13matrixMultCPUPA512_iS0_S0_i.exit
xorl %ebx, %ebx
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 56(%rsp), %xmm1
xorps %xmm2, %xmm2
cvtsi2sdq 64(%rsp), %xmm2
movsd .LCPI1_0(%rip), %xmm4 # xmm4 = mem[0],zero
divsd %xmm4, %xmm2
xorps %xmm3, %xmm3
cvtsi2sdq 8(%rsp), %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
addsd %xmm1, %xmm2
divsd %xmm4, %xmm0
addsd %xmm3, %xmm0
subsd %xmm2, %xmm0
movl $.L.str.1, %edi
movl $512, %esi # imm = 0x200
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
leaq 112(%rsp), %rax
.p2align 4, 0x90
.LBB1_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_14 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_14: # Parent Loop BB1_13 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rax,%rdx,4), %ecx
movl (%r14,%rdx,4), %r8d
cmpl %r8d, %ecx
jne .LBB1_18
# %bb.15: # in Loop: Header=BB1_14 Depth=2
incq %rdx
cmpq $512, %rdx # imm = 0x200
jne .LBB1_14
# %bb.16: # in Loop: Header=BB1_13 Depth=1
incq %rbx
addq $2048, %rax # imm = 0x800
addq $2048, %r14 # imm = 0x800
cmpq $512, %rbx # imm = 0x200
jne .LBB1_13
# %bb.17:
xorl %eax, %eax
addq $4194424, %rsp # imm = 0x400078
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 4194464
movl $.L.str.2, %edi
movl %ebx, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matrixMultPiS_S_i # -- Begin function _Z25__device_stub__matrixMultPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixMultPiS_S_i,@function
_Z25__device_stub__matrixMultPiS_S_i: # @_Z25__device_stub__matrixMultPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixMultPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__matrixMultPiS_S_i, .Lfunc_end2-_Z25__device_stub__matrixMultPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13matrixMultCPUPA512_iS0_S0_i # -- Begin function _Z13matrixMultCPUPA512_iS0_S0_i
.p2align 4, 0x90
.type _Z13matrixMultCPUPA512_iS0_S0_i,@function
_Z13matrixMultCPUPA512_iS0_S0_i: # @_Z13matrixMultCPUPA512_iS0_S0_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB3_8
# %bb.1: # %.preheader25.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.preheader25
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
# Child Loop BB3_4 Depth 3
movq %rcx, %r8
shlq $11, %r8
addq %rdx, %r8
movq %rsi, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_3: # %.preheader
# Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
xorl %r11d, %r11d
movq %r9, %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# Parent Loop BB3_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rbx), %r14d
imull (%rdi,%r11,4), %r14d
addl %r14d, %ebp
incq %r11
addq $2048, %rbx # imm = 0x800
cmpq %r11, %rax
jne .LBB3_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB3_3 Depth=2
movl %ebp, (%r8,%r10,4)
incq %r10
addq $4, %r9
cmpq %rax, %r10
jne .LBB3_3
# %bb.6: # %._crit_edge29
# in Loop: Header=BB3_2 Depth=1
incq %rcx
addq $2048, %rdi # imm = 0x800
cmpq %rax, %rcx
jne .LBB3_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %rbp
.LBB3_8: # %._crit_edge31
retq
.Lfunc_end3:
.size _Z13matrixMultCPUPA512_iS0_S0_i, .Lfunc_end3-_Z13matrixMultCPUPA512_iS0_S0_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixMultPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixMultPiS_S_i,@object # @_Z10matrixMultPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10matrixMultPiS_S_i
.p2align 3, 0x0
_Z10matrixMultPiS_S_i:
.quad _Z25__device_stub__matrixMultPiS_S_i
.size _Z10matrixMultPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU Time for %i additions: %f\n"
.size .L.str, 31
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU Time for %i additions: %f\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Results do not match! %i, %i, c=%i, g=%i\n"
.size .L.str.2, 42
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixMultPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixMultPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixMultPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>
#define N 10000
__global__ void add(int *d_a, int *d_b, int *d_c){
d_c[blockIdx.x] = d_a[blockIdx.x] + d_b[blockIdx.x];
}
int main(){
int *a, *b, *c, *gold_c;
int *d_a, *d_b, *d_c;
int i;
int pass = 1;
a = (int*)malloc(N*sizeof(int));
b = (int*)malloc(N*sizeof(int));
c = (int*)malloc(N*sizeof(int));
gold_c = (int*)malloc(N*sizeof(int));
for(i=0; i<N; i++){
a[i] = rand()%100;
b[i] = rand()%100;
}
struct timespec t_start, t_end;
double elapsedTimeCPU;
// start time
clock_gettime( CLOCK_REALTIME, &t_start);
for(i=0; i<N; i++){
gold_c[i] = a[i] + b[i];
}
// stop time
clock_gettime( CLOCK_REALTIME, &t_end);
// compute and print the elapsed time in millisec
elapsedTimeCPU = (t_end.tv_sec - t_start.tv_sec) * 1000.0;
elapsedTimeCPU += (t_end.tv_nsec - t_start.tv_nsec) / 1000000.0;
printf("CPU elapsedTime: %lf ms\n", elapsedTimeCPU);
cudaMalloc((void**)&d_a, N * sizeof(int));
cudaMalloc((void**)&d_b, N * sizeof(int));
cudaMalloc((void**)&d_c, N * sizeof(int));
cudaMemcpy(d_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
// Get start time event
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
add<<<N, 1>>>(d_a, d_b, d_c);
// Get stop time event
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Compute execution time
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("GPU time: %13f msec\n", elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(c, d_c, N*sizeof(int), cudaMemcpyDeviceToHost);
for(i=0; i<N; i++){
if(gold_c[i]!=c[i]){
pass = 0;
break;
}
}
if(pass==1)
printf("test pass!\n");
else
printf("error...\n");
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>
#define N 10000
__global__ void add(int *d_a, int *d_b, int *d_c){
d_c[blockIdx.x] = d_a[blockIdx.x] + d_b[blockIdx.x];
}
int main(){
int *a, *b, *c, *gold_c;
int *d_a, *d_b, *d_c;
int i;
int pass = 1;
a = (int*)malloc(N*sizeof(int));
b = (int*)malloc(N*sizeof(int));
c = (int*)malloc(N*sizeof(int));
gold_c = (int*)malloc(N*sizeof(int));
for(i=0; i<N; i++){
a[i] = rand()%100;
b[i] = rand()%100;
}
struct timespec t_start, t_end;
double elapsedTimeCPU;
// start time
clock_gettime( CLOCK_REALTIME, &t_start);
for(i=0; i<N; i++){
gold_c[i] = a[i] + b[i];
}
// stop time
clock_gettime( CLOCK_REALTIME, &t_end);
// compute and print the elapsed time in millisec
elapsedTimeCPU = (t_end.tv_sec - t_start.tv_sec) * 1000.0;
elapsedTimeCPU += (t_end.tv_nsec - t_start.tv_nsec) / 1000000.0;
printf("CPU elapsedTime: %lf ms\n", elapsedTimeCPU);
cudaMalloc((void**)&d_a, N * sizeof(int));
cudaMalloc((void**)&d_b, N * sizeof(int));
cudaMalloc((void**)&d_c, N * sizeof(int));
cudaMemcpy(d_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
// Get start time event
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
add<<<N, 1>>>(d_a, d_b, d_c);
// Get stop time event
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Compute execution time
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("GPU time: %13f msec\n", elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(c, d_c, N*sizeof(int), cudaMemcpyDeviceToHost);
for(i=0; i<N; i++){
if(gold_c[i]!=c[i]){
pass = 0;
break;
}
}
if(pass==1)
printf("test pass!\n");
else
printf("error...\n");
return 0;
} | .file "tmpxft_0018523d_00000000-6_cuda2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CPU elapsedTime:\302\240%lf ms\n"
.LC3:
.string "GPU time: %13f msec\n"
.LC4:
.string "test pass!\n"
.LC5:
.string "error...\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $40000, %edi
call malloc@PLT
movq %rax, %r12
movl $40000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000, %edi
call malloc@PLT
movq %rax, %r14
movl $40000, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $40000, %rbx
jne .L12
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $0, %eax
.L13:
movl 0(%rbp,%rax), %edx
addl (%r12,%rax), %edx
movl %edx, 0(%r13,%rax)
addq $4, %rax
cmpq $40000, %rax
jne .L13
leaq 80(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC0(%rip), %xmm1
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
addsd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $10000, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L14:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $40000, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %eax
.L16:
movl (%r14,%rax), %esi
cmpl %esi, 0(%r13,%rax)
jne .L15
addq $4, %rax
cmpq $40000, %rax
jne .L16
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L26:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L14
.L15:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L18:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>
#define N 10000
__global__ void add(int *d_a, int *d_b, int *d_c){
d_c[blockIdx.x] = d_a[blockIdx.x] + d_b[blockIdx.x];
}
int main(){
int *a, *b, *c, *gold_c;
int *d_a, *d_b, *d_c;
int i;
int pass = 1;
a = (int*)malloc(N*sizeof(int));
b = (int*)malloc(N*sizeof(int));
c = (int*)malloc(N*sizeof(int));
gold_c = (int*)malloc(N*sizeof(int));
for(i=0; i<N; i++){
a[i] = rand()%100;
b[i] = rand()%100;
}
struct timespec t_start, t_end;
double elapsedTimeCPU;
// start time
clock_gettime( CLOCK_REALTIME, &t_start);
for(i=0; i<N; i++){
gold_c[i] = a[i] + b[i];
}
// stop time
clock_gettime( CLOCK_REALTIME, &t_end);
// compute and print the elapsed time in millisec
elapsedTimeCPU = (t_end.tv_sec - t_start.tv_sec) * 1000.0;
elapsedTimeCPU += (t_end.tv_nsec - t_start.tv_nsec) / 1000000.0;
printf("CPU elapsedTime: %lf ms\n", elapsedTimeCPU);
cudaMalloc((void**)&d_a, N * sizeof(int));
cudaMalloc((void**)&d_b, N * sizeof(int));
cudaMalloc((void**)&d_c, N * sizeof(int));
cudaMemcpy(d_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
// Get start time event
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
add<<<N, 1>>>(d_a, d_b, d_c);
// Get stop time event
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Compute execution time
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("GPU time: %13f msec\n", elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(c, d_c, N*sizeof(int), cudaMemcpyDeviceToHost);
for(i=0; i<N; i++){
if(gold_c[i]!=c[i]){
pass = 0;
break;
}
}
if(pass==1)
printf("test pass!\n");
else
printf("error...\n");
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define N 10000
__global__ void add(int *d_a, int *d_b, int *d_c){
d_c[blockIdx.x] = d_a[blockIdx.x] + d_b[blockIdx.x];
}
int main(){
int *a, *b, *c, *gold_c;
int *d_a, *d_b, *d_c;
int i;
int pass = 1;
a = (int*)malloc(N*sizeof(int));
b = (int*)malloc(N*sizeof(int));
c = (int*)malloc(N*sizeof(int));
gold_c = (int*)malloc(N*sizeof(int));
for(i=0; i<N; i++){
a[i] = rand()%100;
b[i] = rand()%100;
}
struct timespec t_start, t_end;
double elapsedTimeCPU;
// start time
clock_gettime( CLOCK_REALTIME, &t_start);
for(i=0; i<N; i++){
gold_c[i] = a[i] + b[i];
}
// stop time
clock_gettime( CLOCK_REALTIME, &t_end);
// compute and print the elapsed time in millisec
elapsedTimeCPU = (t_end.tv_sec - t_start.tv_sec) * 1000.0;
elapsedTimeCPU += (t_end.tv_nsec - t_start.tv_nsec) / 1000000.0;
printf("CPU elapsedTime: %lf ms\n", elapsedTimeCPU);
hipMalloc((void**)&d_a, N * sizeof(int));
hipMalloc((void**)&d_b, N * sizeof(int));
hipMalloc((void**)&d_c, N * sizeof(int));
hipMemcpy(d_a, a, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, N*sizeof(int), hipMemcpyHostToDevice);
// Get start time event
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
add<<<N, 1>>>(d_a, d_b, d_c);
// Get stop time event
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Compute execution time
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("GPU time: %13f msec\n", elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(c, d_c, N*sizeof(int), hipMemcpyDeviceToHost);
for(i=0; i<N; i++){
if(gold_c[i]!=c[i]){
pass = 0;
break;
}
}
if(pass==1)
printf("test pass!\n");
else
printf("error...\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define N 10000
__global__ void add(int *d_a, int *d_b, int *d_c){
d_c[blockIdx.x] = d_a[blockIdx.x] + d_b[blockIdx.x];
}
int main(){
int *a, *b, *c, *gold_c;
int *d_a, *d_b, *d_c;
int i;
int pass = 1;
a = (int*)malloc(N*sizeof(int));
b = (int*)malloc(N*sizeof(int));
c = (int*)malloc(N*sizeof(int));
gold_c = (int*)malloc(N*sizeof(int));
for(i=0; i<N; i++){
a[i] = rand()%100;
b[i] = rand()%100;
}
struct timespec t_start, t_end;
double elapsedTimeCPU;
// start time
clock_gettime( CLOCK_REALTIME, &t_start);
for(i=0; i<N; i++){
gold_c[i] = a[i] + b[i];
}
// stop time
clock_gettime( CLOCK_REALTIME, &t_end);
// compute and print the elapsed time in millisec
elapsedTimeCPU = (t_end.tv_sec - t_start.tv_sec) * 1000.0;
elapsedTimeCPU += (t_end.tv_nsec - t_start.tv_nsec) / 1000000.0;
printf("CPU elapsedTime: %lf ms\n", elapsedTimeCPU);
hipMalloc((void**)&d_a, N * sizeof(int));
hipMalloc((void**)&d_b, N * sizeof(int));
hipMalloc((void**)&d_c, N * sizeof(int));
hipMemcpy(d_a, a, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, N*sizeof(int), hipMemcpyHostToDevice);
// Get start time event
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
add<<<N, 1>>>(d_a, d_b, d_c);
// Get stop time event
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Compute execution time
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("GPU time: %13f msec\n", elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(c, d_c, N*sizeof(int), hipMemcpyDeviceToHost);
for(i=0; i<N; i++){
if(gold_c[i]!=c[i]){
pass = 0;
break;
}
}
if(pass==1)
printf("test pass!\n");
else
printf("error...\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define N 10000
__global__ void add(int *d_a, int *d_b, int *d_c){
d_c[blockIdx.x] = d_a[blockIdx.x] + d_b[blockIdx.x];
}
int main(){
int *a, *b, *c, *gold_c;
int *d_a, *d_b, *d_c;
int i;
int pass = 1;
a = (int*)malloc(N*sizeof(int));
b = (int*)malloc(N*sizeof(int));
c = (int*)malloc(N*sizeof(int));
gold_c = (int*)malloc(N*sizeof(int));
for(i=0; i<N; i++){
a[i] = rand()%100;
b[i] = rand()%100;
}
struct timespec t_start, t_end;
double elapsedTimeCPU;
// start time
clock_gettime( CLOCK_REALTIME, &t_start);
for(i=0; i<N; i++){
gold_c[i] = a[i] + b[i];
}
// stop time
clock_gettime( CLOCK_REALTIME, &t_end);
// compute and print the elapsed time in millisec
elapsedTimeCPU = (t_end.tv_sec - t_start.tv_sec) * 1000.0;
elapsedTimeCPU += (t_end.tv_nsec - t_start.tv_nsec) / 1000000.0;
printf("CPU elapsedTime: %lf ms\n", elapsedTimeCPU);
hipMalloc((void**)&d_a, N * sizeof(int));
hipMalloc((void**)&d_b, N * sizeof(int));
hipMalloc((void**)&d_c, N * sizeof(int));
hipMemcpy(d_a, a, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, N*sizeof(int), hipMemcpyHostToDevice);
// Get start time event
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
add<<<N, 1>>>(d_a, d_b, d_c);
// Get stop time event
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Compute execution time
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("GPU time: %13f msec\n", elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(c, d_c, N*sizeof(int), hipMemcpyDeviceToHost);
for(i=0; i<N; i++){
if(gold_c[i]!=c[i]){
pass = 0;
break;
}
}
if(pass==1)
printf("test pass!\n");
else
printf("error...\n");
return 0;
} | .text
.file "cuda2.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r12
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r15
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %rbx
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r12,%r13,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r15,%r13,4)
incq %r13
cmpq $10000, %r13 # imm = 0x2710
jne .LBB1_1
# %bb.2:
xorl %r13d, %r13d
leaq 160(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %eax
addl (%r12,%r13,4), %eax
movl %eax, (%r14,%r13,4)
incq %r13
cmpq $10000, %r13 # imm = 0x2710
jne .LBB1_3
# %bb.4:
leaq 144(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 144(%rsp), %rax
movq 152(%rsp), %rcx
subq 160(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
subq 168(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI1_1(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
leaq 40(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 32(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq 40(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9999(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %eax
cmpl (%rbx,%r15,4), %eax
jne .LBB1_10
# %bb.8: # in Loop: Header=BB1_7 Depth=1
incq %r15
cmpq $10000, %r15 # imm = 0x2710
jne .LBB1_7
# %bb.9:
movl $.Lstr.1, %edi
jmp .LBB1_11
.LBB1_10:
movl $.Lstr, %edi
.LBB1_11: # %.critedge
callq puts@PLT
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU elapsedTime:\302\240%lf ms\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU time: %13f msec\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "error..."
.size .Lstr, 9
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "test pass!"
.size .Lstr.1, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018523d_00000000-6_cuda2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CPU elapsedTime:\302\240%lf ms\n"
.LC3:
.string "GPU time: %13f msec\n"
.LC4:
.string "test pass!\n"
.LC5:
.string "error...\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $40000, %edi
call malloc@PLT
movq %rax, %r12
movl $40000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000, %edi
call malloc@PLT
movq %rax, %r14
movl $40000, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $40000, %rbx
jne .L12
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $0, %eax
.L13:
movl 0(%rbp,%rax), %edx
addl (%r12,%rax), %edx
movl %edx, 0(%r13,%rax)
addq $4, %rax
cmpq $40000, %rax
jne .L13
leaq 80(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC0(%rip), %xmm1
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
addsd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $10000, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L14:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $40000, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %eax
.L16:
movl (%r14,%rax), %esi
cmpl %esi, 0(%r13,%rax)
jne .L15
addq $4, %rax
cmpq $40000, %rax
jne .L16
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L26:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L14
.L15:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L18:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda2.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r12
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r15
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %rbx
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r12,%r13,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r15,%r13,4)
incq %r13
cmpq $10000, %r13 # imm = 0x2710
jne .LBB1_1
# %bb.2:
xorl %r13d, %r13d
leaq 160(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %eax
addl (%r12,%r13,4), %eax
movl %eax, (%r14,%r13,4)
incq %r13
cmpq $10000, %r13 # imm = 0x2710
jne .LBB1_3
# %bb.4:
leaq 144(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 144(%rsp), %rax
movq 152(%rsp), %rcx
subq 160(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
subq 168(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI1_1(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
leaq 40(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 32(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq 40(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9999(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %eax
cmpl (%rbx,%r15,4), %eax
jne .LBB1_10
# %bb.8: # in Loop: Header=BB1_7 Depth=1
incq %r15
cmpq $10000, %r15 # imm = 0x2710
jne .LBB1_7
# %bb.9:
movl $.Lstr.1, %edi
jmp .LBB1_11
.LBB1_10:
movl $.Lstr, %edi
.LBB1_11: # %.critedge
callq puts@PLT
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU elapsedTime:\302\240%lf ms\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU time: %13f msec\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "error..."
.size .Lstr, 9
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "test pass!"
.size .Lstr.1, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// customDllFunctions.cu
//////////////////////////
// Template to write .dlls
//////////////////////////
/* Include the following directories for the program to run appropriately:
///////////////////////
in the VC++ directories:
$(VC_IncludePath);
$(WindowsSDK_IncludePath);
C:\ProgramData\NVIDIA Corporation\CUDA Samples\v9.0\common\inc;
$(CUDA_INC_PATH)
C:\Program Files\National Instruments\LabVIEW 2015\cintools
////////////////////////
CUDA/C/C++ directories:
./
../../common/inc
$(CudaToolkitDir)/include
////////////////////////////////
Linker/General include libraries:
cudart.lib
//changed the target machine platform from 32 to 64 bit
*/
////////////////////////////////////////////////////////////////////////////////
// Complex operations,
////////////////////////////////////////////////////////////////////////////////
__device__ static __inline__ float cmagf(float x, float y)
{
float a, b, v, w, t;
a = fabsf(x);
b = fabsf(y);
if (a > b) {
v = a;
w = b;
}
else {
v = b;
w = a;
}
t = w / v;
t = 1.0f + t * t;
t = v * sqrtf(t);
if ((v == 0.0f) || (v > 3.402823466e38f) || (w > 3.402823466e38f)) {
t = v + w;
}
return t;
}
__global__ void ConvertCmplx2Polar(float* inRe, float* inIm, float* mag, float* phase, int size) {
const int numThreads = blockDim.x * gridDim.x;
const int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = threadID; i < size; i += numThreads)
{
phase[i] = atan2f(inIm[i], inRe[i]);
mag[i] = cmagf(inIm[i], inRe[i]);
}
} | .file "tmpxft_000b0948_00000000-6_ConvertCmplx2Polar.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z18ConvertCmplx2PolarPfS_S_S_iPfS_S_S_i
.type _Z45__device_stub__Z18ConvertCmplx2PolarPfS_S_S_iPfS_S_S_i, @function
_Z45__device_stub__Z18ConvertCmplx2PolarPfS_S_S_iPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18ConvertCmplx2PolarPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z45__device_stub__Z18ConvertCmplx2PolarPfS_S_S_iPfS_S_S_i, .-_Z45__device_stub__Z18ConvertCmplx2PolarPfS_S_S_iPfS_S_S_i
.globl _Z18ConvertCmplx2PolarPfS_S_S_i
.type _Z18ConvertCmplx2PolarPfS_S_S_i, @function
_Z18ConvertCmplx2PolarPfS_S_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18ConvertCmplx2PolarPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18ConvertCmplx2PolarPfS_S_S_i, .-_Z18ConvertCmplx2PolarPfS_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18ConvertCmplx2PolarPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18ConvertCmplx2PolarPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// customDllFunctions.cu
//////////////////////////
// Template to write .dlls
//////////////////////////
/* Include the following directories for the program to run appropriately:
///////////////////////
in the VC++ directories:
$(VC_IncludePath);
$(WindowsSDK_IncludePath);
C:\ProgramData\NVIDIA Corporation\CUDA Samples\v9.0\common\inc;
$(CUDA_INC_PATH)
C:\Program Files\National Instruments\LabVIEW 2015\cintools
////////////////////////
CUDA/C/C++ directories:
./
../../common/inc
$(CudaToolkitDir)/include
////////////////////////////////
Linker/General include libraries:
cudart.lib
//changed the target machine platform from 32 to 64 bit
*/
////////////////////////////////////////////////////////////////////////////////
// Complex operations,
////////////////////////////////////////////////////////////////////////////////
__device__ static __inline__ float cmagf(float x, float y)
{
float a, b, v, w, t;
a = fabsf(x);
b = fabsf(y);
if (a > b) {
v = a;
w = b;
}
else {
v = b;
w = a;
}
t = w / v;
t = 1.0f + t * t;
t = v * sqrtf(t);
if ((v == 0.0f) || (v > 3.402823466e38f) || (w > 3.402823466e38f)) {
t = v + w;
}
return t;
}
__global__ void ConvertCmplx2Polar(float* inRe, float* inIm, float* mag, float* phase, int size) {
const int numThreads = blockDim.x * gridDim.x;
const int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = threadID; i < size; i += numThreads)
{
phase[i] = atan2f(inIm[i], inRe[i]);
mag[i] = cmagf(inIm[i], inRe[i]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// customDllFunctions.cu
//////////////////////////
// Template to write .dlls
//////////////////////////
/* Include the following directories for the program to run appropriately:
///////////////////////
in the VC++ directories:
$(VC_IncludePath);
$(WindowsSDK_IncludePath);
C:\ProgramData\NVIDIA Corporation\CUDA Samples\v9.0\common\inc;
$(CUDA_INC_PATH)
C:\Program Files\National Instruments\LabVIEW 2015\cintools
////////////////////////
CUDA/C/C++ directories:
./
../../common/inc
$(CudaToolkitDir)/include
////////////////////////////////
Linker/General include libraries:
cudart.lib
//changed the target machine platform from 32 to 64 bit
*/
////////////////////////////////////////////////////////////////////////////////
// Complex operations,
////////////////////////////////////////////////////////////////////////////////
__device__ static __inline__ float cmagf(float x, float y)
{
float a, b, v, w, t;
a = fabsf(x);
b = fabsf(y);
if (a > b) {
v = a;
w = b;
}
else {
v = b;
w = a;
}
t = w / v;
t = 1.0f + t * t;
t = v * sqrtf(t);
if ((v == 0.0f) || (v > 3.402823466e38f) || (w > 3.402823466e38f)) {
t = v + w;
}
return t;
}
__global__ void ConvertCmplx2Polar(float* inRe, float* inIm, float* mag, float* phase, int size) {
const int numThreads = blockDim.x * gridDim.x;
const int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = threadID; i < size; i += numThreads)
{
phase[i] = atan2f(inIm[i], inRe[i]);
mag[i] = cmagf(inIm[i], inRe[i]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// customDllFunctions.cu
//////////////////////////
// Template to write .dlls
//////////////////////////
/* Include the following directories for the program to run appropriately:
///////////////////////
in the VC++ directories:
$(VC_IncludePath);
$(WindowsSDK_IncludePath);
C:\ProgramData\NVIDIA Corporation\CUDA Samples\v9.0\common\inc;
$(CUDA_INC_PATH)
C:\Program Files\National Instruments\LabVIEW 2015\cintools
////////////////////////
CUDA/C/C++ directories:
./
../../common/inc
$(CudaToolkitDir)/include
////////////////////////////////
Linker/General include libraries:
cudart.lib
//changed the target machine platform from 32 to 64 bit
*/
////////////////////////////////////////////////////////////////////////////////
// Complex operations,
////////////////////////////////////////////////////////////////////////////////
__device__ static __inline__ float cmagf(float x, float y)
{
float a, b, v, w, t;
a = fabsf(x);
b = fabsf(y);
if (a > b) {
v = a;
w = b;
}
else {
v = b;
w = a;
}
t = w / v;
t = 1.0f + t * t;
t = v * sqrtf(t);
if ((v == 0.0f) || (v > 3.402823466e38f) || (w > 3.402823466e38f)) {
t = v + w;
}
return t;
}
__global__ void ConvertCmplx2Polar(float* inRe, float* inIm, float* mag, float* phase, int size) {
const int numThreads = blockDim.x * gridDim.x;
const int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = threadID; i < size; i += numThreads)
{
phase[i] = atan2f(inIm[i], inRe[i]);
mag[i] = cmagf(inIm[i], inRe[i]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18ConvertCmplx2PolarPfS_S_S_i
.globl _Z18ConvertCmplx2PolarPfS_S_S_i
.p2align 8
.type _Z18ConvertCmplx2PolarPfS_S_S_i,@function
_Z18ConvertCmplx2PolarPfS_S_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s16, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s16, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0x4016cbe4
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s2, s12
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[14:15], s[12:13], 2
s_mov_b32 s13, 0x3b2d2a58
.LBB0_2:
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
global_load_b32 v10, v[4:5], off
global_load_b32 v9, v[6:7], off
v_add_nc_u32_e32 v1, s12, v1
s_waitcnt vmcnt(1)
v_max_f32_e64 v8, |v10|, |v10|
s_waitcnt vmcnt(0)
v_max_f32_e64 v11, |v9|, |v9|
v_cmp_gt_i32_e64 s0, 0, v9
v_cmp_class_f32_e64 s1, v9, 0x204
v_cmp_class_f32_e64 s2, v10, 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_max_f32_e32 v12, v11, v8
v_min_f32_e32 v8, v11, v8
v_frexp_mant_f32_e32 v11, v12
v_frexp_exp_i32_f32_e32 v12, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_frexp_exp_i32_f32_e32 v13, v8
v_frexp_mant_f32_e32 v8, v8
v_rcp_f32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v12, v13, v12
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v8, v8, v11
v_ldexp_f32 v11, v8, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, v11, v11
v_fmaak_f32 v8, s13, v12, 0xbc7a590c
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v8, v12, v8, 0x3d29fb3f
v_fmaak_f32 v8, v12, v8, 0xbd97d4d7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v8, v12, v8, 0x3dd931b2
v_fmaak_f32 v8, v12, v8, 0xbe1160e6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmaak_f32 v13, v12, v8, 0x3e4cb8bf
v_add_co_u32 v8, vcc_lo, s10, v2
v_fmaak_f32 v13, v12, v13, 0xbeaaaa62
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f32_e32 v12, v12, v13
v_cndmask_b32_e64 v13, 0, 0x40490fdb, s0
v_cmp_gt_f32_e64 s0, |v10|, |v9|
v_fmac_f32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, 0x3fc90fdb, v11
v_cndmask_b32_e64 v11, v11, v12, s0
v_cmp_gt_f32_e64 s0, 0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, 0x40490fdb, v11
v_cndmask_b32_e64 v11, v11, v12, s0
v_cndmask_b32_e64 v12, 0x3f490fdb, v0, s0
v_cmp_eq_f32_e64 s0, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v11, v11, v13, s0
s_and_b32 s0, s2, s1
v_cmp_le_i32_e64 s2, s16, v1
v_cndmask_b32_e64 v11, v11, v12, s0
v_cmp_o_f32_e64 s0, v9, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v11, 0x7fc00000, v11, s0
v_bfi_b32 v10, 0x7fffffff, v11, v10
global_store_b32 v[8:9], v10, off
global_load_b32 v8, v[4:5], off
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e64 s0, |v8|, |v6|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v7, |v6|, |v8|, s0
v_cndmask_b32_e64 v9, |v8|, |v6|, s0
v_add_f32_e64 v6, |v8|, |v6|
v_div_scale_f32 v4, null, v7, v7, v9
v_div_scale_f32 v11, vcc_lo, v9, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v4, v5, 1.0
v_fmac_f32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v11, v5
v_fma_f32 v12, -v4, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v12, v5
v_fma_f32 v4, -v4, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v10
v_div_fixup_f32 v4, v4, v7, v9
v_max_f32_e32 v9, v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v4, v4, 1.0
v_mul_f32_e32 v5, 0x4f800000, v4
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v10, v4, v5, vcc_lo
v_sqrt_f32_e32 v4, v10
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v11, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v5, v4, v10
v_fma_f32 v13, -v11, v4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v12
v_cndmask_b32_e64 v4, v4, v5, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s0, 0, v13
v_max_f32_e32 v13, v7, v7
v_cndmask_b32_e64 v11, v4, v11, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_f32_e32 v9, v13, v9
v_add_co_u32 v4, s0, s8, v2
v_add_co_ci_u32_e64 v5, s0, s9, v3, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v12, 0x37800000, v11
v_cmp_lt_f32_e64 s0, 0x7f7fffff, v9
v_add_co_u32 v2, s1, v2, s14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v11, v11, v12, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v10, 0x260
v_cndmask_b32_e32 v10, v11, v10, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v7, v7, v10
s_or_b32 vcc_lo, s0, vcc_lo
s_or_b32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
v_add_co_ci_u32_e64 v3, vcc_lo, s15, v3, s1
global_store_b32 v[4:5], v6, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18ConvertCmplx2PolarPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18ConvertCmplx2PolarPfS_S_S_i, .Lfunc_end0-_Z18ConvertCmplx2PolarPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18ConvertCmplx2PolarPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z18ConvertCmplx2PolarPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// customDllFunctions.cu
//////////////////////////
// Template to write .dlls
//////////////////////////
/* Include the following directories for the program to run appropriately:
///////////////////////
in the VC++ directories:
$(VC_IncludePath);
$(WindowsSDK_IncludePath);
C:\ProgramData\NVIDIA Corporation\CUDA Samples\v9.0\common\inc;
$(CUDA_INC_PATH)
C:\Program Files\National Instruments\LabVIEW 2015\cintools
////////////////////////
CUDA/C/C++ directories:
./
../../common/inc
$(CudaToolkitDir)/include
////////////////////////////////
Linker/General include libraries:
cudart.lib
//changed the target machine platform from 32 to 64 bit
*/
////////////////////////////////////////////////////////////////////////////////
// Complex operations,
////////////////////////////////////////////////////////////////////////////////
__device__ static __inline__ float cmagf(float x, float y)
{
float a, b, v, w, t;
a = fabsf(x);
b = fabsf(y);
if (a > b) {
v = a;
w = b;
}
else {
v = b;
w = a;
}
t = w / v;
t = 1.0f + t * t;
t = v * sqrtf(t);
if ((v == 0.0f) || (v > 3.402823466e38f) || (w > 3.402823466e38f)) {
t = v + w;
}
return t;
}
__global__ void ConvertCmplx2Polar(float* inRe, float* inIm, float* mag, float* phase, int size) {
const int numThreads = blockDim.x * gridDim.x;
const int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = threadID; i < size; i += numThreads)
{
phase[i] = atan2f(inIm[i], inRe[i]);
mag[i] = cmagf(inIm[i], inRe[i]);
}
} | .text
.file "ConvertCmplx2Polar.hip"
.globl _Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i # -- Begin function _Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i
.p2align 4, 0x90
.type _Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i,@function
_Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i: # @_Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18ConvertCmplx2PolarPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i, .Lfunc_end0-_Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18ConvertCmplx2PolarPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18ConvertCmplx2PolarPfS_S_S_i,@object # @_Z18ConvertCmplx2PolarPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z18ConvertCmplx2PolarPfS_S_S_i
.p2align 3, 0x0
_Z18ConvertCmplx2PolarPfS_S_S_i:
.quad _Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i
.size _Z18ConvertCmplx2PolarPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18ConvertCmplx2PolarPfS_S_S_i"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18ConvertCmplx2PolarPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b0948_00000000-6_ConvertCmplx2Polar.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z18ConvertCmplx2PolarPfS_S_S_iPfS_S_S_i
.type _Z45__device_stub__Z18ConvertCmplx2PolarPfS_S_S_iPfS_S_S_i, @function
_Z45__device_stub__Z18ConvertCmplx2PolarPfS_S_S_iPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18ConvertCmplx2PolarPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z45__device_stub__Z18ConvertCmplx2PolarPfS_S_S_iPfS_S_S_i, .-_Z45__device_stub__Z18ConvertCmplx2PolarPfS_S_S_iPfS_S_S_i
.globl _Z18ConvertCmplx2PolarPfS_S_S_i
.type _Z18ConvertCmplx2PolarPfS_S_S_i, @function
_Z18ConvertCmplx2PolarPfS_S_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18ConvertCmplx2PolarPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18ConvertCmplx2PolarPfS_S_S_i, .-_Z18ConvertCmplx2PolarPfS_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18ConvertCmplx2PolarPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18ConvertCmplx2PolarPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ConvertCmplx2Polar.hip"
.globl _Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i # -- Begin function _Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i
.p2align 4, 0x90
.type _Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i,@function
_Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i: # @_Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18ConvertCmplx2PolarPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i, .Lfunc_end0-_Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18ConvertCmplx2PolarPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18ConvertCmplx2PolarPfS_S_S_i,@object # @_Z18ConvertCmplx2PolarPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z18ConvertCmplx2PolarPfS_S_S_i
.p2align 3, 0x0
_Z18ConvertCmplx2PolarPfS_S_S_i:
.quad _Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i
.size _Z18ConvertCmplx2PolarPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18ConvertCmplx2PolarPfS_S_S_i"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__ConvertCmplx2PolarPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18ConvertCmplx2PolarPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void convertPitchedFloatToRGBA_kernel(uchar4 *out_image, const float *in_image, int width, int height, int pitch, float lowerLim, float upperLim) {
const int x = __mul24(blockIdx.x, blockDim.x) + threadIdx.x;
const int y = __mul24(blockIdx.y, blockDim.y) + threadIdx.y;
uchar4 temp;
if (x < width && y < height) {
float val = *((float *)((char *)in_image + y * pitch) + x);
// first draw unmatched pixels in white
if (!isfinite(val)) {
temp.x = 255;
temp.y = 255;
temp.z = 255;
temp.w = 255;
} else {
// rescale value from [lowerLim,upperLim] to [0,1]
val -= lowerLim;
val /= (upperLim - lowerLim);
float r = 1.0f;
float g = 1.0f;
float b = 1.0f;
if (val < 0.25f) {
r = 0;
g = 4.0f * val;
} else if (val < 0.5f) {
r = 0;
b = 1.0 + 4.0f * (0.25f - val);
} else if (val < 0.75f) {
r = 4.0f * (val - 0.5f);
b = 0;
} else {
g = 1.0f + 4.0f * (0.75f - val);
b = 0;
}
temp.x = 255.0 * r;
temp.y = 255.0 * g;
temp.z = 255.0 * b;
temp.w = 255;
}
out_image[__mul24(y, width) + x] = temp;
}
} | code for sm_80
Function : _Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000e220000002600 */
/*0020*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff027624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD.SHL.U32 R2, R2, 0x100, RZ ; /* 0x0000010002027824 */
/* 0x000fe400078e00ff */
/*0070*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000ee20000002500 */
/*0080*/ IMAD.SHL.U32 R0, R0, 0x100, RZ ; /* 0x0000010000007824 */
/* 0x000fe400078e00ff */
/*0090*/ SHF.R.S32.HI R3, RZ, 0x8, R2 ; /* 0x00000008ff037819 */
/* 0x000fc60000011402 */
/*00a0*/ SHF.R.S32.HI R2, RZ, 0x8, R0 ; /* 0x00000008ff027819 */
/* 0x000fe20000011400 */
/*00b0*/ USHF.L.U32 UR5, UR5, 0x8, URZ ; /* 0x0000000805057899 */
/* 0x001fc8000800063f */
/*00c0*/ USHF.R.S32.HI UR5, URZ, 0x8, UR5 ; /* 0x000000083f057899 */
/* 0x000fe40008011405 */
/*00d0*/ USHF.L.U32 UR4, UR4, 0x8, URZ ; /* 0x0000000804047899 */
/* 0x008fc8000800063f */
/*00e0*/ IMAD R0, R3, UR5, R4 ; /* 0x0000000503007c24 */
/* 0x002fe2000f8e0204 */
/*00f0*/ USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; /* 0x000000083f047899 */
/* 0x000fc80008011404 */
/*0100*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe40003f06270 */
/*0110*/ IMAD R2, R2, UR4, R5 ; /* 0x0000000402027c24 */
/* 0x004fca000f8e0205 */
/*0120*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fda0000706670 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ IMAD R3, R0, c[0x0][0x178], RZ ; /* 0x00005e0000037a24 */
/* 0x000fe200078e02ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0160*/ IADD3 R4, P0, R3, c[0x0][0x168], RZ ; /* 0x00005a0003047a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ LEA.HI.X.SX32 R5, R3, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0003057a11 */
/* 0x000fca00000f0eff */
/*0180*/ IMAD.WIDE R4, R2, 0x4, R4 ; /* 0x0000000402047825 */
/* 0x000fcc00078e0204 */
/*0190*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ BSSY B0, 0x560 ; /* 0x000003b000007945 */
/* 0x000fe20003800000 */
/*01b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0xff ; /* 0x000000ffff037424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R10, RZ, RZ, 0xff ; /* 0x000000ffff0a7424 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, 0xff ; /* 0x000000ffff0b7424 */
/* 0x000fe200078e00ff */
/*01e0*/ FSETP.GEU.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x004fda0003f0e200 */
/*01f0*/ @P0 BRA 0x550 ; /* 0x0000035000000947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*0210*/ BSSY B1, 0x300 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0220*/ FADD R3, R4, -c[0x0][0x17c] ; /* 0x80005f0004037621 */
/* 0x000fe40000000000 */
/*0230*/ FADD R6, R6, -c[0x0][0x17c] ; /* 0x80005f0006067621 */
/* 0x000fc80000000000 */
/*0240*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x000e300000001000 */
/*0250*/ FCHK P0, R3, R6 ; /* 0x0000000603007302 */
/* 0x000e620000000000 */
/*0260*/ FFMA R8, -R6, R5, 1 ; /* 0x3f80000006087423 */
/* 0x001fc80000000105 */
/*0270*/ FFMA R8, R5, R8, R5 ; /* 0x0000000805087223 */
/* 0x000fc80000000005 */
/*0280*/ FFMA R5, R3, R8, RZ ; /* 0x0000000803057223 */
/* 0x000fc800000000ff */
/*0290*/ FFMA R4, -R6, R5, R3 ; /* 0x0000000506047223 */
/* 0x000fc80000000103 */
/*02a0*/ FFMA R8, R8, R4, R5 ; /* 0x0000000408087223 */
/* 0x000fe20000000005 */
/*02b0*/ @!P0 BRA 0x2f0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*02c0*/ MOV R4, 0x2e0 ; /* 0x000002e000047802 */
/* 0x000fe40000000f00 */
/*02d0*/ CALL.REL.NOINC 0x640 ; /* 0x0000036000007944 */
/* 0x000fea0003c00000 */
/*02e0*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0003 */
/*02f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0300*/ FSETP.GEU.AND P0, PT, R8, 0.25, PT ; /* 0x3e8000000800780b */
/* 0x000fe20003f0e000 */
/*0310*/ BSSY B1, 0x4d0 ; /* 0x000001b000017945 */
/* 0x000fe20003800000 */
/*0320*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fd6000001ff00 */
/*0330*/ @!P0 BRA 0x490 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0340*/ FSETP.GEU.AND P0, PT, R8, 0.5, PT ; /* 0x3f0000000800780b */
/* 0x000fda0003f0e000 */
/*0350*/ @!P0 BRA 0x420 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0360*/ FADD R3, R8.reuse, -0.5 ; /* 0xbf00000008037421 */
/* 0x040fe20000000000 */
/*0370*/ FSETP.GEU.AND P0, PT, R8.reuse, 0.75, PT ; /* 0x3f4000000800780b */
/* 0x040fe20003f0e000 */
/*0380*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff077424 */
/* 0x000fe400078e00ff */
/*0390*/ FMUL R3, R3, 4 ; /* 0x4080000003037820 */
/* 0x000fe40000400000 */
/*03a0*/ FADD R8, -R8, 0.75 ; /* 0x3f40000008087421 */
/* 0x000fc60000000100 */
/*03b0*/ FSEL R3, R3, 1, !P0 ; /* 0x3f80000003037808 */
/* 0x000fe20004000000 */
/*03c0*/ FFMA R8, R8, 4, R7 ; /* 0x4080000008087823 */
/* 0x000fe40000000007 */
/*03d0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*03e0*/ F2F.F64.F32 R4, R3 ; /* 0x0000000300047310 */
/* 0x000e240000201800 */
/*03f0*/ FSEL R12, R8, 1, P0 ; /* 0x3f800000080c7808 */
/* 0x000fe20000000000 */
/*0400*/ DMUL R4, R4, 255 ; /* 0x406fe00004047828 */
/* 0x001e220000000000 */
/*0410*/ BRA 0x4c0 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0420*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff037424 */
/* 0x000fe400078e00ff */
/*0430*/ FADD R8, -R8, 0.25 ; /* 0x3e80000008087421 */
/* 0x000fc40000000100 */
/*0440*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0c7424 */
/* 0x000fe400078e00ff */
/*0450*/ FFMA R8, R8, 4, R3 ; /* 0x4080000008087823 */
/* 0x000fc80000000003 */
/*0460*/ F2F.F64.F32 R6, R8 ; /* 0x0000000800067310 */
/* 0x000e240000201800 */
/*0470*/ DMUL R6, R6, 255 ; /* 0x406fe00006067828 */
/* 0x001e220000000000 */
/*0480*/ BRA 0x4c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0490*/ FMUL R12, R8, 4 ; /* 0x40800000080c7820 */
/* 0x000fe40000400000 */
/*04a0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff077424 */
/* 0x000fe400078e00ff */
/*04c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04d0*/ F2F.F64.F32 R8, R12 ; /* 0x0000000c00087310 */
/* 0x000e700000201800 */
/*04e0*/ F2I.U32.F64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x001e22000030d000 */
/*04f0*/ DMUL R8, R8, 255 ; /* 0x406fe00008087828 */
/* 0x002e4e0000000000 */
/*0500*/ F2I.U32.F64.TRUNC R6, R6 ; /* 0x0000000600067311 */
/* 0x000ea2000030d000 */
/*0510*/ PRMT R11, R4, 0x7610, R11 ; /* 0x00007610040b7816 */
/* 0x001fce000000000b */
/*0520*/ F2I.U32.F64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x002e22000030d000 */
/*0530*/ PRMT R3, R6, 0x7610, R3 ; /* 0x0000761006037816 */
/* 0x004fe40000000003 */
/*0540*/ PRMT R10, R8, 0x7610, R10 ; /* 0x00007610080a7816 */
/* 0x001fca000000000a */
/*0550*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0560*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0570*/ IMAD.SHL.U32 R0, R0, 0x100, RZ ; /* 0x0000010000007824 */
/* 0x000fe200078e00ff */
/*0580*/ USHF.L.U32 UR4, UR4, 0x8, URZ ; /* 0x0000000804047899 */
/* 0x000fe2000800063f */
/*0590*/ PRMT R10, R10, 0x7604, R11 ; /* 0x000076040a0a7816 */
/* 0x000fe2000000000b */
/*05a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*05b0*/ USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; /* 0x000000083f047899 */
/* 0x000fe20008011404 */
/*05c0*/ SHF.R.S32.HI R5, RZ, 0x8, R0 ; /* 0x00000008ff057819 */
/* 0x000fe20000011400 */
/*05d0*/ IMAD.MOV.U32 R0, RZ, RZ, 0xff ; /* 0x000000ffff007424 */
/* 0x000fe200078e00ff */
/*05e0*/ PRMT R3, R3, 0x7054, R10 ; /* 0x0000705403037816 */
/* 0x000fc6000000000a */
/*05f0*/ IMAD R2, R5, UR4, R2 ; /* 0x0000000405027c24 */
/* 0x000fe2000f8e0202 */
/*0600*/ PRMT R5, R0, 0x654, R3 ; /* 0x0000065400057816 */
/* 0x000fc60000000003 */
/*0610*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0620*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0630*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0640*/ SHF.R.U32.HI R7, RZ, 0x17, R6.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011606 */
/*0650*/ BSSY B2, 0xca0 ; /* 0x0000064000027945 */
/* 0x000fe20003800000 */
/*0660*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*0670*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0003 */
/*0680*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe200078ec0ff */
/*0690*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0006 */
/*06a0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*06b0*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x000fc40007ffe0ff */
/*06d0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*06e0*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*06f0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0700*/ @!P0 BRA 0x880 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0710*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1c200 */
/*0720*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f3c200 */
/*0730*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0740*/ @P0 BRA 0xc80 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0760*/ @!P0 BRA 0xc60 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0770*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*0780*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*0790*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*07a0*/ @!P1 BRA !P2, 0xc60 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*07b0*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*07c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*07d0*/ @P1 BRA 0xc40 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*07f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0800*/ @P0 BRA 0xc10 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0820*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0830*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0840*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0850*/ @!P0 FFMA R8, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003088823 */
/* 0x000fe400000000ff */
/*0860*/ @!P1 FFMA R9, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006099823 */
/* 0x000fe200000000ff */
/*0870*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0880*/ LEA R6, R7, 0xc0800000, 0x17 ; /* 0xc080000007067811 */
/* 0x000fe200078eb8ff */
/*0890*/ BSSY B3, 0xc00 ; /* 0x0000036000037945 */
/* 0x000fe20003800000 */
/*08a0*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*08b0*/ IMAD.IADD R6, R9, 0x1, -R6 ; /* 0x0000000109067824 */
/* 0x000fe200078e0a06 */
/*08c0*/ IADD3 R7, R5.reuse, 0x7f, -R7 ; /* 0x0000007f05077810 */
/* 0x040fe20007ffe807 */
/*08d0*/ IMAD R8, R5, -0x800000, R8 ; /* 0xff80000005087824 */
/* 0x000fe400078e0208 */
/*08e0*/ MUFU.RCP R3, R6 ; /* 0x0000000600037308 */
/* 0x000e220000001000 */
/*08f0*/ FADD.FTZ R9, -R6, -RZ ; /* 0x800000ff06097221 */
/* 0x000fe40000010100 */
/*0900*/ IMAD.IADD R10, R7, 0x1, R10 ; /* 0x00000001070a7824 */
/* 0x000fe400078e020a */
/*0910*/ FFMA R12, R3, R9, 1 ; /* 0x3f800000030c7423 */
/* 0x001fc80000000009 */
/*0920*/ FFMA R11, R3, R12, R3 ; /* 0x0000000c030b7223 */
/* 0x000fc80000000003 */
/*0930*/ FFMA R3, R8, R11, RZ ; /* 0x0000000b08037223 */
/* 0x000fc800000000ff */
/*0940*/ FFMA R12, R9, R3, R8 ; /* 0x00000003090c7223 */
/* 0x000fc80000000008 */
/*0950*/ FFMA R12, R11, R12, R3 ; /* 0x0000000c0b0c7223 */
/* 0x000fc80000000003 */
/*0960*/ FFMA R8, R9, R12, R8 ; /* 0x0000000c09087223 */
/* 0x000fc80000000008 */
/*0970*/ FFMA R3, R11, R8, R12 ; /* 0x000000080b037223 */
/* 0x000fca000000000c */
/*0980*/ SHF.R.U32.HI R5, RZ, 0x17, R3 ; /* 0x00000017ff057819 */
/* 0x000fc80000011603 */
/*0990*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*09a0*/ IMAD.IADD R9, R5, 0x1, R10 ; /* 0x0000000105097824 */
/* 0x000fca00078e020a */
/*09b0*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*09c0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*09d0*/ @!P0 BRA 0xbe0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*09e0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*09f0*/ @P0 BRA 0xbb0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0a00*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0a10*/ @P0 BRA 0xbf0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0a20*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0a30*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0a40*/ @!P0 BRA 0xbf0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a50*/ FFMA.RZ R5, R11, R8.reuse, R12.reuse ; /* 0x000000080b057223 */
/* 0x180fe2000000c00c */
/*0a60*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0a70*/ FFMA.RM R6, R11, R8.reuse, R12.reuse ; /* 0x000000080b067223 */
/* 0x180fe2000000400c */
/*0a80*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0a90*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0aa0*/ FFMA.RP R5, R11, R8, R12 ; /* 0x000000080b057223 */
/* 0x000fe2000000800c */
/*0ab0*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0ad0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0ae0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0af0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0b00*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0b10*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0b20*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0b30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0b40*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0b50*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0b60*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0b70*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0b80*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*0b90*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*0ba0*/ BRA 0xbf0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0bc0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0bd0*/ BRA 0xbf0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0be0*/ IMAD R3, R10, 0x800000, R3 ; /* 0x008000000a037824 */
/* 0x000fe400078e0203 */
/*0bf0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0c00*/ BRA 0xc90 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0c10*/ LOP3.LUT R3, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009037812 */
/* 0x000fc800078e4808 */
/*0c20*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0c30*/ BRA 0xc90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R3, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009037812 */
/* 0x000fe200078e4808 */
/*0c50*/ BRA 0xc90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c60*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0c70*/ BRA 0xc90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c80*/ FADD.FTZ R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x000fe40000010000 */
/*0c90*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ca0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0cb0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff34004007950 */
/* 0x000fea0003c3ffff */
/*0cc0*/ BRA 0xcc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void convertPitchedFloatToRGBA_kernel(uchar4 *out_image, const float *in_image, int width, int height, int pitch, float lowerLim, float upperLim) {
const int x = __mul24(blockIdx.x, blockDim.x) + threadIdx.x;
const int y = __mul24(blockIdx.y, blockDim.y) + threadIdx.y;
uchar4 temp;
if (x < width && y < height) {
float val = *((float *)((char *)in_image + y * pitch) + x);
// first draw unmatched pixels in white
if (!isfinite(val)) {
temp.x = 255;
temp.y = 255;
temp.z = 255;
temp.w = 255;
} else {
// rescale value from [lowerLim,upperLim] to [0,1]
val -= lowerLim;
val /= (upperLim - lowerLim);
float r = 1.0f;
float g = 1.0f;
float b = 1.0f;
if (val < 0.25f) {
r = 0;
g = 4.0f * val;
} else if (val < 0.5f) {
r = 0;
b = 1.0 + 4.0f * (0.25f - val);
} else if (val < 0.75f) {
r = 4.0f * (val - 0.5f);
b = 0;
} else {
g = 1.0f + 4.0f * (0.75f - val);
b = 0;
}
temp.x = 255.0 * r;
temp.y = 255.0 * g;
temp.z = 255.0 * b;
temp.w = 255;
}
out_image[__mul24(y, width) + x] = temp;
}
} | .file "tmpxft_001b5346_00000000-6_convertPitchedFloatToRGBA_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiffP6uchar4PKfiiiff
.type _Z66__device_stub__Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiffP6uchar4PKfiiiff, @function
_Z66__device_stub__Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiffP6uchar4PKfiiiff:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z66__device_stub__Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiffP6uchar4PKfiiiff, .-_Z66__device_stub__Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiffP6uchar4PKfiiiff
.globl _Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff
.type _Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff, @function
_Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z66__device_stub__Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiffP6uchar4PKfiiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff, .-_Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void convertPitchedFloatToRGBA_kernel(uchar4 *out_image, const float *in_image, int width, int height, int pitch, float lowerLim, float upperLim) {
const int x = __mul24(blockIdx.x, blockDim.x) + threadIdx.x;
const int y = __mul24(blockIdx.y, blockDim.y) + threadIdx.y;
uchar4 temp;
if (x < width && y < height) {
float val = *((float *)((char *)in_image + y * pitch) + x);
// first draw unmatched pixels in white
if (!isfinite(val)) {
temp.x = 255;
temp.y = 255;
temp.z = 255;
temp.w = 255;
} else {
// rescale value from [lowerLim,upperLim] to [0,1]
val -= lowerLim;
val /= (upperLim - lowerLim);
float r = 1.0f;
float g = 1.0f;
float b = 1.0f;
if (val < 0.25f) {
r = 0;
g = 4.0f * val;
} else if (val < 0.5f) {
r = 0;
b = 1.0 + 4.0f * (0.25f - val);
} else if (val < 0.75f) {
r = 4.0f * (val - 0.5f);
b = 0;
} else {
g = 1.0f + 4.0f * (0.75f - val);
b = 0;
}
temp.x = 255.0 * r;
temp.y = 255.0 * g;
temp.z = 255.0 * b;
temp.w = 255;
}
out_image[__mul24(y, width) + x] = temp;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convertPitchedFloatToRGBA_kernel(uchar4 *out_image, const float *in_image, int width, int height, int pitch, float lowerLim, float upperLim) {
const int x = __mul24(blockIdx.x, blockDim.x) + threadIdx.x;
const int y = __mul24(blockIdx.y, blockDim.y) + threadIdx.y;
uchar4 temp;
if (x < width && y < height) {
float val = *((float *)((char *)in_image + y * pitch) + x);
// first draw unmatched pixels in white
if (!isfinite(val)) {
temp.x = 255;
temp.y = 255;
temp.z = 255;
temp.w = 255;
} else {
// rescale value from [lowerLim,upperLim] to [0,1]
val -= lowerLim;
val /= (upperLim - lowerLim);
float r = 1.0f;
float g = 1.0f;
float b = 1.0f;
if (val < 0.25f) {
r = 0;
g = 4.0f * val;
} else if (val < 0.5f) {
r = 0;
b = 1.0 + 4.0f * (0.25f - val);
} else if (val < 0.75f) {
r = 4.0f * (val - 0.5f);
b = 0;
} else {
g = 1.0f + 4.0f * (0.75f - val);
b = 0;
}
temp.x = 255.0 * r;
temp.y = 255.0 * g;
temp.z = 255.0 * b;
temp.w = 255;
}
out_image[__mul24(y, width) + x] = temp;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convertPitchedFloatToRGBA_kernel(uchar4 *out_image, const float *in_image, int width, int height, int pitch, float lowerLim, float upperLim) {
const int x = __mul24(blockIdx.x, blockDim.x) + threadIdx.x;
const int y = __mul24(blockIdx.y, blockDim.y) + threadIdx.y;
uchar4 temp;
if (x < width && y < height) {
float val = *((float *)((char *)in_image + y * pitch) + x);
// first draw unmatched pixels in white
if (!isfinite(val)) {
temp.x = 255;
temp.y = 255;
temp.z = 255;
temp.w = 255;
} else {
// rescale value from [lowerLim,upperLim] to [0,1]
val -= lowerLim;
val /= (upperLim - lowerLim);
float r = 1.0f;
float g = 1.0f;
float b = 1.0f;
if (val < 0.25f) {
r = 0;
g = 4.0f * val;
} else if (val < 0.5f) {
r = 0;
b = 1.0 + 4.0f * (0.25f - val);
} else if (val < 0.75f) {
r = 4.0f * (val - 0.5f);
b = 0;
} else {
g = 1.0f + 4.0f * (0.75f - val);
b = 0;
}
temp.x = 255.0 * r;
temp.y = 255.0 * g;
temp.z = 255.0 * b;
temp.w = 255;
}
out_image[__mul24(y, width) + x] = temp;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.globl _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.p2align 8
.type _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff,@function
_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_bfe_i32 s3, s14, 0x180000
s_bfe_i32 s6, s15, 0x180000
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s3, s7, v[2:3]
v_mad_u64_u32 v[2:3], null, s6, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_16
s_clause 0x1
s_load_b32 s5, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v5, v2, s5
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v1, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, v1, v3
v_mov_b32_e32 v1, 0xff
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, v5, v4, vcc_lo
global_load_b32 v5, v[3:4], off
v_dual_mov_b32 v3, 0xff :: v_dual_mov_b32 v4, 0xff
s_waitcnt vmcnt(0)
v_cmp_class_f32_e64 s3, v5, 0x1f8
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_15
s_load_b64 s[6:7], s[0:1], 0x1c
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_subrev_f32_e32 v1, s6, v5
v_sub_f32_e64 v3, s7, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v3, v3, v1
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v1, v3, v1
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v5, v4, v3, v1
v_cmpx_ngt_f32_e32 0x3e800000, v5
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_12
s_mov_b32 s5, exec_lo
v_cmpx_ngt_f32_e32 0.5, v5
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_9
s_mov_b32 s6, exec_lo
v_cmpx_ngt_f32_e32 0x3f400000, v5
s_xor_b32 s6, exec_lo, s6
v_sub_f32_e32 v1, 0x3f400000, v5
s_movk_i32 s8, 0xff
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v4, v1, 4.0, 1.0
s_or_saveexec_b32 s6, s6
v_mov_b32_e32 v1, s7
v_mov_b32_e32 v3, s8
s_xor_b32 exec_lo, exec_lo, s6
v_add_f32_e32 v1, -0.5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 4.0, v1
v_cvt_f64_f32_e32 v[3:4], v1
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], 0x406fe000
v_cvt_i32_f64_e32 v3, v[3:4]
v_mov_b32_e32 v4, 1.0
s_or_b32 exec_lo, exec_lo, s6
.LBB0_9:
s_and_not1_saveexec_b32 s5, s5
v_sub_f32_e32 v1, 0x3e800000, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, v1, 4.0, 1.0
v_cvt_f64_f32_e32 v[3:4], v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], 0x406fe000
v_cvt_i32_f64_e32 v1, v[3:4]
v_dual_mov_b32 v4, 1.0 :: v_dual_mov_b32 v3, 0
s_or_b32 exec_lo, exec_lo, s5
.LBB0_12:
s_and_not1_saveexec_b32 s3, s3
v_dual_mul_f32 v4, 4.0, v5 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v1, 0xff
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v4
v_mul_f64 v[4:5], v[4:5], 0x406fe000
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f64_e32 v4, v[4:5]
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_i32_i24 v5, v2, s4, v0
v_mov_b32_e32 v0, 0xff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x3
global_store_b8 v[5:6], v3, off
global_store_b8 v[5:6], v4, off offset:1
global_store_b8 v[5:6], v1, off offset:2
global_store_b8 v[5:6], v0, off offset:3
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff, .Lfunc_end0-_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convertPitchedFloatToRGBA_kernel(uchar4 *out_image, const float *in_image, int width, int height, int pitch, float lowerLim, float upperLim) {
const int x = __mul24(blockIdx.x, blockDim.x) + threadIdx.x;
const int y = __mul24(blockIdx.y, blockDim.y) + threadIdx.y;
uchar4 temp;
if (x < width && y < height) {
float val = *((float *)((char *)in_image + y * pitch) + x);
// first draw unmatched pixels in white
if (!isfinite(val)) {
temp.x = 255;
temp.y = 255;
temp.z = 255;
temp.w = 255;
} else {
// rescale value from [lowerLim,upperLim] to [0,1]
val -= lowerLim;
val /= (upperLim - lowerLim);
float r = 1.0f;
float g = 1.0f;
float b = 1.0f;
if (val < 0.25f) {
r = 0;
g = 4.0f * val;
} else if (val < 0.5f) {
r = 0;
b = 1.0 + 4.0f * (0.25f - val);
} else if (val < 0.75f) {
r = 4.0f * (val - 0.5f);
b = 0;
} else {
g = 1.0f + 4.0f * (0.75f - val);
b = 0;
}
temp.x = 255.0 * r;
temp.y = 255.0 * g;
temp.z = 255.0 * b;
temp.w = 255;
}
out_image[__mul24(y, width) + x] = temp;
}
} | .text
.file "convertPitchedFloatToRGBA_kernel.hip"
.globl _Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff # -- Begin function _Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.p2align 4, 0x90
.type _Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff,@function
_Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff: # @_Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff, .Lfunc_end0-_Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff,@object # @_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.section .rodata,"a",@progbits
.globl _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.p2align 3, 0x0
_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff:
.quad _Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.size _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff"
.size .L__unnamed_1, 70
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000e220000002600 */
/*0020*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff027624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD.SHL.U32 R2, R2, 0x100, RZ ; /* 0x0000010002027824 */
/* 0x000fe400078e00ff */
/*0070*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000ee20000002500 */
/*0080*/ IMAD.SHL.U32 R0, R0, 0x100, RZ ; /* 0x0000010000007824 */
/* 0x000fe400078e00ff */
/*0090*/ SHF.R.S32.HI R3, RZ, 0x8, R2 ; /* 0x00000008ff037819 */
/* 0x000fc60000011402 */
/*00a0*/ SHF.R.S32.HI R2, RZ, 0x8, R0 ; /* 0x00000008ff027819 */
/* 0x000fe20000011400 */
/*00b0*/ USHF.L.U32 UR5, UR5, 0x8, URZ ; /* 0x0000000805057899 */
/* 0x001fc8000800063f */
/*00c0*/ USHF.R.S32.HI UR5, URZ, 0x8, UR5 ; /* 0x000000083f057899 */
/* 0x000fe40008011405 */
/*00d0*/ USHF.L.U32 UR4, UR4, 0x8, URZ ; /* 0x0000000804047899 */
/* 0x008fc8000800063f */
/*00e0*/ IMAD R0, R3, UR5, R4 ; /* 0x0000000503007c24 */
/* 0x002fe2000f8e0204 */
/*00f0*/ USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; /* 0x000000083f047899 */
/* 0x000fc80008011404 */
/*0100*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe40003f06270 */
/*0110*/ IMAD R2, R2, UR4, R5 ; /* 0x0000000402027c24 */
/* 0x004fca000f8e0205 */
/*0120*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fda0000706670 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ IMAD R3, R0, c[0x0][0x178], RZ ; /* 0x00005e0000037a24 */
/* 0x000fe200078e02ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0160*/ IADD3 R4, P0, R3, c[0x0][0x168], RZ ; /* 0x00005a0003047a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ LEA.HI.X.SX32 R5, R3, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0003057a11 */
/* 0x000fca00000f0eff */
/*0180*/ IMAD.WIDE R4, R2, 0x4, R4 ; /* 0x0000000402047825 */
/* 0x000fcc00078e0204 */
/*0190*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ BSSY B0, 0x560 ; /* 0x000003b000007945 */
/* 0x000fe20003800000 */
/*01b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0xff ; /* 0x000000ffff037424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R10, RZ, RZ, 0xff ; /* 0x000000ffff0a7424 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, 0xff ; /* 0x000000ffff0b7424 */
/* 0x000fe200078e00ff */
/*01e0*/ FSETP.GEU.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x004fda0003f0e200 */
/*01f0*/ @P0 BRA 0x550 ; /* 0x0000035000000947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*0210*/ BSSY B1, 0x300 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0220*/ FADD R3, R4, -c[0x0][0x17c] ; /* 0x80005f0004037621 */
/* 0x000fe40000000000 */
/*0230*/ FADD R6, R6, -c[0x0][0x17c] ; /* 0x80005f0006067621 */
/* 0x000fc80000000000 */
/*0240*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x000e300000001000 */
/*0250*/ FCHK P0, R3, R6 ; /* 0x0000000603007302 */
/* 0x000e620000000000 */
/*0260*/ FFMA R8, -R6, R5, 1 ; /* 0x3f80000006087423 */
/* 0x001fc80000000105 */
/*0270*/ FFMA R8, R5, R8, R5 ; /* 0x0000000805087223 */
/* 0x000fc80000000005 */
/*0280*/ FFMA R5, R3, R8, RZ ; /* 0x0000000803057223 */
/* 0x000fc800000000ff */
/*0290*/ FFMA R4, -R6, R5, R3 ; /* 0x0000000506047223 */
/* 0x000fc80000000103 */
/*02a0*/ FFMA R8, R8, R4, R5 ; /* 0x0000000408087223 */
/* 0x000fe20000000005 */
/*02b0*/ @!P0 BRA 0x2f0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*02c0*/ MOV R4, 0x2e0 ; /* 0x000002e000047802 */
/* 0x000fe40000000f00 */
/*02d0*/ CALL.REL.NOINC 0x640 ; /* 0x0000036000007944 */
/* 0x000fea0003c00000 */
/*02e0*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0003 */
/*02f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0300*/ FSETP.GEU.AND P0, PT, R8, 0.25, PT ; /* 0x3e8000000800780b */
/* 0x000fe20003f0e000 */
/*0310*/ BSSY B1, 0x4d0 ; /* 0x000001b000017945 */
/* 0x000fe20003800000 */
/*0320*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fd6000001ff00 */
/*0330*/ @!P0 BRA 0x490 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0340*/ FSETP.GEU.AND P0, PT, R8, 0.5, PT ; /* 0x3f0000000800780b */
/* 0x000fda0003f0e000 */
/*0350*/ @!P0 BRA 0x420 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0360*/ FADD R3, R8.reuse, -0.5 ; /* 0xbf00000008037421 */
/* 0x040fe20000000000 */
/*0370*/ FSETP.GEU.AND P0, PT, R8.reuse, 0.75, PT ; /* 0x3f4000000800780b */
/* 0x040fe20003f0e000 */
/*0380*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff077424 */
/* 0x000fe400078e00ff */
/*0390*/ FMUL R3, R3, 4 ; /* 0x4080000003037820 */
/* 0x000fe40000400000 */
/*03a0*/ FADD R8, -R8, 0.75 ; /* 0x3f40000008087421 */
/* 0x000fc60000000100 */
/*03b0*/ FSEL R3, R3, 1, !P0 ; /* 0x3f80000003037808 */
/* 0x000fe20004000000 */
/*03c0*/ FFMA R8, R8, 4, R7 ; /* 0x4080000008087823 */
/* 0x000fe40000000007 */
/*03d0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*03e0*/ F2F.F64.F32 R4, R3 ; /* 0x0000000300047310 */
/* 0x000e240000201800 */
/*03f0*/ FSEL R12, R8, 1, P0 ; /* 0x3f800000080c7808 */
/* 0x000fe20000000000 */
/*0400*/ DMUL R4, R4, 255 ; /* 0x406fe00004047828 */
/* 0x001e220000000000 */
/*0410*/ BRA 0x4c0 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0420*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff037424 */
/* 0x000fe400078e00ff */
/*0430*/ FADD R8, -R8, 0.25 ; /* 0x3e80000008087421 */
/* 0x000fc40000000100 */
/*0440*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0c7424 */
/* 0x000fe400078e00ff */
/*0450*/ FFMA R8, R8, 4, R3 ; /* 0x4080000008087823 */
/* 0x000fc80000000003 */
/*0460*/ F2F.F64.F32 R6, R8 ; /* 0x0000000800067310 */
/* 0x000e240000201800 */
/*0470*/ DMUL R6, R6, 255 ; /* 0x406fe00006067828 */
/* 0x001e220000000000 */
/*0480*/ BRA 0x4c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0490*/ FMUL R12, R8, 4 ; /* 0x40800000080c7820 */
/* 0x000fe40000400000 */
/*04a0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x406fe000 ; /* 0x406fe000ff077424 */
/* 0x000fe400078e00ff */
/*04c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04d0*/ F2F.F64.F32 R8, R12 ; /* 0x0000000c00087310 */
/* 0x000e700000201800 */
/*04e0*/ F2I.U32.F64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x001e22000030d000 */
/*04f0*/ DMUL R8, R8, 255 ; /* 0x406fe00008087828 */
/* 0x002e4e0000000000 */
/*0500*/ F2I.U32.F64.TRUNC R6, R6 ; /* 0x0000000600067311 */
/* 0x000ea2000030d000 */
/*0510*/ PRMT R11, R4, 0x7610, R11 ; /* 0x00007610040b7816 */
/* 0x001fce000000000b */
/*0520*/ F2I.U32.F64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x002e22000030d000 */
/*0530*/ PRMT R3, R6, 0x7610, R3 ; /* 0x0000761006037816 */
/* 0x004fe40000000003 */
/*0540*/ PRMT R10, R8, 0x7610, R10 ; /* 0x00007610080a7816 */
/* 0x001fca000000000a */
/*0550*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0560*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0570*/ IMAD.SHL.U32 R0, R0, 0x100, RZ ; /* 0x0000010000007824 */
/* 0x000fe200078e00ff */
/*0580*/ USHF.L.U32 UR4, UR4, 0x8, URZ ; /* 0x0000000804047899 */
/* 0x000fe2000800063f */
/*0590*/ PRMT R10, R10, 0x7604, R11 ; /* 0x000076040a0a7816 */
/* 0x000fe2000000000b */
/*05a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*05b0*/ USHF.R.S32.HI UR4, URZ, 0x8, UR4 ; /* 0x000000083f047899 */
/* 0x000fe20008011404 */
/*05c0*/ SHF.R.S32.HI R5, RZ, 0x8, R0 ; /* 0x00000008ff057819 */
/* 0x000fe20000011400 */
/*05d0*/ IMAD.MOV.U32 R0, RZ, RZ, 0xff ; /* 0x000000ffff007424 */
/* 0x000fe200078e00ff */
/*05e0*/ PRMT R3, R3, 0x7054, R10 ; /* 0x0000705403037816 */
/* 0x000fc6000000000a */
/*05f0*/ IMAD R2, R5, UR4, R2 ; /* 0x0000000405027c24 */
/* 0x000fe2000f8e0202 */
/*0600*/ PRMT R5, R0, 0x654, R3 ; /* 0x0000065400057816 */
/* 0x000fc60000000003 */
/*0610*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0620*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0630*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0640*/ SHF.R.U32.HI R7, RZ, 0x17, R6.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011606 */
/*0650*/ BSSY B2, 0xca0 ; /* 0x0000064000027945 */
/* 0x000fe20003800000 */
/*0660*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*0670*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0003 */
/*0680*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe200078ec0ff */
/*0690*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0006 */
/*06a0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*06b0*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x000fc40007ffe0ff */
/*06d0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*06e0*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*06f0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0700*/ @!P0 BRA 0x880 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0710*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1c200 */
/*0720*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f3c200 */
/*0730*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0740*/ @P0 BRA 0xc80 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0760*/ @!P0 BRA 0xc60 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0770*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*0780*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*0790*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*07a0*/ @!P1 BRA !P2, 0xc60 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*07b0*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*07c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*07d0*/ @P1 BRA 0xc40 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*07f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0800*/ @P0 BRA 0xc10 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0820*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0830*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0840*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0850*/ @!P0 FFMA R8, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003088823 */
/* 0x000fe400000000ff */
/*0860*/ @!P1 FFMA R9, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006099823 */
/* 0x000fe200000000ff */
/*0870*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0880*/ LEA R6, R7, 0xc0800000, 0x17 ; /* 0xc080000007067811 */
/* 0x000fe200078eb8ff */
/*0890*/ BSSY B3, 0xc00 ; /* 0x0000036000037945 */
/* 0x000fe20003800000 */
/*08a0*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*08b0*/ IMAD.IADD R6, R9, 0x1, -R6 ; /* 0x0000000109067824 */
/* 0x000fe200078e0a06 */
/*08c0*/ IADD3 R7, R5.reuse, 0x7f, -R7 ; /* 0x0000007f05077810 */
/* 0x040fe20007ffe807 */
/*08d0*/ IMAD R8, R5, -0x800000, R8 ; /* 0xff80000005087824 */
/* 0x000fe400078e0208 */
/*08e0*/ MUFU.RCP R3, R6 ; /* 0x0000000600037308 */
/* 0x000e220000001000 */
/*08f0*/ FADD.FTZ R9, -R6, -RZ ; /* 0x800000ff06097221 */
/* 0x000fe40000010100 */
/*0900*/ IMAD.IADD R10, R7, 0x1, R10 ; /* 0x00000001070a7824 */
/* 0x000fe400078e020a */
/*0910*/ FFMA R12, R3, R9, 1 ; /* 0x3f800000030c7423 */
/* 0x001fc80000000009 */
/*0920*/ FFMA R11, R3, R12, R3 ; /* 0x0000000c030b7223 */
/* 0x000fc80000000003 */
/*0930*/ FFMA R3, R8, R11, RZ ; /* 0x0000000b08037223 */
/* 0x000fc800000000ff */
/*0940*/ FFMA R12, R9, R3, R8 ; /* 0x00000003090c7223 */
/* 0x000fc80000000008 */
/*0950*/ FFMA R12, R11, R12, R3 ; /* 0x0000000c0b0c7223 */
/* 0x000fc80000000003 */
/*0960*/ FFMA R8, R9, R12, R8 ; /* 0x0000000c09087223 */
/* 0x000fc80000000008 */
/*0970*/ FFMA R3, R11, R8, R12 ; /* 0x000000080b037223 */
/* 0x000fca000000000c */
/*0980*/ SHF.R.U32.HI R5, RZ, 0x17, R3 ; /* 0x00000017ff057819 */
/* 0x000fc80000011603 */
/*0990*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*09a0*/ IMAD.IADD R9, R5, 0x1, R10 ; /* 0x0000000105097824 */
/* 0x000fca00078e020a */
/*09b0*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*09c0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*09d0*/ @!P0 BRA 0xbe0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*09e0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*09f0*/ @P0 BRA 0xbb0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0a00*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0a10*/ @P0 BRA 0xbf0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0a20*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0a30*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0a40*/ @!P0 BRA 0xbf0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a50*/ FFMA.RZ R5, R11, R8.reuse, R12.reuse ; /* 0x000000080b057223 */
/* 0x180fe2000000c00c */
/*0a60*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0a70*/ FFMA.RM R6, R11, R8.reuse, R12.reuse ; /* 0x000000080b067223 */
/* 0x180fe2000000400c */
/*0a80*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0a90*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0aa0*/ FFMA.RP R5, R11, R8, R12 ; /* 0x000000080b057223 */
/* 0x000fe2000000800c */
/*0ab0*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0ad0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0ae0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0af0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0b00*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0b10*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0b20*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0b30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0b40*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0b50*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0b60*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0b70*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0b80*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*0b90*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*0ba0*/ BRA 0xbf0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0bc0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0bd0*/ BRA 0xbf0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0be0*/ IMAD R3, R10, 0x800000, R3 ; /* 0x008000000a037824 */
/* 0x000fe400078e0203 */
/*0bf0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0c00*/ BRA 0xc90 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0c10*/ LOP3.LUT R3, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009037812 */
/* 0x000fc800078e4808 */
/*0c20*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0c30*/ BRA 0xc90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R3, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009037812 */
/* 0x000fe200078e4808 */
/*0c50*/ BRA 0xc90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c60*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0c70*/ BRA 0xc90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c80*/ FADD.FTZ R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x000fe40000010000 */
/*0c90*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ca0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0cb0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff34004007950 */
/* 0x000fea0003c3ffff */
/*0cc0*/ BRA 0xcc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.globl _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.p2align 8
.type _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff,@function
_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_bfe_i32 s3, s14, 0x180000
s_bfe_i32 s6, s15, 0x180000
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s3, s7, v[2:3]
v_mad_u64_u32 v[2:3], null, s6, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_16
s_clause 0x1
s_load_b32 s5, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v5, v2, s5
v_ashrrev_i32_e32 v6, 31, v5
v_add_co_u32 v1, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, v1, v3
v_mov_b32_e32 v1, 0xff
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, v5, v4, vcc_lo
global_load_b32 v5, v[3:4], off
v_dual_mov_b32 v3, 0xff :: v_dual_mov_b32 v4, 0xff
s_waitcnt vmcnt(0)
v_cmp_class_f32_e64 s3, v5, 0x1f8
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_15
s_load_b64 s[6:7], s[0:1], 0x1c
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_subrev_f32_e32 v1, s6, v5
v_sub_f32_e64 v3, s7, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v3, v3, v1
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v1, v3, v1
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v5, v4, v3, v1
v_cmpx_ngt_f32_e32 0x3e800000, v5
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_12
s_mov_b32 s5, exec_lo
v_cmpx_ngt_f32_e32 0.5, v5
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_9
s_mov_b32 s6, exec_lo
v_cmpx_ngt_f32_e32 0x3f400000, v5
s_xor_b32 s6, exec_lo, s6
v_sub_f32_e32 v1, 0x3f400000, v5
s_movk_i32 s8, 0xff
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v4, v1, 4.0, 1.0
s_or_saveexec_b32 s6, s6
v_mov_b32_e32 v1, s7
v_mov_b32_e32 v3, s8
s_xor_b32 exec_lo, exec_lo, s6
v_add_f32_e32 v1, -0.5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 4.0, v1
v_cvt_f64_f32_e32 v[3:4], v1
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], 0x406fe000
v_cvt_i32_f64_e32 v3, v[3:4]
v_mov_b32_e32 v4, 1.0
s_or_b32 exec_lo, exec_lo, s6
.LBB0_9:
s_and_not1_saveexec_b32 s5, s5
v_sub_f32_e32 v1, 0x3e800000, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, v1, 4.0, 1.0
v_cvt_f64_f32_e32 v[3:4], v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], 0x406fe000
v_cvt_i32_f64_e32 v1, v[3:4]
v_dual_mov_b32 v4, 1.0 :: v_dual_mov_b32 v3, 0
s_or_b32 exec_lo, exec_lo, s5
.LBB0_12:
s_and_not1_saveexec_b32 s3, s3
v_dual_mul_f32 v4, 4.0, v5 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v1, 0xff
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v4
v_mul_f64 v[4:5], v[4:5], 0x406fe000
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f64_e32 v4, v[4:5]
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_i32_i24 v5, v2, s4, v0
v_mov_b32_e32 v0, 0xff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x3
global_store_b8 v[5:6], v3, off
global_store_b8 v[5:6], v4, off offset:1
global_store_b8 v[5:6], v1, off offset:2
global_store_b8 v[5:6], v0, off offset:3
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff, .Lfunc_end0-_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b5346_00000000-6_convertPitchedFloatToRGBA_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiffP6uchar4PKfiiiff
.type _Z66__device_stub__Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiffP6uchar4PKfiiiff, @function
_Z66__device_stub__Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiffP6uchar4PKfiiiff:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z66__device_stub__Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiffP6uchar4PKfiiiff, .-_Z66__device_stub__Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiffP6uchar4PKfiiiff
.globl _Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff
.type _Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff, @function
_Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z66__device_stub__Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiffP6uchar4PKfiiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff, .-_Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32convertPitchedFloatToRGBA_kernelP6uchar4PKfiiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convertPitchedFloatToRGBA_kernel.hip"
.globl _Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff # -- Begin function _Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.p2align 4, 0x90
.type _Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff,@function
_Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff: # @_Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff, .Lfunc_end0-_Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff,@object # @_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.section .rodata,"a",@progbits
.globl _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.p2align 3, 0x0
_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff:
.quad _Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.size _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff"
.size .L__unnamed_1, 70
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32convertPitchedFloatToRGBA_kernelP15HIP_vector_typeIhLj4EEPKfiiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
__global__ void empty() {}
void benchmark_gpu_init() {
cudaFree(0);
empty<<<1,1>>>();
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z5emptyv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
__global__ void empty() {}
void benchmark_gpu_init() {
cudaFree(0);
empty<<<1,1>>>();
cudaDeviceSynchronize();
} | .file "tmpxft_001a7554_00000000-6_utils_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5emptyvv
.type _Z23__device_stub__Z5emptyvv, @function
_Z23__device_stub__Z5emptyvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5emptyv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z23__device_stub__Z5emptyvv, .-_Z23__device_stub__Z5emptyvv
.globl _Z5emptyv
.type _Z5emptyv, @function
_Z5emptyv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5emptyvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z5emptyv, .-_Z5emptyv
.globl _Z18benchmark_gpu_initv
.type _Z18benchmark_gpu_initv, @function
_Z18benchmark_gpu_initv:
.LFB2027:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $0, %edi
call cudaFree@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5emptyvv
jmp .L12
.cfi_endproc
.LFE2027:
.size _Z18benchmark_gpu_initv, .-_Z18benchmark_gpu_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5emptyv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5emptyv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
__global__ void empty() {}
void benchmark_gpu_init() {
cudaFree(0);
empty<<<1,1>>>();
cudaDeviceSynchronize();
} | #include <hip/hip_runtime.h>
__global__ void empty() {}
void benchmark_gpu_init() {
hipFree(0);
empty<<<1,1>>>();
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void empty() {}
void benchmark_gpu_init() {
hipFree(0);
empty<<<1,1>>>();
hipDeviceSynchronize();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5emptyv
.globl _Z5emptyv
.p2align 8
.type _Z5emptyv,@function
_Z5emptyv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5emptyv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5emptyv, .Lfunc_end0-_Z5emptyv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5emptyv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z5emptyv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void empty() {}
void benchmark_gpu_init() {
hipFree(0);
empty<<<1,1>>>();
hipDeviceSynchronize();
} | .text
.file "utils_cuda.hip"
.globl _Z20__device_stub__emptyv # -- Begin function _Z20__device_stub__emptyv
.p2align 4, 0x90
.type _Z20__device_stub__emptyv,@function
_Z20__device_stub__emptyv: # @_Z20__device_stub__emptyv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5emptyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__emptyv, .Lfunc_end0-_Z20__device_stub__emptyv
.cfi_endproc
# -- End function
.globl _Z18benchmark_gpu_initv # -- Begin function _Z18benchmark_gpu_initv
.p2align 4, 0x90
.type _Z18benchmark_gpu_initv,@function
_Z18benchmark_gpu_initv: # @_Z18benchmark_gpu_initv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorl %edi, %edi
callq hipFree
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5emptyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18benchmark_gpu_initv, .Lfunc_end1-_Z18benchmark_gpu_initv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5emptyv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5emptyv,@object # @_Z5emptyv
.section .rodata,"a",@progbits
.globl _Z5emptyv
.p2align 3, 0x0
_Z5emptyv:
.quad _Z20__device_stub__emptyv
.size _Z5emptyv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5emptyv"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__emptyv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5emptyv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5emptyv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5emptyv
.globl _Z5emptyv
.p2align 8
.type _Z5emptyv,@function
_Z5emptyv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5emptyv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5emptyv, .Lfunc_end0-_Z5emptyv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5emptyv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z5emptyv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a7554_00000000-6_utils_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5emptyvv
.type _Z23__device_stub__Z5emptyvv, @function
_Z23__device_stub__Z5emptyvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5emptyv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z23__device_stub__Z5emptyvv, .-_Z23__device_stub__Z5emptyvv
.globl _Z5emptyv
.type _Z5emptyv, @function
_Z5emptyv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5emptyvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z5emptyv, .-_Z5emptyv
.globl _Z18benchmark_gpu_initv
.type _Z18benchmark_gpu_initv, @function
_Z18benchmark_gpu_initv:
.LFB2027:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $0, %edi
call cudaFree@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5emptyvv
jmp .L12
.cfi_endproc
.LFE2027:
.size _Z18benchmark_gpu_initv, .-_Z18benchmark_gpu_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5emptyv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5emptyv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "utils_cuda.hip"
.globl _Z20__device_stub__emptyv # -- Begin function _Z20__device_stub__emptyv
.p2align 4, 0x90
.type _Z20__device_stub__emptyv,@function
_Z20__device_stub__emptyv: # @_Z20__device_stub__emptyv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5emptyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__emptyv, .Lfunc_end0-_Z20__device_stub__emptyv
.cfi_endproc
# -- End function
.globl _Z18benchmark_gpu_initv # -- Begin function _Z18benchmark_gpu_initv
.p2align 4, 0x90
.type _Z18benchmark_gpu_initv,@function
_Z18benchmark_gpu_initv: # @_Z18benchmark_gpu_initv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorl %edi, %edi
callq hipFree
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5emptyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18benchmark_gpu_initv, .Lfunc_end1-_Z18benchmark_gpu_initv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5emptyv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5emptyv,@object # @_Z5emptyv
.section .rodata,"a",@progbits
.globl _Z5emptyv
.p2align 3, 0x0
_Z5emptyv:
.quad _Z20__device_stub__emptyv
.size _Z5emptyv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5emptyv"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__emptyv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5emptyv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
int *d_a,*d_b,*d_c;
int *h_a,*h_b,*h_c;
__host__ void init(){
h_a = (int*)malloc(sizeof(int));
h_b = (int*)malloc(sizeof(int));
h_c = (int*)malloc(sizeof(int));
*h_c=0;
cudaMalloc((void**)&d_a,sizeof(int));
cudaMalloc((void**)&d_b,sizeof(int));
cudaMalloc((void**)&d_c,sizeof(int));
cudaMemcpy(d_c,h_c,sizeof(int),cudaMemcpyHostToDevice);
}
__host__ void assign(int a,int b){
*h_a = a;
*h_b = b;
cudaMemcpy(d_a,h_a,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,sizeof(int),cudaMemcpyHostToDevice);
}
__global__ void add(int *a,int *b,int *c){
*c += *a + *b;
}
__host__ void process(){
add<<<1,1>>>(d_a,d_b,d_c);
}
__host__ int get(){
cudaMemcpy(h_c,d_c,sizeof(int),cudaMemcpyDeviceToHost);
return *h_c;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IADD3 R9, R0, R5, R2 ; /* 0x0000000500097210 */
/* 0x004fca0007ffe002 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
int *d_a,*d_b,*d_c;
int *h_a,*h_b,*h_c;
__host__ void init(){
h_a = (int*)malloc(sizeof(int));
h_b = (int*)malloc(sizeof(int));
h_c = (int*)malloc(sizeof(int));
*h_c=0;
cudaMalloc((void**)&d_a,sizeof(int));
cudaMalloc((void**)&d_b,sizeof(int));
cudaMalloc((void**)&d_c,sizeof(int));
cudaMemcpy(d_c,h_c,sizeof(int),cudaMemcpyHostToDevice);
}
__host__ void assign(int a,int b){
*h_a = a;
*h_b = b;
cudaMemcpy(d_a,h_a,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,sizeof(int),cudaMemcpyHostToDevice);
}
__global__ void add(int *a,int *b,int *c){
*c += *a + *b;
}
__host__ void process(){
add<<<1,1>>>(d_a,d_b,d_c);
}
__host__ int get(){
cudaMemcpy(h_c,d_c,sizeof(int),cudaMemcpyDeviceToHost);
return *h_c;
} | .file "tmpxft_000035dd_00000000-6_detour.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initv
.type _Z4initv, @function
_Z4initv:
.LFB2027:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $4, %edi
call malloc@PLT
movq %rax, h_a(%rip)
movl $4, %edi
call malloc@PLT
movq %rax, h_b(%rip)
movl $4, %edi
call malloc@PLT
movq %rax, h_c(%rip)
movl $0, (%rax)
movl $4, %esi
leaq d_a(%rip), %rdi
call cudaMalloc@PLT
movl $4, %esi
leaq d_b(%rip), %rdi
call cudaMalloc@PLT
movl $4, %esi
leaq d_c(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $4, %edx
movq h_c(%rip), %rsi
movq d_c(%rip), %rdi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size _Z4initv, .-_Z4initv
.globl _Z6assignii
.type _Z6assignii, @function
_Z6assignii:
.LFB2028:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq h_a(%rip), %rax
movl %edi, (%rax)
movq h_b(%rip), %rax
movl %esi, (%rax)
movl $1, %ecx
movl $4, %edx
movq h_a(%rip), %rsi
movq d_a(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq h_b(%rip), %rsi
movq d_b(%rip), %rdi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2028:
.size _Z6assignii, .-_Z6assignii
.globl _Z3getv
.type _Z3getv, @function
_Z3getv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $2, %ecx
movl $4, %edx
movq d_c(%rip), %rsi
movq h_c(%rip), %rdi
call cudaMemcpy@PLT
movq h_c(%rip), %rax
movl (%rax), %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _Z3getv, .-_Z3getv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2055:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl _Z7processv
.type _Z7processv, @function
_Z7processv:
.LFB2029:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq d_c(%rip), %rdx
movq d_b(%rip), %rsi
movq d_a(%rip), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L17
.cfi_endproc
.LFE2029:
.size _Z7processv, .-_Z7processv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl h_c
.bss
.align 8
.type h_c, @object
.size h_c, 8
h_c:
.zero 8
.globl h_b
.align 8
.type h_b, @object
.size h_b, 8
h_b:
.zero 8
.globl h_a
.align 8
.type h_a, @object
.size h_a, 8
h_a:
.zero 8
.globl d_c
.align 8
.type d_c, @object
.size d_c, 8
d_c:
.zero 8
.globl d_b
.align 8
.type d_b, @object
.size d_b, 8
d_b:
.zero 8
.globl d_a
.align 8
.type d_a, @object
.size d_a, 8
d_a:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
int *d_a,*d_b,*d_c;
int *h_a,*h_b,*h_c;
__host__ void init(){
h_a = (int*)malloc(sizeof(int));
h_b = (int*)malloc(sizeof(int));
h_c = (int*)malloc(sizeof(int));
*h_c=0;
cudaMalloc((void**)&d_a,sizeof(int));
cudaMalloc((void**)&d_b,sizeof(int));
cudaMalloc((void**)&d_c,sizeof(int));
cudaMemcpy(d_c,h_c,sizeof(int),cudaMemcpyHostToDevice);
}
__host__ void assign(int a,int b){
*h_a = a;
*h_b = b;
cudaMemcpy(d_a,h_a,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,sizeof(int),cudaMemcpyHostToDevice);
}
__global__ void add(int *a,int *b,int *c){
*c += *a + *b;
}
__host__ void process(){
add<<<1,1>>>(d_a,d_b,d_c);
}
__host__ int get(){
cudaMemcpy(h_c,d_c,sizeof(int),cudaMemcpyDeviceToHost);
return *h_c;
} | #include "hip/hip_runtime.h"
int *d_a,*d_b,*d_c;
int *h_a,*h_b,*h_c;
__host__ void init(){
h_a = (int*)malloc(sizeof(int));
h_b = (int*)malloc(sizeof(int));
h_c = (int*)malloc(sizeof(int));
*h_c=0;
hipMalloc((void**)&d_a,sizeof(int));
hipMalloc((void**)&d_b,sizeof(int));
hipMalloc((void**)&d_c,sizeof(int));
hipMemcpy(d_c,h_c,sizeof(int),hipMemcpyHostToDevice);
}
__host__ void assign(int a,int b){
*h_a = a;
*h_b = b;
hipMemcpy(d_a,h_a,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,sizeof(int),hipMemcpyHostToDevice);
}
__global__ void add(int *a,int *b,int *c){
*c += *a + *b;
}
__host__ void process(){
add<<<1,1>>>(d_a,d_b,d_c);
}
__host__ int get(){
hipMemcpy(h_c,d_c,sizeof(int),hipMemcpyDeviceToHost);
return *h_c;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
int *d_a,*d_b,*d_c;
int *h_a,*h_b,*h_c;
__host__ void init(){
h_a = (int*)malloc(sizeof(int));
h_b = (int*)malloc(sizeof(int));
h_c = (int*)malloc(sizeof(int));
*h_c=0;
hipMalloc((void**)&d_a,sizeof(int));
hipMalloc((void**)&d_b,sizeof(int));
hipMalloc((void**)&d_c,sizeof(int));
hipMemcpy(d_c,h_c,sizeof(int),hipMemcpyHostToDevice);
}
__host__ void assign(int a,int b){
*h_a = a;
*h_b = b;
hipMemcpy(d_a,h_a,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,sizeof(int),hipMemcpyHostToDevice);
}
__global__ void add(int *a,int *b,int *c){
*c += *a + *b;
}
__host__ void process(){
add<<<1,1>>>(d_a,d_b,d_c);
}
__host__ int get(){
hipMemcpy(h_c,d_c,sizeof(int),hipMemcpyDeviceToHost);
return *h_c;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s4
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
int *d_a,*d_b,*d_c;
int *h_a,*h_b,*h_c;
__host__ void init(){
h_a = (int*)malloc(sizeof(int));
h_b = (int*)malloc(sizeof(int));
h_c = (int*)malloc(sizeof(int));
*h_c=0;
hipMalloc((void**)&d_a,sizeof(int));
hipMalloc((void**)&d_b,sizeof(int));
hipMalloc((void**)&d_c,sizeof(int));
hipMemcpy(d_c,h_c,sizeof(int),hipMemcpyHostToDevice);
}
__host__ void assign(int a,int b){
*h_a = a;
*h_b = b;
hipMemcpy(d_a,h_a,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,sizeof(int),hipMemcpyHostToDevice);
}
__global__ void add(int *a,int *b,int *c){
*c += *a + *b;
}
__host__ void process(){
add<<<1,1>>>(d_a,d_b,d_c);
}
__host__ int get(){
hipMemcpy(h_c,d_c,sizeof(int),hipMemcpyDeviceToHost);
return *h_c;
} | .text
.file "detour.hip"
.globl _Z4initv # -- Begin function _Z4initv
.p2align 4, 0x90
.type _Z4initv,@function
_Z4initv: # @_Z4initv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $4, %edi
callq malloc
movq %rax, h_a(%rip)
movl $4, %edi
callq malloc
movq %rax, h_b(%rip)
movl $4, %edi
callq malloc
movq %rax, h_c(%rip)
movl $0, (%rax)
movl $d_a, %edi
movl $4, %esi
callq hipMalloc
movl $d_b, %edi
movl $4, %esi
callq hipMalloc
movl $d_c, %edi
movl $4, %esi
callq hipMalloc
movq d_c(%rip), %rdi
movq h_c(%rip), %rsi
movl $4, %edx
movl $1, %ecx
popq %rax
.cfi_def_cfa_offset 8
jmp hipMemcpy # TAILCALL
.Lfunc_end0:
.size _Z4initv, .Lfunc_end0-_Z4initv
.cfi_endproc
# -- End function
.globl _Z6assignii # -- Begin function _Z6assignii
.p2align 4, 0x90
.type _Z6assignii,@function
_Z6assignii: # @_Z6assignii
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq h_a(%rip), %rax
movl %edi, (%rax)
movq h_b(%rip), %rcx
movl %esi, (%rcx)
movq d_a(%rip), %rdi
movl $4, %edx
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
movq d_b(%rip), %rdi
movq h_b(%rip), %rsi
movl $4, %edx
movl $1, %ecx
popq %rax
.cfi_def_cfa_offset 8
jmp hipMemcpy # TAILCALL
.Lfunc_end1:
.size _Z6assignii, .Lfunc_end1-_Z6assignii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end2-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z7processv # -- Begin function _Z7processv
.p2align 4, 0x90
.type _Z7processv,@function
_Z7processv: # @_Z7processv
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB3_1
# %bb.2:
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 112
movq d_a(%rip), %rax
movq d_b(%rip), %rcx
movq d_c(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7processv, .Lfunc_end3-_Z7processv
.cfi_endproc
# -- End function
.globl _Z3getv # -- Begin function _Z3getv
.p2align 4, 0x90
.type _Z3getv,@function
_Z3getv: # @_Z3getv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq h_c(%rip), %rdi
movq d_c(%rip), %rsi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq h_c(%rip), %rax
movl (%rax), %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z3getv, .Lfunc_end4-_Z3getv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_a,@object # @d_a
.bss
.globl d_a
.p2align 3, 0x0
d_a:
.quad 0
.size d_a, 8
.type d_b,@object # @d_b
.globl d_b
.p2align 3, 0x0
d_b:
.quad 0
.size d_b, 8
.type d_c,@object # @d_c
.globl d_c
.p2align 3, 0x0
d_c:
.quad 0
.size d_c, 8
.type h_a,@object # @h_a
.globl h_a
.p2align 3, 0x0
h_a:
.quad 0
.size h_a, 8
.type h_b,@object # @h_b
.globl h_b
.p2align 3, 0x0
h_b:
.quad 0
.size h_b, 8
.type h_c,@object # @h_c
.globl h_c
.p2align 3, 0x0
h_c:
.quad 0
.size h_c, 8
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_a
.addrsig_sym d_b
.addrsig_sym d_c
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IADD3 R9, R0, R5, R2 ; /* 0x0000000500097210 */
/* 0x004fca0007ffe002 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s4
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000035dd_00000000-6_detour.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initv
.type _Z4initv, @function
_Z4initv:
.LFB2027:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $4, %edi
call malloc@PLT
movq %rax, h_a(%rip)
movl $4, %edi
call malloc@PLT
movq %rax, h_b(%rip)
movl $4, %edi
call malloc@PLT
movq %rax, h_c(%rip)
movl $0, (%rax)
movl $4, %esi
leaq d_a(%rip), %rdi
call cudaMalloc@PLT
movl $4, %esi
leaq d_b(%rip), %rdi
call cudaMalloc@PLT
movl $4, %esi
leaq d_c(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $4, %edx
movq h_c(%rip), %rsi
movq d_c(%rip), %rdi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size _Z4initv, .-_Z4initv
.globl _Z6assignii
.type _Z6assignii, @function
_Z6assignii:
.LFB2028:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq h_a(%rip), %rax
movl %edi, (%rax)
movq h_b(%rip), %rax
movl %esi, (%rax)
movl $1, %ecx
movl $4, %edx
movq h_a(%rip), %rsi
movq d_a(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq h_b(%rip), %rsi
movq d_b(%rip), %rdi
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2028:
.size _Z6assignii, .-_Z6assignii
.globl _Z3getv
.type _Z3getv, @function
_Z3getv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $2, %ecx
movl $4, %edx
movq d_c(%rip), %rsi
movq h_c(%rip), %rdi
call cudaMemcpy@PLT
movq h_c(%rip), %rax
movl (%rax), %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _Z3getv, .-_Z3getv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2055:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl _Z7processv
.type _Z7processv, @function
_Z7processv:
.LFB2029:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq d_c(%rip), %rdx
movq d_b(%rip), %rsi
movq d_a(%rip), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L17
.cfi_endproc
.LFE2029:
.size _Z7processv, .-_Z7processv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl h_c
.bss
.align 8
.type h_c, @object
.size h_c, 8
h_c:
.zero 8
.globl h_b
.align 8
.type h_b, @object
.size h_b, 8
h_b:
.zero 8
.globl h_a
.align 8
.type h_a, @object
.size h_a, 8
h_a:
.zero 8
.globl d_c
.align 8
.type d_c, @object
.size d_c, 8
d_c:
.zero 8
.globl d_b
.align 8
.type d_b, @object
.size d_b, 8
d_b:
.zero 8
.globl d_a
.align 8
.type d_a, @object
.size d_a, 8
d_a:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "detour.hip"
.globl _Z4initv # -- Begin function _Z4initv
.p2align 4, 0x90
.type _Z4initv,@function
_Z4initv: # @_Z4initv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $4, %edi
callq malloc
movq %rax, h_a(%rip)
movl $4, %edi
callq malloc
movq %rax, h_b(%rip)
movl $4, %edi
callq malloc
movq %rax, h_c(%rip)
movl $0, (%rax)
movl $d_a, %edi
movl $4, %esi
callq hipMalloc
movl $d_b, %edi
movl $4, %esi
callq hipMalloc
movl $d_c, %edi
movl $4, %esi
callq hipMalloc
movq d_c(%rip), %rdi
movq h_c(%rip), %rsi
movl $4, %edx
movl $1, %ecx
popq %rax
.cfi_def_cfa_offset 8
jmp hipMemcpy # TAILCALL
.Lfunc_end0:
.size _Z4initv, .Lfunc_end0-_Z4initv
.cfi_endproc
# -- End function
.globl _Z6assignii # -- Begin function _Z6assignii
.p2align 4, 0x90
.type _Z6assignii,@function
_Z6assignii: # @_Z6assignii
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq h_a(%rip), %rax
movl %edi, (%rax)
movq h_b(%rip), %rcx
movl %esi, (%rcx)
movq d_a(%rip), %rdi
movl $4, %edx
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
movq d_b(%rip), %rdi
movq h_b(%rip), %rsi
movl $4, %edx
movl $1, %ecx
popq %rax
.cfi_def_cfa_offset 8
jmp hipMemcpy # TAILCALL
.Lfunc_end1:
.size _Z6assignii, .Lfunc_end1-_Z6assignii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end2-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z7processv # -- Begin function _Z7processv
.p2align 4, 0x90
.type _Z7processv,@function
_Z7processv: # @_Z7processv
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB3_1
# %bb.2:
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 112
movq d_a(%rip), %rax
movq d_b(%rip), %rcx
movq d_c(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7processv, .Lfunc_end3-_Z7processv
.cfi_endproc
# -- End function
.globl _Z3getv # -- Begin function _Z3getv
.p2align 4, 0x90
.type _Z3getv,@function
_Z3getv: # @_Z3getv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq h_c(%rip), %rdi
movq d_c(%rip), %rsi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq h_c(%rip), %rax
movl (%rax), %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z3getv, .Lfunc_end4-_Z3getv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_a,@object # @d_a
.bss
.globl d_a
.p2align 3, 0x0
d_a:
.quad 0
.size d_a, 8
.type d_b,@object # @d_b
.globl d_b
.p2align 3, 0x0
d_b:
.quad 0
.size d_b, 8
.type d_c,@object # @d_c
.globl d_c
.p2align 3, 0x0
d_c:
.quad 0
.size d_c, 8
.type h_a,@object # @h_a
.globl h_a
.p2align 3, 0x0
h_a:
.quad 0
.size h_a, 8
.type h_b,@object # @h_b
.globl h_b
.p2align 3, 0x0
h_b:
.quad 0
.size h_b, 8
.type h_c,@object # @h_c
.globl h_c
.p2align 3, 0x0
h_c:
.quad 0
.size h_c, 8
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_a
.addrsig_sym d_b
.addrsig_sym d_c
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void vecAdd(float * in1, float * in2, float * out, int len) {
//@@ Insert code to implement vector addition here
int i = threadIdx.x+blockDim.x*blockIdx.x;
if(i<len) out[i] = in1[i] + in2[i];
} | code for sm_80
Function : _Z6vecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void vecAdd(float * in1, float * in2, float * out, int len) {
//@@ Insert code to implement vector addition here
int i = threadIdx.x+blockDim.x*blockIdx.x;
if(i<len) out[i] = in1[i] + in2[i];
} | .file "tmpxft_0018a7fd_00000000-6_vecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void vecAdd(float * in1, float * in2, float * out, int len) {
//@@ Insert code to implement vector addition here
int i = threadIdx.x+blockDim.x*blockIdx.x;
if(i<len) out[i] = in1[i] + in2[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecAdd(float * in1, float * in2, float * out, int len) {
//@@ Insert code to implement vector addition here
int i = threadIdx.x+blockDim.x*blockIdx.x;
if(i<len) out[i] = in1[i] + in2[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecAdd(float * in1, float * in2, float * out, int len) {
//@@ Insert code to implement vector addition here
int i = threadIdx.x+blockDim.x*blockIdx.x;
if(i<len) out[i] = in1[i] + in2[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_i
.globl _Z6vecAddPfS_S_i
.p2align 8
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_i, .Lfunc_end0-_Z6vecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecAdd(float * in1, float * in2, float * out, int len) {
//@@ Insert code to implement vector addition here
int i = threadIdx.x+blockDim.x*blockIdx.x;
if(i<len) out[i] = in1[i] + in2[i];
} | .text
.file "vecAdd.hip"
.globl _Z21__device_stub__vecAddPfS_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_i,@function
_Z21__device_stub__vecAddPfS_S_i: # @_Z21__device_stub__vecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_i,@object # @_Z6vecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_i
.p2align 3, 0x0
_Z6vecAddPfS_S_i:
.quad _Z21__device_stub__vecAddPfS_S_i
.size _Z6vecAddPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_i
.globl _Z6vecAddPfS_S_i
.p2align 8
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_i, .Lfunc_end0-_Z6vecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018a7fd_00000000-6_vecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecAdd.hip"
.globl _Z21__device_stub__vecAddPfS_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_i,@function
_Z21__device_stub__vecAddPfS_S_i: # @_Z21__device_stub__vecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_i,@object # @_Z6vecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_i
.p2align 3, 0x0
_Z6vecAddPfS_S_i:
.quad _Z21__device_stub__vecAddPfS_S_i
.size _Z6vecAddPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*--------------------------------------------------------------------*/
/* CUDA utility Library */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "cuda.h"
int nblock_size = 64;
int ngrid_size = 1;
int maxgsx = 65535;
int mmcc = 0;
static int devid;
static cudaError_t crc;
__global__ void emptyKernel() {}
/*--------------------------------------------------------------------*/
extern "C" void gpu_setgbsize(int nblock) {
/* set blocksize */
nblock_size = nblock;
return;
}
/*--------------------------------------------------------------------*/
extern "C" int getmmcc() {
/* get major and minor computer capability */
return mmcc;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate(float **g_f, int nsize, int *irc) {
/* allocate global float memory on GPU, return pointer to C */
void *gptr;
crc = cudaMalloc(&gptr,sizeof(float)*nsize);
if (crc) {
printf("cudaMalloc float Error=%d:%s,l=%d\n",crc,
cudaGetErrorString(crc),nsize);
*irc = 1;
}
*g_f = (float *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_iallocate(int **g_i, int nsize, int *irc) {
/* allocate global integer memory on GPU, return pointer to C */
void *gptr;
crc = cudaMalloc(&gptr,sizeof(int)*nsize);
if (crc) {
printf("cudaMalloc int Error=%d:%s,l=%d\n",crc,
cudaGetErrorString(crc),nsize);
*irc = 1;
}
*g_i = (int *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_callocate(float2 **g_c, int nsize, int *irc) {
/* allocate global float2 memory on GPU, return pointer to C */
void *gptr;
crc = cudaMalloc(&gptr,sizeof(float2)*nsize);
if (crc) {
printf("cudaMalloc float2 Error=%d:%s,l=%d\n",crc,
cudaGetErrorString(crc),nsize);
*irc = 1;
}
*g_c = (float2 *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate(void *g_d, int *irc) {
/* deallocate global memory on GPU */
crc = cudaFree(g_d);
if (crc) {
printf("cudaFree Error=%d:%s\n",crc,cudaGetErrorString(crc));
*irc = 1;
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin(float *f, float *g_f, int nsize) {
/* copy float array from host memory to global GPU memory */
crc = cudaMemcpy((void *)g_f,f,sizeof(float)*nsize,
cudaMemcpyHostToDevice);
if (crc) {
printf("cudaMemcpyHostToDevice float Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout(float *f, float *g_f, int nsize) {
/* copy float array from global GPU memory to host memory */
crc = cudaMemcpy(f,(void *)g_f,sizeof(float)*nsize,
cudaMemcpyDeviceToHost);
if (crc) {
printf("cudaMemcpyDeviceToHost float Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyin(int *f, int *g_f, int nsize) {
/* copy int array from host memory to global GPU memory */
crc = cudaMemcpy((void *)g_f,f,sizeof(int)*nsize,
cudaMemcpyHostToDevice);
if (crc) {
printf("cudaMemcpyHostToDevice int Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyout(int *f, int *g_f, int nsize) {
/* copy int array from global GPU memory to host memory */
crc = cudaMemcpy(f,(void *)g_f,sizeof(int)*nsize,
cudaMemcpyDeviceToHost);
if (crc) {
printf("cudaMemcpyDeviceToHost int Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyin(float2 *f, float2 *g_f, int nsize) {
/* copy float2 array from host memory to global GPU memory */
crc = cudaMemcpy((void *)g_f,f,sizeof(float2)*nsize,
cudaMemcpyHostToDevice);
if (crc) {
printf("cudaMemcpyHostToDevice float2 Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyout(float2 *f, float2 *g_f, int nsize) {
/* copy float2 array from global GPU memory to host memory */
crc = cudaMemcpy(f,(void *)g_f,sizeof(float2)*nsize,
cudaMemcpyDeviceToHost);
if (crc) {
printf("cudaMemcpyDeviceToHost float2 Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_zfmem(float *g_f, int nsize) {
/* initialize float array in global GPU memory to zero */
crc = cudaMemset((void *)g_f,0,sizeof(float)*nsize);
if (crc) {
printf("cudaMemset Error=%d:%s\n",crc,cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_set_cache_size(int nscache) {
/* request preferred cache size, requires CUDA 3.2 or higher */
/* nscache = (0,1,2) = (no,small,big) cache size */
cudaFuncCache cpref;
if ((nscache < 0) || (nscache > 2))
return;
if (nscache==0)
cpref = cudaFuncCachePreferNone;
else if (nscache==1)
cpref = cudaFuncCachePreferShared;
else if (nscache==2)
cpref = cudaFuncCachePreferL1;
crc = cudaThreadSetCacheConfig(cpref);
/* crc = cudaDeviceSetCacheConfig(cpref); */
if (crc) {
printf("cudaThreadSetCacheConfig error=%d:%s\n",crc,
cudaGetErrorString(crc));
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel() {
int ngx, ngy;
ngx = nblock_size < 32768 ? nblock_size : 32768;
ngy = (ngrid_size - 1)/ngx + 1;
dim3 dimBlock(nblock_size,1);
dim3 dimGrid(ngx,ngy);
crc = cudaGetLastError();
emptyKernel<<<dimGrid,dimBlock>>>();
cudaThreadSynchronize();
crc = cudaGetLastError();
if (crc) {
printf("emptyKernel error=%d:%s\n",crc,cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu(int dev, int *irc) {
/* initialize CUDA with device dev or selects best GPU available */
/* searches throughs devices, selects the device with the most compute */
/* units, and saves the device id devid */
/* if dev is a valid device, it is used, otherwise the GPU with the */
/* most multi-processors is selected */
/* error code is modified only if there is an error */
int maxcpus = 0, jm = -1;
int j, ndevs, maxunits;
unsigned long msize;
double z;
struct cudaDeviceProp prop;
/* returns number of device */
crc = cudaGetDeviceCount(&ndevs);
if (crc) {
printf("cudaGetDeviceCount Error=%i:%s\n",crc,
cudaGetErrorString(crc));
*irc = 1;
return;
}
/* get information about devices */
for (j = 0; j < ndevs; j++) {
crc = cudaGetDeviceProperties(&prop,j);
if (crc) {
printf("cudaGetDeviceProperties Error=%i:%s\n",crc,
cudaGetErrorString(crc));
prop.name[0] = 0;
}
maxunits = prop.multiProcessorCount;
if (dev <= 0) {
printf("j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n",
j,prop.name,maxunits);
msize = prop.totalGlobalMem;
z = ((double) msize)/1073741824.0;
mmcc = 10*prop.major + prop.minor;
printf(" CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n",
msize,(float) z,mmcc);
if (maxunits > maxcpus) {
maxcpus = maxunits;
jm = j;
}
}
}
devid = jm;
if (dev >= 0)
devid = dev % ndevs;
printf("using device j=%i\n",devid);
/* get properties for this device */
crc = cudaGetDeviceProperties(&prop,devid);
maxgsx = prop.maxGridSize[0];
mmcc = 10*prop.major + prop.minor;
/* set device */
crc = cudaSetDevice(devid);
if (crc) {
printf("cudaSetDevice Error=%i:%s\n",crc,
cudaGetErrorString(crc));
*irc = 1;
return;
}
/* run empty kernel */
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu() {
/* terminate CUDA */
crc = cudaThreadExit();
if (crc) {
printf("cudaThreadExit Error=%d:%s\n",crc,cudaGetErrorString(crc));
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpu_setgbsize_(int *nblock) {
gpu_setgbsize(*nblock);
return;
}
/*--------------------------------------------------------------------*/
extern "C" int getmmcc_() {
/* get major and minor computer capability */
return getmmcc();
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float memory on GPU, return pointer to Fortran */
float *fptr;
gpu_fallocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_iallocate_(unsigned long *gp_i, int *nsize,
int *irc) {
/* allocate global integer memory on GPU, return pointer to Fortran */
int *iptr;
gpu_iallocate(&iptr,*nsize,irc);
*gp_i = (long )iptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_callocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float2 memory on GPU, return pointer */
/* to Fortran */
float2 *fptr;
gpu_callocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate_(unsigned long *gp_d, int *irc) {
/* deallocate global memory on GPU, return pointer to Fortran */
void *d;
d = (void *)*gp_d;
gpu_deallocate(d,irc);
*gp_d = 0;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from main memory to global GPU memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from global GPU memory to main memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyin_(int *f, unsigned long *gp_f, int *nsize) {
/* copy int array from main memory to global GPU memory */
int *g_f;
g_f = (int *)*gp_f;
gpu_icopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyout_(int *f, unsigned long *gp_f, int *nsize) {
/* copy int array from global GPU memory to main memory */
int *g_f;
g_f = (int *)*gp_f;
gpu_icopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyin_(float2 *f, unsigned long *gp_f,
int *nsize) {
/* copy float2 array from main memory to global GPU memory */
float2 *g_f;
g_f = (float2 *)*gp_f;
gpu_ccopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyout_(float2 *f, unsigned long *gp_f,
int *nsize) {
/* copy float2 array from global GPU memory to main memory */
float2 *g_f;
g_f = (float2 *)*gp_f;
gpu_ccopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_zfmem_(unsigned long *gp_f, int *nsize) {
float *g_f;
g_f = (float *)*gp_f;
gpu_zfmem(g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_set_cache_size_(int *nscache) {
gpu_set_cache_size(*nscache);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel_() {
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu_(int *dev, int *irc) {
init_cu(*dev,irc);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu_() {
end_cu();
return;
} | code for sm_80
Function : _Z11emptyKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*--------------------------------------------------------------------*/
/* CUDA utility Library */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "cuda.h"
int nblock_size = 64;
int ngrid_size = 1;
int maxgsx = 65535;
int mmcc = 0;
static int devid;
static cudaError_t crc;
__global__ void emptyKernel() {}
/*--------------------------------------------------------------------*/
extern "C" void gpu_setgbsize(int nblock) {
/* set blocksize */
nblock_size = nblock;
return;
}
/*--------------------------------------------------------------------*/
extern "C" int getmmcc() {
/* get major and minor computer capability */
return mmcc;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate(float **g_f, int nsize, int *irc) {
/* allocate global float memory on GPU, return pointer to C */
void *gptr;
crc = cudaMalloc(&gptr,sizeof(float)*nsize);
if (crc) {
printf("cudaMalloc float Error=%d:%s,l=%d\n",crc,
cudaGetErrorString(crc),nsize);
*irc = 1;
}
*g_f = (float *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_iallocate(int **g_i, int nsize, int *irc) {
/* allocate global integer memory on GPU, return pointer to C */
void *gptr;
crc = cudaMalloc(&gptr,sizeof(int)*nsize);
if (crc) {
printf("cudaMalloc int Error=%d:%s,l=%d\n",crc,
cudaGetErrorString(crc),nsize);
*irc = 1;
}
*g_i = (int *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_callocate(float2 **g_c, int nsize, int *irc) {
/* allocate global float2 memory on GPU, return pointer to C */
void *gptr;
crc = cudaMalloc(&gptr,sizeof(float2)*nsize);
if (crc) {
printf("cudaMalloc float2 Error=%d:%s,l=%d\n",crc,
cudaGetErrorString(crc),nsize);
*irc = 1;
}
*g_c = (float2 *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate(void *g_d, int *irc) {
/* deallocate global memory on GPU */
crc = cudaFree(g_d);
if (crc) {
printf("cudaFree Error=%d:%s\n",crc,cudaGetErrorString(crc));
*irc = 1;
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin(float *f, float *g_f, int nsize) {
/* copy float array from host memory to global GPU memory */
crc = cudaMemcpy((void *)g_f,f,sizeof(float)*nsize,
cudaMemcpyHostToDevice);
if (crc) {
printf("cudaMemcpyHostToDevice float Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout(float *f, float *g_f, int nsize) {
/* copy float array from global GPU memory to host memory */
crc = cudaMemcpy(f,(void *)g_f,sizeof(float)*nsize,
cudaMemcpyDeviceToHost);
if (crc) {
printf("cudaMemcpyDeviceToHost float Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyin(int *f, int *g_f, int nsize) {
/* copy int array from host memory to global GPU memory */
crc = cudaMemcpy((void *)g_f,f,sizeof(int)*nsize,
cudaMemcpyHostToDevice);
if (crc) {
printf("cudaMemcpyHostToDevice int Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyout(int *f, int *g_f, int nsize) {
/* copy int array from global GPU memory to host memory */
crc = cudaMemcpy(f,(void *)g_f,sizeof(int)*nsize,
cudaMemcpyDeviceToHost);
if (crc) {
printf("cudaMemcpyDeviceToHost int Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyin(float2 *f, float2 *g_f, int nsize) {
/* copy float2 array from host memory to global GPU memory */
crc = cudaMemcpy((void *)g_f,f,sizeof(float2)*nsize,
cudaMemcpyHostToDevice);
if (crc) {
printf("cudaMemcpyHostToDevice float2 Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyout(float2 *f, float2 *g_f, int nsize) {
/* copy float2 array from global GPU memory to host memory */
crc = cudaMemcpy(f,(void *)g_f,sizeof(float2)*nsize,
cudaMemcpyDeviceToHost);
if (crc) {
printf("cudaMemcpyDeviceToHost float2 Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_zfmem(float *g_f, int nsize) {
/* initialize float array in global GPU memory to zero */
crc = cudaMemset((void *)g_f,0,sizeof(float)*nsize);
if (crc) {
printf("cudaMemset Error=%d:%s\n",crc,cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_set_cache_size(int nscache) {
/* request preferred cache size, requires CUDA 3.2 or higher */
/* nscache = (0,1,2) = (no,small,big) cache size */
cudaFuncCache cpref;
if ((nscache < 0) || (nscache > 2))
return;
if (nscache==0)
cpref = cudaFuncCachePreferNone;
else if (nscache==1)
cpref = cudaFuncCachePreferShared;
else if (nscache==2)
cpref = cudaFuncCachePreferL1;
crc = cudaThreadSetCacheConfig(cpref);
/* crc = cudaDeviceSetCacheConfig(cpref); */
if (crc) {
printf("cudaThreadSetCacheConfig error=%d:%s\n",crc,
cudaGetErrorString(crc));
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel() {
int ngx, ngy;
ngx = nblock_size < 32768 ? nblock_size : 32768;
ngy = (ngrid_size - 1)/ngx + 1;
dim3 dimBlock(nblock_size,1);
dim3 dimGrid(ngx,ngy);
crc = cudaGetLastError();
emptyKernel<<<dimGrid,dimBlock>>>();
cudaThreadSynchronize();
crc = cudaGetLastError();
if (crc) {
printf("emptyKernel error=%d:%s\n",crc,cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu(int dev, int *irc) {
/* initialize CUDA with device dev or selects best GPU available */
/* searches throughs devices, selects the device with the most compute */
/* units, and saves the device id devid */
/* if dev is a valid device, it is used, otherwise the GPU with the */
/* most multi-processors is selected */
/* error code is modified only if there is an error */
int maxcpus = 0, jm = -1;
int j, ndevs, maxunits;
unsigned long msize;
double z;
struct cudaDeviceProp prop;
/* returns number of device */
crc = cudaGetDeviceCount(&ndevs);
if (crc) {
printf("cudaGetDeviceCount Error=%i:%s\n",crc,
cudaGetErrorString(crc));
*irc = 1;
return;
}
/* get information about devices */
for (j = 0; j < ndevs; j++) {
crc = cudaGetDeviceProperties(&prop,j);
if (crc) {
printf("cudaGetDeviceProperties Error=%i:%s\n",crc,
cudaGetErrorString(crc));
prop.name[0] = 0;
}
maxunits = prop.multiProcessorCount;
if (dev <= 0) {
printf("j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n",
j,prop.name,maxunits);
msize = prop.totalGlobalMem;
z = ((double) msize)/1073741824.0;
mmcc = 10*prop.major + prop.minor;
printf(" CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n",
msize,(float) z,mmcc);
if (maxunits > maxcpus) {
maxcpus = maxunits;
jm = j;
}
}
}
devid = jm;
if (dev >= 0)
devid = dev % ndevs;
printf("using device j=%i\n",devid);
/* get properties for this device */
crc = cudaGetDeviceProperties(&prop,devid);
maxgsx = prop.maxGridSize[0];
mmcc = 10*prop.major + prop.minor;
/* set device */
crc = cudaSetDevice(devid);
if (crc) {
printf("cudaSetDevice Error=%i:%s\n",crc,
cudaGetErrorString(crc));
*irc = 1;
return;
}
/* run empty kernel */
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu() {
/* terminate CUDA */
crc = cudaThreadExit();
if (crc) {
printf("cudaThreadExit Error=%d:%s\n",crc,cudaGetErrorString(crc));
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpu_setgbsize_(int *nblock) {
gpu_setgbsize(*nblock);
return;
}
/*--------------------------------------------------------------------*/
extern "C" int getmmcc_() {
/* get major and minor computer capability */
return getmmcc();
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float memory on GPU, return pointer to Fortran */
float *fptr;
gpu_fallocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_iallocate_(unsigned long *gp_i, int *nsize,
int *irc) {
/* allocate global integer memory on GPU, return pointer to Fortran */
int *iptr;
gpu_iallocate(&iptr,*nsize,irc);
*gp_i = (long )iptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_callocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float2 memory on GPU, return pointer */
/* to Fortran */
float2 *fptr;
gpu_callocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate_(unsigned long *gp_d, int *irc) {
/* deallocate global memory on GPU, return pointer to Fortran */
void *d;
d = (void *)*gp_d;
gpu_deallocate(d,irc);
*gp_d = 0;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from main memory to global GPU memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from global GPU memory to main memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyin_(int *f, unsigned long *gp_f, int *nsize) {
/* copy int array from main memory to global GPU memory */
int *g_f;
g_f = (int *)*gp_f;
gpu_icopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyout_(int *f, unsigned long *gp_f, int *nsize) {
/* copy int array from global GPU memory to main memory */
int *g_f;
g_f = (int *)*gp_f;
gpu_icopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyin_(float2 *f, unsigned long *gp_f,
int *nsize) {
/* copy float2 array from main memory to global GPU memory */
float2 *g_f;
g_f = (float2 *)*gp_f;
gpu_ccopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyout_(float2 *f, unsigned long *gp_f,
int *nsize) {
/* copy float2 array from global GPU memory to main memory */
float2 *g_f;
g_f = (float2 *)*gp_f;
gpu_ccopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_zfmem_(unsigned long *gp_f, int *nsize) {
float *g_f;
g_f = (float *)*gp_f;
gpu_zfmem(g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_set_cache_size_(int *nscache) {
gpu_set_cache_size(*nscache);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel_() {
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu_(int *dev, int *irc) {
init_cu(*dev,irc);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu_() {
end_cu();
return;
} | .file "tmpxft_00180aae_00000000-6_gpulib2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl gpu_setgbsize
.type gpu_setgbsize, @function
gpu_setgbsize:
.LFB2057:
.cfi_startproc
endbr64
movl %edi, nblock_size(%rip)
ret
.cfi_endproc
.LFE2057:
.size gpu_setgbsize, .-gpu_setgbsize
.globl getmmcc
.type getmmcc, @function
getmmcc:
.LFB2058:
.cfi_startproc
endbr64
movl mmcc(%rip), %eax
ret
.cfi_endproc
.LFE2058:
.size getmmcc, .-getmmcc
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaMalloc float Error=%d:%s,l=%d\n"
.text
.globl gpu_fallocate
.type gpu_fallocate, @function
gpu_fallocate:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq %esi, %rsi
salq $2, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L9
.L6:
movq (%rsp), %rax
movq %rax, 0(%rbp)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %r8d
movl _ZL3crc(%rip), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, (%r12)
jmp .L6
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size gpu_fallocate, .-gpu_fallocate
.section .rodata.str1.8
.align 8
.LC1:
.string "cudaMalloc int Error=%d:%s,l=%d\n"
.text
.globl gpu_iallocate
.type gpu_iallocate, @function
gpu_iallocate:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq %esi, %rsi
salq $2, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L15
.L12:
movq (%rsp), %rax
movq %rax, 0(%rbp)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %r8d
movl _ZL3crc(%rip), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, (%r12)
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size gpu_iallocate, .-gpu_iallocate
.section .rodata.str1.8
.align 8
.LC2:
.string "cudaMalloc float2 Error=%d:%s,l=%d\n"
.text
.globl gpu_callocate
.type gpu_callocate, @function
gpu_callocate:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq %esi, %rsi
salq $3, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L21
.L18:
movq (%rsp), %rax
movq %rax, 0(%rbp)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %r8d
movl _ZL3crc(%rip), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, (%r12)
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size gpu_callocate, .-gpu_callocate
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "cudaFree Error=%d:%s\n"
.text
.globl gpu_deallocate
.type gpu_deallocate, @function
gpu_deallocate:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
call cudaFree@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L26
.L23:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, (%rbx)
jmp .L23
.cfi_endproc
.LFE2062:
.size gpu_deallocate, .-gpu_deallocate
.section .rodata.str1.8
.align 8
.LC4:
.string "cudaMemcpyHostToDevice float Error=%d:%s\n"
.text
.globl gpu_fcopyin
.type gpu_fcopyin, @function
gpu_fcopyin:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rsi, %rdi
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rax, %rsi
call cudaMemcpy@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L30
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size gpu_fcopyin, .-gpu_fcopyin
.section .rodata.str1.8
.align 8
.LC5:
.string "cudaMemcpyDeviceToHost float Error=%d:%s\n"
.text
.globl gpu_fcopyout
.type gpu_fcopyout, @function
gpu_fcopyout:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
call cudaMemcpy@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L34
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size gpu_fcopyout, .-gpu_fcopyout
.section .rodata.str1.8
.align 8
.LC6:
.string "cudaMemcpyHostToDevice int Error=%d:%s\n"
.text
.globl gpu_icopyin
.type gpu_icopyin, @function
gpu_icopyin:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rsi, %rdi
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rax, %rsi
call cudaMemcpy@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L38
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size gpu_icopyin, .-gpu_icopyin
.section .rodata.str1.8
.align 8
.LC7:
.string "cudaMemcpyDeviceToHost int Error=%d:%s\n"
.text
.globl gpu_icopyout
.type gpu_icopyout, @function
gpu_icopyout:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
call cudaMemcpy@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L42
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size gpu_icopyout, .-gpu_icopyout
.section .rodata.str1.8
.align 8
.LC8:
.string "cudaMemcpyHostToDevice float2 Error=%d:%s\n"
.text
.globl gpu_ccopyin
.type gpu_ccopyin, @function
gpu_ccopyin:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rsi, %rdi
movslq %edx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %rax, %rsi
call cudaMemcpy@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L46
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size gpu_ccopyin, .-gpu_ccopyin
.section .rodata.str1.8
.align 8
.LC9:
.string "cudaMemcpyDeviceToHost float2 Error=%d:%s\n"
.text
.globl gpu_ccopyout
.type gpu_ccopyout, @function
gpu_ccopyout:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edx, %rdx
salq $3, %rdx
movl $2, %ecx
call cudaMemcpy@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L50
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2068:
.size gpu_ccopyout, .-gpu_ccopyout
.section .rodata.str1.1
.LC10:
.string "cudaMemset Error=%d:%s\n"
.text
.globl gpu_zfmem
.type gpu_zfmem, @function
gpu_zfmem:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %esi, %rdx
salq $2, %rdx
movl $0, %esi
call cudaMemset@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L54
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2069:
.size gpu_zfmem, .-gpu_zfmem
.section .rodata.str1.8
.align 8
.LC11:
.string "cudaThreadSetCacheConfig error=%d:%s\n"
.text
.globl gpu_set_cache_size
.type gpu_set_cache_size, @function
gpu_set_cache_size:
.LFB2070:
.cfi_startproc
endbr64
cmpl $2, %edi
ja .L61
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %eax
testl %edi, %edi
je .L57
cmpl $1, %edi
setne %al
movzbl %al, %eax
addl $1, %eax
.L57:
movl %eax, %edi
call cudaThreadSetCacheConfig@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L64
.L55:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L55
.L61:
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size gpu_set_cache_size, .-gpu_set_cache_size
.section .rodata.str1.1
.LC12:
.string "cudaThreadExit Error=%d:%s\n"
.text
.globl end_cu
.type end_cu, @function
end_cu:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaThreadExit@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L68
.L65:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L65
.cfi_endproc
.LFE2073:
.size end_cu, .-end_cu
.globl gpu_setgbsize_
.type gpu_setgbsize_, @function
gpu_setgbsize_:
.LFB2074:
.cfi_startproc
endbr64
movl (%rdi), %eax
movl %eax, nblock_size(%rip)
ret
.cfi_endproc
.LFE2074:
.size gpu_setgbsize_, .-gpu_setgbsize_
.globl getmmcc_
.type getmmcc_, @function
getmmcc_:
.LFB2075:
.cfi_startproc
endbr64
movl mmcc(%rip), %eax
ret
.cfi_endproc
.LFE2075:
.size getmmcc_, .-getmmcc_
.globl gpu_fallocate_
.type gpu_fallocate_, @function
gpu_fallocate_:
.LFB2076:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl (%rsi), %esi
movq %rsp, %rdi
call gpu_fallocate
movq (%rsp), %rax
movq %rax, (%rbx)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L74:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2076:
.size gpu_fallocate_, .-gpu_fallocate_
.globl gpu_iallocate_
.type gpu_iallocate_, @function
gpu_iallocate_:
.LFB2077:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl (%rsi), %esi
movq %rsp, %rdi
call gpu_iallocate
movq (%rsp), %rax
movq %rax, (%rbx)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L78
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size gpu_iallocate_, .-gpu_iallocate_
.globl gpu_callocate_
.type gpu_callocate_, @function
gpu_callocate_:
.LFB2078:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl (%rsi), %esi
movq %rsp, %rdi
call gpu_callocate
movq (%rsp), %rax
movq %rax, (%rbx)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L82
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2078:
.size gpu_callocate_, .-gpu_callocate_
.globl gpu_deallocate_
.type gpu_deallocate_, @function
gpu_deallocate_:
.LFB2079:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq (%rdi), %rdi
call gpu_deallocate
movq $0, (%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2079:
.size gpu_deallocate_, .-gpu_deallocate_
.globl gpu_fcopyin_
.type gpu_fcopyin_, @function
gpu_fcopyin_:
.LFB2080:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdx), %edx
movq (%rsi), %rsi
call gpu_fcopyin
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2080:
.size gpu_fcopyin_, .-gpu_fcopyin_
.globl gpu_fcopyout_
.type gpu_fcopyout_, @function
gpu_fcopyout_:
.LFB2081:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdx), %edx
movq (%rsi), %rsi
call gpu_fcopyout
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2081:
.size gpu_fcopyout_, .-gpu_fcopyout_
.globl gpu_icopyin_
.type gpu_icopyin_, @function
gpu_icopyin_:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdx), %edx
movq (%rsi), %rsi
call gpu_icopyin
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size gpu_icopyin_, .-gpu_icopyin_
.globl gpu_icopyout_
.type gpu_icopyout_, @function
gpu_icopyout_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdx), %edx
movq (%rsi), %rsi
call gpu_icopyout
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size gpu_icopyout_, .-gpu_icopyout_
.globl gpu_ccopyin_
.type gpu_ccopyin_, @function
gpu_ccopyin_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdx), %edx
movq (%rsi), %rsi
call gpu_ccopyin
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size gpu_ccopyin_, .-gpu_ccopyin_
.globl gpu_ccopyout_
.type gpu_ccopyout_, @function
gpu_ccopyout_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdx), %edx
movq (%rsi), %rsi
call gpu_ccopyout
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size gpu_ccopyout_, .-gpu_ccopyout_
.globl gpu_zfmem_
.type gpu_zfmem_, @function
gpu_zfmem_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rsi), %esi
movq (%rdi), %rdi
call gpu_zfmem
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size gpu_zfmem_, .-gpu_zfmem_
.globl gpu_set_cache_size_
.type gpu_set_cache_size_, @function
gpu_set_cache_size_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdi), %edi
call gpu_set_cache_size
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size gpu_set_cache_size_, .-gpu_set_cache_size_
.globl end_cu_
.type end_cu_, @function
end_cu_:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call end_cu
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size end_cu_, .-end_cu_
.globl _Z30__device_stub__Z11emptyKernelvv
.type _Z30__device_stub__Z11emptyKernelvv, @function
_Z30__device_stub__Z11emptyKernelvv:
.LFB2115:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L107
.L103:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L108
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L107:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11emptyKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L103
.L108:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2115:
.size _Z30__device_stub__Z11emptyKernelvv, .-_Z30__device_stub__Z11emptyKernelvv
.globl _Z11emptyKernelv
.type _Z11emptyKernelv, @function
_Z11emptyKernelv:
.LFB2116:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11emptyKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2116:
.size _Z11emptyKernelv, .-_Z11emptyKernelv
.section .rodata.str1.1
.LC13:
.string "emptyKernel error=%d:%s\n"
.text
.globl emptykernel
.type emptykernel, @function
emptykernel:
.LFB2071:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl nblock_size(%rip), %esi
movl $32768, %ecx
cmpl %ecx, %esi
cmovle %esi, %ecx
movl ngrid_size(%rip), %eax
subl $1, %eax
cltd
idivl %ecx
addl $1, %eax
movl %esi, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl %ecx, 20(%rsp)
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L115
.L112:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L116
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L115:
.cfi_restore_state
call _Z30__device_stub__Z11emptyKernelvv
jmp .L112
.L116:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size emptykernel, .-emptykernel
.section .rodata.str1.8
.align 8
.LC14:
.string "cudaGetDeviceCount Error=%i:%s\n"
.align 8
.LC15:
.string "cudaGetDeviceProperties Error=%i:%s\n"
.align 8
.LC16:
.string "j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n"
.align 8
.LC18:
.string " CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n"
.section .rodata.str1.1
.LC19:
.string "using device j=%i\n"
.LC20:
.string "cudaSetDevice Error=%i:%s\n"
.text
.globl init_cu
.type init_cu, @function
init_cu:
.LFB2072:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1080, %rsp
.cfi_def_cfa_offset 1136
movl %edi, %ebp
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L118
movl 28(%rsp), %ecx
movl $0, %ebx
movl $-1, %r13d
movl $0, %r14d
leaq .LC15(%rip), %r15
testl %ecx, %ecx
jg .L119
.L120:
testl %ebp, %ebp
js .L126
movl %ebp, %eax
cltd
idivl %ecx
movl %edx, %r13d
.L126:
movl %r13d, _ZL5devid(%rip)
movl %r13d, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movl _ZL5devid(%rip), %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, _ZL3crc(%rip)
movl 368(%rsp), %eax
movl %eax, maxgsx(%rip)
movl 392(%rsp), %eax
leal (%rax,%rax,4), %edx
movl 396(%rsp), %eax
leal (%rax,%rdx,2), %eax
movl %eax, mmcc(%rip)
movl _ZL5devid(%rip), %edi
call cudaSetDevice@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
jne .L135
call emptykernel
.L117:
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L136
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L118:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L121
.L122:
testl %ebp, %ebp
jle .L137
.L123:
addl $1, %ebx
movl 28(%rsp), %ecx
cmpl %ebx, %ecx
jle .L120
.L119:
leaq 32(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, _ZL3crc(%rip)
testl %eax, %eax
je .L122
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movb $0, 32(%rsp)
jmp .L122
.L137:
movl 420(%rsp), %r12d
leaq 32(%rsp), %rcx
movl %r12d, %r8d
movl %ebx, %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
movl 392(%rsp), %eax
leal (%rax,%rax,4), %ecx
movl 396(%rsp), %eax
leal (%rax,%rcx,2), %ecx
movl %ecx, mmcc(%rip)
testq %rdx, %rdx
js .L124
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
.L125:
mulsd .LC17(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl %r14d, %r12d
jle .L123
movl %ebx, %r13d
movl %r12d, %r14d
jmp .L123
.L124:
movq %rdx, %rax
shrq %rax
movq %rdx, %rsi
andl $1, %esi
orq %rsi, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L125
.L135:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl _ZL3crc(%rip), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L121:
movq 8(%rsp), %rax
movl $1, (%rax)
jmp .L117
.L136:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size init_cu, .-init_cu
.globl init_cu_
.type init_cu_, @function
init_cu_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl (%rdi), %edi
call init_cu
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size init_cu_, .-init_cu_
.globl emptykernel_
.type emptykernel_, @function
emptykernel_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call emptykernel
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size emptykernel_, .-emptykernel_
.section .rodata.str1.1
.LC21:
.string "_Z11emptyKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2118:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z11emptyKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2118:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3crc
.comm _ZL3crc,4,4
.local _ZL5devid
.comm _ZL5devid,4,4
.globl mmcc
.bss
.align 4
.type mmcc, @object
.size mmcc, 4
mmcc:
.zero 4
.globl maxgsx
.data
.align 4
.type maxgsx, @object
.size maxgsx, 4
maxgsx:
.long 65535
.globl ngrid_size
.align 4
.type ngrid_size, @object
.size ngrid_size, 4
ngrid_size:
.long 1
.globl nblock_size
.align 4
.type nblock_size, @object
.size nblock_size, 4
nblock_size:
.long 64
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC17:
.long 0
.long 1041235968
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*--------------------------------------------------------------------*/
/* CUDA utility Library */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "cuda.h"
int nblock_size = 64;
int ngrid_size = 1;
int maxgsx = 65535;
int mmcc = 0;
static int devid;
static cudaError_t crc;
__global__ void emptyKernel() {}
/*--------------------------------------------------------------------*/
extern "C" void gpu_setgbsize(int nblock) {
/* set blocksize */
nblock_size = nblock;
return;
}
/*--------------------------------------------------------------------*/
extern "C" int getmmcc() {
/* get major and minor computer capability */
return mmcc;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate(float **g_f, int nsize, int *irc) {
/* allocate global float memory on GPU, return pointer to C */
void *gptr;
crc = cudaMalloc(&gptr,sizeof(float)*nsize);
if (crc) {
printf("cudaMalloc float Error=%d:%s,l=%d\n",crc,
cudaGetErrorString(crc),nsize);
*irc = 1;
}
*g_f = (float *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_iallocate(int **g_i, int nsize, int *irc) {
/* allocate global integer memory on GPU, return pointer to C */
void *gptr;
crc = cudaMalloc(&gptr,sizeof(int)*nsize);
if (crc) {
printf("cudaMalloc int Error=%d:%s,l=%d\n",crc,
cudaGetErrorString(crc),nsize);
*irc = 1;
}
*g_i = (int *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_callocate(float2 **g_c, int nsize, int *irc) {
/* allocate global float2 memory on GPU, return pointer to C */
void *gptr;
crc = cudaMalloc(&gptr,sizeof(float2)*nsize);
if (crc) {
printf("cudaMalloc float2 Error=%d:%s,l=%d\n",crc,
cudaGetErrorString(crc),nsize);
*irc = 1;
}
*g_c = (float2 *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate(void *g_d, int *irc) {
/* deallocate global memory on GPU */
crc = cudaFree(g_d);
if (crc) {
printf("cudaFree Error=%d:%s\n",crc,cudaGetErrorString(crc));
*irc = 1;
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin(float *f, float *g_f, int nsize) {
/* copy float array from host memory to global GPU memory */
crc = cudaMemcpy((void *)g_f,f,sizeof(float)*nsize,
cudaMemcpyHostToDevice);
if (crc) {
printf("cudaMemcpyHostToDevice float Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout(float *f, float *g_f, int nsize) {
/* copy float array from global GPU memory to host memory */
crc = cudaMemcpy(f,(void *)g_f,sizeof(float)*nsize,
cudaMemcpyDeviceToHost);
if (crc) {
printf("cudaMemcpyDeviceToHost float Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyin(int *f, int *g_f, int nsize) {
/* copy int array from host memory to global GPU memory */
crc = cudaMemcpy((void *)g_f,f,sizeof(int)*nsize,
cudaMemcpyHostToDevice);
if (crc) {
printf("cudaMemcpyHostToDevice int Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyout(int *f, int *g_f, int nsize) {
/* copy int array from global GPU memory to host memory */
crc = cudaMemcpy(f,(void *)g_f,sizeof(int)*nsize,
cudaMemcpyDeviceToHost);
if (crc) {
printf("cudaMemcpyDeviceToHost int Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyin(float2 *f, float2 *g_f, int nsize) {
/* copy float2 array from host memory to global GPU memory */
crc = cudaMemcpy((void *)g_f,f,sizeof(float2)*nsize,
cudaMemcpyHostToDevice);
if (crc) {
printf("cudaMemcpyHostToDevice float2 Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyout(float2 *f, float2 *g_f, int nsize) {
/* copy float2 array from global GPU memory to host memory */
crc = cudaMemcpy(f,(void *)g_f,sizeof(float2)*nsize,
cudaMemcpyDeviceToHost);
if (crc) {
printf("cudaMemcpyDeviceToHost float2 Error=%d:%s\n",crc,
cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_zfmem(float *g_f, int nsize) {
/* initialize float array in global GPU memory to zero */
crc = cudaMemset((void *)g_f,0,sizeof(float)*nsize);
if (crc) {
printf("cudaMemset Error=%d:%s\n",crc,cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_set_cache_size(int nscache) {
/* request preferred cache size, requires CUDA 3.2 or higher */
/* nscache = (0,1,2) = (no,small,big) cache size */
cudaFuncCache cpref;
if ((nscache < 0) || (nscache > 2))
return;
if (nscache==0)
cpref = cudaFuncCachePreferNone;
else if (nscache==1)
cpref = cudaFuncCachePreferShared;
else if (nscache==2)
cpref = cudaFuncCachePreferL1;
crc = cudaThreadSetCacheConfig(cpref);
/* crc = cudaDeviceSetCacheConfig(cpref); */
if (crc) {
printf("cudaThreadSetCacheConfig error=%d:%s\n",crc,
cudaGetErrorString(crc));
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel() {
int ngx, ngy;
ngx = nblock_size < 32768 ? nblock_size : 32768;
ngy = (ngrid_size - 1)/ngx + 1;
dim3 dimBlock(nblock_size,1);
dim3 dimGrid(ngx,ngy);
crc = cudaGetLastError();
emptyKernel<<<dimGrid,dimBlock>>>();
cudaThreadSynchronize();
crc = cudaGetLastError();
if (crc) {
printf("emptyKernel error=%d:%s\n",crc,cudaGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu(int dev, int *irc) {
/* initialize CUDA with device dev or selects best GPU available */
/* searches throughs devices, selects the device with the most compute */
/* units, and saves the device id devid */
/* if dev is a valid device, it is used, otherwise the GPU with the */
/* most multi-processors is selected */
/* error code is modified only if there is an error */
int maxcpus = 0, jm = -1;
int j, ndevs, maxunits;
unsigned long msize;
double z;
struct cudaDeviceProp prop;
/* returns number of device */
crc = cudaGetDeviceCount(&ndevs);
if (crc) {
printf("cudaGetDeviceCount Error=%i:%s\n",crc,
cudaGetErrorString(crc));
*irc = 1;
return;
}
/* get information about devices */
for (j = 0; j < ndevs; j++) {
crc = cudaGetDeviceProperties(&prop,j);
if (crc) {
printf("cudaGetDeviceProperties Error=%i:%s\n",crc,
cudaGetErrorString(crc));
prop.name[0] = 0;
}
maxunits = prop.multiProcessorCount;
if (dev <= 0) {
printf("j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n",
j,prop.name,maxunits);
msize = prop.totalGlobalMem;
z = ((double) msize)/1073741824.0;
mmcc = 10*prop.major + prop.minor;
printf(" CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n",
msize,(float) z,mmcc);
if (maxunits > maxcpus) {
maxcpus = maxunits;
jm = j;
}
}
}
devid = jm;
if (dev >= 0)
devid = dev % ndevs;
printf("using device j=%i\n",devid);
/* get properties for this device */
crc = cudaGetDeviceProperties(&prop,devid);
maxgsx = prop.maxGridSize[0];
mmcc = 10*prop.major + prop.minor;
/* set device */
crc = cudaSetDevice(devid);
if (crc) {
printf("cudaSetDevice Error=%i:%s\n",crc,
cudaGetErrorString(crc));
*irc = 1;
return;
}
/* run empty kernel */
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu() {
/* terminate CUDA */
crc = cudaThreadExit();
if (crc) {
printf("cudaThreadExit Error=%d:%s\n",crc,cudaGetErrorString(crc));
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpu_setgbsize_(int *nblock) {
gpu_setgbsize(*nblock);
return;
}
/*--------------------------------------------------------------------*/
extern "C" int getmmcc_() {
/* get major and minor computer capability */
return getmmcc();
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float memory on GPU, return pointer to Fortran */
float *fptr;
gpu_fallocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_iallocate_(unsigned long *gp_i, int *nsize,
int *irc) {
/* allocate global integer memory on GPU, return pointer to Fortran */
int *iptr;
gpu_iallocate(&iptr,*nsize,irc);
*gp_i = (long )iptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_callocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float2 memory on GPU, return pointer */
/* to Fortran */
float2 *fptr;
gpu_callocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate_(unsigned long *gp_d, int *irc) {
/* deallocate global memory on GPU, return pointer to Fortran */
void *d;
d = (void *)*gp_d;
gpu_deallocate(d,irc);
*gp_d = 0;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from main memory to global GPU memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from global GPU memory to main memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyin_(int *f, unsigned long *gp_f, int *nsize) {
/* copy int array from main memory to global GPU memory */
int *g_f;
g_f = (int *)*gp_f;
gpu_icopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyout_(int *f, unsigned long *gp_f, int *nsize) {
/* copy int array from global GPU memory to main memory */
int *g_f;
g_f = (int *)*gp_f;
gpu_icopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyin_(float2 *f, unsigned long *gp_f,
int *nsize) {
/* copy float2 array from main memory to global GPU memory */
float2 *g_f;
g_f = (float2 *)*gp_f;
gpu_ccopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyout_(float2 *f, unsigned long *gp_f,
int *nsize) {
/* copy float2 array from global GPU memory to main memory */
float2 *g_f;
g_f = (float2 *)*gp_f;
gpu_ccopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_zfmem_(unsigned long *gp_f, int *nsize) {
float *g_f;
g_f = (float *)*gp_f;
gpu_zfmem(g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_set_cache_size_(int *nscache) {
gpu_set_cache_size(*nscache);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel_() {
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu_(int *dev, int *irc) {
init_cu(*dev,irc);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu_() {
end_cu();
return;
} | /*--------------------------------------------------------------------*/
/* CUDA utility Library */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "hip/hip_runtime.h"
int nblock_size = 64;
int ngrid_size = 1;
int maxgsx = 65535;
int mmcc = 0;
static int devid;
static hipError_t crc;
__global__ void emptyKernel() {}
/*--------------------------------------------------------------------*/
extern "C" void gpu_setgbsize(int nblock) {
/* set blocksize */
nblock_size = nblock;
return;
}
/*--------------------------------------------------------------------*/
extern "C" int getmmcc() {
/* get major and minor computer capability */
return mmcc;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate(float **g_f, int nsize, int *irc) {
/* allocate global float memory on GPU, return pointer to C */
void *gptr;
crc = hipMalloc(&gptr,sizeof(float)*nsize);
if (crc) {
printf("hipMalloc float Error=%d:%s,l=%d\n",crc,
hipGetErrorString(crc),nsize);
*irc = 1;
}
*g_f = (float *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_iallocate(int **g_i, int nsize, int *irc) {
/* allocate global integer memory on GPU, return pointer to C */
void *gptr;
crc = hipMalloc(&gptr,sizeof(int)*nsize);
if (crc) {
printf("hipMalloc int Error=%d:%s,l=%d\n",crc,
hipGetErrorString(crc),nsize);
*irc = 1;
}
*g_i = (int *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_callocate(float2 **g_c, int nsize, int *irc) {
/* allocate global float2 memory on GPU, return pointer to C */
void *gptr;
crc = hipMalloc(&gptr,sizeof(float2)*nsize);
if (crc) {
printf("hipMalloc float2 Error=%d:%s,l=%d\n",crc,
hipGetErrorString(crc),nsize);
*irc = 1;
}
*g_c = (float2 *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate(void *g_d, int *irc) {
/* deallocate global memory on GPU */
crc = hipFree(g_d);
if (crc) {
printf("hipFree Error=%d:%s\n",crc,hipGetErrorString(crc));
*irc = 1;
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin(float *f, float *g_f, int nsize) {
/* copy float array from host memory to global GPU memory */
crc = hipMemcpy((void *)g_f,f,sizeof(float)*nsize,
hipMemcpyHostToDevice);
if (crc) {
printf("hipMemcpyHostToDevice float Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout(float *f, float *g_f, int nsize) {
/* copy float array from global GPU memory to host memory */
crc = hipMemcpy(f,(void *)g_f,sizeof(float)*nsize,
hipMemcpyDeviceToHost);
if (crc) {
printf("hipMemcpyDeviceToHost float Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyin(int *f, int *g_f, int nsize) {
/* copy int array from host memory to global GPU memory */
crc = hipMemcpy((void *)g_f,f,sizeof(int)*nsize,
hipMemcpyHostToDevice);
if (crc) {
printf("hipMemcpyHostToDevice int Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyout(int *f, int *g_f, int nsize) {
/* copy int array from global GPU memory to host memory */
crc = hipMemcpy(f,(void *)g_f,sizeof(int)*nsize,
hipMemcpyDeviceToHost);
if (crc) {
printf("hipMemcpyDeviceToHost int Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyin(float2 *f, float2 *g_f, int nsize) {
/* copy float2 array from host memory to global GPU memory */
crc = hipMemcpy((void *)g_f,f,sizeof(float2)*nsize,
hipMemcpyHostToDevice);
if (crc) {
printf("hipMemcpyHostToDevice float2 Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyout(float2 *f, float2 *g_f, int nsize) {
/* copy float2 array from global GPU memory to host memory */
crc = hipMemcpy(f,(void *)g_f,sizeof(float2)*nsize,
hipMemcpyDeviceToHost);
if (crc) {
printf("hipMemcpyDeviceToHost float2 Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_zfmem(float *g_f, int nsize) {
/* initialize float array in global GPU memory to zero */
crc = hipMemset((void *)g_f,0,sizeof(float)*nsize);
if (crc) {
printf("hipMemset Error=%d:%s\n",crc,hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_set_cache_size(int nscache) {
/* request preferred cache size, requires CUDA 3.2 or higher */
/* nscache = (0,1,2) = (no,small,big) cache size */
hipFuncCache_t cpref;
if ((nscache < 0) || (nscache > 2))
return;
if (nscache==0)
cpref = hipFuncCachePreferNone;
else if (nscache==1)
cpref = hipFuncCachePreferShared;
else if (nscache==2)
cpref = hipFuncCachePreferL1;
crc = hipDeviceSetCacheConfig(cpref);
/* crc = cudaDeviceSetCacheConfig(cpref); */
if (crc) {
printf("hipDeviceSetCacheConfig error=%d:%s\n",crc,
hipGetErrorString(crc));
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel() {
int ngx, ngy;
ngx = nblock_size < 32768 ? nblock_size : 32768;
ngy = (ngrid_size - 1)/ngx + 1;
dim3 dimBlock(nblock_size,1);
dim3 dimGrid(ngx,ngy);
crc = hipGetLastError();
emptyKernel<<<dimGrid,dimBlock>>>();
hipDeviceSynchronize();
crc = hipGetLastError();
if (crc) {
printf("emptyKernel error=%d:%s\n",crc,hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu(int dev, int *irc) {
/* initialize CUDA with device dev or selects best GPU available */
/* searches throughs devices, selects the device with the most compute */
/* units, and saves the device id devid */
/* if dev is a valid device, it is used, otherwise the GPU with the */
/* most multi-processors is selected */
/* error code is modified only if there is an error */
int maxcpus = 0, jm = -1;
int j, ndevs, maxunits;
unsigned long msize;
double z;
struct hipDeviceProp_t prop;
/* returns number of device */
crc = hipGetDeviceCount(&ndevs);
if (crc) {
printf("hipGetDeviceCount Error=%i:%s\n",crc,
hipGetErrorString(crc));
*irc = 1;
return;
}
/* get information about devices */
for (j = 0; j < ndevs; j++) {
crc = hipGetDeviceProperties(&prop,j);
if (crc) {
printf("hipGetDeviceProperties Error=%i:%s\n",crc,
hipGetErrorString(crc));
prop.name[0] = 0;
}
maxunits = prop.multiProcessorCount;
if (dev <= 0) {
printf("j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n",
j,prop.name,maxunits);
msize = prop.totalGlobalMem;
z = ((double) msize)/1073741824.0;
mmcc = 10*prop.major + prop.minor;
printf(" CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n",
msize,(float) z,mmcc);
if (maxunits > maxcpus) {
maxcpus = maxunits;
jm = j;
}
}
}
devid = jm;
if (dev >= 0)
devid = dev % ndevs;
printf("using device j=%i\n",devid);
/* get properties for this device */
crc = hipGetDeviceProperties(&prop,devid);
maxgsx = prop.maxGridSize[0];
mmcc = 10*prop.major + prop.minor;
/* set device */
crc = hipSetDevice(devid);
if (crc) {
printf("hipSetDevice Error=%i:%s\n",crc,
hipGetErrorString(crc));
*irc = 1;
return;
}
/* run empty kernel */
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu() {
/* terminate CUDA */
crc = hipDeviceReset();
if (crc) {
printf("hipDeviceReset Error=%d:%s\n",crc,hipGetErrorString(crc));
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpu_setgbsize_(int *nblock) {
gpu_setgbsize(*nblock);
return;
}
/*--------------------------------------------------------------------*/
extern "C" int getmmcc_() {
/* get major and minor computer capability */
return getmmcc();
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float memory on GPU, return pointer to Fortran */
float *fptr;
gpu_fallocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_iallocate_(unsigned long *gp_i, int *nsize,
int *irc) {
/* allocate global integer memory on GPU, return pointer to Fortran */
int *iptr;
gpu_iallocate(&iptr,*nsize,irc);
*gp_i = (long )iptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_callocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float2 memory on GPU, return pointer */
/* to Fortran */
float2 *fptr;
gpu_callocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate_(unsigned long *gp_d, int *irc) {
/* deallocate global memory on GPU, return pointer to Fortran */
void *d;
d = (void *)*gp_d;
gpu_deallocate(d,irc);
*gp_d = 0;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from main memory to global GPU memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from global GPU memory to main memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyin_(int *f, unsigned long *gp_f, int *nsize) {
/* copy int array from main memory to global GPU memory */
int *g_f;
g_f = (int *)*gp_f;
gpu_icopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyout_(int *f, unsigned long *gp_f, int *nsize) {
/* copy int array from global GPU memory to main memory */
int *g_f;
g_f = (int *)*gp_f;
gpu_icopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyin_(float2 *f, unsigned long *gp_f,
int *nsize) {
/* copy float2 array from main memory to global GPU memory */
float2 *g_f;
g_f = (float2 *)*gp_f;
gpu_ccopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyout_(float2 *f, unsigned long *gp_f,
int *nsize) {
/* copy float2 array from global GPU memory to main memory */
float2 *g_f;
g_f = (float2 *)*gp_f;
gpu_ccopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_zfmem_(unsigned long *gp_f, int *nsize) {
float *g_f;
g_f = (float *)*gp_f;
gpu_zfmem(g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_set_cache_size_(int *nscache) {
gpu_set_cache_size(*nscache);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel_() {
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu_(int *dev, int *irc) {
init_cu(*dev,irc);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu_() {
end_cu();
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*--------------------------------------------------------------------*/
/* CUDA utility Library */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "hip/hip_runtime.h"
int nblock_size = 64;
int ngrid_size = 1;
int maxgsx = 65535;
int mmcc = 0;
static int devid;
static hipError_t crc;
__global__ void emptyKernel() {}
/*--------------------------------------------------------------------*/
extern "C" void gpu_setgbsize(int nblock) {
/* set blocksize */
nblock_size = nblock;
return;
}
/*--------------------------------------------------------------------*/
extern "C" int getmmcc() {
/* get major and minor computer capability */
return mmcc;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate(float **g_f, int nsize, int *irc) {
/* allocate global float memory on GPU, return pointer to C */
void *gptr;
crc = hipMalloc(&gptr,sizeof(float)*nsize);
if (crc) {
printf("hipMalloc float Error=%d:%s,l=%d\n",crc,
hipGetErrorString(crc),nsize);
*irc = 1;
}
*g_f = (float *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_iallocate(int **g_i, int nsize, int *irc) {
/* allocate global integer memory on GPU, return pointer to C */
void *gptr;
crc = hipMalloc(&gptr,sizeof(int)*nsize);
if (crc) {
printf("hipMalloc int Error=%d:%s,l=%d\n",crc,
hipGetErrorString(crc),nsize);
*irc = 1;
}
*g_i = (int *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_callocate(float2 **g_c, int nsize, int *irc) {
/* allocate global float2 memory on GPU, return pointer to C */
void *gptr;
crc = hipMalloc(&gptr,sizeof(float2)*nsize);
if (crc) {
printf("hipMalloc float2 Error=%d:%s,l=%d\n",crc,
hipGetErrorString(crc),nsize);
*irc = 1;
}
*g_c = (float2 *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate(void *g_d, int *irc) {
/* deallocate global memory on GPU */
crc = hipFree(g_d);
if (crc) {
printf("hipFree Error=%d:%s\n",crc,hipGetErrorString(crc));
*irc = 1;
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin(float *f, float *g_f, int nsize) {
/* copy float array from host memory to global GPU memory */
crc = hipMemcpy((void *)g_f,f,sizeof(float)*nsize,
hipMemcpyHostToDevice);
if (crc) {
printf("hipMemcpyHostToDevice float Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout(float *f, float *g_f, int nsize) {
/* copy float array from global GPU memory to host memory */
crc = hipMemcpy(f,(void *)g_f,sizeof(float)*nsize,
hipMemcpyDeviceToHost);
if (crc) {
printf("hipMemcpyDeviceToHost float Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyin(int *f, int *g_f, int nsize) {
/* copy int array from host memory to global GPU memory */
crc = hipMemcpy((void *)g_f,f,sizeof(int)*nsize,
hipMemcpyHostToDevice);
if (crc) {
printf("hipMemcpyHostToDevice int Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyout(int *f, int *g_f, int nsize) {
/* copy int array from global GPU memory to host memory */
crc = hipMemcpy(f,(void *)g_f,sizeof(int)*nsize,
hipMemcpyDeviceToHost);
if (crc) {
printf("hipMemcpyDeviceToHost int Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyin(float2 *f, float2 *g_f, int nsize) {
/* copy float2 array from host memory to global GPU memory */
crc = hipMemcpy((void *)g_f,f,sizeof(float2)*nsize,
hipMemcpyHostToDevice);
if (crc) {
printf("hipMemcpyHostToDevice float2 Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyout(float2 *f, float2 *g_f, int nsize) {
/* copy float2 array from global GPU memory to host memory */
crc = hipMemcpy(f,(void *)g_f,sizeof(float2)*nsize,
hipMemcpyDeviceToHost);
if (crc) {
printf("hipMemcpyDeviceToHost float2 Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_zfmem(float *g_f, int nsize) {
/* initialize float array in global GPU memory to zero */
crc = hipMemset((void *)g_f,0,sizeof(float)*nsize);
if (crc) {
printf("hipMemset Error=%d:%s\n",crc,hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_set_cache_size(int nscache) {
/* request preferred cache size, requires CUDA 3.2 or higher */
/* nscache = (0,1,2) = (no,small,big) cache size */
hipFuncCache_t cpref;
if ((nscache < 0) || (nscache > 2))
return;
if (nscache==0)
cpref = hipFuncCachePreferNone;
else if (nscache==1)
cpref = hipFuncCachePreferShared;
else if (nscache==2)
cpref = hipFuncCachePreferL1;
crc = hipDeviceSetCacheConfig(cpref);
/* crc = cudaDeviceSetCacheConfig(cpref); */
if (crc) {
printf("hipDeviceSetCacheConfig error=%d:%s\n",crc,
hipGetErrorString(crc));
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel() {
int ngx, ngy;
ngx = nblock_size < 32768 ? nblock_size : 32768;
ngy = (ngrid_size - 1)/ngx + 1;
dim3 dimBlock(nblock_size,1);
dim3 dimGrid(ngx,ngy);
crc = hipGetLastError();
emptyKernel<<<dimGrid,dimBlock>>>();
hipDeviceSynchronize();
crc = hipGetLastError();
if (crc) {
printf("emptyKernel error=%d:%s\n",crc,hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu(int dev, int *irc) {
/* initialize CUDA with device dev or selects best GPU available */
/* searches throughs devices, selects the device with the most compute */
/* units, and saves the device id devid */
/* if dev is a valid device, it is used, otherwise the GPU with the */
/* most multi-processors is selected */
/* error code is modified only if there is an error */
int maxcpus = 0, jm = -1;
int j, ndevs, maxunits;
unsigned long msize;
double z;
struct hipDeviceProp_t prop;
/* returns number of device */
crc = hipGetDeviceCount(&ndevs);
if (crc) {
printf("hipGetDeviceCount Error=%i:%s\n",crc,
hipGetErrorString(crc));
*irc = 1;
return;
}
/* get information about devices */
for (j = 0; j < ndevs; j++) {
crc = hipGetDeviceProperties(&prop,j);
if (crc) {
printf("hipGetDeviceProperties Error=%i:%s\n",crc,
hipGetErrorString(crc));
prop.name[0] = 0;
}
maxunits = prop.multiProcessorCount;
if (dev <= 0) {
printf("j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n",
j,prop.name,maxunits);
msize = prop.totalGlobalMem;
z = ((double) msize)/1073741824.0;
mmcc = 10*prop.major + prop.minor;
printf(" CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n",
msize,(float) z,mmcc);
if (maxunits > maxcpus) {
maxcpus = maxunits;
jm = j;
}
}
}
devid = jm;
if (dev >= 0)
devid = dev % ndevs;
printf("using device j=%i\n",devid);
/* get properties for this device */
crc = hipGetDeviceProperties(&prop,devid);
maxgsx = prop.maxGridSize[0];
mmcc = 10*prop.major + prop.minor;
/* set device */
crc = hipSetDevice(devid);
if (crc) {
printf("hipSetDevice Error=%i:%s\n",crc,
hipGetErrorString(crc));
*irc = 1;
return;
}
/* run empty kernel */
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu() {
/* terminate CUDA */
crc = hipDeviceReset();
if (crc) {
printf("hipDeviceReset Error=%d:%s\n",crc,hipGetErrorString(crc));
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpu_setgbsize_(int *nblock) {
gpu_setgbsize(*nblock);
return;
}
/*--------------------------------------------------------------------*/
extern "C" int getmmcc_() {
/* get major and minor computer capability */
return getmmcc();
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float memory on GPU, return pointer to Fortran */
float *fptr;
gpu_fallocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_iallocate_(unsigned long *gp_i, int *nsize,
int *irc) {
/* allocate global integer memory on GPU, return pointer to Fortran */
int *iptr;
gpu_iallocate(&iptr,*nsize,irc);
*gp_i = (long )iptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_callocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float2 memory on GPU, return pointer */
/* to Fortran */
float2 *fptr;
gpu_callocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate_(unsigned long *gp_d, int *irc) {
/* deallocate global memory on GPU, return pointer to Fortran */
void *d;
d = (void *)*gp_d;
gpu_deallocate(d,irc);
*gp_d = 0;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from main memory to global GPU memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from global GPU memory to main memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyin_(int *f, unsigned long *gp_f, int *nsize) {
/* copy int array from main memory to global GPU memory */
int *g_f;
g_f = (int *)*gp_f;
gpu_icopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyout_(int *f, unsigned long *gp_f, int *nsize) {
/* copy int array from global GPU memory to main memory */
int *g_f;
g_f = (int *)*gp_f;
gpu_icopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyin_(float2 *f, unsigned long *gp_f,
int *nsize) {
/* copy float2 array from main memory to global GPU memory */
float2 *g_f;
g_f = (float2 *)*gp_f;
gpu_ccopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyout_(float2 *f, unsigned long *gp_f,
int *nsize) {
/* copy float2 array from global GPU memory to main memory */
float2 *g_f;
g_f = (float2 *)*gp_f;
gpu_ccopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_zfmem_(unsigned long *gp_f, int *nsize) {
float *g_f;
g_f = (float *)*gp_f;
gpu_zfmem(g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_set_cache_size_(int *nscache) {
gpu_set_cache_size(*nscache);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel_() {
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu_(int *dev, int *irc) {
init_cu(*dev,irc);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu_() {
end_cu();
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11emptyKernelv
.globl _Z11emptyKernelv
.p2align 8
.type _Z11emptyKernelv,@function
_Z11emptyKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11emptyKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11emptyKernelv, .Lfunc_end0-_Z11emptyKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11emptyKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z11emptyKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*--------------------------------------------------------------------*/
/* CUDA utility Library */
/* written by Viktor K. Decyk, UCLA */
#include <stdlib.h>
#include <stdio.h>
#include "hip/hip_runtime.h"
int nblock_size = 64;
int ngrid_size = 1;
int maxgsx = 65535;
int mmcc = 0;
static int devid;
static hipError_t crc;
__global__ void emptyKernel() {}
/*--------------------------------------------------------------------*/
extern "C" void gpu_setgbsize(int nblock) {
/* set blocksize */
nblock_size = nblock;
return;
}
/*--------------------------------------------------------------------*/
extern "C" int getmmcc() {
/* get major and minor computer capability */
return mmcc;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate(float **g_f, int nsize, int *irc) {
/* allocate global float memory on GPU, return pointer to C */
void *gptr;
crc = hipMalloc(&gptr,sizeof(float)*nsize);
if (crc) {
printf("hipMalloc float Error=%d:%s,l=%d\n",crc,
hipGetErrorString(crc),nsize);
*irc = 1;
}
*g_f = (float *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_iallocate(int **g_i, int nsize, int *irc) {
/* allocate global integer memory on GPU, return pointer to C */
void *gptr;
crc = hipMalloc(&gptr,sizeof(int)*nsize);
if (crc) {
printf("hipMalloc int Error=%d:%s,l=%d\n",crc,
hipGetErrorString(crc),nsize);
*irc = 1;
}
*g_i = (int *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_callocate(float2 **g_c, int nsize, int *irc) {
/* allocate global float2 memory on GPU, return pointer to C */
void *gptr;
crc = hipMalloc(&gptr,sizeof(float2)*nsize);
if (crc) {
printf("hipMalloc float2 Error=%d:%s,l=%d\n",crc,
hipGetErrorString(crc),nsize);
*irc = 1;
}
*g_c = (float2 *)gptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate(void *g_d, int *irc) {
/* deallocate global memory on GPU */
crc = hipFree(g_d);
if (crc) {
printf("hipFree Error=%d:%s\n",crc,hipGetErrorString(crc));
*irc = 1;
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin(float *f, float *g_f, int nsize) {
/* copy float array from host memory to global GPU memory */
crc = hipMemcpy((void *)g_f,f,sizeof(float)*nsize,
hipMemcpyHostToDevice);
if (crc) {
printf("hipMemcpyHostToDevice float Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout(float *f, float *g_f, int nsize) {
/* copy float array from global GPU memory to host memory */
crc = hipMemcpy(f,(void *)g_f,sizeof(float)*nsize,
hipMemcpyDeviceToHost);
if (crc) {
printf("hipMemcpyDeviceToHost float Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyin(int *f, int *g_f, int nsize) {
/* copy int array from host memory to global GPU memory */
crc = hipMemcpy((void *)g_f,f,sizeof(int)*nsize,
hipMemcpyHostToDevice);
if (crc) {
printf("hipMemcpyHostToDevice int Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyout(int *f, int *g_f, int nsize) {
/* copy int array from global GPU memory to host memory */
crc = hipMemcpy(f,(void *)g_f,sizeof(int)*nsize,
hipMemcpyDeviceToHost);
if (crc) {
printf("hipMemcpyDeviceToHost int Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyin(float2 *f, float2 *g_f, int nsize) {
/* copy float2 array from host memory to global GPU memory */
crc = hipMemcpy((void *)g_f,f,sizeof(float2)*nsize,
hipMemcpyHostToDevice);
if (crc) {
printf("hipMemcpyHostToDevice float2 Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyout(float2 *f, float2 *g_f, int nsize) {
/* copy float2 array from global GPU memory to host memory */
crc = hipMemcpy(f,(void *)g_f,sizeof(float2)*nsize,
hipMemcpyDeviceToHost);
if (crc) {
printf("hipMemcpyDeviceToHost float2 Error=%d:%s\n",crc,
hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_zfmem(float *g_f, int nsize) {
/* initialize float array in global GPU memory to zero */
crc = hipMemset((void *)g_f,0,sizeof(float)*nsize);
if (crc) {
printf("hipMemset Error=%d:%s\n",crc,hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_set_cache_size(int nscache) {
/* request preferred cache size, requires CUDA 3.2 or higher */
/* nscache = (0,1,2) = (no,small,big) cache size */
hipFuncCache_t cpref;
if ((nscache < 0) || (nscache > 2))
return;
if (nscache==0)
cpref = hipFuncCachePreferNone;
else if (nscache==1)
cpref = hipFuncCachePreferShared;
else if (nscache==2)
cpref = hipFuncCachePreferL1;
crc = hipDeviceSetCacheConfig(cpref);
/* crc = cudaDeviceSetCacheConfig(cpref); */
if (crc) {
printf("hipDeviceSetCacheConfig error=%d:%s\n",crc,
hipGetErrorString(crc));
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel() {
int ngx, ngy;
ngx = nblock_size < 32768 ? nblock_size : 32768;
ngy = (ngrid_size - 1)/ngx + 1;
dim3 dimBlock(nblock_size,1);
dim3 dimGrid(ngx,ngy);
crc = hipGetLastError();
emptyKernel<<<dimGrid,dimBlock>>>();
hipDeviceSynchronize();
crc = hipGetLastError();
if (crc) {
printf("emptyKernel error=%d:%s\n",crc,hipGetErrorString(crc));
exit(1);
}
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu(int dev, int *irc) {
/* initialize CUDA with device dev or selects best GPU available */
/* searches throughs devices, selects the device with the most compute */
/* units, and saves the device id devid */
/* if dev is a valid device, it is used, otherwise the GPU with the */
/* most multi-processors is selected */
/* error code is modified only if there is an error */
int maxcpus = 0, jm = -1;
int j, ndevs, maxunits;
unsigned long msize;
double z;
struct hipDeviceProp_t prop;
/* returns number of device */
crc = hipGetDeviceCount(&ndevs);
if (crc) {
printf("hipGetDeviceCount Error=%i:%s\n",crc,
hipGetErrorString(crc));
*irc = 1;
return;
}
/* get information about devices */
for (j = 0; j < ndevs; j++) {
crc = hipGetDeviceProperties(&prop,j);
if (crc) {
printf("hipGetDeviceProperties Error=%i:%s\n",crc,
hipGetErrorString(crc));
prop.name[0] = 0;
}
maxunits = prop.multiProcessorCount;
if (dev <= 0) {
printf("j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n",
j,prop.name,maxunits);
msize = prop.totalGlobalMem;
z = ((double) msize)/1073741824.0;
mmcc = 10*prop.major + prop.minor;
printf(" CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n",
msize,(float) z,mmcc);
if (maxunits > maxcpus) {
maxcpus = maxunits;
jm = j;
}
}
}
devid = jm;
if (dev >= 0)
devid = dev % ndevs;
printf("using device j=%i\n",devid);
/* get properties for this device */
crc = hipGetDeviceProperties(&prop,devid);
maxgsx = prop.maxGridSize[0];
mmcc = 10*prop.major + prop.minor;
/* set device */
crc = hipSetDevice(devid);
if (crc) {
printf("hipSetDevice Error=%i:%s\n",crc,
hipGetErrorString(crc));
*irc = 1;
return;
}
/* run empty kernel */
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu() {
/* terminate CUDA */
crc = hipDeviceReset();
if (crc) {
printf("hipDeviceReset Error=%d:%s\n",crc,hipGetErrorString(crc));
}
return;
}
/* Interfaces to Fortran */
/*--------------------------------------------------------------------*/
extern "C" void gpu_setgbsize_(int *nblock) {
gpu_setgbsize(*nblock);
return;
}
/*--------------------------------------------------------------------*/
extern "C" int getmmcc_() {
/* get major and minor computer capability */
return getmmcc();
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fallocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float memory on GPU, return pointer to Fortran */
float *fptr;
gpu_fallocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_iallocate_(unsigned long *gp_i, int *nsize,
int *irc) {
/* allocate global integer memory on GPU, return pointer to Fortran */
int *iptr;
gpu_iallocate(&iptr,*nsize,irc);
*gp_i = (long )iptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_callocate_(unsigned long *gp_f, int *nsize,
int *irc) {
/* allocate global float2 memory on GPU, return pointer */
/* to Fortran */
float2 *fptr;
gpu_callocate(&fptr,*nsize,irc);
*gp_f = (long )fptr;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_deallocate_(unsigned long *gp_d, int *irc) {
/* deallocate global memory on GPU, return pointer to Fortran */
void *d;
d = (void *)*gp_d;
gpu_deallocate(d,irc);
*gp_d = 0;
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyin_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from main memory to global GPU memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_fcopyout_(float *f, unsigned long *gp_f,
int *nsize) {
/* copy float array from global GPU memory to main memory */
float *g_f;
g_f = (float *)*gp_f;
gpu_fcopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyin_(int *f, unsigned long *gp_f, int *nsize) {
/* copy int array from main memory to global GPU memory */
int *g_f;
g_f = (int *)*gp_f;
gpu_icopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_icopyout_(int *f, unsigned long *gp_f, int *nsize) {
/* copy int array from global GPU memory to main memory */
int *g_f;
g_f = (int *)*gp_f;
gpu_icopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyin_(float2 *f, unsigned long *gp_f,
int *nsize) {
/* copy float2 array from main memory to global GPU memory */
float2 *g_f;
g_f = (float2 *)*gp_f;
gpu_ccopyin(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_ccopyout_(float2 *f, unsigned long *gp_f,
int *nsize) {
/* copy float2 array from global GPU memory to main memory */
float2 *g_f;
g_f = (float2 *)*gp_f;
gpu_ccopyout(f,g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_zfmem_(unsigned long *gp_f, int *nsize) {
float *g_f;
g_f = (float *)*gp_f;
gpu_zfmem(g_f,*nsize);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void gpu_set_cache_size_(int *nscache) {
gpu_set_cache_size(*nscache);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void emptykernel_() {
emptykernel();
return;
}
/*--------------------------------------------------------------------*/
extern "C" void init_cu_(int *dev, int *irc) {
init_cu(*dev,irc);
return;
}
/*--------------------------------------------------------------------*/
extern "C" void end_cu_() {
end_cu();
return;
} | .text
.file "gpulib2.hip"
.globl _Z26__device_stub__emptyKernelv # -- Begin function _Z26__device_stub__emptyKernelv
.p2align 4, 0x90
.type _Z26__device_stub__emptyKernelv,@function
_Z26__device_stub__emptyKernelv: # @_Z26__device_stub__emptyKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11emptyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__emptyKernelv, .Lfunc_end0-_Z26__device_stub__emptyKernelv
.cfi_endproc
# -- End function
.globl gpu_setgbsize # -- Begin function gpu_setgbsize
.p2align 4, 0x90
.type gpu_setgbsize,@function
gpu_setgbsize: # @gpu_setgbsize
.cfi_startproc
# %bb.0:
movl %edi, nblock_size(%rip)
retq
.Lfunc_end1:
.size gpu_setgbsize, .Lfunc_end1-gpu_setgbsize
.cfi_endproc
# -- End function
.globl getmmcc # -- Begin function getmmcc
.p2align 4, 0x90
.type getmmcc,@function
getmmcc: # @getmmcc
.cfi_startproc
# %bb.0:
movl mmcc(%rip), %eax
retq
.Lfunc_end2:
.size getmmcc, .Lfunc_end2-getmmcc
.cfi_endproc
# -- End function
.globl gpu_fallocate # -- Begin function gpu_fallocate
.p2align 4, 0x90
.type gpu_fallocate,@function
gpu_fallocate: # @gpu_fallocate
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %rsi
shlq $2, %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB3_2
# %bb.1:
movl %eax, %edi
movl %eax, %r15d
callq hipGetErrorString
movl $.L.str, %edi
movl %r15d, %esi
movq %rax, %rdx
movl %ebp, %ecx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB3_2:
movq (%rsp), %rax
movq %rax, (%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size gpu_fallocate, .Lfunc_end3-gpu_fallocate
.cfi_endproc
# -- End function
.globl gpu_iallocate # -- Begin function gpu_iallocate
.p2align 4, 0x90
.type gpu_iallocate,@function
gpu_iallocate: # @gpu_iallocate
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %rsi
shlq $2, %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB4_2
# %bb.1:
movl %eax, %edi
movl %eax, %r15d
callq hipGetErrorString
movl $.L.str.1, %edi
movl %r15d, %esi
movq %rax, %rdx
movl %ebp, %ecx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB4_2:
movq (%rsp), %rax
movq %rax, (%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size gpu_iallocate, .Lfunc_end4-gpu_iallocate
.cfi_endproc
# -- End function
.globl gpu_callocate # -- Begin function gpu_callocate
.p2align 4, 0x90
.type gpu_callocate,@function
gpu_callocate: # @gpu_callocate
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %rsi
shlq $3, %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB5_2
# %bb.1:
movl %eax, %edi
movl %eax, %r15d
callq hipGetErrorString
movl $.L.str.2, %edi
movl %r15d, %esi
movq %rax, %rdx
movl %ebp, %ecx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB5_2:
movq (%rsp), %rax
movq %rax, (%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size gpu_callocate, .Lfunc_end5-gpu_callocate
.cfi_endproc
# -- End function
.globl gpu_deallocate # -- Begin function gpu_deallocate
.p2align 4, 0x90
.type gpu_deallocate,@function
gpu_deallocate: # @gpu_deallocate
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
callq hipFree
testl %eax, %eax
je .LBB6_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, (%rbx)
.LBB6_2:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size gpu_deallocate, .Lfunc_end6-gpu_deallocate
.cfi_endproc
# -- End function
.globl gpu_fcopyin # -- Begin function gpu_fcopyin
.p2align 4, 0x90
.type gpu_fcopyin,@function
gpu_fcopyin: # @gpu_fcopyin
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rax
movslq %edx, %rdx
shlq $2, %rdx
movq %rsi, %rdi
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB7_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.4, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end7:
.size gpu_fcopyin, .Lfunc_end7-gpu_fcopyin
.cfi_endproc
# -- End function
.globl gpu_fcopyout # -- Begin function gpu_fcopyout
.p2align 4, 0x90
.type gpu_fcopyout,@function
gpu_fcopyout: # @gpu_fcopyout
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movslq %edx, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB8_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB8_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.5, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end8:
.size gpu_fcopyout, .Lfunc_end8-gpu_fcopyout
.cfi_endproc
# -- End function
.globl gpu_icopyin # -- Begin function gpu_icopyin
.p2align 4, 0x90
.type gpu_icopyin,@function
gpu_icopyin: # @gpu_icopyin
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rax
movslq %edx, %rdx
shlq $2, %rdx
movq %rsi, %rdi
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB9_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB9_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.6, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end9:
.size gpu_icopyin, .Lfunc_end9-gpu_icopyin
.cfi_endproc
# -- End function
.globl gpu_icopyout # -- Begin function gpu_icopyout
.p2align 4, 0x90
.type gpu_icopyout,@function
gpu_icopyout: # @gpu_icopyout
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movslq %edx, %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB10_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB10_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.7, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end10:
.size gpu_icopyout, .Lfunc_end10-gpu_icopyout
.cfi_endproc
# -- End function
.globl gpu_ccopyin # -- Begin function gpu_ccopyin
.p2align 4, 0x90
.type gpu_ccopyin,@function
gpu_ccopyin: # @gpu_ccopyin
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rax
movslq %edx, %rdx
shlq $3, %rdx
movq %rsi, %rdi
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB11_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB11_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.8, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end11:
.size gpu_ccopyin, .Lfunc_end11-gpu_ccopyin
.cfi_endproc
# -- End function
.globl gpu_ccopyout # -- Begin function gpu_ccopyout
.p2align 4, 0x90
.type gpu_ccopyout,@function
gpu_ccopyout: # @gpu_ccopyout
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movslq %edx, %rdx
shlq $3, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB12_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB12_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.9, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end12:
.size gpu_ccopyout, .Lfunc_end12-gpu_ccopyout
.cfi_endproc
# -- End function
.globl gpu_zfmem # -- Begin function gpu_zfmem
.p2align 4, 0x90
.type gpu_zfmem,@function
gpu_zfmem: # @gpu_zfmem
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movslq %esi, %rdx
shlq $2, %rdx
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB13_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB13_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.10, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end13:
.size gpu_zfmem, .Lfunc_end13-gpu_zfmem
.cfi_endproc
# -- End function
.globl gpu_set_cache_size # -- Begin function gpu_set_cache_size
.p2align 4, 0x90
.type gpu_set_cache_size,@function
gpu_set_cache_size: # @gpu_set_cache_size
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpl $2, %edi
ja .LBB14_2
# %bb.1:
xorl %eax, %eax
cmpl $1, %edi
setne %al
incl %eax
testl %edi, %edi
cmovel %edi, %eax
movl %eax, %edi
callq hipDeviceSetCacheConfig
testl %eax, %eax
je .LBB14_2
# %bb.3:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB14_2:
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end14:
.size gpu_set_cache_size, .Lfunc_end14-gpu_set_cache_size
.cfi_endproc
# -- End function
.globl emptykernel # -- Begin function emptykernel
.p2align 4, 0x90
.type emptykernel,@function
emptykernel: # @emptykernel
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl nblock_size(%rip), %ecx
cmpl $32768, %ecx # imm = 0x8000
movl $32768, %ebx # imm = 0x8000
cmovll %ecx, %ebx
movl ngrid_size(%rip), %eax
decl %eax
cltd
idivl %ebx
# kill: def $eax killed $eax def $rax
incl %eax
movabsq $4294967296, %r14 # imm = 0x100000000
orq %rcx, %r14
shlq $32, %rax
orq %rax, %rbx
callq hipGetLastError
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB15_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11emptyKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB15_2:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB15_4
# %bb.3:
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB15_4:
.cfi_def_cfa_offset 80
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.12, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end15:
.size emptykernel, .Lfunc_end15-emptykernel
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function init_cu
.LCPI16_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI16_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI16_2:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.text
.globl init_cu
.p2align 4, 0x90
.type init_cu,@function
init_cu: # @init_cu
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
je .LBB16_1
# %bb.14:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.13, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, (%rbx)
jmp .LBB16_13
.LBB16_1: # %.preheader
movq %rbx, 16(%rsp) # 8-byte Spill
movl 12(%rsp), %ecx
movl $-1, %r14d
testl %ecx, %ecx
jle .LBB16_8
# %bb.2: # %.lr.ph
leaq 24(%rsp), %r15
xorl %ebx, %ebx
xorl %r12d, %r12d
jmp .LBB16_3
.p2align 4, 0x90
.LBB16_7: # in Loop: Header=BB16_3 Depth=1
incl %r12d
movl 12(%rsp), %ecx
cmpl %ecx, %r12d
jge .LBB16_8
.LBB16_3: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl %r12d, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
je .LBB16_5
# %bb.4: # in Loop: Header=BB16_3 Depth=1
movl %eax, %edi
movl %eax, %r13d
callq hipGetErrorString
movl $.L.str.14, %edi
movl %r13d, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movb $0, 24(%rsp)
.LBB16_5: # in Loop: Header=BB16_3 Depth=1
testl %ebp, %ebp
jg .LBB16_7
# %bb.6: # in Loop: Header=BB16_3 Depth=1
movl 412(%rsp), %r13d
movl $.L.str.15, %edi
movl %r12d, %esi
movq %r15, %rdx
movl %r13d, %ecx
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movq %rsi, %xmm0
punpckldq .LCPI16_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI16_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
mulsd .LCPI16_2(%rip), %xmm1
movl 384(%rsp), %eax
leal (%rax,%rax,4), %edx
addl %edx, %edx
addl 388(%rsp), %edx
movl %edx, mmcc(%rip)
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.16, %edi
movb $1, %al
callq printf
cmpl %ebx, %r13d
cmovgl %r12d, %r14d
cmovgl %r13d, %ebx
jmp .LBB16_7
.LBB16_8: # %._crit_edge
testl %ebp, %ebp
js .LBB16_10
# %bb.9:
movl %ebp, %eax
cltd
idivl %ecx
movl %edx, %r14d
.LBB16_10:
movl %r14d, _ZL5devid(%rip)
movl $.L.str.17, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl _ZL5devid(%rip), %esi
leaq 24(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl 360(%rsp), %eax
movl 384(%rsp), %ecx
movl %eax, maxgsx(%rip)
leal (%rcx,%rcx,4), %eax
addl %eax, %eax
addl 388(%rsp), %eax
movl %eax, mmcc(%rip)
movl _ZL5devid(%rip), %edi
callq hipSetDevice
testl %eax, %eax
je .LBB16_12
# %bb.11:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.18, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movq 16(%rsp), %rax # 8-byte Reload
movl $1, (%rax)
jmp .LBB16_13
.LBB16_12:
callq emptykernel
.LBB16_13:
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end16:
.size init_cu, .Lfunc_end16-init_cu
.cfi_endproc
# -- End function
.globl end_cu # -- Begin function end_cu
.p2align 4, 0x90
.type end_cu,@function
end_cu: # @end_cu
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq hipDeviceReset
testl %eax, %eax
je .LBB17_1
# %bb.2:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.19, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB17_1:
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end17:
.size end_cu, .Lfunc_end17-end_cu
.cfi_endproc
# -- End function
.globl gpu_setgbsize_ # -- Begin function gpu_setgbsize_
.p2align 4, 0x90
.type gpu_setgbsize_,@function
gpu_setgbsize_: # @gpu_setgbsize_
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
movl %eax, nblock_size(%rip)
retq
.Lfunc_end18:
.size gpu_setgbsize_, .Lfunc_end18-gpu_setgbsize_
.cfi_endproc
# -- End function
.globl getmmcc_ # -- Begin function getmmcc_
.p2align 4, 0x90
.type getmmcc_,@function
getmmcc_: # @getmmcc_
.cfi_startproc
# %bb.0:
movl mmcc(%rip), %eax
retq
.Lfunc_end19:
.size getmmcc_, .Lfunc_end19-getmmcc_
.cfi_endproc
# -- End function
.globl gpu_fallocate_ # -- Begin function gpu_fallocate_
.p2align 4, 0x90
.type gpu_fallocate_,@function
gpu_fallocate_: # @gpu_fallocate_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r14
movq %rdi, %rbx
movslq (%rsi), %r15
leaq (,%r15,4), %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB20_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str, %edi
movl %ebp, %esi
movq %rax, %rdx
movl %r15d, %ecx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB20_2: # %gpu_fallocate.exit
movq (%rsp), %rax
movq %rax, (%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end20:
.size gpu_fallocate_, .Lfunc_end20-gpu_fallocate_
.cfi_endproc
# -- End function
.globl gpu_iallocate_ # -- Begin function gpu_iallocate_
.p2align 4, 0x90
.type gpu_iallocate_,@function
gpu_iallocate_: # @gpu_iallocate_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r14
movq %rdi, %rbx
movslq (%rsi), %r15
leaq (,%r15,4), %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB21_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %edi
movl %ebp, %esi
movq %rax, %rdx
movl %r15d, %ecx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB21_2: # %gpu_iallocate.exit
movq (%rsp), %rax
movq %rax, (%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end21:
.size gpu_iallocate_, .Lfunc_end21-gpu_iallocate_
.cfi_endproc
# -- End function
.globl gpu_callocate_ # -- Begin function gpu_callocate_
.p2align 4, 0x90
.type gpu_callocate_,@function
gpu_callocate_: # @gpu_callocate_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r14
movq %rdi, %rbx
movslq (%rsi), %r15
leaq (,%r15,8), %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB22_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %edi
movl %ebp, %esi
movq %rax, %rdx
movl %r15d, %ecx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB22_2: # %gpu_callocate.exit
movq (%rsp), %rax
movq %rax, (%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end22:
.size gpu_callocate_, .Lfunc_end22-gpu_callocate_
.cfi_endproc
# -- End function
.globl gpu_deallocate_ # -- Begin function gpu_deallocate_
.p2align 4, 0x90
.type gpu_deallocate_,@function
gpu_deallocate_: # @gpu_deallocate_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq %rdi, %rbx
movq (%rdi), %rdi
callq hipFree
testl %eax, %eax
je .LBB23_2
# %bb.1:
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %edi
movl %ebp, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, (%r14)
.LBB23_2: # %gpu_deallocate.exit
movq $0, (%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end23:
.size gpu_deallocate_, .Lfunc_end23-gpu_deallocate_
.cfi_endproc
# -- End function
.globl gpu_fcopyin_ # -- Begin function gpu_fcopyin_
.p2align 4, 0x90
.type gpu_fcopyin_,@function
gpu_fcopyin_: # @gpu_fcopyin_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rax
movq (%rsi), %rdi
movslq (%rdx), %rdx
shlq $2, %rdx
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB24_2
# %bb.1: # %gpu_fcopyin.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB24_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.4, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end24:
.size gpu_fcopyin_, .Lfunc_end24-gpu_fcopyin_
.cfi_endproc
# -- End function
.globl gpu_fcopyout_ # -- Begin function gpu_fcopyout_
.p2align 4, 0x90
.type gpu_fcopyout_,@function
gpu_fcopyout_: # @gpu_fcopyout_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq (%rsi), %rsi
movslq (%rdx), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB25_2
# %bb.1: # %gpu_fcopyout.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB25_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.5, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end25:
.size gpu_fcopyout_, .Lfunc_end25-gpu_fcopyout_
.cfi_endproc
# -- End function
.globl gpu_icopyin_ # -- Begin function gpu_icopyin_
.p2align 4, 0x90
.type gpu_icopyin_,@function
gpu_icopyin_: # @gpu_icopyin_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rax
movq (%rsi), %rdi
movslq (%rdx), %rdx
shlq $2, %rdx
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB26_2
# %bb.1: # %gpu_icopyin.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB26_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.6, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end26:
.size gpu_icopyin_, .Lfunc_end26-gpu_icopyin_
.cfi_endproc
# -- End function
.globl gpu_icopyout_ # -- Begin function gpu_icopyout_
.p2align 4, 0x90
.type gpu_icopyout_,@function
gpu_icopyout_: # @gpu_icopyout_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq (%rsi), %rsi
movslq (%rdx), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB27_2
# %bb.1: # %gpu_icopyout.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB27_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.7, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end27:
.size gpu_icopyout_, .Lfunc_end27-gpu_icopyout_
.cfi_endproc
# -- End function
.globl gpu_ccopyin_ # -- Begin function gpu_ccopyin_
.p2align 4, 0x90
.type gpu_ccopyin_,@function
gpu_ccopyin_: # @gpu_ccopyin_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rax
movq (%rsi), %rdi
movslq (%rdx), %rdx
shlq $3, %rdx
movq %rax, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB28_2
# %bb.1: # %gpu_ccopyin.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB28_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.8, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end28:
.size gpu_ccopyin_, .Lfunc_end28-gpu_ccopyin_
.cfi_endproc
# -- End function
.globl gpu_ccopyout_ # -- Begin function gpu_ccopyout_
.p2align 4, 0x90
.type gpu_ccopyout_,@function
gpu_ccopyout_: # @gpu_ccopyout_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq (%rsi), %rsi
movslq (%rdx), %rdx
shlq $3, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB29_2
# %bb.1: # %gpu_ccopyout.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB29_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.9, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end29:
.size gpu_ccopyout_, .Lfunc_end29-gpu_ccopyout_
.cfi_endproc
# -- End function
.globl gpu_zfmem_ # -- Begin function gpu_zfmem_
.p2align 4, 0x90
.type gpu_zfmem_,@function
gpu_zfmem_: # @gpu_zfmem_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq (%rdi), %rdi
movslq (%rsi), %rdx
shlq $2, %rdx
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB30_2
# %bb.1: # %gpu_zfmem.exit
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB30_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.10, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end30:
.size gpu_zfmem_, .Lfunc_end30-gpu_zfmem_
.cfi_endproc
# -- End function
.globl gpu_set_cache_size_ # -- Begin function gpu_set_cache_size_
.p2align 4, 0x90
.type gpu_set_cache_size_,@function
gpu_set_cache_size_: # @gpu_set_cache_size_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl (%rdi), %eax
cmpl $2, %eax
ja .LBB31_2
# %bb.1:
xorl %edi, %edi
cmpl $1, %eax
setne %dil
incl %edi
testl %eax, %eax
cmovel %eax, %edi
callq hipDeviceSetCacheConfig
testl %eax, %eax
je .LBB31_2
# %bb.3:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB31_2: # %gpu_set_cache_size.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end31:
.size gpu_set_cache_size_, .Lfunc_end31-gpu_set_cache_size_
.cfi_endproc
# -- End function
.globl emptykernel_ # -- Begin function emptykernel_
.p2align 4, 0x90
.type emptykernel_,@function
emptykernel_: # @emptykernel_
.cfi_startproc
# %bb.0:
jmp emptykernel # TAILCALL
.Lfunc_end32:
.size emptykernel_, .Lfunc_end32-emptykernel_
.cfi_endproc
# -- End function
.globl init_cu_ # -- Begin function init_cu_
.p2align 4, 0x90
.type init_cu_,@function
init_cu_: # @init_cu_
.cfi_startproc
# %bb.0:
movl (%rdi), %edi
jmp init_cu # TAILCALL
.Lfunc_end33:
.size init_cu_, .Lfunc_end33-init_cu_
.cfi_endproc
# -- End function
.globl end_cu_ # -- Begin function end_cu_
.p2align 4, 0x90
.type end_cu_,@function
end_cu_: # @end_cu_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq hipDeviceReset
testl %eax, %eax
je .LBB34_1
# %bb.2:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.19, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB34_1: # %end_cu.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end34:
.size end_cu_, .Lfunc_end34-end_cu_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB35_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB35_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11emptyKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end35:
.size __hip_module_ctor, .Lfunc_end35-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB36_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB36_2:
retq
.Lfunc_end36:
.size __hip_module_dtor, .Lfunc_end36-__hip_module_dtor
.cfi_endproc
# -- End function
.type nblock_size,@object # @nblock_size
.data
.globl nblock_size
.p2align 2, 0x0
nblock_size:
.long 64 # 0x40
.size nblock_size, 4
.type ngrid_size,@object # @ngrid_size
.globl ngrid_size
.p2align 2, 0x0
ngrid_size:
.long 1 # 0x1
.size ngrid_size, 4
.type maxgsx,@object # @maxgsx
.globl maxgsx
.p2align 2, 0x0
maxgsx:
.long 65535 # 0xffff
.size maxgsx, 4
.type mmcc,@object # @mmcc
.bss
.globl mmcc
.p2align 2, 0x0
mmcc:
.long 0 # 0x0
.size mmcc, 4
.type _Z11emptyKernelv,@object # @_Z11emptyKernelv
.section .rodata,"a",@progbits
.globl _Z11emptyKernelv
.p2align 3, 0x0
_Z11emptyKernelv:
.quad _Z26__device_stub__emptyKernelv
.size _Z11emptyKernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMalloc float Error=%d:%s,l=%d\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc int Error=%d:%s,l=%d\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc float2 Error=%d:%s,l=%d\n"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipFree Error=%d:%s\n"
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpyHostToDevice float Error=%d:%s\n"
.size .L.str.4, 41
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpyDeviceToHost float Error=%d:%s\n"
.size .L.str.5, 41
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpyHostToDevice int Error=%d:%s\n"
.size .L.str.6, 39
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpyDeviceToHost int Error=%d:%s\n"
.size .L.str.7, 39
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpyHostToDevice float2 Error=%d:%s\n"
.size .L.str.8, 42
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMemcpyDeviceToHost float2 Error=%d:%s\n"
.size .L.str.9, 42
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipMemset Error=%d:%s\n"
.size .L.str.10, 23
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipDeviceSetCacheConfig error=%d:%s\n"
.size .L.str.11, 37
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "emptyKernel error=%d:%s\n"
.size .L.str.12, 25
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipGetDeviceCount Error=%i:%s\n"
.size .L.str.13, 31
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "hipGetDeviceProperties Error=%i:%s\n"
.size .L.str.14, 36
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "j=%i:CUDA_DEVICE_NAME=%s,CUDA_MULTIPROCESSOR_COUNT=%i\n"
.size .L.str.15, 55
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " CUDA_GLOBAL_MEM_SIZE=%lu(%f GB),Capability=%d\n"
.size .L.str.16, 51
.type _ZL5devid,@object # @_ZL5devid
.local _ZL5devid
.comm _ZL5devid,4,4
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "using device j=%i\n"
.size .L.str.17, 19
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "hipSetDevice Error=%i:%s\n"
.size .L.str.18, 26
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "hipDeviceReset Error=%d:%s\n"
.size .L.str.19, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11emptyKernelv"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__emptyKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11emptyKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11emptyKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11emptyKernelv
.globl _Z11emptyKernelv
.p2align 8
.type _Z11emptyKernelv,@function
_Z11emptyKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11emptyKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11emptyKernelv, .Lfunc_end0-_Z11emptyKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11emptyKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z11emptyKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
__global__ void scan(int* v, const int n);
int main(int argc, char** argv) {
const int size = 10;
int h_v[size] = { 3, 7, 1, 10, 6, 9, 5, 2, 8, 4 };
int *d_v = 0;
cudaMalloc((void**)&d_v, size * sizeof(int));
cudaMemcpy(d_v, h_v, size * sizeof(int), cudaMemcpyHostToDevice);
dim3 grdDim(1, 1, 1);
dim3 blkDim(size - 1, 1, 1);
scan <<<grdDim, blkDim>>>(d_v, size);
cudaMemcpy(h_v, d_v, size * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_v);
for (int i = 0; i < size; i++) {
std::cout << (i == 0 ? "{" : "") << h_v[i] << (i < size -1 ? " ," : "}");
}
std::cout << std::endl;
return 0;
}
__global__ void scan(int *v, const int n)
{
int tIdx = threadIdx.x;
int step = 1;
while (step < n) {
int indiceDroite = tIdx;
int indiceGauche = indiceDroite + step;
if (indiceGauche < n) {
v[indiceDroite] = v[indiceDroite] + v[indiceGauche];
}
step = step * 2;
__syncthreads();
}
} | code for sm_80
Function : _Z4scanPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, c[0x0][0x168] ; /* 0x00005a0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fce00078e0203 */
/*0090*/ IMAD.IADD R0, R6, 0x1, R7 ; /* 0x0000000106007824 */
/* 0x000fe200078e0207 */
/*00a0*/ BSSY B0, 0x130 ; /* 0x0000008000007945 */
/* 0x000fe80003800000 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*00c0*/ @P0 BRA 0x120 ; /* 0x0000005000000947 */
/* 0x001fea0003800000 */
/*00d0*/ IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407047825 */
/* 0x000fe200078e0202 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000eaa000c1e1900 */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0100*/ IADD3 R9, R0, R5, RZ ; /* 0x0000000500097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0150*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fda0003f06270 */
/*0160*/ @!P0 BRA 0x90 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
__global__ void scan(int* v, const int n);
int main(int argc, char** argv) {
const int size = 10;
int h_v[size] = { 3, 7, 1, 10, 6, 9, 5, 2, 8, 4 };
int *d_v = 0;
cudaMalloc((void**)&d_v, size * sizeof(int));
cudaMemcpy(d_v, h_v, size * sizeof(int), cudaMemcpyHostToDevice);
dim3 grdDim(1, 1, 1);
dim3 blkDim(size - 1, 1, 1);
scan <<<grdDim, blkDim>>>(d_v, size);
cudaMemcpy(h_v, d_v, size * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_v);
for (int i = 0; i < size; i++) {
std::cout << (i == 0 ? "{" : "") << h_v[i] << (i < size -1 ? " ," : "}");
}
std::cout << std::endl;
return 0;
}
__global__ void scan(int *v, const int n)
{
int tIdx = threadIdx.x;
int step = 1;
while (step < n) {
int indiceDroite = tIdx;
int indiceGauche = indiceDroite + step;
if (indiceGauche < n) {
v[indiceDroite] = v[indiceDroite] + v[indiceGauche];
}
step = step * 2;
__syncthreads();
}
} | .file "tmpxft_000d50f4_00000000-6_generic-scan.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4scanPiiPii
.type _Z24__device_stub__Z4scanPiiPii, @function
_Z24__device_stub__Z4scanPiiPii:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4scanPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z4scanPiiPii, .-_Z24__device_stub__Z4scanPiiPii
.globl _Z4scanPii
.type _Z4scanPii, @function
_Z4scanPii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4scanPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4scanPii, .-_Z4scanPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ""
.LC1:
.string "}"
.LC2:
.string " ,"
.LC3:
.string "{"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $3, 32(%rsp)
movl $7, 36(%rsp)
movl $1, 40(%rsp)
movl $10, 44(%rsp)
movl $6, 48(%rsp)
movl $9, 52(%rsp)
movl $5, 56(%rsp)
movl $2, 60(%rsp)
movl $8, 64(%rsp)
movl $4, 68(%rsp)
movq $0, (%rsp)
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $9, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC3(%rip), %r14
leaq _ZSt4cout(%rip), %rbp
leaq .LC2(%rip), %r12
leaq .LC0(%rip), %r13
jmp .L16
.L21:
movl $10, %esi
movq (%rsp), %rdi
call _Z24__device_stub__Z4scanPiiPii
jmp .L12
.L13:
movl $1, %edx
movq %r14, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 32(%rsp,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
.L14:
movl $2, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
.L16:
testl %ebx, %ebx
je .L13
movl $0, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 32(%rsp,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
cmpl $8, %ebx
jle .L14
movl $1, %edx
leaq .LC1(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L16
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z4scanPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
__global__ void scan(int* v, const int n);
int main(int argc, char** argv) {
const int size = 10;
int h_v[size] = { 3, 7, 1, 10, 6, 9, 5, 2, 8, 4 };
int *d_v = 0;
cudaMalloc((void**)&d_v, size * sizeof(int));
cudaMemcpy(d_v, h_v, size * sizeof(int), cudaMemcpyHostToDevice);
dim3 grdDim(1, 1, 1);
dim3 blkDim(size - 1, 1, 1);
scan <<<grdDim, blkDim>>>(d_v, size);
cudaMemcpy(h_v, d_v, size * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_v);
for (int i = 0; i < size; i++) {
std::cout << (i == 0 ? "{" : "") << h_v[i] << (i < size -1 ? " ," : "}");
}
std::cout << std::endl;
return 0;
}
__global__ void scan(int *v, const int n)
{
int tIdx = threadIdx.x;
int step = 1;
while (step < n) {
int indiceDroite = tIdx;
int indiceGauche = indiceDroite + step;
if (indiceGauche < n) {
v[indiceDroite] = v[indiceDroite] + v[indiceGauche];
}
step = step * 2;
__syncthreads();
}
} | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void scan(int* v, const int n);
int main(int argc, char** argv) {
const int size = 10;
int h_v[size] = { 3, 7, 1, 10, 6, 9, 5, 2, 8, 4 };
int *d_v = 0;
hipMalloc((void**)&d_v, size * sizeof(int));
hipMemcpy(d_v, h_v, size * sizeof(int), hipMemcpyHostToDevice);
dim3 grdDim(1, 1, 1);
dim3 blkDim(size - 1, 1, 1);
scan <<<grdDim, blkDim>>>(d_v, size);
hipMemcpy(h_v, d_v, size * sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_v);
for (int i = 0; i < size; i++) {
std::cout << (i == 0 ? "{" : "") << h_v[i] << (i < size -1 ? " ," : "}");
}
std::cout << std::endl;
return 0;
}
__global__ void scan(int *v, const int n)
{
int tIdx = threadIdx.x;
int step = 1;
while (step < n) {
int indiceDroite = tIdx;
int indiceGauche = indiceDroite + step;
if (indiceGauche < n) {
v[indiceDroite] = v[indiceDroite] + v[indiceGauche];
}
step = step * 2;
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void scan(int* v, const int n);
int main(int argc, char** argv) {
const int size = 10;
int h_v[size] = { 3, 7, 1, 10, 6, 9, 5, 2, 8, 4 };
int *d_v = 0;
hipMalloc((void**)&d_v, size * sizeof(int));
hipMemcpy(d_v, h_v, size * sizeof(int), hipMemcpyHostToDevice);
dim3 grdDim(1, 1, 1);
dim3 blkDim(size - 1, 1, 1);
scan <<<grdDim, blkDim>>>(d_v, size);
hipMemcpy(h_v, d_v, size * sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_v);
for (int i = 0; i < size; i++) {
std::cout << (i == 0 ? "{" : "") << h_v[i] << (i < size -1 ? " ," : "}");
}
std::cout << std::endl;
return 0;
}
__global__ void scan(int *v, const int n)
{
int tIdx = threadIdx.x;
int step = 1;
while (step < n) {
int indiceDroite = tIdx;
int indiceGauche = indiceDroite + step;
if (indiceGauche < n) {
v[indiceDroite] = v[indiceDroite] + v[indiceGauche];
}
step = step * 2;
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4scanPii
.globl _Z4scanPii
.p2align 8
.type _Z4scanPii,@function
_Z4scanPii:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s3, s0, v1
v_add_co_ci_u32_e64 v4, null, s1, 0, s3
s_mov_b32 s3, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s3, s3, 1
s_waitcnt_vscnt null, 0x0
s_cmp_lt_i32 s3, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_3:
v_add_nc_u32_e32 v1, s3, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v5, v1
global_store_b32 v[3:4], v1, off
s_branch .LBB0_2
.LBB0_5:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4scanPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4scanPii, .Lfunc_end0-_Z4scanPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4scanPii
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z4scanPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void scan(int* v, const int n);
int main(int argc, char** argv) {
const int size = 10;
int h_v[size] = { 3, 7, 1, 10, 6, 9, 5, 2, 8, 4 };
int *d_v = 0;
hipMalloc((void**)&d_v, size * sizeof(int));
hipMemcpy(d_v, h_v, size * sizeof(int), hipMemcpyHostToDevice);
dim3 grdDim(1, 1, 1);
dim3 blkDim(size - 1, 1, 1);
scan <<<grdDim, blkDim>>>(d_v, size);
hipMemcpy(h_v, d_v, size * sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_v);
for (int i = 0; i < size; i++) {
std::cout << (i == 0 ? "{" : "") << h_v[i] << (i < size -1 ? " ," : "}");
}
std::cout << std::endl;
return 0;
}
__global__ void scan(int *v, const int n)
{
int tIdx = threadIdx.x;
int step = 1;
while (step < n) {
int indiceDroite = tIdx;
int indiceGauche = indiceDroite + step;
if (indiceGauche < n) {
v[indiceDroite] = v[indiceDroite] + v[indiceGauche];
}
step = step * 2;
__syncthreads();
}
} | .text
.file "generic-scan.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 3 # 0x3
.long 7 # 0x7
.long 1 # 0x1
.long 10 # 0xa
.LCPI0_1:
.long 6 # 0x6
.long 9 # 0x9
.long 5 # 0x5
.long 2 # 0x2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [3,7,1,10]
movaps %xmm0, 96(%rsp)
movaps .LCPI0_1(%rip), %xmm0 # xmm0 = [6,9,5,2]
movaps %xmm0, 112(%rsp)
movabsq $17179869192, %rax # imm = 0x400000008
movq %rax, 128(%rsp)
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 8(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $10, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4scanPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
movl $.L.str, %r14d
movl $.L.str.3, %r15d
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
xorl %edx, %edx
testq %rbx, %rbx
sete %dl
movl $.L.str.1, %esi
cmoveq %r14, %rsi
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 96(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
xorl %edx, %edx
cmpq $9, %rbx
movl $.L.str.2, %esi
cmoveq %r15, %rsi
setne %dl
incq %rdx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $10, %rbx
jne .LBB0_3
# %bb.4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB0_8
.LBB0_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_9:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z19__device_stub__scanPii # -- Begin function _Z19__device_stub__scanPii
.p2align 4, 0x90
.type _Z19__device_stub__scanPii,@function
_Z19__device_stub__scanPii: # @_Z19__device_stub__scanPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4scanPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__scanPii, .Lfunc_end1-_Z19__device_stub__scanPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4scanPii,@object # @_Z4scanPii
.section .rodata,"a",@progbits
.globl _Z4scanPii
.p2align 3, 0x0
_Z4scanPii:
.quad _Z19__device_stub__scanPii
.size _Z4scanPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "{"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.zero 1
.size .L.str.1, 1
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ,"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "}"
.size .L.str.3, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4scanPii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__scanPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4scanPii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4scanPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, c[0x0][0x168] ; /* 0x00005a0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fce00078e0203 */
/*0090*/ IMAD.IADD R0, R6, 0x1, R7 ; /* 0x0000000106007824 */
/* 0x000fe200078e0207 */
/*00a0*/ BSSY B0, 0x130 ; /* 0x0000008000007945 */
/* 0x000fe80003800000 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*00c0*/ @P0 BRA 0x120 ; /* 0x0000005000000947 */
/* 0x001fea0003800000 */
/*00d0*/ IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407047825 */
/* 0x000fe200078e0202 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000eaa000c1e1900 */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0100*/ IADD3 R9, R0, R5, RZ ; /* 0x0000000500097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0150*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fda0003f06270 */
/*0160*/ @!P0 BRA 0x90 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4scanPii
.globl _Z4scanPii
.p2align 8
.type _Z4scanPii,@function
_Z4scanPii:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s3, s0, v1
v_add_co_ci_u32_e64 v4, null, s1, 0, s3
s_mov_b32 s3, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s3, s3, 1
s_waitcnt_vscnt null, 0x0
s_cmp_lt_i32 s3, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_3:
v_add_nc_u32_e32 v1, s3, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v5, v1
global_store_b32 v[3:4], v1, off
s_branch .LBB0_2
.LBB0_5:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4scanPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4scanPii, .Lfunc_end0-_Z4scanPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4scanPii
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z4scanPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d50f4_00000000-6_generic-scan.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4scanPiiPii
.type _Z24__device_stub__Z4scanPiiPii, @function
_Z24__device_stub__Z4scanPiiPii:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4scanPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z4scanPiiPii, .-_Z24__device_stub__Z4scanPiiPii
.globl _Z4scanPii
.type _Z4scanPii, @function
_Z4scanPii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4scanPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4scanPii, .-_Z4scanPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ""
.LC1:
.string "}"
.LC2:
.string " ,"
.LC3:
.string "{"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $3, 32(%rsp)
movl $7, 36(%rsp)
movl $1, 40(%rsp)
movl $10, 44(%rsp)
movl $6, 48(%rsp)
movl $9, 52(%rsp)
movl $5, 56(%rsp)
movl $2, 60(%rsp)
movl $8, 64(%rsp)
movl $4, 68(%rsp)
movq $0, (%rsp)
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $9, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC3(%rip), %r14
leaq _ZSt4cout(%rip), %rbp
leaq .LC2(%rip), %r12
leaq .LC0(%rip), %r13
jmp .L16
.L21:
movl $10, %esi
movq (%rsp), %rdi
call _Z24__device_stub__Z4scanPiiPii
jmp .L12
.L13:
movl $1, %edx
movq %r14, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 32(%rsp,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
.L14:
movl $2, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
.L16:
testl %ebx, %ebx
je .L13
movl $0, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 32(%rsp,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
cmpl $8, %ebx
jle .L14
movl $1, %edx
leaq .LC1(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L16
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z4scanPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "generic-scan.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 3 # 0x3
.long 7 # 0x7
.long 1 # 0x1
.long 10 # 0xa
.LCPI0_1:
.long 6 # 0x6
.long 9 # 0x9
.long 5 # 0x5
.long 2 # 0x2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [3,7,1,10]
movaps %xmm0, 96(%rsp)
movaps .LCPI0_1(%rip), %xmm0 # xmm0 = [6,9,5,2]
movaps %xmm0, 112(%rsp)
movabsq $17179869192, %rax # imm = 0x400000008
movq %rax, 128(%rsp)
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 8(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $10, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4scanPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
movl $.L.str, %r14d
movl $.L.str.3, %r15d
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
xorl %edx, %edx
testq %rbx, %rbx
sete %dl
movl $.L.str.1, %esi
cmoveq %r14, %rsi
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 96(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
xorl %edx, %edx
cmpq $9, %rbx
movl $.L.str.2, %esi
cmoveq %r15, %rsi
setne %dl
incq %rdx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $10, %rbx
jne .LBB0_3
# %bb.4:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB0_8
.LBB0_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_9:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z19__device_stub__scanPii # -- Begin function _Z19__device_stub__scanPii
.p2align 4, 0x90
.type _Z19__device_stub__scanPii,@function
_Z19__device_stub__scanPii: # @_Z19__device_stub__scanPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4scanPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__scanPii, .Lfunc_end1-_Z19__device_stub__scanPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4scanPii,@object # @_Z4scanPii
.section .rodata,"a",@progbits
.globl _Z4scanPii
.p2align 3, 0x0
_Z4scanPii:
.quad _Z19__device_stub__scanPii
.size _Z4scanPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "{"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.zero 1
.size .L.str.1, 1
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ,"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "}"
.size .L.str.3, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4scanPii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__scanPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4scanPii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define MATRIX_DIM 10
__host__ double* createArrayWithRandoms(){
double *matrix = (double *) malloc(MATRIX_DIM * sizeof(double));
for (int i = 0; i < MATRIX_DIM; i++)
*(matrix + i) = (10.0*rand()/(RAND_MAX+1.0));
return matrix;
}
__global__ void addArrays(double *a, double *b, double *c, int length){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < length)
*(c + i) = *(a + i) + *(b + i);
}
__host__ void checkError(cudaError_t error, const char *point){
if (error != cudaSuccess){
printf("there was an error at %s, error code: %d", point, error);
exit(EXIT_FAILURE);
}
}
int main(){
cudaError_t error = cudaSuccess;
size_t size = MATRIX_DIM * sizeof(double);
double *h_a = createArrayWithRandoms();
double *h_b = createArrayWithRandoms();
double *h_c = (double *) malloc(MATRIX_DIM * sizeof(double));
double *d_a , *d_b, *d_c;
error = cudaMalloc(&d_a, size);
checkError(error, "allocating device memory for A");
error = cudaMalloc(&d_b, size);
checkError(error, "allocating device memory for B");
error = cudaMalloc(&d_c, size);
checkError(error, "allocating device memory for C");
cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
checkError(error, "copy A from host to device");
cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);
checkError(error, "copy B from host to device");
cudaMemcpy(d_c, h_c, size, cudaMemcpyHostToDevice);
checkError(error, "copy C from host to device");
addArrays<<< 1, MATRIX_DIM >>>(d_a, d_b, d_c, MATRIX_DIM);
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
checkError(error, "copy C from device to host");
for (int i = 0; i < MATRIX_DIM; i++)
printf("%.2f + %.2f = %.2f \n", *(h_a + i), *(h_b + i), *(h_c + i));
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z9addArraysPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define MATRIX_DIM 10
__host__ double* createArrayWithRandoms(){
double *matrix = (double *) malloc(MATRIX_DIM * sizeof(double));
for (int i = 0; i < MATRIX_DIM; i++)
*(matrix + i) = (10.0*rand()/(RAND_MAX+1.0));
return matrix;
}
__global__ void addArrays(double *a, double *b, double *c, int length){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < length)
*(c + i) = *(a + i) + *(b + i);
}
__host__ void checkError(cudaError_t error, const char *point){
if (error != cudaSuccess){
printf("there was an error at %s, error code: %d", point, error);
exit(EXIT_FAILURE);
}
}
int main(){
cudaError_t error = cudaSuccess;
size_t size = MATRIX_DIM * sizeof(double);
double *h_a = createArrayWithRandoms();
double *h_b = createArrayWithRandoms();
double *h_c = (double *) malloc(MATRIX_DIM * sizeof(double));
double *d_a , *d_b, *d_c;
error = cudaMalloc(&d_a, size);
checkError(error, "allocating device memory for A");
error = cudaMalloc(&d_b, size);
checkError(error, "allocating device memory for B");
error = cudaMalloc(&d_c, size);
checkError(error, "allocating device memory for C");
cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
checkError(error, "copy A from host to device");
cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);
checkError(error, "copy B from host to device");
cudaMemcpy(d_c, h_c, size, cudaMemcpyHostToDevice);
checkError(error, "copy C from host to device");
addArrays<<< 1, MATRIX_DIM >>>(d_a, d_b, d_c, MATRIX_DIM);
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
checkError(error, "copy C from device to host");
for (int i = 0; i < MATRIX_DIM; i++)
printf("%.2f + %.2f = %.2f \n", *(h_a + i), *(h_b + i), *(h_c + i));
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_00000609_00000000-6_cudaMatrices.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22createArrayWithRandomsv
.type _Z22createArrayWithRandomsv, @function
_Z22createArrayWithRandomsv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $80, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, %rbx
leaq 80(%rax), %rbp
.L4:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L4
movq %r12, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z22createArrayWithRandomsv, .-_Z22createArrayWithRandomsv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "there was an error at %s, error code: %d"
.text
.globl _Z10checkError9cudaErrorPKc
.type _Z10checkError9cudaErrorPKc, @function
_Z10checkError9cudaErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L12
ret
.L12:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %ecx
movq %rsi, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10checkError9cudaErrorPKc, .-_Z10checkError9cudaErrorPKc
.globl _Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i
.type _Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i, @function
_Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addArraysPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i, .-_Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i
.globl _Z9addArraysPdS_S_i
.type _Z9addArraysPdS_S_i, @function
_Z9addArraysPdS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9addArraysPdS_S_i, .-_Z9addArraysPdS_S_i
.section .rodata.str1.8
.align 8
.LC3:
.string "allocating device memory for A"
.align 8
.LC4:
.string "allocating device memory for B"
.align 8
.LC5:
.string "allocating device memory for C"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "copy A from host to device"
.LC7:
.string "copy B from host to device"
.LC8:
.string "copy C from host to device"
.LC9:
.string "copy C from device to host"
.LC10:
.string "%.2f + %.2f = %.2f \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _Z22createArrayWithRandomsv
movq %rax, %r13
call _Z22createArrayWithRandomsv
movq %rax, %r12
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %edi
leaq .LC3(%rip), %rsi
call _Z10checkError9cudaErrorPKc
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %edi
leaq .LC4(%rip), %rsi
call _Z10checkError9cudaErrorPKc
leaq 24(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %ebx
leaq .LC5(%rip), %rsi
movl %eax, %edi
call _Z10checkError9cudaErrorPKc
movl $1, %ecx
movl $80, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl %ebx, %edi
call _Z10checkError9cudaErrorPKc
movl $1, %ecx
movl $80, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
movl %ebx, %edi
call _Z10checkError9cudaErrorPKc
movl $1, %ecx
movl $80, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl %ebx, %edi
call _Z10checkError9cudaErrorPKc
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L22:
movl $2, %ecx
movl $80, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC9(%rip), %rsi
movl %ebx, %edi
call _Z10checkError9cudaErrorPKc
movl $0, %ebx
leaq .LC10(%rip), %r14
.L23:
movsd 0(%r13,%rbx), %xmm0
movsd 0(%rbp,%rbx), %xmm2
movsd (%r12,%rbx), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq $80, %rbx
jne .L23
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $10, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i
jmp .L22
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z9addArraysPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addArraysPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1076101120
.align 8
.LC1:
.long 0
.long 1040187392
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define MATRIX_DIM 10
__host__ double* createArrayWithRandoms(){
double *matrix = (double *) malloc(MATRIX_DIM * sizeof(double));
for (int i = 0; i < MATRIX_DIM; i++)
*(matrix + i) = (10.0*rand()/(RAND_MAX+1.0));
return matrix;
}
__global__ void addArrays(double *a, double *b, double *c, int length){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < length)
*(c + i) = *(a + i) + *(b + i);
}
__host__ void checkError(cudaError_t error, const char *point){
if (error != cudaSuccess){
printf("there was an error at %s, error code: %d", point, error);
exit(EXIT_FAILURE);
}
}
int main(){
cudaError_t error = cudaSuccess;
size_t size = MATRIX_DIM * sizeof(double);
double *h_a = createArrayWithRandoms();
double *h_b = createArrayWithRandoms();
double *h_c = (double *) malloc(MATRIX_DIM * sizeof(double));
double *d_a , *d_b, *d_c;
error = cudaMalloc(&d_a, size);
checkError(error, "allocating device memory for A");
error = cudaMalloc(&d_b, size);
checkError(error, "allocating device memory for B");
error = cudaMalloc(&d_c, size);
checkError(error, "allocating device memory for C");
cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
checkError(error, "copy A from host to device");
cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);
checkError(error, "copy B from host to device");
cudaMemcpy(d_c, h_c, size, cudaMemcpyHostToDevice);
checkError(error, "copy C from host to device");
addArrays<<< 1, MATRIX_DIM >>>(d_a, d_b, d_c, MATRIX_DIM);
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
checkError(error, "copy C from device to host");
for (int i = 0; i < MATRIX_DIM; i++)
printf("%.2f + %.2f = %.2f \n", *(h_a + i), *(h_b + i), *(h_c + i));
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define MATRIX_DIM 10
__host__ double* createArrayWithRandoms(){
double *matrix = (double *) malloc(MATRIX_DIM * sizeof(double));
for (int i = 0; i < MATRIX_DIM; i++)
*(matrix + i) = (10.0*rand()/(RAND_MAX+1.0));
return matrix;
}
__global__ void addArrays(double *a, double *b, double *c, int length){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < length)
*(c + i) = *(a + i) + *(b + i);
}
__host__ void checkError(hipError_t error, const char *point){
if (error != hipSuccess){
printf("there was an error at %s, error code: %d", point, error);
exit(EXIT_FAILURE);
}
}
int main(){
hipError_t error = hipSuccess;
size_t size = MATRIX_DIM * sizeof(double);
double *h_a = createArrayWithRandoms();
double *h_b = createArrayWithRandoms();
double *h_c = (double *) malloc(MATRIX_DIM * sizeof(double));
double *d_a , *d_b, *d_c;
error = hipMalloc(&d_a, size);
checkError(error, "allocating device memory for A");
error = hipMalloc(&d_b, size);
checkError(error, "allocating device memory for B");
error = hipMalloc(&d_c, size);
checkError(error, "allocating device memory for C");
hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
checkError(error, "copy A from host to device");
hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);
checkError(error, "copy B from host to device");
hipMemcpy(d_c, h_c, size, hipMemcpyHostToDevice);
checkError(error, "copy C from host to device");
addArrays<<< 1, MATRIX_DIM >>>(d_a, d_b, d_c, MATRIX_DIM);
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
checkError(error, "copy C from device to host");
for (int i = 0; i < MATRIX_DIM; i++)
printf("%.2f + %.2f = %.2f \n", *(h_a + i), *(h_b + i), *(h_c + i));
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define MATRIX_DIM 10
__host__ double* createArrayWithRandoms(){
double *matrix = (double *) malloc(MATRIX_DIM * sizeof(double));
for (int i = 0; i < MATRIX_DIM; i++)
*(matrix + i) = (10.0*rand()/(RAND_MAX+1.0));
return matrix;
}
__global__ void addArrays(double *a, double *b, double *c, int length){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < length)
*(c + i) = *(a + i) + *(b + i);
}
__host__ void checkError(hipError_t error, const char *point){
if (error != hipSuccess){
printf("there was an error at %s, error code: %d", point, error);
exit(EXIT_FAILURE);
}
}
int main(){
hipError_t error = hipSuccess;
size_t size = MATRIX_DIM * sizeof(double);
double *h_a = createArrayWithRandoms();
double *h_b = createArrayWithRandoms();
double *h_c = (double *) malloc(MATRIX_DIM * sizeof(double));
double *d_a , *d_b, *d_c;
error = hipMalloc(&d_a, size);
checkError(error, "allocating device memory for A");
error = hipMalloc(&d_b, size);
checkError(error, "allocating device memory for B");
error = hipMalloc(&d_c, size);
checkError(error, "allocating device memory for C");
hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
checkError(error, "copy A from host to device");
hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);
checkError(error, "copy B from host to device");
hipMemcpy(d_c, h_c, size, hipMemcpyHostToDevice);
checkError(error, "copy C from host to device");
addArrays<<< 1, MATRIX_DIM >>>(d_a, d_b, d_c, MATRIX_DIM);
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
checkError(error, "copy C from device to host");
for (int i = 0; i < MATRIX_DIM; i++)
printf("%.2f + %.2f = %.2f \n", *(h_a + i), *(h_b + i), *(h_c + i));
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addArraysPdS_S_i
.globl _Z9addArraysPdS_S_i
.p2align 8
.type _Z9addArraysPdS_S_i,@function
_Z9addArraysPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addArraysPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addArraysPdS_S_i, .Lfunc_end0-_Z9addArraysPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addArraysPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addArraysPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define MATRIX_DIM 10
__host__ double* createArrayWithRandoms(){
double *matrix = (double *) malloc(MATRIX_DIM * sizeof(double));
for (int i = 0; i < MATRIX_DIM; i++)
*(matrix + i) = (10.0*rand()/(RAND_MAX+1.0));
return matrix;
}
__global__ void addArrays(double *a, double *b, double *c, int length){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < length)
*(c + i) = *(a + i) + *(b + i);
}
__host__ void checkError(hipError_t error, const char *point){
if (error != hipSuccess){
printf("there was an error at %s, error code: %d", point, error);
exit(EXIT_FAILURE);
}
}
int main(){
hipError_t error = hipSuccess;
size_t size = MATRIX_DIM * sizeof(double);
double *h_a = createArrayWithRandoms();
double *h_b = createArrayWithRandoms();
double *h_c = (double *) malloc(MATRIX_DIM * sizeof(double));
double *d_a , *d_b, *d_c;
error = hipMalloc(&d_a, size);
checkError(error, "allocating device memory for A");
error = hipMalloc(&d_b, size);
checkError(error, "allocating device memory for B");
error = hipMalloc(&d_c, size);
checkError(error, "allocating device memory for C");
hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
checkError(error, "copy A from host to device");
hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);
checkError(error, "copy B from host to device");
hipMemcpy(d_c, h_c, size, hipMemcpyHostToDevice);
checkError(error, "copy C from host to device");
addArrays<<< 1, MATRIX_DIM >>>(d_a, d_b, d_c, MATRIX_DIM);
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
checkError(error, "copy C from device to host");
for (int i = 0; i < MATRIX_DIM; i++)
printf("%.2f + %.2f = %.2f \n", *(h_a + i), *(h_b + i), *(h_c + i));
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "cudaMatrices.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z22createArrayWithRandomsv
.LCPI0_0:
.quad 0x4024000000000000 # double 10
.LCPI0_1:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.text
.globl _Z22createArrayWithRandomsv
.p2align 4, 0x90
.type _Z22createArrayWithRandomsv,@function
_Z22createArrayWithRandomsv: # @_Z22createArrayWithRandomsv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $80, %edi
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
movsd %xmm0, (%rbx,%r14,8)
incq %r14
cmpq $10, %r14
jne .LBB0_1
# %bb.2:
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z22createArrayWithRandomsv, .Lfunc_end0-_Z22createArrayWithRandomsv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__addArraysPdS_S_i # -- Begin function _Z24__device_stub__addArraysPdS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__addArraysPdS_S_i,@function
_Z24__device_stub__addArraysPdS_S_i: # @_Z24__device_stub__addArraysPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addArraysPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__addArraysPdS_S_i, .Lfunc_end1-_Z24__device_stub__addArraysPdS_S_i
.cfi_endproc
# -- End function
.globl _Z10checkError10hipError_tPKc # -- Begin function _Z10checkError10hipError_tPKc
.p2align 4, 0x90
.type _Z10checkError10hipError_tPKc,@function
_Z10checkError10hipError_tPKc: # @_Z10checkError10hipError_tPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB2_2
# %bb.1:
retq
.LBB2_2:
pushq %rax
.cfi_def_cfa_offset 16
movl %edi, %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z10checkError10hipError_tPKc, .Lfunc_end2-_Z10checkError10hipError_tPKc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x4024000000000000 # double 10
.LCPI3_1:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $80, %edi
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
mulsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, (%rbx,%r14,8)
incq %r14
cmpq $10, %r14
jne .LBB3_1
# %bb.2: # %_Z22createArrayWithRandomsv.exit
movl $80, %edi
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
mulsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, (%r14,%r15,8)
incq %r15
cmpq $10, %r15
jne .LBB3_3
# %bb.4: # %_Z22createArrayWithRandomsv.exit33
movl $80, %edi
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB3_5
# %bb.7: # %_Z10checkError10hipError_tPKc.exit
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB3_8
# %bb.9: # %_Z10checkError10hipError_tPKc.exit35
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB3_10
# %bb.11: # %_Z10checkError10hipError_tPKc.exit37
movq 24(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $80, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9addArraysPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13: # %_Z10checkError10hipError_tPKc.exit45
movq 8(%rsp), %rsi
movl $80, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_14: # =>This Inner Loop Header: Depth=1
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r14,%r12,8), %xmm1 # xmm1 = mem[0],zero
movsd (%r15,%r12,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.8, %edi
movb $3, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB3_14
# %bb.15:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_5:
.cfi_def_cfa_offset 192
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB3_6
.LBB3_8:
movl $.L.str, %edi
movl $.L.str.2, %esi
jmp .LBB3_6
.LBB3_10:
movl $.L.str, %edi
movl $.L.str.3, %esi
.LBB3_6:
movl %eax, %edx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addArraysPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addArraysPdS_S_i,@object # @_Z9addArraysPdS_S_i
.section .rodata,"a",@progbits
.globl _Z9addArraysPdS_S_i
.p2align 3, 0x0
_Z9addArraysPdS_S_i:
.quad _Z24__device_stub__addArraysPdS_S_i
.size _Z9addArraysPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "there was an error at %s, error code: %d"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "allocating device memory for A"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "allocating device memory for B"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "allocating device memory for C"
.size .L.str.3, 31
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%.2f + %.2f = %.2f \n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addArraysPdS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addArraysPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addArraysPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addArraysPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addArraysPdS_S_i
.globl _Z9addArraysPdS_S_i
.p2align 8
.type _Z9addArraysPdS_S_i,@function
_Z9addArraysPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addArraysPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addArraysPdS_S_i, .Lfunc_end0-_Z9addArraysPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addArraysPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addArraysPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00000609_00000000-6_cudaMatrices.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22createArrayWithRandomsv
.type _Z22createArrayWithRandomsv, @function
_Z22createArrayWithRandomsv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $80, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, %rbx
leaq 80(%rax), %rbp
.L4:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L4
movq %r12, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z22createArrayWithRandomsv, .-_Z22createArrayWithRandomsv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "there was an error at %s, error code: %d"
.text
.globl _Z10checkError9cudaErrorPKc
.type _Z10checkError9cudaErrorPKc, @function
_Z10checkError9cudaErrorPKc:
.LFB2058:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L12
ret
.L12:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %ecx
movq %rsi, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10checkError9cudaErrorPKc, .-_Z10checkError9cudaErrorPKc
.globl _Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i
.type _Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i, @function
_Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addArraysPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i, .-_Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i
.globl _Z9addArraysPdS_S_i
.type _Z9addArraysPdS_S_i, @function
_Z9addArraysPdS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9addArraysPdS_S_i, .-_Z9addArraysPdS_S_i
.section .rodata.str1.8
.align 8
.LC3:
.string "allocating device memory for A"
.align 8
.LC4:
.string "allocating device memory for B"
.align 8
.LC5:
.string "allocating device memory for C"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "copy A from host to device"
.LC7:
.string "copy B from host to device"
.LC8:
.string "copy C from host to device"
.LC9:
.string "copy C from device to host"
.LC10:
.string "%.2f + %.2f = %.2f \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _Z22createArrayWithRandomsv
movq %rax, %r13
call _Z22createArrayWithRandomsv
movq %rax, %r12
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %edi
leaq .LC3(%rip), %rsi
call _Z10checkError9cudaErrorPKc
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %edi
leaq .LC4(%rip), %rsi
call _Z10checkError9cudaErrorPKc
leaq 24(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl %eax, %ebx
leaq .LC5(%rip), %rsi
movl %eax, %edi
call _Z10checkError9cudaErrorPKc
movl $1, %ecx
movl $80, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl %ebx, %edi
call _Z10checkError9cudaErrorPKc
movl $1, %ecx
movl $80, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
movl %ebx, %edi
call _Z10checkError9cudaErrorPKc
movl $1, %ecx
movl $80, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl %ebx, %edi
call _Z10checkError9cudaErrorPKc
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L22:
movl $2, %ecx
movl $80, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC9(%rip), %rsi
movl %ebx, %edi
call _Z10checkError9cudaErrorPKc
movl $0, %ebx
leaq .LC10(%rip), %r14
.L23:
movsd 0(%r13,%rbx), %xmm0
movsd 0(%rbp,%rbx), %xmm2
movsd (%r12,%rbx), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq $80, %rbx
jne .L23
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $10, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9addArraysPdS_S_iPdS_S_i
jmp .L22
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z9addArraysPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addArraysPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1076101120
.align 8
.LC1:
.long 0
.long 1040187392
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaMatrices.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z22createArrayWithRandomsv
.LCPI0_0:
.quad 0x4024000000000000 # double 10
.LCPI0_1:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.text
.globl _Z22createArrayWithRandomsv
.p2align 4, 0x90
.type _Z22createArrayWithRandomsv,@function
_Z22createArrayWithRandomsv: # @_Z22createArrayWithRandomsv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $80, %edi
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
mulsd .LCPI0_1(%rip), %xmm0
movsd %xmm0, (%rbx,%r14,8)
incq %r14
cmpq $10, %r14
jne .LBB0_1
# %bb.2:
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z22createArrayWithRandomsv, .Lfunc_end0-_Z22createArrayWithRandomsv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__addArraysPdS_S_i # -- Begin function _Z24__device_stub__addArraysPdS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__addArraysPdS_S_i,@function
_Z24__device_stub__addArraysPdS_S_i: # @_Z24__device_stub__addArraysPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addArraysPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__addArraysPdS_S_i, .Lfunc_end1-_Z24__device_stub__addArraysPdS_S_i
.cfi_endproc
# -- End function
.globl _Z10checkError10hipError_tPKc # -- Begin function _Z10checkError10hipError_tPKc
.p2align 4, 0x90
.type _Z10checkError10hipError_tPKc,@function
_Z10checkError10hipError_tPKc: # @_Z10checkError10hipError_tPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB2_2
# %bb.1:
retq
.LBB2_2:
pushq %rax
.cfi_def_cfa_offset 16
movl %edi, %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z10checkError10hipError_tPKc, .Lfunc_end2-_Z10checkError10hipError_tPKc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x4024000000000000 # double 10
.LCPI3_1:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $80, %edi
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
mulsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, (%rbx,%r14,8)
incq %r14
cmpq $10, %r14
jne .LBB3_1
# %bb.2: # %_Z22createArrayWithRandomsv.exit
movl $80, %edi
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
mulsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, (%r14,%r15,8)
incq %r15
cmpq $10, %r15
jne .LBB3_3
# %bb.4: # %_Z22createArrayWithRandomsv.exit33
movl $80, %edi
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB3_5
# %bb.7: # %_Z10checkError10hipError_tPKc.exit
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB3_8
# %bb.9: # %_Z10checkError10hipError_tPKc.exit35
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB3_10
# %bb.11: # %_Z10checkError10hipError_tPKc.exit37
movq 24(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $80, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9addArraysPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13: # %_Z10checkError10hipError_tPKc.exit45
movq 8(%rsp), %rsi
movl $80, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_14: # =>This Inner Loop Header: Depth=1
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r14,%r12,8), %xmm1 # xmm1 = mem[0],zero
movsd (%r15,%r12,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.8, %edi
movb $3, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB3_14
# %bb.15:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_5:
.cfi_def_cfa_offset 192
movl $.L.str, %edi
movl $.L.str.1, %esi
jmp .LBB3_6
.LBB3_8:
movl $.L.str, %edi
movl $.L.str.2, %esi
jmp .LBB3_6
.LBB3_10:
movl $.L.str, %edi
movl $.L.str.3, %esi
.LBB3_6:
movl %eax, %edx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addArraysPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addArraysPdS_S_i,@object # @_Z9addArraysPdS_S_i
.section .rodata,"a",@progbits
.globl _Z9addArraysPdS_S_i
.p2align 3, 0x0
_Z9addArraysPdS_S_i:
.quad _Z24__device_stub__addArraysPdS_S_i
.size _Z9addArraysPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "there was an error at %s, error code: %d"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "allocating device memory for A"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "allocating device memory for B"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "allocating device memory for C"
.size .L.str.3, 31
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%.2f + %.2f = %.2f \n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addArraysPdS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addArraysPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addArraysPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float* var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32,float var_33) {
if (comp > (var_3 - sinf(var_4 + +1.1880E20f + -1.5717E22f))) {
for (int i=0; i < var_1; ++i) {
if (comp > atanf((var_5 * var_6))) {
comp += var_7 + (var_8 - var_9);
comp += (-1.4369E-7f / (+1.5416E-35f / (var_10 / (+1.5498E-43f / var_11))));
comp = asinf(-1.3356E-41f / +1.1703E-36f);
comp += (+0.0f + var_12 - var_13 + (var_14 + fabsf(acosf((var_15 + (-0.0f * log10f((-1.6169E3f + atanf(-1.5079E36f)))))))));
if (comp <= var_16 + -1.4471E36f / (var_17 / var_18 + (var_19 / var_20))) {
comp = (var_21 + var_22 - log10f((+1.5675E35f - (-1.9158E34f + ldexpf(-0.0f, 2)))));
float tmp_1 = var_23 * +1.3799E36f * +1.7034E-35f;
comp = tmp_1 + -0.0f - var_24 / var_25 + +1.6619E10f;
}
for (int i=0; i < var_2; ++i) {
comp = (-1.2967E9f / -1.0508E18f * +1.5166E-36f * -1.2234E-26f / var_27);
var_26[i] = +1.6957E35f / var_28 + (var_29 + var_30);
comp = var_26[i] / (var_31 * -1.3135E-36f / (+0.0f + (-0.0f + (var_32 / var_33))));
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float* tmp_27 = initPointer( atof(argv[27]) );
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
float tmp_34 = atof(argv[34]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33,tmp_34);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000727ba_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff
.type _Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff, @function
_Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $408, %rsp
.cfi_def_cfa_offset 416
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 392(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 416(%rsp), %rax
movq %rax, 192(%rsp)
leaq 424(%rsp), %rax
movq %rax, 200(%rsp)
leaq 432(%rsp), %rax
movq %rax, 208(%rsp)
leaq 440(%rsp), %rax
movq %rax, 216(%rsp)
leaq 448(%rsp), %rax
movq %rax, 224(%rsp)
leaq 456(%rsp), %rax
movq %rax, 232(%rsp)
leaq 464(%rsp), %rax
movq %rax, 240(%rsp)
leaq 472(%rsp), %rax
movq %rax, 248(%rsp)
leaq 480(%rsp), %rax
movq %rax, 256(%rsp)
leaq 488(%rsp), %rax
movq %rax, 264(%rsp)
leaq 496(%rsp), %rax
movq %rax, 272(%rsp)
leaq 504(%rsp), %rax
movq %rax, 280(%rsp)
leaq 512(%rsp), %rax
movq %rax, 288(%rsp)
leaq 520(%rsp), %rax
movq %rax, 296(%rsp)
leaq 528(%rsp), %rax
movq %rax, 304(%rsp)
leaq 536(%rsp), %rax
movq %rax, 312(%rsp)
movq %rsp, %rax
movq %rax, 320(%rsp)
leaq 544(%rsp), %rax
movq %rax, 328(%rsp)
leaq 552(%rsp), %rax
movq %rax, 336(%rsp)
leaq 560(%rsp), %rax
movq %rax, 344(%rsp)
leaq 568(%rsp), %rax
movq %rax, 352(%rsp)
leaq 576(%rsp), %rax
movq %rax, 360(%rsp)
leaq 584(%rsp), %rax
movq %rax, 368(%rsp)
leaq 592(%rsp), %rax
movq %rax, 376(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 392(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 424
pushq 56(%rsp)
.cfi_def_cfa_offset 432
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefiifffffffffffffffffffffffPffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 416
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff, .-_Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff
.globl _Z7computefiifffffffffffffffffffffffPffffffff
.type _Z7computefiifffffffffffffffffffffffPffffffff, @function
_Z7computefiifffffffffffffffffffffffPffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movss 384(%rsp), %xmm8
movss %xmm8, 176(%rsp)
movss 376(%rsp), %xmm8
movss %xmm8, 168(%rsp)
movss 368(%rsp), %xmm8
movss %xmm8, 160(%rsp)
movss 360(%rsp), %xmm8
movss %xmm8, 152(%rsp)
movss 352(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 344(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 336(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 328(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 320(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff
addq $200, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiifffffffffffffffffffffffPffffffff, .-_Z7computefiifffffffffffffffffffffffPffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $296, %rsp
.cfi_def_cfa_offset 336
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 248(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 240(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 232(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 224(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 216(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 208(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r13
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 240(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 248(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 256(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 264(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 272(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 276(%rsp)
movl $1, 280(%rsp)
movl $1, 264(%rsp)
movl $1, 268(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 276(%rsp), %rdx
movl $1, %ecx
movq 264(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 248(%rsp), %xmm0
subq $192, %rsp
.cfi_def_cfa_offset 528
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 176(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 168(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 160(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 152(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 144(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 288(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 296(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 312(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 320(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 328(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 336(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 344(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 352(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 360(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 368(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 376(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r13, %rdx
pxor %xmm7, %xmm7
cvtsd2ss 384(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 392(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 400(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 408(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 416(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 424(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 432(%rsp), %xmm1
movl %r12d, %esi
movl %ebp, %edi
call _Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff
addq $192, %rsp
.cfi_def_cfa_offset 336
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiifffffffffffffffffffffffPffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiifffffffffffffffffffffffPffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float* var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32,float var_33) {
if (comp > (var_3 - sinf(var_4 + +1.1880E20f + -1.5717E22f))) {
for (int i=0; i < var_1; ++i) {
if (comp > atanf((var_5 * var_6))) {
comp += var_7 + (var_8 - var_9);
comp += (-1.4369E-7f / (+1.5416E-35f / (var_10 / (+1.5498E-43f / var_11))));
comp = asinf(-1.3356E-41f / +1.1703E-36f);
comp += (+0.0f + var_12 - var_13 + (var_14 + fabsf(acosf((var_15 + (-0.0f * log10f((-1.6169E3f + atanf(-1.5079E36f)))))))));
if (comp <= var_16 + -1.4471E36f / (var_17 / var_18 + (var_19 / var_20))) {
comp = (var_21 + var_22 - log10f((+1.5675E35f - (-1.9158E34f + ldexpf(-0.0f, 2)))));
float tmp_1 = var_23 * +1.3799E36f * +1.7034E-35f;
comp = tmp_1 + -0.0f - var_24 / var_25 + +1.6619E10f;
}
for (int i=0; i < var_2; ++i) {
comp = (-1.2967E9f / -1.0508E18f * +1.5166E-36f * -1.2234E-26f / var_27);
var_26[i] = +1.6957E35f / var_28 + (var_29 + var_30);
comp = var_26[i] / (var_31 * -1.3135E-36f / (+0.0f + (-0.0f + (var_32 / var_33))));
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float* tmp_27 = initPointer( atof(argv[27]) );
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
float tmp_34 = atof(argv[34]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33,tmp_34);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float* var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32,float var_33) {
if (comp > (var_3 - sinf(var_4 + +1.1880E20f + -1.5717E22f))) {
for (int i=0; i < var_1; ++i) {
if (comp > atanf((var_5 * var_6))) {
comp += var_7 + (var_8 - var_9);
comp += (-1.4369E-7f / (+1.5416E-35f / (var_10 / (+1.5498E-43f / var_11))));
comp = asinf(-1.3356E-41f / +1.1703E-36f);
comp += (+0.0f + var_12 - var_13 + (var_14 + fabsf(acosf((var_15 + (-0.0f * log10f((-1.6169E3f + atanf(-1.5079E36f)))))))));
if (comp <= var_16 + -1.4471E36f / (var_17 / var_18 + (var_19 / var_20))) {
comp = (var_21 + var_22 - log10f((+1.5675E35f - (-1.9158E34f + ldexpf(-0.0f, 2)))));
float tmp_1 = var_23 * +1.3799E36f * +1.7034E-35f;
comp = tmp_1 + -0.0f - var_24 / var_25 + +1.6619E10f;
}
for (int i=0; i < var_2; ++i) {
comp = (-1.2967E9f / -1.0508E18f * +1.5166E-36f * -1.2234E-26f / var_27);
var_26[i] = +1.6957E35f / var_28 + (var_29 + var_30);
comp = var_26[i] / (var_31 * -1.3135E-36f / (+0.0f + (-0.0f + (var_32 / var_33))));
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float* tmp_27 = initPointer( atof(argv[27]) );
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
float tmp_34 = atof(argv[34]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33,tmp_34);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float* var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32,float var_33) {
if (comp > (var_3 - sinf(var_4 + +1.1880E20f + -1.5717E22f))) {
for (int i=0; i < var_1; ++i) {
if (comp > atanf((var_5 * var_6))) {
comp += var_7 + (var_8 - var_9);
comp += (-1.4369E-7f / (+1.5416E-35f / (var_10 / (+1.5498E-43f / var_11))));
comp = asinf(-1.3356E-41f / +1.1703E-36f);
comp += (+0.0f + var_12 - var_13 + (var_14 + fabsf(acosf((var_15 + (-0.0f * log10f((-1.6169E3f + atanf(-1.5079E36f)))))))));
if (comp <= var_16 + -1.4471E36f / (var_17 / var_18 + (var_19 / var_20))) {
comp = (var_21 + var_22 - log10f((+1.5675E35f - (-1.9158E34f + ldexpf(-0.0f, 2)))));
float tmp_1 = var_23 * +1.3799E36f * +1.7034E-35f;
comp = tmp_1 + -0.0f - var_24 / var_25 + +1.6619E10f;
}
for (int i=0; i < var_2; ++i) {
comp = (-1.2967E9f / -1.0508E18f * +1.5166E-36f * -1.2234E-26f / var_27);
var_26[i] = +1.6957E35f / var_28 + (var_29 + var_30);
comp = var_26[i] / (var_31 * -1.3135E-36f / (+0.0f + (-0.0f + (var_32 / var_33))));
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float* tmp_27 = initPointer( atof(argv[27]) );
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
float tmp_34 = atof(argv[34]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33,tmp_34);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff # -- Begin function _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff,@function
_Z22__device_stub__computefiifffffffffffffffffffffffPffffffff: # @_Z22__device_stub__computefiifffffffffffffffffffffffPffffffff
.cfi_startproc
# %bb.0:
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 384
movss %xmm0, 36(%rsp)
movl %edi, 32(%rsp)
movl %esi, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
leaq 384(%rsp), %rax
movq %rax, 176(%rsp)
leaq 392(%rsp), %rax
movq %rax, 184(%rsp)
leaq 400(%rsp), %rax
movq %rax, 192(%rsp)
leaq 408(%rsp), %rax
movq %rax, 200(%rsp)
leaq 416(%rsp), %rax
movq %rax, 208(%rsp)
leaq 424(%rsp), %rax
movq %rax, 216(%rsp)
leaq 432(%rsp), %rax
movq %rax, 224(%rsp)
leaq 440(%rsp), %rax
movq %rax, 232(%rsp)
leaq 448(%rsp), %rax
movq %rax, 240(%rsp)
leaq 456(%rsp), %rax
movq %rax, 248(%rsp)
leaq 464(%rsp), %rax
movq %rax, 256(%rsp)
leaq 472(%rsp), %rax
movq %rax, 264(%rsp)
leaq 480(%rsp), %rax
movq %rax, 272(%rsp)
leaq 488(%rsp), %rax
movq %rax, 280(%rsp)
leaq 496(%rsp), %rax
movq %rax, 288(%rsp)
leaq 504(%rsp), %rax
movq %rax, 296(%rsp)
leaq 88(%rsp), %rax
movq %rax, 304(%rsp)
leaq 512(%rsp), %rax
movq %rax, 312(%rsp)
leaq 520(%rsp), %rax
movq %rax, 320(%rsp)
leaq 528(%rsp), %rax
movq %rax, 328(%rsp)
leaq 536(%rsp), %rax
movq %rax, 336(%rsp)
leaq 544(%rsp), %rax
movq %rax, 344(%rsp)
leaq 552(%rsp), %rax
movq %rax, 352(%rsp)
leaq 560(%rsp), %rax
movq %rax, 360(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefiifffffffffffffffffffffffPffffffff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $392, %rsp # imm = 0x188
.cfi_adjust_cfa_offset -392
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff, .Lfunc_end0-_Z22__device_stub__computefiifffffffffffffffffffffffPffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $432, %rsp # imm = 0x1B0
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq strtod
movsd %xmm0, 424(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 416(%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 408(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 400(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 120(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 128(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 144(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 152(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 160(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 168(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 392(%rsp) # 8-byte Spill
movq 176(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 384(%rsp) # 8-byte Spill
movq 184(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 376(%rsp) # 8-byte Spill
movq 192(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 368(%rsp) # 8-byte Spill
movq 200(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 360(%rsp) # 8-byte Spill
movq 208(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 216(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 184(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $10, %r13
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 224(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 232(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 240(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 248(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 256(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movq 264(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 272(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 360(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 368(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 376(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 384(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 392(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 232(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 240(%rsp) # 4-byte Spill
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 248(%rsp) # 4-byte Spill
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 256(%rsp) # 4-byte Spill
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 264(%rsp) # 4-byte Spill
movsd 400(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 272(%rsp) # 4-byte Spill
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 280(%rsp) # 4-byte Spill
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 288(%rsp) # 4-byte Spill
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 296(%rsp) # 4-byte Spill
movsd 408(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 416(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 424(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 176(%rsp)
movss %xmm9, 168(%rsp)
movss %xmm10, 160(%rsp)
movss %xmm11, 152(%rsp)
movss %xmm12, 144(%rsp)
movss %xmm13, 136(%rsp)
movss %xmm14, 128(%rsp)
movss %xmm15, 120(%rsp)
movss %xmm3, 112(%rsp)
movss %xmm4, 104(%rsp)
movss %xmm5, 96(%rsp)
movss %xmm6, 88(%rsp)
movss %xmm7, 80(%rsp)
movss 192(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 72(%rsp)
movss 200(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 64(%rsp)
movss 208(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 56(%rsp)
movss 216(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 48(%rsp)
movss 224(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 40(%rsp)
movss 232(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 32(%rsp)
movss 240(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 24(%rsp)
movss 248(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 16(%rsp)
movss 256(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 8(%rsp)
movss 264(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, (%rsp)
movl %ebx, %edi
movl %r14d, %esi
movss 296(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 288(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 280(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 272(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 184(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
movq %r12, %rdx
callq _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $432, %rsp # imm = 0x1B0
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiifffffffffffffffffffffffPffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiifffffffffffffffffffffffPffffffff,@object # @_Z7computefiifffffffffffffffffffffffPffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiifffffffffffffffffffffffPffffffff
.p2align 3, 0x0
_Z7computefiifffffffffffffffffffffffPffffffff:
.quad _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff
.size _Z7computefiifffffffffffffffffffffffPffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiifffffffffffffffffffffffPffffffff"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiifffffffffffffffffffffffPffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000727ba_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff
.type _Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff, @function
_Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $408, %rsp
.cfi_def_cfa_offset 416
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 392(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 416(%rsp), %rax
movq %rax, 192(%rsp)
leaq 424(%rsp), %rax
movq %rax, 200(%rsp)
leaq 432(%rsp), %rax
movq %rax, 208(%rsp)
leaq 440(%rsp), %rax
movq %rax, 216(%rsp)
leaq 448(%rsp), %rax
movq %rax, 224(%rsp)
leaq 456(%rsp), %rax
movq %rax, 232(%rsp)
leaq 464(%rsp), %rax
movq %rax, 240(%rsp)
leaq 472(%rsp), %rax
movq %rax, 248(%rsp)
leaq 480(%rsp), %rax
movq %rax, 256(%rsp)
leaq 488(%rsp), %rax
movq %rax, 264(%rsp)
leaq 496(%rsp), %rax
movq %rax, 272(%rsp)
leaq 504(%rsp), %rax
movq %rax, 280(%rsp)
leaq 512(%rsp), %rax
movq %rax, 288(%rsp)
leaq 520(%rsp), %rax
movq %rax, 296(%rsp)
leaq 528(%rsp), %rax
movq %rax, 304(%rsp)
leaq 536(%rsp), %rax
movq %rax, 312(%rsp)
movq %rsp, %rax
movq %rax, 320(%rsp)
leaq 544(%rsp), %rax
movq %rax, 328(%rsp)
leaq 552(%rsp), %rax
movq %rax, 336(%rsp)
leaq 560(%rsp), %rax
movq %rax, 344(%rsp)
leaq 568(%rsp), %rax
movq %rax, 352(%rsp)
leaq 576(%rsp), %rax
movq %rax, 360(%rsp)
leaq 584(%rsp), %rax
movq %rax, 368(%rsp)
leaq 592(%rsp), %rax
movq %rax, 376(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 392(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 424
pushq 56(%rsp)
.cfi_def_cfa_offset 432
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefiifffffffffffffffffffffffPffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 416
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff, .-_Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff
.globl _Z7computefiifffffffffffffffffffffffPffffffff
.type _Z7computefiifffffffffffffffffffffffPffffffff, @function
_Z7computefiifffffffffffffffffffffffPffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movss 384(%rsp), %xmm8
movss %xmm8, 176(%rsp)
movss 376(%rsp), %xmm8
movss %xmm8, 168(%rsp)
movss 368(%rsp), %xmm8
movss %xmm8, 160(%rsp)
movss 360(%rsp), %xmm8
movss %xmm8, 152(%rsp)
movss 352(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 344(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 336(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 328(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 320(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff
addq $200, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiifffffffffffffffffffffffPffffffff, .-_Z7computefiifffffffffffffffffffffffPffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $296, %rsp
.cfi_def_cfa_offset 336
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 248(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 240(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 232(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 224(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 216(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 208(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r13
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 240(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 248(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 256(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 264(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 272(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 276(%rsp)
movl $1, 280(%rsp)
movl $1, 264(%rsp)
movl $1, 268(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 276(%rsp), %rdx
movl $1, %ecx
movq 264(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 248(%rsp), %xmm0
subq $192, %rsp
.cfi_def_cfa_offset 528
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 176(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 168(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 160(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 152(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 144(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 288(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 296(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 312(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 320(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 328(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 336(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 344(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 352(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 360(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 368(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 376(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r13, %rdx
pxor %xmm7, %xmm7
cvtsd2ss 384(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 392(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 400(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 408(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 416(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 424(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 432(%rsp), %xmm1
movl %r12d, %esi
movl %ebp, %edi
call _Z59__device_stub__Z7computefiifffffffffffffffffffffffPfffffffffiifffffffffffffffffffffffPffffffff
addq $192, %rsp
.cfi_def_cfa_offset 336
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiifffffffffffffffffffffffPffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiifffffffffffffffffffffffPffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff # -- Begin function _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff,@function
_Z22__device_stub__computefiifffffffffffffffffffffffPffffffff: # @_Z22__device_stub__computefiifffffffffffffffffffffffPffffffff
.cfi_startproc
# %bb.0:
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 384
movss %xmm0, 36(%rsp)
movl %edi, 32(%rsp)
movl %esi, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
leaq 384(%rsp), %rax
movq %rax, 176(%rsp)
leaq 392(%rsp), %rax
movq %rax, 184(%rsp)
leaq 400(%rsp), %rax
movq %rax, 192(%rsp)
leaq 408(%rsp), %rax
movq %rax, 200(%rsp)
leaq 416(%rsp), %rax
movq %rax, 208(%rsp)
leaq 424(%rsp), %rax
movq %rax, 216(%rsp)
leaq 432(%rsp), %rax
movq %rax, 224(%rsp)
leaq 440(%rsp), %rax
movq %rax, 232(%rsp)
leaq 448(%rsp), %rax
movq %rax, 240(%rsp)
leaq 456(%rsp), %rax
movq %rax, 248(%rsp)
leaq 464(%rsp), %rax
movq %rax, 256(%rsp)
leaq 472(%rsp), %rax
movq %rax, 264(%rsp)
leaq 480(%rsp), %rax
movq %rax, 272(%rsp)
leaq 488(%rsp), %rax
movq %rax, 280(%rsp)
leaq 496(%rsp), %rax
movq %rax, 288(%rsp)
leaq 504(%rsp), %rax
movq %rax, 296(%rsp)
leaq 88(%rsp), %rax
movq %rax, 304(%rsp)
leaq 512(%rsp), %rax
movq %rax, 312(%rsp)
leaq 520(%rsp), %rax
movq %rax, 320(%rsp)
leaq 528(%rsp), %rax
movq %rax, 328(%rsp)
leaq 536(%rsp), %rax
movq %rax, 336(%rsp)
leaq 544(%rsp), %rax
movq %rax, 344(%rsp)
leaq 552(%rsp), %rax
movq %rax, 352(%rsp)
leaq 560(%rsp), %rax
movq %rax, 360(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefiifffffffffffffffffffffffPffffffff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $392, %rsp # imm = 0x188
.cfi_adjust_cfa_offset -392
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff, .Lfunc_end0-_Z22__device_stub__computefiifffffffffffffffffffffffPffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $432, %rsp # imm = 0x1B0
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq strtod
movsd %xmm0, 424(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 416(%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 408(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 400(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 120(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 128(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 144(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 152(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 160(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 168(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 392(%rsp) # 8-byte Spill
movq 176(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 384(%rsp) # 8-byte Spill
movq 184(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 376(%rsp) # 8-byte Spill
movq 192(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 368(%rsp) # 8-byte Spill
movq 200(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 360(%rsp) # 8-byte Spill
movq 208(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 216(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 184(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $10, %r13
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 224(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 232(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 240(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 248(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 256(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movq 264(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 272(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 360(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 368(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 376(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 384(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 392(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 232(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 240(%rsp) # 4-byte Spill
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 248(%rsp) # 4-byte Spill
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 256(%rsp) # 4-byte Spill
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 264(%rsp) # 4-byte Spill
movsd 400(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 272(%rsp) # 4-byte Spill
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 280(%rsp) # 4-byte Spill
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 288(%rsp) # 4-byte Spill
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 296(%rsp) # 4-byte Spill
movsd 408(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 416(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 424(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 176(%rsp)
movss %xmm9, 168(%rsp)
movss %xmm10, 160(%rsp)
movss %xmm11, 152(%rsp)
movss %xmm12, 144(%rsp)
movss %xmm13, 136(%rsp)
movss %xmm14, 128(%rsp)
movss %xmm15, 120(%rsp)
movss %xmm3, 112(%rsp)
movss %xmm4, 104(%rsp)
movss %xmm5, 96(%rsp)
movss %xmm6, 88(%rsp)
movss %xmm7, 80(%rsp)
movss 192(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 72(%rsp)
movss 200(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 64(%rsp)
movss 208(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 56(%rsp)
movss 216(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 48(%rsp)
movss 224(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 40(%rsp)
movss 232(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 32(%rsp)
movss 240(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 24(%rsp)
movss 248(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 16(%rsp)
movss 256(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 8(%rsp)
movss 264(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, (%rsp)
movl %ebx, %edi
movl %r14d, %esi
movss 296(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 288(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 280(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 272(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 184(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
movq %r12, %rdx
callq _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $432, %rsp # imm = 0x1B0
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiifffffffffffffffffffffffPffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiifffffffffffffffffffffffPffffffff,@object # @_Z7computefiifffffffffffffffffffffffPffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiifffffffffffffffffffffffPffffffff
.p2align 3, 0x0
_Z7computefiifffffffffffffffffffffffPffffffff:
.quad _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff
.size _Z7computefiifffffffffffffffffffffffPffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiifffffffffffffffffffffffPffffffff"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiifffffffffffffffffffffffPffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiifffffffffffffffffffffffPffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void vsort1(int *input0,int *result0){
unsigned int tid = threadIdx.x;
unsigned int bid = blockIdx.x;
extern __shared__ __attribute__ ((aligned (16))) unsigned char sbase[];
(( int *)sbase)[tid] = ((tid&256)==0) ? min(input0[((bid*512)+tid)],input0[((bid*512)+(tid^256))]) : max(input0[((bid*512)+tid)],input0[((bid*512)+(tid^256))]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^384)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^384)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^128)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^128)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^448)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^448)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^192)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^192)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^480)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^480)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^224)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^224)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^96)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^96)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^496)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^496)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^240)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^240)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^112)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^112)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^48)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^48)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^504)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^504)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^248)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^248)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^120)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^120)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^56)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^56)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^24)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^24)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^508)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^508)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^252)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^252)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^124)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^124)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^60)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^60)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^28)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^28)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^12)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^12)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^510)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^510)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^254)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^254)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^126)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^126)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^62)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^62)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^30)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^30)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^14)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^14)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^6)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^6)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^255)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^255)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^127)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^127)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^15)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^15)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^7)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^7)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
__syncthreads();
result0[((bid*512)+tid)] = (( int *)sbase)[tid];
} | .file "tmpxft_000e9e27_00000000-6_vsort1Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6vsort1PiS_PiS_
.type _Z27__device_stub__Z6vsort1PiS_PiS_, @function
_Z27__device_stub__Z6vsort1PiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6vsort1PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z6vsort1PiS_PiS_, .-_Z27__device_stub__Z6vsort1PiS_PiS_
.globl _Z6vsort1PiS_
.type _Z6vsort1PiS_, @function
_Z6vsort1PiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6vsort1PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vsort1PiS_, .-_Z6vsort1PiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vsort1PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vsort1PiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void vsort1(int *input0,int *result0){
unsigned int tid = threadIdx.x;
unsigned int bid = blockIdx.x;
extern __shared__ __attribute__ ((aligned (16))) unsigned char sbase[];
(( int *)sbase)[tid] = ((tid&256)==0) ? min(input0[((bid*512)+tid)],input0[((bid*512)+(tid^256))]) : max(input0[((bid*512)+tid)],input0[((bid*512)+(tid^256))]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^384)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^384)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^128)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^128)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^448)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^448)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^192)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^192)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^480)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^480)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^224)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^224)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^96)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^96)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^496)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^496)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^240)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^240)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^112)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^112)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^48)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^48)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^504)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^504)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^248)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^248)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^120)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^120)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^56)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^56)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^24)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^24)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^508)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^508)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^252)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^252)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^124)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^124)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^60)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^60)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^28)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^28)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^12)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^12)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^510)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^510)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^254)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^254)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^126)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^126)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^62)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^62)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^30)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^30)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^14)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^14)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^6)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^6)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^255)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^255)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^127)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^127)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^15)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^15)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^7)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^7)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
__syncthreads();
result0[((bid*512)+tid)] = (( int *)sbase)[tid];
} | #include <hip/hip_runtime.h>
__global__ void vsort1(int *input0,int *result0){
unsigned int tid = threadIdx.x;
unsigned int bid = blockIdx.x;
extern __shared__ __attribute__ ((aligned (16))) unsigned char sbase[];
(( int *)sbase)[tid] = ((tid&256)==0) ? min(input0[((bid*512)+tid)],input0[((bid*512)+(tid^256))]) : max(input0[((bid*512)+tid)],input0[((bid*512)+(tid^256))]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^384)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^384)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^128)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^128)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^448)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^448)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^192)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^192)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^480)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^480)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^224)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^224)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^96)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^96)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^496)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^496)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^240)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^240)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^112)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^112)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^48)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^48)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^504)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^504)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^248)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^248)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^120)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^120)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^56)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^56)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^24)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^24)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^508)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^508)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^252)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^252)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^124)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^124)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^60)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^60)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^28)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^28)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^12)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^12)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^510)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^510)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^254)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^254)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^126)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^126)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^62)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^62)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^30)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^30)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^14)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^14)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^6)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^6)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^255)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^255)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^127)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^127)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^15)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^15)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^7)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^7)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
__syncthreads();
result0[((bid*512)+tid)] = (( int *)sbase)[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void vsort1(int *input0,int *result0){
unsigned int tid = threadIdx.x;
unsigned int bid = blockIdx.x;
extern __shared__ __attribute__ ((aligned (16))) unsigned char sbase[];
(( int *)sbase)[tid] = ((tid&256)==0) ? min(input0[((bid*512)+tid)],input0[((bid*512)+(tid^256))]) : max(input0[((bid*512)+tid)],input0[((bid*512)+(tid^256))]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^384)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^384)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^128)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^128)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^448)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^448)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^192)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^192)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^480)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^480)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^224)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^224)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^96)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^96)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^496)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^496)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^240)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^240)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^112)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^112)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^48)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^48)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^504)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^504)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^248)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^248)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^120)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^120)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^56)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^56)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^24)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^24)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^508)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^508)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^252)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^252)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^124)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^124)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^60)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^60)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^28)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^28)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^12)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^12)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^510)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^510)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^254)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^254)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^126)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^126)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^62)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^62)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^30)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^30)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^14)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^14)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^6)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^6)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^255)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^255)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^127)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^127)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^15)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^15)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^7)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^7)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
__syncthreads();
result0[((bid*512)+tid)] = (( int *)sbase)[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vsort1PiS_
.globl _Z6vsort1PiS_
.p2align 8
.type _Z6vsort1PiS_,@function
_Z6vsort1PiS_:
s_load_b64 s[4:5], s[0:1], 0x0
s_lshl_b32 s3, s15, 9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s3, v0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_and_b32_e32 v1, 0x100, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
global_load_b32 v3, v[3:4], off
v_and_b32_e32 v4, 0x100, v0
v_cmp_ne_u32_e64 s2, 0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s2
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_2
v_and_b32_e32 v1, 0x2ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s3, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s2, s4, v1
v_add_co_ci_u32_e64 v2, s2, s5, v2, s2
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_max_i32_e32 v4, v3, v1
.LBB0_2:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_4
v_add3_u32 v1, s3, v0, 0x100
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, s2, s4, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s2, s5, v2, s2
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v4, v3, v1
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
v_xor_b32_e32 v2, 0x180, v0
v_lshl_add_u32 v1, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v2, v2, 2, 0
ds_store_b32 v1, v4
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v4, v3, v2
v_max_i32_e32 v2, v3, v2
v_and_b32_e32 v3, 0x80, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_cmp_ne_u32_e64 s3, 0, v3
ds_store_b32 v1, v2 offset:2048
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v1 offset:2048
v_and_b32_e32 v2, 0x80, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e64 s2, 0, v2
s_and_saveexec_b32 s4, s3
s_xor_b32 s3, exec_lo, s4
s_cbranch_execz .LBB0_6
v_and_b32_e32 v2, 0x37f, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2 offset:2048
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v3, v4, v2
.LBB0_6:
s_or_saveexec_b32 s3, s3
v_add_nc_u32_e32 v2, 0x800, v1
s_xor_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_8
v_lshl_add_u32 v3, v0, 2, 0
ds_load_b32 v3, v3 offset:2560
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v3, v4, v3
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
v_xor_b32_e32 v4, 0x1c0, v0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_lshl_add_u32 v3, v4, 2, 0
ds_load_b32 v4, v1
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v4, v3
v_max_i32_e32 v3, v4, v3
v_xor_b32_e32 v4, 0xc0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4 offset:2048
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s2
v_and_b32_e32 v5, 64, v0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v1
v_and_b32_e32 v3, 64, v0
v_cmp_ne_u32_e64 s4, 0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s3, 0, v3
s_and_saveexec_b32 s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s5
s_cbranch_execz .LBB0_10
v_and_b32_e32 v3, 0x3bf, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v3, v3, 2, 0
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v3, v4, v3
.LBB0_10:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_12
v_lshl_add_u32 v3, v0, 2, 0
ds_load_b32 v3, v3 offset:256
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v3, v4, v3
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
v_xor_b32_e32 v4, 0x1e0, v0
s_add_i32 s4, 0, 0x800
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
v_lshl_add_u32 v3, v4, 2, s4
buffer_gl0_inv
ds_load_b32 v4, v2
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v4, v3
v_max_i32_e32 v3, v4, v3
v_xor_b32_e32 v4, 0xe0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 0x60, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s2
v_lshl_add_u32 v4, v4, 2, s4
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s3
v_and_b32_e32 v5, 32, v0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v1
v_and_b32_e32 v3, 32, v0
v_cmp_ne_u32_e64 s5, 0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s4, 0, v3
s_and_saveexec_b32 s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s5, exec_lo, s6
s_cbranch_execz .LBB0_14
v_and_b32_e32 v3, 0x3df, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v3, v3, 2, 0
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v3, v4, v3
.LBB0_14:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_16
v_lshl_add_u32 v3, v0, 2, 0
ds_load_b32 v3, v3 offset:128
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v3, v4, v3
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
v_xor_b32_e32 v4, 0x1f0, v0
s_add_i32 s5, 0, 0x800
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
v_lshl_add_u32 v3, v4, 2, s5
buffer_gl0_inv
ds_load_b32 v4, v2
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v4, v3
v_max_i32_e32 v3, v4, v3
v_xor_b32_e32 v4, 0xf0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 0x70, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s2
v_lshl_add_u32 v4, v4, 2, s5
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 48, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s3
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s4
v_and_b32_e32 v5, 16, v0
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v2
v_and_b32_e32 v3, 16, v0
v_cmp_ne_u32_e64 s6, 0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s5, 0, v3
s_and_saveexec_b32 s7, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s7
s_cbranch_execz .LBB0_18
v_and_b32_e32 v3, 0x3ef, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v3, v3, 2, 0
ds_load_b32 v3, v3 offset:2048
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v3, v4, v3
.LBB0_18:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_20
v_lshl_add_u32 v3, v0, 2, 0
ds_load_b32 v3, v3 offset:2112
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v3, v4, v3
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt lgkmcnt(0)
v_xor_b32_e32 v4, 0x1f8, v0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_lshl_add_u32 v3, v4, 2, 0
s_add_i32 s6, 0, 0x800
ds_load_b32 v4, v1
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v4, v3
v_max_i32_e32 v3, v4, v3
v_xor_b32_e32 v4, 0xf8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_lshl_add_u32 v4, v4, 2, s6
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 0x78, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s2
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 56, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s3
v_lshl_add_u32 v4, v4, 2, s6
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 24, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s4
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s5
v_and_b32_e32 v5, 8, v0
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v2
v_and_b32_e32 v3, 8, v0
v_cmp_ne_u32_e64 s7, 0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s6, 0, v3
s_and_saveexec_b32 s8, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s7, exec_lo, s8
s_cbranch_execz .LBB0_22
v_and_b32_e32 v3, 0x3f7, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v3, v3, 2, 0
ds_load_b32 v3, v3 offset:2048
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v3, v4, v3
.LBB0_22:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_24
v_lshl_add_u32 v3, v0, 2, 0
ds_load_b32 v3, v3 offset:2080
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v3, v4, v3
.LBB0_24:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
v_xor_b32_e32 v4, 0x1fc, v0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_lshl_add_u32 v3, v4, 2, 0
s_add_i32 s7, 0, 0x800
ds_load_b32 v4, v1
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v4, v3
v_max_i32_e32 v3, v4, v3
v_xor_b32_e32 v4, 0xfc, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_lshl_add_u32 v4, v4, 2, s7
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 0x7c, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s2
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 60, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s3
v_lshl_add_u32 v4, v4, 2, s7
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 28, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s4
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 12, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s5
v_lshl_add_u32 v4, v4, 2, s7
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s6
v_and_b32_e32 v5, 4, v0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v1
v_and_b32_e32 v3, 4, v0
v_cmp_ne_u32_e64 s8, 0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s7, 0, v3
s_and_saveexec_b32 s9, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s9
s_cbranch_execz .LBB0_26
v_and_b32_e32 v3, 0x3fb, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v3, v3, 2, 0
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v3, v4, v3
.LBB0_26:
s_and_not1_saveexec_b32 s8, s8
s_cbranch_execz .LBB0_28
v_lshl_add_u32 v3, v0, 2, 0
ds_load_b32 v3, v3 offset:16
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v3, v4, v3
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt lgkmcnt(0)
v_xor_b32_e32 v4, 0x1fe, v0
s_add_i32 s8, 0, 0x800
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
v_lshl_add_u32 v3, v4, 2, s8
buffer_gl0_inv
ds_load_b32 v4, v2
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v4, v3
v_max_i32_e32 v3, v4, v3
v_xor_b32_e32 v4, 0xfe, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 0x7e, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s2
v_lshl_add_u32 v4, v4, 2, s8
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 62, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s3
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 30, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s4
v_lshl_add_u32 v4, v4, 2, s8
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 14, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s5
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s6
v_lshl_add_u32 v4, v4, 2, s8
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s7
v_and_b32_e32 v5, 2, v0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v1
v_and_b32_e32 v3, 2, v0
v_cmp_ne_u32_e64 s9, 0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s8, 0, v3
s_and_saveexec_b32 s10, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s9, exec_lo, s10
s_cbranch_execz .LBB0_30
v_and_b32_e32 v3, 0x3fd, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v3, v3, 2, 0
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v3, v4, v3
.LBB0_30:
s_and_not1_saveexec_b32 s9, s9
s_cbranch_execz .LBB0_32
v_lshl_add_u32 v3, v0, 2, 0
ds_load_b32 v3, v3 offset:8
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v3, v4, v3
.LBB0_32:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt lgkmcnt(0)
v_xor_b32_e32 v4, 0x1ff, v0
s_add_i32 s9, 0, 0x800
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
v_lshl_add_u32 v3, v4, 2, s9
buffer_gl0_inv
ds_load_b32 v4, v2
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v4, v3
v_max_i32_e32 v3, v4, v3
v_xor_b32_e32 v4, 0xff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 0x7f, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s2
v_lshl_add_u32 v4, v4, 2, s9
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 63, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s3
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s4
v_lshl_add_u32 v4, v4, 2, s9
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 15, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s5
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s6
v_lshl_add_u32 v4, v4, 2, s9
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v2
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
v_xor_b32_e32 v4, 3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v5, s7
v_lshl_add_u32 v4, v4, 2, 0
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v1
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v3, v4
v_max_i32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s8
ds_store_b32 v2, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v2
v_and_b32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 1, v3
s_and_saveexec_b32 s2, vcc_lo
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_34
v_and_b32_e32 v3, 0x3fe, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v3, v3, 2, 0
ds_load_b32 v3, v3 offset:2048
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v3, v2, v3
.LBB0_34:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_36
v_lshl_add_u32 v3, v0, 2, 0
ds_load_b32 v3, v3 offset:2052
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v3, v2, v3
.LBB0_36:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v1
v_lshl_add_u32 v0, s15, 9, v0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vsort1PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vsort1PiS_, .Lfunc_end0-_Z6vsort1PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vsort1PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vsort1PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void vsort1(int *input0,int *result0){
unsigned int tid = threadIdx.x;
unsigned int bid = blockIdx.x;
extern __shared__ __attribute__ ((aligned (16))) unsigned char sbase[];
(( int *)sbase)[tid] = ((tid&256)==0) ? min(input0[((bid*512)+tid)],input0[((bid*512)+(tid^256))]) : max(input0[((bid*512)+tid)],input0[((bid*512)+(tid^256))]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^384)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^384)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^128)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^128)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^448)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^448)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^192)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^192)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^64)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^480)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^480)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^224)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^224)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^96)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^96)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^32)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^496)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^496)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^240)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^240)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^112)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^112)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^48)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^48)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^16)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^504)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^504)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^248)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^248)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^120)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^120)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^56)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^56)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^24)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^24)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^8)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&256)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^508)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^508)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&128)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^252)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^252)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&64)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^124)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^124)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&32)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^60)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^60)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&16)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^28)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^28)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&8)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^12)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^12)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&4)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^4)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^510)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^510)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^254)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^254)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^126)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^126)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^62)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^62)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^30)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^30)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^14)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^14)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^6)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^6)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^2)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&256)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^511)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&128)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^255)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^255)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&64)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^127)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^127)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&32)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^63)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&16)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^31)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&8)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^15)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^15)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&4)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^7)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^7)]);
__syncthreads();
(( int *)(sbase + 2048))[tid] = ((tid&2)==0) ? min((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]) : max((( int *)sbase)[tid],(( int *)sbase)[(tid^3)]);
__syncthreads();
(( int *)sbase)[tid] = ((tid&1)==0) ? min((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]) : max((( int *)(sbase+2048))[tid],(( int *)(sbase+2048))[(tid^1)]);
__syncthreads();
result0[((bid*512)+tid)] = (( int *)sbase)[tid];
} | .text
.file "vsort1Kernel.hip"
.globl _Z21__device_stub__vsort1PiS_ # -- Begin function _Z21__device_stub__vsort1PiS_
.p2align 4, 0x90
.type _Z21__device_stub__vsort1PiS_,@function
_Z21__device_stub__vsort1PiS_: # @_Z21__device_stub__vsort1PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6vsort1PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__vsort1PiS_, .Lfunc_end0-_Z21__device_stub__vsort1PiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vsort1PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vsort1PiS_,@object # @_Z6vsort1PiS_
.section .rodata,"a",@progbits
.globl _Z6vsort1PiS_
.p2align 3, 0x0
_Z6vsort1PiS_:
.quad _Z21__device_stub__vsort1PiS_
.size _Z6vsort1PiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vsort1PiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vsort1PiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vsort1PiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e9e27_00000000-6_vsort1Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6vsort1PiS_PiS_
.type _Z27__device_stub__Z6vsort1PiS_PiS_, @function
_Z27__device_stub__Z6vsort1PiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6vsort1PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z6vsort1PiS_PiS_, .-_Z27__device_stub__Z6vsort1PiS_PiS_
.globl _Z6vsort1PiS_
.type _Z6vsort1PiS_, @function
_Z6vsort1PiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6vsort1PiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vsort1PiS_, .-_Z6vsort1PiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vsort1PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vsort1PiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vsort1Kernel.hip"
.globl _Z21__device_stub__vsort1PiS_ # -- Begin function _Z21__device_stub__vsort1PiS_
.p2align 4, 0x90
.type _Z21__device_stub__vsort1PiS_,@function
_Z21__device_stub__vsort1PiS_: # @_Z21__device_stub__vsort1PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6vsort1PiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__vsort1PiS_, .Lfunc_end0-_Z21__device_stub__vsort1PiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vsort1PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vsort1PiS_,@object # @_Z6vsort1PiS_
.section .rodata,"a",@progbits
.globl _Z6vsort1PiS_
.p2align 3, 0x0
_Z6vsort1PiS_:
.quad _Z21__device_stub__vsort1PiS_
.size _Z6vsort1PiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vsort1PiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vsort1PiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vsort1PiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __constant__ int numFreqs;
__constant__ int numPoints;
__constant__ float centerFreq;
/*Finds the index of largest value among the input (size numFreqs)*/
__device__ int argmax(float* input) {
float max = input[0];
int best = 0;
for (int i = 1; i < numFreqs; i++) {
if (input[i] > max) {
max = input[i];
best = i;
}
}
return best;
}
__device__ int dCountPeaks(float *input, float *frequencies) {
int peaks = 0;
for (int i = 1; i < numFreqs - 1; i++) {
if ((input[i] > input[i-1] ||
(input[i] == input[i-1] && i > 1 && input[i] > input[i-2])) //extra term where y progresses like 1, 4, 4, 2
&& input[i] > input[i+1]) peaks++;
}
return peaks;
}
/*Output is numPoints * 3 array: height, center, standard deviation (a*e^(-(x-b)^2/(2c^2)))
Only uses the points surrounding the maximum value where y>ymax*cutoffPortion
If quadratic is true, outputs an approximation for the top of the gaussian in the form a(x-b)^2 + c
Otherwise outputs gaussian parameters*/
__global__ void reg(float *input, float *output, float *frequencies, float cutoffPortion, bool quadratic){
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input += idx * numFreqs;
output += idx * 3;
float scaleFactor = 1.0 / (frequencies[numFreqs-1] - frequencies[0]); //avoid float overflow, just scale things
int maxI = argmax(input);
float threshold = input[maxI] * cutoffPortion;
float s40 = 0, s30 = 0, s20 = 0, s10 = 0, s00 = 0, s21 = 0, s11 = 0, s01 = 0; //quadratic regression stuff
float yval, frequency;
//go left from peak, then go right from peak
for (int i = maxI; i < numFreqs && input[i] > threshold; i++) {
yval = quadratic ? input[i] / input[maxI] : __logf(input[i]); //in quadratic, divide by input[maxI] to avoid underflow
frequency = frequencies[i] - frequencies[0]; //shift over by maxFreq to avoid floating point errors
frequency *= scaleFactor; //scale by scaleFactor to avoid underflow/overflow
s00++;
s10 += frequency;
s20 += frequency * frequency;
s30 += frequency * frequency * frequency;
s40 += frequency * frequency * frequency * frequency;
s01 += yval;
s11 += frequency * yval;
s21 += frequency * frequency * yval;
}
for (int i = maxI-1; i > 0 && input[i] > threshold; i--) {
yval = quadratic ? input[i] / input[maxI] : __logf(input[i]);
frequency = frequencies[i] - frequencies[0]; //shift over by maxFreq to avoid floating point errors
frequency *= scaleFactor; //scale by scaleFactor to avoid underflow/overflow
s00++;
s10 += frequency;
s20 += frequency * frequency;
s30 += frequency * frequency * frequency;
s40 += frequency * frequency * frequency * frequency;
s01 += yval;
s11 += frequency * yval;
s21 += frequency * frequency * yval;
}
float a, b, c, q;
//magical quadratic regression stuff
q = (s40*(s20 * s00 - s10 * s10) -
s30*(s30 * s00 - s10 * s20) +
s20*(s30 * s10 - s20 * s20));
a = (s21*(s20 * s00 - s10 * s10) -
s11*(s30 * s00 - s10 * s20) +
s01*(s30 * s10 - s20 * s20))
/ q;
b = (s40*(s11 * s00 - s01 * s10) -
s30*(s21 * s00 - s01 * s20) +
s20*(s21 * s10 - s11 * s20))
/ q;
c = (s40*(s20 * s01 - s10 * s11) -
s30*(s30 * s01 - s10 * s21) +
s20*(s30 * s11 - s20 * s21))
/ q;
//ax^2+bx+c=Ae^((x-b)^2/2c^2)
if (a > 0) {
output[0] = output[1] = output[2] = 0;
}
if (quadratic) { //scalefactors and input[maxI] and frequencies[0] terms are there to fix scaled/shifted values
output[0] = a * input[maxI] / scaleFactor;
output[1] = -b / scaleFactor / (2 * a) + frequencies[0];
output[2] = (c - b * b / (4 * a)) * input[maxI];
} else {
output[0] = __expf(c - (b * b) / (4 * a));
output[1] = -b / scaleFactor / (2 * a) + frequencies[0];
output[2] = sqrtf(-1 / (2 * a)) / scaleFactor;
}
if (!isfinite(a) || !isfinite(b) || !isfinite(c)) {
output[0] = output[1] = output[2] = 0;
return;
}
}
/*Finds the absolute peak values of the function.*/
__global__ void findPeaks(float *input, float *output, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
int maxI = argmax(input);
output[0] = frequencies[maxI];
}
/*Counts the number of peaks, where d2y/df2 < 0 and dy/df=0*/
__global__ void countPeaks(float *input, int *output, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input += idx * numFreqs;
output += idx;
*output = dCountPeaks(input, frequencies);
}
/*Does a single integration using frequency bounds*/
__device__ float integrate(float *input, float *frequencies, float lowerbound, float upperbound) {
int i;
float integral = 0, width, h1;
for (i = 0; frequencies[i] < lowerbound && i < numFreqs; i++);
if (i == numFreqs) return 0;
if (i != 0) {
//interpolation to find trapezoid size
width = frequencies[i] - lowerbound;
h1 = input[i-1] + (lowerbound - frequencies[i-1]) / (frequencies[i] - frequencies[i-1]) * (input[i] - input[i-1]);
integral += (h1 + input[i]) * width / 2;
}
for(i++; frequencies[i] < upperbound && i < numFreqs; i++) {
integral += (input[i] + input[i-1]) * (frequencies[i] - frequencies[i-1]) / 2;
}
if (i == numFreqs) return integral;
//interpolation to find trapezoid size
width = upperbound - frequencies[i-1];
h1 = input[i-1] + (upperbound - frequencies[i-1]) / (frequencies[i] - frequencies[i-1]) * (input[i] - input[i-1]);
integral += (h1 + input[i-1]) * width / 2;
return integral;
}
/*Integrates everything to the left or right of a particular frequency until input hits limit * input[target]*/
__global__ void integrateLR(float *input, float *output, float *target, float *frequencies, float limit, bool left) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
float targetFrequency = target[idx];
float boundFrequency;
int end;
for (end = 0; frequencies[end] < targetFrequency; end++); //end is frequency position of target
limit *= input[end]; //set limit input value
if (left) {
for (; end >= 0 && input[end] > limit; end--);
boundFrequency = end >= 0 ? frequencies[end] : -INFINITY;
*output = integrate(input, frequencies, boundFrequency, targetFrequency);
} else { //right
for (; end < numFreqs && input[end] > limit; end++);
boundFrequency = end < numFreqs ? frequencies[end] : INFINITY;
*output = integrate(input, frequencies, targetFrequency, boundFrequency);
}
}
/*Does integration between bounds, where bounds is a n*2 array*/
__global__ void integrateBounds(float *input, float *output, float *bounds, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
float lowerbound = bounds[idx];
float upperbound = bounds[idx + numPoints];
*output = integrate(input, frequencies, lowerbound, upperbound);
}
/* Finds the width of the profile at half maximum.*/
__global__ void fwhm(float *input, float *output, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
int peak = argmax(input);
float halfIntensity = input[peak] / 2;
float upperbound = 0;
float lowerbound = 0;
int i;
for (i = peak; input[i] > halfIntensity && i < numFreqs; i++);
upperbound = frequencies[i-1] + (frequencies[i] - frequencies[i-1]) *
(halfIntensity - input[i]) / (input[i-1] - input[i]);
for (i = peak; input[i] > halfIntensity && i >= 0; i--);
lowerbound = frequencies[i] + (frequencies[i+1] - frequencies[i]) *
(halfIntensity - input[i]) / (input[i+1] - input[i]);
if (upperbound != upperbound || lowerbound != lowerbound)
*output = 0;
else
*output = upperbound - lowerbound;
} | .file "tmpxft_000ea266_00000000-6_sa.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6argmaxPf
.type _Z6argmaxPf, @function
_Z6argmaxPf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z6argmaxPf, .-_Z6argmaxPf
.globl _Z11dCountPeaksPfS_
.type _Z11dCountPeaksPfS_, @function
_Z11dCountPeaksPfS_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z11dCountPeaksPfS_, .-_Z11dCountPeaksPfS_
.globl _Z9integratePfS_ff
.type _Z9integratePfS_ff, @function
_Z9integratePfS_ff:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z9integratePfS_ff, .-_Z9integratePfS_ff
.globl _Z28__device_stub__Z3regPfS_S_fbPfS_S_fb
.type _Z28__device_stub__Z3regPfS_S_fbPfS_S_fb, @function
_Z28__device_stub__Z3regPfS_S_fbPfS_S_fb:
.LFB2054:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movb %cl, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3regPfS_S_fb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z28__device_stub__Z3regPfS_S_fbPfS_S_fb, .-_Z28__device_stub__Z3regPfS_S_fbPfS_S_fb
.globl _Z3regPfS_S_fb
.type _Z3regPfS_S_fb, @function
_Z3regPfS_S_fb:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %cl, %ecx
call _Z28__device_stub__Z3regPfS_S_fbPfS_S_fb
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z3regPfS_S_fb, .-_Z3regPfS_S_fb
.globl _Z32__device_stub__Z9findPeaksPfS_S_PfS_S_
.type _Z32__device_stub__Z9findPeaksPfS_S_PfS_S_, @function
_Z32__device_stub__Z9findPeaksPfS_S_PfS_S_:
.LFB2056:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9findPeaksPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z32__device_stub__Z9findPeaksPfS_S_PfS_S_, .-_Z32__device_stub__Z9findPeaksPfS_S_PfS_S_
.globl _Z9findPeaksPfS_S_
.type _Z9findPeaksPfS_S_, @function
_Z9findPeaksPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9findPeaksPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z9findPeaksPfS_S_, .-_Z9findPeaksPfS_S_
.globl _Z34__device_stub__Z10countPeaksPfPiS_PfPiS_
.type _Z34__device_stub__Z10countPeaksPfPiS_PfPiS_, @function
_Z34__device_stub__Z10countPeaksPfPiS_PfPiS_:
.LFB2058:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10countPeaksPfPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z34__device_stub__Z10countPeaksPfPiS_PfPiS_, .-_Z34__device_stub__Z10countPeaksPfPiS_PfPiS_
.globl _Z10countPeaksPfPiS_
.type _Z10countPeaksPfPiS_, @function
_Z10countPeaksPfPiS_:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10countPeaksPfPiS_PfPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10countPeaksPfPiS_, .-_Z10countPeaksPfPiS_
.globl _Z39__device_stub__Z11integrateLRPfS_S_S_fbPfS_S_S_fb
.type _Z39__device_stub__Z11integrateLRPfS_S_S_fbPfS_S_S_fb, @function
_Z39__device_stub__Z11integrateLRPfS_S_S_fbPfS_S_S_fb:
.LFB2060:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movb %r8b, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11integrateLRPfS_S_S_fb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z39__device_stub__Z11integrateLRPfS_S_S_fbPfS_S_S_fb, .-_Z39__device_stub__Z11integrateLRPfS_S_S_fbPfS_S_S_fb
.globl _Z11integrateLRPfS_S_S_fb
.type _Z11integrateLRPfS_S_S_fb, @function
_Z11integrateLRPfS_S_S_fb:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r8b, %r8d
call _Z39__device_stub__Z11integrateLRPfS_S_S_fbPfS_S_S_fb
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z11integrateLRPfS_S_S_fb, .-_Z11integrateLRPfS_S_S_fb
.globl _Z41__device_stub__Z15integrateBoundsPfS_S_S_PfS_S_S_
.type _Z41__device_stub__Z15integrateBoundsPfS_S_S_PfS_S_S_, @function
_Z41__device_stub__Z15integrateBoundsPfS_S_S_PfS_S_S_:
.LFB2062:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15integrateBoundsPfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z41__device_stub__Z15integrateBoundsPfS_S_S_PfS_S_S_, .-_Z41__device_stub__Z15integrateBoundsPfS_S_S_PfS_S_S_
.globl _Z15integrateBoundsPfS_S_S_
.type _Z15integrateBoundsPfS_S_S_, @function
_Z15integrateBoundsPfS_S_S_:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15integrateBoundsPfS_S_S_PfS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z15integrateBoundsPfS_S_S_, .-_Z15integrateBoundsPfS_S_S_
.globl _Z27__device_stub__Z4fwhmPfS_S_PfS_S_
.type _Z27__device_stub__Z4fwhmPfS_S_PfS_S_, @function
_Z27__device_stub__Z4fwhmPfS_S_PfS_S_:
.LFB2064:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4fwhmPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z27__device_stub__Z4fwhmPfS_S_PfS_S_, .-_Z27__device_stub__Z4fwhmPfS_S_PfS_S_
.globl _Z4fwhmPfS_S_
.type _Z4fwhmPfS_S_, @function
_Z4fwhmPfS_S_:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4fwhmPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z4fwhmPfS_S_, .-_Z4fwhmPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4fwhmPfS_S_"
.LC1:
.string "_Z15integrateBoundsPfS_S_S_"
.LC2:
.string "_Z11integrateLRPfS_S_S_fb"
.LC3:
.string "_Z10countPeaksPfPiS_"
.LC4:
.string "_Z9findPeaksPfS_S_"
.LC5:
.string "_Z3regPfS_S_fb"
.LC6:
.string "numFreqs"
.LC7:
.string "numPoints"
.LC8:
.string "centerFreq"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4fwhmPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15integrateBoundsPfS_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11integrateLRPfS_S_S_fb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10countPeaksPfPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9findPeaksPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3regPfS_S_fb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8numFreqs(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9numPoints(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10centerFreq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL10centerFreq
.comm _ZL10centerFreq,4,4
.local _ZL9numPoints
.comm _ZL9numPoints,4,4
.local _ZL8numFreqs
.comm _ZL8numFreqs,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __constant__ int numFreqs;
__constant__ int numPoints;
__constant__ float centerFreq;
/*Finds the index of largest value among the input (size numFreqs)*/
__device__ int argmax(float* input) {
float max = input[0];
int best = 0;
for (int i = 1; i < numFreqs; i++) {
if (input[i] > max) {
max = input[i];
best = i;
}
}
return best;
}
__device__ int dCountPeaks(float *input, float *frequencies) {
int peaks = 0;
for (int i = 1; i < numFreqs - 1; i++) {
if ((input[i] > input[i-1] ||
(input[i] == input[i-1] && i > 1 && input[i] > input[i-2])) //extra term where y progresses like 1, 4, 4, 2
&& input[i] > input[i+1]) peaks++;
}
return peaks;
}
/*Output is numPoints * 3 array: height, center, standard deviation (a*e^(-(x-b)^2/(2c^2)))
Only uses the points surrounding the maximum value where y>ymax*cutoffPortion
If quadratic is true, outputs an approximation for the top of the gaussian in the form a(x-b)^2 + c
Otherwise outputs gaussian parameters*/
__global__ void reg(float *input, float *output, float *frequencies, float cutoffPortion, bool quadratic){
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input += idx * numFreqs;
output += idx * 3;
float scaleFactor = 1.0 / (frequencies[numFreqs-1] - frequencies[0]); //avoid float overflow, just scale things
int maxI = argmax(input);
float threshold = input[maxI] * cutoffPortion;
float s40 = 0, s30 = 0, s20 = 0, s10 = 0, s00 = 0, s21 = 0, s11 = 0, s01 = 0; //quadratic regression stuff
float yval, frequency;
//go left from peak, then go right from peak
for (int i = maxI; i < numFreqs && input[i] > threshold; i++) {
yval = quadratic ? input[i] / input[maxI] : __logf(input[i]); //in quadratic, divide by input[maxI] to avoid underflow
frequency = frequencies[i] - frequencies[0]; //shift over by maxFreq to avoid floating point errors
frequency *= scaleFactor; //scale by scaleFactor to avoid underflow/overflow
s00++;
s10 += frequency;
s20 += frequency * frequency;
s30 += frequency * frequency * frequency;
s40 += frequency * frequency * frequency * frequency;
s01 += yval;
s11 += frequency * yval;
s21 += frequency * frequency * yval;
}
for (int i = maxI-1; i > 0 && input[i] > threshold; i--) {
yval = quadratic ? input[i] / input[maxI] : __logf(input[i]);
frequency = frequencies[i] - frequencies[0]; //shift over by maxFreq to avoid floating point errors
frequency *= scaleFactor; //scale by scaleFactor to avoid underflow/overflow
s00++;
s10 += frequency;
s20 += frequency * frequency;
s30 += frequency * frequency * frequency;
s40 += frequency * frequency * frequency * frequency;
s01 += yval;
s11 += frequency * yval;
s21 += frequency * frequency * yval;
}
float a, b, c, q;
//magical quadratic regression stuff
q = (s40*(s20 * s00 - s10 * s10) -
s30*(s30 * s00 - s10 * s20) +
s20*(s30 * s10 - s20 * s20));
a = (s21*(s20 * s00 - s10 * s10) -
s11*(s30 * s00 - s10 * s20) +
s01*(s30 * s10 - s20 * s20))
/ q;
b = (s40*(s11 * s00 - s01 * s10) -
s30*(s21 * s00 - s01 * s20) +
s20*(s21 * s10 - s11 * s20))
/ q;
c = (s40*(s20 * s01 - s10 * s11) -
s30*(s30 * s01 - s10 * s21) +
s20*(s30 * s11 - s20 * s21))
/ q;
//ax^2+bx+c=Ae^((x-b)^2/2c^2)
if (a > 0) {
output[0] = output[1] = output[2] = 0;
}
if (quadratic) { //scalefactors and input[maxI] and frequencies[0] terms are there to fix scaled/shifted values
output[0] = a * input[maxI] / scaleFactor;
output[1] = -b / scaleFactor / (2 * a) + frequencies[0];
output[2] = (c - b * b / (4 * a)) * input[maxI];
} else {
output[0] = __expf(c - (b * b) / (4 * a));
output[1] = -b / scaleFactor / (2 * a) + frequencies[0];
output[2] = sqrtf(-1 / (2 * a)) / scaleFactor;
}
if (!isfinite(a) || !isfinite(b) || !isfinite(c)) {
output[0] = output[1] = output[2] = 0;
return;
}
}
/*Finds the absolute peak values of the function.*/
__global__ void findPeaks(float *input, float *output, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
int maxI = argmax(input);
output[0] = frequencies[maxI];
}
/*Counts the number of peaks, where d2y/df2 < 0 and dy/df=0*/
__global__ void countPeaks(float *input, int *output, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input += idx * numFreqs;
output += idx;
*output = dCountPeaks(input, frequencies);
}
/*Does a single integration using frequency bounds*/
__device__ float integrate(float *input, float *frequencies, float lowerbound, float upperbound) {
int i;
float integral = 0, width, h1;
for (i = 0; frequencies[i] < lowerbound && i < numFreqs; i++);
if (i == numFreqs) return 0;
if (i != 0) {
//interpolation to find trapezoid size
width = frequencies[i] - lowerbound;
h1 = input[i-1] + (lowerbound - frequencies[i-1]) / (frequencies[i] - frequencies[i-1]) * (input[i] - input[i-1]);
integral += (h1 + input[i]) * width / 2;
}
for(i++; frequencies[i] < upperbound && i < numFreqs; i++) {
integral += (input[i] + input[i-1]) * (frequencies[i] - frequencies[i-1]) / 2;
}
if (i == numFreqs) return integral;
//interpolation to find trapezoid size
width = upperbound - frequencies[i-1];
h1 = input[i-1] + (upperbound - frequencies[i-1]) / (frequencies[i] - frequencies[i-1]) * (input[i] - input[i-1]);
integral += (h1 + input[i-1]) * width / 2;
return integral;
}
/*Integrates everything to the left or right of a particular frequency until input hits limit * input[target]*/
__global__ void integrateLR(float *input, float *output, float *target, float *frequencies, float limit, bool left) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
float targetFrequency = target[idx];
float boundFrequency;
int end;
for (end = 0; frequencies[end] < targetFrequency; end++); //end is frequency position of target
limit *= input[end]; //set limit input value
if (left) {
for (; end >= 0 && input[end] > limit; end--);
boundFrequency = end >= 0 ? frequencies[end] : -INFINITY;
*output = integrate(input, frequencies, boundFrequency, targetFrequency);
} else { //right
for (; end < numFreqs && input[end] > limit; end++);
boundFrequency = end < numFreqs ? frequencies[end] : INFINITY;
*output = integrate(input, frequencies, targetFrequency, boundFrequency);
}
}
/*Does integration between bounds, where bounds is a n*2 array*/
__global__ void integrateBounds(float *input, float *output, float *bounds, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
float lowerbound = bounds[idx];
float upperbound = bounds[idx + numPoints];
*output = integrate(input, frequencies, lowerbound, upperbound);
}
/* Finds the width of the profile at half maximum.*/
__global__ void fwhm(float *input, float *output, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
int peak = argmax(input);
float halfIntensity = input[peak] / 2;
float upperbound = 0;
float lowerbound = 0;
int i;
for (i = peak; input[i] > halfIntensity && i < numFreqs; i++);
upperbound = frequencies[i-1] + (frequencies[i] - frequencies[i-1]) *
(halfIntensity - input[i]) / (input[i-1] - input[i]);
for (i = peak; input[i] > halfIntensity && i >= 0; i--);
lowerbound = frequencies[i] + (frequencies[i+1] - frequencies[i]) *
(halfIntensity - input[i]) / (input[i+1] - input[i]);
if (upperbound != upperbound || lowerbound != lowerbound)
*output = 0;
else
*output = upperbound - lowerbound;
} | #include <hip/hip_runtime.h>
__constant__ int numFreqs;
__constant__ int numPoints;
__constant__ float centerFreq;
/*Finds the index of largest value among the input (size numFreqs)*/
__device__ int argmax(float* input) {
float max = input[0];
int best = 0;
for (int i = 1; i < numFreqs; i++) {
if (input[i] > max) {
max = input[i];
best = i;
}
}
return best;
}
__device__ int dCountPeaks(float *input, float *frequencies) {
int peaks = 0;
for (int i = 1; i < numFreqs - 1; i++) {
if ((input[i] > input[i-1] ||
(input[i] == input[i-1] && i > 1 && input[i] > input[i-2])) //extra term where y progresses like 1, 4, 4, 2
&& input[i] > input[i+1]) peaks++;
}
return peaks;
}
/*Output is numPoints * 3 array: height, center, standard deviation (a*e^(-(x-b)^2/(2c^2)))
Only uses the points surrounding the maximum value where y>ymax*cutoffPortion
If quadratic is true, outputs an approximation for the top of the gaussian in the form a(x-b)^2 + c
Otherwise outputs gaussian parameters*/
__global__ void reg(float *input, float *output, float *frequencies, float cutoffPortion, bool quadratic){
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input += idx * numFreqs;
output += idx * 3;
float scaleFactor = 1.0 / (frequencies[numFreqs-1] - frequencies[0]); //avoid float overflow, just scale things
int maxI = argmax(input);
float threshold = input[maxI] * cutoffPortion;
float s40 = 0, s30 = 0, s20 = 0, s10 = 0, s00 = 0, s21 = 0, s11 = 0, s01 = 0; //quadratic regression stuff
float yval, frequency;
//go left from peak, then go right from peak
for (int i = maxI; i < numFreqs && input[i] > threshold; i++) {
yval = quadratic ? input[i] / input[maxI] : __logf(input[i]); //in quadratic, divide by input[maxI] to avoid underflow
frequency = frequencies[i] - frequencies[0]; //shift over by maxFreq to avoid floating point errors
frequency *= scaleFactor; //scale by scaleFactor to avoid underflow/overflow
s00++;
s10 += frequency;
s20 += frequency * frequency;
s30 += frequency * frequency * frequency;
s40 += frequency * frequency * frequency * frequency;
s01 += yval;
s11 += frequency * yval;
s21 += frequency * frequency * yval;
}
for (int i = maxI-1; i > 0 && input[i] > threshold; i--) {
yval = quadratic ? input[i] / input[maxI] : __logf(input[i]);
frequency = frequencies[i] - frequencies[0]; //shift over by maxFreq to avoid floating point errors
frequency *= scaleFactor; //scale by scaleFactor to avoid underflow/overflow
s00++;
s10 += frequency;
s20 += frequency * frequency;
s30 += frequency * frequency * frequency;
s40 += frequency * frequency * frequency * frequency;
s01 += yval;
s11 += frequency * yval;
s21 += frequency * frequency * yval;
}
float a, b, c, q;
//magical quadratic regression stuff
q = (s40*(s20 * s00 - s10 * s10) -
s30*(s30 * s00 - s10 * s20) +
s20*(s30 * s10 - s20 * s20));
a = (s21*(s20 * s00 - s10 * s10) -
s11*(s30 * s00 - s10 * s20) +
s01*(s30 * s10 - s20 * s20))
/ q;
b = (s40*(s11 * s00 - s01 * s10) -
s30*(s21 * s00 - s01 * s20) +
s20*(s21 * s10 - s11 * s20))
/ q;
c = (s40*(s20 * s01 - s10 * s11) -
s30*(s30 * s01 - s10 * s21) +
s20*(s30 * s11 - s20 * s21))
/ q;
//ax^2+bx+c=Ae^((x-b)^2/2c^2)
if (a > 0) {
output[0] = output[1] = output[2] = 0;
}
if (quadratic) { //scalefactors and input[maxI] and frequencies[0] terms are there to fix scaled/shifted values
output[0] = a * input[maxI] / scaleFactor;
output[1] = -b / scaleFactor / (2 * a) + frequencies[0];
output[2] = (c - b * b / (4 * a)) * input[maxI];
} else {
output[0] = __expf(c - (b * b) / (4 * a));
output[1] = -b / scaleFactor / (2 * a) + frequencies[0];
output[2] = sqrtf(-1 / (2 * a)) / scaleFactor;
}
if (!isfinite(a) || !isfinite(b) || !isfinite(c)) {
output[0] = output[1] = output[2] = 0;
return;
}
}
/*Finds the absolute peak values of the function.*/
__global__ void findPeaks(float *input, float *output, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
int maxI = argmax(input);
output[0] = frequencies[maxI];
}
/*Counts the number of peaks, where d2y/df2 < 0 and dy/df=0*/
__global__ void countPeaks(float *input, int *output, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input += idx * numFreqs;
output += idx;
*output = dCountPeaks(input, frequencies);
}
/*Does a single integration using frequency bounds*/
__device__ float integrate(float *input, float *frequencies, float lowerbound, float upperbound) {
int i;
float integral = 0, width, h1;
for (i = 0; frequencies[i] < lowerbound && i < numFreqs; i++);
if (i == numFreqs) return 0;
if (i != 0) {
//interpolation to find trapezoid size
width = frequencies[i] - lowerbound;
h1 = input[i-1] + (lowerbound - frequencies[i-1]) / (frequencies[i] - frequencies[i-1]) * (input[i] - input[i-1]);
integral += (h1 + input[i]) * width / 2;
}
for(i++; frequencies[i] < upperbound && i < numFreqs; i++) {
integral += (input[i] + input[i-1]) * (frequencies[i] - frequencies[i-1]) / 2;
}
if (i == numFreqs) return integral;
//interpolation to find trapezoid size
width = upperbound - frequencies[i-1];
h1 = input[i-1] + (upperbound - frequencies[i-1]) / (frequencies[i] - frequencies[i-1]) * (input[i] - input[i-1]);
integral += (h1 + input[i-1]) * width / 2;
return integral;
}
/*Integrates everything to the left or right of a particular frequency until input hits limit * input[target]*/
__global__ void integrateLR(float *input, float *output, float *target, float *frequencies, float limit, bool left) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
float targetFrequency = target[idx];
float boundFrequency;
int end;
for (end = 0; frequencies[end] < targetFrequency; end++); //end is frequency position of target
limit *= input[end]; //set limit input value
if (left) {
for (; end >= 0 && input[end] > limit; end--);
boundFrequency = end >= 0 ? frequencies[end] : -INFINITY;
*output = integrate(input, frequencies, boundFrequency, targetFrequency);
} else { //right
for (; end < numFreqs && input[end] > limit; end++);
boundFrequency = end < numFreqs ? frequencies[end] : INFINITY;
*output = integrate(input, frequencies, targetFrequency, boundFrequency);
}
}
/*Does integration between bounds, where bounds is a n*2 array*/
__global__ void integrateBounds(float *input, float *output, float *bounds, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
float lowerbound = bounds[idx];
float upperbound = bounds[idx + numPoints];
*output = integrate(input, frequencies, lowerbound, upperbound);
}
/* Finds the width of the profile at half maximum.*/
__global__ void fwhm(float *input, float *output, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
int peak = argmax(input);
float halfIntensity = input[peak] / 2;
float upperbound = 0;
float lowerbound = 0;
int i;
for (i = peak; input[i] > halfIntensity && i < numFreqs; i++);
upperbound = frequencies[i-1] + (frequencies[i] - frequencies[i-1]) *
(halfIntensity - input[i]) / (input[i-1] - input[i]);
for (i = peak; input[i] > halfIntensity && i >= 0; i--);
lowerbound = frequencies[i] + (frequencies[i+1] - frequencies[i]) *
(halfIntensity - input[i]) / (input[i+1] - input[i]);
if (upperbound != upperbound || lowerbound != lowerbound)
*output = 0;
else
*output = upperbound - lowerbound;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__constant__ int numFreqs;
__constant__ int numPoints;
__constant__ float centerFreq;
/*Finds the index of largest value among the input (size numFreqs)*/
__device__ int argmax(float* input) {
float max = input[0];
int best = 0;
for (int i = 1; i < numFreqs; i++) {
if (input[i] > max) {
max = input[i];
best = i;
}
}
return best;
}
__device__ int dCountPeaks(float *input, float *frequencies) {
int peaks = 0;
for (int i = 1; i < numFreqs - 1; i++) {
if ((input[i] > input[i-1] ||
(input[i] == input[i-1] && i > 1 && input[i] > input[i-2])) //extra term where y progresses like 1, 4, 4, 2
&& input[i] > input[i+1]) peaks++;
}
return peaks;
}
/*Output is numPoints * 3 array: height, center, standard deviation (a*e^(-(x-b)^2/(2c^2)))
Only uses the points surrounding the maximum value where y>ymax*cutoffPortion
If quadratic is true, outputs an approximation for the top of the gaussian in the form a(x-b)^2 + c
Otherwise outputs gaussian parameters*/
__global__ void reg(float *input, float *output, float *frequencies, float cutoffPortion, bool quadratic){
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input += idx * numFreqs;
output += idx * 3;
float scaleFactor = 1.0 / (frequencies[numFreqs-1] - frequencies[0]); //avoid float overflow, just scale things
int maxI = argmax(input);
float threshold = input[maxI] * cutoffPortion;
float s40 = 0, s30 = 0, s20 = 0, s10 = 0, s00 = 0, s21 = 0, s11 = 0, s01 = 0; //quadratic regression stuff
float yval, frequency;
//go left from peak, then go right from peak
for (int i = maxI; i < numFreqs && input[i] > threshold; i++) {
yval = quadratic ? input[i] / input[maxI] : __logf(input[i]); //in quadratic, divide by input[maxI] to avoid underflow
frequency = frequencies[i] - frequencies[0]; //shift over by maxFreq to avoid floating point errors
frequency *= scaleFactor; //scale by scaleFactor to avoid underflow/overflow
s00++;
s10 += frequency;
s20 += frequency * frequency;
s30 += frequency * frequency * frequency;
s40 += frequency * frequency * frequency * frequency;
s01 += yval;
s11 += frequency * yval;
s21 += frequency * frequency * yval;
}
for (int i = maxI-1; i > 0 && input[i] > threshold; i--) {
yval = quadratic ? input[i] / input[maxI] : __logf(input[i]);
frequency = frequencies[i] - frequencies[0]; //shift over by maxFreq to avoid floating point errors
frequency *= scaleFactor; //scale by scaleFactor to avoid underflow/overflow
s00++;
s10 += frequency;
s20 += frequency * frequency;
s30 += frequency * frequency * frequency;
s40 += frequency * frequency * frequency * frequency;
s01 += yval;
s11 += frequency * yval;
s21 += frequency * frequency * yval;
}
float a, b, c, q;
//magical quadratic regression stuff
q = (s40*(s20 * s00 - s10 * s10) -
s30*(s30 * s00 - s10 * s20) +
s20*(s30 * s10 - s20 * s20));
a = (s21*(s20 * s00 - s10 * s10) -
s11*(s30 * s00 - s10 * s20) +
s01*(s30 * s10 - s20 * s20))
/ q;
b = (s40*(s11 * s00 - s01 * s10) -
s30*(s21 * s00 - s01 * s20) +
s20*(s21 * s10 - s11 * s20))
/ q;
c = (s40*(s20 * s01 - s10 * s11) -
s30*(s30 * s01 - s10 * s21) +
s20*(s30 * s11 - s20 * s21))
/ q;
//ax^2+bx+c=Ae^((x-b)^2/2c^2)
if (a > 0) {
output[0] = output[1] = output[2] = 0;
}
if (quadratic) { //scalefactors and input[maxI] and frequencies[0] terms are there to fix scaled/shifted values
output[0] = a * input[maxI] / scaleFactor;
output[1] = -b / scaleFactor / (2 * a) + frequencies[0];
output[2] = (c - b * b / (4 * a)) * input[maxI];
} else {
output[0] = __expf(c - (b * b) / (4 * a));
output[1] = -b / scaleFactor / (2 * a) + frequencies[0];
output[2] = sqrtf(-1 / (2 * a)) / scaleFactor;
}
if (!isfinite(a) || !isfinite(b) || !isfinite(c)) {
output[0] = output[1] = output[2] = 0;
return;
}
}
/*Finds the absolute peak values of the function.*/
__global__ void findPeaks(float *input, float *output, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
int maxI = argmax(input);
output[0] = frequencies[maxI];
}
/*Counts the number of peaks, where d2y/df2 < 0 and dy/df=0*/
__global__ void countPeaks(float *input, int *output, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input += idx * numFreqs;
output += idx;
*output = dCountPeaks(input, frequencies);
}
/*Does a single integration using frequency bounds*/
__device__ float integrate(float *input, float *frequencies, float lowerbound, float upperbound) {
int i;
float integral = 0, width, h1;
for (i = 0; frequencies[i] < lowerbound && i < numFreqs; i++);
if (i == numFreqs) return 0;
if (i != 0) {
//interpolation to find trapezoid size
width = frequencies[i] - lowerbound;
h1 = input[i-1] + (lowerbound - frequencies[i-1]) / (frequencies[i] - frequencies[i-1]) * (input[i] - input[i-1]);
integral += (h1 + input[i]) * width / 2;
}
for(i++; frequencies[i] < upperbound && i < numFreqs; i++) {
integral += (input[i] + input[i-1]) * (frequencies[i] - frequencies[i-1]) / 2;
}
if (i == numFreqs) return integral;
//interpolation to find trapezoid size
width = upperbound - frequencies[i-1];
h1 = input[i-1] + (upperbound - frequencies[i-1]) / (frequencies[i] - frequencies[i-1]) * (input[i] - input[i-1]);
integral += (h1 + input[i-1]) * width / 2;
return integral;
}
/*Integrates everything to the left or right of a particular frequency until input hits limit * input[target]*/
__global__ void integrateLR(float *input, float *output, float *target, float *frequencies, float limit, bool left) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
float targetFrequency = target[idx];
float boundFrequency;
int end;
for (end = 0; frequencies[end] < targetFrequency; end++); //end is frequency position of target
limit *= input[end]; //set limit input value
if (left) {
for (; end >= 0 && input[end] > limit; end--);
boundFrequency = end >= 0 ? frequencies[end] : -INFINITY;
*output = integrate(input, frequencies, boundFrequency, targetFrequency);
} else { //right
for (; end < numFreqs && input[end] > limit; end++);
boundFrequency = end < numFreqs ? frequencies[end] : INFINITY;
*output = integrate(input, frequencies, targetFrequency, boundFrequency);
}
}
/*Does integration between bounds, where bounds is a n*2 array*/
__global__ void integrateBounds(float *input, float *output, float *bounds, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
float lowerbound = bounds[idx];
float upperbound = bounds[idx + numPoints];
*output = integrate(input, frequencies, lowerbound, upperbound);
}
/* Finds the width of the profile at half maximum.*/
__global__ void fwhm(float *input, float *output, float *frequencies) {
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if (idx >= numPoints) return;
input = input + idx * numFreqs;
output = output + idx;
int peak = argmax(input);
float halfIntensity = input[peak] / 2;
float upperbound = 0;
float lowerbound = 0;
int i;
for (i = peak; input[i] > halfIntensity && i < numFreqs; i++);
upperbound = frequencies[i-1] + (frequencies[i] - frequencies[i-1]) *
(halfIntensity - input[i]) / (input[i-1] - input[i]);
for (i = peak; input[i] > halfIntensity && i >= 0; i--);
lowerbound = frequencies[i] + (frequencies[i+1] - frequencies[i]) *
(halfIntensity - input[i]) / (input[i+1] - input[i]);
if (upperbound != upperbound || lowerbound != lowerbound)
*output = 0;
else
*output = upperbound - lowerbound;
} | .text
.file "sa.hip"
.globl _Z18__device_stub__regPfS_S_fb # -- Begin function _Z18__device_stub__regPfS_S_fb
.p2align 4, 0x90
.type _Z18__device_stub__regPfS_S_fb,@function
_Z18__device_stub__regPfS_S_fb: # @_Z18__device_stub__regPfS_S_fb
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
movb %cl, 3(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 3(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3regPfS_S_fb, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__regPfS_S_fb, .Lfunc_end0-_Z18__device_stub__regPfS_S_fb
.cfi_endproc
# -- End function
.globl _Z24__device_stub__findPeaksPfS_S_ # -- Begin function _Z24__device_stub__findPeaksPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__findPeaksPfS_S_,@function
_Z24__device_stub__findPeaksPfS_S_: # @_Z24__device_stub__findPeaksPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9findPeaksPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__findPeaksPfS_S_, .Lfunc_end1-_Z24__device_stub__findPeaksPfS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__countPeaksPfPiS_ # -- Begin function _Z25__device_stub__countPeaksPfPiS_
.p2align 4, 0x90
.type _Z25__device_stub__countPeaksPfPiS_,@function
_Z25__device_stub__countPeaksPfPiS_: # @_Z25__device_stub__countPeaksPfPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10countPeaksPfPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z25__device_stub__countPeaksPfPiS_, .Lfunc_end2-_Z25__device_stub__countPeaksPfPiS_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__integrateLRPfS_S_S_fb # -- Begin function _Z26__device_stub__integrateLRPfS_S_S_fb
.p2align 4, 0x90
.type _Z26__device_stub__integrateLRPfS_S_S_fb,@function
_Z26__device_stub__integrateLRPfS_S_S_fb: # @_Z26__device_stub__integrateLRPfS_S_S_fb
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
movb %r8b, 11(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 11(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11integrateLRPfS_S_S_fb, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z26__device_stub__integrateLRPfS_S_S_fb, .Lfunc_end3-_Z26__device_stub__integrateLRPfS_S_S_fb
.cfi_endproc
# -- End function
.globl _Z30__device_stub__integrateBoundsPfS_S_S_ # -- Begin function _Z30__device_stub__integrateBoundsPfS_S_S_
.p2align 4, 0x90
.type _Z30__device_stub__integrateBoundsPfS_S_S_,@function
_Z30__device_stub__integrateBoundsPfS_S_S_: # @_Z30__device_stub__integrateBoundsPfS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15integrateBoundsPfS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z30__device_stub__integrateBoundsPfS_S_S_, .Lfunc_end4-_Z30__device_stub__integrateBoundsPfS_S_S_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__fwhmPfS_S_ # -- Begin function _Z19__device_stub__fwhmPfS_S_
.p2align 4, 0x90
.type _Z19__device_stub__fwhmPfS_S_,@function
_Z19__device_stub__fwhmPfS_S_: # @_Z19__device_stub__fwhmPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4fwhmPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z19__device_stub__fwhmPfS_S_, .Lfunc_end5-_Z19__device_stub__fwhmPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3regPfS_S_fb, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9findPeaksPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10countPeaksPfPiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11integrateLRPfS_S_S_fb, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15integrateBoundsPfS_S_S_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4fwhmPfS_S_, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $numFreqs, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $numPoints, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $centerFreq, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type numFreqs,@object # @numFreqs
.local numFreqs
.comm numFreqs,4,4
.type numPoints,@object # @numPoints
.local numPoints
.comm numPoints,4,4
.type centerFreq,@object # @centerFreq
.local centerFreq
.comm centerFreq,4,4
.type _Z3regPfS_S_fb,@object # @_Z3regPfS_S_fb
.section .rodata,"a",@progbits
.globl _Z3regPfS_S_fb
.p2align 3, 0x0
_Z3regPfS_S_fb:
.quad _Z18__device_stub__regPfS_S_fb
.size _Z3regPfS_S_fb, 8
.type _Z9findPeaksPfS_S_,@object # @_Z9findPeaksPfS_S_
.globl _Z9findPeaksPfS_S_
.p2align 3, 0x0
_Z9findPeaksPfS_S_:
.quad _Z24__device_stub__findPeaksPfS_S_
.size _Z9findPeaksPfS_S_, 8
.type _Z10countPeaksPfPiS_,@object # @_Z10countPeaksPfPiS_
.globl _Z10countPeaksPfPiS_
.p2align 3, 0x0
_Z10countPeaksPfPiS_:
.quad _Z25__device_stub__countPeaksPfPiS_
.size _Z10countPeaksPfPiS_, 8
.type _Z11integrateLRPfS_S_S_fb,@object # @_Z11integrateLRPfS_S_S_fb
.globl _Z11integrateLRPfS_S_S_fb
.p2align 3, 0x0
_Z11integrateLRPfS_S_S_fb:
.quad _Z26__device_stub__integrateLRPfS_S_S_fb
.size _Z11integrateLRPfS_S_S_fb, 8
.type _Z15integrateBoundsPfS_S_S_,@object # @_Z15integrateBoundsPfS_S_S_
.globl _Z15integrateBoundsPfS_S_S_
.p2align 3, 0x0
_Z15integrateBoundsPfS_S_S_:
.quad _Z30__device_stub__integrateBoundsPfS_S_S_
.size _Z15integrateBoundsPfS_S_S_, 8
.type _Z4fwhmPfS_S_,@object # @_Z4fwhmPfS_S_
.globl _Z4fwhmPfS_S_
.p2align 3, 0x0
_Z4fwhmPfS_S_:
.quad _Z19__device_stub__fwhmPfS_S_
.size _Z4fwhmPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3regPfS_S_fb"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9findPeaksPfS_S_"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10countPeaksPfPiS_"
.size .L__unnamed_3, 21
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z11integrateLRPfS_S_S_fb"
.size .L__unnamed_4, 26
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z15integrateBoundsPfS_S_S_"
.size .L__unnamed_5, 28
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z4fwhmPfS_S_"
.size .L__unnamed_6, 14
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "numFreqs"
.size .L__unnamed_7, 9
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "numPoints"
.size .L__unnamed_8, 10
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "centerFreq"
.size .L__unnamed_9, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__regPfS_S_fb
.addrsig_sym _Z24__device_stub__findPeaksPfS_S_
.addrsig_sym _Z25__device_stub__countPeaksPfPiS_
.addrsig_sym _Z26__device_stub__integrateLRPfS_S_S_fb
.addrsig_sym _Z30__device_stub__integrateBoundsPfS_S_S_
.addrsig_sym _Z19__device_stub__fwhmPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym numFreqs
.addrsig_sym numPoints
.addrsig_sym centerFreq
.addrsig_sym _Z3regPfS_S_fb
.addrsig_sym _Z9findPeaksPfS_S_
.addrsig_sym _Z10countPeaksPfPiS_
.addrsig_sym _Z11integrateLRPfS_S_S_fb
.addrsig_sym _Z15integrateBoundsPfS_S_S_
.addrsig_sym _Z4fwhmPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ea266_00000000-6_sa.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6argmaxPf
.type _Z6argmaxPf, @function
_Z6argmaxPf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z6argmaxPf, .-_Z6argmaxPf
.globl _Z11dCountPeaksPfS_
.type _Z11dCountPeaksPfS_, @function
_Z11dCountPeaksPfS_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z11dCountPeaksPfS_, .-_Z11dCountPeaksPfS_
.globl _Z9integratePfS_ff
.type _Z9integratePfS_ff, @function
_Z9integratePfS_ff:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z9integratePfS_ff, .-_Z9integratePfS_ff
.globl _Z28__device_stub__Z3regPfS_S_fbPfS_S_fb
.type _Z28__device_stub__Z3regPfS_S_fbPfS_S_fb, @function
_Z28__device_stub__Z3regPfS_S_fbPfS_S_fb:
.LFB2054:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movb %cl, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3regPfS_S_fb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z28__device_stub__Z3regPfS_S_fbPfS_S_fb, .-_Z28__device_stub__Z3regPfS_S_fbPfS_S_fb
.globl _Z3regPfS_S_fb
.type _Z3regPfS_S_fb, @function
_Z3regPfS_S_fb:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %cl, %ecx
call _Z28__device_stub__Z3regPfS_S_fbPfS_S_fb
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z3regPfS_S_fb, .-_Z3regPfS_S_fb
.globl _Z32__device_stub__Z9findPeaksPfS_S_PfS_S_
.type _Z32__device_stub__Z9findPeaksPfS_S_PfS_S_, @function
_Z32__device_stub__Z9findPeaksPfS_S_PfS_S_:
.LFB2056:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9findPeaksPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z32__device_stub__Z9findPeaksPfS_S_PfS_S_, .-_Z32__device_stub__Z9findPeaksPfS_S_PfS_S_
.globl _Z9findPeaksPfS_S_
.type _Z9findPeaksPfS_S_, @function
_Z9findPeaksPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9findPeaksPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z9findPeaksPfS_S_, .-_Z9findPeaksPfS_S_
.globl _Z34__device_stub__Z10countPeaksPfPiS_PfPiS_
.type _Z34__device_stub__Z10countPeaksPfPiS_PfPiS_, @function
_Z34__device_stub__Z10countPeaksPfPiS_PfPiS_:
.LFB2058:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10countPeaksPfPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z34__device_stub__Z10countPeaksPfPiS_PfPiS_, .-_Z34__device_stub__Z10countPeaksPfPiS_PfPiS_
.globl _Z10countPeaksPfPiS_
.type _Z10countPeaksPfPiS_, @function
_Z10countPeaksPfPiS_:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10countPeaksPfPiS_PfPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10countPeaksPfPiS_, .-_Z10countPeaksPfPiS_
.globl _Z39__device_stub__Z11integrateLRPfS_S_S_fbPfS_S_S_fb
.type _Z39__device_stub__Z11integrateLRPfS_S_S_fbPfS_S_S_fb, @function
_Z39__device_stub__Z11integrateLRPfS_S_S_fbPfS_S_S_fb:
.LFB2060:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movb %r8b, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11integrateLRPfS_S_S_fb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z39__device_stub__Z11integrateLRPfS_S_S_fbPfS_S_S_fb, .-_Z39__device_stub__Z11integrateLRPfS_S_S_fbPfS_S_S_fb
.globl _Z11integrateLRPfS_S_S_fb
.type _Z11integrateLRPfS_S_S_fb, @function
_Z11integrateLRPfS_S_S_fb:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r8b, %r8d
call _Z39__device_stub__Z11integrateLRPfS_S_S_fbPfS_S_S_fb
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z11integrateLRPfS_S_S_fb, .-_Z11integrateLRPfS_S_S_fb
.globl _Z41__device_stub__Z15integrateBoundsPfS_S_S_PfS_S_S_
.type _Z41__device_stub__Z15integrateBoundsPfS_S_S_PfS_S_S_, @function
_Z41__device_stub__Z15integrateBoundsPfS_S_S_PfS_S_S_:
.LFB2062:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15integrateBoundsPfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z41__device_stub__Z15integrateBoundsPfS_S_S_PfS_S_S_, .-_Z41__device_stub__Z15integrateBoundsPfS_S_S_PfS_S_S_
.globl _Z15integrateBoundsPfS_S_S_
.type _Z15integrateBoundsPfS_S_S_, @function
_Z15integrateBoundsPfS_S_S_:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15integrateBoundsPfS_S_S_PfS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z15integrateBoundsPfS_S_S_, .-_Z15integrateBoundsPfS_S_S_
.globl _Z27__device_stub__Z4fwhmPfS_S_PfS_S_
.type _Z27__device_stub__Z4fwhmPfS_S_PfS_S_, @function
_Z27__device_stub__Z4fwhmPfS_S_PfS_S_:
.LFB2064:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4fwhmPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z27__device_stub__Z4fwhmPfS_S_PfS_S_, .-_Z27__device_stub__Z4fwhmPfS_S_PfS_S_
.globl _Z4fwhmPfS_S_
.type _Z4fwhmPfS_S_, @function
_Z4fwhmPfS_S_:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4fwhmPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z4fwhmPfS_S_, .-_Z4fwhmPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4fwhmPfS_S_"
.LC1:
.string "_Z15integrateBoundsPfS_S_S_"
.LC2:
.string "_Z11integrateLRPfS_S_S_fb"
.LC3:
.string "_Z10countPeaksPfPiS_"
.LC4:
.string "_Z9findPeaksPfS_S_"
.LC5:
.string "_Z3regPfS_S_fb"
.LC6:
.string "numFreqs"
.LC7:
.string "numPoints"
.LC8:
.string "centerFreq"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4fwhmPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15integrateBoundsPfS_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11integrateLRPfS_S_S_fb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10countPeaksPfPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9findPeaksPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3regPfS_S_fb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8numFreqs(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9numPoints(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10centerFreq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL10centerFreq
.comm _ZL10centerFreq,4,4
.local _ZL9numPoints
.comm _ZL9numPoints,4,4
.local _ZL8numFreqs
.comm _ZL8numFreqs,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sa.hip"
.globl _Z18__device_stub__regPfS_S_fb # -- Begin function _Z18__device_stub__regPfS_S_fb
.p2align 4, 0x90
.type _Z18__device_stub__regPfS_S_fb,@function
_Z18__device_stub__regPfS_S_fb: # @_Z18__device_stub__regPfS_S_fb
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
movb %cl, 3(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 3(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3regPfS_S_fb, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__regPfS_S_fb, .Lfunc_end0-_Z18__device_stub__regPfS_S_fb
.cfi_endproc
# -- End function
.globl _Z24__device_stub__findPeaksPfS_S_ # -- Begin function _Z24__device_stub__findPeaksPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__findPeaksPfS_S_,@function
_Z24__device_stub__findPeaksPfS_S_: # @_Z24__device_stub__findPeaksPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9findPeaksPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__findPeaksPfS_S_, .Lfunc_end1-_Z24__device_stub__findPeaksPfS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__countPeaksPfPiS_ # -- Begin function _Z25__device_stub__countPeaksPfPiS_
.p2align 4, 0x90
.type _Z25__device_stub__countPeaksPfPiS_,@function
_Z25__device_stub__countPeaksPfPiS_: # @_Z25__device_stub__countPeaksPfPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10countPeaksPfPiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z25__device_stub__countPeaksPfPiS_, .Lfunc_end2-_Z25__device_stub__countPeaksPfPiS_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__integrateLRPfS_S_S_fb # -- Begin function _Z26__device_stub__integrateLRPfS_S_S_fb
.p2align 4, 0x90
.type _Z26__device_stub__integrateLRPfS_S_S_fb,@function
_Z26__device_stub__integrateLRPfS_S_S_fb: # @_Z26__device_stub__integrateLRPfS_S_S_fb
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
movb %r8b, 11(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 11(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11integrateLRPfS_S_S_fb, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z26__device_stub__integrateLRPfS_S_S_fb, .Lfunc_end3-_Z26__device_stub__integrateLRPfS_S_S_fb
.cfi_endproc
# -- End function
.globl _Z30__device_stub__integrateBoundsPfS_S_S_ # -- Begin function _Z30__device_stub__integrateBoundsPfS_S_S_
.p2align 4, 0x90
.type _Z30__device_stub__integrateBoundsPfS_S_S_,@function
_Z30__device_stub__integrateBoundsPfS_S_S_: # @_Z30__device_stub__integrateBoundsPfS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15integrateBoundsPfS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z30__device_stub__integrateBoundsPfS_S_S_, .Lfunc_end4-_Z30__device_stub__integrateBoundsPfS_S_S_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__fwhmPfS_S_ # -- Begin function _Z19__device_stub__fwhmPfS_S_
.p2align 4, 0x90
.type _Z19__device_stub__fwhmPfS_S_,@function
_Z19__device_stub__fwhmPfS_S_: # @_Z19__device_stub__fwhmPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4fwhmPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z19__device_stub__fwhmPfS_S_, .Lfunc_end5-_Z19__device_stub__fwhmPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3regPfS_S_fb, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9findPeaksPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10countPeaksPfPiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11integrateLRPfS_S_S_fb, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15integrateBoundsPfS_S_S_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4fwhmPfS_S_, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $numFreqs, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $numPoints, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $centerFreq, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type numFreqs,@object # @numFreqs
.local numFreqs
.comm numFreqs,4,4
.type numPoints,@object # @numPoints
.local numPoints
.comm numPoints,4,4
.type centerFreq,@object # @centerFreq
.local centerFreq
.comm centerFreq,4,4
.type _Z3regPfS_S_fb,@object # @_Z3regPfS_S_fb
.section .rodata,"a",@progbits
.globl _Z3regPfS_S_fb
.p2align 3, 0x0
_Z3regPfS_S_fb:
.quad _Z18__device_stub__regPfS_S_fb
.size _Z3regPfS_S_fb, 8
.type _Z9findPeaksPfS_S_,@object # @_Z9findPeaksPfS_S_
.globl _Z9findPeaksPfS_S_
.p2align 3, 0x0
_Z9findPeaksPfS_S_:
.quad _Z24__device_stub__findPeaksPfS_S_
.size _Z9findPeaksPfS_S_, 8
.type _Z10countPeaksPfPiS_,@object # @_Z10countPeaksPfPiS_
.globl _Z10countPeaksPfPiS_
.p2align 3, 0x0
_Z10countPeaksPfPiS_:
.quad _Z25__device_stub__countPeaksPfPiS_
.size _Z10countPeaksPfPiS_, 8
.type _Z11integrateLRPfS_S_S_fb,@object # @_Z11integrateLRPfS_S_S_fb
.globl _Z11integrateLRPfS_S_S_fb
.p2align 3, 0x0
_Z11integrateLRPfS_S_S_fb:
.quad _Z26__device_stub__integrateLRPfS_S_S_fb
.size _Z11integrateLRPfS_S_S_fb, 8
.type _Z15integrateBoundsPfS_S_S_,@object # @_Z15integrateBoundsPfS_S_S_
.globl _Z15integrateBoundsPfS_S_S_
.p2align 3, 0x0
_Z15integrateBoundsPfS_S_S_:
.quad _Z30__device_stub__integrateBoundsPfS_S_S_
.size _Z15integrateBoundsPfS_S_S_, 8
.type _Z4fwhmPfS_S_,@object # @_Z4fwhmPfS_S_
.globl _Z4fwhmPfS_S_
.p2align 3, 0x0
_Z4fwhmPfS_S_:
.quad _Z19__device_stub__fwhmPfS_S_
.size _Z4fwhmPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3regPfS_S_fb"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9findPeaksPfS_S_"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10countPeaksPfPiS_"
.size .L__unnamed_3, 21
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z11integrateLRPfS_S_S_fb"
.size .L__unnamed_4, 26
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z15integrateBoundsPfS_S_S_"
.size .L__unnamed_5, 28
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z4fwhmPfS_S_"
.size .L__unnamed_6, 14
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "numFreqs"
.size .L__unnamed_7, 9
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "numPoints"
.size .L__unnamed_8, 10
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "centerFreq"
.size .L__unnamed_9, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__regPfS_S_fb
.addrsig_sym _Z24__device_stub__findPeaksPfS_S_
.addrsig_sym _Z25__device_stub__countPeaksPfPiS_
.addrsig_sym _Z26__device_stub__integrateLRPfS_S_S_fb
.addrsig_sym _Z30__device_stub__integrateBoundsPfS_S_S_
.addrsig_sym _Z19__device_stub__fwhmPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym numFreqs
.addrsig_sym numPoints
.addrsig_sym centerFreq
.addrsig_sym _Z3regPfS_S_fb
.addrsig_sym _Z9findPeaksPfS_S_
.addrsig_sym _Z10countPeaksPfPiS_
.addrsig_sym _Z11integrateLRPfS_S_S_fb
.addrsig_sym _Z15integrateBoundsPfS_S_S_
.addrsig_sym _Z4fwhmPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Compile: nvcc [-g] [-G] -arch=sm_21 -o mat_add mat_add.cu
* Run: ./mat_add <m> <n>
* m is the number of rows
* n is the number of columns
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define BLOCK_DIM 512
/*
[1 1 1]
[1 1 1] => [1 1 1][1 1 1][1 1 1]
[1 1 1]
*/
/*Kernel*/
__global__ void matrixAdd(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (blockIdx.x < N && threadIdx.x < N)
c[index] = a[index] + b[index];
}
__global__ void matrixAddRow(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
for(index = index * N; index < N*N; index++)
{
c[index] = a[index] + b[index];
}
}
__global__ void matrixAddColumn(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
for(; index < N*N; index = index + N)
{
c[index] = a[index] + b[index];
}
}
void Read_matrix(float A[], int s) {
int i, j;
for (i = 0; i < s; i++)
for (j = 0; j < s; j++)
scanf("%f", &A[i*s+j]);
}
void Print_matrix(char name[], float A[], int s) {
int i, j;
printf("%s\n", name);
for (i = 0; i < s; i++) {
for (j = 0; j < s; j++)
printf("%.1f ", A[i*s+j]);
printf("\n");
}
}
/* Host */
int main(int argc, char* argv[]) {
int N;
int size;
float *dev_a, *dev_b, *dev_c;
float *a, *b, *c;
N = strtol(argv[1], NULL, 10);
printf("size = %d", N);
size = N*N*sizeof(float);
a = (float*) malloc(size);
b = (float*) malloc(size);
c = (float*) malloc(size);
printf("Matriz A: \n");
Read_matrix(a, N);
printf("Matriz B: \n");
Read_matrix(b, N);
Print_matrix("A =", a, N);
Print_matrix("B =", b, N);
cudaMalloc(&dev_a, size);
cudaMalloc(&dev_b, size);
cudaMalloc(&dev_c, size);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
// dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
// dim3 dimGrid((int)ceil(N/dimBlock.x),(int)ceil(N/dimBlock.y));
// matrixAddColumn<<<N,N>>>(dev_a,dev_b,dev_c,N);
// matrixAddRow<<<N,N>>>(dev_a,dev_b,dev_c,N);
matrixAdd<<<N,N>>>(dev_a,dev_b,dev_c,N);
cudaThreadSynchronize();
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
Print_matrix("Result =", c, N);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
free(a);
free(b);
free(c);
return 0;
} | .file "tmpxft_001a17f9_00000000-6_cap-3-1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f"
.text
.globl _Z11Read_matrixPfi
.type _Z11Read_matrixPfi, @function
_Z11Read_matrixPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L3
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L5:
leaq 0(%rbp,%r14), %rbx
.L6:
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11Read_matrixPfi, .-_Z11Read_matrixPfi
.section .rodata.str1.1
.LC1:
.string "%s\n"
.LC2:
.string "%.1f "
.LC3:
.string "\n"
.text
.globl _Z12Print_matrixPcPfi
.type _Z12Print_matrixPcPfi, @function
_Z12Print_matrixPcPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movl %edx, %ebx
movl %edx, 12(%rsp)
movq %rdi, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L9
movslq %ebx, %r14
leaq 0(,%r14,4), %r15
addq %r15, %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC2(%rip), %r12
.L11:
leaq 0(%rbp,%r14), %rbx
.L12:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L11
.L9:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12Print_matrixPcPfi, .-_Z12Print_matrixPcPfi
.globl _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
.globl _Z9matrixAddPfS_S_i
.type _Z9matrixAddPfS_S_i, @function
_Z9matrixAddPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9matrixAddPfS_S_i, .-_Z9matrixAddPfS_S_i
.section .rodata.str1.1
.LC4:
.string "size = %d"
.LC5:
.string "Matriz A: \n"
.LC6:
.string "Matriz B: \n"
.LC7:
.string "A ="
.LC8:
.string "B ="
.LC9:
.string "Result ="
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r12d
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %ebx
imull %ebp, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %esi
movq %r14, %rdi
call _Z11Read_matrixPfi
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %esi
movq %r13, %rdi
call _Z11Read_matrixPfi
movl %ebp, %edx
movq %r14, %rsi
leaq .LC7(%rip), %rdi
call _Z12Print_matrixPcPfi
movl %ebp, %edx
movq %r13, %rsi
leaq .LC8(%rip), %rdi
call _Z12Print_matrixPcPfi
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L24:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %r12d, %edx
movq %r15, %rsi
leaq .LC9(%rip), %rdi
call _Z12Print_matrixPcPfi
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
jmp .L24
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.globl _Z37__device_stub__Z12matrixAddRowPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12matrixAddRowPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12matrixAddRowPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matrixAddRowPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z37__device_stub__Z12matrixAddRowPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12matrixAddRowPfS_S_iPfS_S_i
.globl _Z12matrixAddRowPfS_S_i
.type _Z12matrixAddRowPfS_S_i, @function
_Z12matrixAddRowPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12matrixAddRowPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z12matrixAddRowPfS_S_i, .-_Z12matrixAddRowPfS_S_i
.globl _Z40__device_stub__Z15matrixAddColumnPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15matrixAddColumnPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15matrixAddColumnPfS_S_iPfS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixAddColumnPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z40__device_stub__Z15matrixAddColumnPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15matrixAddColumnPfS_S_iPfS_S_i
.globl _Z15matrixAddColumnPfS_S_i
.type _Z15matrixAddColumnPfS_S_i, @function
_Z15matrixAddColumnPfS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrixAddColumnPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z15matrixAddColumnPfS_S_i, .-_Z15matrixAddColumnPfS_S_i
.section .rodata.str1.1
.LC10:
.string "_Z15matrixAddColumnPfS_S_i"
.LC11:
.string "_Z12matrixAddRowPfS_S_i"
.LC12:
.string "_Z9matrixAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixAddColumnPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matrixAddRowPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Compile: nvcc [-g] [-G] -arch=sm_21 -o mat_add mat_add.cu
* Run: ./mat_add <m> <n>
* m is the number of rows
* n is the number of columns
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define BLOCK_DIM 512
/*
[1 1 1]
[1 1 1] => [1 1 1][1 1 1][1 1 1]
[1 1 1]
*/
/*Kernel*/
__global__ void matrixAdd(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (blockIdx.x < N && threadIdx.x < N)
c[index] = a[index] + b[index];
}
__global__ void matrixAddRow(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
for(index = index * N; index < N*N; index++)
{
c[index] = a[index] + b[index];
}
}
__global__ void matrixAddColumn(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
for(; index < N*N; index = index + N)
{
c[index] = a[index] + b[index];
}
}
void Read_matrix(float A[], int s) {
int i, j;
for (i = 0; i < s; i++)
for (j = 0; j < s; j++)
scanf("%f", &A[i*s+j]);
}
void Print_matrix(char name[], float A[], int s) {
int i, j;
printf("%s\n", name);
for (i = 0; i < s; i++) {
for (j = 0; j < s; j++)
printf("%.1f ", A[i*s+j]);
printf("\n");
}
}
/* Host */
int main(int argc, char* argv[]) {
int N;
int size;
float *dev_a, *dev_b, *dev_c;
float *a, *b, *c;
N = strtol(argv[1], NULL, 10);
printf("size = %d", N);
size = N*N*sizeof(float);
a = (float*) malloc(size);
b = (float*) malloc(size);
c = (float*) malloc(size);
printf("Matriz A: \n");
Read_matrix(a, N);
printf("Matriz B: \n");
Read_matrix(b, N);
Print_matrix("A =", a, N);
Print_matrix("B =", b, N);
cudaMalloc(&dev_a, size);
cudaMalloc(&dev_b, size);
cudaMalloc(&dev_c, size);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
// dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
// dim3 dimGrid((int)ceil(N/dimBlock.x),(int)ceil(N/dimBlock.y));
// matrixAddColumn<<<N,N>>>(dev_a,dev_b,dev_c,N);
// matrixAddRow<<<N,N>>>(dev_a,dev_b,dev_c,N);
matrixAdd<<<N,N>>>(dev_a,dev_b,dev_c,N);
cudaThreadSynchronize();
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
Print_matrix("Result =", c, N);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
free(a);
free(b);
free(c);
return 0;
} | /*
* Compile: nvcc [-g] [-G] -arch=sm_21 -o mat_add mat_add.cu
* Run: ./mat_add <m> <n>
* m is the number of rows
* n is the number of columns
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define BLOCK_DIM 512
/*
[1 1 1]
[1 1 1] => [1 1 1][1 1 1][1 1 1]
[1 1 1]
*/
/*Kernel*/
__global__ void matrixAdd(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (blockIdx.x < N && threadIdx.x < N)
c[index] = a[index] + b[index];
}
__global__ void matrixAddRow(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
for(index = index * N; index < N*N; index++)
{
c[index] = a[index] + b[index];
}
}
__global__ void matrixAddColumn(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
for(; index < N*N; index = index + N)
{
c[index] = a[index] + b[index];
}
}
void Read_matrix(float A[], int s) {
int i, j;
for (i = 0; i < s; i++)
for (j = 0; j < s; j++)
scanf("%f", &A[i*s+j]);
}
void Print_matrix(char name[], float A[], int s) {
int i, j;
printf("%s\n", name);
for (i = 0; i < s; i++) {
for (j = 0; j < s; j++)
printf("%.1f ", A[i*s+j]);
printf("\n");
}
}
/* Host */
int main(int argc, char* argv[]) {
int N;
int size;
float *dev_a, *dev_b, *dev_c;
float *a, *b, *c;
N = strtol(argv[1], NULL, 10);
printf("size = %d", N);
size = N*N*sizeof(float);
a = (float*) malloc(size);
b = (float*) malloc(size);
c = (float*) malloc(size);
printf("Matriz A: \n");
Read_matrix(a, N);
printf("Matriz B: \n");
Read_matrix(b, N);
Print_matrix("A =", a, N);
Print_matrix("B =", b, N);
hipMalloc(&dev_a, size);
hipMalloc(&dev_b, size);
hipMalloc(&dev_c, size);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
// dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
// dim3 dimGrid((int)ceil(N/dimBlock.x),(int)ceil(N/dimBlock.y));
// matrixAddColumn<<<N,N>>>(dev_a,dev_b,dev_c,N);
// matrixAddRow<<<N,N>>>(dev_a,dev_b,dev_c,N);
matrixAdd<<<N,N>>>(dev_a,dev_b,dev_c,N);
hipDeviceSynchronize();
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
Print_matrix("Result =", c, N);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
free(a);
free(b);
free(c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Compile: nvcc [-g] [-G] -arch=sm_21 -o mat_add mat_add.cu
* Run: ./mat_add <m> <n>
* m is the number of rows
* n is the number of columns
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define BLOCK_DIM 512
/*
[1 1 1]
[1 1 1] => [1 1 1][1 1 1][1 1 1]
[1 1 1]
*/
/*Kernel*/
__global__ void matrixAdd(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (blockIdx.x < N && threadIdx.x < N)
c[index] = a[index] + b[index];
}
__global__ void matrixAddRow(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
for(index = index * N; index < N*N; index++)
{
c[index] = a[index] + b[index];
}
}
__global__ void matrixAddColumn(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
for(; index < N*N; index = index + N)
{
c[index] = a[index] + b[index];
}
}
void Read_matrix(float A[], int s) {
int i, j;
for (i = 0; i < s; i++)
for (j = 0; j < s; j++)
scanf("%f", &A[i*s+j]);
}
void Print_matrix(char name[], float A[], int s) {
int i, j;
printf("%s\n", name);
for (i = 0; i < s; i++) {
for (j = 0; j < s; j++)
printf("%.1f ", A[i*s+j]);
printf("\n");
}
}
/* Host */
int main(int argc, char* argv[]) {
int N;
int size;
float *dev_a, *dev_b, *dev_c;
float *a, *b, *c;
N = strtol(argv[1], NULL, 10);
printf("size = %d", N);
size = N*N*sizeof(float);
a = (float*) malloc(size);
b = (float*) malloc(size);
c = (float*) malloc(size);
printf("Matriz A: \n");
Read_matrix(a, N);
printf("Matriz B: \n");
Read_matrix(b, N);
Print_matrix("A =", a, N);
Print_matrix("B =", b, N);
hipMalloc(&dev_a, size);
hipMalloc(&dev_b, size);
hipMalloc(&dev_c, size);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
// dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
// dim3 dimGrid((int)ceil(N/dimBlock.x),(int)ceil(N/dimBlock.y));
// matrixAddColumn<<<N,N>>>(dev_a,dev_b,dev_c,N);
// matrixAddRow<<<N,N>>>(dev_a,dev_b,dev_c,N);
matrixAdd<<<N,N>>>(dev_a,dev_b,dev_c,N);
hipDeviceSynchronize();
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
Print_matrix("Result =", c, N);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
free(a);
free(b);
free(c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixAddPfS_S_i
.globl _Z9matrixAddPfS_S_i
.p2align 8
.type _Z9matrixAddPfS_S_i,@function
_Z9matrixAddPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_max_u32_e32 v1, s15, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixAddPfS_S_i, .Lfunc_end0-_Z9matrixAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12matrixAddRowPfS_S_i
.globl _Z12matrixAddRowPfS_S_i
.p2align 8
.type _Z12matrixAddRowPfS_S_i,@function
_Z12matrixAddRowPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s3, s3
v_mul_lo_u32 v0, v1, s3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB1_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_mov_b32 s1, 0
.p2align 6
.LBB1_2:
global_load_b32 v7, v[1:2], off
global_load_b32 v8, v[3:4], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_nc_u32_e32 v0, 1, v0
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_cmp_le_i32_e32 vcc_lo, s2, v0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v7, v7, v8
global_store_b32 v[5:6], v7, off
v_add_co_u32 v5, s0, v5, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matrixAddRowPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12matrixAddRowPfS_S_i, .Lfunc_end1-_Z12matrixAddRowPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15matrixAddColumnPfS_S_i
.globl _Z15matrixAddColumnPfS_S_i
.p2align 8
.type _Z15matrixAddColumnPfS_S_i,@function
_Z15matrixAddColumnPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_mul_i32 s12, s2, s2
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB2_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s3, s2, 31
s_mov_b32 s1, 0
s_lshl_b64 s[10:11], s[2:3], 2
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
.p2align 6
.LBB2_2:
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v4, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixAddColumnPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15matrixAddColumnPfS_S_i, .Lfunc_end2-_Z15matrixAddColumnPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matrixAddRowPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matrixAddRowPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixAddColumnPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixAddColumnPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Compile: nvcc [-g] [-G] -arch=sm_21 -o mat_add mat_add.cu
* Run: ./mat_add <m> <n>
* m is the number of rows
* n is the number of columns
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define BLOCK_DIM 512
/*
[1 1 1]
[1 1 1] => [1 1 1][1 1 1][1 1 1]
[1 1 1]
*/
/*Kernel*/
__global__ void matrixAdd(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (blockIdx.x < N && threadIdx.x < N)
c[index] = a[index] + b[index];
}
__global__ void matrixAddRow(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
for(index = index * N; index < N*N; index++)
{
c[index] = a[index] + b[index];
}
}
__global__ void matrixAddColumn(float a[], float b[], float c[], int N) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
for(; index < N*N; index = index + N)
{
c[index] = a[index] + b[index];
}
}
void Read_matrix(float A[], int s) {
int i, j;
for (i = 0; i < s; i++)
for (j = 0; j < s; j++)
scanf("%f", &A[i*s+j]);
}
void Print_matrix(char name[], float A[], int s) {
int i, j;
printf("%s\n", name);
for (i = 0; i < s; i++) {
for (j = 0; j < s; j++)
printf("%.1f ", A[i*s+j]);
printf("\n");
}
}
/* Host */
int main(int argc, char* argv[]) {
int N;
int size;
float *dev_a, *dev_b, *dev_c;
float *a, *b, *c;
N = strtol(argv[1], NULL, 10);
printf("size = %d", N);
size = N*N*sizeof(float);
a = (float*) malloc(size);
b = (float*) malloc(size);
c = (float*) malloc(size);
printf("Matriz A: \n");
Read_matrix(a, N);
printf("Matriz B: \n");
Read_matrix(b, N);
Print_matrix("A =", a, N);
Print_matrix("B =", b, N);
hipMalloc(&dev_a, size);
hipMalloc(&dev_b, size);
hipMalloc(&dev_c, size);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
// dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
// dim3 dimGrid((int)ceil(N/dimBlock.x),(int)ceil(N/dimBlock.y));
// matrixAddColumn<<<N,N>>>(dev_a,dev_b,dev_c,N);
// matrixAddRow<<<N,N>>>(dev_a,dev_b,dev_c,N);
matrixAdd<<<N,N>>>(dev_a,dev_b,dev_c,N);
hipDeviceSynchronize();
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
Print_matrix("Result =", c, N);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
free(a);
free(b);
free(c);
return 0;
} | .text
.file "cap-3-1.hip"
.globl _Z24__device_stub__matrixAddPfS_S_i # -- Begin function _Z24__device_stub__matrixAddPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matrixAddPfS_S_i,@function
_Z24__device_stub__matrixAddPfS_S_i: # @_Z24__device_stub__matrixAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixAddPfS_S_i, .Lfunc_end0-_Z24__device_stub__matrixAddPfS_S_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__matrixAddRowPfS_S_i # -- Begin function _Z27__device_stub__matrixAddRowPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__matrixAddRowPfS_S_i,@function
_Z27__device_stub__matrixAddRowPfS_S_i: # @_Z27__device_stub__matrixAddRowPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matrixAddRowPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__matrixAddRowPfS_S_i, .Lfunc_end1-_Z27__device_stub__matrixAddRowPfS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixAddColumnPfS_S_i # -- Begin function _Z30__device_stub__matrixAddColumnPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixAddColumnPfS_S_i,@function
_Z30__device_stub__matrixAddColumnPfS_S_i: # @_Z30__device_stub__matrixAddColumnPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixAddColumnPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z30__device_stub__matrixAddColumnPfS_S_i, .Lfunc_end2-_Z30__device_stub__matrixAddColumnPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11Read_matrixPfi # -- Begin function _Z11Read_matrixPfi
.p2align 4, 0x90
.type _Z11Read_matrixPfi,@function
_Z11Read_matrixPfi: # @_Z11Read_matrixPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r14d
xorl %ebp, %ebp
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
movq %r14, %r12
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %r15
decq %r12
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r13
addl %ebx, %ebp
cmpq %r14, %r13
jne .LBB3_2
.LBB3_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11Read_matrixPfi, .Lfunc_end3-_Z11Read_matrixPfi
.cfi_endproc
# -- End function
.globl _Z12Print_matrixPcPfi # -- Begin function _Z12Print_matrixPcPfi
.p2align 4, 0x90
.type _Z12Print_matrixPcPfi,@function
_Z12Print_matrixPcPfi: # @_Z12Print_matrixPcPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rsi, (%rsp) # 8-byte Spill
callq puts@PLT
testl %ebx, %ebx
jle .LBB4_5
# %bb.1: # %.preheader.lr.ph
movl %ebx, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB4_2
.LBB4_5: # %._crit_edge14
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z12Print_matrixPcPfi, .Lfunc_end4-_Z12Print_matrixPcPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $.L.str.4, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl %ebx, %eax
imull %ebx, %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %r14, 64(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movl $.Lstr, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB5_10
# %bb.1: # %.preheader.lr.ph.i
movl %ebx, %r14d
xorl %r12d, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
movl %r12d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
movq %r14, %r13
.p2align 4, 0x90
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbp
decq %r13
jne .LBB5_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB5_2 Depth=1
incq %r15
addl %ebx, %r12d
cmpq %r14, %r15
jne .LBB5_2
# %bb.5: # %_Z11Read_matrixPfi.exit
movl $.Lstr.1, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB5_16
# %bb.6: # %.preheader.lr.ph.i34
movl %ebx, %r13d
xorl %r12d, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_7: # %.preheader.i36
# =>This Loop Header: Depth=1
# Child Loop BB5_8 Depth 2
movl %r12d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
movq %r13, %r14
.p2align 4, 0x90
.LBB5_8: # Parent Loop BB5_7 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbp
decq %r14
jne .LBB5_8
# %bb.9: # %._crit_edge.i42
# in Loop: Header=BB5_7 Depth=1
incq %r15
addl %ebx, %r12d
cmpq %r13, %r15
jne .LBB5_7
jmp .LBB5_11
.LBB5_10: # %_Z11Read_matrixPfi.exit45.critedge
movl $.Lstr.1, %edi
callq puts@PLT
.LBB5_11: # %_Z11Read_matrixPfi.exit45
movl $.L.str.7, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB5_22
# %bb.12: # %.preheader.lr.ph.i46
movl %ebx, %ebp
xorl %r13d, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_13: # %.preheader.i47
# =>This Loop Header: Depth=1
# Child Loop BB5_14 Depth 2
movl %r13d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_14: # Parent Loop BB5_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %rbp
jne .LBB5_14
# %bb.15: # %._crit_edge.i52
# in Loop: Header=BB5_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebx, %r13d
cmpq %rbp, %r12
jne .LBB5_13
jmp .LBB5_17
.LBB5_22: # %_Z12Print_matrixPcPfi.exit66.critedge
movl $.L.str.8, %edi
callq puts@PLT
jmp .LBB5_23
.LBB5_16: # %_Z12Print_matrixPcPfi.exit.critedge
movl $.L.str.7, %edi
callq puts@PLT
.LBB5_17: # %_Z12Print_matrixPcPfi.exit
movl $.L.str.8, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB5_23
# %bb.18: # %.preheader.lr.ph.i54
movl %ebx, %ebp
xorl %r13d, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_19: # %.preheader.i56
# =>This Loop Header: Depth=1
# Child Loop BB5_20 Depth 2
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_20: # Parent Loop BB5_19 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %rbp
jne .LBB5_20
# %bb.21: # %._crit_edge.i62
# in Loop: Header=BB5_19 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebx, %r13d
cmpq %rbp, %r12
jne .LBB5_19
.LBB5_23: # %_Z12Print_matrixPcPfi.exit66
leaq 48(%rsp), %rdi
movq 64(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebx, %ebp
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rbp, %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_25
# %bb.24:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %ebx, 60(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z9matrixAddPfS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_25:
callq hipDeviceSynchronize
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.9, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB5_30
# %bb.26: # %.preheader.i70.preheader
xorl %r13d, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_27: # %.preheader.i70
# =>This Loop Header: Depth=1
# Child Loop BB5_28 Depth 2
movl %r13d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_28: # Parent Loop BB5_27 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %rbp
jne .LBB5_28
# %bb.29: # %._crit_edge.i76
# in Loop: Header=BB5_27 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebx, %r13d
cmpq %rbp, %r12
jne .LBB5_27
.LBB5_30: # %_Z12Print_matrixPcPfi.exit80
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matrixAddRowPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixAddColumnPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixAddPfS_S_i,@object # @_Z9matrixAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9matrixAddPfS_S_i
.p2align 3, 0x0
_Z9matrixAddPfS_S_i:
.quad _Z24__device_stub__matrixAddPfS_S_i
.size _Z9matrixAddPfS_S_i, 8
.type _Z12matrixAddRowPfS_S_i,@object # @_Z12matrixAddRowPfS_S_i
.globl _Z12matrixAddRowPfS_S_i
.p2align 3, 0x0
_Z12matrixAddRowPfS_S_i:
.quad _Z27__device_stub__matrixAddRowPfS_S_i
.size _Z12matrixAddRowPfS_S_i, 8
.type _Z15matrixAddColumnPfS_S_i,@object # @_Z15matrixAddColumnPfS_S_i
.globl _Z15matrixAddColumnPfS_S_i
.p2align 3, 0x0
_Z15matrixAddColumnPfS_S_i:
.quad _Z30__device_stub__matrixAddColumnPfS_S_i
.size _Z15matrixAddColumnPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%.1f "
.size .L.str.2, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "size = %d"
.size .L.str.4, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "A ="
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "B ="
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Result ="
.size .L.str.9, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixAddPfS_S_i"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12matrixAddRowPfS_S_i"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15matrixAddColumnPfS_S_i"
.size .L__unnamed_3, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matriz A: "
.size .Lstr, 11
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Matriz B: "
.size .Lstr.1, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixAddPfS_S_i
.addrsig_sym _Z27__device_stub__matrixAddRowPfS_S_i
.addrsig_sym _Z30__device_stub__matrixAddColumnPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixAddPfS_S_i
.addrsig_sym _Z12matrixAddRowPfS_S_i
.addrsig_sym _Z15matrixAddColumnPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a17f9_00000000-6_cap-3-1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f"
.text
.globl _Z11Read_matrixPfi
.type _Z11Read_matrixPfi, @function
_Z11Read_matrixPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L3
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L5:
leaq 0(%rbp,%r14), %rbx
.L6:
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11Read_matrixPfi, .-_Z11Read_matrixPfi
.section .rodata.str1.1
.LC1:
.string "%s\n"
.LC2:
.string "%.1f "
.LC3:
.string "\n"
.text
.globl _Z12Print_matrixPcPfi
.type _Z12Print_matrixPcPfi, @function
_Z12Print_matrixPcPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movl %edx, %ebx
movl %edx, 12(%rsp)
movq %rdi, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L9
movslq %ebx, %r14
leaq 0(,%r14,4), %r15
addq %r15, %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC2(%rip), %r12
.L11:
leaq 0(%rbp,%r14), %rbx
.L12:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L11
.L9:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12Print_matrixPcPfi, .-_Z12Print_matrixPcPfi
.globl _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
.globl _Z9matrixAddPfS_S_i
.type _Z9matrixAddPfS_S_i, @function
_Z9matrixAddPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9matrixAddPfS_S_i, .-_Z9matrixAddPfS_S_i
.section .rodata.str1.1
.LC4:
.string "size = %d"
.LC5:
.string "Matriz A: \n"
.LC6:
.string "Matriz B: \n"
.LC7:
.string "A ="
.LC8:
.string "B ="
.LC9:
.string "Result ="
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r12d
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %ebx
imull %ebp, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %esi
movq %r14, %rdi
call _Z11Read_matrixPfi
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %esi
movq %r13, %rdi
call _Z11Read_matrixPfi
movl %ebp, %edx
movq %r14, %rsi
leaq .LC7(%rip), %rdi
call _Z12Print_matrixPcPfi
movl %ebp, %edx
movq %r13, %rsi
leaq .LC8(%rip), %rdi
call _Z12Print_matrixPcPfi
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L24:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %r12d, %edx
movq %r15, %rsi
leaq .LC9(%rip), %rdi
call _Z12Print_matrixPcPfi
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
jmp .L24
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.globl _Z37__device_stub__Z12matrixAddRowPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12matrixAddRowPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12matrixAddRowPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matrixAddRowPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z37__device_stub__Z12matrixAddRowPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12matrixAddRowPfS_S_iPfS_S_i
.globl _Z12matrixAddRowPfS_S_i
.type _Z12matrixAddRowPfS_S_i, @function
_Z12matrixAddRowPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12matrixAddRowPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z12matrixAddRowPfS_S_i, .-_Z12matrixAddRowPfS_S_i
.globl _Z40__device_stub__Z15matrixAddColumnPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15matrixAddColumnPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15matrixAddColumnPfS_S_iPfS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixAddColumnPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z40__device_stub__Z15matrixAddColumnPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15matrixAddColumnPfS_S_iPfS_S_i
.globl _Z15matrixAddColumnPfS_S_i
.type _Z15matrixAddColumnPfS_S_i, @function
_Z15matrixAddColumnPfS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrixAddColumnPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z15matrixAddColumnPfS_S_i, .-_Z15matrixAddColumnPfS_S_i
.section .rodata.str1.1
.LC10:
.string "_Z15matrixAddColumnPfS_S_i"
.LC11:
.string "_Z12matrixAddRowPfS_S_i"
.LC12:
.string "_Z9matrixAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixAddColumnPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matrixAddRowPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cap-3-1.hip"
.globl _Z24__device_stub__matrixAddPfS_S_i # -- Begin function _Z24__device_stub__matrixAddPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matrixAddPfS_S_i,@function
_Z24__device_stub__matrixAddPfS_S_i: # @_Z24__device_stub__matrixAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixAddPfS_S_i, .Lfunc_end0-_Z24__device_stub__matrixAddPfS_S_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__matrixAddRowPfS_S_i # -- Begin function _Z27__device_stub__matrixAddRowPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__matrixAddRowPfS_S_i,@function
_Z27__device_stub__matrixAddRowPfS_S_i: # @_Z27__device_stub__matrixAddRowPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matrixAddRowPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__matrixAddRowPfS_S_i, .Lfunc_end1-_Z27__device_stub__matrixAddRowPfS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixAddColumnPfS_S_i # -- Begin function _Z30__device_stub__matrixAddColumnPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixAddColumnPfS_S_i,@function
_Z30__device_stub__matrixAddColumnPfS_S_i: # @_Z30__device_stub__matrixAddColumnPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixAddColumnPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z30__device_stub__matrixAddColumnPfS_S_i, .Lfunc_end2-_Z30__device_stub__matrixAddColumnPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11Read_matrixPfi # -- Begin function _Z11Read_matrixPfi
.p2align 4, 0x90
.type _Z11Read_matrixPfi,@function
_Z11Read_matrixPfi: # @_Z11Read_matrixPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r14d
xorl %ebp, %ebp
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
movq %r14, %r12
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %r15
decq %r12
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r13
addl %ebx, %ebp
cmpq %r14, %r13
jne .LBB3_2
.LBB3_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11Read_matrixPfi, .Lfunc_end3-_Z11Read_matrixPfi
.cfi_endproc
# -- End function
.globl _Z12Print_matrixPcPfi # -- Begin function _Z12Print_matrixPcPfi
.p2align 4, 0x90
.type _Z12Print_matrixPcPfi,@function
_Z12Print_matrixPcPfi: # @_Z12Print_matrixPcPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rsi, (%rsp) # 8-byte Spill
callq puts@PLT
testl %ebx, %ebx
jle .LBB4_5
# %bb.1: # %.preheader.lr.ph
movl %ebx, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB4_2
.LBB4_5: # %._crit_edge14
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z12Print_matrixPcPfi, .Lfunc_end4-_Z12Print_matrixPcPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $.L.str.4, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl %ebx, %eax
imull %ebx, %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %r14, 64(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movl $.Lstr, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB5_10
# %bb.1: # %.preheader.lr.ph.i
movl %ebx, %r14d
xorl %r12d, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
movl %r12d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
movq %r14, %r13
.p2align 4, 0x90
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbp
decq %r13
jne .LBB5_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB5_2 Depth=1
incq %r15
addl %ebx, %r12d
cmpq %r14, %r15
jne .LBB5_2
# %bb.5: # %_Z11Read_matrixPfi.exit
movl $.Lstr.1, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB5_16
# %bb.6: # %.preheader.lr.ph.i34
movl %ebx, %r13d
xorl %r12d, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_7: # %.preheader.i36
# =>This Loop Header: Depth=1
# Child Loop BB5_8 Depth 2
movl %r12d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
movq %r13, %r14
.p2align 4, 0x90
.LBB5_8: # Parent Loop BB5_7 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbp
decq %r14
jne .LBB5_8
# %bb.9: # %._crit_edge.i42
# in Loop: Header=BB5_7 Depth=1
incq %r15
addl %ebx, %r12d
cmpq %r13, %r15
jne .LBB5_7
jmp .LBB5_11
.LBB5_10: # %_Z11Read_matrixPfi.exit45.critedge
movl $.Lstr.1, %edi
callq puts@PLT
.LBB5_11: # %_Z11Read_matrixPfi.exit45
movl $.L.str.7, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB5_22
# %bb.12: # %.preheader.lr.ph.i46
movl %ebx, %ebp
xorl %r13d, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_13: # %.preheader.i47
# =>This Loop Header: Depth=1
# Child Loop BB5_14 Depth 2
movl %r13d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_14: # Parent Loop BB5_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %rbp
jne .LBB5_14
# %bb.15: # %._crit_edge.i52
# in Loop: Header=BB5_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebx, %r13d
cmpq %rbp, %r12
jne .LBB5_13
jmp .LBB5_17
.LBB5_22: # %_Z12Print_matrixPcPfi.exit66.critedge
movl $.L.str.8, %edi
callq puts@PLT
jmp .LBB5_23
.LBB5_16: # %_Z12Print_matrixPcPfi.exit.critedge
movl $.L.str.7, %edi
callq puts@PLT
.LBB5_17: # %_Z12Print_matrixPcPfi.exit
movl $.L.str.8, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB5_23
# %bb.18: # %.preheader.lr.ph.i54
movl %ebx, %ebp
xorl %r13d, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_19: # %.preheader.i56
# =>This Loop Header: Depth=1
# Child Loop BB5_20 Depth 2
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_20: # Parent Loop BB5_19 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %rbp
jne .LBB5_20
# %bb.21: # %._crit_edge.i62
# in Loop: Header=BB5_19 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebx, %r13d
cmpq %rbp, %r12
jne .LBB5_19
.LBB5_23: # %_Z12Print_matrixPcPfi.exit66
leaq 48(%rsp), %rdi
movq 64(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebx, %ebp
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rbp, %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_25
# %bb.24:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %ebx, 60(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z9matrixAddPfS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_25:
callq hipDeviceSynchronize
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.9, %edi
callq puts@PLT
testl %ebx, %ebx
jle .LBB5_30
# %bb.26: # %.preheader.i70.preheader
xorl %r13d, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_27: # %.preheader.i70
# =>This Loop Header: Depth=1
# Child Loop BB5_28 Depth 2
movl %r13d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_28: # Parent Loop BB5_27 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %rbp
jne .LBB5_28
# %bb.29: # %._crit_edge.i76
# in Loop: Header=BB5_27 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebx, %r13d
cmpq %rbp, %r12
jne .LBB5_27
.LBB5_30: # %_Z12Print_matrixPcPfi.exit80
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matrixAddRowPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixAddColumnPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixAddPfS_S_i,@object # @_Z9matrixAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9matrixAddPfS_S_i
.p2align 3, 0x0
_Z9matrixAddPfS_S_i:
.quad _Z24__device_stub__matrixAddPfS_S_i
.size _Z9matrixAddPfS_S_i, 8
.type _Z12matrixAddRowPfS_S_i,@object # @_Z12matrixAddRowPfS_S_i
.globl _Z12matrixAddRowPfS_S_i
.p2align 3, 0x0
_Z12matrixAddRowPfS_S_i:
.quad _Z27__device_stub__matrixAddRowPfS_S_i
.size _Z12matrixAddRowPfS_S_i, 8
.type _Z15matrixAddColumnPfS_S_i,@object # @_Z15matrixAddColumnPfS_S_i
.globl _Z15matrixAddColumnPfS_S_i
.p2align 3, 0x0
_Z15matrixAddColumnPfS_S_i:
.quad _Z30__device_stub__matrixAddColumnPfS_S_i
.size _Z15matrixAddColumnPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%.1f "
.size .L.str.2, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "size = %d"
.size .L.str.4, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "A ="
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "B ="
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Result ="
.size .L.str.9, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixAddPfS_S_i"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12matrixAddRowPfS_S_i"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15matrixAddColumnPfS_S_i"
.size .L__unnamed_3, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matriz A: "
.size .Lstr, 11
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Matriz B: "
.size .Lstr.1, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixAddPfS_S_i
.addrsig_sym _Z27__device_stub__matrixAddRowPfS_S_i
.addrsig_sym _Z30__device_stub__matrixAddColumnPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixAddPfS_S_i
.addrsig_sym _Z12matrixAddRowPfS_S_i
.addrsig_sym _Z15matrixAddColumnPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define T 16 // As Threads
#define array_size 64
__global__ void vecMultiplyReverse(int *A, int *B, int *C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i%2 == 0)
{
C[i] = A[i] + B[i];
}
else if(i%2 != 0)
{
C[i] = A[i] - B[i];
}
}
int main (int argc, char *argv[])
{
int i;
int size = T*sizeof(int);
int a[T],b[T],c[T], *devA,*devB,*devC;
for (i=0; i< T; i++)
{
a[i] = i + 2;
b[i] = i + 1;
}
cudaMalloc( (void**)&devA,size);
cudaMalloc( (void**)&devB,size);
cudaMalloc( (void**)&devC,size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
cudaMemcpy( devB, b, size, cudaMemcpyHostToDevice);
cudaMemcpy( devC, c, size, cudaMemcpyHostToDevice);
dim3 dimBlock(T);
dim3 dimGrid(array_size/T - 1);
vecMultiplyReverse<<<dimGrid,dimBlock>>>(devA,devB,devC);
printf("Before A: \n");
for (i=0; i< T; i++)
{
printf("%d ", a[i]);
}
printf("\n");
printf("Before B: \n");
for (i=0; i< T; i++)
{
printf("%d ", b[i]);
}
printf("\n");
cudaMemcpy(a, devA, size, cudaMemcpyDeviceToHost);
cudaMemcpy(b, devB, size, cudaMemcpyDeviceToHost);
cudaMemcpy(c, devC, size, cudaMemcpyDeviceToHost);
cudaFree(devA);
cudaFree(devB);
cudaFree(devC);
printf("After\n");
for (i=0; i < T; i++)
{
printf("%d ",c[i]);
}
printf("\n");
return 0;
} | code for sm_80
Function : _Z18vecMultiplyReversePiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe200078e0207 */
/*0080*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000eaa000c1e1900 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*00a0*/ LOP3.LUT R0, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106007812 */
/* 0x040fe200078ec0ff */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc600078e0207 */
/*00c0*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*00d0*/ @!P0 IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09098210 */
/* 0x004fc80007ffe1ff */
/*00e0*/ IADD3 R9, R2, R9, RZ ; /* 0x0000000902097210 */
/* 0x008fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define T 16 // As Threads
#define array_size 64
__global__ void vecMultiplyReverse(int *A, int *B, int *C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i%2 == 0)
{
C[i] = A[i] + B[i];
}
else if(i%2 != 0)
{
C[i] = A[i] - B[i];
}
}
int main (int argc, char *argv[])
{
int i;
int size = T*sizeof(int);
int a[T],b[T],c[T], *devA,*devB,*devC;
for (i=0; i< T; i++)
{
a[i] = i + 2;
b[i] = i + 1;
}
cudaMalloc( (void**)&devA,size);
cudaMalloc( (void**)&devB,size);
cudaMalloc( (void**)&devC,size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
cudaMemcpy( devB, b, size, cudaMemcpyHostToDevice);
cudaMemcpy( devC, c, size, cudaMemcpyHostToDevice);
dim3 dimBlock(T);
dim3 dimGrid(array_size/T - 1);
vecMultiplyReverse<<<dimGrid,dimBlock>>>(devA,devB,devC);
printf("Before A: \n");
for (i=0; i< T; i++)
{
printf("%d ", a[i]);
}
printf("\n");
printf("Before B: \n");
for (i=0; i< T; i++)
{
printf("%d ", b[i]);
}
printf("\n");
cudaMemcpy(a, devA, size, cudaMemcpyDeviceToHost);
cudaMemcpy(b, devB, size, cudaMemcpyDeviceToHost);
cudaMemcpy(c, devC, size, cudaMemcpyDeviceToHost);
cudaFree(devA);
cudaFree(devB);
cudaFree(devC);
printf("After\n");
for (i=0; i < T; i++)
{
printf("%d ",c[i]);
}
printf("\n");
return 0;
} | .file "tmpxft_0019c662_00000000-6_cuda3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
.type _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_, @function
_Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18vecMultiplyReversePiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_, .-_Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
.globl _Z18vecMultiplyReversePiS_S_
.type _Z18vecMultiplyReversePiS_S_, @function
_Z18vecMultiplyReversePiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z18vecMultiplyReversePiS_S_, .-_Z18vecMultiplyReversePiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Before A: \n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "Before B: \n"
.LC4:
.string "After\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $256, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movl $1, %eax
.L12:
leal 1(%rax), %edx
movl %edx, 44(%rsp,%rax,4)
movl %eax, 108(%rsp,%rax,4)
addq $1, %rax
cmpq $17, %rax
jne .L12
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 176(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $3, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rbx
leaq 112(%rsp), %r12
leaq .LC1(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 112(%rsp), %rbx
leaq 176(%rsp), %r12
leaq .LC1(%rip), %rbp
.L15:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq 176(%rsp), %rbx
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 240(%rsp), %r12
leaq .LC1(%rip), %rbp
.L16:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L16
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
jmp .L13
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z18vecMultiplyReversePiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z18vecMultiplyReversePiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define T 16 // As Threads
#define array_size 64
__global__ void vecMultiplyReverse(int *A, int *B, int *C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i%2 == 0)
{
C[i] = A[i] + B[i];
}
else if(i%2 != 0)
{
C[i] = A[i] - B[i];
}
}
int main (int argc, char *argv[])
{
int i;
int size = T*sizeof(int);
int a[T],b[T],c[T], *devA,*devB,*devC;
for (i=0; i< T; i++)
{
a[i] = i + 2;
b[i] = i + 1;
}
cudaMalloc( (void**)&devA,size);
cudaMalloc( (void**)&devB,size);
cudaMalloc( (void**)&devC,size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
cudaMemcpy( devB, b, size, cudaMemcpyHostToDevice);
cudaMemcpy( devC, c, size, cudaMemcpyHostToDevice);
dim3 dimBlock(T);
dim3 dimGrid(array_size/T - 1);
vecMultiplyReverse<<<dimGrid,dimBlock>>>(devA,devB,devC);
printf("Before A: \n");
for (i=0; i< T; i++)
{
printf("%d ", a[i]);
}
printf("\n");
printf("Before B: \n");
for (i=0; i< T; i++)
{
printf("%d ", b[i]);
}
printf("\n");
cudaMemcpy(a, devA, size, cudaMemcpyDeviceToHost);
cudaMemcpy(b, devB, size, cudaMemcpyDeviceToHost);
cudaMemcpy(c, devC, size, cudaMemcpyDeviceToHost);
cudaFree(devA);
cudaFree(devB);
cudaFree(devC);
printf("After\n");
for (i=0; i < T; i++)
{
printf("%d ",c[i]);
}
printf("\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define T 16 // As Threads
#define array_size 64
__global__ void vecMultiplyReverse(int *A, int *B, int *C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i%2 == 0)
{
C[i] = A[i] + B[i];
}
else if(i%2 != 0)
{
C[i] = A[i] - B[i];
}
}
int main (int argc, char *argv[])
{
int i;
int size = T*sizeof(int);
int a[T],b[T],c[T], *devA,*devB,*devC;
for (i=0; i< T; i++)
{
a[i] = i + 2;
b[i] = i + 1;
}
hipMalloc( (void**)&devA,size);
hipMalloc( (void**)&devB,size);
hipMalloc( (void**)&devC,size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
hipMemcpy( devB, b, size, hipMemcpyHostToDevice);
hipMemcpy( devC, c, size, hipMemcpyHostToDevice);
dim3 dimBlock(T);
dim3 dimGrid(array_size/T - 1);
vecMultiplyReverse<<<dimGrid,dimBlock>>>(devA,devB,devC);
printf("Before A: \n");
for (i=0; i< T; i++)
{
printf("%d ", a[i]);
}
printf("\n");
printf("Before B: \n");
for (i=0; i< T; i++)
{
printf("%d ", b[i]);
}
printf("\n");
hipMemcpy(a, devA, size, hipMemcpyDeviceToHost);
hipMemcpy(b, devB, size, hipMemcpyDeviceToHost);
hipMemcpy(c, devC, size, hipMemcpyDeviceToHost);
hipFree(devA);
hipFree(devB);
hipFree(devC);
printf("After\n");
for (i=0; i < T; i++)
{
printf("%d ",c[i]);
}
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define T 16 // As Threads
#define array_size 64
__global__ void vecMultiplyReverse(int *A, int *B, int *C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i%2 == 0)
{
C[i] = A[i] + B[i];
}
else if(i%2 != 0)
{
C[i] = A[i] - B[i];
}
}
int main (int argc, char *argv[])
{
int i;
int size = T*sizeof(int);
int a[T],b[T],c[T], *devA,*devB,*devC;
for (i=0; i< T; i++)
{
a[i] = i + 2;
b[i] = i + 1;
}
hipMalloc( (void**)&devA,size);
hipMalloc( (void**)&devB,size);
hipMalloc( (void**)&devC,size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
hipMemcpy( devB, b, size, hipMemcpyHostToDevice);
hipMemcpy( devC, c, size, hipMemcpyHostToDevice);
dim3 dimBlock(T);
dim3 dimGrid(array_size/T - 1);
vecMultiplyReverse<<<dimGrid,dimBlock>>>(devA,devB,devC);
printf("Before A: \n");
for (i=0; i< T; i++)
{
printf("%d ", a[i]);
}
printf("\n");
printf("Before B: \n");
for (i=0; i< T; i++)
{
printf("%d ", b[i]);
}
printf("\n");
hipMemcpy(a, devA, size, hipMemcpyDeviceToHost);
hipMemcpy(b, devB, size, hipMemcpyDeviceToHost);
hipMemcpy(c, devC, size, hipMemcpyDeviceToHost);
hipFree(devA);
hipFree(devB);
hipFree(devC);
printf("After\n");
for (i=0; i < T; i++)
{
printf("%d ",c[i]);
}
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18vecMultiplyReversePiS_S_
.globl _Z18vecMultiplyReversePiS_S_
.p2align 8
.type _Z18vecMultiplyReversePiS_S_,@function
_Z18vecMultiplyReversePiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_and_b32_e32 v1, 1, v1
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v1
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(1)
v_sub_nc_u32_e32 v5, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v5, v0, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v4, v5
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18vecMultiplyReversePiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18vecMultiplyReversePiS_S_, .Lfunc_end0-_Z18vecMultiplyReversePiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18vecMultiplyReversePiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18vecMultiplyReversePiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define T 16 // As Threads
#define array_size 64
__global__ void vecMultiplyReverse(int *A, int *B, int *C)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i%2 == 0)
{
C[i] = A[i] + B[i];
}
else if(i%2 != 0)
{
C[i] = A[i] - B[i];
}
}
int main (int argc, char *argv[])
{
int i;
int size = T*sizeof(int);
int a[T],b[T],c[T], *devA,*devB,*devC;
for (i=0; i< T; i++)
{
a[i] = i + 2;
b[i] = i + 1;
}
hipMalloc( (void**)&devA,size);
hipMalloc( (void**)&devB,size);
hipMalloc( (void**)&devC,size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
hipMemcpy( devB, b, size, hipMemcpyHostToDevice);
hipMemcpy( devC, c, size, hipMemcpyHostToDevice);
dim3 dimBlock(T);
dim3 dimGrid(array_size/T - 1);
vecMultiplyReverse<<<dimGrid,dimBlock>>>(devA,devB,devC);
printf("Before A: \n");
for (i=0; i< T; i++)
{
printf("%d ", a[i]);
}
printf("\n");
printf("Before B: \n");
for (i=0; i< T; i++)
{
printf("%d ", b[i]);
}
printf("\n");
hipMemcpy(a, devA, size, hipMemcpyDeviceToHost);
hipMemcpy(b, devB, size, hipMemcpyDeviceToHost);
hipMemcpy(c, devC, size, hipMemcpyDeviceToHost);
hipFree(devA);
hipFree(devB);
hipFree(devC);
printf("After\n");
for (i=0; i < T; i++)
{
printf("%d ",c[i]);
}
printf("\n");
return 0;
} | .text
.file "cuda3.hip"
.globl _Z33__device_stub__vecMultiplyReversePiS_S_ # -- Begin function _Z33__device_stub__vecMultiplyReversePiS_S_
.p2align 4, 0x90
.type _Z33__device_stub__vecMultiplyReversePiS_S_,@function
_Z33__device_stub__vecMultiplyReversePiS_S_: # @_Z33__device_stub__vecMultiplyReversePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18vecMultiplyReversePiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__vecMultiplyReversePiS_S_, .Lfunc_end0-_Z33__device_stub__vecMultiplyReversePiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leal 2(%rax), %ecx
movl %ecx, 192(%rsp,%rax,4)
leaq 1(%rax), %rcx
movl %ecx, 128(%rsp,%rax,4)
movq %rcx, %rax
cmpq $16, %rcx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 256(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 13(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18vecMultiplyReversePiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 192(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 128(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rsi
leaq 192(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
leaq 256(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.Lstr.2, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl 256(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_9
# %bb.10:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18vecMultiplyReversePiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18vecMultiplyReversePiS_S_,@object # @_Z18vecMultiplyReversePiS_S_
.section .rodata,"a",@progbits
.globl _Z18vecMultiplyReversePiS_S_
.p2align 3, 0x0
_Z18vecMultiplyReversePiS_S_:
.quad _Z33__device_stub__vecMultiplyReversePiS_S_
.size _Z18vecMultiplyReversePiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18vecMultiplyReversePiS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Before A: "
.size .Lstr, 11
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Before B: "
.size .Lstr.1, 11
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "After"
.size .Lstr.2, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__vecMultiplyReversePiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18vecMultiplyReversePiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18vecMultiplyReversePiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe200078e0207 */
/*0080*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000eaa000c1e1900 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*00a0*/ LOP3.LUT R0, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106007812 */
/* 0x040fe200078ec0ff */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc600078e0207 */
/*00c0*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*00d0*/ @!P0 IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09098210 */
/* 0x004fc80007ffe1ff */
/*00e0*/ IADD3 R9, R2, R9, RZ ; /* 0x0000000902097210 */
/* 0x008fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18vecMultiplyReversePiS_S_
.globl _Z18vecMultiplyReversePiS_S_
.p2align 8
.type _Z18vecMultiplyReversePiS_S_,@function
_Z18vecMultiplyReversePiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_and_b32_e32 v1, 1, v1
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v1
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(1)
v_sub_nc_u32_e32 v5, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v5, v0, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v4, v5
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18vecMultiplyReversePiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18vecMultiplyReversePiS_S_, .Lfunc_end0-_Z18vecMultiplyReversePiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18vecMultiplyReversePiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18vecMultiplyReversePiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019c662_00000000-6_cuda3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
.type _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_, @function
_Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18vecMultiplyReversePiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_, .-_Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
.globl _Z18vecMultiplyReversePiS_S_
.type _Z18vecMultiplyReversePiS_S_, @function
_Z18vecMultiplyReversePiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z18vecMultiplyReversePiS_S_, .-_Z18vecMultiplyReversePiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Before A: \n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "Before B: \n"
.LC4:
.string "After\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $256, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movl $1, %eax
.L12:
leal 1(%rax), %edx
movl %edx, 44(%rsp,%rax,4)
movl %eax, 108(%rsp,%rax,4)
addq $1, %rax
cmpq $17, %rax
jne .L12
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 176(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $3, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rbx
leaq 112(%rsp), %r12
leaq .LC1(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 112(%rsp), %rbx
leaq 176(%rsp), %r12
leaq .LC1(%rip), %rbp
.L15:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq 176(%rsp), %rbx
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 240(%rsp), %r12
leaq .LC1(%rip), %rbp
.L16:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L16
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z42__device_stub__Z18vecMultiplyReversePiS_S_PiS_S_
jmp .L13
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z18vecMultiplyReversePiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z18vecMultiplyReversePiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda3.hip"
.globl _Z33__device_stub__vecMultiplyReversePiS_S_ # -- Begin function _Z33__device_stub__vecMultiplyReversePiS_S_
.p2align 4, 0x90
.type _Z33__device_stub__vecMultiplyReversePiS_S_,@function
_Z33__device_stub__vecMultiplyReversePiS_S_: # @_Z33__device_stub__vecMultiplyReversePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18vecMultiplyReversePiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__vecMultiplyReversePiS_S_, .Lfunc_end0-_Z33__device_stub__vecMultiplyReversePiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leal 2(%rax), %ecx
movl %ecx, 192(%rsp,%rax,4)
leaq 1(%rax), %rcx
movl %ecx, 128(%rsp,%rax,4)
movq %rcx, %rax
cmpq $16, %rcx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $64, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 256(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 13(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18vecMultiplyReversePiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 192(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 128(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rsi
leaq 192(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
leaq 256(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.Lstr.2, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl 256(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_9
# %bb.10:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18vecMultiplyReversePiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18vecMultiplyReversePiS_S_,@object # @_Z18vecMultiplyReversePiS_S_
.section .rodata,"a",@progbits
.globl _Z18vecMultiplyReversePiS_S_
.p2align 3, 0x0
_Z18vecMultiplyReversePiS_S_:
.quad _Z33__device_stub__vecMultiplyReversePiS_S_
.size _Z18vecMultiplyReversePiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18vecMultiplyReversePiS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Before A: "
.size .Lstr, 11
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Before B: "
.size .Lstr.1, 11
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "After"
.size .Lstr.2, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__vecMultiplyReversePiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18vecMultiplyReversePiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //add 2 arrays in parallel, often this is faster on CPU than GPU
//reason is computation is not intense, require more data than
//computation
#include <cstdlib>
#include <ctime>
#include <iostream>
#define BSZ 2048
#define TSZ 1024
#define TEST_SIZE BSZ * TSZ
#define TT float
#define EPS 10e-6
using namespace std;
template <typename T>
__global__ void add1d_cuda(T* c, T* a, T* b){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
c[idx] = a[idx] + b[idx];
}
template <typename T>
clock_t add1d(T* c, T* a, T* b, size_t sz){
for (size_t i = 0; i < sz; ++i)
c[i] = a[i] + b[i];
return clock();
}
template <typename T>
void random_array(T* array, size_t sz){
srand(time(0));
for (size_t i = 0; i < sz; ++i)
array[i] = (TT)rand() / 100.F;
}
int main(){
TT *a = new TT[TEST_SIZE], *b = new TT[TEST_SIZE], *c = new TT[TEST_SIZE], *d = new TT[TEST_SIZE];
TT* da, *db, *dc;
random_array(a, TEST_SIZE);
random_array(b, TEST_SIZE);
cudaMalloc((void**)&da, sizeof(TT) * TEST_SIZE);
cudaMalloc((void**)&db, sizeof(TT) * TEST_SIZE);
cudaMalloc((void**)&dc, sizeof(TT) * TEST_SIZE);
clock_t timing_start = clock();
cudaMemcpy(da, a, sizeof(TT) * TEST_SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(db, b, sizeof(TT) * TEST_SIZE, cudaMemcpyHostToDevice);
add1d_cuda<<<BSZ, TSZ>>>(dc, da, db);
cudaMemcpy(c, dc, sizeof(TT) * TEST_SIZE, cudaMemcpyDeviceToHost);
cout << "CUDA time: " << (clock() - timing_start) / (double)(CLOCKS_PER_SEC / 1000) << " ms" << endl;
cudaFree(da);
cudaFree(db);
cudaFree(dc);
timing_start = clock();
clock_t timing_end = add1d(d, a, b, TEST_SIZE);
cout << "CPU time: " << (timing_end - timing_start) / (double)(CLOCKS_PER_SEC / 1000) << " ms" << endl;
bool match = true;
for (size_t i = 0; i < TEST_SIZE; ++i)
if (c[i] - d[i] > EPS){
cout << "value does not match" << endl;
match = false;
}
if (match) cout << "All values match" << endl;
} | code for sm_80
Function : _Z10add1d_cudaIfEvPT_S1_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //add 2 arrays in parallel, often this is faster on CPU than GPU
//reason is computation is not intense, require more data than
//computation
#include <cstdlib>
#include <ctime>
#include <iostream>
#define BSZ 2048
#define TSZ 1024
#define TEST_SIZE BSZ * TSZ
#define TT float
#define EPS 10e-6
using namespace std;
template <typename T>
__global__ void add1d_cuda(T* c, T* a, T* b){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
c[idx] = a[idx] + b[idx];
}
template <typename T>
clock_t add1d(T* c, T* a, T* b, size_t sz){
for (size_t i = 0; i < sz; ++i)
c[i] = a[i] + b[i];
return clock();
}
template <typename T>
void random_array(T* array, size_t sz){
srand(time(0));
for (size_t i = 0; i < sz; ++i)
array[i] = (TT)rand() / 100.F;
}
int main(){
TT *a = new TT[TEST_SIZE], *b = new TT[TEST_SIZE], *c = new TT[TEST_SIZE], *d = new TT[TEST_SIZE];
TT* da, *db, *dc;
random_array(a, TEST_SIZE);
random_array(b, TEST_SIZE);
cudaMalloc((void**)&da, sizeof(TT) * TEST_SIZE);
cudaMalloc((void**)&db, sizeof(TT) * TEST_SIZE);
cudaMalloc((void**)&dc, sizeof(TT) * TEST_SIZE);
clock_t timing_start = clock();
cudaMemcpy(da, a, sizeof(TT) * TEST_SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(db, b, sizeof(TT) * TEST_SIZE, cudaMemcpyHostToDevice);
add1d_cuda<<<BSZ, TSZ>>>(dc, da, db);
cudaMemcpy(c, dc, sizeof(TT) * TEST_SIZE, cudaMemcpyDeviceToHost);
cout << "CUDA time: " << (clock() - timing_start) / (double)(CLOCKS_PER_SEC / 1000) << " ms" << endl;
cudaFree(da);
cudaFree(db);
cudaFree(dc);
timing_start = clock();
clock_t timing_end = add1d(d, a, b, TEST_SIZE);
cout << "CPU time: " << (timing_end - timing_start) / (double)(CLOCKS_PER_SEC / 1000) << " ms" << endl;
bool match = true;
for (size_t i = 0; i < TEST_SIZE; ++i)
if (c[i] - d[i] > EPS){
cout << "value does not match" << endl;
match = false;
}
if (match) cout << "All values match" << endl;
} | .file "tmpxft_00053e7c_00000000-6_add1d.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z10add1d_cudaIfEvPT_S1_S1_,"axG",@progbits,_Z10add1d_cudaIfEvPT_S1_S1_,comdat
.weak _Z10add1d_cudaIfEvPT_S1_S1_
.type _Z10add1d_cudaIfEvPT_S1_S1_, @function
_Z10add1d_cudaIfEvPT_S1_S1_:
.LFB4002:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add1d_cudaIfEvPT_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4002:
.size _Z10add1d_cudaIfEvPT_S1_S1_, .-_Z10add1d_cudaIfEvPT_S1_S1_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10add1d_cudaIfEvPT_S1_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add1d_cudaIfEvPT_S1_S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._Z12random_arrayIfEvPT_m,"axG",@progbits,_Z12random_arrayIfEvPT_m,comdat
.weak _Z12random_arrayIfEvPT_m
.type _Z12random_arrayIfEvPT_m, @function
_Z12random_arrayIfEvPT_m:
.LFB4001:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testq %rbp, %rbp
je .L11
movl $0, %ebx
.L13:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC1(%rip), %xmm0
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbx, %rbp
jne .L13
.L11:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4001:
.size _Z12random_arrayIfEvPT_m, .-_Z12random_arrayIfEvPT_m
.section .rodata.str1.1
.LC2:
.string "CUDA time: "
.LC4:
.string " ms"
.LC5:
.string "CPU time: "
.LC7:
.string "value does not match"
.LC8:
.string "All values match"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $8388608, %edi
call _Znam@PLT
movq %rax, %rbx
movl $8388608, %edi
call _Znam@PLT
movq %rax, %rbp
movl $8388608, %edi
call _Znam@PLT
movq %rax, %r14
movl $8388608, %edi
call _Znam@PLT
movq %rax, %r13
movl $2097152, %esi
movq %rbx, %rdi
call _Z12random_arrayIfEvPT_m
movl $2097152, %esi
movq %rbp, %rdi
call _Z12random_arrayIfEvPT_m
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
call clock@PLT
movq %rax, %r15
movl $1, %ecx
movl $8388608, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8388608, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $2048, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L17:
movl $2, %ecx
movl $8388608, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
movq %rax, %r12
movl $0, %eax
.L18:
movss (%rbx,%rax,4), %xmm0
addss 0(%rbp,%rax,4), %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $2097152, %rax
jne .L18
call clock@PLT
movq %rax, %rbx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %r12, %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC3(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
movl $1, %eax
leaq .LC7(%rip), %r15
leaq _ZSt4cout(%rip), %r12
jmp .L25
.L32:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z10add1d_cudaIfEvPT_S1_S1_
jmp .L17
.L35:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
call _ZSt16__throw_bad_castv@PLT
.L33:
call __stack_chk_fail@PLT
.L23:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L24:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
.L19:
addq $1, %rbx
cmpq $2097152, %rbx
je .L34
.L25:
movss (%r14,%rbx,4), %xmm0
subss 0(%r13,%rbx,4), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC6(%rip), %xmm0
jbe .L19
movl $20, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbp
testq %rbp, %rbp
je .L35
cmpb $0, 56(%rbp)
je .L23
movzbl 67(%rbp), %esi
jmp .L24
.L34:
testb %al, %al
jne .L36
.L26:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L26
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1120403456
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1083129856
.align 8
.LC6:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //add 2 arrays in parallel, often this is faster on CPU than GPU
//reason is computation is not intense, require more data than
//computation
#include <cstdlib>
#include <ctime>
#include <iostream>
#define BSZ 2048
#define TSZ 1024
#define TEST_SIZE BSZ * TSZ
#define TT float
#define EPS 10e-6
using namespace std;
template <typename T>
__global__ void add1d_cuda(T* c, T* a, T* b){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
c[idx] = a[idx] + b[idx];
}
template <typename T>
clock_t add1d(T* c, T* a, T* b, size_t sz){
for (size_t i = 0; i < sz; ++i)
c[i] = a[i] + b[i];
return clock();
}
template <typename T>
void random_array(T* array, size_t sz){
srand(time(0));
for (size_t i = 0; i < sz; ++i)
array[i] = (TT)rand() / 100.F;
}
int main(){
TT *a = new TT[TEST_SIZE], *b = new TT[TEST_SIZE], *c = new TT[TEST_SIZE], *d = new TT[TEST_SIZE];
TT* da, *db, *dc;
random_array(a, TEST_SIZE);
random_array(b, TEST_SIZE);
cudaMalloc((void**)&da, sizeof(TT) * TEST_SIZE);
cudaMalloc((void**)&db, sizeof(TT) * TEST_SIZE);
cudaMalloc((void**)&dc, sizeof(TT) * TEST_SIZE);
clock_t timing_start = clock();
cudaMemcpy(da, a, sizeof(TT) * TEST_SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(db, b, sizeof(TT) * TEST_SIZE, cudaMemcpyHostToDevice);
add1d_cuda<<<BSZ, TSZ>>>(dc, da, db);
cudaMemcpy(c, dc, sizeof(TT) * TEST_SIZE, cudaMemcpyDeviceToHost);
cout << "CUDA time: " << (clock() - timing_start) / (double)(CLOCKS_PER_SEC / 1000) << " ms" << endl;
cudaFree(da);
cudaFree(db);
cudaFree(dc);
timing_start = clock();
clock_t timing_end = add1d(d, a, b, TEST_SIZE);
cout << "CPU time: " << (timing_end - timing_start) / (double)(CLOCKS_PER_SEC / 1000) << " ms" << endl;
bool match = true;
for (size_t i = 0; i < TEST_SIZE; ++i)
if (c[i] - d[i] > EPS){
cout << "value does not match" << endl;
match = false;
}
if (match) cout << "All values match" << endl;
} | //add 2 arrays in parallel, often this is faster on CPU than GPU
//reason is computation is not intense, require more data than
//computation
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <ctime>
#include <iostream>
#define BSZ 2048
#define TSZ 1024
#define TEST_SIZE BSZ * TSZ
#define TT float
#define EPS 10e-6
using namespace std;
template <typename T>
__global__ void add1d_cuda(T* c, T* a, T* b){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
c[idx] = a[idx] + b[idx];
}
template <typename T>
clock_t add1d(T* c, T* a, T* b, size_t sz){
for (size_t i = 0; i < sz; ++i)
c[i] = a[i] + b[i];
return clock();
}
template <typename T>
void random_array(T* array, size_t sz){
srand(time(0));
for (size_t i = 0; i < sz; ++i)
array[i] = (TT)rand() / 100.F;
}
int main(){
TT *a = new TT[TEST_SIZE], *b = new TT[TEST_SIZE], *c = new TT[TEST_SIZE], *d = new TT[TEST_SIZE];
TT* da, *db, *dc;
random_array(a, TEST_SIZE);
random_array(b, TEST_SIZE);
hipMalloc((void**)&da, sizeof(TT) * TEST_SIZE);
hipMalloc((void**)&db, sizeof(TT) * TEST_SIZE);
hipMalloc((void**)&dc, sizeof(TT) * TEST_SIZE);
clock_t timing_start = clock();
hipMemcpy(da, a, sizeof(TT) * TEST_SIZE, hipMemcpyHostToDevice);
hipMemcpy(db, b, sizeof(TT) * TEST_SIZE, hipMemcpyHostToDevice);
add1d_cuda<<<BSZ, TSZ>>>(dc, da, db);
hipMemcpy(c, dc, sizeof(TT) * TEST_SIZE, hipMemcpyDeviceToHost);
cout << "CUDA time: " << (clock() - timing_start) / (double)(CLOCKS_PER_SEC / 1000) << " ms" << endl;
hipFree(da);
hipFree(db);
hipFree(dc);
timing_start = clock();
clock_t timing_end = add1d(d, a, b, TEST_SIZE);
cout << "CPU time: " << (timing_end - timing_start) / (double)(CLOCKS_PER_SEC / 1000) << " ms" << endl;
bool match = true;
for (size_t i = 0; i < TEST_SIZE; ++i)
if (c[i] - d[i] > EPS){
cout << "value does not match" << endl;
match = false;
}
if (match) cout << "All values match" << endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //add 2 arrays in parallel, often this is faster on CPU than GPU
//reason is computation is not intense, require more data than
//computation
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <ctime>
#include <iostream>
#define BSZ 2048
#define TSZ 1024
#define TEST_SIZE BSZ * TSZ
#define TT float
#define EPS 10e-6
using namespace std;
template <typename T>
__global__ void add1d_cuda(T* c, T* a, T* b){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
c[idx] = a[idx] + b[idx];
}
template <typename T>
clock_t add1d(T* c, T* a, T* b, size_t sz){
for (size_t i = 0; i < sz; ++i)
c[i] = a[i] + b[i];
return clock();
}
template <typename T>
void random_array(T* array, size_t sz){
srand(time(0));
for (size_t i = 0; i < sz; ++i)
array[i] = (TT)rand() / 100.F;
}
int main(){
TT *a = new TT[TEST_SIZE], *b = new TT[TEST_SIZE], *c = new TT[TEST_SIZE], *d = new TT[TEST_SIZE];
TT* da, *db, *dc;
random_array(a, TEST_SIZE);
random_array(b, TEST_SIZE);
hipMalloc((void**)&da, sizeof(TT) * TEST_SIZE);
hipMalloc((void**)&db, sizeof(TT) * TEST_SIZE);
hipMalloc((void**)&dc, sizeof(TT) * TEST_SIZE);
clock_t timing_start = clock();
hipMemcpy(da, a, sizeof(TT) * TEST_SIZE, hipMemcpyHostToDevice);
hipMemcpy(db, b, sizeof(TT) * TEST_SIZE, hipMemcpyHostToDevice);
add1d_cuda<<<BSZ, TSZ>>>(dc, da, db);
hipMemcpy(c, dc, sizeof(TT) * TEST_SIZE, hipMemcpyDeviceToHost);
cout << "CUDA time: " << (clock() - timing_start) / (double)(CLOCKS_PER_SEC / 1000) << " ms" << endl;
hipFree(da);
hipFree(db);
hipFree(dc);
timing_start = clock();
clock_t timing_end = add1d(d, a, b, TEST_SIZE);
cout << "CPU time: " << (timing_end - timing_start) / (double)(CLOCKS_PER_SEC / 1000) << " ms" << endl;
bool match = true;
for (size_t i = 0; i < TEST_SIZE; ++i)
if (c[i] - d[i] > EPS){
cout << "value does not match" << endl;
match = false;
}
if (match) cout << "All values match" << endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z10add1d_cudaIfEvPT_S1_S1_,"axG",@progbits,_Z10add1d_cudaIfEvPT_S1_S1_,comdat
.protected _Z10add1d_cudaIfEvPT_S1_S1_
.globl _Z10add1d_cudaIfEvPT_S1_S1_
.p2align 8
.type _Z10add1d_cudaIfEvPT_S1_S1_,@function
_Z10add1d_cudaIfEvPT_S1_S1_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add1d_cudaIfEvPT_S1_S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z10add1d_cudaIfEvPT_S1_S1_,"axG",@progbits,_Z10add1d_cudaIfEvPT_S1_S1_,comdat
.Lfunc_end0:
.size _Z10add1d_cudaIfEvPT_S1_S1_, .Lfunc_end0-_Z10add1d_cudaIfEvPT_S1_S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add1d_cudaIfEvPT_S1_S1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add1d_cudaIfEvPT_S1_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //add 2 arrays in parallel, often this is faster on CPU than GPU
//reason is computation is not intense, require more data than
//computation
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <ctime>
#include <iostream>
#define BSZ 2048
#define TSZ 1024
#define TEST_SIZE BSZ * TSZ
#define TT float
#define EPS 10e-6
using namespace std;
template <typename T>
__global__ void add1d_cuda(T* c, T* a, T* b){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
c[idx] = a[idx] + b[idx];
}
template <typename T>
clock_t add1d(T* c, T* a, T* b, size_t sz){
for (size_t i = 0; i < sz; ++i)
c[i] = a[i] + b[i];
return clock();
}
template <typename T>
void random_array(T* array, size_t sz){
srand(time(0));
for (size_t i = 0; i < sz; ++i)
array[i] = (TT)rand() / 100.F;
}
int main(){
TT *a = new TT[TEST_SIZE], *b = new TT[TEST_SIZE], *c = new TT[TEST_SIZE], *d = new TT[TEST_SIZE];
TT* da, *db, *dc;
random_array(a, TEST_SIZE);
random_array(b, TEST_SIZE);
hipMalloc((void**)&da, sizeof(TT) * TEST_SIZE);
hipMalloc((void**)&db, sizeof(TT) * TEST_SIZE);
hipMalloc((void**)&dc, sizeof(TT) * TEST_SIZE);
clock_t timing_start = clock();
hipMemcpy(da, a, sizeof(TT) * TEST_SIZE, hipMemcpyHostToDevice);
hipMemcpy(db, b, sizeof(TT) * TEST_SIZE, hipMemcpyHostToDevice);
add1d_cuda<<<BSZ, TSZ>>>(dc, da, db);
hipMemcpy(c, dc, sizeof(TT) * TEST_SIZE, hipMemcpyDeviceToHost);
cout << "CUDA time: " << (clock() - timing_start) / (double)(CLOCKS_PER_SEC / 1000) << " ms" << endl;
hipFree(da);
hipFree(db);
hipFree(dc);
timing_start = clock();
clock_t timing_end = add1d(d, a, b, TEST_SIZE);
cout << "CPU time: " << (timing_end - timing_start) / (double)(CLOCKS_PER_SEC / 1000) << " ms" << endl;
bool match = true;
for (size_t i = 0; i < TEST_SIZE; ++i)
if (c[i] - d[i] > EPS){
cout << "value does not match" << endl;
match = false;
}
if (match) cout << "All values match" << endl;
} | .text
.file "add1d.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x42c80000 # float 100
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_1:
.quad 0x408f400000000000 # double 1000
.LCPI0_2:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8388608, %edi # imm = 0x800000
callq _Znam
movq %rax, %r15
movl $8388608, %edi # imm = 0x800000
callq _Znam
movq %rax, %r12
movl $8388608, %edi # imm = 0x800000
callq _Znam
movq %rax, %rbx
movl $8388608, %edi # imm = 0x800000
callq _Znam
movq %rax, %r14
xorl %r13d, %r13d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%r15,%r13,4)
incq %r13
cmpq $2097152, %r13 # imm = 0x200000
jne .LBB0_1
# %bb.2: # %_Z12random_arrayIfEvPT_m.exit
xorl %r13d, %r13d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i22
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $2097152, %r13 # imm = 0x200000
jne .LBB0_3
# %bb.4: # %_Z12random_arrayIfEvPT_m.exit25
leaq 16(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movq %rsp, %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
callq clock
movq %rax, %r13
movq 16(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 1024(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10add1d_cudaIfEvPT_S1_S1_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq (%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI0_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB0_31
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB0_9
# %bb.8:
movzbl 67(%rbp), %eax
jmp .LBB0_10
.LBB0_9:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %ebp, %ebp
callq clock
movq %rax, %r13
.p2align 4, 0x90
.LBB0_11: # %.lr.ph.i26
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r12,%rbp,4), %xmm0
movss %xmm0, (%r14,%rbp,4)
incq %rbp
cmpq $2097152, %rbp # imm = 0x200000
jne .LBB0_11
# %bb.12: # %_Z5add1dIfElPT_S1_S1_m.exit
callq clock
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r13, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI0_1(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_31
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i29
cmpb $0, 56(%r12)
je .LBB0_15
# %bb.14:
movzbl 67(%r12), %eax
jmp .LBB0_16
.LBB0_15:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movb $1, %al
xorl %r12d, %r12d
movsd .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB0_17
.p2align 4, 0x90
.LBB0_20: # in Loop: Header=BB0_17 Depth=1
movzbl 67(%r15), %eax
.LBB0_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit37
# in Loop: Header=BB0_17 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
movsd .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero
.LBB0_23: # in Loop: Header=BB0_17 Depth=1
incq %r12
cmpq $2097152, %r12 # imm = 0x200000
je .LBB0_24
.LBB0_17: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%r14,%r12,4), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm1, %xmm0
jbe .LBB0_23
# %bb.18: # in Loop: Header=BB0_17 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_31
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i34
# in Loop: Header=BB0_17 Depth=1
cmpb $0, 56(%r15)
jne .LBB0_20
# %bb.21: # in Loop: Header=BB0_17 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_22
.LBB0_24:
testb $1, %al
je .LBB0_30
# %bb.25:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_31
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i39
cmpb $0, 56(%rbx)
je .LBB0_28
# %bb.27:
movzbl 67(%rbx), %eax
jmp .LBB0_29
.LBB0_28:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit42
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB0_30:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_31:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z25__device_stub__add1d_cudaIfEvPT_S1_S1_,"axG",@progbits,_Z25__device_stub__add1d_cudaIfEvPT_S1_S1_,comdat
.weak _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_ # -- Begin function _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_
.p2align 4, 0x90
.type _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_,@function
_Z25__device_stub__add1d_cudaIfEvPT_S1_S1_: # @_Z25__device_stub__add1d_cudaIfEvPT_S1_S1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add1d_cudaIfEvPT_S1_S1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_, .Lfunc_end1-_Z25__device_stub__add1d_cudaIfEvPT_S1_S1_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add1d_cudaIfEvPT_S1_S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10add1d_cudaIfEvPT_S1_S1_,@object # @_Z10add1d_cudaIfEvPT_S1_S1_
.section .rodata._Z10add1d_cudaIfEvPT_S1_S1_,"aG",@progbits,_Z10add1d_cudaIfEvPT_S1_S1_,comdat
.weak _Z10add1d_cudaIfEvPT_S1_S1_
.p2align 3, 0x0
_Z10add1d_cudaIfEvPT_S1_S1_:
.quad _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_
.size _Z10add1d_cudaIfEvPT_S1_S1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA time: "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU time: "
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "value does not match"
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "All values match"
.size .L.str.4, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add1d_cudaIfEvPT_S1_S1_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add1d_cudaIfEvPT_S1_S1_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10add1d_cudaIfEvPT_S1_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z10add1d_cudaIfEvPT_S1_S1_,"axG",@progbits,_Z10add1d_cudaIfEvPT_S1_S1_,comdat
.protected _Z10add1d_cudaIfEvPT_S1_S1_
.globl _Z10add1d_cudaIfEvPT_S1_S1_
.p2align 8
.type _Z10add1d_cudaIfEvPT_S1_S1_,@function
_Z10add1d_cudaIfEvPT_S1_S1_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add1d_cudaIfEvPT_S1_S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z10add1d_cudaIfEvPT_S1_S1_,"axG",@progbits,_Z10add1d_cudaIfEvPT_S1_S1_,comdat
.Lfunc_end0:
.size _Z10add1d_cudaIfEvPT_S1_S1_, .Lfunc_end0-_Z10add1d_cudaIfEvPT_S1_S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add1d_cudaIfEvPT_S1_S1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add1d_cudaIfEvPT_S1_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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