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You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00053e7c_00000000-6_add1d.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .section .text._Z10add1d_cudaIfEvPT_S1_S1_,"axG",@progbits,_Z10add1d_cudaIfEvPT_S1_S1_,comdat .weak _Z10add1d_cudaIfEvPT_S1_S1_ .type _Z10add1d_cudaIfEvPT_S1_S1_, @function _Z10add1d_cudaIfEvPT_S1_S1_: .LFB4002: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax movq %rdi, 8(%rsp) movq %rsi, 16(%rsp) movq %rdx, 24(%rsp) leaq 8(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 24(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L5 .L1: movq 120(%rsp), %rax subq %fs:40, %rax jne .L6 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L5: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z10add1d_cudaIfEvPT_S1_S1_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L1 .L6: call __stack_chk_fail@PLT .cfi_endproc .LFE4002: .size _Z10add1d_cudaIfEvPT_S1_S1_, .-_Z10add1d_cudaIfEvPT_S1_S1_ .text .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3676: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3676: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z10add1d_cudaIfEvPT_S1_S1_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3701: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z10add1d_cudaIfEvPT_S1_S1_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3701: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .text._Z12random_arrayIfEvPT_m,"axG",@progbits,_Z12random_arrayIfEvPT_m,comdat .weak _Z12random_arrayIfEvPT_m .type _Z12random_arrayIfEvPT_m, @function _Z12random_arrayIfEvPT_m: .LFB4001: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 movq %rdi, %r12 movq %rsi, %rbp movl $0, %edi call time@PLT movl %eax, %edi call srand@PLT testq %rbp, %rbp je .L11 movl $0, %ebx .L13: call rand@PLT pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 divss .LC1(%rip), %xmm0 movss %xmm0, (%r12,%rbx,4) addq $1, %rbx cmpq %rbx, %rbp jne .L13 .L11: popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE4001: .size _Z12random_arrayIfEvPT_m, .-_Z12random_arrayIfEvPT_m .section .rodata.str1.1 .LC2: .string "CUDA time: " .LC4: .string " ms" .LC5: .string "CPU time: " .LC7: .string "value does not match" .LC8: .string "All values match" .text .globl main .type main, @function main: .LFB3673: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movl $8388608, %edi call _Znam@PLT movq %rax, %rbx movl $8388608, %edi call _Znam@PLT movq %rax, %rbp movl $8388608, %edi call _Znam@PLT movq %rax, %r14 movl $8388608, %edi call _Znam@PLT movq %rax, %r13 movl $2097152, %esi movq %rbx, %rdi call _Z12random_arrayIfEvPT_m movl $2097152, %esi movq %rbp, %rdi call _Z12random_arrayIfEvPT_m leaq 8(%rsp), %rdi movl $8388608, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $8388608, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $8388608, %esi call cudaMalloc@PLT call clock@PLT movq %rax, %r15 movl $1, %ecx movl $8388608, %edx movq %rbx, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $8388608, %edx movq %rbp, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl $1024, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $2048, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L32 .L17: movl $2, %ecx movl $8388608, %edx movq 24(%rsp), %rsi movq %r14, %rdi call cudaMemcpy@PLT leaq .LC2(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %r12 call clock@PLT subq %r15, %rax pxor %xmm0, %xmm0 cvtsi2sdq %rax, %xmm0 divsd .LC3(%rip), %xmm0 movq %r12, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC4(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT call clock@PLT movq %rax, %r12 movl $0, %eax .L18: movss (%rbx,%rax,4), %xmm0 addss 0(%rbp,%rax,4), %xmm0 movss %xmm0, 0(%r13,%rax,4) addq $1, %rax cmpq $2097152, %rax jne .L18 call clock@PLT movq %rax, %rbx leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi subq %r12, %rbx pxor %xmm0, %xmm0 cvtsi2sdq %rbx, %xmm0 divsd .LC3(%rip), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC4(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT movl $0, %ebx movl $1, %eax leaq .LC7(%rip), %r15 leaq _ZSt4cout(%rip), %r12 jmp .L25 .L32: movq 16(%rsp), %rdx movq 8(%rsp), %rsi movq 24(%rsp), %rdi call _Z10add1d_cudaIfEvPT_S1_S1_ jmp .L17 .L35: movq 56(%rsp), %rax subq %fs:40, %rax jne .L33 call _ZSt16__throw_bad_castv@PLT .L33: call __stack_chk_fail@PLT .L23: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi .L24: movsbl %sil, %esi movq %r12, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT movl $0, %eax .L19: addq $1, %rbx cmpq $2097152, %rbx je .L34 .L25: movss (%r14,%rbx,4), %xmm0 subss 0(%r13,%rbx,4), %xmm0 cvtss2sd %xmm0, %xmm0 comisd .LC6(%rip), %xmm0 jbe .L19 movl $20, %edx movq %r15, %rsi movq %r12, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movq (%r12), %rax movq -24(%rax), %rax movq 240(%r12,%rax), %rbp testq %rbp, %rbp je .L35 cmpb $0, 56(%rbp) je .L23 movzbl 67(%rbp), %esi jmp .L24 .L34: testb %al, %al jne .L36 .L26: movq 56(%rsp), %rax subq %fs:40, %rax jne .L37 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L36: .cfi_restore_state leaq .LC8(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT jmp .L26 .L37: call __stack_chk_fail@PLT .cfi_endproc .LFE3673: .size main, .-main .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 1120403456 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC3: .long 0 .long 1083129856 .align 8 .LC6: .long -1998362383 .long 1055193269 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "add1d.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI0_0: .long 0x42c80000 # float 100 .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 .LCPI0_1: .quad 0x408f400000000000 # double 1000 .LCPI0_2: .quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $120, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $8388608, %edi # imm = 0x800000 callq _Znam movq %rax, %r15 movl $8388608, %edi # imm = 0x800000 callq _Znam movq %rax, %r12 movl $8388608, %edi # imm = 0x800000 callq _Znam movq %rax, %rbx movl $8388608, %edi # imm = 0x800000 callq _Znam movq %rax, %r14 xorl %r13d, %r13d xorl %edi, %edi callq time movl %eax, %edi callq srand .p2align 4, 0x90 .LBB0_1: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 divss .LCPI0_0(%rip), %xmm0 movss %xmm0, (%r15,%r13,4) incq %r13 cmpq $2097152, %r13 # imm = 0x200000 jne .LBB0_1 # %bb.2: # %_Z12random_arrayIfEvPT_m.exit xorl %r13d, %r13d xorl %edi, %edi callq time movl %eax, %edi callq srand .p2align 4, 0x90 .LBB0_3: # %.lr.ph.i22 # =>This Inner Loop Header: Depth=1 callq rand xorps %xmm0, %xmm0 cvtsi2ss %eax, %xmm0 divss .LCPI0_0(%rip), %xmm0 movss %xmm0, (%r12,%r13,4) incq %r13 cmpq $2097152, %r13 # imm = 0x200000 jne .LBB0_3 # %bb.4: # %_Z12random_arrayIfEvPT_m.exit25 leaq 16(%rsp), %rdi movl $8388608, %esi # imm = 0x800000 callq hipMalloc leaq 8(%rsp), %rdi movl $8388608, %esi # imm = 0x800000 callq hipMalloc movq %rsp, %rdi movl $8388608, %esi # imm = 0x800000 callq hipMalloc callq clock movq %rax, %r13 movq 16(%rsp), %rdi movl $8388608, %edx # imm = 0x800000 movq %r15, %rsi movl $1, %ecx callq hipMemcpy movq 8(%rsp), %rdi movl $8388608, %edx # imm = 0x800000 movq %r12, %rsi movl $1, %ecx callq hipMemcpy movabsq $4294968320, %rdx # imm = 0x100000400 leaq 1024(%rdx), %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB0_6 # %bb.5: movq (%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movq %rdx, 72(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 56(%rsp), %rdi leaq 40(%rsp), %rsi leaq 32(%rsp), %rdx leaq 24(%rsp), %rcx callq __hipPopCallConfiguration movq 56(%rsp), %rsi movl 64(%rsp), %edx movq 40(%rsp), %rcx movl 48(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z10add1d_cudaIfEvPT_S1_S1_, %edi pushq 24(%rsp) .cfi_adjust_cfa_offset 8 pushq 40(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB0_6: movq (%rsp), %rsi movl $8388608, %edx # imm = 0x800000 movq %rbx, %rdi movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %edi movl $.L.str, %esi movl $11, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l callq clock subq %r13, %rax xorps %xmm0, %xmm0 cvtsi2sd %rax, %xmm0 divsd .LCPI0_1(%rip), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r13 movl $.L.str.1, %esi movl $3, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%r13), %rax movq -24(%rax), %rax movq 240(%r13,%rax), %rbp testq %rbp, %rbp je .LBB0_31 # %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i cmpb $0, 56(%rbp) je .LBB0_9 # %bb.8: movzbl 67(%rbp), %eax jmp .LBB0_10 .LBB0_9: movq %rbp, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbp), %rax movq %rbp, %rdi movl $10, %esi callq *48(%rax) .LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit movsbl %al, %esi movq %r13, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree xorl %ebp, %ebp callq clock movq %rax, %r13 .p2align 4, 0x90 .LBB0_11: # %.lr.ph.i26 # =>This Inner Loop Header: Depth=1 movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero addss (%r12,%rbp,4), %xmm0 movss %xmm0, (%r14,%rbp,4) incq %rbp cmpq $2097152, %rbp # imm = 0x200000 jne .LBB0_11 # %bb.12: # %_Z5add1dIfElPT_S1_S1_m.exit callq clock movq %rax, %r15 movl $_ZSt4cout, %edi movl $.L.str.2, %esi movl $10, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l subq %r13, %r15 xorps %xmm0, %xmm0 cvtsi2sd %r15, %xmm0 divsd .LCPI0_1(%rip), %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %r15 movl $.L.str.1, %esi movl $3, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq (%r15), %rax movq -24(%rax), %rax movq 240(%r15,%rax), %r12 testq %r12, %r12 je .LBB0_31 # %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i29 cmpb $0, 56(%r12) je .LBB0_15 # %bb.14: movzbl 67(%r12), %eax jmp .LBB0_16 .LBB0_15: movq %r12, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r12), %rax movq %r12, %rdi movl $10, %esi callq *48(%rax) .LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32 movsbl %al, %esi movq %r15, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv movb $1, %al xorl %r12d, %r12d movsd .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero jmp .LBB0_17 .p2align 4, 0x90 .LBB0_20: # in Loop: Header=BB0_17 Depth=1 movzbl 67(%r15), %eax .LBB0_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit37 # in Loop: Header=BB0_17 Depth=1 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv xorl %eax, %eax movsd .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero .LBB0_23: # in Loop: Header=BB0_17 Depth=1 incq %r12 cmpq $2097152, %r12 # imm = 0x200000 je .LBB0_24 .LBB0_17: # =>This Inner Loop Header: Depth=1 movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero subss (%r14,%r12,4), %xmm0 cvtss2sd %xmm0, %xmm0 ucomisd %xmm1, %xmm0 jbe .LBB0_23 # %bb.18: # in Loop: Header=BB0_17 Depth=1 movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $20, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %r15 testq %r15, %r15 je .LBB0_31 # %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i34 # in Loop: Header=BB0_17 Depth=1 cmpb $0, 56(%r15) jne .LBB0_20 # %bb.21: # in Loop: Header=BB0_17 Depth=1 movq %r15, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) jmp .LBB0_22 .LBB0_24: testb $1, %al je .LBB0_30 # %bb.25: movl $_ZSt4cout, %edi movl $.L.str.4, %esi movl $16, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq _ZSt4cout(%rip), %rax movq -24(%rax), %rax movq _ZSt4cout+240(%rax), %rbx testq %rbx, %rbx je .LBB0_31 # %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i39 cmpb $0, 56(%rbx) je .LBB0_28 # %bb.27: movzbl 67(%rbx), %eax jmp .LBB0_29 .LBB0_28: movq %rbx, %rdi callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%rbx), %rax movq %rbx, %rdi movl $10, %esi callq *48(%rax) .LBB0_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit42 movsbl %al, %esi movl $_ZSt4cout, %edi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv .LBB0_30: xorl %eax, %eax addq $120, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB0_31: .cfi_def_cfa_offset 176 callq _ZSt16__throw_bad_castv .Lfunc_end0: .size main, .Lfunc_end0-main .cfi_endproc # -- End function .section .text._Z25__device_stub__add1d_cudaIfEvPT_S1_S1_,"axG",@progbits,_Z25__device_stub__add1d_cudaIfEvPT_S1_S1_,comdat .weak _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_ # -- Begin function _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_ .p2align 4, 0x90 .type _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_,@function _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_: # @_Z25__device_stub__add1d_cudaIfEvPT_S1_S1_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z10add1d_cudaIfEvPT_S1_S1_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end1: .size _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_, .Lfunc_end1-_Z25__device_stub__add1d_cudaIfEvPT_S1_S1_ .cfi_endproc # -- End function .text .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10add1d_cudaIfEvPT_S1_S1_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z10add1d_cudaIfEvPT_S1_S1_,@object # @_Z10add1d_cudaIfEvPT_S1_S1_ .section .rodata._Z10add1d_cudaIfEvPT_S1_S1_,"aG",@progbits,_Z10add1d_cudaIfEvPT_S1_S1_,comdat .weak _Z10add1d_cudaIfEvPT_S1_S1_ .p2align 3, 0x0 _Z10add1d_cudaIfEvPT_S1_S1_: .quad _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_ .size _Z10add1d_cudaIfEvPT_S1_S1_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "CUDA time: " .size .L.str, 12 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz " ms" .size .L.str.1, 4 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "CPU time: " .size .L.str.2, 11 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "value does not match" .size .L.str.3, 21 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "All values match" .size .L.str.4, 17 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z10add1d_cudaIfEvPT_S1_S1_" .size .L__unnamed_1, 28 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__add1d_cudaIfEvPT_S1_S1_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10add1d_cudaIfEvPT_S1_S1_ .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdint.h> __global__ void adjust_hue_hwc(const int height, const int width, uint8_t * const __restrict__ input, uint8_t * const __restrict__ output, const float hue_delta) { // multiply by 3 since we're dealing with contiguous RGB bytes for each pixel const int idx = (blockDim.x * blockIdx.x + threadIdx.x) * 3; // bounds check if (idx > height * width * 3) { return; } // RGB to HSV const float r = input[idx]; const float g = input[idx + 1]; const float b = input[idx + 2]; const float M = fmaxf(r, fmaxf(g, b)); const float m = fminf(r, fminf(g, b)); const float chroma = M - m; // v is the same as M float h = 0.0f, s = 0.0f; // v = 0.0; // hue if (chroma > 0.0f) { if (M == r) { const float num = (g - b) / chroma; const float sgn = num < 0.0f; const float sign = powf(-1.0f, sgn); h = (sgn * 6.0f + sign * fmodf(sign * num, 6.0f)) / 6.0f; } else if (M == g) { h = ((b - r) / chroma + 2.0f) / 6.0f; } else { h = ((r - g) / chroma + 4.0f) / 6.0f; } } else { h = 0.0f; } // saturation if (M > 0.0f) { s = chroma / M; } else { s = 0.0f; } // hue adjustment h = fmodf(h + hue_delta, 1.0f); //////////////////////////////////////////// // Murmurhash - based random adjustment // uint32_t k = idx; // uint32_t seed = 42; // k *= 0xcc9e2d51; // k = (k << 15) | (k >> 17); // k *= 0x1b873593; // seed ^= k; // seed ^= 1; // seed ^= seed >> 16; // seed *= 0x85ebca6b; // seed ^= seed >> 13; // seed *= 0xc2b2ae35; // seed ^= seed >> 16; // // TODO: Add scaling factor // // TODO: Cover shifts both up and down with wrap-around // float rand_delta = (seed >> 8) / (float) (1 << 24); // h = fmod(h + rand_delta, 1.0f); //////////////////////////////////////////// // HSV to RGB const float new_h = h * 6.0f; const float new_chroma = M * s; const float x = chroma * (1.0 - fabs(fmod(new_h, 2.0f) - 1.0f)); const float new_m = M - chroma; const bool between_0_and_1 = new_h >= 0.0f && new_h < 1.0f; const bool between_1_and_2 = new_h >= 1.0f && new_h < 2.0f; const bool between_2_and_3 = new_h >= 2.0f && new_h < 3.0f; const bool between_3_and_4 = new_h >= 3.0f && new_h < 4.0f; const bool between_4_and_5 = new_h >= 4.0f && new_h < 5.0f; const bool between_5_and_6 = new_h >= 5.0f && new_h < 6.0f; output[idx] = roundf(new_chroma * (between_0_and_1 || between_5_and_6) + x * (between_1_and_2 || between_4_and_5) + new_m); output[idx + 1] = roundf(new_chroma * (between_1_and_2 || between_2_and_3) + x * (between_0_and_1 || between_3_and_4) + new_m); output[idx + 2] = roundf(new_chroma * (between_3_and_4 || between_4_and_5) + x * (between_2_and_3 || between_5_and_6) + new_m); }
.file "tmpxft_00013018_00000000-6_gpu_impl.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z39__device_stub__Z14adjust_hue_hwciiPhS_fiiPhS_f .type _Z39__device_stub__Z14adjust_hue_hwciiPhS_fiiPhS_f, @function _Z39__device_stub__Z14adjust_hue_hwciiPhS_fiiPhS_f: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movss %xmm0, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) movq %rdx, 16(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) movq %rcx, 24(%rsp) leaq 24(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z14adjust_hue_hwciiPhS_f(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z39__device_stub__Z14adjust_hue_hwciiPhS_fiiPhS_f, .-_Z39__device_stub__Z14adjust_hue_hwciiPhS_fiiPhS_f .globl _Z14adjust_hue_hwciiPhS_f .type _Z14adjust_hue_hwciiPhS_f, @function _Z14adjust_hue_hwciiPhS_f: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z39__device_stub__Z14adjust_hue_hwciiPhS_fiiPhS_f addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z14adjust_hue_hwciiPhS_f, .-_Z14adjust_hue_hwciiPhS_f .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z14adjust_hue_hwciiPhS_f" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z14adjust_hue_hwciiPhS_f(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdint.h> __global__ void adjust_hue_hwc(const int height, const int width, uint8_t * const __restrict__ input, uint8_t * const __restrict__ output, const float hue_delta) { // multiply by 3 since we're dealing with contiguous RGB bytes for each pixel const int idx = (blockDim.x * blockIdx.x + threadIdx.x) * 3; // bounds check if (idx > height * width * 3) { return; } // RGB to HSV const float r = input[idx]; const float g = input[idx + 1]; const float b = input[idx + 2]; const float M = fmaxf(r, fmaxf(g, b)); const float m = fminf(r, fminf(g, b)); const float chroma = M - m; // v is the same as M float h = 0.0f, s = 0.0f; // v = 0.0; // hue if (chroma > 0.0f) { if (M == r) { const float num = (g - b) / chroma; const float sgn = num < 0.0f; const float sign = powf(-1.0f, sgn); h = (sgn * 6.0f + sign * fmodf(sign * num, 6.0f)) / 6.0f; } else if (M == g) { h = ((b - r) / chroma + 2.0f) / 6.0f; } else { h = ((r - g) / chroma + 4.0f) / 6.0f; } } else { h = 0.0f; } // saturation if (M > 0.0f) { s = chroma / M; } else { s = 0.0f; } // hue adjustment h = fmodf(h + hue_delta, 1.0f); //////////////////////////////////////////// // Murmurhash - based random adjustment // uint32_t k = idx; // uint32_t seed = 42; // k *= 0xcc9e2d51; // k = (k << 15) | (k >> 17); // k *= 0x1b873593; // seed ^= k; // seed ^= 1; // seed ^= seed >> 16; // seed *= 0x85ebca6b; // seed ^= seed >> 13; // seed *= 0xc2b2ae35; // seed ^= seed >> 16; // // TODO: Add scaling factor // // TODO: Cover shifts both up and down with wrap-around // float rand_delta = (seed >> 8) / (float) (1 << 24); // h = fmod(h + rand_delta, 1.0f); //////////////////////////////////////////// // HSV to RGB const float new_h = h * 6.0f; const float new_chroma = M * s; const float x = chroma * (1.0 - fabs(fmod(new_h, 2.0f) - 1.0f)); const float new_m = M - chroma; const bool between_0_and_1 = new_h >= 0.0f && new_h < 1.0f; const bool between_1_and_2 = new_h >= 1.0f && new_h < 2.0f; const bool between_2_and_3 = new_h >= 2.0f && new_h < 3.0f; const bool between_3_and_4 = new_h >= 3.0f && new_h < 4.0f; const bool between_4_and_5 = new_h >= 4.0f && new_h < 5.0f; const bool between_5_and_6 = new_h >= 5.0f && new_h < 6.0f; output[idx] = roundf(new_chroma * (between_0_and_1 || between_5_and_6) + x * (between_1_and_2 || between_4_and_5) + new_m); output[idx + 1] = roundf(new_chroma * (between_1_and_2 || between_2_and_3) + x * (between_0_and_1 || between_3_and_4) + new_m); output[idx + 2] = roundf(new_chroma * (between_3_and_4 || between_4_and_5) + x * (between_2_and_3 || between_5_and_6) + new_m); }
#include <hip/hip_runtime.h> #include <stdint.h> #ifndef __ADJUST_HUE_CUDA #define __ADJUST_HUE_CUDA __global__ void adjust_hue_hwc(const int height, const int width, uint8_t * const input, uint8_t * const output, const float hue_delta); #endif
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <stdint.h> #ifndef __ADJUST_HUE_CUDA #define __ADJUST_HUE_CUDA __global__ void adjust_hue_hwc(const int height, const int width, uint8_t * const input, uint8_t * const output, const float hue_delta); #endif
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <stdint.h> #ifndef __ADJUST_HUE_CUDA #define __ADJUST_HUE_CUDA __global__ void adjust_hue_hwc(const int height, const int width, uint8_t * const input, uint8_t * const output, const float hue_delta); #endif
.text .file "gpu_impl.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00013018_00000000-6_gpu_impl.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z39__device_stub__Z14adjust_hue_hwciiPhS_fiiPhS_f .type _Z39__device_stub__Z14adjust_hue_hwciiPhS_fiiPhS_f, @function _Z39__device_stub__Z14adjust_hue_hwciiPhS_fiiPhS_f: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movss %xmm0, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) movq %rdx, 16(%rsp) leaq 16(%rsp), %rax movq %rax, 112(%rsp) movq %rcx, 24(%rsp) leaq 24(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z14adjust_hue_hwciiPhS_f(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z39__device_stub__Z14adjust_hue_hwciiPhS_fiiPhS_f, .-_Z39__device_stub__Z14adjust_hue_hwciiPhS_fiiPhS_f .globl _Z14adjust_hue_hwciiPhS_f .type _Z14adjust_hue_hwciiPhS_f, @function _Z14adjust_hue_hwciiPhS_f: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z39__device_stub__Z14adjust_hue_hwciiPhS_fiiPhS_f addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z14adjust_hue_hwciiPhS_f, .-_Z14adjust_hue_hwciiPhS_f .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z14adjust_hue_hwciiPhS_f" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z14adjust_hue_hwciiPhS_f(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "gpu_impl.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
/* Lab 4 Exercise 1 Program In this exercise we write a CUDA program to decipher some text encoded using an affine cipher (in the file `encrypted1.bin`) An affine cipher is a monoalphabetic substitution cipher, and it is decrypted by an affine decipher The encryption function is E(x) = (Ax + B) mod M The decryption function is D(x) = A^{−1}(x − B) mod M In this exercise `M` is 128 (the size of the ASCII alphabet), `A` is 15, `B` is 27, and so `A^{-1}` is 111. As each of the encrypted character values are independent we can use the GPU to decrypt them in parallel. To do this we will launch a thread for each of the encrypted character values and use a kernel function to perform the decryption. */ #include <stdio.h> #include <stdlib.h> #include "cuda_runtime.h" #include "device_launch_parameters.h" #define N 1024 // The number of characters in the encrypted text #define A 111 // The inverse multiplier to the encryption multiplier #define B 27 // The shift value in the encryption function #define M 128 // The modulus of the encryption (the size of the ASCII alphabet) #define MULTIBLOCK 1 // Set this definition to `0` for single block, `1` to run the multiblock kernel void checkCUDAError(const char*); void read_encrypted_file(int*); /* 1.1 Modify the `modulo` function so that it can be called on the device by the `affine_decrypt` kernel. */ __device__ int modulo(int a, int m) { int r = a % m; // The remainder operator works differently for negative numbers (as we always want positive output) r = (r < 0) ? r + m : r; // We add `m` to the remainder `r` when `r` is negative, else do nothing return r; } /* 1.2 Implement the decryption kernel for a single block of threads with an `x` dimension of `N` (1024). The function should store the result in `d_output`. You can define the inverse modulus `A`, `B` and `M` using pre-processor definitions. */ __global__ void affine_decrypt(int *d_input, int *d_output) { int i = threadIdx.x; d_output[i] = modulo(A * (d_input[i] - B), M); } /* 1.8 Complete the `affine_decrypt_multiblock` kernel to work using multiple blocks of threads. Change your grid and block dimensions so that you launch 8 blocks of 128 threads. Note: 8 * 128 = 1024. */ __global__ void affine_decrypt_multiblock(int *d_input, int *d_output) { int i = blockIdx.x * blockDim.x + threadIdx.x; d_output[i] = modulo(A * (d_input[i] - B), M); } int main(int argc, char *argv[]) { int *h_input, *h_output; int *d_input, *d_output; unsigned int size; int i; size = N * sizeof(int); // Define the size of the data /* Allocate the host memory */ h_input = (int *)malloc(size); h_output = (int *)malloc(size); /* 1.3 Allocate memory on the device for the input `d_input` and output `d_output` */ cudaMalloc((void **)&d_input, size); cudaMalloc((void **)&d_output, size); checkCUDAError("Memory allocation"); /* Read the encryted text from file to `h_input` */ read_encrypted_file(h_input); /* 1.4 Copy the host input values in `h_input` to the device memory `d_input`. */ cudaMemcpy(d_input, h_input, size, cudaMemcpyHostToDevice); checkCUDAError("Input transfer to device"); /* Configure the grid of thread blocks and run the GPU kernel. */ if (MULTIBLOCK == 0) { // 1.5 Configure a single block of `N` threads and launch the `affine_decrypt` kernel. dim3 blocksPerGrid(1, 1, 1); dim3 threadsPerBlock(N, 1, 1); affine_decrypt <<<blocksPerGrid, threadsPerBlock >>>(d_input, d_output); } else if (MULTIBLOCK == 1) { /* 1.8 Configure 8 blocks of 128 threads and launch the `affine_decrypt_multiblock` kernel */ dim3 blocksPerGrid(8, 1, 1); dim3 threadsPerBlock(N/8, 1, 1); // Note: 8 * 128 = 1024. affine_decrypt_multiblock <<<blocksPerGrid, threadsPerBlock >>>(d_input, d_output); } /* Wait for all threads to complete */ cudaThreadSynchronize(); checkCUDAError("Kernel execution"); /* 1.6 Copy the GPU output back to the host. Copy the device output values in `d_output` to the host memory `h_output`. */ cudaMemcpy(h_output, d_output, size, cudaMemcpyDeviceToHost); checkCUDAError("Result transfer to host"); /* Print out the result to screen */ for (i = 0; i < N; i++) { printf("%c", (char)h_output[i]); } printf("\n"); /* 1.7: Free device memory */ cudaFree(d_input); cudaFree(d_output); checkCUDAError("Free memory"); /* Free host buffers */ free(h_input); free(h_output); return 0; } void checkCUDAError(const char *msg) { cudaError_t err = cudaGetLastError(); if (err != cudaSuccess) { fprintf(stderr, "CUDA ERROR: %s: %s.\n", msg, cudaGetErrorString(err)); exit(EXIT_FAILURE); } } void read_encrypted_file(int* input) { FILE *f = NULL; f = fopen("encrypted1.bin", "rb"); // Read-only and binary flags if (f == NULL) { fprintf(stderr, "Error: Could not find encrypted1.bin file \n"); exit(1); } // Read the encrypted data fread(input, sizeof(unsigned int), N, f); fclose(f); }
code for sm_80 Function : _Z25affine_decrypt_multiblockPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */ /* 0x000e220000002500 */ /*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */ /* 0x001fc800078e0203 */ /*0060*/ IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */ /* 0x000fcc00078e0209 */ /*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 6.616115570068359375e-06 ; /* 0x0000006fff057435 */ /* 0x000fd400000001ff */ /*0090*/ IMAD R0, R2, R5, -0xbb5 ; /* 0xfffff44b02007424 */ /* 0x004fca00078e0205 */ /*00a0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */ /* 0x000fc80000011400 */ /*00b0*/ LEA.HI R5, R5, R0, RZ, 0x7 ; /* 0x0000000005057211 */ /* 0x000fc800078f38ff */ /*00c0*/ LOP3.LUT R5, R5, 0xffffff80, RZ, 0xc0, !PT ; /* 0xffffff8005057812 */ /* 0x000fc800078ec0ff */ /*00d0*/ IADD3 R0, R0, -R5, RZ ; /* 0x8000000500007210 */ /* 0x000fe20007ffe0ff */ /*00e0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */ /* 0x000fc600078e0209 */ /*00f0*/ LOP3.LUT R7, R0, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000000077812 */ /* 0x000fc800078ec0ff */ /*0100*/ LEA.HI R7, R7, R0, RZ, 0x8 ; /* 0x0000000007077211 */ /* 0x000fca00078f40ff */ /*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x000fe2000c101904 */ /*0120*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0130*/ BRA 0x130; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _Z14affine_decryptPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */ /* 0x000e220000002100 */ /*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0040*/ IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */ /* 0x001fcc00078e0209 */ /*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 6.616115570068359375e-06 ; /* 0x0000006fff057435 */ /* 0x000fd400000001ff */ /*0070*/ IMAD R0, R2, R5, -0xbb5 ; /* 0xfffff44b02007424 */ /* 0x004fca00078e0205 */ /*0080*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */ /* 0x000fc80000011400 */ /*0090*/ LEA.HI R5, R5, R0, RZ, 0x7 ; /* 0x0000000005057211 */ /* 0x000fc800078f38ff */ /*00a0*/ LOP3.LUT R5, R5, 0xffffff80, RZ, 0xc0, !PT ; /* 0xffffff8005057812 */ /* 0x000fca00078ec0ff */ /*00b0*/ IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x0000000100007824 */ /* 0x000fe400078e0a05 */ /*00c0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */ /* 0x000fc600078e0209 */ /*00d0*/ LOP3.LUT R7, R0, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000000077812 */ /* 0x000fc800078ec0ff */ /*00e0*/ LEA.HI R7, R7, R0, RZ, 0x8 ; /* 0x0000000007077211 */ /* 0x000fca00078f40ff */ /*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x000fe2000c101904 */ /*0100*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0110*/ BRA 0x110; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
/* Lab 4 Exercise 1 Program In this exercise we write a CUDA program to decipher some text encoded using an affine cipher (in the file `encrypted1.bin`) An affine cipher is a monoalphabetic substitution cipher, and it is decrypted by an affine decipher The encryption function is E(x) = (Ax + B) mod M The decryption function is D(x) = A^{−1}(x − B) mod M In this exercise `M` is 128 (the size of the ASCII alphabet), `A` is 15, `B` is 27, and so `A^{-1}` is 111. As each of the encrypted character values are independent we can use the GPU to decrypt them in parallel. To do this we will launch a thread for each of the encrypted character values and use a kernel function to perform the decryption. */ #include <stdio.h> #include <stdlib.h> #include "cuda_runtime.h" #include "device_launch_parameters.h" #define N 1024 // The number of characters in the encrypted text #define A 111 // The inverse multiplier to the encryption multiplier #define B 27 // The shift value in the encryption function #define M 128 // The modulus of the encryption (the size of the ASCII alphabet) #define MULTIBLOCK 1 // Set this definition to `0` for single block, `1` to run the multiblock kernel void checkCUDAError(const char*); void read_encrypted_file(int*); /* 1.1 Modify the `modulo` function so that it can be called on the device by the `affine_decrypt` kernel. */ __device__ int modulo(int a, int m) { int r = a % m; // The remainder operator works differently for negative numbers (as we always want positive output) r = (r < 0) ? r + m : r; // We add `m` to the remainder `r` when `r` is negative, else do nothing return r; } /* 1.2 Implement the decryption kernel for a single block of threads with an `x` dimension of `N` (1024). The function should store the result in `d_output`. You can define the inverse modulus `A`, `B` and `M` using pre-processor definitions. */ __global__ void affine_decrypt(int *d_input, int *d_output) { int i = threadIdx.x; d_output[i] = modulo(A * (d_input[i] - B), M); } /* 1.8 Complete the `affine_decrypt_multiblock` kernel to work using multiple blocks of threads. Change your grid and block dimensions so that you launch 8 blocks of 128 threads. Note: 8 * 128 = 1024. */ __global__ void affine_decrypt_multiblock(int *d_input, int *d_output) { int i = blockIdx.x * blockDim.x + threadIdx.x; d_output[i] = modulo(A * (d_input[i] - B), M); } int main(int argc, char *argv[]) { int *h_input, *h_output; int *d_input, *d_output; unsigned int size; int i; size = N * sizeof(int); // Define the size of the data /* Allocate the host memory */ h_input = (int *)malloc(size); h_output = (int *)malloc(size); /* 1.3 Allocate memory on the device for the input `d_input` and output `d_output` */ cudaMalloc((void **)&d_input, size); cudaMalloc((void **)&d_output, size); checkCUDAError("Memory allocation"); /* Read the encryted text from file to `h_input` */ read_encrypted_file(h_input); /* 1.4 Copy the host input values in `h_input` to the device memory `d_input`. */ cudaMemcpy(d_input, h_input, size, cudaMemcpyHostToDevice); checkCUDAError("Input transfer to device"); /* Configure the grid of thread blocks and run the GPU kernel. */ if (MULTIBLOCK == 0) { // 1.5 Configure a single block of `N` threads and launch the `affine_decrypt` kernel. dim3 blocksPerGrid(1, 1, 1); dim3 threadsPerBlock(N, 1, 1); affine_decrypt <<<blocksPerGrid, threadsPerBlock >>>(d_input, d_output); } else if (MULTIBLOCK == 1) { /* 1.8 Configure 8 blocks of 128 threads and launch the `affine_decrypt_multiblock` kernel */ dim3 blocksPerGrid(8, 1, 1); dim3 threadsPerBlock(N/8, 1, 1); // Note: 8 * 128 = 1024. affine_decrypt_multiblock <<<blocksPerGrid, threadsPerBlock >>>(d_input, d_output); } /* Wait for all threads to complete */ cudaThreadSynchronize(); checkCUDAError("Kernel execution"); /* 1.6 Copy the GPU output back to the host. Copy the device output values in `d_output` to the host memory `h_output`. */ cudaMemcpy(h_output, d_output, size, cudaMemcpyDeviceToHost); checkCUDAError("Result transfer to host"); /* Print out the result to screen */ for (i = 0; i < N; i++) { printf("%c", (char)h_output[i]); } printf("\n"); /* 1.7: Free device memory */ cudaFree(d_input); cudaFree(d_output); checkCUDAError("Free memory"); /* Free host buffers */ free(h_input); free(h_output); return 0; } void checkCUDAError(const char *msg) { cudaError_t err = cudaGetLastError(); if (err != cudaSuccess) { fprintf(stderr, "CUDA ERROR: %s: %s.\n", msg, cudaGetErrorString(err)); exit(EXIT_FAILURE); } } void read_encrypted_file(int* input) { FILE *f = NULL; f = fopen("encrypted1.bin", "rb"); // Read-only and binary flags if (f == NULL) { fprintf(stderr, "Error: Could not find encrypted1.bin file \n"); exit(1); } // Read the encrypted data fread(input, sizeof(unsigned int), N, f); fclose(f); }
.file "tmpxft_0018d1d2_00000000-6_exercise1.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2063: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2063: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z6moduloii .type _Z6moduloii, @function _Z6moduloii: .LFB2057: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2057: .size _Z6moduloii, .-_Z6moduloii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA ERROR: %s: %s.\n" .text .globl _Z14checkCUDAErrorPKc .type _Z14checkCUDAErrorPKc, @function _Z14checkCUDAErrorPKc: .LFB2059: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx call cudaGetLastError@PLT testl %eax, %eax jne .L8 popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L8: .cfi_restore_state movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %r8 movq %rbx, %rcx leaq .LC0(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .cfi_endproc .LFE2059: .size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc .section .rodata.str1.1 .LC1: .string "rb" .LC2: .string "encrypted1.bin" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC3: .string "Error: Could not find encrypted1.bin file \n" .text .globl _Z19read_encrypted_filePi .type _Z19read_encrypted_filePi, @function _Z19read_encrypted_filePi: .LFB2060: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbp leaq .LC1(%rip), %rsi leaq .LC2(%rip), %rdi call fopen@PLT testq %rax, %rax je .L12 movq %rax, %rbx movq %rax, %r8 movl $1024, %ecx movl $4, %edx movq $-1, %rsi movq %rbp, %rdi call __fread_chk@PLT movq %rbx, %rdi call fclose@PLT addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L12: .cfi_restore_state leaq .LC3(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .cfi_endproc .LFE2060: .size _Z19read_encrypted_filePi, .-_Z19read_encrypted_filePi .globl _Z36__device_stub__Z14affine_decryptPiS_PiS_ .type _Z36__device_stub__Z14affine_decryptPiS_PiS_, @function _Z36__device_stub__Z14affine_decryptPiS_PiS_: .LFB2085: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L17 .L13: movq 104(%rsp), %rax subq %fs:40, %rax jne .L18 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z14affine_decryptPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L13 .L18: call __stack_chk_fail@PLT .cfi_endproc .LFE2085: .size _Z36__device_stub__Z14affine_decryptPiS_PiS_, .-_Z36__device_stub__Z14affine_decryptPiS_PiS_ .globl _Z14affine_decryptPiS_ .type _Z14affine_decryptPiS_, @function _Z14affine_decryptPiS_: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z14affine_decryptPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _Z14affine_decryptPiS_, .-_Z14affine_decryptPiS_ .globl _Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_ .type _Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_, @function _Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_: .LFB2087: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L25 .L21: movq 104(%rsp), %rax subq %fs:40, %rax jne .L26 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L25: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z25affine_decrypt_multiblockPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L21 .L26: call __stack_chk_fail@PLT .cfi_endproc .LFE2087: .size _Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_, .-_Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_ .globl _Z25affine_decrypt_multiblockPiS_ .type _Z25affine_decrypt_multiblockPiS_, @function _Z25affine_decrypt_multiblockPiS_: .LFB2088: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2088: .size _Z25affine_decrypt_multiblockPiS_, .-_Z25affine_decrypt_multiblockPiS_ .section .rodata.str1.1 .LC4: .string "Memory allocation" .LC5: .string "Input transfer to device" .LC6: .string "Kernel execution" .LC7: .string "Result transfer to host" .LC8: .string "%c" .LC9: .string "\n" .LC10: .string "Free memory" .text .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $48, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $4096, %edi call malloc@PLT movq %rax, %r14 movl $4096, %edi call malloc@PLT movq %rax, %r13 movq %rsp, %rdi movl $4096, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq .LC4(%rip), %rdi call _Z14checkCUDAErrorPKc movq %r14, %rdi call _Z19read_encrypted_filePi movl $1, %ecx movl $4096, %edx movq %r14, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT leaq .LC5(%rip), %rdi call _Z14checkCUDAErrorPKc movl $8, 16(%rsp) movl $1, 20(%rsp) movl $128, 28(%rsp) movl $1, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L35 .L30: call cudaThreadSynchronize@PLT leaq .LC6(%rip), %rdi call _Z14checkCUDAErrorPKc movl $2, %ecx movl $4096, %edx movq 8(%rsp), %rsi movq %r13, %rdi call cudaMemcpy@PLT leaq .LC7(%rip), %rdi call _Z14checkCUDAErrorPKc movq %r13, %rbx leaq 4096(%r13), %r12 leaq .LC8(%rip), %rbp .L31: movsbl (%rbx), %edx movq %rbp, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %r12, %rbx jne .L31 leaq .LC9(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT leaq .LC10(%rip), %rdi call _Z14checkCUDAErrorPKc movq %r14, %rdi call free@PLT movq %r13, %rdi call free@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L36 movl $0, %eax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L35: .cfi_restore_state movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_ jmp .L30 .L36: call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.8 .align 8 .LC11: .string "_Z25affine_decrypt_multiblockPiS_" .section .rodata.str1.1 .LC12: .string "_Z14affine_decryptPiS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2090: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC11(%rip), %rdx movq %rdx, %rcx leaq _Z25affine_decrypt_multiblockPiS_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z14affine_decryptPiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2090: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
/* Lab 4 Exercise 1 Program In this exercise we write a CUDA program to decipher some text encoded using an affine cipher (in the file `encrypted1.bin`) An affine cipher is a monoalphabetic substitution cipher, and it is decrypted by an affine decipher The encryption function is E(x) = (Ax + B) mod M The decryption function is D(x) = A^{−1}(x − B) mod M In this exercise `M` is 128 (the size of the ASCII alphabet), `A` is 15, `B` is 27, and so `A^{-1}` is 111. As each of the encrypted character values are independent we can use the GPU to decrypt them in parallel. To do this we will launch a thread for each of the encrypted character values and use a kernel function to perform the decryption. */ #include <stdio.h> #include <stdlib.h> #include "cuda_runtime.h" #include "device_launch_parameters.h" #define N 1024 // The number of characters in the encrypted text #define A 111 // The inverse multiplier to the encryption multiplier #define B 27 // The shift value in the encryption function #define M 128 // The modulus of the encryption (the size of the ASCII alphabet) #define MULTIBLOCK 1 // Set this definition to `0` for single block, `1` to run the multiblock kernel void checkCUDAError(const char*); void read_encrypted_file(int*); /* 1.1 Modify the `modulo` function so that it can be called on the device by the `affine_decrypt` kernel. */ __device__ int modulo(int a, int m) { int r = a % m; // The remainder operator works differently for negative numbers (as we always want positive output) r = (r < 0) ? r + m : r; // We add `m` to the remainder `r` when `r` is negative, else do nothing return r; } /* 1.2 Implement the decryption kernel for a single block of threads with an `x` dimension of `N` (1024). The function should store the result in `d_output`. You can define the inverse modulus `A`, `B` and `M` using pre-processor definitions. */ __global__ void affine_decrypt(int *d_input, int *d_output) { int i = threadIdx.x; d_output[i] = modulo(A * (d_input[i] - B), M); } /* 1.8 Complete the `affine_decrypt_multiblock` kernel to work using multiple blocks of threads. Change your grid and block dimensions so that you launch 8 blocks of 128 threads. Note: 8 * 128 = 1024. */ __global__ void affine_decrypt_multiblock(int *d_input, int *d_output) { int i = blockIdx.x * blockDim.x + threadIdx.x; d_output[i] = modulo(A * (d_input[i] - B), M); } int main(int argc, char *argv[]) { int *h_input, *h_output; int *d_input, *d_output; unsigned int size; int i; size = N * sizeof(int); // Define the size of the data /* Allocate the host memory */ h_input = (int *)malloc(size); h_output = (int *)malloc(size); /* 1.3 Allocate memory on the device for the input `d_input` and output `d_output` */ cudaMalloc((void **)&d_input, size); cudaMalloc((void **)&d_output, size); checkCUDAError("Memory allocation"); /* Read the encryted text from file to `h_input` */ read_encrypted_file(h_input); /* 1.4 Copy the host input values in `h_input` to the device memory `d_input`. */ cudaMemcpy(d_input, h_input, size, cudaMemcpyHostToDevice); checkCUDAError("Input transfer to device"); /* Configure the grid of thread blocks and run the GPU kernel. */ if (MULTIBLOCK == 0) { // 1.5 Configure a single block of `N` threads and launch the `affine_decrypt` kernel. dim3 blocksPerGrid(1, 1, 1); dim3 threadsPerBlock(N, 1, 1); affine_decrypt <<<blocksPerGrid, threadsPerBlock >>>(d_input, d_output); } else if (MULTIBLOCK == 1) { /* 1.8 Configure 8 blocks of 128 threads and launch the `affine_decrypt_multiblock` kernel */ dim3 blocksPerGrid(8, 1, 1); dim3 threadsPerBlock(N/8, 1, 1); // Note: 8 * 128 = 1024. affine_decrypt_multiblock <<<blocksPerGrid, threadsPerBlock >>>(d_input, d_output); } /* Wait for all threads to complete */ cudaThreadSynchronize(); checkCUDAError("Kernel execution"); /* 1.6 Copy the GPU output back to the host. Copy the device output values in `d_output` to the host memory `h_output`. */ cudaMemcpy(h_output, d_output, size, cudaMemcpyDeviceToHost); checkCUDAError("Result transfer to host"); /* Print out the result to screen */ for (i = 0; i < N; i++) { printf("%c", (char)h_output[i]); } printf("\n"); /* 1.7: Free device memory */ cudaFree(d_input); cudaFree(d_output); checkCUDAError("Free memory"); /* Free host buffers */ free(h_input); free(h_output); return 0; } void checkCUDAError(const char *msg) { cudaError_t err = cudaGetLastError(); if (err != cudaSuccess) { fprintf(stderr, "CUDA ERROR: %s: %s.\n", msg, cudaGetErrorString(err)); exit(EXIT_FAILURE); } } void read_encrypted_file(int* input) { FILE *f = NULL; f = fopen("encrypted1.bin", "rb"); // Read-only and binary flags if (f == NULL) { fprintf(stderr, "Error: Could not find encrypted1.bin file \n"); exit(1); } // Read the encrypted data fread(input, sizeof(unsigned int), N, f); fclose(f); }
/* Lab 4 Exercise 1 Program In this exercise we write a CUDA program to decipher some text encoded using an affine cipher (in the file `encrypted1.bin`) An affine cipher is a monoalphabetic substitution cipher, and it is decrypted by an affine decipher The encryption function is E(x) = (Ax + B) mod M The decryption function is D(x) = A^{−1}(x − B) mod M In this exercise `M` is 128 (the size of the ASCII alphabet), `A` is 15, `B` is 27, and so `A^{-1}` is 111. As each of the encrypted character values are independent we can use the GPU to decrypt them in parallel. To do this we will launch a thread for each of the encrypted character values and use a kernel function to perform the decryption. */ #include <stdio.h> #include <stdlib.h> #include "hip/hip_runtime.h" #define N 1024 // The number of characters in the encrypted text #define A 111 // The inverse multiplier to the encryption multiplier #define B 27 // The shift value in the encryption function #define M 128 // The modulus of the encryption (the size of the ASCII alphabet) #define MULTIBLOCK 1 // Set this definition to `0` for single block, `1` to run the multiblock kernel void checkCUDAError(const char*); void read_encrypted_file(int*); /* 1.1 Modify the `modulo` function so that it can be called on the device by the `affine_decrypt` kernel. */ __device__ int modulo(int a, int m) { int r = a % m; // The remainder operator works differently for negative numbers (as we always want positive output) r = (r < 0) ? r + m : r; // We add `m` to the remainder `r` when `r` is negative, else do nothing return r; } /* 1.2 Implement the decryption kernel for a single block of threads with an `x` dimension of `N` (1024). The function should store the result in `d_output`. You can define the inverse modulus `A`, `B` and `M` using pre-processor definitions. */ __global__ void affine_decrypt(int *d_input, int *d_output) { int i = threadIdx.x; d_output[i] = modulo(A * (d_input[i] - B), M); } /* 1.8 Complete the `affine_decrypt_multiblock` kernel to work using multiple blocks of threads. Change your grid and block dimensions so that you launch 8 blocks of 128 threads. Note: 8 * 128 = 1024. */ __global__ void affine_decrypt_multiblock(int *d_input, int *d_output) { int i = blockIdx.x * blockDim.x + threadIdx.x; d_output[i] = modulo(A * (d_input[i] - B), M); } int main(int argc, char *argv[]) { int *h_input, *h_output; int *d_input, *d_output; unsigned int size; int i; size = N * sizeof(int); // Define the size of the data /* Allocate the host memory */ h_input = (int *)malloc(size); h_output = (int *)malloc(size); /* 1.3 Allocate memory on the device for the input `d_input` and output `d_output` */ hipMalloc((void **)&d_input, size); hipMalloc((void **)&d_output, size); checkCUDAError("Memory allocation"); /* Read the encryted text from file to `h_input` */ read_encrypted_file(h_input); /* 1.4 Copy the host input values in `h_input` to the device memory `d_input`. */ hipMemcpy(d_input, h_input, size, hipMemcpyHostToDevice); checkCUDAError("Input transfer to device"); /* Configure the grid of thread blocks and run the GPU kernel. */ if (MULTIBLOCK == 0) { // 1.5 Configure a single block of `N` threads and launch the `affine_decrypt` kernel. dim3 blocksPerGrid(1, 1, 1); dim3 threadsPerBlock(N, 1, 1); affine_decrypt <<<blocksPerGrid, threadsPerBlock >>>(d_input, d_output); } else if (MULTIBLOCK == 1) { /* 1.8 Configure 8 blocks of 128 threads and launch the `affine_decrypt_multiblock` kernel */ dim3 blocksPerGrid(8, 1, 1); dim3 threadsPerBlock(N/8, 1, 1); // Note: 8 * 128 = 1024. affine_decrypt_multiblock <<<blocksPerGrid, threadsPerBlock >>>(d_input, d_output); } /* Wait for all threads to complete */ hipDeviceSynchronize(); checkCUDAError("Kernel execution"); /* 1.6 Copy the GPU output back to the host. Copy the device output values in `d_output` to the host memory `h_output`. */ hipMemcpy(h_output, d_output, size, hipMemcpyDeviceToHost); checkCUDAError("Result transfer to host"); /* Print out the result to screen */ for (i = 0; i < N; i++) { printf("%c", (char)h_output[i]); } printf("\n"); /* 1.7: Free device memory */ hipFree(d_input); hipFree(d_output); checkCUDAError("Free memory"); /* Free host buffers */ free(h_input); free(h_output); return 0; } void checkCUDAError(const char *msg) { hipError_t err = hipGetLastError(); if (err != hipSuccess) { fprintf(stderr, "CUDA ERROR: %s: %s.\n", msg, hipGetErrorString(err)); exit(EXIT_FAILURE); } } void read_encrypted_file(int* input) { FILE *f = NULL; f = fopen("encrypted1.bin", "rb"); // Read-only and binary flags if (f == NULL) { fprintf(stderr, "Error: Could not find encrypted1.bin file \n"); exit(1); } // Read the encrypted data fread(input, sizeof(unsigned int), N, f); fclose(f); }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
/* Lab 4 Exercise 1 Program In this exercise we write a CUDA program to decipher some text encoded using an affine cipher (in the file `encrypted1.bin`) An affine cipher is a monoalphabetic substitution cipher, and it is decrypted by an affine decipher The encryption function is E(x) = (Ax + B) mod M The decryption function is D(x) = A^{−1}(x − B) mod M In this exercise `M` is 128 (the size of the ASCII alphabet), `A` is 15, `B` is 27, and so `A^{-1}` is 111. As each of the encrypted character values are independent we can use the GPU to decrypt them in parallel. To do this we will launch a thread for each of the encrypted character values and use a kernel function to perform the decryption. */ #include <stdio.h> #include <stdlib.h> #include "hip/hip_runtime.h" #define N 1024 // The number of characters in the encrypted text #define A 111 // The inverse multiplier to the encryption multiplier #define B 27 // The shift value in the encryption function #define M 128 // The modulus of the encryption (the size of the ASCII alphabet) #define MULTIBLOCK 1 // Set this definition to `0` for single block, `1` to run the multiblock kernel void checkCUDAError(const char*); void read_encrypted_file(int*); /* 1.1 Modify the `modulo` function so that it can be called on the device by the `affine_decrypt` kernel. */ __device__ int modulo(int a, int m) { int r = a % m; // The remainder operator works differently for negative numbers (as we always want positive output) r = (r < 0) ? r + m : r; // We add `m` to the remainder `r` when `r` is negative, else do nothing return r; } /* 1.2 Implement the decryption kernel for a single block of threads with an `x` dimension of `N` (1024). The function should store the result in `d_output`. You can define the inverse modulus `A`, `B` and `M` using pre-processor definitions. */ __global__ void affine_decrypt(int *d_input, int *d_output) { int i = threadIdx.x; d_output[i] = modulo(A * (d_input[i] - B), M); } /* 1.8 Complete the `affine_decrypt_multiblock` kernel to work using multiple blocks of threads. Change your grid and block dimensions so that you launch 8 blocks of 128 threads. Note: 8 * 128 = 1024. */ __global__ void affine_decrypt_multiblock(int *d_input, int *d_output) { int i = blockIdx.x * blockDim.x + threadIdx.x; d_output[i] = modulo(A * (d_input[i] - B), M); } int main(int argc, char *argv[]) { int *h_input, *h_output; int *d_input, *d_output; unsigned int size; int i; size = N * sizeof(int); // Define the size of the data /* Allocate the host memory */ h_input = (int *)malloc(size); h_output = (int *)malloc(size); /* 1.3 Allocate memory on the device for the input `d_input` and output `d_output` */ hipMalloc((void **)&d_input, size); hipMalloc((void **)&d_output, size); checkCUDAError("Memory allocation"); /* Read the encryted text from file to `h_input` */ read_encrypted_file(h_input); /* 1.4 Copy the host input values in `h_input` to the device memory `d_input`. */ hipMemcpy(d_input, h_input, size, hipMemcpyHostToDevice); checkCUDAError("Input transfer to device"); /* Configure the grid of thread blocks and run the GPU kernel. */ if (MULTIBLOCK == 0) { // 1.5 Configure a single block of `N` threads and launch the `affine_decrypt` kernel. dim3 blocksPerGrid(1, 1, 1); dim3 threadsPerBlock(N, 1, 1); affine_decrypt <<<blocksPerGrid, threadsPerBlock >>>(d_input, d_output); } else if (MULTIBLOCK == 1) { /* 1.8 Configure 8 blocks of 128 threads and launch the `affine_decrypt_multiblock` kernel */ dim3 blocksPerGrid(8, 1, 1); dim3 threadsPerBlock(N/8, 1, 1); // Note: 8 * 128 = 1024. affine_decrypt_multiblock <<<blocksPerGrid, threadsPerBlock >>>(d_input, d_output); } /* Wait for all threads to complete */ hipDeviceSynchronize(); checkCUDAError("Kernel execution"); /* 1.6 Copy the GPU output back to the host. Copy the device output values in `d_output` to the host memory `h_output`. */ hipMemcpy(h_output, d_output, size, hipMemcpyDeviceToHost); checkCUDAError("Result transfer to host"); /* Print out the result to screen */ for (i = 0; i < N; i++) { printf("%c", (char)h_output[i]); } printf("\n"); /* 1.7: Free device memory */ hipFree(d_input); hipFree(d_output); checkCUDAError("Free memory"); /* Free host buffers */ free(h_input); free(h_output); return 0; } void checkCUDAError(const char *msg) { hipError_t err = hipGetLastError(); if (err != hipSuccess) { fprintf(stderr, "CUDA ERROR: %s: %s.\n", msg, hipGetErrorString(err)); exit(EXIT_FAILURE); } } void read_encrypted_file(int* input) { FILE *f = NULL; f = fopen("encrypted1.bin", "rb"); // Read-only and binary flags if (f == NULL) { fprintf(stderr, "Error: Could not find encrypted1.bin file \n"); exit(1); } // Read the encrypted data fread(input, sizeof(unsigned int), N, f); fclose(f); }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14affine_decryptPiS_ .globl _Z14affine_decryptPiS_ .p2align 8 .type _Z14affine_decryptPiS_,@function _Z14affine_decryptPiS_: s_load_b128 s[0:3], s[0:1], 0x0 v_lshlrev_b32_e32 v2, 2, v0 s_waitcnt lgkmcnt(0) global_load_b32 v3, v2, s[0:1] s_movk_i32 s0, 0x6f s_waitcnt vmcnt(0) v_mad_u64_u32 v[0:1], null, v3, s0, 0x4b s_delay_alu instid0(VALU_DEP_1) v_and_b32_e32 v0, 0x7f, v0 global_store_b32 v2, v0, s[2:3] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14affine_decryptPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14affine_decryptPiS_, .Lfunc_end0-_Z14affine_decryptPiS_ .section .AMDGPU.csdata,"",@progbits .text .protected _Z25affine_decrypt_multiblockPiS_ .globl _Z25affine_decrypt_multiblockPiS_ .p2align 8 .type _Z25affine_decrypt_multiblockPiS_,@function _Z25affine_decrypt_multiblockPiS_: s_clause 0x1 s_load_b32 s4, s[0:1], 0x1c s_load_b128 s[0:3], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] v_add_co_u32 v2, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo s_movk_i32 s0, 0x6f v_add_co_u32 v0, vcc_lo, s2, v0 global_load_b32 v4, v[2:3], off v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo s_waitcnt vmcnt(0) v_mad_u64_u32 v[2:3], null, v4, s0, 0x4b s_delay_alu instid0(VALU_DEP_1) v_and_b32_e32 v2, 0x7f, v2 global_store_b32 v[0:1], v2, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z25affine_decrypt_multiblockPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z25affine_decrypt_multiblockPiS_, .Lfunc_end1-_Z25affine_decrypt_multiblockPiS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14affine_decryptPiS_ .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z14affine_decryptPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z25affine_decrypt_multiblockPiS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z25affine_decrypt_multiblockPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
/* Lab 4 Exercise 1 Program In this exercise we write a CUDA program to decipher some text encoded using an affine cipher (in the file `encrypted1.bin`) An affine cipher is a monoalphabetic substitution cipher, and it is decrypted by an affine decipher The encryption function is E(x) = (Ax + B) mod M The decryption function is D(x) = A^{−1}(x − B) mod M In this exercise `M` is 128 (the size of the ASCII alphabet), `A` is 15, `B` is 27, and so `A^{-1}` is 111. As each of the encrypted character values are independent we can use the GPU to decrypt them in parallel. To do this we will launch a thread for each of the encrypted character values and use a kernel function to perform the decryption. */ #include <stdio.h> #include <stdlib.h> #include "hip/hip_runtime.h" #define N 1024 // The number of characters in the encrypted text #define A 111 // The inverse multiplier to the encryption multiplier #define B 27 // The shift value in the encryption function #define M 128 // The modulus of the encryption (the size of the ASCII alphabet) #define MULTIBLOCK 1 // Set this definition to `0` for single block, `1` to run the multiblock kernel void checkCUDAError(const char*); void read_encrypted_file(int*); /* 1.1 Modify the `modulo` function so that it can be called on the device by the `affine_decrypt` kernel. */ __device__ int modulo(int a, int m) { int r = a % m; // The remainder operator works differently for negative numbers (as we always want positive output) r = (r < 0) ? r + m : r; // We add `m` to the remainder `r` when `r` is negative, else do nothing return r; } /* 1.2 Implement the decryption kernel for a single block of threads with an `x` dimension of `N` (1024). The function should store the result in `d_output`. You can define the inverse modulus `A`, `B` and `M` using pre-processor definitions. */ __global__ void affine_decrypt(int *d_input, int *d_output) { int i = threadIdx.x; d_output[i] = modulo(A * (d_input[i] - B), M); } /* 1.8 Complete the `affine_decrypt_multiblock` kernel to work using multiple blocks of threads. Change your grid and block dimensions so that you launch 8 blocks of 128 threads. Note: 8 * 128 = 1024. */ __global__ void affine_decrypt_multiblock(int *d_input, int *d_output) { int i = blockIdx.x * blockDim.x + threadIdx.x; d_output[i] = modulo(A * (d_input[i] - B), M); } int main(int argc, char *argv[]) { int *h_input, *h_output; int *d_input, *d_output; unsigned int size; int i; size = N * sizeof(int); // Define the size of the data /* Allocate the host memory */ h_input = (int *)malloc(size); h_output = (int *)malloc(size); /* 1.3 Allocate memory on the device for the input `d_input` and output `d_output` */ hipMalloc((void **)&d_input, size); hipMalloc((void **)&d_output, size); checkCUDAError("Memory allocation"); /* Read the encryted text from file to `h_input` */ read_encrypted_file(h_input); /* 1.4 Copy the host input values in `h_input` to the device memory `d_input`. */ hipMemcpy(d_input, h_input, size, hipMemcpyHostToDevice); checkCUDAError("Input transfer to device"); /* Configure the grid of thread blocks and run the GPU kernel. */ if (MULTIBLOCK == 0) { // 1.5 Configure a single block of `N` threads and launch the `affine_decrypt` kernel. dim3 blocksPerGrid(1, 1, 1); dim3 threadsPerBlock(N, 1, 1); affine_decrypt <<<blocksPerGrid, threadsPerBlock >>>(d_input, d_output); } else if (MULTIBLOCK == 1) { /* 1.8 Configure 8 blocks of 128 threads and launch the `affine_decrypt_multiblock` kernel */ dim3 blocksPerGrid(8, 1, 1); dim3 threadsPerBlock(N/8, 1, 1); // Note: 8 * 128 = 1024. affine_decrypt_multiblock <<<blocksPerGrid, threadsPerBlock >>>(d_input, d_output); } /* Wait for all threads to complete */ hipDeviceSynchronize(); checkCUDAError("Kernel execution"); /* 1.6 Copy the GPU output back to the host. Copy the device output values in `d_output` to the host memory `h_output`. */ hipMemcpy(h_output, d_output, size, hipMemcpyDeviceToHost); checkCUDAError("Result transfer to host"); /* Print out the result to screen */ for (i = 0; i < N; i++) { printf("%c", (char)h_output[i]); } printf("\n"); /* 1.7: Free device memory */ hipFree(d_input); hipFree(d_output); checkCUDAError("Free memory"); /* Free host buffers */ free(h_input); free(h_output); return 0; } void checkCUDAError(const char *msg) { hipError_t err = hipGetLastError(); if (err != hipSuccess) { fprintf(stderr, "CUDA ERROR: %s: %s.\n", msg, hipGetErrorString(err)); exit(EXIT_FAILURE); } } void read_encrypted_file(int* input) { FILE *f = NULL; f = fopen("encrypted1.bin", "rb"); // Read-only and binary flags if (f == NULL) { fprintf(stderr, "Error: Could not find encrypted1.bin file \n"); exit(1); } // Read the encrypted data fread(input, sizeof(unsigned int), N, f); fclose(f); }
.text .file "exercise1.hip" .globl _Z29__device_stub__affine_decryptPiS_ # -- Begin function _Z29__device_stub__affine_decryptPiS_ .p2align 4, 0x90 .type _Z29__device_stub__affine_decryptPiS_,@function _Z29__device_stub__affine_decryptPiS_: # @_Z29__device_stub__affine_decryptPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z14affine_decryptPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z29__device_stub__affine_decryptPiS_, .Lfunc_end0-_Z29__device_stub__affine_decryptPiS_ .cfi_endproc # -- End function .globl _Z40__device_stub__affine_decrypt_multiblockPiS_ # -- Begin function _Z40__device_stub__affine_decrypt_multiblockPiS_ .p2align 4, 0x90 .type _Z40__device_stub__affine_decrypt_multiblockPiS_,@function _Z40__device_stub__affine_decrypt_multiblockPiS_: # @_Z40__device_stub__affine_decrypt_multiblockPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z25affine_decrypt_multiblockPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end1: .size _Z40__device_stub__affine_decrypt_multiblockPiS_, .Lfunc_end1-_Z40__device_stub__affine_decrypt_multiblockPiS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $96, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $4096, %edi # imm = 0x1000 callq malloc movq %rax, %rbx movl $4096, %edi # imm = 0x1000 callq malloc movq %rax, %r14 leaq 8(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc movq %rsp, %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_1 # %bb.3: # %_Z14checkCUDAErrorPKc.exit movl $.L.str.8, %edi movl $.L.str.9, %esi callq fopen testq %rax, %rax je .LBB2_16 # %bb.4: # %_Z19read_encrypted_filePi.exit movq %rax, %r15 movl $4, %esi movl $1024, %edx # imm = 0x400 movq %rbx, %rdi movq %rax, %rcx callq fread movq %r15, %rdi callq fclose movq 8(%rsp), %rdi movl $4096, %edx # imm = 0x1000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB2_5 # %bb.6: # %_Z14checkCUDAErrorPKc.exit22 movabsq $4294967304, %rdi # imm = 0x100000008 leaq 120(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_8 # %bb.7: movq 8(%rsp), %rax movq (%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z25affine_decrypt_multiblockPiS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_8: callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax jne .LBB2_9 # %bb.10: # %_Z14checkCUDAErrorPKc.exit24 movq (%rsp), %rsi movl $4096, %edx # imm = 0x1000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB2_17 # %bb.11: # %_Z14checkCUDAErrorPKc.exit26.preheader xorl %r15d, %r15d .p2align 4, 0x90 .LBB2_12: # %_Z14checkCUDAErrorPKc.exit26 # =>This Inner Loop Header: Depth=1 movsbl (%r14,%r15,4), %edi callq putchar@PLT incq %r15 cmpq $1024, %r15 # imm = 0x400 jne .LBB2_12 # %bb.13: movl $10, %edi callq putchar@PLT movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree callq hipGetLastError testl %eax, %eax jne .LBB2_14 # %bb.15: # %_Z14checkCUDAErrorPKc.exit28 movq %rbx, %rdi callq free movq %r14, %rdi callq free xorl %eax, %eax addq $96, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB2_1: .cfi_def_cfa_offset 128 movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %esi movl $.L.str, %edx jmp .LBB2_2 .LBB2_16: movq stderr(%rip), %rcx movl $.L.str.10, %edi movl $43, %esi movl $1, %edx callq fwrite@PLT movl $1, %edi callq exit .LBB2_5: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %esi movl $.L.str.1, %edx jmp .LBB2_2 .LBB2_9: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %esi movl $.L.str.2, %edx jmp .LBB2_2 .LBB2_17: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %esi movl $.L.str.3, %edx jmp .LBB2_2 .LBB2_14: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %esi movl $.L.str.6, %edx .LBB2_2: movq %rbx, %rdi movq %rax, %rcx xorl %eax, %eax callq fprintf movl $1, %edi callq exit .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc .p2align 4, 0x90 .type _Z14checkCUDAErrorPKc,@function _Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rdi, %rbx callq hipGetLastError testl %eax, %eax jne .LBB3_2 # %bb.1: addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB3_2: .cfi_def_cfa_offset 32 movq stderr(%rip), %r14 movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %esi movq %r14, %rdi movq %rbx, %rdx movq %rax, %rcx xorl %eax, %eax callq fprintf movl $1, %edi callq exit .Lfunc_end3: .size _Z14checkCUDAErrorPKc, .Lfunc_end3-_Z14checkCUDAErrorPKc .cfi_endproc # -- End function .globl _Z19read_encrypted_filePi # -- Begin function _Z19read_encrypted_filePi .p2align 4, 0x90 .type _Z19read_encrypted_filePi,@function _Z19read_encrypted_filePi: # @_Z19read_encrypted_filePi .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rdi, %rbx movl $.L.str.8, %edi movl $.L.str.9, %esi callq fopen testq %rax, %rax je .LBB4_1 # %bb.2: movq %rax, %r14 movl $4, %esi movl $1024, %edx # imm = 0x400 movq %rbx, %rdi movq %rax, %rcx callq fread movq %r14, %rdi addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 jmp fclose # TAILCALL .LBB4_1: .cfi_def_cfa_offset 32 movq stderr(%rip), %rcx movl $.L.str.10, %edi movl $43, %esi movl $1, %edx callq fwrite@PLT movl $1, %edi callq exit .Lfunc_end4: .size _Z19read_encrypted_filePi, .Lfunc_end4-_Z19read_encrypted_filePi .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB5_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB5_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14affine_decryptPiS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z25affine_decrypt_multiblockPiS_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end5: .size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB6_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB6_2: retq .Lfunc_end6: .size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor .cfi_endproc # -- End function .type _Z14affine_decryptPiS_,@object # @_Z14affine_decryptPiS_ .section .rodata,"a",@progbits .globl _Z14affine_decryptPiS_ .p2align 3, 0x0 _Z14affine_decryptPiS_: .quad _Z29__device_stub__affine_decryptPiS_ .size _Z14affine_decryptPiS_, 8 .type _Z25affine_decrypt_multiblockPiS_,@object # @_Z25affine_decrypt_multiblockPiS_ .globl _Z25affine_decrypt_multiblockPiS_ .p2align 3, 0x0 _Z25affine_decrypt_multiblockPiS_: .quad _Z40__device_stub__affine_decrypt_multiblockPiS_ .size _Z25affine_decrypt_multiblockPiS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Memory allocation" .size .L.str, 18 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Input transfer to device" .size .L.str.1, 25 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Kernel execution" .size .L.str.2, 17 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Result transfer to host" .size .L.str.3, 24 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Free memory" .size .L.str.6, 12 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "CUDA ERROR: %s: %s.\n" .size .L.str.7, 21 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "encrypted1.bin" .size .L.str.8, 15 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "rb" .size .L.str.9, 3 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Error: Could not find encrypted1.bin file \n" .size .L.str.10, 44 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z14affine_decryptPiS_" .size .L__unnamed_1, 23 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z25affine_decrypt_multiblockPiS_" .size .L__unnamed_2, 34 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__affine_decryptPiS_ .addrsig_sym _Z40__device_stub__affine_decrypt_multiblockPiS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14affine_decryptPiS_ .addrsig_sym _Z25affine_decrypt_multiblockPiS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z25affine_decrypt_multiblockPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */ /* 0x000e220000002500 */ /*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe40000000a00 */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */ /* 0x001fc800078e0203 */ /*0060*/ IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */ /* 0x000fcc00078e0209 */ /*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 6.616115570068359375e-06 ; /* 0x0000006fff057435 */ /* 0x000fd400000001ff */ /*0090*/ IMAD R0, R2, R5, -0xbb5 ; /* 0xfffff44b02007424 */ /* 0x004fca00078e0205 */ /*00a0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */ /* 0x000fc80000011400 */ /*00b0*/ LEA.HI R5, R5, R0, RZ, 0x7 ; /* 0x0000000005057211 */ /* 0x000fc800078f38ff */ /*00c0*/ LOP3.LUT R5, R5, 0xffffff80, RZ, 0xc0, !PT ; /* 0xffffff8005057812 */ /* 0x000fc800078ec0ff */ /*00d0*/ IADD3 R0, R0, -R5, RZ ; /* 0x8000000500007210 */ /* 0x000fe20007ffe0ff */ /*00e0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */ /* 0x000fc600078e0209 */ /*00f0*/ LOP3.LUT R7, R0, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000000077812 */ /* 0x000fc800078ec0ff */ /*0100*/ LEA.HI R7, R7, R0, RZ, 0x8 ; /* 0x0000000007077211 */ /* 0x000fca00078f40ff */ /*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x000fe2000c101904 */ /*0120*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0130*/ BRA 0x130; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _Z14affine_decryptPiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */ /* 0x000e220000002100 */ /*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */ /* 0x000fe200078e00ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0040*/ IMAD.WIDE R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */ /* 0x001fcc00078e0209 */ /*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 6.616115570068359375e-06 ; /* 0x0000006fff057435 */ /* 0x000fd400000001ff */ /*0070*/ IMAD R0, R2, R5, -0xbb5 ; /* 0xfffff44b02007424 */ /* 0x004fca00078e0205 */ /*0080*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */ /* 0x000fc80000011400 */ /*0090*/ LEA.HI R5, R5, R0, RZ, 0x7 ; /* 0x0000000005057211 */ /* 0x000fc800078f38ff */ /*00a0*/ LOP3.LUT R5, R5, 0xffffff80, RZ, 0xc0, !PT ; /* 0xffffff8005057812 */ /* 0x000fca00078ec0ff */ /*00b0*/ IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x0000000100007824 */ /* 0x000fe400078e0a05 */ /*00c0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */ /* 0x000fc600078e0209 */ /*00d0*/ LOP3.LUT R7, R0, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000000077812 */ /* 0x000fc800078ec0ff */ /*00e0*/ LEA.HI R7, R7, R0, RZ, 0x8 ; /* 0x0000000007077211 */ /* 0x000fca00078f40ff */ /*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x000fe2000c101904 */ /*0100*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0110*/ BRA 0x110; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14affine_decryptPiS_ .globl _Z14affine_decryptPiS_ .p2align 8 .type _Z14affine_decryptPiS_,@function _Z14affine_decryptPiS_: s_load_b128 s[0:3], s[0:1], 0x0 v_lshlrev_b32_e32 v2, 2, v0 s_waitcnt lgkmcnt(0) global_load_b32 v3, v2, s[0:1] s_movk_i32 s0, 0x6f s_waitcnt vmcnt(0) v_mad_u64_u32 v[0:1], null, v3, s0, 0x4b s_delay_alu instid0(VALU_DEP_1) v_and_b32_e32 v0, 0x7f, v0 global_store_b32 v2, v0, s[2:3] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14affine_decryptPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14affine_decryptPiS_, .Lfunc_end0-_Z14affine_decryptPiS_ .section .AMDGPU.csdata,"",@progbits .text .protected _Z25affine_decrypt_multiblockPiS_ .globl _Z25affine_decrypt_multiblockPiS_ .p2align 8 .type _Z25affine_decrypt_multiblockPiS_,@function _Z25affine_decrypt_multiblockPiS_: s_clause 0x1 s_load_b32 s4, s[0:1], 0x1c s_load_b128 s[0:3], s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s4, s4, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] v_add_co_u32 v2, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo s_movk_i32 s0, 0x6f v_add_co_u32 v0, vcc_lo, s2, v0 global_load_b32 v4, v[2:3], off v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo s_waitcnt vmcnt(0) v_mad_u64_u32 v[2:3], null, v4, s0, 0x4b s_delay_alu instid0(VALU_DEP_1) v_and_b32_e32 v2, 0x7f, v2 global_store_b32 v[0:1], v2, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z25affine_decrypt_multiblockPiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 272 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z25affine_decrypt_multiblockPiS_, .Lfunc_end1-_Z25affine_decrypt_multiblockPiS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14affine_decryptPiS_ .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z14affine_decryptPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: hidden_block_count_x - .offset: 20 .size: 4 .value_kind: hidden_block_count_y - .offset: 24 .size: 4 .value_kind: hidden_block_count_z - .offset: 28 .size: 2 .value_kind: hidden_group_size_x - .offset: 30 .size: 2 .value_kind: hidden_group_size_y - .offset: 32 .size: 2 .value_kind: hidden_group_size_z - .offset: 34 .size: 2 .value_kind: hidden_remainder_x - .offset: 36 .size: 2 .value_kind: hidden_remainder_y - .offset: 38 .size: 2 .value_kind: hidden_remainder_z - .offset: 56 .size: 8 .value_kind: hidden_global_offset_x - .offset: 64 .size: 8 .value_kind: hidden_global_offset_y - .offset: 72 .size: 8 .value_kind: hidden_global_offset_z - .offset: 80 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 272 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z25affine_decrypt_multiblockPiS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z25affine_decrypt_multiblockPiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0018d1d2_00000000-6_exercise1.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2063: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2063: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z6moduloii .type _Z6moduloii, @function _Z6moduloii: .LFB2057: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2057: .size _Z6moduloii, .-_Z6moduloii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "CUDA ERROR: %s: %s.\n" .text .globl _Z14checkCUDAErrorPKc .type _Z14checkCUDAErrorPKc, @function _Z14checkCUDAErrorPKc: .LFB2059: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx call cudaGetLastError@PLT testl %eax, %eax jne .L8 popq %rbx .cfi_remember_state .cfi_def_cfa_offset 8 ret .L8: .cfi_restore_state movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %r8 movq %rbx, %rcx leaq .LC0(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .cfi_endproc .LFE2059: .size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc .section .rodata.str1.1 .LC1: .string "rb" .LC2: .string "encrypted1.bin" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC3: .string "Error: Could not find encrypted1.bin file \n" .text .globl _Z19read_encrypted_filePi .type _Z19read_encrypted_filePi, @function _Z19read_encrypted_filePi: .LFB2060: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $8, %rsp .cfi_def_cfa_offset 32 movq %rdi, %rbp leaq .LC1(%rip), %rsi leaq .LC2(%rip), %rdi call fopen@PLT testq %rax, %rax je .L12 movq %rax, %rbx movq %rax, %r8 movl $1024, %ecx movl $4, %edx movq $-1, %rsi movq %rbp, %rdi call __fread_chk@PLT movq %rbx, %rdi call fclose@PLT addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L12: .cfi_restore_state leaq .LC3(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %edi call exit@PLT .cfi_endproc .LFE2060: .size _Z19read_encrypted_filePi, .-_Z19read_encrypted_filePi .globl _Z36__device_stub__Z14affine_decryptPiS_PiS_ .type _Z36__device_stub__Z14affine_decryptPiS_PiS_, @function _Z36__device_stub__Z14affine_decryptPiS_PiS_: .LFB2085: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L17 .L13: movq 104(%rsp), %rax subq %fs:40, %rax jne .L18 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z14affine_decryptPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L13 .L18: call __stack_chk_fail@PLT .cfi_endproc .LFE2085: .size _Z36__device_stub__Z14affine_decryptPiS_PiS_, .-_Z36__device_stub__Z14affine_decryptPiS_PiS_ .globl _Z14affine_decryptPiS_ .type _Z14affine_decryptPiS_, @function _Z14affine_decryptPiS_: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z14affine_decryptPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _Z14affine_decryptPiS_, .-_Z14affine_decryptPiS_ .globl _Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_ .type _Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_, @function _Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_: .LFB2087: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L25 .L21: movq 104(%rsp), %rax subq %fs:40, %rax jne .L26 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L25: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z25affine_decrypt_multiblockPiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L21 .L26: call __stack_chk_fail@PLT .cfi_endproc .LFE2087: .size _Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_, .-_Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_ .globl _Z25affine_decrypt_multiblockPiS_ .type _Z25affine_decrypt_multiblockPiS_, @function _Z25affine_decrypt_multiblockPiS_: .LFB2088: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2088: .size _Z25affine_decrypt_multiblockPiS_, .-_Z25affine_decrypt_multiblockPiS_ .section .rodata.str1.1 .LC4: .string "Memory allocation" .LC5: .string "Input transfer to device" .LC6: .string "Kernel execution" .LC7: .string "Result transfer to host" .LC8: .string "%c" .LC9: .string "\n" .LC10: .string "Free memory" .text .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $48, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movl $4096, %edi call malloc@PLT movq %rax, %r14 movl $4096, %edi call malloc@PLT movq %rax, %r13 movq %rsp, %rdi movl $4096, %esi call cudaMalloc@PLT leaq 8(%rsp), %rdi movl $4096, %esi call cudaMalloc@PLT leaq .LC4(%rip), %rdi call _Z14checkCUDAErrorPKc movq %r14, %rdi call _Z19read_encrypted_filePi movl $1, %ecx movl $4096, %edx movq %r14, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT leaq .LC5(%rip), %rdi call _Z14checkCUDAErrorPKc movl $8, 16(%rsp) movl $1, 20(%rsp) movl $128, 28(%rsp) movl $1, 32(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L35 .L30: call cudaThreadSynchronize@PLT leaq .LC6(%rip), %rdi call _Z14checkCUDAErrorPKc movl $2, %ecx movl $4096, %edx movq 8(%rsp), %rsi movq %r13, %rdi call cudaMemcpy@PLT leaq .LC7(%rip), %rdi call _Z14checkCUDAErrorPKc movq %r13, %rbx leaq 4096(%r13), %r12 leaq .LC8(%rip), %rbp .L31: movsbl (%rbx), %edx movq %rbp, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %r12, %rbx jne .L31 leaq .LC9(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT leaq .LC10(%rip), %rdi call _Z14checkCUDAErrorPKc movq %r14, %rdi call free@PLT movq %r13, %rdi call free@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L36 movl $0, %eax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L35: .cfi_restore_state movq 8(%rsp), %rsi movq (%rsp), %rdi call _Z47__device_stub__Z25affine_decrypt_multiblockPiS_PiS_ jmp .L30 .L36: call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.8 .align 8 .LC11: .string "_Z25affine_decrypt_multiblockPiS_" .section .rodata.str1.1 .LC12: .string "_Z14affine_decryptPiS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2090: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC11(%rip), %rdx movq %rdx, %rcx leaq _Z25affine_decrypt_multiblockPiS_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z14affine_decryptPiS_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2090: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "exercise1.hip" .globl _Z29__device_stub__affine_decryptPiS_ # -- Begin function _Z29__device_stub__affine_decryptPiS_ .p2align 4, 0x90 .type _Z29__device_stub__affine_decryptPiS_,@function _Z29__device_stub__affine_decryptPiS_: # @_Z29__device_stub__affine_decryptPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z14affine_decryptPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z29__device_stub__affine_decryptPiS_, .Lfunc_end0-_Z29__device_stub__affine_decryptPiS_ .cfi_endproc # -- End function .globl _Z40__device_stub__affine_decrypt_multiblockPiS_ # -- Begin function _Z40__device_stub__affine_decrypt_multiblockPiS_ .p2align 4, 0x90 .type _Z40__device_stub__affine_decrypt_multiblockPiS_,@function _Z40__device_stub__affine_decrypt_multiblockPiS_: # @_Z40__device_stub__affine_decrypt_multiblockPiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z25affine_decrypt_multiblockPiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end1: .size _Z40__device_stub__affine_decrypt_multiblockPiS_, .Lfunc_end1-_Z40__device_stub__affine_decrypt_multiblockPiS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $96, %rsp .cfi_def_cfa_offset 128 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $4096, %edi # imm = 0x1000 callq malloc movq %rax, %rbx movl $4096, %edi # imm = 0x1000 callq malloc movq %rax, %r14 leaq 8(%rsp), %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc movq %rsp, %rdi movl $4096, %esi # imm = 0x1000 callq hipMalloc callq hipGetLastError testl %eax, %eax jne .LBB2_1 # %bb.3: # %_Z14checkCUDAErrorPKc.exit movl $.L.str.8, %edi movl $.L.str.9, %esi callq fopen testq %rax, %rax je .LBB2_16 # %bb.4: # %_Z19read_encrypted_filePi.exit movq %rax, %r15 movl $4, %esi movl $1024, %edx # imm = 0x400 movq %rbx, %rdi movq %rax, %rcx callq fread movq %r15, %rdi callq fclose movq 8(%rsp), %rdi movl $4096, %edx # imm = 0x1000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB2_5 # %bb.6: # %_Z14checkCUDAErrorPKc.exit22 movabsq $4294967304, %rdi # imm = 0x100000008 leaq 120(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_8 # %bb.7: movq 8(%rsp), %rax movq (%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z25affine_decrypt_multiblockPiS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_8: callq hipDeviceSynchronize callq hipGetLastError testl %eax, %eax jne .LBB2_9 # %bb.10: # %_Z14checkCUDAErrorPKc.exit24 movq (%rsp), %rsi movl $4096, %edx # imm = 0x1000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy callq hipGetLastError testl %eax, %eax jne .LBB2_17 # %bb.11: # %_Z14checkCUDAErrorPKc.exit26.preheader xorl %r15d, %r15d .p2align 4, 0x90 .LBB2_12: # %_Z14checkCUDAErrorPKc.exit26 # =>This Inner Loop Header: Depth=1 movsbl (%r14,%r15,4), %edi callq putchar@PLT incq %r15 cmpq $1024, %r15 # imm = 0x400 jne .LBB2_12 # %bb.13: movl $10, %edi callq putchar@PLT movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree callq hipGetLastError testl %eax, %eax jne .LBB2_14 # %bb.15: # %_Z14checkCUDAErrorPKc.exit28 movq %rbx, %rdi callq free movq %r14, %rdi callq free xorl %eax, %eax addq $96, %rsp .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB2_1: .cfi_def_cfa_offset 128 movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %esi movl $.L.str, %edx jmp .LBB2_2 .LBB2_16: movq stderr(%rip), %rcx movl $.L.str.10, %edi movl $43, %esi movl $1, %edx callq fwrite@PLT movl $1, %edi callq exit .LBB2_5: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %esi movl $.L.str.1, %edx jmp .LBB2_2 .LBB2_9: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %esi movl $.L.str.2, %edx jmp .LBB2_2 .LBB2_17: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %esi movl $.L.str.3, %edx jmp .LBB2_2 .LBB2_14: movq stderr(%rip), %rbx movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %esi movl $.L.str.6, %edx .LBB2_2: movq %rbx, %rdi movq %rax, %rcx xorl %eax, %eax callq fprintf movl $1, %edi callq exit .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc .p2align 4, 0x90 .type _Z14checkCUDAErrorPKc,@function _Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rdi, %rbx callq hipGetLastError testl %eax, %eax jne .LBB3_2 # %bb.1: addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB3_2: .cfi_def_cfa_offset 32 movq stderr(%rip), %r14 movl %eax, %edi callq hipGetErrorString movl $.L.str.7, %esi movq %r14, %rdi movq %rbx, %rdx movq %rax, %rcx xorl %eax, %eax callq fprintf movl $1, %edi callq exit .Lfunc_end3: .size _Z14checkCUDAErrorPKc, .Lfunc_end3-_Z14checkCUDAErrorPKc .cfi_endproc # -- End function .globl _Z19read_encrypted_filePi # -- Begin function _Z19read_encrypted_filePi .p2align 4, 0x90 .type _Z19read_encrypted_filePi,@function _Z19read_encrypted_filePi: # @_Z19read_encrypted_filePi .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movq %rdi, %rbx movl $.L.str.8, %edi movl $.L.str.9, %esi callq fopen testq %rax, %rax je .LBB4_1 # %bb.2: movq %rax, %r14 movl $4, %esi movl $1024, %edx # imm = 0x400 movq %rbx, %rdi movq %rax, %rcx callq fread movq %r14, %rdi addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 jmp fclose # TAILCALL .LBB4_1: .cfi_def_cfa_offset 32 movq stderr(%rip), %rcx movl $.L.str.10, %edi movl $43, %esi movl $1, %edx callq fwrite@PLT movl $1, %edi callq exit .Lfunc_end4: .size _Z19read_encrypted_filePi, .Lfunc_end4-_Z19read_encrypted_filePi .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB5_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB5_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14affine_decryptPiS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z25affine_decrypt_multiblockPiS_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end5: .size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB6_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB6_2: retq .Lfunc_end6: .size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor .cfi_endproc # -- End function .type _Z14affine_decryptPiS_,@object # @_Z14affine_decryptPiS_ .section .rodata,"a",@progbits .globl _Z14affine_decryptPiS_ .p2align 3, 0x0 _Z14affine_decryptPiS_: .quad _Z29__device_stub__affine_decryptPiS_ .size _Z14affine_decryptPiS_, 8 .type _Z25affine_decrypt_multiblockPiS_,@object # @_Z25affine_decrypt_multiblockPiS_ .globl _Z25affine_decrypt_multiblockPiS_ .p2align 3, 0x0 _Z25affine_decrypt_multiblockPiS_: .quad _Z40__device_stub__affine_decrypt_multiblockPiS_ .size _Z25affine_decrypt_multiblockPiS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Memory allocation" .size .L.str, 18 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Input transfer to device" .size .L.str.1, 25 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Kernel execution" .size .L.str.2, 17 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Result transfer to host" .size .L.str.3, 24 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "Free memory" .size .L.str.6, 12 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "CUDA ERROR: %s: %s.\n" .size .L.str.7, 21 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "encrypted1.bin" .size .L.str.8, 15 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "rb" .size .L.str.9, 3 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Error: Could not find encrypted1.bin file \n" .size .L.str.10, 44 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z14affine_decryptPiS_" .size .L__unnamed_1, 23 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z25affine_decrypt_multiblockPiS_" .size .L__unnamed_2, 34 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__affine_decryptPiS_ .addrsig_sym _Z40__device_stub__affine_decrypt_multiblockPiS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14affine_decryptPiS_ .addrsig_sym _Z25affine_decrypt_multiblockPiS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" extern "C" { } #define TB 256 #define EPS 0.1 #undef MIN #define MIN(a, b) ((a) < (b) ? (a) : (b)) #undef MAX #define MAX(a, b) ((a) > (b) ? (a) : (b)) __global__ void Ring2_kernel( float *A, float *BP, int *corrAB, int *mask, int *m, int ring, int c, int h, int w ) { int id1 = blockIdx.x * blockDim.x + threadIdx.x; int size = h * w; if (id1 < size) { // int y1 = id1 / w, x1 = id1 % w; if (mask[id1] != 0) { int y2 = corrAB[2 * id1 + 1], x2 = corrAB[2 * id1 + 0]; for (int dx = -ring; dx <= ring; dx++) for (int dy = -ring; dy <= ring; dy++) { int _x2 = x2 + dx, _y2 = y2 + dy; if (_x2 >= 0 && _x2 < w && _y2 >= 0 && _y2 < h) { m[_y2 * w + _x2] = 1; } } } } return ; }
code for sm_80 Function : _Z12Ring2_kernelPfS_PiS0_S0_iiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x190] ; /* 0x0000640000047ab9 */ /* 0x000fe40000000a00 */ /*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */ /* 0x000fe2000f8e023f */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */ /* 0x001fca00078e0203 */ /*0060*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */ /* 0x000fda000bf06270 */ /*0070*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */ /* 0x000fe200078e00ff */ /*0090*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */ /* 0x000fc60000000a00 */ /*00a0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x178] ; /* 0x00005e0004027625 */ /* 0x000fcc00078e0205 */ /*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */ /* 0x000ea4000c1e1900 */ /*00c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x004fda0003f05270 */ /*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*00e0*/ IMAD.MOV R0, RZ, RZ, -c[0x0][0x188] ; /* 0x80006200ff007624 */ /* 0x000fe400078e02ff */ /*00f0*/ IMAD.SHL.U32 R2, R4, 0x2, RZ ; /* 0x0000000204027824 */ /* 0x000fc600078e00ff */ /*0100*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */ /* 0x000fe20003f04270 */ /*0110*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */ /* 0x000fd800078e0205 */ /*0120*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0130*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000408020a7981 */ /* 0x000ea8000c1e1900 */ /*0140*/ LDG.E R11, [R2.64] ; /* 0x00000008020b7981 */ /* 0x000162000c1e1900 */ /*0150*/ IMNMX R13, R0, c[0x0][0x188], !PT ; /* 0x00006200000d7a17 */ /* 0x000fe20007800200 */ /*0160*/ ULDC UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */ /* 0x000fe20000000800 */ /*0170*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */ /* 0x000fe200078e0000 */ /*0180*/ UIADD3 UR5, -UR4, 0x1, URZ ; /* 0x0000000104057890 */ /* 0x000fe2000fffe13f */ /*0190*/ IADD3 R13, R13, c[0x0][0x188], RZ ; /* 0x000062000d0d7a10 */ /* 0x000fe20007ffe0ff */ /*01a0*/ UIADD3 UR6, -UR4, 0x2, URZ ; /* 0x0000000204067890 */ /* 0x000fc4000fffe13f */ /*01b0*/ UIADD3 UR4, -UR4, 0x3, URZ ; /* 0x0000000304047890 */ /* 0x000fe2000fffe13f */ /*01c0*/ IADD3 R20, R13, 0x1, RZ ; /* 0x000000010d147810 */ /* 0x000fc80007ffe0ff */ /*01d0*/ LOP3.LUT R20, R20, 0x3, RZ, 0xc0, !PT ; /* 0x0000000314147812 */ /* 0x000fe400078ec0ff */ /*01e0*/ IADD3 R14, R10.reuse, -c[0x0][0x188], RZ ; /* 0x800062000a0e7a10 */ /* 0x044fe40007ffe0ff */ /*01f0*/ IADD3 R15, R10.reuse, 0x3, RZ ; /* 0x000000030a0f7810 */ /* 0x040fe40007ffe0ff */ /*0200*/ IADD3 R16, R10.reuse, 0x2, RZ ; /* 0x000000020a107810 */ /* 0x040fe40007ffe0ff */ /*0210*/ IADD3 R17, R10.reuse, 0x1, RZ ; /* 0x000000010a117810 */ /* 0x040fe40007ffe0ff */ /*0220*/ IADD3 R18, R10, UR5, RZ ; /* 0x000000050a127c10 */ /* 0x000fc4000fffe0ff */ /*0230*/ IADD3 R19, R10, UR6, RZ ; /* 0x000000060a137c10 */ /* 0x001fe4000fffe0ff */ /*0240*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */ /* 0x000fe20003f05270 */ /*0250*/ IMAD.IADD R21, R11, 0x1, R12 ; /* 0x000000010b157824 */ /* 0x020fe200078e020c */ /*0260*/ ISETP.GE.AND P4, PT, R12.reuse, c[0x0][0x188], PT ; /* 0x000062000c007a0c */ /* 0x040fe20003f86270 */ /*0270*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */ /* 0x001fe200078e0000 */ /*0280*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */ /* 0x000fd20007ffe0ff */ /*0290*/ @!P0 BRA 0x4a0 ; /* 0x0000020000008947 */ /* 0x000fea0003800000 */ /*02a0*/ ISETP.GE.AND P0, PT, R21, c[0x0][0x194], PT ; /* 0x0000650015007a0c */ /* 0x000fe20003f06270 */ /*02b0*/ IMAD.U32 R4, RZ, RZ, UR5 ; /* 0x00000005ff047e24 */ /* 0x000fe2000f8e00ff */ /*02c0*/ LOP3.LUT R2, R14, R21, RZ, 0xfc, !PT ; /* 0x000000150e027212 */ /* 0x000fc800078efcff */ /*02d0*/ ISETP.LT.OR P1, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */ /* 0x000fc80000721670 */ /*02e0*/ ISETP.GE.OR P1, PT, R14, c[0x0][0x190], P1 ; /* 0x000064000e007a0c */ /* 0x000fda0000f26670 */ /*02f0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */ /* 0x000fe400078e00ff */ /*0300*/ @!P1 IMAD R2, R14, c[0x0][0x194], R21 ; /* 0x000065000e029a24 */ /* 0x000fe400078e0215 */ /*0310*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff059424 */ /* 0x000fe400078e00ff */ /*0320*/ @!P1 IMAD.WIDE R2, R2, R3, c[0x0][0x180] ; /* 0x0000600002029625 */ /* 0x000fca00078e0203 */ /*0330*/ @!P1 STG.E [R2.64], R5 ; /* 0x0000000502009986 */ /* 0x0001e2000c101908 */ /*0340*/ ISETP.NE.AND P1, PT, R20, 0x1, PT ; /* 0x000000011400780c */ /* 0x000fda0003f25270 */ /*0350*/ @!P1 BRA 0x4a0 ; /* 0x0000014000009947 */ /* 0x000fea0003800000 */ /*0360*/ LOP3.LUT R2, R18, R21, RZ, 0xfc, !PT ; /* 0x0000001512027212 */ /* 0x001fe200078efcff */ /*0370*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */ /* 0x000fc6000f8e00ff */ /*0380*/ ISETP.LT.OR P1, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */ /* 0x000fc80000721670 */ /*0390*/ ISETP.GE.OR P1, PT, R18, c[0x0][0x190], P1 ; /* 0x0000640012007a0c */ /* 0x000fda0000f26670 */ /*03a0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */ /* 0x000fe400078e00ff */ /*03b0*/ @!P1 IMAD R2, R18, c[0x0][0x194], R21 ; /* 0x0000650012029a24 */ /* 0x000fe400078e0215 */ /*03c0*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff059424 */ /* 0x000fe400078e00ff */ /*03d0*/ @!P1 IMAD.WIDE R2, R2, R3, c[0x0][0x180] ; /* 0x0000600002029625 */ /* 0x000fca00078e0203 */ /*03e0*/ @!P1 STG.E [R2.64], R5 ; /* 0x0000000502009986 */ /* 0x0001e2000c101908 */ /*03f0*/ ISETP.NE.AND P1, PT, R20, 0x2, PT ; /* 0x000000021400780c */ /* 0x000fda0003f25270 */ /*0400*/ @!P1 BRA 0x4a0 ; /* 0x0000009000009947 */ /* 0x000fea0003800000 */ /*0410*/ LOP3.LUT R2, R19, R21, RZ, 0xfc, !PT ; /* 0x0000001513027212 */ /* 0x001fe200078efcff */ /*0420*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */ /* 0x000fc6000f8e00ff */ /*0430*/ ISETP.LT.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */ /* 0x000fc80000701670 */ /*0440*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x190], P0 ; /* 0x0000640013007a0c */ /* 0x000fda0000706670 */ /*0450*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */ /* 0x000fe400078e00ff */ /*0460*/ @!P0 IMAD R2, R19, c[0x0][0x194], R21 ; /* 0x0000650013028a24 */ /* 0x000fe400078e0215 */ /*0470*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff058424 */ /* 0x000fe400078e00ff */ /*0480*/ @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x180] ; /* 0x0000600002028625 */ /* 0x000fca00078e0203 */ /*0490*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */ /* 0x0001e4000c101908 */ /*04a0*/ ISETP.GE.U32.AND P0, PT, R13, 0x3, PT ; /* 0x000000030d00780c */ /* 0x001fda0003f06070 */ /*04b0*/ @!P0 BRA 0x7e0 ; /* 0x0000032000008947 */ /* 0x000fea0003800000 */ /*04c0*/ IADD3 R24, R15, R4, RZ ; /* 0x000000040f187210 */ /* 0x000fe20007ffe0ff */ /*04d0*/ IMAD.IADD R2, R16, 0x1, R4.reuse ; /* 0x0000000110027824 */ /* 0x100fe200078e0204 */ /*04e0*/ ISETP.GE.AND P5, PT, R21, c[0x0][0x194], PT ; /* 0x0000650015007a0c */ /* 0x000fe20003fa6270 */ /*04f0*/ IMAD.IADD R6, R17, 0x1, R4.reuse ; /* 0x0000000111067824 */ /* 0x100fe200078e0204 */ /*0500*/ IADD3 R23, R4, -0x1, RZ ; /* 0xffffffff04177810 */ /* 0x000fe20007ffe0ff */ /*0510*/ IMAD.IADD R22, R10, 0x1, R4 ; /* 0x000000010a167824 */ /* 0x000fe400078e0204 */ /*0520*/ IMAD R24, R24, c[0x0][0x194], R21.reuse ; /* 0x0000650018187a24 */ /* 0x100fe400078e0215 */ /*0530*/ IMAD R25, R2, c[0x0][0x194], R21.reuse ; /* 0x0000650002197a24 */ /* 0x100fe400078e0215 */ /*0540*/ IMAD R27, R6, c[0x0][0x194], R21 ; /* 0x00006500061b7a24 */ /* 0x000fc400078e0215 */ /*0550*/ IMAD R26, R22, c[0x0][0x194], R21 ; /* 0x00006500161a7a24 */ /* 0x000fe400078e0215 */ /*0560*/ LOP3.LUT R3, R22.reuse, R21.reuse, RZ, 0xfc, !PT ; /* 0x0000001516037212 */ /* 0x0c1fe400078efcff */ /*0570*/ IADD3 R2, R22, 0x1, RZ ; /* 0x0000000116027810 */ /* 0x000fe40007ffe0ff */ /*0580*/ ISETP.LT.OR P0, PT, R3, RZ, P5 ; /* 0x000000ff0300720c */ /* 0x000fe40002f01670 */ /*0590*/ LOP3.LUT R3, R2, R21, RZ, 0xfc, !PT ; /* 0x0000001502037212 */ /* 0x000fe400078efcff */ /*05a0*/ IADD3 R4, R22, 0x2, RZ ; /* 0x0000000216047810 */ /* 0x000fe40007ffe0ff */ /*05b0*/ ISETP.LT.OR P1, PT, R3, RZ, P5 ; /* 0x000000ff0300720c */ /* 0x000fc40002f21670 */ /*05c0*/ IADD3 R6, R22, 0x3, RZ ; /* 0x0000000316067810 */ /* 0x000fe40007ffe0ff */ /*05d0*/ ISETP.GE.OR P1, PT, R2, c[0x0][0x190], P1 ; /* 0x0000640002007a0c */ /* 0x000fe40000f26670 */ /*05e0*/ LOP3.LUT R2, R4, R21.reuse, RZ, 0xfc, !PT ; /* 0x0000001504027212 */ /* 0x080fe400078efcff */ /*05f0*/ LOP3.LUT R3, R6, R21, RZ, 0xfc, !PT ; /* 0x0000001506037212 */ /* 0x000fe400078efcff */ /*0600*/ ISETP.GE.OR P0, PT, R22, c[0x0][0x190], P0 ; /* 0x0000640016007a0c */ /* 0x000fe40000706670 */ /*0610*/ ISETP.LT.OR P3, PT, R2, RZ, P5 ; /* 0x000000ff0200720c */ /* 0x000fc40002f61670 */ /*0620*/ ISETP.LT.OR P2, PT, R3, RZ, P5 ; /* 0x000000ff0300720c */ /* 0x000fe40002f41670 */ /*0630*/ ISETP.GE.OR P3, PT, R4, c[0x0][0x190], P3 ; /* 0x0000640004007a0c */ /* 0x000fe20001f66670 */ /*0640*/ @!P1 IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff089424 */ /* 0x000fe200078e00ff */ /*0650*/ ISETP.GE.OR P2, PT, R6, c[0x0][0x190], P2 ; /* 0x0000640006007a0c */ /* 0x000fe20001746670 */ /*0660*/ @!P1 IMAD.MOV.U32 R28, RZ, RZ, 0x1 ; /* 0x00000001ff1c9424 */ /* 0x000fe200078e00ff */ /*0670*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */ /* 0x000fe20007ffe0ff */ /*0680*/ @!P1 IMAD.WIDE R8, R27, R8, c[0x0][0x180] ; /* 0x000060001b089625 */ /* 0x000fe200078e0208 */ /*0690*/ IADD3 R22, R22, 0x4, RZ ; /* 0x0000000416167810 */ /* 0x000fc60007ffe0ff */ /*06a0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff078424 */ /* 0x000fe400078e00ff */ /*06b0*/ @!P0 IMAD.MOV.U32 R29, RZ, RZ, 0x1 ; /* 0x00000001ff1d8424 */ /* 0x000fe400078e00ff */ /*06c0*/ @!P0 IMAD.WIDE R6, R26, R7, c[0x0][0x180] ; /* 0x000060001a068625 */ /* 0x000fe400078e0207 */ /*06d0*/ @!P2 MOV R5, 0x4 ; /* 0x000000040005a802 */ /* 0x000fe40000000f00 */ /*06e0*/ @!P3 IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff02b424 */ /* 0x000fe200078e00ff */ /*06f0*/ @!P0 STG.E [R6.64], R29 ; /* 0x0000001d06008986 */ /* 0x0001e2000c101908 */ /*0700*/ ISETP.GE.AND P0, PT, R23, c[0x0][0x188], PT ; /* 0x0000620017007a0c */ /* 0x000fe20003f06270 */ /*0710*/ @!P2 IMAD.WIDE R4, R24, R5, c[0x0][0x180] ; /* 0x000060001804a625 */ /* 0x000fc400078e0205 */ /*0720*/ @!P1 STG.E [R8.64], R28 ; /* 0x0000001c08009986 */ /* 0x0003e4000c101908 */ /*0730*/ @!P3 IMAD.WIDE R2, R25, R2, c[0x0][0x180] ; /* 0x000060001902b625 */ /* 0x000fc800078e0202 */ /*0740*/ @!P3 IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff07b424 */ /* 0x001fe400078e00ff */ /*0750*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff067624 */ /* 0x000fe400078e00ff */ /*0760*/ @!P2 IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff09a424 */ /* 0x002fe200078e00ff */ /*0770*/ @!P3 STG.E [R2.64], R7 ; /* 0x000000070200b986 */ /* 0x0001e2000c101908 */ /*0780*/ IMAD R26, R6.reuse, 0x4, R26 ; /* 0x00000004061a7824 */ /* 0x040fe400078e021a */ /*0790*/ IMAD R24, R6.reuse, 0x4, R24 ; /* 0x0000000406187824 */ /* 0x040fe200078e0218 */ /*07a0*/ @!P2 STG.E [R4.64], R9 ; /* 0x000000090400a986 */ /* 0x0001e2000c101908 */ /*07b0*/ IMAD R25, R6, 0x4, R25 ; /* 0x0000000406197824 */ /* 0x000fc400078e0219 */ /*07c0*/ IMAD R27, R6, 0x4, R27 ; /* 0x00000004061b7824 */ /* 0x000fe200078e021b */ /*07d0*/ @!P0 BRA 0x560 ; /* 0xfffffd8000008947 */ /* 0x000fea000383ffff */ /*07e0*/ @!P4 BRA 0x240 ; /* 0xfffffa500000c947 */ /* 0x000fea000383ffff */ /*07f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0800*/ BRA 0x800; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0810*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0820*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0830*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0840*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0850*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0860*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0870*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0880*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0890*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" extern "C" { } #define TB 256 #define EPS 0.1 #undef MIN #define MIN(a, b) ((a) < (b) ? (a) : (b)) #undef MAX #define MAX(a, b) ((a) > (b) ? (a) : (b)) __global__ void Ring2_kernel( float *A, float *BP, int *corrAB, int *mask, int *m, int ring, int c, int h, int w ) { int id1 = blockIdx.x * blockDim.x + threadIdx.x; int size = h * w; if (id1 < size) { // int y1 = id1 / w, x1 = id1 % w; if (mask[id1] != 0) { int y2 = corrAB[2 * id1 + 1], x2 = corrAB[2 * id1 + 0]; for (int dx = -ring; dx <= ring; dx++) for (int dy = -ring; dy <= ring; dy++) { int _x2 = x2 + dx, _y2 = y2 + dy; if (_x2 >= 0 && _x2 < w && _y2 >= 0 && _y2 < h) { m[_y2 * w + _x2] = 1; } } } } return ; }
.file "tmpxft_0003ff80_00000000-6_Ring2_kernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z46__device_stub__Z12Ring2_kernelPfS_PiS0_S0_iiiiPfS_PiS0_S0_iiii .type _Z46__device_stub__Z12Ring2_kernelPfS_PiS0_S0_iiiiPfS_PiS0_S0_iiii, @function _Z46__device_stub__Z12Ring2_kernelPfS_PiS0_S0_iiiiPfS_PiS0_S0_iiii: .LFB2051: .cfi_startproc endbr64 subq $200, %rsp .cfi_def_cfa_offset 208 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movq %r8, 8(%rsp) movl %r9d, 4(%rsp) movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) leaq 4(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 184(%rsp), %rax subq %fs:40, %rax jne .L8 addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 216 pushq 56(%rsp) .cfi_def_cfa_offset 224 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z12Ring2_kernelPfS_PiS0_S0_iiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 208 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z46__device_stub__Z12Ring2_kernelPfS_PiS0_S0_iiiiPfS_PiS0_S0_iiii, .-_Z46__device_stub__Z12Ring2_kernelPfS_PiS0_S0_iiiiPfS_PiS0_S0_iiii .globl _Z12Ring2_kernelPfS_PiS0_S0_iiii .type _Z12Ring2_kernelPfS_PiS0_S0_iiii, @function _Z12Ring2_kernelPfS_PiS0_S0_iiii: .LFB2052: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 call _Z46__device_stub__Z12Ring2_kernelPfS_PiS0_S0_iiiiPfS_PiS0_S0_iiii addq $40, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z12Ring2_kernelPfS_PiS0_S0_iiii, .-_Z12Ring2_kernelPfS_PiS0_S0_iiii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z12Ring2_kernelPfS_PiS0_S0_iiii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z12Ring2_kernelPfS_PiS0_S0_iiii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" extern "C" { } #define TB 256 #define EPS 0.1 #undef MIN #define MIN(a, b) ((a) < (b) ? (a) : (b)) #undef MAX #define MAX(a, b) ((a) > (b) ? (a) : (b)) __global__ void Ring2_kernel( float *A, float *BP, int *corrAB, int *mask, int *m, int ring, int c, int h, int w ) { int id1 = blockIdx.x * blockDim.x + threadIdx.x; int size = h * w; if (id1 < size) { // int y1 = id1 / w, x1 = id1 % w; if (mask[id1] != 0) { int y2 = corrAB[2 * id1 + 1], x2 = corrAB[2 * id1 + 0]; for (int dx = -ring; dx <= ring; dx++) for (int dy = -ring; dy <= ring; dy++) { int _x2 = x2 + dx, _y2 = y2 + dy; if (_x2 >= 0 && _x2 < w && _y2 >= 0 && _y2 < h) { m[_y2 * w + _x2] = 1; } } } } return ; }
#include <hip/hip_runtime.h> #include "includes.h" extern "C" { } #define TB 256 #define EPS 0.1 #undef MIN #define MIN(a, b) ((a) < (b) ? (a) : (b)) #undef MAX #define MAX(a, b) ((a) > (b) ? (a) : (b)) __global__ void Ring2_kernel( float *A, float *BP, int *corrAB, int *mask, int *m, int ring, int c, int h, int w ) { int id1 = blockIdx.x * blockDim.x + threadIdx.x; int size = h * w; if (id1 < size) { // int y1 = id1 / w, x1 = id1 % w; if (mask[id1] != 0) { int y2 = corrAB[2 * id1 + 1], x2 = corrAB[2 * id1 + 0]; for (int dx = -ring; dx <= ring; dx++) for (int dy = -ring; dy <= ring; dy++) { int _x2 = x2 + dx, _y2 = y2 + dy; if (_x2 >= 0 && _x2 < w && _y2 >= 0 && _y2 < h) { m[_y2 * w + _x2] = 1; } } } } return ; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" extern "C" { } #define TB 256 #define EPS 0.1 #undef MIN #define MIN(a, b) ((a) < (b) ? (a) : (b)) #undef MAX #define MAX(a, b) ((a) > (b) ? (a) : (b)) __global__ void Ring2_kernel( float *A, float *BP, int *corrAB, int *mask, int *m, int ring, int c, int h, int w ) { int id1 = blockIdx.x * blockDim.x + threadIdx.x; int size = h * w; if (id1 < size) { // int y1 = id1 / w, x1 = id1 % w; if (mask[id1] != 0) { int y2 = corrAB[2 * id1 + 1], x2 = corrAB[2 * id1 + 0]; for (int dx = -ring; dx <= ring; dx++) for (int dy = -ring; dy <= ring; dy++) { int _x2 = x2 + dx, _y2 = y2 + dy; if (_x2 >= 0 && _x2 < w && _y2 >= 0 && _y2 < h) { m[_y2 * w + _x2] = 1; } } } } return ; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z12Ring2_kernelPfS_PiS0_S0_iiii .globl _Z12Ring2_kernelPfS_PiS0_S0_iiii .p2align 8 .type _Z12Ring2_kernelPfS_PiS0_S0_iiii,@function _Z12Ring2_kernelPfS_PiS0_S0_iiii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x44 s_load_b64 s[4:5], s[0:1], 0x30 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mul_i32 s2, s5, s4 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s2, v1 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_9 s_load_b64 s[2:3], s[0:1], 0x18 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s2, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b32 v0, v[2:3], off s_waitcnt vmcnt(0) v_cmp_ne_u32_e32 vcc_lo, 0, v0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_9 s_load_b32 s3, s[0:1], 0x28 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s3, 0 s_cbranch_scc1 .LBB0_9 v_dual_mov_b32 v5, 1 :: v_dual_lshlrev_b32 v0, 1, v1 s_clause 0x1 s_load_b64 s[8:9], s[0:1], 0x10 s_load_b64 s[6:7], s[0:1], 0x20 s_lshl_b32 s0, s3, 1 v_or_b32_e32 v2, 1, v0 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[0:1], 2, v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s8, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo v_add_co_u32 v0, vcc_lo, s8, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo s_clause 0x1 global_load_b32 v2, v[2:3], off global_load_b32 v0, v[0:1], off s_sub_i32 s9, 0, s3 s_or_b32 s8, s0, 1 s_waitcnt vmcnt(1) v_subrev_nc_u32_e32 v3, s3, v2 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s5, v3, v[0:1] v_subrev_nc_u32_e32 v4, s3, v1 s_set_inst_prefetch_distance 0x1 s_branch .LBB0_5 .p2align 6 .LBB0_4: v_add_nc_u32_e32 v4, 1, v4 s_add_i32 s0, s9, 1 s_cmp_eq_u32 s9, s3 s_mov_b32 s9, s0 s_cbranch_scc1 .LBB0_9 .LBB0_5: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_dual_mov_b32 v1, v4 :: v_dual_add_nc_u32 v2, s9, v0 v_mov_b32_e32 v6, v3 s_mov_b32 s10, s8 v_cmp_lt_i32_e32 vcc_lo, -1, v2 v_cmp_gt_i32_e64 s0, s5, v2 s_branch .LBB0_7 .p2align 6 .LBB0_6: s_or_b32 exec_lo, exec_lo, s2 v_add_nc_u32_e32 v6, 1, v6 v_add_nc_u32_e32 v1, s5, v1 s_add_i32 s10, s10, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s10, 0 s_cbranch_scc1 .LBB0_4 .LBB0_7: v_cmp_lt_i32_e64 s1, -1, v6 v_cmp_gt_i32_e64 s2, s4, v6 s_delay_alu instid0(VALU_DEP_2) s_and_b32 s1, s0, s1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s1, s1, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s1, vcc_lo, s1 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB0_6 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[1:2] v_add_co_u32 v7, s1, s6, v7 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v8, s1, s7, v8, s1 global_store_b32 v[7:8], v5, off s_branch .LBB0_6 .LBB0_9: s_set_inst_prefetch_distance 0x2 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12Ring2_kernelPfS_PiS0_S0_iiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 312 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z12Ring2_kernelPfS_PiS0_S0_iiii, .Lfunc_end0-_Z12Ring2_kernelPfS_PiS0_S0_iiii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: by_value - .offset: 44 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: by_value - .offset: 52 .size: 4 .value_kind: by_value - .offset: 56 .size: 4 .value_kind: hidden_block_count_x - .offset: 60 .size: 4 .value_kind: hidden_block_count_y - .offset: 64 .size: 4 .value_kind: hidden_block_count_z - .offset: 68 .size: 2 .value_kind: hidden_group_size_x - .offset: 70 .size: 2 .value_kind: hidden_group_size_y - .offset: 72 .size: 2 .value_kind: hidden_group_size_z - .offset: 74 .size: 2 .value_kind: hidden_remainder_x - .offset: 76 .size: 2 .value_kind: hidden_remainder_y - .offset: 78 .size: 2 .value_kind: hidden_remainder_z - .offset: 96 .size: 8 .value_kind: hidden_global_offset_x - .offset: 104 .size: 8 .value_kind: hidden_global_offset_y - .offset: 112 .size: 8 .value_kind: hidden_global_offset_z - .offset: 120 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 312 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12Ring2_kernelPfS_PiS0_S0_iiii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z12Ring2_kernelPfS_PiS0_S0_iiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" extern "C" { } #define TB 256 #define EPS 0.1 #undef MIN #define MIN(a, b) ((a) < (b) ? (a) : (b)) #undef MAX #define MAX(a, b) ((a) > (b) ? (a) : (b)) __global__ void Ring2_kernel( float *A, float *BP, int *corrAB, int *mask, int *m, int ring, int c, int h, int w ) { int id1 = blockIdx.x * blockDim.x + threadIdx.x; int size = h * w; if (id1 < size) { // int y1 = id1 / w, x1 = id1 % w; if (mask[id1] != 0) { int y2 = corrAB[2 * id1 + 1], x2 = corrAB[2 * id1 + 0]; for (int dx = -ring; dx <= ring; dx++) for (int dy = -ring; dy <= ring; dy++) { int _x2 = x2 + dx, _y2 = y2 + dy; if (_x2 >= 0 && _x2 < w && _y2 >= 0 && _y2 < h) { m[_y2 * w + _x2] = 1; } } } } return ; }
.text .file "Ring2_kernel.hip" .globl _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii # -- Begin function _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii .p2align 4, 0x90 .type _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii,@function _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii: # @_Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii .cfi_startproc # %bb.0: subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movl %r9d, 4(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 4(%rsp), %rax movq %rax, 136(%rsp) leaq 176(%rsp), %rax movq %rax, 144(%rsp) leaq 184(%rsp), %rax movq %rax, 152(%rsp) leaq 192(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z12Ring2_kernelPfS_PiS0_S0_iiii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $184, %rsp .cfi_adjust_cfa_offset -184 retq .Lfunc_end0: .size _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii, .Lfunc_end0-_Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12Ring2_kernelPfS_PiS0_S0_iiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z12Ring2_kernelPfS_PiS0_S0_iiii,@object # @_Z12Ring2_kernelPfS_PiS0_S0_iiii .section .rodata,"a",@progbits .globl _Z12Ring2_kernelPfS_PiS0_S0_iiii .p2align 3, 0x0 _Z12Ring2_kernelPfS_PiS0_S0_iiii: .quad _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii .size _Z12Ring2_kernelPfS_PiS0_S0_iiii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z12Ring2_kernelPfS_PiS0_S0_iiii" .size .L__unnamed_1, 33 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12Ring2_kernelPfS_PiS0_S0_iiii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z12Ring2_kernelPfS_PiS0_S0_iiii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x190] ; /* 0x0000640000047ab9 */ /* 0x000fe40000000a00 */ /*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */ /* 0x000fe2000f8e023f */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */ /* 0x001fca00078e0203 */ /*0060*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */ /* 0x000fda000bf06270 */ /*0070*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */ /* 0x000fe200078e00ff */ /*0090*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */ /* 0x000fc60000000a00 */ /*00a0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x178] ; /* 0x00005e0004027625 */ /* 0x000fcc00078e0205 */ /*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */ /* 0x000ea4000c1e1900 */ /*00c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x004fda0003f05270 */ /*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*00e0*/ IMAD.MOV R0, RZ, RZ, -c[0x0][0x188] ; /* 0x80006200ff007624 */ /* 0x000fe400078e02ff */ /*00f0*/ IMAD.SHL.U32 R2, R4, 0x2, RZ ; /* 0x0000000204027824 */ /* 0x000fc600078e00ff */ /*0100*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */ /* 0x000fe20003f04270 */ /*0110*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */ /* 0x000fd800078e0205 */ /*0120*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0130*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000408020a7981 */ /* 0x000ea8000c1e1900 */ /*0140*/ LDG.E R11, [R2.64] ; /* 0x00000008020b7981 */ /* 0x000162000c1e1900 */ /*0150*/ IMNMX R13, R0, c[0x0][0x188], !PT ; /* 0x00006200000d7a17 */ /* 0x000fe20007800200 */ /*0160*/ ULDC UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */ /* 0x000fe20000000800 */ /*0170*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */ /* 0x000fe200078e0000 */ /*0180*/ UIADD3 UR5, -UR4, 0x1, URZ ; /* 0x0000000104057890 */ /* 0x000fe2000fffe13f */ /*0190*/ IADD3 R13, R13, c[0x0][0x188], RZ ; /* 0x000062000d0d7a10 */ /* 0x000fe20007ffe0ff */ /*01a0*/ UIADD3 UR6, -UR4, 0x2, URZ ; /* 0x0000000204067890 */ /* 0x000fc4000fffe13f */ /*01b0*/ UIADD3 UR4, -UR4, 0x3, URZ ; /* 0x0000000304047890 */ /* 0x000fe2000fffe13f */ /*01c0*/ IADD3 R20, R13, 0x1, RZ ; /* 0x000000010d147810 */ /* 0x000fc80007ffe0ff */ /*01d0*/ LOP3.LUT R20, R20, 0x3, RZ, 0xc0, !PT ; /* 0x0000000314147812 */ /* 0x000fe400078ec0ff */ /*01e0*/ IADD3 R14, R10.reuse, -c[0x0][0x188], RZ ; /* 0x800062000a0e7a10 */ /* 0x044fe40007ffe0ff */ /*01f0*/ IADD3 R15, R10.reuse, 0x3, RZ ; /* 0x000000030a0f7810 */ /* 0x040fe40007ffe0ff */ /*0200*/ IADD3 R16, R10.reuse, 0x2, RZ ; /* 0x000000020a107810 */ /* 0x040fe40007ffe0ff */ /*0210*/ IADD3 R17, R10.reuse, 0x1, RZ ; /* 0x000000010a117810 */ /* 0x040fe40007ffe0ff */ /*0220*/ IADD3 R18, R10, UR5, RZ ; /* 0x000000050a127c10 */ /* 0x000fc4000fffe0ff */ /*0230*/ IADD3 R19, R10, UR6, RZ ; /* 0x000000060a137c10 */ /* 0x001fe4000fffe0ff */ /*0240*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */ /* 0x000fe20003f05270 */ /*0250*/ IMAD.IADD R21, R11, 0x1, R12 ; /* 0x000000010b157824 */ /* 0x020fe200078e020c */ /*0260*/ ISETP.GE.AND P4, PT, R12.reuse, c[0x0][0x188], PT ; /* 0x000062000c007a0c */ /* 0x040fe20003f86270 */ /*0270*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */ /* 0x001fe200078e0000 */ /*0280*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */ /* 0x000fd20007ffe0ff */ /*0290*/ @!P0 BRA 0x4a0 ; /* 0x0000020000008947 */ /* 0x000fea0003800000 */ /*02a0*/ ISETP.GE.AND P0, PT, R21, c[0x0][0x194], PT ; /* 0x0000650015007a0c */ /* 0x000fe20003f06270 */ /*02b0*/ IMAD.U32 R4, RZ, RZ, UR5 ; /* 0x00000005ff047e24 */ /* 0x000fe2000f8e00ff */ /*02c0*/ LOP3.LUT R2, R14, R21, RZ, 0xfc, !PT ; /* 0x000000150e027212 */ /* 0x000fc800078efcff */ /*02d0*/ ISETP.LT.OR P1, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */ /* 0x000fc80000721670 */ /*02e0*/ ISETP.GE.OR P1, PT, R14, c[0x0][0x190], P1 ; /* 0x000064000e007a0c */ /* 0x000fda0000f26670 */ /*02f0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */ /* 0x000fe400078e00ff */ /*0300*/ @!P1 IMAD R2, R14, c[0x0][0x194], R21 ; /* 0x000065000e029a24 */ /* 0x000fe400078e0215 */ /*0310*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff059424 */ /* 0x000fe400078e00ff */ /*0320*/ @!P1 IMAD.WIDE R2, R2, R3, c[0x0][0x180] ; /* 0x0000600002029625 */ /* 0x000fca00078e0203 */ /*0330*/ @!P1 STG.E [R2.64], R5 ; /* 0x0000000502009986 */ /* 0x0001e2000c101908 */ /*0340*/ ISETP.NE.AND P1, PT, R20, 0x1, PT ; /* 0x000000011400780c */ /* 0x000fda0003f25270 */ /*0350*/ @!P1 BRA 0x4a0 ; /* 0x0000014000009947 */ /* 0x000fea0003800000 */ /*0360*/ LOP3.LUT R2, R18, R21, RZ, 0xfc, !PT ; /* 0x0000001512027212 */ /* 0x001fe200078efcff */ /*0370*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */ /* 0x000fc6000f8e00ff */ /*0380*/ ISETP.LT.OR P1, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */ /* 0x000fc80000721670 */ /*0390*/ ISETP.GE.OR P1, PT, R18, c[0x0][0x190], P1 ; /* 0x0000640012007a0c */ /* 0x000fda0000f26670 */ /*03a0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */ /* 0x000fe400078e00ff */ /*03b0*/ @!P1 IMAD R2, R18, c[0x0][0x194], R21 ; /* 0x0000650012029a24 */ /* 0x000fe400078e0215 */ /*03c0*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff059424 */ /* 0x000fe400078e00ff */ /*03d0*/ @!P1 IMAD.WIDE R2, R2, R3, c[0x0][0x180] ; /* 0x0000600002029625 */ /* 0x000fca00078e0203 */ /*03e0*/ @!P1 STG.E [R2.64], R5 ; /* 0x0000000502009986 */ /* 0x0001e2000c101908 */ /*03f0*/ ISETP.NE.AND P1, PT, R20, 0x2, PT ; /* 0x000000021400780c */ /* 0x000fda0003f25270 */ /*0400*/ @!P1 BRA 0x4a0 ; /* 0x0000009000009947 */ /* 0x000fea0003800000 */ /*0410*/ LOP3.LUT R2, R19, R21, RZ, 0xfc, !PT ; /* 0x0000001513027212 */ /* 0x001fe200078efcff */ /*0420*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */ /* 0x000fc6000f8e00ff */ /*0430*/ ISETP.LT.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */ /* 0x000fc80000701670 */ /*0440*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x190], P0 ; /* 0x0000640013007a0c */ /* 0x000fda0000706670 */ /*0450*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */ /* 0x000fe400078e00ff */ /*0460*/ @!P0 IMAD R2, R19, c[0x0][0x194], R21 ; /* 0x0000650013028a24 */ /* 0x000fe400078e0215 */ /*0470*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff058424 */ /* 0x000fe400078e00ff */ /*0480*/ @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x180] ; /* 0x0000600002028625 */ /* 0x000fca00078e0203 */ /*0490*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */ /* 0x0001e4000c101908 */ /*04a0*/ ISETP.GE.U32.AND P0, PT, R13, 0x3, PT ; /* 0x000000030d00780c */ /* 0x001fda0003f06070 */ /*04b0*/ @!P0 BRA 0x7e0 ; /* 0x0000032000008947 */ /* 0x000fea0003800000 */ /*04c0*/ IADD3 R24, R15, R4, RZ ; /* 0x000000040f187210 */ /* 0x000fe20007ffe0ff */ /*04d0*/ IMAD.IADD R2, R16, 0x1, R4.reuse ; /* 0x0000000110027824 */ /* 0x100fe200078e0204 */ /*04e0*/ ISETP.GE.AND P5, PT, R21, c[0x0][0x194], PT ; /* 0x0000650015007a0c */ /* 0x000fe20003fa6270 */ /*04f0*/ IMAD.IADD R6, R17, 0x1, R4.reuse ; /* 0x0000000111067824 */ /* 0x100fe200078e0204 */ /*0500*/ IADD3 R23, R4, -0x1, RZ ; /* 0xffffffff04177810 */ /* 0x000fe20007ffe0ff */ /*0510*/ IMAD.IADD R22, R10, 0x1, R4 ; /* 0x000000010a167824 */ /* 0x000fe400078e0204 */ /*0520*/ IMAD R24, R24, c[0x0][0x194], R21.reuse ; /* 0x0000650018187a24 */ /* 0x100fe400078e0215 */ /*0530*/ IMAD R25, R2, c[0x0][0x194], R21.reuse ; /* 0x0000650002197a24 */ /* 0x100fe400078e0215 */ /*0540*/ IMAD R27, R6, c[0x0][0x194], R21 ; /* 0x00006500061b7a24 */ /* 0x000fc400078e0215 */ /*0550*/ IMAD R26, R22, c[0x0][0x194], R21 ; /* 0x00006500161a7a24 */ /* 0x000fe400078e0215 */ /*0560*/ LOP3.LUT R3, R22.reuse, R21.reuse, RZ, 0xfc, !PT ; /* 0x0000001516037212 */ /* 0x0c1fe400078efcff */ /*0570*/ IADD3 R2, R22, 0x1, RZ ; /* 0x0000000116027810 */ /* 0x000fe40007ffe0ff */ /*0580*/ ISETP.LT.OR P0, PT, R3, RZ, P5 ; /* 0x000000ff0300720c */ /* 0x000fe40002f01670 */ /*0590*/ LOP3.LUT R3, R2, R21, RZ, 0xfc, !PT ; /* 0x0000001502037212 */ /* 0x000fe400078efcff */ /*05a0*/ IADD3 R4, R22, 0x2, RZ ; /* 0x0000000216047810 */ /* 0x000fe40007ffe0ff */ /*05b0*/ ISETP.LT.OR P1, PT, R3, RZ, P5 ; /* 0x000000ff0300720c */ /* 0x000fc40002f21670 */ /*05c0*/ IADD3 R6, R22, 0x3, RZ ; /* 0x0000000316067810 */ /* 0x000fe40007ffe0ff */ /*05d0*/ ISETP.GE.OR P1, PT, R2, c[0x0][0x190], P1 ; /* 0x0000640002007a0c */ /* 0x000fe40000f26670 */ /*05e0*/ LOP3.LUT R2, R4, R21.reuse, RZ, 0xfc, !PT ; /* 0x0000001504027212 */ /* 0x080fe400078efcff */ /*05f0*/ LOP3.LUT R3, R6, R21, RZ, 0xfc, !PT ; /* 0x0000001506037212 */ /* 0x000fe400078efcff */ /*0600*/ ISETP.GE.OR P0, PT, R22, c[0x0][0x190], P0 ; /* 0x0000640016007a0c */ /* 0x000fe40000706670 */ /*0610*/ ISETP.LT.OR P3, PT, R2, RZ, P5 ; /* 0x000000ff0200720c */ /* 0x000fc40002f61670 */ /*0620*/ ISETP.LT.OR P2, PT, R3, RZ, P5 ; /* 0x000000ff0300720c */ /* 0x000fe40002f41670 */ /*0630*/ ISETP.GE.OR P3, PT, R4, c[0x0][0x190], P3 ; /* 0x0000640004007a0c */ /* 0x000fe20001f66670 */ /*0640*/ @!P1 IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff089424 */ /* 0x000fe200078e00ff */ /*0650*/ ISETP.GE.OR P2, PT, R6, c[0x0][0x190], P2 ; /* 0x0000640006007a0c */ /* 0x000fe20001746670 */ /*0660*/ @!P1 IMAD.MOV.U32 R28, RZ, RZ, 0x1 ; /* 0x00000001ff1c9424 */ /* 0x000fe200078e00ff */ /*0670*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */ /* 0x000fe20007ffe0ff */ /*0680*/ @!P1 IMAD.WIDE R8, R27, R8, c[0x0][0x180] ; /* 0x000060001b089625 */ /* 0x000fe200078e0208 */ /*0690*/ IADD3 R22, R22, 0x4, RZ ; /* 0x0000000416167810 */ /* 0x000fc60007ffe0ff */ /*06a0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff078424 */ /* 0x000fe400078e00ff */ /*06b0*/ @!P0 IMAD.MOV.U32 R29, RZ, RZ, 0x1 ; /* 0x00000001ff1d8424 */ /* 0x000fe400078e00ff */ /*06c0*/ @!P0 IMAD.WIDE R6, R26, R7, c[0x0][0x180] ; /* 0x000060001a068625 */ /* 0x000fe400078e0207 */ /*06d0*/ @!P2 MOV R5, 0x4 ; /* 0x000000040005a802 */ /* 0x000fe40000000f00 */ /*06e0*/ @!P3 IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff02b424 */ /* 0x000fe200078e00ff */ /*06f0*/ @!P0 STG.E [R6.64], R29 ; /* 0x0000001d06008986 */ /* 0x0001e2000c101908 */ /*0700*/ ISETP.GE.AND P0, PT, R23, c[0x0][0x188], PT ; /* 0x0000620017007a0c */ /* 0x000fe20003f06270 */ /*0710*/ @!P2 IMAD.WIDE R4, R24, R5, c[0x0][0x180] ; /* 0x000060001804a625 */ /* 0x000fc400078e0205 */ /*0720*/ @!P1 STG.E [R8.64], R28 ; /* 0x0000001c08009986 */ /* 0x0003e4000c101908 */ /*0730*/ @!P3 IMAD.WIDE R2, R25, R2, c[0x0][0x180] ; /* 0x000060001902b625 */ /* 0x000fc800078e0202 */ /*0740*/ @!P3 IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff07b424 */ /* 0x001fe400078e00ff */ /*0750*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff067624 */ /* 0x000fe400078e00ff */ /*0760*/ @!P2 IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff09a424 */ /* 0x002fe200078e00ff */ /*0770*/ @!P3 STG.E [R2.64], R7 ; /* 0x000000070200b986 */ /* 0x0001e2000c101908 */ /*0780*/ IMAD R26, R6.reuse, 0x4, R26 ; /* 0x00000004061a7824 */ /* 0x040fe400078e021a */ /*0790*/ IMAD R24, R6.reuse, 0x4, R24 ; /* 0x0000000406187824 */ /* 0x040fe200078e0218 */ /*07a0*/ @!P2 STG.E [R4.64], R9 ; /* 0x000000090400a986 */ /* 0x0001e2000c101908 */ /*07b0*/ IMAD R25, R6, 0x4, R25 ; /* 0x0000000406197824 */ /* 0x000fc400078e0219 */ /*07c0*/ IMAD R27, R6, 0x4, R27 ; /* 0x00000004061b7824 */ /* 0x000fe200078e021b */ /*07d0*/ @!P0 BRA 0x560 ; /* 0xfffffd8000008947 */ /* 0x000fea000383ffff */ /*07e0*/ @!P4 BRA 0x240 ; /* 0xfffffa500000c947 */ /* 0x000fea000383ffff */ /*07f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0800*/ BRA 0x800; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0810*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0820*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0830*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0840*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0850*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0860*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0870*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0880*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0890*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*08f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z12Ring2_kernelPfS_PiS0_S0_iiii .globl _Z12Ring2_kernelPfS_PiS0_S0_iiii .p2align 8 .type _Z12Ring2_kernelPfS_PiS0_S0_iiii,@function _Z12Ring2_kernelPfS_PiS0_S0_iiii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x44 s_load_b64 s[4:5], s[0:1], 0x30 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mul_i32 s2, s5, s4 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, s2, v1 s_and_saveexec_b32 s2, vcc_lo s_cbranch_execz .LBB0_9 s_load_b64 s[2:3], s[0:1], 0x18 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s2, v2 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo global_load_b32 v0, v[2:3], off s_waitcnt vmcnt(0) v_cmp_ne_u32_e32 vcc_lo, 0, v0 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_9 s_load_b32 s3, s[0:1], 0x28 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s3, 0 s_cbranch_scc1 .LBB0_9 v_dual_mov_b32 v5, 1 :: v_dual_lshlrev_b32 v0, 1, v1 s_clause 0x1 s_load_b64 s[8:9], s[0:1], 0x10 s_load_b64 s[6:7], s[0:1], 0x20 s_lshl_b32 s0, s3, 1 v_or_b32_e32 v2, 1, v0 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[0:1], 2, v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s8, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo v_add_co_u32 v0, vcc_lo, s8, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo s_clause 0x1 global_load_b32 v2, v[2:3], off global_load_b32 v0, v[0:1], off s_sub_i32 s9, 0, s3 s_or_b32 s8, s0, 1 s_waitcnt vmcnt(1) v_subrev_nc_u32_e32 v3, s3, v2 s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s5, v3, v[0:1] v_subrev_nc_u32_e32 v4, s3, v1 s_set_inst_prefetch_distance 0x1 s_branch .LBB0_5 .p2align 6 .LBB0_4: v_add_nc_u32_e32 v4, 1, v4 s_add_i32 s0, s9, 1 s_cmp_eq_u32 s9, s3 s_mov_b32 s9, s0 s_cbranch_scc1 .LBB0_9 .LBB0_5: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_dual_mov_b32 v1, v4 :: v_dual_add_nc_u32 v2, s9, v0 v_mov_b32_e32 v6, v3 s_mov_b32 s10, s8 v_cmp_lt_i32_e32 vcc_lo, -1, v2 v_cmp_gt_i32_e64 s0, s5, v2 s_branch .LBB0_7 .p2align 6 .LBB0_6: s_or_b32 exec_lo, exec_lo, s2 v_add_nc_u32_e32 v6, 1, v6 v_add_nc_u32_e32 v1, s5, v1 s_add_i32 s10, s10, -1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s10, 0 s_cbranch_scc1 .LBB0_4 .LBB0_7: v_cmp_lt_i32_e64 s1, -1, v6 v_cmp_gt_i32_e64 s2, s4, v6 s_delay_alu instid0(VALU_DEP_2) s_and_b32 s1, s0, s1 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_and_b32 s1, s1, s2 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s1, vcc_lo, s1 s_and_saveexec_b32 s2, s1 s_cbranch_execz .LBB0_6 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[7:8], 2, v[1:2] v_add_co_u32 v7, s1, s6, v7 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v8, s1, s7, v8, s1 global_store_b32 v[7:8], v5, off s_branch .LBB0_6 .LBB0_9: s_set_inst_prefetch_distance 0x2 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12Ring2_kernelPfS_PiS0_S0_iiii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 312 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z12Ring2_kernelPfS_PiS0_S0_iiii, .Lfunc_end0-_Z12Ring2_kernelPfS_PiS0_S0_iiii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: by_value - .offset: 44 .size: 4 .value_kind: by_value - .offset: 48 .size: 4 .value_kind: by_value - .offset: 52 .size: 4 .value_kind: by_value - .offset: 56 .size: 4 .value_kind: hidden_block_count_x - .offset: 60 .size: 4 .value_kind: hidden_block_count_y - .offset: 64 .size: 4 .value_kind: hidden_block_count_z - .offset: 68 .size: 2 .value_kind: hidden_group_size_x - .offset: 70 .size: 2 .value_kind: hidden_group_size_y - .offset: 72 .size: 2 .value_kind: hidden_group_size_z - .offset: 74 .size: 2 .value_kind: hidden_remainder_x - .offset: 76 .size: 2 .value_kind: hidden_remainder_y - .offset: 78 .size: 2 .value_kind: hidden_remainder_z - .offset: 96 .size: 8 .value_kind: hidden_global_offset_x - .offset: 104 .size: 8 .value_kind: hidden_global_offset_y - .offset: 112 .size: 8 .value_kind: hidden_global_offset_z - .offset: 120 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 312 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12Ring2_kernelPfS_PiS0_S0_iiii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z12Ring2_kernelPfS_PiS0_S0_iiii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0003ff80_00000000-6_Ring2_kernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z46__device_stub__Z12Ring2_kernelPfS_PiS0_S0_iiiiPfS_PiS0_S0_iiii .type _Z46__device_stub__Z12Ring2_kernelPfS_PiS0_S0_iiiiPfS_PiS0_S0_iiii, @function _Z46__device_stub__Z12Ring2_kernelPfS_PiS0_S0_iiiiPfS_PiS0_S0_iiii: .LFB2051: .cfi_startproc endbr64 subq $200, %rsp .cfi_def_cfa_offset 208 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movq %r8, 8(%rsp) movl %r9d, 4(%rsp) movq %fs:40, %rax movq %rax, 184(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) leaq 4(%rsp), %rax movq %rax, 152(%rsp) leaq 208(%rsp), %rax movq %rax, 160(%rsp) leaq 216(%rsp), %rax movq %rax, 168(%rsp) leaq 224(%rsp), %rax movq %rax, 176(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 184(%rsp), %rax subq %fs:40, %rax jne .L8 addq $200, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 216 pushq 56(%rsp) .cfi_def_cfa_offset 224 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z12Ring2_kernelPfS_PiS0_S0_iiii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 208 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z46__device_stub__Z12Ring2_kernelPfS_PiS0_S0_iiiiPfS_PiS0_S0_iiii, .-_Z46__device_stub__Z12Ring2_kernelPfS_PiS0_S0_iiiiPfS_PiS0_S0_iiii .globl _Z12Ring2_kernelPfS_PiS0_S0_iiii .type _Z12Ring2_kernelPfS_PiS0_S0_iiii, @function _Z12Ring2_kernelPfS_PiS0_S0_iiii: .LFB2052: .cfi_startproc endbr64 subq $16, %rsp .cfi_def_cfa_offset 24 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 32 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 40 movl 40(%rsp), %eax pushq %rax .cfi_def_cfa_offset 48 call _Z46__device_stub__Z12Ring2_kernelPfS_PiS0_S0_iiiiPfS_PiS0_S0_iiii addq $40, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z12Ring2_kernelPfS_PiS0_S0_iiii, .-_Z12Ring2_kernelPfS_PiS0_S0_iiii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z12Ring2_kernelPfS_PiS0_S0_iiii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z12Ring2_kernelPfS_PiS0_S0_iiii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "Ring2_kernel.hip" .globl _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii # -- Begin function _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii .p2align 4, 0x90 .type _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii,@function _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii: # @_Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii .cfi_startproc # %bb.0: subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) movl %r9d, 4(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 4(%rsp), %rax movq %rax, 136(%rsp) leaq 176(%rsp), %rax movq %rax, 144(%rsp) leaq 184(%rsp), %rax movq %rax, 152(%rsp) leaq 192(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z12Ring2_kernelPfS_PiS0_S0_iiii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $184, %rsp .cfi_adjust_cfa_offset -184 retq .Lfunc_end0: .size _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii, .Lfunc_end0-_Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12Ring2_kernelPfS_PiS0_S0_iiii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z12Ring2_kernelPfS_PiS0_S0_iiii,@object # @_Z12Ring2_kernelPfS_PiS0_S0_iiii .section .rodata,"a",@progbits .globl _Z12Ring2_kernelPfS_PiS0_S0_iiii .p2align 3, 0x0 _Z12Ring2_kernelPfS_PiS0_S0_iiii: .quad _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii .size _Z12Ring2_kernelPfS_PiS0_S0_iiii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z12Ring2_kernelPfS_PiS0_S0_iiii" .size .L__unnamed_1, 33 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__Ring2_kernelPfS_PiS0_S0_iiii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12Ring2_kernelPfS_PiS0_S0_iiii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void OpenBoundaryKernel (double *Vrad, double *Dens, double *Energy, int nsec, double SigmaMed) { int j = threadIdx.x + blockDim.x*blockIdx.x; int i = 1; if(j < nsec){ Dens[(i-1)*nsec + j] = Dens[i*nsec + j]; // copy first ring into ghost ring Energy[(i-1)*nsec + j] = Energy[i*nsec + j]; if (Vrad[(i+1)*nsec + j] > 0.0 || (Dens[i*nsec + j] < SigmaMed)) Vrad[i*nsec + j] = 0.0; // we just allow outflow [inwards] else Vrad[i*nsec +j] = Vrad[(i+1)*nsec + j]; } }
code for sm_80 Function : _Z18OpenBoundaryKernelPdS_S_id .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R15, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0f7435 */ /* 0x000fe200000001ff */ /*0070*/ IADD3 R14, R10, c[0x0][0x178], RZ ; /* 0x00005e000a0e7a10 */ /* 0x000fe20007ffe0ff */ /*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd00000000a00 */ /*0090*/ IMAD.WIDE R2, R14, R15, c[0x0][0x168] ; /* 0x00005a000e027625 */ /* 0x000fca00078e020f */ /*00a0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */ /* 0x000ea2000c1e1b00 */ /*00b0*/ IMAD.WIDE R6, R10, R15, c[0x0][0x168] ; /* 0x00005a000a067625 */ /* 0x000fc800078e020f */ /*00c0*/ IMAD.WIDE R8, R14.reuse, R15.reuse, c[0x0][0x170] ; /* 0x00005c000e087625 */ /* 0x0c0fe200078e020f */ /*00d0*/ IADD3 R12, R14, c[0x0][0x178], RZ ; /* 0x00005e000e0c7a10 */ /* 0x000fe20007ffe0ff */ /*00e0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */ /* 0x0041e8000c101b04 */ /*00f0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */ /* 0x000ea2000c1e1b00 */ /*0100*/ IMAD.WIDE R10, R10, R15, c[0x0][0x170] ; /* 0x00005c000a0a7625 */ /* 0x000fc800078e020f */ /*0110*/ IMAD.WIDE R12, R12, R15.reuse, c[0x0][0x160] ; /* 0x000058000c0c7625 */ /* 0x080fe200078e020f */ /*0120*/ STG.E.64 [R10.64], R8 ; /* 0x000000080a007986 */ /* 0x0041ea000c101b04 */ /*0130*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */ /* 0x000ea2000c1e1b00 */ /*0140*/ BSSY B0, 0x1d0 ; /* 0x0000008000007945 */ /* 0x000fe20003800000 */ /*0150*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */ /* 0x000fe200078e020f */ /*0160*/ DSETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00722a */ /* 0x004e5c0003f04000 */ /*0170*/ @P0 BRA 0x1c0 ; /* 0x0000004000000947 */ /* 0x002fea0003800000 */ /*0180*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x001ea4000c1e1b00 */ /*0190*/ DSETP.GEU.AND P0, PT, R2, c[0x0][0x180], PT ; /* 0x000060000200762a */ /* 0x004e1c0003f0e000 */ /*01a0*/ @P0 STG.E.64 [R14.64], R12 ; /* 0x0000000c0e000986 */ /* 0x0011e2000c101b04 */ /*01b0*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x001fea0003800000 */ /*01d0*/ STG.E.64 [R14.64], RZ ; /* 0x000000ff0e007986 */ /* 0x000fe2000c101b04 */ /*01e0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void OpenBoundaryKernel (double *Vrad, double *Dens, double *Energy, int nsec, double SigmaMed) { int j = threadIdx.x + blockDim.x*blockIdx.x; int i = 1; if(j < nsec){ Dens[(i-1)*nsec + j] = Dens[i*nsec + j]; // copy first ring into ghost ring Energy[(i-1)*nsec + j] = Energy[i*nsec + j]; if (Vrad[(i+1)*nsec + j] > 0.0 || (Dens[i*nsec + j] < SigmaMed)) Vrad[i*nsec + j] = 0.0; // we just allow outflow [inwards] else Vrad[i*nsec +j] = Vrad[(i+1)*nsec + j]; } }
.file "tmpxft_001b1106_00000000-6_OpenBoundaryKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z44__device_stub__Z18OpenBoundaryKernelPdS_S_idPdS_S_id .type _Z44__device_stub__Z18OpenBoundaryKernelPdS_S_idPdS_S_id, @function _Z44__device_stub__Z18OpenBoundaryKernelPdS_S_idPdS_S_id: .LFB2051: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movl %ecx, 20(%rsp) movsd %xmm0, 8(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 20(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 152(%rsp), %rax subq %fs:40, %rax jne .L8 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 184 pushq 56(%rsp) .cfi_def_cfa_offset 192 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z18OpenBoundaryKernelPdS_S_id(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z44__device_stub__Z18OpenBoundaryKernelPdS_S_idPdS_S_id, .-_Z44__device_stub__Z18OpenBoundaryKernelPdS_S_idPdS_S_id .globl _Z18OpenBoundaryKernelPdS_S_id .type _Z18OpenBoundaryKernelPdS_S_id, @function _Z18OpenBoundaryKernelPdS_S_id: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z44__device_stub__Z18OpenBoundaryKernelPdS_S_idPdS_S_id addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z18OpenBoundaryKernelPdS_S_id, .-_Z18OpenBoundaryKernelPdS_S_id .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z18OpenBoundaryKernelPdS_S_id" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z18OpenBoundaryKernelPdS_S_id(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void OpenBoundaryKernel (double *Vrad, double *Dens, double *Energy, int nsec, double SigmaMed) { int j = threadIdx.x + blockDim.x*blockIdx.x; int i = 1; if(j < nsec){ Dens[(i-1)*nsec + j] = Dens[i*nsec + j]; // copy first ring into ghost ring Energy[(i-1)*nsec + j] = Energy[i*nsec + j]; if (Vrad[(i+1)*nsec + j] > 0.0 || (Dens[i*nsec + j] < SigmaMed)) Vrad[i*nsec + j] = 0.0; // we just allow outflow [inwards] else Vrad[i*nsec +j] = Vrad[(i+1)*nsec + j]; } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void OpenBoundaryKernel (double *Vrad, double *Dens, double *Energy, int nsec, double SigmaMed) { int j = threadIdx.x + blockDim.x*blockIdx.x; int i = 1; if(j < nsec){ Dens[(i-1)*nsec + j] = Dens[i*nsec + j]; // copy first ring into ghost ring Energy[(i-1)*nsec + j] = Energy[i*nsec + j]; if (Vrad[(i+1)*nsec + j] > 0.0 || (Dens[i*nsec + j] < SigmaMed)) Vrad[i*nsec + j] = 0.0; // we just allow outflow [inwards] else Vrad[i*nsec +j] = Vrad[(i+1)*nsec + j]; } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void OpenBoundaryKernel (double *Vrad, double *Dens, double *Energy, int nsec, double SigmaMed) { int j = threadIdx.x + blockDim.x*blockIdx.x; int i = 1; if(j < nsec){ Dens[(i-1)*nsec + j] = Dens[i*nsec + j]; // copy first ring into ghost ring Energy[(i-1)*nsec + j] = Energy[i*nsec + j]; if (Vrad[(i+1)*nsec + j] > 0.0 || (Dens[i*nsec + j] < SigmaMed)) Vrad[i*nsec + j] = 0.0; // we just allow outflow [inwards] else Vrad[i*nsec +j] = Vrad[(i+1)*nsec + j]; } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z18OpenBoundaryKernelPdS_S_id .globl _Z18OpenBoundaryKernelPdS_S_id .p2align 8 .type _Z18OpenBoundaryKernelPdS_S_id,@function _Z18OpenBoundaryKernelPdS_S_id: s_clause 0x1 s_load_b32 s3, s[0:1], 0x34 s_load_b32 s2, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1] s_mov_b32 s3, exec_lo v_cmpx_gt_i32_e64 s2, v4 s_cbranch_execz .LBB0_6 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[8:9], s[0:1], 0x10 v_add_nc_u32_e32 v0, s2, v4 v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[8:9], 3, v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s6, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v10, vcc_lo, s6, v8 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v9, vcc_lo global_load_b64 v[6:7], v[2:3], off v_add_co_u32 v12, vcc_lo, s8, v0 v_add_co_ci_u32_e32 v13, vcc_lo, s9, v1, vcc_lo s_waitcnt vmcnt(0) global_store_b64 v[10:11], v[6:7], off global_load_b64 v[5:6], v[12:13], off v_lshl_add_u32 v10, s2, 1, v4 v_add_co_u32 v7, vcc_lo, s8, v8 v_add_co_ci_u32_e32 v8, vcc_lo, s9, v9, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v11, 31, v10 s_mov_b32 s2, exec_lo v_lshlrev_b64 v[10:11], 3, v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v9, vcc_lo, s4, v10 v_add_co_ci_u32_e32 v10, vcc_lo, s5, v11, vcc_lo s_waitcnt vmcnt(0) global_store_b64 v[7:8], v[5:6], off global_load_b64 v[6:7], v[9:10], off v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_waitcnt vmcnt(0) v_cmpx_nlt_f64_e32 0, v[6:7] s_cbranch_execz .LBB0_5 global_load_b64 v[2:3], v[2:3], off s_load_b64 s[0:1], s[0:1], 0x20 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_waitcnt vmcnt(0) lgkmcnt(0) v_cmp_ngt_f64_e32 vcc_lo, s[0:1], v[2:3] s_and_saveexec_b32 s0, vcc_lo v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7 s_or_b32 exec_lo, exec_lo, s0 .LBB0_5: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 v_add_co_u32 v0, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo global_store_b64 v[0:1], v[4:5], off .LBB0_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18OpenBoundaryKernelPdS_S_id .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 14 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z18OpenBoundaryKernelPdS_S_id, .Lfunc_end0-_Z18OpenBoundaryKernelPdS_S_id .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 8 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18OpenBoundaryKernelPdS_S_id .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z18OpenBoundaryKernelPdS_S_id.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 14 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void OpenBoundaryKernel (double *Vrad, double *Dens, double *Energy, int nsec, double SigmaMed) { int j = threadIdx.x + blockDim.x*blockIdx.x; int i = 1; if(j < nsec){ Dens[(i-1)*nsec + j] = Dens[i*nsec + j]; // copy first ring into ghost ring Energy[(i-1)*nsec + j] = Energy[i*nsec + j]; if (Vrad[(i+1)*nsec + j] > 0.0 || (Dens[i*nsec + j] < SigmaMed)) Vrad[i*nsec + j] = 0.0; // we just allow outflow [inwards] else Vrad[i*nsec +j] = Vrad[(i+1)*nsec + j]; } }
.text .file "OpenBoundaryKernel.hip" .globl _Z33__device_stub__OpenBoundaryKernelPdS_S_id # -- Begin function _Z33__device_stub__OpenBoundaryKernelPdS_S_id .p2align 4, 0x90 .type _Z33__device_stub__OpenBoundaryKernelPdS_S_id,@function _Z33__device_stub__OpenBoundaryKernelPdS_S_id: # @_Z33__device_stub__OpenBoundaryKernelPdS_S_id .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movl %ecx, 12(%rsp) movsd %xmm0, 64(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 64(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z18OpenBoundaryKernelPdS_S_id, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end0: .size _Z33__device_stub__OpenBoundaryKernelPdS_S_id, .Lfunc_end0-_Z33__device_stub__OpenBoundaryKernelPdS_S_id .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z18OpenBoundaryKernelPdS_S_id, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z18OpenBoundaryKernelPdS_S_id,@object # @_Z18OpenBoundaryKernelPdS_S_id .section .rodata,"a",@progbits .globl _Z18OpenBoundaryKernelPdS_S_id .p2align 3, 0x0 _Z18OpenBoundaryKernelPdS_S_id: .quad _Z33__device_stub__OpenBoundaryKernelPdS_S_id .size _Z18OpenBoundaryKernelPdS_S_id, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z18OpenBoundaryKernelPdS_S_id" .size .L__unnamed_1, 31 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z33__device_stub__OpenBoundaryKernelPdS_S_id .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z18OpenBoundaryKernelPdS_S_id .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z18OpenBoundaryKernelPdS_S_id .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R15, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0f7435 */ /* 0x000fe200000001ff */ /*0070*/ IADD3 R14, R10, c[0x0][0x178], RZ ; /* 0x00005e000a0e7a10 */ /* 0x000fe20007ffe0ff */ /*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd00000000a00 */ /*0090*/ IMAD.WIDE R2, R14, R15, c[0x0][0x168] ; /* 0x00005a000e027625 */ /* 0x000fca00078e020f */ /*00a0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */ /* 0x000ea2000c1e1b00 */ /*00b0*/ IMAD.WIDE R6, R10, R15, c[0x0][0x168] ; /* 0x00005a000a067625 */ /* 0x000fc800078e020f */ /*00c0*/ IMAD.WIDE R8, R14.reuse, R15.reuse, c[0x0][0x170] ; /* 0x00005c000e087625 */ /* 0x0c0fe200078e020f */ /*00d0*/ IADD3 R12, R14, c[0x0][0x178], RZ ; /* 0x00005e000e0c7a10 */ /* 0x000fe20007ffe0ff */ /*00e0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */ /* 0x0041e8000c101b04 */ /*00f0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */ /* 0x000ea2000c1e1b00 */ /*0100*/ IMAD.WIDE R10, R10, R15, c[0x0][0x170] ; /* 0x00005c000a0a7625 */ /* 0x000fc800078e020f */ /*0110*/ IMAD.WIDE R12, R12, R15.reuse, c[0x0][0x160] ; /* 0x000058000c0c7625 */ /* 0x080fe200078e020f */ /*0120*/ STG.E.64 [R10.64], R8 ; /* 0x000000080a007986 */ /* 0x0041ea000c101b04 */ /*0130*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */ /* 0x000ea2000c1e1b00 */ /*0140*/ BSSY B0, 0x1d0 ; /* 0x0000008000007945 */ /* 0x000fe20003800000 */ /*0150*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */ /* 0x000fe200078e020f */ /*0160*/ DSETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00722a */ /* 0x004e5c0003f04000 */ /*0170*/ @P0 BRA 0x1c0 ; /* 0x0000004000000947 */ /* 0x002fea0003800000 */ /*0180*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x001ea4000c1e1b00 */ /*0190*/ DSETP.GEU.AND P0, PT, R2, c[0x0][0x180], PT ; /* 0x000060000200762a */ /* 0x004e1c0003f0e000 */ /*01a0*/ @P0 STG.E.64 [R14.64], R12 ; /* 0x0000000c0e000986 */ /* 0x0011e2000c101b04 */ /*01b0*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */ /* 0x001fea0003800000 */ /*01d0*/ STG.E.64 [R14.64], RZ ; /* 0x000000ff0e007986 */ /* 0x000fe2000c101b04 */ /*01e0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z18OpenBoundaryKernelPdS_S_id .globl _Z18OpenBoundaryKernelPdS_S_id .p2align 8 .type _Z18OpenBoundaryKernelPdS_S_id,@function _Z18OpenBoundaryKernelPdS_S_id: s_clause 0x1 s_load_b32 s3, s[0:1], 0x34 s_load_b32 s2, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s3, s3, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[4:5], null, s15, s3, v[0:1] s_mov_b32 s3, exec_lo v_cmpx_gt_i32_e64 s2, v4 s_cbranch_execz .LBB0_6 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[8:9], s[0:1], 0x10 v_add_nc_u32_e32 v0, s2, v4 v_ashrrev_i32_e32 v5, 31, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64 v[8:9], 3, v[4:5] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 3, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s6, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v10, vcc_lo, s6, v8 v_add_co_ci_u32_e32 v11, vcc_lo, s7, v9, vcc_lo global_load_b64 v[6:7], v[2:3], off v_add_co_u32 v12, vcc_lo, s8, v0 v_add_co_ci_u32_e32 v13, vcc_lo, s9, v1, vcc_lo s_waitcnt vmcnt(0) global_store_b64 v[10:11], v[6:7], off global_load_b64 v[5:6], v[12:13], off v_lshl_add_u32 v10, s2, 1, v4 v_add_co_u32 v7, vcc_lo, s8, v8 v_add_co_ci_u32_e32 v8, vcc_lo, s9, v9, vcc_lo s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v11, 31, v10 s_mov_b32 s2, exec_lo v_lshlrev_b64 v[10:11], 3, v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v9, vcc_lo, s4, v10 v_add_co_ci_u32_e32 v10, vcc_lo, s5, v11, vcc_lo s_waitcnt vmcnt(0) global_store_b64 v[7:8], v[5:6], off global_load_b64 v[6:7], v[9:10], off v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_waitcnt vmcnt(0) v_cmpx_nlt_f64_e32 0, v[6:7] s_cbranch_execz .LBB0_5 global_load_b64 v[2:3], v[2:3], off s_load_b64 s[0:1], s[0:1], 0x20 v_mov_b32_e32 v4, 0 v_mov_b32_e32 v5, 0 s_waitcnt vmcnt(0) lgkmcnt(0) v_cmp_ngt_f64_e32 vcc_lo, s[0:1], v[2:3] s_and_saveexec_b32 s0, vcc_lo v_dual_mov_b32 v4, v6 :: v_dual_mov_b32 v5, v7 s_or_b32 exec_lo, exec_lo, s0 .LBB0_5: s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s2 v_add_co_u32 v0, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo global_store_b64 v[0:1], v[4:5], off .LBB0_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18OpenBoundaryKernelPdS_S_id .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 14 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z18OpenBoundaryKernelPdS_S_id, .Lfunc_end0-_Z18OpenBoundaryKernelPdS_S_id .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 8 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18OpenBoundaryKernelPdS_S_id .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z18OpenBoundaryKernelPdS_S_id.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 14 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_001b1106_00000000-6_OpenBoundaryKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z44__device_stub__Z18OpenBoundaryKernelPdS_S_idPdS_S_id .type _Z44__device_stub__Z18OpenBoundaryKernelPdS_S_idPdS_S_id, @function _Z44__device_stub__Z18OpenBoundaryKernelPdS_S_idPdS_S_id: .LFB2051: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movl %ecx, 20(%rsp) movsd %xmm0, 8(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 20(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 152(%rsp), %rax subq %fs:40, %rax jne .L8 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 184 pushq 56(%rsp) .cfi_def_cfa_offset 192 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z18OpenBoundaryKernelPdS_S_id(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z44__device_stub__Z18OpenBoundaryKernelPdS_S_idPdS_S_id, .-_Z44__device_stub__Z18OpenBoundaryKernelPdS_S_idPdS_S_id .globl _Z18OpenBoundaryKernelPdS_S_id .type _Z18OpenBoundaryKernelPdS_S_id, @function _Z18OpenBoundaryKernelPdS_S_id: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z44__device_stub__Z18OpenBoundaryKernelPdS_S_idPdS_S_id addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z18OpenBoundaryKernelPdS_S_id, .-_Z18OpenBoundaryKernelPdS_S_id .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z18OpenBoundaryKernelPdS_S_id" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z18OpenBoundaryKernelPdS_S_id(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "OpenBoundaryKernel.hip" .globl _Z33__device_stub__OpenBoundaryKernelPdS_S_id # -- Begin function _Z33__device_stub__OpenBoundaryKernelPdS_S_id .p2align 4, 0x90 .type _Z33__device_stub__OpenBoundaryKernelPdS_S_id,@function _Z33__device_stub__OpenBoundaryKernelPdS_S_id: # @_Z33__device_stub__OpenBoundaryKernelPdS_S_id .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movl %ecx, 12(%rsp) movsd %xmm0, 64(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 12(%rsp), %rax movq %rax, 120(%rsp) leaq 64(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z18OpenBoundaryKernelPdS_S_id, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end0: .size _Z33__device_stub__OpenBoundaryKernelPdS_S_id, .Lfunc_end0-_Z33__device_stub__OpenBoundaryKernelPdS_S_id .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z18OpenBoundaryKernelPdS_S_id, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z18OpenBoundaryKernelPdS_S_id,@object # @_Z18OpenBoundaryKernelPdS_S_id .section .rodata,"a",@progbits .globl _Z18OpenBoundaryKernelPdS_S_id .p2align 3, 0x0 _Z18OpenBoundaryKernelPdS_S_id: .quad _Z33__device_stub__OpenBoundaryKernelPdS_S_id .size _Z18OpenBoundaryKernelPdS_S_id, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z18OpenBoundaryKernelPdS_S_id" .size .L__unnamed_1, 31 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z33__device_stub__OpenBoundaryKernelPdS_S_id .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z18OpenBoundaryKernelPdS_S_id .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void k4(int *Aux,int *S){ if(blockIdx.x==0) return; int tid=blockIdx.x*B+threadIdx.x; S[tid]+=Aux[blockIdx.x-1]; }
code for sm_80 Function : _Z2k4PiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */ /* 0x000e240000002500 */ /*0020*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */ /* 0x001fda0003f05270 */ /*0030*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e220000002100 */ /*0050*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */ /* 0x040fe20007ffe0ff */ /*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */ /* 0x000fe200078e00ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0080*/ LEA R4, R4, R3, 0x5 ; /* 0x0000000304047211 */ /* 0x001fe400078e28ff */ /*0090*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */ /* 0x000fc800078e0005 */ /*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */ /* 0x000fe400078e0205 */ /*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea8000c1e1900 */ /*00c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea4000c1e1900 */ /*00d0*/ IADD3 R7, R0, R3, RZ ; /* 0x0000000300077210 */ /* 0x004fca0007ffe0ff */ /*00e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x000fe2000c101904 */ /*00f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0100*/ BRA 0x100; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void k4(int *Aux,int *S){ if(blockIdx.x==0) return; int tid=blockIdx.x*B+threadIdx.x; S[tid]+=Aux[blockIdx.x-1]; }
.file "tmpxft_0018d3d8_00000000-6_k4.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z23__device_stub__Z2k4PiS_PiS_ .type _Z23__device_stub__Z2k4PiS_PiS_, @function _Z23__device_stub__Z2k4PiS_PiS_: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z2k4PiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z23__device_stub__Z2k4PiS_PiS_, .-_Z23__device_stub__Z2k4PiS_PiS_ .globl _Z2k4PiS_ .type _Z2k4PiS_, @function _Z2k4PiS_: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z23__device_stub__Z2k4PiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z2k4PiS_, .-_Z2k4PiS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z2k4PiS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z2k4PiS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void k4(int *Aux,int *S){ if(blockIdx.x==0) return; int tid=blockIdx.x*B+threadIdx.x; S[tid]+=Aux[blockIdx.x-1]; }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void k4(int *Aux,int *S){ if(blockIdx.x==0) return; int tid=blockIdx.x*B+threadIdx.x; S[tid]+=Aux[blockIdx.x-1]; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void k4(int *Aux,int *S){ if(blockIdx.x==0) return; int tid=blockIdx.x*B+threadIdx.x; S[tid]+=Aux[blockIdx.x-1]; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z2k4PiS_ .globl _Z2k4PiS_ .p2align 8 .type _Z2k4PiS_,@function _Z2k4PiS_: s_cmp_eq_u32 s15, 0 s_mov_b32 s3, 0 s_cbranch_scc1 .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x0 v_lshl_add_u32 v0, s15, 5, v0 s_add_i32 s2, s15, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_lshl_b64 s[0:1], s[2:3], 2 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s6, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_add_u32 s0, s4, s0 s_addc_u32 s1, s5, s1 s_load_b32 s0, s[0:1], 0x0 global_load_b32 v2, v[0:1], off s_waitcnt vmcnt(0) lgkmcnt(0) v_add_nc_u32_e32 v2, s0, v2 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z2k4PiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z2k4PiS_, .Lfunc_end0-_Z2k4PiS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z2k4PiS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z2k4PiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void k4(int *Aux,int *S){ if(blockIdx.x==0) return; int tid=blockIdx.x*B+threadIdx.x; S[tid]+=Aux[blockIdx.x-1]; }
.text .file "k4.hip" .globl _Z17__device_stub__k4PiS_ # -- Begin function _Z17__device_stub__k4PiS_ .p2align 4, 0x90 .type _Z17__device_stub__k4PiS_,@function _Z17__device_stub__k4PiS_: # @_Z17__device_stub__k4PiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z2k4PiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z17__device_stub__k4PiS_, .Lfunc_end0-_Z17__device_stub__k4PiS_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z2k4PiS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z2k4PiS_,@object # @_Z2k4PiS_ .section .rodata,"a",@progbits .globl _Z2k4PiS_ .p2align 3, 0x0 _Z2k4PiS_: .quad _Z17__device_stub__k4PiS_ .size _Z2k4PiS_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z2k4PiS_" .size .L__unnamed_1, 10 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z17__device_stub__k4PiS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z2k4PiS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z2k4PiS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */ /* 0x000e240000002500 */ /*0020*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */ /* 0x001fda0003f05270 */ /*0030*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e220000002100 */ /*0050*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */ /* 0x040fe20007ffe0ff */ /*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */ /* 0x000fe200078e00ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0080*/ LEA R4, R4, R3, 0x5 ; /* 0x0000000304047211 */ /* 0x001fe400078e28ff */ /*0090*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */ /* 0x000fc800078e0005 */ /*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */ /* 0x000fe400078e0205 */ /*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea8000c1e1900 */ /*00c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */ /* 0x000ea4000c1e1900 */ /*00d0*/ IADD3 R7, R0, R3, RZ ; /* 0x0000000300077210 */ /* 0x004fca0007ffe0ff */ /*00e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x000fe2000c101904 */ /*00f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0100*/ BRA 0x100; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z2k4PiS_ .globl _Z2k4PiS_ .p2align 8 .type _Z2k4PiS_,@function _Z2k4PiS_: s_cmp_eq_u32 s15, 0 s_mov_b32 s3, 0 s_cbranch_scc1 .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x0 v_lshl_add_u32 v0, s15, 5, v0 s_add_i32 s2, s15, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_lshl_b64 s[0:1], s[2:3], 2 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s6, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo s_add_u32 s0, s4, s0 s_addc_u32 s1, s5, s1 s_load_b32 s0, s[0:1], 0x0 global_load_b32 v2, v[0:1], off s_waitcnt vmcnt(0) lgkmcnt(0) v_add_nc_u32_e32 v2, s0, v2 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z2k4PiS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z2k4PiS_, .Lfunc_end0-_Z2k4PiS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z2k4PiS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z2k4PiS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0018d3d8_00000000-6_k4.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z23__device_stub__Z2k4PiS_PiS_ .type _Z23__device_stub__Z2k4PiS_PiS_, @function _Z23__device_stub__Z2k4PiS_PiS_: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z2k4PiS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z23__device_stub__Z2k4PiS_PiS_, .-_Z23__device_stub__Z2k4PiS_PiS_ .globl _Z2k4PiS_ .type _Z2k4PiS_, @function _Z2k4PiS_: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z23__device_stub__Z2k4PiS_PiS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z2k4PiS_, .-_Z2k4PiS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z2k4PiS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z2k4PiS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "k4.hip" .globl _Z17__device_stub__k4PiS_ # -- Begin function _Z17__device_stub__k4PiS_ .p2align 4, 0x90 .type _Z17__device_stub__k4PiS_,@function _Z17__device_stub__k4PiS_: # @_Z17__device_stub__k4PiS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z2k4PiS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z17__device_stub__k4PiS_, .Lfunc_end0-_Z17__device_stub__k4PiS_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z2k4PiS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z2k4PiS_,@object # @_Z2k4PiS_ .section .rodata,"a",@progbits .globl _Z2k4PiS_ .p2align 3, 0x0 _Z2k4PiS_: .quad _Z17__device_stub__k4PiS_ .size _Z2k4PiS_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z2k4PiS_" .size .L__unnamed_1, 10 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z17__device_stub__k4PiS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z2k4PiS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "AntSimple.cuh" #include <stdio.h> namespace SIMPLE { __device__ Ant::Ant(int initialLocation, int matrixDim, curandState_t randState) : visitedIndex(0), isVisited(new bool[matrixDim]), position(initialLocation), goodnessNumerators(new double[matrixDim]), m_randomState(randState) { } __device__ void Ant::Venture(int* route, const double* distanceMatrix, const double* pheromoneMatrix, int matrixDim, double alpha, double beta) { while (visitedIndex < matrixDim) { int nextHop = SelectNextHop(distanceMatrix, pheromoneMatrix, matrixDim, alpha, beta); GoTo(nextHop, route, distanceMatrix, matrixDim); } route[matrixDim] = route[0]; distance += distanceMatrix[route[matrixDim - 1] * matrixDim + route[0]]; //printf("Distance Traveled: %f\n", distance); } __device__ int Ant::SelectNextHop(const double* distance_matrix, const double* pheromoneMatrix, int matrixDim, double alpha, double beta) { double denominator = 0; for (int i = 0; i < matrixDim; ++i) { if (isVisited[i]) { continue; } int possiblePosition = i; double goodnessNumerator = pow(pheromoneMatrix[position * matrixDim + possiblePosition], alpha) * pow(1.0 / distance_matrix[position * matrixDim + possiblePosition], beta); goodnessNumerators[possiblePosition] = goodnessNumerator; denominator += goodnessNumerator; } //New /* for (int i = 0; i < matrixDim; ++i) { if (isVisited[i]) { continue; } goodnessNumerators[i] /= denominator; } double random = curand_uniform_double(&m_randomState); for (int i = 0; i < matrixDim; ++i) { if (isVisited[i]) { continue; } random -= goodnessNumerators[i]; if (random <= 0) { return i; } } return -1; */ double sum = 0; double random = curand_uniform_double(&m_randomState); //printf("Random is %f\n", random); for (int i = 0; i < matrixDim; ++i) { if (isVisited[i]) { continue; } int possiblePosition = i; double numerator = goodnessNumerators[possiblePosition]; double probability = numerator / denominator; if (random <= sum + probability) { return possiblePosition; } sum += probability; } return -1; } __device__ void Ant::GoTo(int next, int* route, const double* distanceMatrix, int matrixDim) { route[visitedIndex++] = next; isVisited[next] = true; distance += distanceMatrix[position * matrixDim + next]; position = next; } __device__ void Ant::Reset(int* route, int initialLocation, int matrixDim) { visitedIndex = 0; distance = 0; position = initialLocation; for (int i = 0; i < matrixDim; ++i) { isVisited[i] = false; } isVisited[position] = true; route[visitedIndex++] = initialLocation; } }
code for sm_80
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "AntSimple.cuh" #include <stdio.h> namespace SIMPLE { __device__ Ant::Ant(int initialLocation, int matrixDim, curandState_t randState) : visitedIndex(0), isVisited(new bool[matrixDim]), position(initialLocation), goodnessNumerators(new double[matrixDim]), m_randomState(randState) { } __device__ void Ant::Venture(int* route, const double* distanceMatrix, const double* pheromoneMatrix, int matrixDim, double alpha, double beta) { while (visitedIndex < matrixDim) { int nextHop = SelectNextHop(distanceMatrix, pheromoneMatrix, matrixDim, alpha, beta); GoTo(nextHop, route, distanceMatrix, matrixDim); } route[matrixDim] = route[0]; distance += distanceMatrix[route[matrixDim - 1] * matrixDim + route[0]]; //printf("Distance Traveled: %f\n", distance); } __device__ int Ant::SelectNextHop(const double* distance_matrix, const double* pheromoneMatrix, int matrixDim, double alpha, double beta) { double denominator = 0; for (int i = 0; i < matrixDim; ++i) { if (isVisited[i]) { continue; } int possiblePosition = i; double goodnessNumerator = pow(pheromoneMatrix[position * matrixDim + possiblePosition], alpha) * pow(1.0 / distance_matrix[position * matrixDim + possiblePosition], beta); goodnessNumerators[possiblePosition] = goodnessNumerator; denominator += goodnessNumerator; } //New /* for (int i = 0; i < matrixDim; ++i) { if (isVisited[i]) { continue; } goodnessNumerators[i] /= denominator; } double random = curand_uniform_double(&m_randomState); for (int i = 0; i < matrixDim; ++i) { if (isVisited[i]) { continue; } random -= goodnessNumerators[i]; if (random <= 0) { return i; } } return -1; */ double sum = 0; double random = curand_uniform_double(&m_randomState); //printf("Random is %f\n", random); for (int i = 0; i < matrixDim; ++i) { if (isVisited[i]) { continue; } int possiblePosition = i; double numerator = goodnessNumerators[possiblePosition]; double probability = numerator / denominator; if (random <= sum + probability) { return possiblePosition; } sum += probability; } return -1; } __device__ void Ant::GoTo(int next, int* route, const double* distanceMatrix, int matrixDim) { route[visitedIndex++] = next; isVisited[next] = true; distance += distanceMatrix[position * matrixDim + next]; position = next; } __device__ void Ant::Reset(int* route, int initialLocation, int matrixDim) { visitedIndex = 0; distance = 0; position = initialLocation; for (int i = 0; i < matrixDim; ++i) { isVisited[i] = false; } isVisited[position] = true; route[visitedIndex++] = initialLocation; } }
.file "tmpxft_000e593b_00000000-6_AntSimple.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2280: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2280: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .globl _ZN6SIMPLE3AntC2Eii17curandStateXORWOW .type _ZN6SIMPLE3AntC2Eii17curandStateXORWOW, @function _ZN6SIMPLE3AntC2Eii17curandStateXORWOW: .LFB2272: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $16, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbx movl %esi, %r12d movl $0, (%rdi) movslq %edx, %rbp movq %rbp, %rdi call _Znam@PLT movq %rax, 8(%rbx) movl %r12d, 16(%rbx) movq %rbp, %rax shrq $60, %rax jne .L4 leaq 0(,%rbp,8), %rdi call _Znam@PLT movq %rax, 24(%rbx) movdqu 48(%rsp), %xmm0 movups %xmm0, 32(%rbx) movdqu 64(%rsp), %xmm1 movups %xmm1, 48(%rbx) movdqu 80(%rsp), %xmm2 movups %xmm2, 64(%rbx) movq $0x000000000, 80(%rbx) movq $0, 8(%rsp) movq 8(%rsp), %rdi call free@PLT addq $16, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L4: .cfi_restore_state call __cxa_throw_bad_array_new_length@PLT .cfi_endproc .LFE2272: .size _ZN6SIMPLE3AntC2Eii17curandStateXORWOW, .-_ZN6SIMPLE3AntC2Eii17curandStateXORWOW .globl _ZN6SIMPLE3AntC1Eii17curandStateXORWOW .set _ZN6SIMPLE3AntC1Eii17curandStateXORWOW,_ZN6SIMPLE3AntC2Eii17curandStateXORWOW .align 2 .globl _ZN6SIMPLE3Ant7VentureEPiPKdS3_idd .type _ZN6SIMPLE3Ant7VentureEPiPKdS3_idd, @function _ZN6SIMPLE3Ant7VentureEPiPKdS3_idd: .LFB2274: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2274: .size _ZN6SIMPLE3Ant7VentureEPiPKdS3_idd, .-_ZN6SIMPLE3Ant7VentureEPiPKdS3_idd .align 2 .globl _ZN6SIMPLE3Ant13SelectNextHopEPKdS2_idd .type _ZN6SIMPLE3Ant13SelectNextHopEPKdS2_idd, @function _ZN6SIMPLE3Ant13SelectNextHopEPKdS2_idd: .LFB2275: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2275: .size _ZN6SIMPLE3Ant13SelectNextHopEPKdS2_idd, .-_ZN6SIMPLE3Ant13SelectNextHopEPKdS2_idd .align 2 .globl _ZN6SIMPLE3Ant4GoToEiPiPKdi .type _ZN6SIMPLE3Ant4GoToEiPiPKdi, @function _ZN6SIMPLE3Ant4GoToEiPiPKdi: .LFB2276: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2276: .size _ZN6SIMPLE3Ant4GoToEiPiPKdi, .-_ZN6SIMPLE3Ant4GoToEiPiPKdi .align 2 .globl _ZN6SIMPLE3Ant5ResetEPiii .type _ZN6SIMPLE3Ant5ResetEPiii, @function _ZN6SIMPLE3Ant5ResetEPiii: .LFB2277: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2277: .size _ZN6SIMPLE3Ant5ResetEPiii, .-_ZN6SIMPLE3Ant5ResetEPiii .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "precalc_xorwow_matrix" .LC2: .string "precalc_xorwow_offset_matrix" .LC3: .string "mrg32k3aM1" .LC4: .string "mrg32k3aM2" .LC5: .string "mrg32k3aM1SubSeq" .LC6: .string "mrg32k3aM2SubSeq" .LC7: .string "mrg32k3aM1Seq" .LC8: .string "mrg32k3aM2Seq" .LC9: .string "__cr_lgamma_table" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2303: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $102400, %r9d movl $0, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _ZL21precalc_xorwow_matrix(%rip), %rsi movq %rax, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $102400, %r9d movl $0, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _ZL10mrg32k3aM1(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _ZL10mrg32k3aM2(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2016, %r9d movl $0, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2016, %r9d movl $0, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _ZL13mrg32k3aM1Seq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _ZL13mrg32k3aM2Seq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $72, %r9d movl $0, %r8d leaq .LC9(%rip), %rdx movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2303: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "AntSimple.cuh" #include <stdio.h> namespace SIMPLE { __device__ Ant::Ant(int initialLocation, int matrixDim, curandState_t randState) : visitedIndex(0), isVisited(new bool[matrixDim]), position(initialLocation), goodnessNumerators(new double[matrixDim]), m_randomState(randState) { } __device__ void Ant::Venture(int* route, const double* distanceMatrix, const double* pheromoneMatrix, int matrixDim, double alpha, double beta) { while (visitedIndex < matrixDim) { int nextHop = SelectNextHop(distanceMatrix, pheromoneMatrix, matrixDim, alpha, beta); GoTo(nextHop, route, distanceMatrix, matrixDim); } route[matrixDim] = route[0]; distance += distanceMatrix[route[matrixDim - 1] * matrixDim + route[0]]; //printf("Distance Traveled: %f\n", distance); } __device__ int Ant::SelectNextHop(const double* distance_matrix, const double* pheromoneMatrix, int matrixDim, double alpha, double beta) { double denominator = 0; for (int i = 0; i < matrixDim; ++i) { if (isVisited[i]) { continue; } int possiblePosition = i; double goodnessNumerator = pow(pheromoneMatrix[position * matrixDim + possiblePosition], alpha) * pow(1.0 / distance_matrix[position * matrixDim + possiblePosition], beta); goodnessNumerators[possiblePosition] = goodnessNumerator; denominator += goodnessNumerator; } //New /* for (int i = 0; i < matrixDim; ++i) { if (isVisited[i]) { continue; } goodnessNumerators[i] /= denominator; } double random = curand_uniform_double(&m_randomState); for (int i = 0; i < matrixDim; ++i) { if (isVisited[i]) { continue; } random -= goodnessNumerators[i]; if (random <= 0) { return i; } } return -1; */ double sum = 0; double random = curand_uniform_double(&m_randomState); //printf("Random is %f\n", random); for (int i = 0; i < matrixDim; ++i) { if (isVisited[i]) { continue; } int possiblePosition = i; double numerator = goodnessNumerators[possiblePosition]; double probability = numerator / denominator; if (random <= sum + probability) { return possiblePosition; } sum += probability; } return -1; } __device__ void Ant::GoTo(int next, int* route, const double* distanceMatrix, int matrixDim) { route[visitedIndex++] = next; isVisited[next] = true; distance += distanceMatrix[position * matrixDim + next]; position = next; } __device__ void Ant::Reset(int* route, int initialLocation, int matrixDim) { visitedIndex = 0; distance = 0; position = initialLocation; for (int i = 0; i < matrixDim; ++i) { isVisited[i] = false; } isVisited[position] = true; route[visitedIndex++] = initialLocation; } }
#pragma once #include <hip/hip_runtime.h> #include <hiprand/hiprand_kernel.h> namespace SIMPLE { class Ant { int visitedIndex{}; bool* isVisited{}; int position{}; double* goodnessNumerators{}; hiprandState_t m_randomState{}; public: __device__ Ant(int initialLocation, int matrixDim, hiprandState_t randState); Ant() = default; __device__ void Venture(int* route, const double* distanceMatrix, const double* pheromoneMatrix, int matrixDim, double alpha, double beta); __device__ void Reset(int* route, int initialLocation, int matrixDim); double distance = 0; private: __device__ int SelectNextHop(const double* distance_matrix, const double* pheromoneMatrix, int matrixDim, double alpha, double beta); __device__ void GoTo(int next, int* route, const double* distanceMatrix, int matrixDim); }; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#pragma once #include <hip/hip_runtime.h> #include <hiprand/hiprand_kernel.h> namespace SIMPLE { class Ant { int visitedIndex{}; bool* isVisited{}; int position{}; double* goodnessNumerators{}; hiprandState_t m_randomState{}; public: __device__ Ant(int initialLocation, int matrixDim, hiprandState_t randState); Ant() = default; __device__ void Venture(int* route, const double* distanceMatrix, const double* pheromoneMatrix, int matrixDim, double alpha, double beta); __device__ void Reset(int* route, int initialLocation, int matrixDim); double distance = 0; private: __device__ int SelectNextHop(const double* distance_matrix, const double* pheromoneMatrix, int matrixDim, double alpha, double beta); __device__ void GoTo(int next, int* route, const double* distanceMatrix, int matrixDim); }; }
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#pragma once #include <hip/hip_runtime.h> #include <hiprand/hiprand_kernel.h> namespace SIMPLE { class Ant { int visitedIndex{}; bool* isVisited{}; int position{}; double* goodnessNumerators{}; hiprandState_t m_randomState{}; public: __device__ Ant(int initialLocation, int matrixDim, hiprandState_t randState); Ant() = default; __device__ void Venture(int* route, const double* distanceMatrix, const double* pheromoneMatrix, int matrixDim, double alpha, double beta); __device__ void Reset(int* route, int initialLocation, int matrixDim); double distance = 0; private: __device__ int SelectNextHop(const double* distance_matrix, const double* pheromoneMatrix, int matrixDim, double alpha, double beta); __device__ void GoTo(int next, int* route, const double* distanceMatrix, int matrixDim); }; }
.text .file "AntSimple.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000e593b_00000000-6_AntSimple.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2280: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2280: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .align 2 .globl _ZN6SIMPLE3AntC2Eii17curandStateXORWOW .type _ZN6SIMPLE3AntC2Eii17curandStateXORWOW, @function _ZN6SIMPLE3AntC2Eii17curandStateXORWOW: .LFB2272: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $16, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbx movl %esi, %r12d movl $0, (%rdi) movslq %edx, %rbp movq %rbp, %rdi call _Znam@PLT movq %rax, 8(%rbx) movl %r12d, 16(%rbx) movq %rbp, %rax shrq $60, %rax jne .L4 leaq 0(,%rbp,8), %rdi call _Znam@PLT movq %rax, 24(%rbx) movdqu 48(%rsp), %xmm0 movups %xmm0, 32(%rbx) movdqu 64(%rsp), %xmm1 movups %xmm1, 48(%rbx) movdqu 80(%rsp), %xmm2 movups %xmm2, 64(%rbx) movq $0x000000000, 80(%rbx) movq $0, 8(%rsp) movq 8(%rsp), %rdi call free@PLT addq $16, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L4: .cfi_restore_state call __cxa_throw_bad_array_new_length@PLT .cfi_endproc .LFE2272: .size _ZN6SIMPLE3AntC2Eii17curandStateXORWOW, .-_ZN6SIMPLE3AntC2Eii17curandStateXORWOW .globl _ZN6SIMPLE3AntC1Eii17curandStateXORWOW .set _ZN6SIMPLE3AntC1Eii17curandStateXORWOW,_ZN6SIMPLE3AntC2Eii17curandStateXORWOW .align 2 .globl _ZN6SIMPLE3Ant7VentureEPiPKdS3_idd .type _ZN6SIMPLE3Ant7VentureEPiPKdS3_idd, @function _ZN6SIMPLE3Ant7VentureEPiPKdS3_idd: .LFB2274: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2274: .size _ZN6SIMPLE3Ant7VentureEPiPKdS3_idd, .-_ZN6SIMPLE3Ant7VentureEPiPKdS3_idd .align 2 .globl _ZN6SIMPLE3Ant13SelectNextHopEPKdS2_idd .type _ZN6SIMPLE3Ant13SelectNextHopEPKdS2_idd, @function _ZN6SIMPLE3Ant13SelectNextHopEPKdS2_idd: .LFB2275: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2275: .size _ZN6SIMPLE3Ant13SelectNextHopEPKdS2_idd, .-_ZN6SIMPLE3Ant13SelectNextHopEPKdS2_idd .align 2 .globl _ZN6SIMPLE3Ant4GoToEiPiPKdi .type _ZN6SIMPLE3Ant4GoToEiPiPKdi, @function _ZN6SIMPLE3Ant4GoToEiPiPKdi: .LFB2276: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2276: .size _ZN6SIMPLE3Ant4GoToEiPiPKdi, .-_ZN6SIMPLE3Ant4GoToEiPiPKdi .align 2 .globl _ZN6SIMPLE3Ant5ResetEPiii .type _ZN6SIMPLE3Ant5ResetEPiii, @function _ZN6SIMPLE3Ant5ResetEPiii: .LFB2277: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2277: .size _ZN6SIMPLE3Ant5ResetEPiii, .-_ZN6SIMPLE3Ant5ResetEPiii .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "precalc_xorwow_matrix" .LC2: .string "precalc_xorwow_offset_matrix" .LC3: .string "mrg32k3aM1" .LC4: .string "mrg32k3aM2" .LC5: .string "mrg32k3aM1SubSeq" .LC6: .string "mrg32k3aM2SubSeq" .LC7: .string "mrg32k3aM1Seq" .LC8: .string "mrg32k3aM2Seq" .LC9: .string "__cr_lgamma_table" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2303: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $102400, %r9d movl $0, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _ZL21precalc_xorwow_matrix(%rip), %rsi movq %rax, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $102400, %r9d movl $0, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _ZL10mrg32k3aM1(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _ZL10mrg32k3aM2(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2016, %r9d movl $0, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2016, %r9d movl $0, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _ZL13mrg32k3aM1Seq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _ZL13mrg32k3aM2Seq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $72, %r9d movl $0, %r8d leaq .LC9(%rip), %rdx movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2303: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "AntSimple.hip" .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include<thrust/device_vector.h> #include<thrust/transform.h> #include<thrust/sequence.h> #include<thrust/copy.h> #include<thrust/fill.h> #include<thrust/replace.h> #include<thrust/functional.h> #include<iostream> int main(){ //allocate three device_vectors with 10 elements. thrust::device_vector<int> X(10); thrust::device_vector<int> Y(10); thrust::device_vector<int> Z(10); //initialize X to 0, 1, 2, 3,..... thrust::sequence(X.begin(),X.end()); //compute Y = -X thrust::transform(X.begin(),X.end(),Y.begin(),thrust::negate<int>()); //fill Z with two 2 thrust::fill(Z.begin(),Z.end(),2); //compute Y = X mod Z thrust::transform(X.begin(),X.end(),Z.begin(),Y.begin(),thrust::modulus<int>()); //replace all the ones in Y with tens thrust::replace(Y.begin(),Y.end(),1,10); //print Y thrust::copy(Y.begin(),Y.end(),std::ostream_iterator<int>(std::cout,"\n")); return 0; }
#include <hip/hip_runtime.h> #include<thrust/device_vector.h> #include<thrust/transform.h> #include<thrust/sequence.h> #include<thrust/copy.h> #include<thrust/fill.h> #include<thrust/replace.h> #include<thrust/functional.h> #include<iostream> int main(){ //allocate three device_vectors with 10 elements. thrust::device_vector<int> X(10); thrust::device_vector<int> Y(10); thrust::device_vector<int> Z(10); //initialize X to 0, 1, 2, 3,..... thrust::sequence(X.begin(),X.end()); //compute Y = -X thrust::transform(X.begin(),X.end(),Y.begin(),thrust::negate<int>()); //fill Z with two 2 thrust::fill(Z.begin(),Z.end(),2); //compute Y = X mod Z thrust::transform(X.begin(),X.end(),Z.begin(),Y.begin(),thrust::modulus<int>()); //replace all the ones in Y with tens thrust::replace(Y.begin(),Y.end(),1,10); //print Y thrust::copy(Y.begin(),Y.end(),std::ostream_iterator<int>(std::cout,"\n")); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include<thrust/device_vector.h> #include<thrust/transform.h> #include<thrust/sequence.h> #include<thrust/copy.h> #include<thrust/fill.h> #include<thrust/replace.h> #include<thrust/functional.h> #include<iostream> int main(){ //allocate three device_vectors with 10 elements. thrust::device_vector<int> X(10); thrust::device_vector<int> Y(10); thrust::device_vector<int> Z(10); //initialize X to 0, 1, 2, 3,..... thrust::sequence(X.begin(),X.end()); //compute Y = -X thrust::transform(X.begin(),X.end(),Y.begin(),thrust::negate<int>()); //fill Z with two 2 thrust::fill(Z.begin(),Z.end(),2); //compute Y = X mod Z thrust::transform(X.begin(),X.end(),Z.begin(),Y.begin(),thrust::modulus<int>()); //replace all the ones in Y with tens thrust::replace(Y.begin(),Y.end(),1,10); //print Y thrust::copy(Y.begin(),Y.end(),std::ostream_iterator<int>(std::cout,"\n")); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_: s_load_b128 s[4:7], s[0:1], 0x10 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB0_2 s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x0 s_load_b32 s6, s[0:1], 0x8 v_lshlrev_b32_e32 v0, 2, v0 s_lshl_b64 s[0:1], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s0, s4, s0 s_addc_u32 s1, s5, s1 v_add_co_u32 v0, s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s1, 0, s0 v_mov_b32_e32 v2, s6 flat_store_b32 v[0:1], v2 .LBB0_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat .Lfunc_end0: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .section .AMDGPU.csdata,"",@progbits .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_: s_load_b128 s[4:7], s[0:1], 0x10 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB1_2 s_load_b128 s[4:7], s[0:1], 0x0 v_add_co_u32 v0, s0, s2, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s3, 0, s0 v_lshlrev_b64 v[1:2], 2, v[0:1] s_waitcnt lgkmcnt(0) v_mad_u64_u32 v[3:4], null, s7, v0, s[6:7] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v0, vcc_lo, s4, v1 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo flat_store_b32 v[0:1], v3 .LBB1_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,comdat .Lfunc_end1: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_ .section .AMDGPU.csdata,"",@progbits .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_: s_load_b128 s[4:7], s[0:1], 0x18 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB2_2 s_load_b128 s[4:7], s[0:1], 0x0 v_add_co_u32 v0, s0, s2, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s3, 0, s0 v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo flat_load_b32 v2, v[2:3] s_waitcnt vmcnt(0) lgkmcnt(0) v_sub_nc_u32_e32 v2, 0, v2 flat_store_b32 v[0:1], v2 .LBB2_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 40 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat .Lfunc_end2: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_, .Lfunc_end2-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_ .section .AMDGPU.csdata,"",@progbits .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_: s_load_b128 s[4:7], s[0:1], 0x18 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB3_2 s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x8 s_load_b32 s6, s[0:1], 0x10 v_lshlrev_b32_e32 v0, 2, v0 s_lshl_b64 s[0:1], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s0, s4, s0 s_addc_u32 s1, s5, s1 v_add_co_u32 v0, s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s1, 0, s0 v_mov_b32_e32 v2, s6 flat_store_b32 v[0:1], v2 .LBB3_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 40 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat .Lfunc_end3: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_, .Lfunc_end3-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .section .AMDGPU.csdata,"",@progbits .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_: s_load_b128 s[4:7], s[0:1], 0x20 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB4_2 s_load_b128 s[4:7], s[0:1], 0x0 v_add_co_u32 v0, s2, s2, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s3, 0, s2 s_load_b64 s[0:1], s[0:1], 0x10 v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo flat_load_b32 v4, v[2:3] v_add_co_u32 v2, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo flat_load_b32 v2, v[2:3] s_waitcnt vmcnt(1) lgkmcnt(1) v_ashrrev_i32_e32 v3, 31, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v4, v4, v3 s_waitcnt vmcnt(0) lgkmcnt(0) v_ashrrev_i32_e32 v6, 31, v2 v_xor_b32_e32 v3, v4, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v2, v2, v6 v_cvt_f32_u32_e32 v4, v3 v_sub_nc_u32_e32 v5, 0, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v2, v2, v6 v_rcp_iflag_f32_e32 v4, v4 s_waitcnt_depctr 0xfff v_mul_f32_e32 v4, 0x4f7ffffe, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v4, v4 v_mul_lo_u32 v5, v5, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v5, v4, v5 v_add_nc_u32_e32 v4, v4, v5 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v4, v2, v4 v_mul_lo_u32 v4, v4, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_sub_nc_u32_e32 v2, v2, v4 v_sub_nc_u32_e32 v4, v2, v3 v_cmp_ge_u32_e32 vcc_lo, v2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cndmask_b32_e32 v2, v2, v4, vcc_lo v_sub_nc_u32_e32 v4, v2, v3 v_cmp_ge_u32_e32 vcc_lo, v2, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_cndmask_b32_e32 v2, v2, v4, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo v_xor_b32_e32 v2, v2, v6 s_delay_alu instid0(VALU_DEP_1) v_sub_nc_u32_e32 v2, v2, v6 flat_store_b32 v[0:1], v2 .LBB4_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 48 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat .Lfunc_end4: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_, .Lfunc_end4-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_ .section .AMDGPU.csdata,"",@progbits .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_: s_clause 0x2 s_load_b128 s[8:11], s[0:1], 0x20 s_load_b64 s[2:3], s[0:1], 0x0 s_load_b32 s4, s[0:1], 0x18 s_lshl_b32 s5, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s5, s5, s10 s_addc_u32 s6, 0, s11 s_sub_u32 s8, s8, s5 s_subb_u32 s9, s9, s6 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i64_e64 s7, 0x100, s[8:9] s_and_b32 s7, s7, exec_lo s_cselect_b32 s8, s8, 0x100 s_mov_b32 s7, 0 s_cmpk_lg_i32 s8, 0x100 s_cbranch_scc0 .LBB5_4 v_cmp_gt_u32_e32 vcc_lo, s8, v0 s_mov_b32 s8, 0 s_and_saveexec_b32 s9, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s9, exec_lo, s9 s_cbranch_execz .LBB5_3 v_add_co_u32 v1, s7, s5, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v2, null, s6, 0, s7 v_lshlrev_b64 v[3:4], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s2, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo flat_load_b32 v3, v[3:4] s_waitcnt vmcnt(0) lgkmcnt(0) v_cmp_eq_u32_e32 vcc_lo, s4, v3 s_and_b32 s7, vcc_lo, exec_lo .LBB5_3: s_or_b32 exec_lo, exec_lo, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s8 s_cbranch_vccnz .LBB5_5 s_branch .LBB5_6 .LBB5_4: s_cbranch_execz .LBB5_6 .LBB5_5: v_add_co_u32 v1, s5, s5, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v2, null, s6, 0, s5 v_lshlrev_b64 v[3:4], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s2, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo s_and_not1_b32 s2, s7, exec_lo flat_load_b32 v0, v[3:4] s_waitcnt vmcnt(0) lgkmcnt(0) v_cmp_eq_u32_e32 vcc_lo, s4, v0 s_and_b32 s3, vcc_lo, exec_lo s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 s7, s2, s3 .LBB5_6: s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s2, s7 s_cbranch_execnz .LBB5_8 s_endpgm .LBB5_8: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x8 s_load_b32 s0, s[0:1], 0x10 v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s2, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo v_mov_b32_e32 v2, s0 flat_store_b32 v[0:1], v2 s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 48 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_,comdat .Lfunc_end5: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_, .Lfunc_end5-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_ .section .AMDGPU.csdata,"",@progbits .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_: s_load_b128 s[4:7], s[0:1], 0x10 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB6_2 s_load_b128 s[4:7], s[0:1], 0x0 v_add_co_u32 v0, s0, s2, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s3, 0, s0 v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo flat_load_b32 v2, v[2:3] s_waitcnt vmcnt(0) lgkmcnt(0) flat_store_b32 v[0:1], v2 .LBB6_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_,comdat .Lfunc_end6: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_, .Lfunc_end6-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 16 .value_kind: by_value - .offset: 16 .size: 8 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 16 .value_kind: by_value - .offset: 16 .size: 8 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 24 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 40 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS_6negateIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 24 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 40 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 32 .value_kind: by_value - .offset: 32 .size: 8 .value_kind: by_value - .offset: 40 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 48 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagENS_7modulusIiEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 32 .value_kind: by_value - .offset: 32 .size: 8 .value_kind: by_value - .offset: 40 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 48 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_NS3_14no_stencil_tagENS0_9__replace10constant_fIiEENS5_10functional5actorINSE_9compositeIJNSE_27transparent_binary_operatorINS_8equal_toIvEEEENSF_INSE_8argumentILj0EEEEENSE_5valueIiEEEEEEEEElLj1EEEvT0_T1_SU_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 16 .value_kind: by_value - .offset: 16 .size: 8 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_copy7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_7pointerIiNS0_3tagENS_11use_defaultESC_EEEEmLj1EEEvT0_T1_SG_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
// Compile: nvcc -arch=sm_61 -std=c++11 assignment5-p3.cu -o assignment5-p3 #include <cmath> #include <iostream> #include <sys/time.h> #define SIZE 4096 #define THRESHOLD (0.000001) using namespace std; double rtclock() { struct timezone Tzp; struct timeval Tp; int stat; stat = gettimeofday(&Tp, &Tzp); if (stat != 0) { cout << "Error return from gettimeofday: " << stat << "\n"; } return (Tp.tv_sec + Tp.tv_usec * 1.0e-6); } __host__ void ATAonCPU(double** M, double** P) { for (int k = 0; k < SIZE; k++) { for (int i = 0; i < SIZE; i++) { for (int j = 0; j < SIZE; j++) P[i][j] += M[k][i] * M[k][j]; } } } __host__ void check_result(double** Test, double** Ref) { double maxdiff = 0, rel_diff = 0; int numdiffs = 0; for (int i = 0; i < SIZE; i++) { for (int j = 0; i < SIZE; j++) { rel_diff = (Test[i][j] - Ref[i][j]); if (fabs(rel_diff) > THRESHOLD) { numdiffs++; if (rel_diff > maxdiff) maxdiff = rel_diff; } } } if (numdiffs > 0) cout << numdiffs << " Diffs found over THRESHOLD " << THRESHOLD << " Max Diff = " << maxdiff << "\n"; else cout << "No differences found between base and test versions\n"; } // SB: Implement your kernel here __global__ void ATAkernel(double* A, double* B) {} int main() { cout << "Matrix Size = " << SIZE << "\n"; double** A = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { A[i] = new double[SIZE]; } double** O_s = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { O_s[i] = new double[SIZE]; } double** O_p = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { O_p[i] = new double[SIZE]; } for (int i = 0; i < SIZE; i++) { for (int j = 0; j < SIZE; j++) { A[i][j] = i * j * 0.25; O_s[i][j] = 0; O_p[i][j] = 0; } } double clkbegin, clkend; double t; clkbegin = rtclock(); ATAonCPU(A, O_s); clkend = rtclock(); t = clkend - clkbegin; cout << "A^T.A on CPU: " << (2.0 * SIZE * SIZE * SIZE / t / 1.0e9) << " GFLOPS; Time = " << t * 1000 << " msec\n"; cudaEvent_t start, end; cudaEventCreate(&start); cudaEventCreate(&end); cudaEventRecord(start, 0); // SB: Write your GPU kernel here cudaEventRecord(end, 0); float kernel_time; cudaEventElapsedTime(&kernel_time, start, end); cout << "A^T.A on GPU: " << (2.0 * SIZE * SIZE * SIZE / t / 1.0e9) << " GFLOPS; Time = " << kernel_time << " msec\n"; check_result(O_p, O_s); return EXIT_SUCCESS; }
code for sm_80 Function : _Z9ATAkernelPdS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
// Compile: nvcc -arch=sm_61 -std=c++11 assignment5-p3.cu -o assignment5-p3 #include <cmath> #include <iostream> #include <sys/time.h> #define SIZE 4096 #define THRESHOLD (0.000001) using namespace std; double rtclock() { struct timezone Tzp; struct timeval Tp; int stat; stat = gettimeofday(&Tp, &Tzp); if (stat != 0) { cout << "Error return from gettimeofday: " << stat << "\n"; } return (Tp.tv_sec + Tp.tv_usec * 1.0e-6); } __host__ void ATAonCPU(double** M, double** P) { for (int k = 0; k < SIZE; k++) { for (int i = 0; i < SIZE; i++) { for (int j = 0; j < SIZE; j++) P[i][j] += M[k][i] * M[k][j]; } } } __host__ void check_result(double** Test, double** Ref) { double maxdiff = 0, rel_diff = 0; int numdiffs = 0; for (int i = 0; i < SIZE; i++) { for (int j = 0; i < SIZE; j++) { rel_diff = (Test[i][j] - Ref[i][j]); if (fabs(rel_diff) > THRESHOLD) { numdiffs++; if (rel_diff > maxdiff) maxdiff = rel_diff; } } } if (numdiffs > 0) cout << numdiffs << " Diffs found over THRESHOLD " << THRESHOLD << " Max Diff = " << maxdiff << "\n"; else cout << "No differences found between base and test versions\n"; } // SB: Implement your kernel here __global__ void ATAkernel(double* A, double* B) {} int main() { cout << "Matrix Size = " << SIZE << "\n"; double** A = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { A[i] = new double[SIZE]; } double** O_s = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { O_s[i] = new double[SIZE]; } double** O_p = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { O_p[i] = new double[SIZE]; } for (int i = 0; i < SIZE; i++) { for (int j = 0; j < SIZE; j++) { A[i][j] = i * j * 0.25; O_s[i][j] = 0; O_p[i][j] = 0; } } double clkbegin, clkend; double t; clkbegin = rtclock(); ATAonCPU(A, O_s); clkend = rtclock(); t = clkend - clkbegin; cout << "A^T.A on CPU: " << (2.0 * SIZE * SIZE * SIZE / t / 1.0e9) << " GFLOPS; Time = " << t * 1000 << " msec\n"; cudaEvent_t start, end; cudaEventCreate(&start); cudaEventCreate(&end); cudaEventRecord(start, 0); // SB: Write your GPU kernel here cudaEventRecord(end, 0); float kernel_time; cudaEventElapsedTime(&kernel_time, start, end); cout << "A^T.A on GPU: " << (2.0 * SIZE * SIZE * SIZE / t / 1.0e9) << " GFLOPS; Time = " << kernel_time << " msec\n"; check_result(O_p, O_s); return EXIT_SUCCESS; }
.file "tmpxft_000c6ed4_00000000-6_template_p3.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3675: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3675: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "Error return from gettimeofday: " .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "\n" .text .globl _Z7rtclockv .type _Z7rtclockv, @function _Z7rtclockv: .LFB3669: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $56, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax leaq 8(%rsp), %rsi leaq 16(%rsp), %rdi call gettimeofday@PLT testl %eax, %eax jne .L7 .L4: pxor %xmm0, %xmm0 cvtsi2sdq 24(%rsp), %xmm0 mulsd .LC2(%rip), %xmm0 pxor %xmm1, %xmm1 cvtsi2sdq 16(%rsp), %xmm1 addsd %xmm1, %xmm0 movq 40(%rsp), %rax subq %fs:40, %rax jne .L8 addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state movl %eax, %ebx movl $32, %edx leaq .LC0(%rip), %rsi leaq _ZSt4cout(%rip), %rbp movq %rbp, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl %ebx, %esi movq %rbp, %rdi call _ZNSolsEi@PLT movq %rax, %rdi movl $1, %edx leaq .LC1(%rip), %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT jmp .L4 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size _Z7rtclockv, .-_Z7rtclockv .globl _Z8ATAonCPUPPdS0_ .type _Z8ATAonCPUPPdS0_, @function _Z8ATAonCPUPPdS0_: .LFB3670: .cfi_startproc endbr64 movq %rsi, %r10 movq %rdi, %r8 leaq 32768(%rdi), %r9 .L10: movq %r10, %rdi movl $0, %esi .L14: movl $0, %eax .L11: movq %rax, %rdx addq (%rdi), %rdx movq (%r8), %rcx movsd (%rcx,%rsi), %xmm0 mulsd (%rcx,%rax), %xmm0 addsd (%rdx), %xmm0 movsd %xmm0, (%rdx) addq $8, %rax cmpq $32768, %rax jne .L11 addq $8, %rdi addq $8, %rsi cmpq $32768, %rsi jne .L14 addq $8, %r8 cmpq %r9, %r8 jne .L10 ret .cfi_endproc .LFE3670: .size _Z8ATAonCPUPPdS0_, .-_Z8ATAonCPUPPdS0_ .globl _Z12check_resultPPdS0_ .type _Z12check_resultPPdS0_, @function _Z12check_resultPPdS0_: .LFB3671: .cfi_startproc endbr64 movl $0, %eax .L17: addq $8, %rax jmp .L17 .cfi_endproc .LFE3671: .size _Z12check_resultPPdS0_, .-_Z12check_resultPPdS0_ .section .rodata.str1.1 .LC5: .string "Matrix Size = " .LC7: .string "A^T.A on CPU: " .LC10: .string " GFLOPS; Time = " .LC12: .string " msec\n" .LC13: .string "A^T.A on GPU: " .text .globl main .type main, @function main: .LFB3672: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl $4096, %esi call _ZNSolsEi@PLT movq %rax, %rdi leaq .LC1(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $32768, %edi call _Znam@PLT movq %rax, %r12 movq %rax, %rbx leaq 32768(%rax), %rbp .L22: movl $32768, %edi call _Znam@PLT movq %rax, (%rbx) addq $8, %rbx cmpq %rbp, %rbx jne .L22 movl $32768, %edi call _Znam@PLT movq %rax, %rbx movq %rax, %rbp leaq 32768(%rax), %r13 .L23: movl $32768, %edi call _Znam@PLT movq %rax, 0(%rbp) addq $8, %rbp cmpq %r13, %rbp jne .L23 movl $32768, %edi call _Znam@PLT movq %rax, %rbp movq %rax, %r13 leaq 32768(%rax), %r14 .L24: movl $32768, %edi call _Znam@PLT movq %rax, 0(%r13) addq $8, %r13 cmpq %r14, %r13 jne .L24 movl $0, %r9d movsd .LC6(%rip), %xmm1 .L25: movq (%r12,%r9,8), %r8 movq (%rbx,%r9,8), %rdi movq 0(%rbp,%r9,8), %rsi movl %r9d, %ecx movl $0, %eax movl $0, %edx .L26: pxor %xmm0, %xmm0 cvtsi2sdl %edx, %xmm0 mulsd %xmm1, %xmm0 movsd %xmm0, (%r8,%rax) movq $0x000000000, (%rdi,%rax) movq $0x000000000, (%rsi,%rax) addl %ecx, %edx addq $8, %rax cmpq $32768, %rax jne .L26 addq $1, %r9 cmpq $4096, %r9 jne .L25 call _Z7rtclockv movsd %xmm0, 8(%rsp) movq %rbx, %rsi movq %r12, %rdi call _Z8ATAonCPUPPdS0_ call _Z7rtclockv movapd %xmm0, %xmm2 subsd 8(%rsp), %xmm2 movsd %xmm2, 8(%rsp) leaq .LC7(%rip), %rsi leaq _ZSt4cout(%rip), %r14 movq %r14, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movsd .LC8(%rip), %xmm0 divsd 8(%rsp), %xmm0 divsd .LC9(%rip), %xmm0 movq %xmm0, %r12 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC10(%rip), %r13 movq %r13, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movsd 8(%rsp), %xmm2 mulsd .LC11(%rip), %xmm2 movapd %xmm2, %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC12(%rip), %r15 movq %r15, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq 24(%rsp), %rdi call cudaEventCreate@PLT leaq 32(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT movl $0, %esi movq 32(%rsp), %rdi call cudaEventRecord@PLT leaq 20(%rsp), %rdi movq 32(%rsp), %rdx movq 24(%rsp), %rsi call cudaEventElapsedTime@PLT leaq .LC13(%rip), %rsi movq %r14, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq %r12, %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi movq %r13, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd 20(%rsp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi movq %r15, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbx, %rsi movq %rbp, %rdi call _Z12check_resultPPdS0_ .cfi_endproc .LFE3672: .size main, .-main .globl _Z30__device_stub__Z9ATAkernelPdS_PdS_ .type _Z30__device_stub__Z9ATAkernelPdS_PdS_, @function _Z30__device_stub__Z9ATAkernelPdS_PdS_: .LFB3697: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L38 .L34: movq 104(%rsp), %rax subq %fs:40, %rax jne .L39 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L38: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z9ATAkernelPdS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L34 .L39: call __stack_chk_fail@PLT .cfi_endproc .LFE3697: .size _Z30__device_stub__Z9ATAkernelPdS_PdS_, .-_Z30__device_stub__Z9ATAkernelPdS_PdS_ .globl _Z9ATAkernelPdS_ .type _Z9ATAkernelPdS_, @function _Z9ATAkernelPdS_: .LFB3698: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z9ATAkernelPdS_PdS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3698: .size _Z9ATAkernelPdS_, .-_Z9ATAkernelPdS_ .section .rodata.str1.1 .LC14: .string "_Z9ATAkernelPdS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3700: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC14(%rip), %rdx movq %rdx, %rcx leaq _Z9ATAkernelPdS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3700: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC2: .long -1598689907 .long 1051772663 .align 8 .LC6: .long 0 .long 1070596096 .align 8 .LC8: .long 0 .long 1111490560 .align 8 .LC9: .long 0 .long 1104006501 .align 8 .LC11: .long 0 .long 1083129856 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
// Compile: nvcc -arch=sm_61 -std=c++11 assignment5-p3.cu -o assignment5-p3 #include <cmath> #include <iostream> #include <sys/time.h> #define SIZE 4096 #define THRESHOLD (0.000001) using namespace std; double rtclock() { struct timezone Tzp; struct timeval Tp; int stat; stat = gettimeofday(&Tp, &Tzp); if (stat != 0) { cout << "Error return from gettimeofday: " << stat << "\n"; } return (Tp.tv_sec + Tp.tv_usec * 1.0e-6); } __host__ void ATAonCPU(double** M, double** P) { for (int k = 0; k < SIZE; k++) { for (int i = 0; i < SIZE; i++) { for (int j = 0; j < SIZE; j++) P[i][j] += M[k][i] * M[k][j]; } } } __host__ void check_result(double** Test, double** Ref) { double maxdiff = 0, rel_diff = 0; int numdiffs = 0; for (int i = 0; i < SIZE; i++) { for (int j = 0; i < SIZE; j++) { rel_diff = (Test[i][j] - Ref[i][j]); if (fabs(rel_diff) > THRESHOLD) { numdiffs++; if (rel_diff > maxdiff) maxdiff = rel_diff; } } } if (numdiffs > 0) cout << numdiffs << " Diffs found over THRESHOLD " << THRESHOLD << " Max Diff = " << maxdiff << "\n"; else cout << "No differences found between base and test versions\n"; } // SB: Implement your kernel here __global__ void ATAkernel(double* A, double* B) {} int main() { cout << "Matrix Size = " << SIZE << "\n"; double** A = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { A[i] = new double[SIZE]; } double** O_s = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { O_s[i] = new double[SIZE]; } double** O_p = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { O_p[i] = new double[SIZE]; } for (int i = 0; i < SIZE; i++) { for (int j = 0; j < SIZE; j++) { A[i][j] = i * j * 0.25; O_s[i][j] = 0; O_p[i][j] = 0; } } double clkbegin, clkend; double t; clkbegin = rtclock(); ATAonCPU(A, O_s); clkend = rtclock(); t = clkend - clkbegin; cout << "A^T.A on CPU: " << (2.0 * SIZE * SIZE * SIZE / t / 1.0e9) << " GFLOPS; Time = " << t * 1000 << " msec\n"; cudaEvent_t start, end; cudaEventCreate(&start); cudaEventCreate(&end); cudaEventRecord(start, 0); // SB: Write your GPU kernel here cudaEventRecord(end, 0); float kernel_time; cudaEventElapsedTime(&kernel_time, start, end); cout << "A^T.A on GPU: " << (2.0 * SIZE * SIZE * SIZE / t / 1.0e9) << " GFLOPS; Time = " << kernel_time << " msec\n"; check_result(O_p, O_s); return EXIT_SUCCESS; }
// Compile: nvcc -arch=sm_61 -std=c++11 assignment5-p3.cu -o assignment5-p3 #include <hip/hip_runtime.h> #include <cmath> #include <iostream> #include <sys/time.h> #define SIZE 4096 #define THRESHOLD (0.000001) using namespace std; double rtclock() { struct timezone Tzp; struct timeval Tp; int stat; stat = gettimeofday(&Tp, &Tzp); if (stat != 0) { cout << "Error return from gettimeofday: " << stat << "\n"; } return (Tp.tv_sec + Tp.tv_usec * 1.0e-6); } __host__ void ATAonCPU(double** M, double** P) { for (int k = 0; k < SIZE; k++) { for (int i = 0; i < SIZE; i++) { for (int j = 0; j < SIZE; j++) P[i][j] += M[k][i] * M[k][j]; } } } __host__ void check_result(double** Test, double** Ref) { double maxdiff = 0, rel_diff = 0; int numdiffs = 0; for (int i = 0; i < SIZE; i++) { for (int j = 0; i < SIZE; j++) { rel_diff = (Test[i][j] - Ref[i][j]); if (fabs(rel_diff) > THRESHOLD) { numdiffs++; if (rel_diff > maxdiff) maxdiff = rel_diff; } } } if (numdiffs > 0) cout << numdiffs << " Diffs found over THRESHOLD " << THRESHOLD << " Max Diff = " << maxdiff << "\n"; else cout << "No differences found between base and test versions\n"; } // SB: Implement your kernel here __global__ void ATAkernel(double* A, double* B) {} int main() { cout << "Matrix Size = " << SIZE << "\n"; double** A = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { A[i] = new double[SIZE]; } double** O_s = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { O_s[i] = new double[SIZE]; } double** O_p = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { O_p[i] = new double[SIZE]; } for (int i = 0; i < SIZE; i++) { for (int j = 0; j < SIZE; j++) { A[i][j] = i * j * 0.25; O_s[i][j] = 0; O_p[i][j] = 0; } } double clkbegin, clkend; double t; clkbegin = rtclock(); ATAonCPU(A, O_s); clkend = rtclock(); t = clkend - clkbegin; cout << "A^T.A on CPU: " << (2.0 * SIZE * SIZE * SIZE / t / 1.0e9) << " GFLOPS; Time = " << t * 1000 << " msec\n"; hipEvent_t start, end; hipEventCreate(&start); hipEventCreate(&end); hipEventRecord(start, 0); // SB: Write your GPU kernel here hipEventRecord(end, 0); float kernel_time; hipEventElapsedTime(&kernel_time, start, end); cout << "A^T.A on GPU: " << (2.0 * SIZE * SIZE * SIZE / t / 1.0e9) << " GFLOPS; Time = " << kernel_time << " msec\n"; check_result(O_p, O_s); return EXIT_SUCCESS; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
// Compile: nvcc -arch=sm_61 -std=c++11 assignment5-p3.cu -o assignment5-p3 #include <hip/hip_runtime.h> #include <cmath> #include <iostream> #include <sys/time.h> #define SIZE 4096 #define THRESHOLD (0.000001) using namespace std; double rtclock() { struct timezone Tzp; struct timeval Tp; int stat; stat = gettimeofday(&Tp, &Tzp); if (stat != 0) { cout << "Error return from gettimeofday: " << stat << "\n"; } return (Tp.tv_sec + Tp.tv_usec * 1.0e-6); } __host__ void ATAonCPU(double** M, double** P) { for (int k = 0; k < SIZE; k++) { for (int i = 0; i < SIZE; i++) { for (int j = 0; j < SIZE; j++) P[i][j] += M[k][i] * M[k][j]; } } } __host__ void check_result(double** Test, double** Ref) { double maxdiff = 0, rel_diff = 0; int numdiffs = 0; for (int i = 0; i < SIZE; i++) { for (int j = 0; i < SIZE; j++) { rel_diff = (Test[i][j] - Ref[i][j]); if (fabs(rel_diff) > THRESHOLD) { numdiffs++; if (rel_diff > maxdiff) maxdiff = rel_diff; } } } if (numdiffs > 0) cout << numdiffs << " Diffs found over THRESHOLD " << THRESHOLD << " Max Diff = " << maxdiff << "\n"; else cout << "No differences found between base and test versions\n"; } // SB: Implement your kernel here __global__ void ATAkernel(double* A, double* B) {} int main() { cout << "Matrix Size = " << SIZE << "\n"; double** A = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { A[i] = new double[SIZE]; } double** O_s = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { O_s[i] = new double[SIZE]; } double** O_p = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { O_p[i] = new double[SIZE]; } for (int i = 0; i < SIZE; i++) { for (int j = 0; j < SIZE; j++) { A[i][j] = i * j * 0.25; O_s[i][j] = 0; O_p[i][j] = 0; } } double clkbegin, clkend; double t; clkbegin = rtclock(); ATAonCPU(A, O_s); clkend = rtclock(); t = clkend - clkbegin; cout << "A^T.A on CPU: " << (2.0 * SIZE * SIZE * SIZE / t / 1.0e9) << " GFLOPS; Time = " << t * 1000 << " msec\n"; hipEvent_t start, end; hipEventCreate(&start); hipEventCreate(&end); hipEventRecord(start, 0); // SB: Write your GPU kernel here hipEventRecord(end, 0); float kernel_time; hipEventElapsedTime(&kernel_time, start, end); cout << "A^T.A on GPU: " << (2.0 * SIZE * SIZE * SIZE / t / 1.0e9) << " GFLOPS; Time = " << kernel_time << " msec\n"; check_result(O_p, O_s); return EXIT_SUCCESS; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9ATAkernelPdS_ .globl _Z9ATAkernelPdS_ .p2align 8 .type _Z9ATAkernelPdS_,@function _Z9ATAkernelPdS_: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9ATAkernelPdS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 1 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9ATAkernelPdS_, .Lfunc_end0-_Z9ATAkernelPdS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9ATAkernelPdS_ .private_segment_fixed_size: 0 .sgpr_count: 0 .sgpr_spill_count: 0 .symbol: _Z9ATAkernelPdS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
// Compile: nvcc -arch=sm_61 -std=c++11 assignment5-p3.cu -o assignment5-p3 #include <hip/hip_runtime.h> #include <cmath> #include <iostream> #include <sys/time.h> #define SIZE 4096 #define THRESHOLD (0.000001) using namespace std; double rtclock() { struct timezone Tzp; struct timeval Tp; int stat; stat = gettimeofday(&Tp, &Tzp); if (stat != 0) { cout << "Error return from gettimeofday: " << stat << "\n"; } return (Tp.tv_sec + Tp.tv_usec * 1.0e-6); } __host__ void ATAonCPU(double** M, double** P) { for (int k = 0; k < SIZE; k++) { for (int i = 0; i < SIZE; i++) { for (int j = 0; j < SIZE; j++) P[i][j] += M[k][i] * M[k][j]; } } } __host__ void check_result(double** Test, double** Ref) { double maxdiff = 0, rel_diff = 0; int numdiffs = 0; for (int i = 0; i < SIZE; i++) { for (int j = 0; i < SIZE; j++) { rel_diff = (Test[i][j] - Ref[i][j]); if (fabs(rel_diff) > THRESHOLD) { numdiffs++; if (rel_diff > maxdiff) maxdiff = rel_diff; } } } if (numdiffs > 0) cout << numdiffs << " Diffs found over THRESHOLD " << THRESHOLD << " Max Diff = " << maxdiff << "\n"; else cout << "No differences found between base and test versions\n"; } // SB: Implement your kernel here __global__ void ATAkernel(double* A, double* B) {} int main() { cout << "Matrix Size = " << SIZE << "\n"; double** A = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { A[i] = new double[SIZE]; } double** O_s = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { O_s[i] = new double[SIZE]; } double** O_p = new double*[SIZE]; for (int i = 0; i < SIZE; i++) { O_p[i] = new double[SIZE]; } for (int i = 0; i < SIZE; i++) { for (int j = 0; j < SIZE; j++) { A[i][j] = i * j * 0.25; O_s[i][j] = 0; O_p[i][j] = 0; } } double clkbegin, clkend; double t; clkbegin = rtclock(); ATAonCPU(A, O_s); clkend = rtclock(); t = clkend - clkbegin; cout << "A^T.A on CPU: " << (2.0 * SIZE * SIZE * SIZE / t / 1.0e9) << " GFLOPS; Time = " << t * 1000 << " msec\n"; hipEvent_t start, end; hipEventCreate(&start); hipEventCreate(&end); hipEventRecord(start, 0); // SB: Write your GPU kernel here hipEventRecord(end, 0); float kernel_time; hipEventElapsedTime(&kernel_time, start, end); cout << "A^T.A on GPU: " << (2.0 * SIZE * SIZE * SIZE / t / 1.0e9) << " GFLOPS; Time = " << kernel_time << " msec\n"; check_result(O_p, O_s); return EXIT_SUCCESS; }
.text .file "template_p3.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function _Z7rtclockv .LCPI0_0: .quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7 .text .globl _Z7rtclockv .p2align 4, 0x90 .type _Z7rtclockv,@function _Z7rtclockv: # @_Z7rtclockv .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 leaq 8(%rsp), %rdi leaq 24(%rsp), %rsi callq gettimeofday testl %eax, %eax je .LBB0_2 # %bb.1: movl %eax, %ebx movl $_ZSt4cout, %edi movl $.L.str, %esi movl $32, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %ebx, %esi callq _ZNSolsEi movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .LBB0_2: cvtsi2sdq 8(%rsp), %xmm1 cvtsi2sdq 16(%rsp), %xmm0 mulsd .LCPI0_0(%rip), %xmm0 addsd %xmm1, %xmm0 addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv .cfi_endproc # -- End function .globl _Z8ATAonCPUPPdS0_ # -- Begin function _Z8ATAonCPUPPdS0_ .p2align 4, 0x90 .type _Z8ATAonCPUPPdS0_,@function _Z8ATAonCPUPPdS0_: # @_Z8ATAonCPUPPdS0_ .cfi_startproc # %bb.0: xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # %.preheader16 # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 # Child Loop BB1_3 Depth 3 movq (%rdi,%rax,8), %rcx xorl %edx, %edx .p2align 4, 0x90 .LBB1_2: # %.preheader # Parent Loop BB1_1 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB1_3 Depth 3 movq (%rsi,%rdx,8), %r8 xorl %r9d, %r9d .p2align 4, 0x90 .LBB1_3: # Parent Loop BB1_1 Depth=1 # Parent Loop BB1_2 Depth=2 # => This Inner Loop Header: Depth=3 movsd (%rcx,%rdx,8), %xmm0 # xmm0 = mem[0],zero mulsd (%rcx,%r9,8), %xmm0 addsd (%r8,%r9,8), %xmm0 movsd %xmm0, (%r8,%r9,8) incq %r9 cmpq $4096, %r9 # imm = 0x1000 jne .LBB1_3 # %bb.4: # in Loop: Header=BB1_2 Depth=2 incq %rdx cmpq $4096, %rdx # imm = 0x1000 jne .LBB1_2 # %bb.5: # in Loop: Header=BB1_1 Depth=1 incq %rax cmpq $4096, %rax # imm = 0x1000 jne .LBB1_1 # %bb.6: retq .Lfunc_end1: .size _Z8ATAonCPUPPdS0_, .Lfunc_end1-_Z8ATAonCPUPPdS0_ .cfi_endproc # -- End function .globl _Z12check_resultPPdS0_ # -- Begin function _Z12check_resultPPdS0_ .p2align 4, 0x90 .type _Z12check_resultPPdS0_,@function _Z12check_resultPPdS0_: # @_Z12check_resultPPdS0_ .cfi_startproc # %bb.0: .Lfunc_end2: .size _Z12check_resultPPdS0_, .Lfunc_end2-_Z12check_resultPPdS0_ .cfi_endproc # -- End function .globl _Z24__device_stub__ATAkernelPdS_ # -- Begin function _Z24__device_stub__ATAkernelPdS_ .p2align 4, 0x90 .type _Z24__device_stub__ATAkernelPdS_,@function _Z24__device_stub__ATAkernelPdS_: # @_Z24__device_stub__ATAkernelPdS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z9ATAkernelPdS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end3: .size _Z24__device_stub__ATAkernelPdS_, .Lfunc_end3-_Z24__device_stub__ATAkernelPdS_ .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI4_0: .quad 0x3fd0000000000000 # double 0.25 .LCPI4_1: .quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7 .LCPI4_2: .quad 0x4240000000000000 # double 137438953472 .LCPI4_3: .quad 0x41cdcd6500000000 # double 1.0E+9 .LCPI4_4: .quad 0x408f400000000000 # double 1000 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $48, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $_ZSt4cout, %edi movl $.L.str.5, %esi movl $14, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl $4096, %esi # imm = 0x1000 callq _ZNSolsEi movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $32768, %edi # imm = 0x8000 callq _Znam movq %rax, %rbx xorl %r14d, %r14d .p2align 4, 0x90 .LBB4_1: # =>This Inner Loop Header: Depth=1 movl $32768, %edi # imm = 0x8000 callq _Znam movq %rax, (%rbx,%r14,8) incq %r14 cmpq $4096, %r14 # imm = 0x1000 jne .LBB4_1 # %bb.2: movl $32768, %edi # imm = 0x8000 callq _Znam movq %rax, %r14 xorl %r15d, %r15d .p2align 4, 0x90 .LBB4_3: # =>This Inner Loop Header: Depth=1 movl $32768, %edi # imm = 0x8000 callq _Znam movq %rax, (%r14,%r15,8) incq %r15 cmpq $4096, %r15 # imm = 0x1000 jne .LBB4_3 # %bb.4: movl $32768, %edi # imm = 0x8000 callq _Znam movq %rax, %r15 xorl %r12d, %r12d .p2align 4, 0x90 .LBB4_5: # =>This Inner Loop Header: Depth=1 movl $32768, %edi # imm = 0x8000 callq _Znam movq %rax, (%r15,%r12,8) incq %r12 cmpq $4096, %r12 # imm = 0x1000 jne .LBB4_5 # %bb.6: # %.preheader.preheader xorl %eax, %eax movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero .p2align 4, 0x90 .LBB4_7: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB4_8 Depth 2 movq (%rbx,%rax,8), %rcx movq (%r14,%rax,8), %rdx movq (%r15,%rax,8), %rsi xorl %edi, %edi xorl %r8d, %r8d .p2align 4, 0x90 .LBB4_8: # Parent Loop BB4_7 Depth=1 # => This Inner Loop Header: Depth=2 xorps %xmm1, %xmm1 cvtsi2sd %edi, %xmm1 mulsd %xmm0, %xmm1 movsd %xmm1, (%rcx,%r8,8) movq $0, (%rdx,%r8,8) movq $0, (%rsi,%r8,8) incq %r8 addl %eax, %edi cmpq $4096, %r8 # imm = 0x1000 jne .LBB4_8 # %bb.9: # in Loop: Header=BB4_7 Depth=1 incq %rax cmpq $4096, %rax # imm = 0x1000 jne .LBB4_7 # %bb.10: leaq 8(%rsp), %rdi movq %rsp, %rsi callq gettimeofday testl %eax, %eax je .LBB4_12 # %bb.11: movl %eax, %ebp movl $_ZSt4cout, %edi movl $.L.str, %esi movl $32, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %ebp, %esi callq _ZNSolsEi movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .LBB4_12: # %_Z7rtclockv.exit movq 8(%rsp), %r15 movq 16(%rsp), %r12 xorl %eax, %eax .p2align 4, 0x90 .LBB4_13: # %.preheader16.i # =>This Loop Header: Depth=1 # Child Loop BB4_14 Depth 2 # Child Loop BB4_15 Depth 3 movq (%rbx,%rax,8), %rcx xorl %edx, %edx .p2align 4, 0x90 .LBB4_14: # %.preheader.i # Parent Loop BB4_13 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB4_15 Depth 3 movq (%r14,%rdx,8), %rsi xorl %edi, %edi .p2align 4, 0x90 .LBB4_15: # Parent Loop BB4_13 Depth=1 # Parent Loop BB4_14 Depth=2 # => This Inner Loop Header: Depth=3 movsd (%rcx,%rdx,8), %xmm0 # xmm0 = mem[0],zero mulsd (%rcx,%rdi,8), %xmm0 addsd (%rsi,%rdi,8), %xmm0 movsd %xmm0, (%rsi,%rdi,8) incq %rdi cmpq $4096, %rdi # imm = 0x1000 jne .LBB4_15 # %bb.16: # in Loop: Header=BB4_14 Depth=2 incq %rdx cmpq $4096, %rdx # imm = 0x1000 jne .LBB4_14 # %bb.17: # in Loop: Header=BB4_13 Depth=1 incq %rax cmpq $4096, %rax # imm = 0x1000 jne .LBB4_13 # %bb.18: # %_Z8ATAonCPUPPdS0_.exit leaq 8(%rsp), %rdi movq %rsp, %rsi callq gettimeofday testl %eax, %eax je .LBB4_20 # %bb.19: movl %eax, %ebx movl $_ZSt4cout, %edi movl $.L.str, %esi movl $32, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %ebx, %esi callq _ZNSolsEi movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .LBB4_20: # %_Z7rtclockv.exit41 xorps %xmm0, %xmm0 cvtsi2sd %r12, %xmm0 movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero mulsd %xmm1, %xmm0 cvtsi2sd %r15, %xmm2 cvtsi2sdq 8(%rsp), %xmm3 cvtsi2sdq 16(%rsp), %xmm4 addsd %xmm0, %xmm2 mulsd %xmm1, %xmm4 addsd %xmm3, %xmm4 subsd %xmm2, %xmm4 movsd %xmm4, 32(%rsp) # 8-byte Spill movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $14, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movsd .LCPI4_2(%rip), %xmm0 # xmm0 = mem[0],zero divsd 32(%rsp), %xmm0 # 8-byte Folded Reload divsd .LCPI4_3(%rip), %xmm0 movsd %xmm0, 40(%rsp) # 8-byte Spill movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.7, %esi movl $16, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movsd 32(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero mulsd .LCPI4_4(%rip), %xmm0 movq %rbx, %rdi callq _ZNSo9_M_insertIdEERSoT_ movl $.L.str.8, %esi movl $6, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l leaq 8(%rsp), %rdi callq hipEventCreate movq %rsp, %rdi callq hipEventCreate movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq (%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 8(%rsp), %rsi movq (%rsp), %rdx leaq 28(%rsp), %rdi callq hipEventElapsedTime movl $_ZSt4cout, %edi movl $.L.str.9, %esi movl $14, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movsd 40(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.7, %esi movl $16, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movq %rbx, %rdi callq _ZNSo9_M_insertIdEERSoT_ movl $.L.str.8, %esi movl $6, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Lfunc_end4: .size main, .Lfunc_end4-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB5_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB5_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9ATAkernelPdS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end5: .size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB6_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB6_2: retq .Lfunc_end6: .size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Error return from gettimeofday: " .size .L.str, 33 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "\n" .size .L.str.1, 2 .type _Z9ATAkernelPdS_,@object # @_Z9ATAkernelPdS_ .section .rodata,"a",@progbits .globl _Z9ATAkernelPdS_ .p2align 3, 0x0 _Z9ATAkernelPdS_: .quad _Z24__device_stub__ATAkernelPdS_ .size _Z9ATAkernelPdS_, 8 .type .L.str.5,@object # @.str.5 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.5: .asciz "Matrix Size = " .size .L.str.5, 15 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "A^T.A on CPU: " .size .L.str.6, 15 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz " GFLOPS .size .L.str.7, 17 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz " msec\n" .size .L.str.8, 7 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "A^T.A on GPU: " .size .L.str.9, 15 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9ATAkernelPdS_" .size .L__unnamed_1, 17 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__ATAkernelPdS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _ZSt4cout .addrsig_sym _Z9ATAkernelPdS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z9ATAkernelPdS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9ATAkernelPdS_ .globl _Z9ATAkernelPdS_ .p2align 8 .type _Z9ATAkernelPdS_,@function _Z9ATAkernelPdS_: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9ATAkernelPdS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 1 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9ATAkernelPdS_, .Lfunc_end0-_Z9ATAkernelPdS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9ATAkernelPdS_ .private_segment_fixed_size: 0 .sgpr_count: 0 .sgpr_spill_count: 0 .symbol: _Z9ATAkernelPdS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000c6ed4_00000000-6_template_p3.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3675: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3675: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "Error return from gettimeofday: " .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "\n" .text .globl _Z7rtclockv .type _Z7rtclockv, @function _Z7rtclockv: .LFB3669: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $56, %rsp .cfi_def_cfa_offset 80 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax leaq 8(%rsp), %rsi leaq 16(%rsp), %rdi call gettimeofday@PLT testl %eax, %eax jne .L7 .L4: pxor %xmm0, %xmm0 cvtsi2sdq 24(%rsp), %xmm0 mulsd .LC2(%rip), %xmm0 pxor %xmm1, %xmm1 cvtsi2sdq 16(%rsp), %xmm1 addsd %xmm1, %xmm0 movq 40(%rsp), %rax subq %fs:40, %rax jne .L8 addq $56, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state movl %eax, %ebx movl $32, %edx leaq .LC0(%rip), %rsi leaq _ZSt4cout(%rip), %rbp movq %rbp, %rdi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT movl %ebx, %esi movq %rbp, %rdi call _ZNSolsEi@PLT movq %rax, %rdi movl $1, %edx leaq .LC1(%rip), %rsi call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT jmp .L4 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size _Z7rtclockv, .-_Z7rtclockv .globl _Z8ATAonCPUPPdS0_ .type _Z8ATAonCPUPPdS0_, @function _Z8ATAonCPUPPdS0_: .LFB3670: .cfi_startproc endbr64 movq %rsi, %r10 movq %rdi, %r8 leaq 32768(%rdi), %r9 .L10: movq %r10, %rdi movl $0, %esi .L14: movl $0, %eax .L11: movq %rax, %rdx addq (%rdi), %rdx movq (%r8), %rcx movsd (%rcx,%rsi), %xmm0 mulsd (%rcx,%rax), %xmm0 addsd (%rdx), %xmm0 movsd %xmm0, (%rdx) addq $8, %rax cmpq $32768, %rax jne .L11 addq $8, %rdi addq $8, %rsi cmpq $32768, %rsi jne .L14 addq $8, %r8 cmpq %r9, %r8 jne .L10 ret .cfi_endproc .LFE3670: .size _Z8ATAonCPUPPdS0_, .-_Z8ATAonCPUPPdS0_ .globl _Z12check_resultPPdS0_ .type _Z12check_resultPPdS0_, @function _Z12check_resultPPdS0_: .LFB3671: .cfi_startproc endbr64 movl $0, %eax .L17: addq $8, %rax jmp .L17 .cfi_endproc .LFE3671: .size _Z12check_resultPPdS0_, .-_Z12check_resultPPdS0_ .section .rodata.str1.1 .LC5: .string "Matrix Size = " .LC7: .string "A^T.A on CPU: " .LC10: .string " GFLOPS; Time = " .LC12: .string " msec\n" .LC13: .string "A^T.A on GPU: " .text .globl main .type main, @function main: .LFB3672: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $56, %rsp .cfi_def_cfa_offset 112 movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax leaq .LC5(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movl $4096, %esi call _ZNSolsEi@PLT movq %rax, %rdi leaq .LC1(%rip), %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $32768, %edi call _Znam@PLT movq %rax, %r12 movq %rax, %rbx leaq 32768(%rax), %rbp .L22: movl $32768, %edi call _Znam@PLT movq %rax, (%rbx) addq $8, %rbx cmpq %rbp, %rbx jne .L22 movl $32768, %edi call _Znam@PLT movq %rax, %rbx movq %rax, %rbp leaq 32768(%rax), %r13 .L23: movl $32768, %edi call _Znam@PLT movq %rax, 0(%rbp) addq $8, %rbp cmpq %r13, %rbp jne .L23 movl $32768, %edi call _Znam@PLT movq %rax, %rbp movq %rax, %r13 leaq 32768(%rax), %r14 .L24: movl $32768, %edi call _Znam@PLT movq %rax, 0(%r13) addq $8, %r13 cmpq %r14, %r13 jne .L24 movl $0, %r9d movsd .LC6(%rip), %xmm1 .L25: movq (%r12,%r9,8), %r8 movq (%rbx,%r9,8), %rdi movq 0(%rbp,%r9,8), %rsi movl %r9d, %ecx movl $0, %eax movl $0, %edx .L26: pxor %xmm0, %xmm0 cvtsi2sdl %edx, %xmm0 mulsd %xmm1, %xmm0 movsd %xmm0, (%r8,%rax) movq $0x000000000, (%rdi,%rax) movq $0x000000000, (%rsi,%rax) addl %ecx, %edx addq $8, %rax cmpq $32768, %rax jne .L26 addq $1, %r9 cmpq $4096, %r9 jne .L25 call _Z7rtclockv movsd %xmm0, 8(%rsp) movq %rbx, %rsi movq %r12, %rdi call _Z8ATAonCPUPPdS0_ call _Z7rtclockv movapd %xmm0, %xmm2 subsd 8(%rsp), %xmm2 movsd %xmm2, 8(%rsp) leaq .LC7(%rip), %rsi leaq _ZSt4cout(%rip), %r14 movq %r14, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movsd .LC8(%rip), %xmm0 divsd 8(%rsp), %xmm0 divsd .LC9(%rip), %xmm0 movq %xmm0, %r12 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC10(%rip), %r13 movq %r13, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movsd 8(%rsp), %xmm2 mulsd .LC11(%rip), %xmm2 movapd %xmm2, %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi leaq .LC12(%rip), %r15 movq %r15, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq 24(%rsp), %rdi call cudaEventCreate@PLT leaq 32(%rsp), %rdi call cudaEventCreate@PLT movl $0, %esi movq 24(%rsp), %rdi call cudaEventRecord@PLT movl $0, %esi movq 32(%rsp), %rdi call cudaEventRecord@PLT leaq 20(%rsp), %rdi movq 32(%rsp), %rdx movq 24(%rsp), %rsi call cudaEventElapsedTime@PLT leaq .LC13(%rip), %rsi movq %r14, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi movq %r12, %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi movq %r13, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rax, %rdi pxor %xmm0, %xmm0 cvtss2sd 20(%rsp), %xmm0 call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rdi movq %r15, %rsi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %rbx, %rsi movq %rbp, %rdi call _Z12check_resultPPdS0_ .cfi_endproc .LFE3672: .size main, .-main .globl _Z30__device_stub__Z9ATAkernelPdS_PdS_ .type _Z30__device_stub__Z9ATAkernelPdS_PdS_, @function _Z30__device_stub__Z9ATAkernelPdS_PdS_: .LFB3697: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L38 .L34: movq 104(%rsp), %rax subq %fs:40, %rax jne .L39 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L38: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z9ATAkernelPdS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L34 .L39: call __stack_chk_fail@PLT .cfi_endproc .LFE3697: .size _Z30__device_stub__Z9ATAkernelPdS_PdS_, .-_Z30__device_stub__Z9ATAkernelPdS_PdS_ .globl _Z9ATAkernelPdS_ .type _Z9ATAkernelPdS_, @function _Z9ATAkernelPdS_: .LFB3698: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z9ATAkernelPdS_PdS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3698: .size _Z9ATAkernelPdS_, .-_Z9ATAkernelPdS_ .section .rodata.str1.1 .LC14: .string "_Z9ATAkernelPdS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3700: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC14(%rip), %rdx movq %rdx, %rcx leaq _Z9ATAkernelPdS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3700: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst8,"aM",@progbits,8 .align 8 .LC2: .long -1598689907 .long 1051772663 .align 8 .LC6: .long 0 .long 1070596096 .align 8 .LC8: .long 0 .long 1111490560 .align 8 .LC9: .long 0 .long 1104006501 .align 8 .LC11: .long 0 .long 1083129856 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "template_p3.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function _Z7rtclockv .LCPI0_0: .quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7 .text .globl _Z7rtclockv .p2align 4, 0x90 .type _Z7rtclockv,@function _Z7rtclockv: # @_Z7rtclockv .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 leaq 8(%rsp), %rdi leaq 24(%rsp), %rsi callq gettimeofday testl %eax, %eax je .LBB0_2 # %bb.1: movl %eax, %ebx movl $_ZSt4cout, %edi movl $.L.str, %esi movl $32, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %ebx, %esi callq _ZNSolsEi movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .LBB0_2: cvtsi2sdq 8(%rsp), %xmm1 cvtsi2sdq 16(%rsp), %xmm0 mulsd .LCPI0_0(%rip), %xmm0 addsd %xmm1, %xmm0 addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv .cfi_endproc # -- End function .globl _Z8ATAonCPUPPdS0_ # -- Begin function _Z8ATAonCPUPPdS0_ .p2align 4, 0x90 .type _Z8ATAonCPUPPdS0_,@function _Z8ATAonCPUPPdS0_: # @_Z8ATAonCPUPPdS0_ .cfi_startproc # %bb.0: xorl %eax, %eax .p2align 4, 0x90 .LBB1_1: # %.preheader16 # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 # Child Loop BB1_3 Depth 3 movq (%rdi,%rax,8), %rcx xorl %edx, %edx .p2align 4, 0x90 .LBB1_2: # %.preheader # Parent Loop BB1_1 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB1_3 Depth 3 movq (%rsi,%rdx,8), %r8 xorl %r9d, %r9d .p2align 4, 0x90 .LBB1_3: # Parent Loop BB1_1 Depth=1 # Parent Loop BB1_2 Depth=2 # => This Inner Loop Header: Depth=3 movsd (%rcx,%rdx,8), %xmm0 # xmm0 = mem[0],zero mulsd (%rcx,%r9,8), %xmm0 addsd (%r8,%r9,8), %xmm0 movsd %xmm0, (%r8,%r9,8) incq %r9 cmpq $4096, %r9 # imm = 0x1000 jne .LBB1_3 # %bb.4: # in Loop: Header=BB1_2 Depth=2 incq %rdx cmpq $4096, %rdx # imm = 0x1000 jne .LBB1_2 # %bb.5: # in Loop: Header=BB1_1 Depth=1 incq %rax cmpq $4096, %rax # imm = 0x1000 jne .LBB1_1 # %bb.6: retq .Lfunc_end1: .size _Z8ATAonCPUPPdS0_, .Lfunc_end1-_Z8ATAonCPUPPdS0_ .cfi_endproc # -- End function .globl _Z12check_resultPPdS0_ # -- Begin function _Z12check_resultPPdS0_ .p2align 4, 0x90 .type _Z12check_resultPPdS0_,@function _Z12check_resultPPdS0_: # @_Z12check_resultPPdS0_ .cfi_startproc # %bb.0: .Lfunc_end2: .size _Z12check_resultPPdS0_, .Lfunc_end2-_Z12check_resultPPdS0_ .cfi_endproc # -- End function .globl _Z24__device_stub__ATAkernelPdS_ # -- Begin function _Z24__device_stub__ATAkernelPdS_ .p2align 4, 0x90 .type _Z24__device_stub__ATAkernelPdS_,@function _Z24__device_stub__ATAkernelPdS_: # @_Z24__device_stub__ATAkernelPdS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z9ATAkernelPdS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end3: .size _Z24__device_stub__ATAkernelPdS_, .Lfunc_end3-_Z24__device_stub__ATAkernelPdS_ .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI4_0: .quad 0x3fd0000000000000 # double 0.25 .LCPI4_1: .quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7 .LCPI4_2: .quad 0x4240000000000000 # double 137438953472 .LCPI4_3: .quad 0x41cdcd6500000000 # double 1.0E+9 .LCPI4_4: .quad 0x408f400000000000 # double 1000 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $48, %rsp .cfi_def_cfa_offset 96 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl $_ZSt4cout, %edi movl $.L.str.5, %esi movl $14, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl $4096, %esi # imm = 0x1000 callq _ZNSolsEi movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $32768, %edi # imm = 0x8000 callq _Znam movq %rax, %rbx xorl %r14d, %r14d .p2align 4, 0x90 .LBB4_1: # =>This Inner Loop Header: Depth=1 movl $32768, %edi # imm = 0x8000 callq _Znam movq %rax, (%rbx,%r14,8) incq %r14 cmpq $4096, %r14 # imm = 0x1000 jne .LBB4_1 # %bb.2: movl $32768, %edi # imm = 0x8000 callq _Znam movq %rax, %r14 xorl %r15d, %r15d .p2align 4, 0x90 .LBB4_3: # =>This Inner Loop Header: Depth=1 movl $32768, %edi # imm = 0x8000 callq _Znam movq %rax, (%r14,%r15,8) incq %r15 cmpq $4096, %r15 # imm = 0x1000 jne .LBB4_3 # %bb.4: movl $32768, %edi # imm = 0x8000 callq _Znam movq %rax, %r15 xorl %r12d, %r12d .p2align 4, 0x90 .LBB4_5: # =>This Inner Loop Header: Depth=1 movl $32768, %edi # imm = 0x8000 callq _Znam movq %rax, (%r15,%r12,8) incq %r12 cmpq $4096, %r12 # imm = 0x1000 jne .LBB4_5 # %bb.6: # %.preheader.preheader xorl %eax, %eax movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero .p2align 4, 0x90 .LBB4_7: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB4_8 Depth 2 movq (%rbx,%rax,8), %rcx movq (%r14,%rax,8), %rdx movq (%r15,%rax,8), %rsi xorl %edi, %edi xorl %r8d, %r8d .p2align 4, 0x90 .LBB4_8: # Parent Loop BB4_7 Depth=1 # => This Inner Loop Header: Depth=2 xorps %xmm1, %xmm1 cvtsi2sd %edi, %xmm1 mulsd %xmm0, %xmm1 movsd %xmm1, (%rcx,%r8,8) movq $0, (%rdx,%r8,8) movq $0, (%rsi,%r8,8) incq %r8 addl %eax, %edi cmpq $4096, %r8 # imm = 0x1000 jne .LBB4_8 # %bb.9: # in Loop: Header=BB4_7 Depth=1 incq %rax cmpq $4096, %rax # imm = 0x1000 jne .LBB4_7 # %bb.10: leaq 8(%rsp), %rdi movq %rsp, %rsi callq gettimeofday testl %eax, %eax je .LBB4_12 # %bb.11: movl %eax, %ebp movl $_ZSt4cout, %edi movl $.L.str, %esi movl $32, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %ebp, %esi callq _ZNSolsEi movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .LBB4_12: # %_Z7rtclockv.exit movq 8(%rsp), %r15 movq 16(%rsp), %r12 xorl %eax, %eax .p2align 4, 0x90 .LBB4_13: # %.preheader16.i # =>This Loop Header: Depth=1 # Child Loop BB4_14 Depth 2 # Child Loop BB4_15 Depth 3 movq (%rbx,%rax,8), %rcx xorl %edx, %edx .p2align 4, 0x90 .LBB4_14: # %.preheader.i # Parent Loop BB4_13 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB4_15 Depth 3 movq (%r14,%rdx,8), %rsi xorl %edi, %edi .p2align 4, 0x90 .LBB4_15: # Parent Loop BB4_13 Depth=1 # Parent Loop BB4_14 Depth=2 # => This Inner Loop Header: Depth=3 movsd (%rcx,%rdx,8), %xmm0 # xmm0 = mem[0],zero mulsd (%rcx,%rdi,8), %xmm0 addsd (%rsi,%rdi,8), %xmm0 movsd %xmm0, (%rsi,%rdi,8) incq %rdi cmpq $4096, %rdi # imm = 0x1000 jne .LBB4_15 # %bb.16: # in Loop: Header=BB4_14 Depth=2 incq %rdx cmpq $4096, %rdx # imm = 0x1000 jne .LBB4_14 # %bb.17: # in Loop: Header=BB4_13 Depth=1 incq %rax cmpq $4096, %rax # imm = 0x1000 jne .LBB4_13 # %bb.18: # %_Z8ATAonCPUPPdS0_.exit leaq 8(%rsp), %rdi movq %rsp, %rsi callq gettimeofday testl %eax, %eax je .LBB4_20 # %bb.19: movl %eax, %ebx movl $_ZSt4cout, %edi movl $.L.str, %esi movl $32, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movl %ebx, %esi callq _ZNSolsEi movl $.L.str.1, %esi movl $1, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .LBB4_20: # %_Z7rtclockv.exit41 xorps %xmm0, %xmm0 cvtsi2sd %r12, %xmm0 movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero mulsd %xmm1, %xmm0 cvtsi2sd %r15, %xmm2 cvtsi2sdq 8(%rsp), %xmm3 cvtsi2sdq 16(%rsp), %xmm4 addsd %xmm0, %xmm2 mulsd %xmm1, %xmm4 addsd %xmm3, %xmm4 subsd %xmm2, %xmm4 movsd %xmm4, 32(%rsp) # 8-byte Spill movl $_ZSt4cout, %edi movl $.L.str.6, %esi movl $14, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movsd .LCPI4_2(%rip), %xmm0 # xmm0 = mem[0],zero divsd 32(%rsp), %xmm0 # 8-byte Folded Reload divsd .LCPI4_3(%rip), %xmm0 movsd %xmm0, 40(%rsp) # 8-byte Spill movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.7, %esi movl $16, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movsd 32(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero mulsd .LCPI4_4(%rip), %xmm0 movq %rbx, %rdi callq _ZNSo9_M_insertIdEERSoT_ movl $.L.str.8, %esi movl $6, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l leaq 8(%rsp), %rdi callq hipEventCreate movq %rsp, %rdi callq hipEventCreate movq 8(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq (%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 8(%rsp), %rsi movq (%rsp), %rdx leaq 28(%rsp), %rdi callq hipEventElapsedTime movl $_ZSt4cout, %edi movl $.L.str.9, %esi movl $14, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movl $_ZSt4cout, %edi movsd 40(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero callq _ZNSo9_M_insertIdEERSoT_ movq %rax, %rbx movl $.L.str.7, %esi movl $16, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movq %rbx, %rdi callq _ZNSo9_M_insertIdEERSoT_ movl $.L.str.8, %esi movl $6, %edx movq %rax, %rdi callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l .Lfunc_end4: .size main, .Lfunc_end4-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB5_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB5_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9ATAkernelPdS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end5: .size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB6_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB6_2: retq .Lfunc_end6: .size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Error return from gettimeofday: " .size .L.str, 33 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "\n" .size .L.str.1, 2 .type _Z9ATAkernelPdS_,@object # @_Z9ATAkernelPdS_ .section .rodata,"a",@progbits .globl _Z9ATAkernelPdS_ .p2align 3, 0x0 _Z9ATAkernelPdS_: .quad _Z24__device_stub__ATAkernelPdS_ .size _Z9ATAkernelPdS_, 8 .type .L.str.5,@object # @.str.5 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.5: .asciz "Matrix Size = " .size .L.str.5, 15 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "A^T.A on CPU: " .size .L.str.6, 15 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz " GFLOPS .size .L.str.7, 17 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz " msec\n" .size .L.str.8, 7 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "A^T.A on GPU: " .size .L.str.9, 15 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9ATAkernelPdS_" .size .L__unnamed_1, 17 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__ATAkernelPdS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _ZSt4cout .addrsig_sym _Z9ATAkernelPdS_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void callOperation(int *a, int *b, int x, int *res, int n) { int tid = blockDim.x * blockIdx.x + threadIdx.x; if (tid < n) { res[tid] = ((a[tid] * x) + b[tid]); } }
code for sm_80 Function : _Z13callOperationPiS_iS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */ /* 0x000fc800078e0207 */ /*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */ /* 0x0c0fe400078e0207 */ /*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea8000c1e1900 */ /*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */ /* 0x000ea2000c1e1900 */ /*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */ /* 0x000fc800078e0207 */ /*00d0*/ IMAD R9, R2, c[0x0][0x170], R5 ; /* 0x00005c0002097a24 */ /* 0x004fca00078e0205 */ /*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*00f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0100*/ BRA 0x100; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void callOperation(int *a, int *b, int x, int *res, int n) { int tid = blockDim.x * blockIdx.x + threadIdx.x; if (tid < n) { res[tid] = ((a[tid] * x) + b[tid]); } }
.file "tmpxft_00005d93_00000000-6_callOperation.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z39__device_stub__Z13callOperationPiS_iS_iPiS_iS_i .type _Z39__device_stub__Z13callOperationPiS_iS_iPiS_iS_i, @function _Z39__device_stub__Z13callOperationPiS_iS_iPiS_iS_i: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %rcx, (%rsp) movl %r8d, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) leaq 8(%rsp), %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z13callOperationPiS_iS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z39__device_stub__Z13callOperationPiS_iS_iPiS_iS_i, .-_Z39__device_stub__Z13callOperationPiS_iS_iPiS_iS_i .globl _Z13callOperationPiS_iS_i .type _Z13callOperationPiS_iS_i, @function _Z13callOperationPiS_iS_i: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z39__device_stub__Z13callOperationPiS_iS_iPiS_iS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z13callOperationPiS_iS_i, .-_Z13callOperationPiS_iS_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z13callOperationPiS_iS_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z13callOperationPiS_iS_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void callOperation(int *a, int *b, int x, int *res, int n) { int tid = blockDim.x * blockIdx.x + threadIdx.x; if (tid < n) { res[tid] = ((a[tid] * x) + b[tid]); } }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void callOperation(int *a, int *b, int x, int *res, int n) { int tid = blockDim.x * blockIdx.x + threadIdx.x; if (tid < n) { res[tid] = ((a[tid] * x) + b[tid]); } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void callOperation(int *a, int *b, int x, int *res, int n) { int tid = blockDim.x * blockIdx.x + threadIdx.x; if (tid < n) { res[tid] = ((a[tid] * x) + b[tid]); } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13callOperationPiS_iS_i .globl _Z13callOperationPiS_iS_i .p2align 8 .type _Z13callOperationPiS_iS_i,@function _Z13callOperationPiS_iS_i: s_clause 0x1 s_load_b32 s2, s[0:1], 0x34 s_load_b32 s3, s[0:1], 0x20 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b32 s2, s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v6, v[2:3], off global_load_b32 v2, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_mad_u64_u32 v[3:4], null, v6, s2, v[2:3] global_store_b32 v[0:1], v3, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13callOperationPiS_iS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13callOperationPiS_iS_i, .Lfunc_end0-_Z13callOperationPiS_iS_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13callOperationPiS_iS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13callOperationPiS_iS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void callOperation(int *a, int *b, int x, int *res, int n) { int tid = blockDim.x * blockIdx.x + threadIdx.x; if (tid < n) { res[tid] = ((a[tid] * x) + b[tid]); } }
.text .file "callOperation.hip" .globl _Z28__device_stub__callOperationPiS_iS_i # -- Begin function _Z28__device_stub__callOperationPiS_iS_i .p2align 4, 0x90 .type _Z28__device_stub__callOperationPiS_iS_i,@function _Z28__device_stub__callOperationPiS_iS_i: # @_Z28__device_stub__callOperationPiS_iS_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 4(%rsp) movq %rcx, 56(%rsp) movl %r8d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) leaq 56(%rsp), %rax movq %rax, 104(%rsp) movq %rsp, %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z13callOperationPiS_iS_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z28__device_stub__callOperationPiS_iS_i, .Lfunc_end0-_Z28__device_stub__callOperationPiS_iS_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13callOperationPiS_iS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z13callOperationPiS_iS_i,@object # @_Z13callOperationPiS_iS_i .section .rodata,"a",@progbits .globl _Z13callOperationPiS_iS_i .p2align 3, 0x0 _Z13callOperationPiS_iS_i: .quad _Z28__device_stub__callOperationPiS_iS_i .size _Z13callOperationPiS_iS_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z13callOperationPiS_iS_i" .size .L__unnamed_1, 26 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__callOperationPiS_iS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13callOperationPiS_iS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z13callOperationPiS_iS_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */ /* 0x000fc800078e0207 */ /*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */ /* 0x0c0fe400078e0207 */ /*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea8000c1e1900 */ /*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */ /* 0x000ea2000c1e1900 */ /*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */ /* 0x000fc800078e0207 */ /*00d0*/ IMAD R9, R2, c[0x0][0x170], R5 ; /* 0x00005c0002097a24 */ /* 0x004fca00078e0205 */ /*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*00f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0100*/ BRA 0x100; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13callOperationPiS_iS_i .globl _Z13callOperationPiS_iS_i .p2align 8 .type _Z13callOperationPiS_iS_i,@function _Z13callOperationPiS_iS_i: s_clause 0x1 s_load_b32 s2, s[0:1], 0x34 s_load_b32 s3, s[0:1], 0x20 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b32 s2, s[0:1], 0x10 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v6, v[2:3], off global_load_b32 v2, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_mad_u64_u32 v[3:4], null, v6, s2, v[2:3] global_store_b32 v[0:1], v3, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13callOperationPiS_iS_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13callOperationPiS_iS_i, .Lfunc_end0-_Z13callOperationPiS_iS_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13callOperationPiS_iS_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13callOperationPiS_iS_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00005d93_00000000-6_callOperation.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z39__device_stub__Z13callOperationPiS_iS_iPiS_iS_i .type _Z39__device_stub__Z13callOperationPiS_iS_iPiS_iS_i, @function _Z39__device_stub__Z13callOperationPiS_iS_iPiS_iS_i: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movq %rcx, (%rsp) movl %r8d, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) leaq 8(%rsp), %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z13callOperationPiS_iS_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z39__device_stub__Z13callOperationPiS_iS_iPiS_iS_i, .-_Z39__device_stub__Z13callOperationPiS_iS_iPiS_iS_i .globl _Z13callOperationPiS_iS_i .type _Z13callOperationPiS_iS_i, @function _Z13callOperationPiS_iS_i: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z39__device_stub__Z13callOperationPiS_iS_iPiS_iS_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z13callOperationPiS_iS_i, .-_Z13callOperationPiS_iS_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z13callOperationPiS_iS_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z13callOperationPiS_iS_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "callOperation.hip" .globl _Z28__device_stub__callOperationPiS_iS_i # -- Begin function _Z28__device_stub__callOperationPiS_iS_i .p2align 4, 0x90 .type _Z28__device_stub__callOperationPiS_iS_i,@function _Z28__device_stub__callOperationPiS_iS_i: # @_Z28__device_stub__callOperationPiS_iS_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 4(%rsp) movq %rcx, 56(%rsp) movl %r8d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) leaq 56(%rsp), %rax movq %rax, 104(%rsp) movq %rsp, %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z13callOperationPiS_iS_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z28__device_stub__callOperationPiS_iS_i, .Lfunc_end0-_Z28__device_stub__callOperationPiS_iS_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13callOperationPiS_iS_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z13callOperationPiS_iS_i,@object # @_Z13callOperationPiS_iS_i .section .rodata,"a",@progbits .globl _Z13callOperationPiS_iS_i .p2align 3, 0x0 _Z13callOperationPiS_iS_i: .quad _Z28__device_stub__callOperationPiS_iS_i .size _Z13callOperationPiS_iS_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z13callOperationPiS_iS_i" .size .L__unnamed_1, 26 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__callOperationPiS_iS_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13callOperationPiS_iS_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <stdio.h> #include <stdlib.h> #include <string.h> /* memcpy */ #include <math.h> #include <stdint.h> void *cuda_upload_var(void *host_var, int size) { void *cuda_var; cudaMalloc(&cuda_var, 4); cudaMemcpy(cuda_var, host_var, size, cudaMemcpyHostToDevice); return cuda_var; } void cuda_download_var(void *cuda_var, void *host_var, int size) { cudaMemcpy(host_var, cuda_var, size, cudaMemcpyDeviceToHost); cudaFree(cuda_var); } typedef struct intmat2x2 { int m[4]; } intmat2x2; intmat2x2 intmat2x2_mul(intmat2x2 lhs, intmat2x2 rhs) { intmat2x2 ret; ret.m[0] = lhs.m[0]*rhs.m[0] + lhs.m[1]*rhs.m[2]; ret.m[2] = lhs.m[2]*rhs.m[0] + lhs.m[3]*rhs.m[2]; ret.m[1] = lhs.m[0]*rhs.m[1] + lhs.m[1]*rhs.m[3]; ret.m[3] = lhs.m[2]*rhs.m[1] + lhs.m[3]*rhs.m[3]; return ret; } typedef struct floatmat3x3 { float m[9]; } floatmat3x3; floatmat3x3 floatmat3x3_mul(floatmat3x3 lhs, floatmat3x3 rhs) { floatmat3x3 ret; ret.m[0] = lhs.m[0]*rhs.m[0] + lhs.m[1]*rhs.m[3] + lhs.m[2]*rhs.m[6]; ret.m[3] = lhs.m[3]*rhs.m[0] + lhs.m[4]*rhs.m[3] + lhs.m[5]*rhs.m[6]; ret.m[6] = lhs.m[6]*rhs.m[0] + lhs.m[7]*rhs.m[3] + lhs.m[8]*rhs.m[6]; ret.m[1] = lhs.m[0]*rhs.m[1] + lhs.m[1]*rhs.m[4] + lhs.m[2]*rhs.m[7]; ret.m[4] = lhs.m[3]*rhs.m[1] + lhs.m[4]*rhs.m[4] + lhs.m[5]*rhs.m[7]; ret.m[7] = lhs.m[6]*rhs.m[1] + lhs.m[7]*rhs.m[4] + lhs.m[8]*rhs.m[7]; ret.m[2] = lhs.m[0]*rhs.m[2] + lhs.m[1]*rhs.m[5] + lhs.m[2]*rhs.m[8]; ret.m[5] = lhs.m[3]*rhs.m[2] + lhs.m[4]*rhs.m[5] + lhs.m[5]*rhs.m[8]; ret.m[8] = lhs.m[6]*rhs.m[2] + lhs.m[7]*rhs.m[5] + lhs.m[8]*rhs.m[8]; return ret; } int main(int argc, char **argv) { intmat2x2 mat1; intmat2x2 mat2; floatmat3x3 mat3; floatmat3x3 mat4; int i; int k; mat1.m[1*0 + 2*0] = 0; mat1.m[1*1 + 2*0] = 1; mat1.m[1*1 + 2*1] = 2; mat1.m[1*0 + 2*1] = 3; mat2.m[1*0 + 2*0] = 0; mat2.m[1*1 + 2*0] = 1; mat2.m[1*1 + 2*1] = 2; mat2.m[1*0 + 2*1] = 3; for (i = 0; i < 3; i = i + 1) { for (k = 0; k < 3; k = k + 1) { mat3.m[1*i + 3*k] = 1; mat4.m[1*i + 3*k] = 2; } } mat1 = intmat2x2_mul(mat1, mat2); mat3 = floatmat3x3_mul(floatmat3x3_mul(floatmat3x3_mul(mat4, mat3), mat3), mat3); return 0; }
code for sm_80
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include <stdlib.h> #include <string.h> /* memcpy */ #include <math.h> #include <stdint.h> void *cuda_upload_var(void *host_var, int size) { void *cuda_var; cudaMalloc(&cuda_var, 4); cudaMemcpy(cuda_var, host_var, size, cudaMemcpyHostToDevice); return cuda_var; } void cuda_download_var(void *cuda_var, void *host_var, int size) { cudaMemcpy(host_var, cuda_var, size, cudaMemcpyDeviceToHost); cudaFree(cuda_var); } typedef struct intmat2x2 { int m[4]; } intmat2x2; intmat2x2 intmat2x2_mul(intmat2x2 lhs, intmat2x2 rhs) { intmat2x2 ret; ret.m[0] = lhs.m[0]*rhs.m[0] + lhs.m[1]*rhs.m[2]; ret.m[2] = lhs.m[2]*rhs.m[0] + lhs.m[3]*rhs.m[2]; ret.m[1] = lhs.m[0]*rhs.m[1] + lhs.m[1]*rhs.m[3]; ret.m[3] = lhs.m[2]*rhs.m[1] + lhs.m[3]*rhs.m[3]; return ret; } typedef struct floatmat3x3 { float m[9]; } floatmat3x3; floatmat3x3 floatmat3x3_mul(floatmat3x3 lhs, floatmat3x3 rhs) { floatmat3x3 ret; ret.m[0] = lhs.m[0]*rhs.m[0] + lhs.m[1]*rhs.m[3] + lhs.m[2]*rhs.m[6]; ret.m[3] = lhs.m[3]*rhs.m[0] + lhs.m[4]*rhs.m[3] + lhs.m[5]*rhs.m[6]; ret.m[6] = lhs.m[6]*rhs.m[0] + lhs.m[7]*rhs.m[3] + lhs.m[8]*rhs.m[6]; ret.m[1] = lhs.m[0]*rhs.m[1] + lhs.m[1]*rhs.m[4] + lhs.m[2]*rhs.m[7]; ret.m[4] = lhs.m[3]*rhs.m[1] + lhs.m[4]*rhs.m[4] + lhs.m[5]*rhs.m[7]; ret.m[7] = lhs.m[6]*rhs.m[1] + lhs.m[7]*rhs.m[4] + lhs.m[8]*rhs.m[7]; ret.m[2] = lhs.m[0]*rhs.m[2] + lhs.m[1]*rhs.m[5] + lhs.m[2]*rhs.m[8]; ret.m[5] = lhs.m[3]*rhs.m[2] + lhs.m[4]*rhs.m[5] + lhs.m[5]*rhs.m[8]; ret.m[8] = lhs.m[6]*rhs.m[2] + lhs.m[7]*rhs.m[5] + lhs.m[8]*rhs.m[8]; return ret; } int main(int argc, char **argv) { intmat2x2 mat1; intmat2x2 mat2; floatmat3x3 mat3; floatmat3x3 mat4; int i; int k; mat1.m[1*0 + 2*0] = 0; mat1.m[1*1 + 2*0] = 1; mat1.m[1*1 + 2*1] = 2; mat1.m[1*0 + 2*1] = 3; mat2.m[1*0 + 2*0] = 0; mat2.m[1*1 + 2*0] = 1; mat2.m[1*1 + 2*1] = 2; mat2.m[1*0 + 2*1] = 3; for (i = 0; i < 3; i = i + 1) { for (k = 0; k < 3; k = k + 1) { mat3.m[1*i + 3*k] = 1; mat4.m[1*i + 3*k] = 2; } } mat1 = intmat2x2_mul(mat1, mat2); mat3 = floatmat3x3_mul(floatmat3x3_mul(floatmat3x3_mul(mat4, mat3), mat3), mat3); return 0; }
.file "tmpxft_0005e43f_00000000-6_builtin_types.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2064: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2064: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z15cuda_upload_varPvi .type _Z15cuda_upload_varPvi, @function _Z15cuda_upload_varPvi: .LFB2057: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $24, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbp movl %esi, %ebx movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax movq %rsp, %rdi movl $4, %esi call cudaMalloc@PLT movslq %ebx, %rdx movl $1, %ecx movq %rbp, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movq (%rsp), %rax movq 8(%rsp), %rdx subq %fs:40, %rdx jne .L6 addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L6: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z15cuda_upload_varPvi, .-_Z15cuda_upload_varPvi .globl _Z17cuda_download_varPvS_i .type _Z17cuda_download_varPvS_i, @function _Z17cuda_download_varPvS_i: .LFB2058: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx movq %rsi, %rdi movslq %edx, %rdx movl $2, %ecx movq %rbx, %rsi call cudaMemcpy@PLT movq %rbx, %rdi call cudaFree@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z17cuda_download_varPvS_i, .-_Z17cuda_download_varPvS_i .globl _Z13intmat2x2_mul9intmat2x2S_ .type _Z13intmat2x2_mul9intmat2x2S_, @function _Z13intmat2x2_mul9intmat2x2S_: .LFB2059: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rax movq %rsi, %rdi movq %rdx, %rsi movq %rcx, %rdx movq %rax, %r9 sarq $32, %r9 movq %rdi, %r10 sarq $32, %r10 movq %rsi, %r8 sarq $32, %r8 sarq $32, %rcx movl %esi, %ebx imull %eax, %ebx movl %edx, %r11d imull %r9d, %r11d imull %r8d, %eax imull %ecx, %r9d leal (%rax,%r9), %r9d salq $32, %r9 leal (%rbx,%r11), %eax orq %r9, %rax imull %edi, %esi imull %r10d, %edx imull %edi, %r8d imull %r10d, %ecx leal (%r8,%rcx), %ecx salq $32, %rcx leal (%rsi,%rdx), %edx orq %rcx, %rdx popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2059: .size _Z13intmat2x2_mul9intmat2x2S_, .-_Z13intmat2x2_mul9intmat2x2S_ .globl _Z15floatmat3x3_mul11floatmat3x3S_ .type _Z15floatmat3x3_mul11floatmat3x3S_, @function _Z15floatmat3x3_mul11floatmat3x3S_: .LFB2060: .cfi_startproc endbr64 movq %rdi, %rax movss 8(%rsp), %xmm2 movss 12(%rsp), %xmm8 movss 16(%rsp), %xmm7 movss 20(%rsp), %xmm1 movss 24(%rsp), %xmm6 movss 28(%rsp), %xmm5 movss 32(%rsp), %xmm0 movss 48(%rsp), %xmm12 movss 52(%rsp), %xmm3 movss 60(%rsp), %xmm4 movss 64(%rsp), %xmm10 movss 72(%rsp), %xmm11 movss 76(%rsp), %xmm9 movss 80(%rsp), %xmm14 movaps %xmm2, %xmm15 mulss %xmm12, %xmm15 movaps %xmm8, %xmm13 mulss %xmm4, %xmm13 addss %xmm15, %xmm13 movaps %xmm7, %xmm15 mulss %xmm11, %xmm15 addss %xmm15, %xmm13 movss %xmm13, (%rdi) movaps %xmm1, %xmm15 mulss %xmm12, %xmm15 movaps %xmm6, %xmm13 mulss %xmm4, %xmm13 addss %xmm15, %xmm13 movaps %xmm5, %xmm15 mulss %xmm11, %xmm15 addss %xmm15, %xmm13 movss %xmm13, 12(%rdi) mulss %xmm0, %xmm12 mulss 36(%rsp), %xmm4 addss %xmm12, %xmm4 mulss 40(%rsp), %xmm11 addss %xmm11, %xmm4 movss %xmm4, 24(%rdi) movaps %xmm2, %xmm11 mulss %xmm3, %xmm11 movaps %xmm8, %xmm4 mulss %xmm10, %xmm4 addss %xmm11, %xmm4 movaps %xmm7, %xmm11 mulss %xmm9, %xmm11 addss %xmm11, %xmm4 movss %xmm4, 4(%rdi) movaps %xmm1, %xmm11 mulss %xmm3, %xmm11 movaps %xmm6, %xmm4 mulss %xmm10, %xmm4 addss %xmm11, %xmm4 movaps %xmm5, %xmm11 mulss %xmm9, %xmm11 addss %xmm11, %xmm4 movss %xmm4, 16(%rdi) mulss %xmm0, %xmm3 mulss 36(%rsp), %xmm10 addss %xmm10, %xmm3 mulss 40(%rsp), %xmm9 addss %xmm9, %xmm3 movss %xmm3, 28(%rdi) mulss 56(%rsp), %xmm2 mulss 68(%rsp), %xmm8 addss %xmm8, %xmm2 mulss %xmm14, %xmm7 addss %xmm7, %xmm2 movss %xmm2, 8(%rdi) mulss 56(%rsp), %xmm1 mulss 68(%rsp), %xmm6 addss %xmm6, %xmm1 mulss %xmm14, %xmm5 addss %xmm5, %xmm1 movss %xmm1, 20(%rdi) mulss 56(%rsp), %xmm0 movss 36(%rsp), %xmm1 mulss 68(%rsp), %xmm1 addss %xmm1, %xmm0 movaps %xmm14, %xmm1 mulss 40(%rsp), %xmm1 addss %xmm1, %xmm0 movss %xmm0, 32(%rdi) ret .cfi_endproc .LFE2060: .size _Z15floatmat3x3_mul11floatmat3x3S_, .-_Z15floatmat3x3_mul11floatmat3x3S_ .globl main .type main, @function main: .LFB2061: .cfi_startproc endbr64 movl $0, %eax ret .cfi_endproc .LFE2061: .size main, .-main .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #include <stdlib.h> #include <string.h> /* memcpy */ #include <math.h> #include <stdint.h> void *cuda_upload_var(void *host_var, int size) { void *cuda_var; cudaMalloc(&cuda_var, 4); cudaMemcpy(cuda_var, host_var, size, cudaMemcpyHostToDevice); return cuda_var; } void cuda_download_var(void *cuda_var, void *host_var, int size) { cudaMemcpy(host_var, cuda_var, size, cudaMemcpyDeviceToHost); cudaFree(cuda_var); } typedef struct intmat2x2 { int m[4]; } intmat2x2; intmat2x2 intmat2x2_mul(intmat2x2 lhs, intmat2x2 rhs) { intmat2x2 ret; ret.m[0] = lhs.m[0]*rhs.m[0] + lhs.m[1]*rhs.m[2]; ret.m[2] = lhs.m[2]*rhs.m[0] + lhs.m[3]*rhs.m[2]; ret.m[1] = lhs.m[0]*rhs.m[1] + lhs.m[1]*rhs.m[3]; ret.m[3] = lhs.m[2]*rhs.m[1] + lhs.m[3]*rhs.m[3]; return ret; } typedef struct floatmat3x3 { float m[9]; } floatmat3x3; floatmat3x3 floatmat3x3_mul(floatmat3x3 lhs, floatmat3x3 rhs) { floatmat3x3 ret; ret.m[0] = lhs.m[0]*rhs.m[0] + lhs.m[1]*rhs.m[3] + lhs.m[2]*rhs.m[6]; ret.m[3] = lhs.m[3]*rhs.m[0] + lhs.m[4]*rhs.m[3] + lhs.m[5]*rhs.m[6]; ret.m[6] = lhs.m[6]*rhs.m[0] + lhs.m[7]*rhs.m[3] + lhs.m[8]*rhs.m[6]; ret.m[1] = lhs.m[0]*rhs.m[1] + lhs.m[1]*rhs.m[4] + lhs.m[2]*rhs.m[7]; ret.m[4] = lhs.m[3]*rhs.m[1] + lhs.m[4]*rhs.m[4] + lhs.m[5]*rhs.m[7]; ret.m[7] = lhs.m[6]*rhs.m[1] + lhs.m[7]*rhs.m[4] + lhs.m[8]*rhs.m[7]; ret.m[2] = lhs.m[0]*rhs.m[2] + lhs.m[1]*rhs.m[5] + lhs.m[2]*rhs.m[8]; ret.m[5] = lhs.m[3]*rhs.m[2] + lhs.m[4]*rhs.m[5] + lhs.m[5]*rhs.m[8]; ret.m[8] = lhs.m[6]*rhs.m[2] + lhs.m[7]*rhs.m[5] + lhs.m[8]*rhs.m[8]; return ret; } int main(int argc, char **argv) { intmat2x2 mat1; intmat2x2 mat2; floatmat3x3 mat3; floatmat3x3 mat4; int i; int k; mat1.m[1*0 + 2*0] = 0; mat1.m[1*1 + 2*0] = 1; mat1.m[1*1 + 2*1] = 2; mat1.m[1*0 + 2*1] = 3; mat2.m[1*0 + 2*0] = 0; mat2.m[1*1 + 2*0] = 1; mat2.m[1*1 + 2*1] = 2; mat2.m[1*0 + 2*1] = 3; for (i = 0; i < 3; i = i + 1) { for (k = 0; k < 3; k = k + 1) { mat3.m[1*i + 3*k] = 1; mat4.m[1*i + 3*k] = 2; } } mat1 = intmat2x2_mul(mat1, mat2); mat3 = floatmat3x3_mul(floatmat3x3_mul(floatmat3x3_mul(mat4, mat3), mat3), mat3); return 0; }
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <string.h> /* memcpy */ #include <math.h> #include <stdint.h> void *cuda_upload_var(void *host_var, int size) { void *cuda_var; hipMalloc(&cuda_var, 4); hipMemcpy(cuda_var, host_var, size, hipMemcpyHostToDevice); return cuda_var; } void cuda_download_var(void *cuda_var, void *host_var, int size) { hipMemcpy(host_var, cuda_var, size, hipMemcpyDeviceToHost); hipFree(cuda_var); } typedef struct intmat2x2 { int m[4]; } intmat2x2; intmat2x2 intmat2x2_mul(intmat2x2 lhs, intmat2x2 rhs) { intmat2x2 ret; ret.m[0] = lhs.m[0]*rhs.m[0] + lhs.m[1]*rhs.m[2]; ret.m[2] = lhs.m[2]*rhs.m[0] + lhs.m[3]*rhs.m[2]; ret.m[1] = lhs.m[0]*rhs.m[1] + lhs.m[1]*rhs.m[3]; ret.m[3] = lhs.m[2]*rhs.m[1] + lhs.m[3]*rhs.m[3]; return ret; } typedef struct floatmat3x3 { float m[9]; } floatmat3x3; floatmat3x3 floatmat3x3_mul(floatmat3x3 lhs, floatmat3x3 rhs) { floatmat3x3 ret; ret.m[0] = lhs.m[0]*rhs.m[0] + lhs.m[1]*rhs.m[3] + lhs.m[2]*rhs.m[6]; ret.m[3] = lhs.m[3]*rhs.m[0] + lhs.m[4]*rhs.m[3] + lhs.m[5]*rhs.m[6]; ret.m[6] = lhs.m[6]*rhs.m[0] + lhs.m[7]*rhs.m[3] + lhs.m[8]*rhs.m[6]; ret.m[1] = lhs.m[0]*rhs.m[1] + lhs.m[1]*rhs.m[4] + lhs.m[2]*rhs.m[7]; ret.m[4] = lhs.m[3]*rhs.m[1] + lhs.m[4]*rhs.m[4] + lhs.m[5]*rhs.m[7]; ret.m[7] = lhs.m[6]*rhs.m[1] + lhs.m[7]*rhs.m[4] + lhs.m[8]*rhs.m[7]; ret.m[2] = lhs.m[0]*rhs.m[2] + lhs.m[1]*rhs.m[5] + lhs.m[2]*rhs.m[8]; ret.m[5] = lhs.m[3]*rhs.m[2] + lhs.m[4]*rhs.m[5] + lhs.m[5]*rhs.m[8]; ret.m[8] = lhs.m[6]*rhs.m[2] + lhs.m[7]*rhs.m[5] + lhs.m[8]*rhs.m[8]; return ret; } int main(int argc, char **argv) { intmat2x2 mat1; intmat2x2 mat2; floatmat3x3 mat3; floatmat3x3 mat4; int i; int k; mat1.m[1*0 + 2*0] = 0; mat1.m[1*1 + 2*0] = 1; mat1.m[1*1 + 2*1] = 2; mat1.m[1*0 + 2*1] = 3; mat2.m[1*0 + 2*0] = 0; mat2.m[1*1 + 2*0] = 1; mat2.m[1*1 + 2*1] = 2; mat2.m[1*0 + 2*1] = 3; for (i = 0; i < 3; i = i + 1) { for (k = 0; k < 3; k = k + 1) { mat3.m[1*i + 3*k] = 1; mat4.m[1*i + 3*k] = 2; } } mat1 = intmat2x2_mul(mat1, mat2); mat3 = floatmat3x3_mul(floatmat3x3_mul(floatmat3x3_mul(mat4, mat3), mat3), mat3); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <string.h> /* memcpy */ #include <math.h> #include <stdint.h> void *cuda_upload_var(void *host_var, int size) { void *cuda_var; hipMalloc(&cuda_var, 4); hipMemcpy(cuda_var, host_var, size, hipMemcpyHostToDevice); return cuda_var; } void cuda_download_var(void *cuda_var, void *host_var, int size) { hipMemcpy(host_var, cuda_var, size, hipMemcpyDeviceToHost); hipFree(cuda_var); } typedef struct intmat2x2 { int m[4]; } intmat2x2; intmat2x2 intmat2x2_mul(intmat2x2 lhs, intmat2x2 rhs) { intmat2x2 ret; ret.m[0] = lhs.m[0]*rhs.m[0] + lhs.m[1]*rhs.m[2]; ret.m[2] = lhs.m[2]*rhs.m[0] + lhs.m[3]*rhs.m[2]; ret.m[1] = lhs.m[0]*rhs.m[1] + lhs.m[1]*rhs.m[3]; ret.m[3] = lhs.m[2]*rhs.m[1] + lhs.m[3]*rhs.m[3]; return ret; } typedef struct floatmat3x3 { float m[9]; } floatmat3x3; floatmat3x3 floatmat3x3_mul(floatmat3x3 lhs, floatmat3x3 rhs) { floatmat3x3 ret; ret.m[0] = lhs.m[0]*rhs.m[0] + lhs.m[1]*rhs.m[3] + lhs.m[2]*rhs.m[6]; ret.m[3] = lhs.m[3]*rhs.m[0] + lhs.m[4]*rhs.m[3] + lhs.m[5]*rhs.m[6]; ret.m[6] = lhs.m[6]*rhs.m[0] + lhs.m[7]*rhs.m[3] + lhs.m[8]*rhs.m[6]; ret.m[1] = lhs.m[0]*rhs.m[1] + lhs.m[1]*rhs.m[4] + lhs.m[2]*rhs.m[7]; ret.m[4] = lhs.m[3]*rhs.m[1] + lhs.m[4]*rhs.m[4] + lhs.m[5]*rhs.m[7]; ret.m[7] = lhs.m[6]*rhs.m[1] + lhs.m[7]*rhs.m[4] + lhs.m[8]*rhs.m[7]; ret.m[2] = lhs.m[0]*rhs.m[2] + lhs.m[1]*rhs.m[5] + lhs.m[2]*rhs.m[8]; ret.m[5] = lhs.m[3]*rhs.m[2] + lhs.m[4]*rhs.m[5] + lhs.m[5]*rhs.m[8]; ret.m[8] = lhs.m[6]*rhs.m[2] + lhs.m[7]*rhs.m[5] + lhs.m[8]*rhs.m[8]; return ret; } int main(int argc, char **argv) { intmat2x2 mat1; intmat2x2 mat2; floatmat3x3 mat3; floatmat3x3 mat4; int i; int k; mat1.m[1*0 + 2*0] = 0; mat1.m[1*1 + 2*0] = 1; mat1.m[1*1 + 2*1] = 2; mat1.m[1*0 + 2*1] = 3; mat2.m[1*0 + 2*0] = 0; mat2.m[1*1 + 2*0] = 1; mat2.m[1*1 + 2*1] = 2; mat2.m[1*0 + 2*1] = 3; for (i = 0; i < 3; i = i + 1) { for (k = 0; k < 3; k = k + 1) { mat3.m[1*i + 3*k] = 1; mat4.m[1*i + 3*k] = 2; } } mat1 = intmat2x2_mul(mat1, mat2); mat3 = floatmat3x3_mul(floatmat3x3_mul(floatmat3x3_mul(mat4, mat3), mat3), mat3); return 0; }
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <string.h> /* memcpy */ #include <math.h> #include <stdint.h> void *cuda_upload_var(void *host_var, int size) { void *cuda_var; hipMalloc(&cuda_var, 4); hipMemcpy(cuda_var, host_var, size, hipMemcpyHostToDevice); return cuda_var; } void cuda_download_var(void *cuda_var, void *host_var, int size) { hipMemcpy(host_var, cuda_var, size, hipMemcpyDeviceToHost); hipFree(cuda_var); } typedef struct intmat2x2 { int m[4]; } intmat2x2; intmat2x2 intmat2x2_mul(intmat2x2 lhs, intmat2x2 rhs) { intmat2x2 ret; ret.m[0] = lhs.m[0]*rhs.m[0] + lhs.m[1]*rhs.m[2]; ret.m[2] = lhs.m[2]*rhs.m[0] + lhs.m[3]*rhs.m[2]; ret.m[1] = lhs.m[0]*rhs.m[1] + lhs.m[1]*rhs.m[3]; ret.m[3] = lhs.m[2]*rhs.m[1] + lhs.m[3]*rhs.m[3]; return ret; } typedef struct floatmat3x3 { float m[9]; } floatmat3x3; floatmat3x3 floatmat3x3_mul(floatmat3x3 lhs, floatmat3x3 rhs) { floatmat3x3 ret; ret.m[0] = lhs.m[0]*rhs.m[0] + lhs.m[1]*rhs.m[3] + lhs.m[2]*rhs.m[6]; ret.m[3] = lhs.m[3]*rhs.m[0] + lhs.m[4]*rhs.m[3] + lhs.m[5]*rhs.m[6]; ret.m[6] = lhs.m[6]*rhs.m[0] + lhs.m[7]*rhs.m[3] + lhs.m[8]*rhs.m[6]; ret.m[1] = lhs.m[0]*rhs.m[1] + lhs.m[1]*rhs.m[4] + lhs.m[2]*rhs.m[7]; ret.m[4] = lhs.m[3]*rhs.m[1] + lhs.m[4]*rhs.m[4] + lhs.m[5]*rhs.m[7]; ret.m[7] = lhs.m[6]*rhs.m[1] + lhs.m[7]*rhs.m[4] + lhs.m[8]*rhs.m[7]; ret.m[2] = lhs.m[0]*rhs.m[2] + lhs.m[1]*rhs.m[5] + lhs.m[2]*rhs.m[8]; ret.m[5] = lhs.m[3]*rhs.m[2] + lhs.m[4]*rhs.m[5] + lhs.m[5]*rhs.m[8]; ret.m[8] = lhs.m[6]*rhs.m[2] + lhs.m[7]*rhs.m[5] + lhs.m[8]*rhs.m[8]; return ret; } int main(int argc, char **argv) { intmat2x2 mat1; intmat2x2 mat2; floatmat3x3 mat3; floatmat3x3 mat4; int i; int k; mat1.m[1*0 + 2*0] = 0; mat1.m[1*1 + 2*0] = 1; mat1.m[1*1 + 2*1] = 2; mat1.m[1*0 + 2*1] = 3; mat2.m[1*0 + 2*0] = 0; mat2.m[1*1 + 2*0] = 1; mat2.m[1*1 + 2*1] = 2; mat2.m[1*0 + 2*1] = 3; for (i = 0; i < 3; i = i + 1) { for (k = 0; k < 3; k = k + 1) { mat3.m[1*i + 3*k] = 1; mat4.m[1*i + 3*k] = 2; } } mat1 = intmat2x2_mul(mat1, mat2); mat3 = floatmat3x3_mul(floatmat3x3_mul(floatmat3x3_mul(mat4, mat3), mat3), mat3); return 0; }
.text .file "builtin_types.hip" .globl _Z15cuda_upload_varPvi # -- Begin function _Z15cuda_upload_varPvi .p2align 4, 0x90 .type _Z15cuda_upload_varPvi,@function _Z15cuda_upload_varPvi: # @_Z15cuda_upload_varPvi .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl %esi, %ebx movq %rdi, %r14 movq %rsp, %rdi movl $4, %esi callq hipMalloc movq (%rsp), %rdi movslq %ebx, %rdx movq %r14, %rsi movl $1, %ecx callq hipMemcpy movq (%rsp), %rax addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z15cuda_upload_varPvi, .Lfunc_end0-_Z15cuda_upload_varPvi .cfi_endproc # -- End function .globl _Z17cuda_download_varPvS_i # -- Begin function _Z17cuda_download_varPvS_i .p2align 4, 0x90 .type _Z17cuda_download_varPvS_i,@function _Z17cuda_download_varPvS_i: # @_Z17cuda_download_varPvS_i .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq %rdi, %rbx movslq %edx, %rdx movq %rsi, %rdi movq %rbx, %rsi movl $2, %ecx callq hipMemcpy movq %rbx, %rdi popq %rbx .cfi_def_cfa_offset 8 jmp hipFree # TAILCALL .Lfunc_end1: .size _Z17cuda_download_varPvS_i, .Lfunc_end1-_Z17cuda_download_varPvS_i .cfi_endproc # -- End function .globl _Z13intmat2x2_mul9intmat2x2S_ # -- Begin function _Z13intmat2x2_mul9intmat2x2S_ .p2align 4, 0x90 .type _Z13intmat2x2_mul9intmat2x2S_,@function _Z13intmat2x2_mul9intmat2x2S_: # @_Z13intmat2x2_mul9intmat2x2S_ .cfi_startproc # %bb.0: movq %rdi, %r8 shrq $32, %r8 movq %rdx, %r9 shrq $32, %r9 movl %edx, %r10d imull %edi, %r10d imull %esi, %edx imull %r9d, %edi imull %esi, %r9d shrq $32, %rsi movq %rcx, %r11 shrq $32, %r11 movl %r8d, %eax imull %ecx, %eax addl %r10d, %eax imull %esi, %ecx addl %ecx, %edx imull %r11d, %r8d addl %edi, %r8d imull %esi, %r11d addl %r9d, %r11d shlq $32, %r8 orq %r8, %rax shlq $32, %r11 orq %r11, %rdx retq .Lfunc_end2: .size _Z13intmat2x2_mul9intmat2x2S_, .Lfunc_end2-_Z13intmat2x2_mul9intmat2x2S_ .cfi_endproc # -- End function .globl _Z15floatmat3x3_mul11floatmat3x3S_ # -- Begin function _Z15floatmat3x3_mul11floatmat3x3S_ .p2align 4, 0x90 .type _Z15floatmat3x3_mul11floatmat3x3S_,@function _Z15floatmat3x3_mul11floatmat3x3S_: # @_Z15floatmat3x3_mul11floatmat3x3S_ .cfi_startproc # %bb.0: movq %rdi, %rax movss 8(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero movss 48(%rsp), %xmm8 # xmm8 = mem[0],zero,zero,zero movss 60(%rsp), %xmm9 # xmm9 = mem[0],zero,zero,zero movaps %xmm1, %xmm2 mulss %xmm8, %xmm2 movaps %xmm0, %xmm4 mulss %xmm9, %xmm4 addss %xmm2, %xmm4 movss 16(%rsp), %xmm3 # xmm3 = mem[0],zero,zero,zero movss 72(%rsp), %xmm10 # xmm10 = mem[0],zero,zero,zero movaps %xmm3, %xmm2 mulss %xmm10, %xmm2 addss %xmm4, %xmm2 movss %xmm2, (%rdi) movss 20(%rsp), %xmm4 # xmm4 = mem[0],zero,zero,zero movss 24(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero movaps %xmm8, %xmm5 mulss %xmm4, %xmm5 movaps %xmm9, %xmm7 mulss %xmm2, %xmm7 addss %xmm5, %xmm7 movss 28(%rsp), %xmm6 # xmm6 = mem[0],zero,zero,zero movaps %xmm10, %xmm5 mulss %xmm6, %xmm5 addss %xmm7, %xmm5 movss %xmm5, 12(%rdi) movss 32(%rsp), %xmm7 # xmm7 = mem[0],zero,zero,zero movss 36(%rsp), %xmm5 # xmm5 = mem[0],zero,zero,zero mulss %xmm7, %xmm8 mulss %xmm5, %xmm9 addss %xmm8, %xmm9 movss 40(%rsp), %xmm8 # xmm8 = mem[0],zero,zero,zero mulss %xmm8, %xmm10 addss %xmm9, %xmm10 movss %xmm10, 24(%rdi) movss 52(%rsp), %xmm10 # xmm10 = mem[0],zero,zero,zero movss 64(%rsp), %xmm9 # xmm9 = mem[0],zero,zero,zero movaps %xmm1, %xmm11 mulss %xmm10, %xmm11 movaps %xmm0, %xmm12 mulss %xmm9, %xmm12 addss %xmm11, %xmm12 movss 76(%rsp), %xmm11 # xmm11 = mem[0],zero,zero,zero movaps %xmm3, %xmm13 mulss %xmm11, %xmm13 addss %xmm12, %xmm13 movss %xmm13, 4(%rdi) movaps %xmm4, %xmm12 mulss %xmm10, %xmm12 movaps %xmm2, %xmm13 mulss %xmm9, %xmm13 addss %xmm12, %xmm13 movaps %xmm6, %xmm12 mulss %xmm11, %xmm12 addss %xmm13, %xmm12 movss %xmm12, 16(%rdi) mulss %xmm7, %xmm10 mulss %xmm5, %xmm9 addss %xmm10, %xmm9 mulss %xmm8, %xmm11 addss %xmm9, %xmm11 movss %xmm11, 28(%rdi) movss 56(%rsp), %xmm9 # xmm9 = mem[0],zero,zero,zero movss 68(%rsp), %xmm10 # xmm10 = mem[0],zero,zero,zero mulss %xmm9, %xmm1 mulss %xmm10, %xmm0 addss %xmm1, %xmm0 movss 80(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero mulss %xmm1, %xmm3 addss %xmm0, %xmm3 movss %xmm3, 8(%rdi) mulss %xmm9, %xmm4 mulss %xmm10, %xmm2 addss %xmm4, %xmm2 mulss %xmm1, %xmm6 addss %xmm2, %xmm6 movss %xmm6, 20(%rdi) mulss %xmm9, %xmm7 mulss %xmm10, %xmm5 addss %xmm7, %xmm5 mulss %xmm1, %xmm8 addss %xmm5, %xmm8 movss %xmm8, 32(%rdi) retq .Lfunc_end3: .size _Z15floatmat3x3_mul11floatmat3x3S_, .Lfunc_end3-_Z15floatmat3x3_mul11floatmat3x3S_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: leaq -36(%rsp), %rax leaq -72(%rsp), %rcx xorl %edx, %edx .p2align 4, 0x90 .LBB4_1: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB4_2 Depth 2 xorl %esi, %esi .p2align 4, 0x90 .LBB4_2: # Parent Loop BB4_1 Depth=1 # => This Inner Loop Header: Depth=2 movl $1065353216, (%rcx,%rsi) # imm = 0x3F800000 movl $1073741824, (%rax,%rsi) # imm = 0x40000000 addq $12, %rsi cmpq $36, %rsi jne .LBB4_2 # %bb.3: # in Loop: Header=BB4_1 Depth=1 incq %rdx addq $4, %rax addq $4, %rcx cmpq $3, %rdx jne .LBB4_1 # %bb.4: movss -36(%rsp), %xmm11 # xmm11 = mem[0],zero,zero,zero movss -32(%rsp), %xmm15 # xmm15 = mem[0],zero,zero,zero movss -28(%rsp), %xmm10 # xmm10 = mem[0],zero,zero,zero movss %xmm10, -128(%rsp) # 4-byte Spill movss -24(%rsp), %xmm7 # xmm7 = mem[0],zero,zero,zero movss -20(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero movss -16(%rsp), %xmm4 # xmm4 = mem[0],zero,zero,zero movss %xmm4, -124(%rsp) # 4-byte Spill movss -12(%rsp), %xmm12 # xmm12 = mem[0],zero,zero,zero movss -8(%rsp), %xmm3 # xmm3 = mem[0],zero,zero,zero movss -4(%rsp), %xmm13 # xmm13 = mem[0],zero,zero,zero movss %xmm13, -112(%rsp) # 4-byte Spill movss -72(%rsp), %xmm8 # xmm8 = mem[0],zero,zero,zero movss %xmm8, -84(%rsp) # 4-byte Spill movss -60(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, -88(%rsp) # 4-byte Spill movss -48(%rsp), %xmm5 # xmm5 = mem[0],zero,zero,zero movss %xmm5, -120(%rsp) # 4-byte Spill movaps %xmm11, %xmm2 mulss %xmm8, %xmm2 movaps %xmm15, %xmm6 mulss %xmm0, %xmm6 addss %xmm2, %xmm6 mulss %xmm5, %xmm10 addss %xmm6, %xmm10 movaps %xmm7, %xmm2 movss %xmm7, -116(%rsp) # 4-byte Spill mulss %xmm8, %xmm2 movaps %xmm1, %xmm6 mulss %xmm0, %xmm6 addss %xmm2, %xmm6 movaps %xmm4, %xmm9 mulss %xmm5, %xmm9 addss %xmm6, %xmm9 movaps %xmm12, %xmm2 movaps %xmm12, %xmm4 movss %xmm12, -80(%rsp) # 4-byte Spill mulss %xmm8, %xmm2 movaps %xmm3, %xmm12 mulss %xmm0, %xmm12 addss %xmm2, %xmm12 movaps %xmm13, %xmm6 mulss %xmm5, %xmm6 addss %xmm12, %xmm6 movss -68(%rsp), %xmm5 # xmm5 = mem[0],zero,zero,zero movaps %xmm11, %xmm2 mulss %xmm5, %xmm2 movss -56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero movaps %xmm15, %xmm13 mulss %xmm0, %xmm13 movss %xmm0, -92(%rsp) # 4-byte Spill addss %xmm2, %xmm13 movss -44(%rsp), %xmm14 # xmm14 = mem[0],zero,zero,zero movss -128(%rsp), %xmm12 # 4-byte Reload # xmm12 = mem[0],zero,zero,zero mulss %xmm14, %xmm12 addss %xmm13, %xmm12 movaps %xmm7, %xmm2 movaps %xmm5, %xmm7 movss %xmm5, -108(%rsp) # 4-byte Spill mulss %xmm5, %xmm2 movaps %xmm1, %xmm5 mulss %xmm0, %xmm5 addss %xmm2, %xmm5 movss -124(%rsp), %xmm8 # 4-byte Reload # xmm8 = mem[0],zero,zero,zero mulss %xmm14, %xmm8 movss %xmm14, -96(%rsp) # 4-byte Spill addss %xmm5, %xmm8 movaps %xmm4, %xmm2 mulss %xmm7, %xmm2 movaps %xmm3, %xmm5 mulss %xmm0, %xmm5 addss %xmm2, %xmm5 movss -112(%rsp), %xmm13 # 4-byte Reload # xmm13 = mem[0],zero,zero,zero movaps %xmm13, %xmm7 mulss %xmm14, %xmm7 addss %xmm5, %xmm7 movss -64(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero mulss %xmm2, %xmm11 movaps %xmm2, %xmm0 movss -52(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero mulss %xmm2, %xmm15 movaps %xmm2, %xmm5 movss %xmm2, -104(%rsp) # 4-byte Spill addss %xmm11, %xmm15 movss -40(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero movss %xmm2, -100(%rsp) # 4-byte Spill movss -128(%rsp), %xmm4 # 4-byte Reload # xmm4 = mem[0],zero,zero,zero mulss %xmm2, %xmm4 addss %xmm15, %xmm4 movss -116(%rsp), %xmm11 # 4-byte Reload # xmm11 = mem[0],zero,zero,zero mulss %xmm0, %xmm11 movaps %xmm0, %xmm14 movss %xmm0, -76(%rsp) # 4-byte Spill mulss %xmm5, %xmm1 addss %xmm11, %xmm1 movss -124(%rsp), %xmm15 # 4-byte Reload # xmm15 = mem[0],zero,zero,zero mulss %xmm2, %xmm15 addss %xmm1, %xmm15 movss -80(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero mulss %xmm14, %xmm0 mulss %xmm5, %xmm3 addss %xmm0, %xmm3 mulss %xmm2, %xmm13 addss %xmm3, %xmm13 movss %xmm13, -112(%rsp) # 4-byte Spill movss -84(%rsp), %xmm5 # 4-byte Reload # xmm5 = mem[0],zero,zero,zero movaps %xmm5, %xmm0 mulss %xmm10, %xmm0 movss -88(%rsp), %xmm3 # 4-byte Reload # xmm3 = mem[0],zero,zero,zero movaps %xmm3, %xmm1 mulss %xmm12, %xmm1 addss %xmm0, %xmm1 movss -120(%rsp), %xmm2 # 4-byte Reload # xmm2 = mem[0],zero,zero,zero movaps %xmm2, %xmm0 mulss %xmm4, %xmm0 movss %xmm4, -128(%rsp) # 4-byte Spill addss %xmm1, %xmm0 movss %xmm0, -124(%rsp) # 4-byte Spill movaps %xmm5, %xmm0 mulss %xmm9, %xmm0 movaps %xmm3, %xmm1 mulss %xmm8, %xmm1 addss %xmm0, %xmm1 movaps %xmm2, %xmm0 mulss %xmm15, %xmm0 addss %xmm1, %xmm0 movss %xmm0, -116(%rsp) # 4-byte Spill movaps %xmm5, %xmm0 mulss %xmm6, %xmm0 movaps %xmm3, %xmm1 mulss %xmm7, %xmm1 addss %xmm0, %xmm1 movaps %xmm2, %xmm5 mulss %xmm13, %xmm5 addss %xmm1, %xmm5 movss -108(%rsp), %xmm3 # 4-byte Reload # xmm3 = mem[0],zero,zero,zero movaps %xmm3, %xmm0 mulss %xmm10, %xmm0 movss -92(%rsp), %xmm2 # 4-byte Reload # xmm2 = mem[0],zero,zero,zero movaps %xmm2, %xmm1 mulss %xmm12, %xmm1 addss %xmm0, %xmm1 movss -96(%rsp), %xmm11 # 4-byte Reload # xmm11 = mem[0],zero,zero,zero movaps %xmm11, %xmm14 mulss %xmm4, %xmm14 addss %xmm1, %xmm14 movaps %xmm3, %xmm1 movaps %xmm3, %xmm4 mulss %xmm9, %xmm1 movaps %xmm2, %xmm0 movaps %xmm2, %xmm13 mulss %xmm8, %xmm0 addss %xmm1, %xmm0 movaps %xmm11, %xmm2 mulss %xmm15, %xmm2 addss %xmm0, %xmm2 mulss %xmm6, %xmm4 movaps %xmm13, %xmm0 mulss %xmm7, %xmm0 addss %xmm4, %xmm0 movaps %xmm11, %xmm1 movss -112(%rsp), %xmm4 # 4-byte Reload # xmm4 = mem[0],zero,zero,zero mulss %xmm4, %xmm1 addss %xmm0, %xmm1 movss -76(%rsp), %xmm13 # 4-byte Reload # xmm13 = mem[0],zero,zero,zero mulss %xmm13, %xmm10 movss -104(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero mulss %xmm0, %xmm12 addss %xmm10, %xmm12 movss -100(%rsp), %xmm3 # 4-byte Reload # xmm3 = mem[0],zero,zero,zero movss -128(%rsp), %xmm10 # 4-byte Reload # xmm10 = mem[0],zero,zero,zero mulss %xmm3, %xmm10 addss %xmm12, %xmm10 movss %xmm10, -128(%rsp) # 4-byte Spill mulss %xmm13, %xmm9 mulss %xmm0, %xmm8 addss %xmm9, %xmm8 mulss %xmm3, %xmm15 addss %xmm8, %xmm15 mulss %xmm13, %xmm6 mulss %xmm0, %xmm7 addss %xmm6, %xmm7 mulss %xmm3, %xmm4 addss %xmm7, %xmm4 movss -84(%rsp), %xmm9 # 4-byte Reload # xmm9 = mem[0],zero,zero,zero movaps %xmm9, %xmm0 movss -116(%rsp), %xmm11 # 4-byte Reload # xmm11 = mem[0],zero,zero,zero mulss %xmm11, %xmm0 movss -88(%rsp), %xmm7 # 4-byte Reload # xmm7 = mem[0],zero,zero,zero movaps %xmm7, %xmm6 mulss %xmm2, %xmm6 addss %xmm0, %xmm6 movss -120(%rsp), %xmm12 # 4-byte Reload # xmm12 = mem[0],zero,zero,zero movaps %xmm12, %xmm3 mulss %xmm15, %xmm3 addss %xmm6, %xmm3 mulss %xmm5, %xmm9 movaps %xmm7, %xmm6 mulss %xmm1, %xmm6 addss %xmm9, %xmm6 movaps %xmm12, %xmm0 mulss %xmm4, %xmm0 addss %xmm6, %xmm0 movss %xmm0, -120(%rsp) # 4-byte Spill movss -108(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movaps %xmm0, %xmm6 movss -124(%rsp), %xmm8 # 4-byte Reload # xmm8 = mem[0],zero,zero,zero mulss %xmm8, %xmm6 movss -92(%rsp), %xmm10 # 4-byte Reload # xmm10 = mem[0],zero,zero,zero movaps %xmm10, %xmm9 mulss %xmm14, %xmm9 addss %xmm6, %xmm9 movss -96(%rsp), %xmm7 # 4-byte Reload # xmm7 = mem[0],zero,zero,zero movaps %xmm7, %xmm6 movss -128(%rsp), %xmm12 # 4-byte Reload # xmm12 = mem[0],zero,zero,zero mulss %xmm12, %xmm6 addss %xmm9, %xmm6 mulss %xmm0, %xmm5 movaps %xmm0, %xmm9 mulss %xmm10, %xmm1 movaps %xmm11, %xmm0 mulss %xmm11, %xmm9 mulss %xmm2, %xmm10 addss %xmm9, %xmm10 movaps %xmm7, %xmm9 mulss %xmm7, %xmm4 mulss %xmm15, %xmm9 addss %xmm10, %xmm9 addss %xmm5, %xmm1 addss %xmm1, %xmm4 movaps %xmm8, %xmm5 mulss %xmm13, %xmm5 movss -104(%rsp), %xmm1 # 4-byte Reload # xmm1 = mem[0],zero,zero,zero mulss %xmm1, %xmm14 addss %xmm5, %xmm14 movss -100(%rsp), %xmm7 # 4-byte Reload # xmm7 = mem[0],zero,zero,zero mulss %xmm7, %xmm12 addss %xmm14, %xmm12 mulss %xmm13, %xmm0 mulss %xmm1, %xmm2 addss %xmm0, %xmm2 mulss %xmm7, %xmm15 addss %xmm2, %xmm15 movss %xmm6, -68(%rsp) movss %xmm12, -64(%rsp) movss %xmm3, -60(%rsp) movss %xmm9, -56(%rsp) movss %xmm15, -52(%rsp) movss -120(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, -48(%rsp) movss %xmm4, -44(%rsp) xorl %eax, %eax retq .Lfunc_end4: .size main, .Lfunc_end4-main .cfi_endproc # -- End function .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80
.text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .amdgpu_metadata --- amdhsa.kernels: [] amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0005e43f_00000000-6_builtin_types.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2064: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2064: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z15cuda_upload_varPvi .type _Z15cuda_upload_varPvi, @function _Z15cuda_upload_varPvi: .LFB2057: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $24, %rsp .cfi_def_cfa_offset 48 movq %rdi, %rbp movl %esi, %ebx movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax movq %rsp, %rdi movl $4, %esi call cudaMalloc@PLT movslq %ebx, %rdx movl $1, %ecx movq %rbp, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movq (%rsp), %rax movq 8(%rsp), %rdx subq %fs:40, %rdx jne .L6 addq $24, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L6: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z15cuda_upload_varPvi, .-_Z15cuda_upload_varPvi .globl _Z17cuda_download_varPvS_i .type _Z17cuda_download_varPvS_i, @function _Z17cuda_download_varPvS_i: .LFB2058: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rbx movq %rsi, %rdi movslq %edx, %rdx movl $2, %ecx movq %rbx, %rsi call cudaMemcpy@PLT movq %rbx, %rdi call cudaFree@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z17cuda_download_varPvS_i, .-_Z17cuda_download_varPvS_i .globl _Z13intmat2x2_mul9intmat2x2S_ .type _Z13intmat2x2_mul9intmat2x2S_, @function _Z13intmat2x2_mul9intmat2x2S_: .LFB2059: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdi, %rax movq %rsi, %rdi movq %rdx, %rsi movq %rcx, %rdx movq %rax, %r9 sarq $32, %r9 movq %rdi, %r10 sarq $32, %r10 movq %rsi, %r8 sarq $32, %r8 sarq $32, %rcx movl %esi, %ebx imull %eax, %ebx movl %edx, %r11d imull %r9d, %r11d imull %r8d, %eax imull %ecx, %r9d leal (%rax,%r9), %r9d salq $32, %r9 leal (%rbx,%r11), %eax orq %r9, %rax imull %edi, %esi imull %r10d, %edx imull %edi, %r8d imull %r10d, %ecx leal (%r8,%rcx), %ecx salq $32, %rcx leal (%rsi,%rdx), %edx orq %rcx, %rdx popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2059: .size _Z13intmat2x2_mul9intmat2x2S_, .-_Z13intmat2x2_mul9intmat2x2S_ .globl _Z15floatmat3x3_mul11floatmat3x3S_ .type _Z15floatmat3x3_mul11floatmat3x3S_, @function _Z15floatmat3x3_mul11floatmat3x3S_: .LFB2060: .cfi_startproc endbr64 movq %rdi, %rax movss 8(%rsp), %xmm2 movss 12(%rsp), %xmm8 movss 16(%rsp), %xmm7 movss 20(%rsp), %xmm1 movss 24(%rsp), %xmm6 movss 28(%rsp), %xmm5 movss 32(%rsp), %xmm0 movss 48(%rsp), %xmm12 movss 52(%rsp), %xmm3 movss 60(%rsp), %xmm4 movss 64(%rsp), %xmm10 movss 72(%rsp), %xmm11 movss 76(%rsp), %xmm9 movss 80(%rsp), %xmm14 movaps %xmm2, %xmm15 mulss %xmm12, %xmm15 movaps %xmm8, %xmm13 mulss %xmm4, %xmm13 addss %xmm15, %xmm13 movaps %xmm7, %xmm15 mulss %xmm11, %xmm15 addss %xmm15, %xmm13 movss %xmm13, (%rdi) movaps %xmm1, %xmm15 mulss %xmm12, %xmm15 movaps %xmm6, %xmm13 mulss %xmm4, %xmm13 addss %xmm15, %xmm13 movaps %xmm5, %xmm15 mulss %xmm11, %xmm15 addss %xmm15, %xmm13 movss %xmm13, 12(%rdi) mulss %xmm0, %xmm12 mulss 36(%rsp), %xmm4 addss %xmm12, %xmm4 mulss 40(%rsp), %xmm11 addss %xmm11, %xmm4 movss %xmm4, 24(%rdi) movaps %xmm2, %xmm11 mulss %xmm3, %xmm11 movaps %xmm8, %xmm4 mulss %xmm10, %xmm4 addss %xmm11, %xmm4 movaps %xmm7, %xmm11 mulss %xmm9, %xmm11 addss %xmm11, %xmm4 movss %xmm4, 4(%rdi) movaps %xmm1, %xmm11 mulss %xmm3, %xmm11 movaps %xmm6, %xmm4 mulss %xmm10, %xmm4 addss %xmm11, %xmm4 movaps %xmm5, %xmm11 mulss %xmm9, %xmm11 addss %xmm11, %xmm4 movss %xmm4, 16(%rdi) mulss %xmm0, %xmm3 mulss 36(%rsp), %xmm10 addss %xmm10, %xmm3 mulss 40(%rsp), %xmm9 addss %xmm9, %xmm3 movss %xmm3, 28(%rdi) mulss 56(%rsp), %xmm2 mulss 68(%rsp), %xmm8 addss %xmm8, %xmm2 mulss %xmm14, %xmm7 addss %xmm7, %xmm2 movss %xmm2, 8(%rdi) mulss 56(%rsp), %xmm1 mulss 68(%rsp), %xmm6 addss %xmm6, %xmm1 mulss %xmm14, %xmm5 addss %xmm5, %xmm1 movss %xmm1, 20(%rdi) mulss 56(%rsp), %xmm0 movss 36(%rsp), %xmm1 mulss 68(%rsp), %xmm1 addss %xmm1, %xmm0 movaps %xmm14, %xmm1 mulss 40(%rsp), %xmm1 addss %xmm1, %xmm0 movss %xmm0, 32(%rdi) ret .cfi_endproc .LFE2060: .size _Z15floatmat3x3_mul11floatmat3x3S_, .-_Z15floatmat3x3_mul11floatmat3x3S_ .globl main .type main, @function main: .LFB2061: .cfi_startproc endbr64 movl $0, %eax ret .cfi_endproc .LFE2061: .size main, .-main .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "builtin_types.hip" .globl _Z15cuda_upload_varPvi # -- Begin function _Z15cuda_upload_varPvi .p2align 4, 0x90 .type _Z15cuda_upload_varPvi,@function _Z15cuda_upload_varPvi: # @_Z15cuda_upload_varPvi .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 pushq %rax .cfi_def_cfa_offset 32 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movl %esi, %ebx movq %rdi, %r14 movq %rsp, %rdi movl $4, %esi callq hipMalloc movq (%rsp), %rdi movslq %ebx, %rdx movq %r14, %rsi movl $1, %ecx callq hipMemcpy movq (%rsp), %rax addq $8, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z15cuda_upload_varPvi, .Lfunc_end0-_Z15cuda_upload_varPvi .cfi_endproc # -- End function .globl _Z17cuda_download_varPvS_i # -- Begin function _Z17cuda_download_varPvS_i .p2align 4, 0x90 .type _Z17cuda_download_varPvS_i,@function _Z17cuda_download_varPvS_i: # @_Z17cuda_download_varPvS_i .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset %rbx, -16 movq %rdi, %rbx movslq %edx, %rdx movq %rsi, %rdi movq %rbx, %rsi movl $2, %ecx callq hipMemcpy movq %rbx, %rdi popq %rbx .cfi_def_cfa_offset 8 jmp hipFree # TAILCALL .Lfunc_end1: .size _Z17cuda_download_varPvS_i, .Lfunc_end1-_Z17cuda_download_varPvS_i .cfi_endproc # -- End function .globl _Z13intmat2x2_mul9intmat2x2S_ # -- Begin function _Z13intmat2x2_mul9intmat2x2S_ .p2align 4, 0x90 .type _Z13intmat2x2_mul9intmat2x2S_,@function _Z13intmat2x2_mul9intmat2x2S_: # @_Z13intmat2x2_mul9intmat2x2S_ .cfi_startproc # %bb.0: movq %rdi, %r8 shrq $32, %r8 movq %rdx, %r9 shrq $32, %r9 movl %edx, %r10d imull %edi, %r10d imull %esi, %edx imull %r9d, %edi imull %esi, %r9d shrq $32, %rsi movq %rcx, %r11 shrq $32, %r11 movl %r8d, %eax imull %ecx, %eax addl %r10d, %eax imull %esi, %ecx addl %ecx, %edx imull %r11d, %r8d addl %edi, %r8d imull %esi, %r11d addl %r9d, %r11d shlq $32, %r8 orq %r8, %rax shlq $32, %r11 orq %r11, %rdx retq .Lfunc_end2: .size _Z13intmat2x2_mul9intmat2x2S_, .Lfunc_end2-_Z13intmat2x2_mul9intmat2x2S_ .cfi_endproc # -- End function .globl _Z15floatmat3x3_mul11floatmat3x3S_ # -- Begin function _Z15floatmat3x3_mul11floatmat3x3S_ .p2align 4, 0x90 .type _Z15floatmat3x3_mul11floatmat3x3S_,@function _Z15floatmat3x3_mul11floatmat3x3S_: # @_Z15floatmat3x3_mul11floatmat3x3S_ .cfi_startproc # %bb.0: movq %rdi, %rax movss 8(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero movss 48(%rsp), %xmm8 # xmm8 = mem[0],zero,zero,zero movss 60(%rsp), %xmm9 # xmm9 = mem[0],zero,zero,zero movaps %xmm1, %xmm2 mulss %xmm8, %xmm2 movaps %xmm0, %xmm4 mulss %xmm9, %xmm4 addss %xmm2, %xmm4 movss 16(%rsp), %xmm3 # xmm3 = mem[0],zero,zero,zero movss 72(%rsp), %xmm10 # xmm10 = mem[0],zero,zero,zero movaps %xmm3, %xmm2 mulss %xmm10, %xmm2 addss %xmm4, %xmm2 movss %xmm2, (%rdi) movss 20(%rsp), %xmm4 # xmm4 = mem[0],zero,zero,zero movss 24(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero movaps %xmm8, %xmm5 mulss %xmm4, %xmm5 movaps %xmm9, %xmm7 mulss %xmm2, %xmm7 addss %xmm5, %xmm7 movss 28(%rsp), %xmm6 # xmm6 = mem[0],zero,zero,zero movaps %xmm10, %xmm5 mulss %xmm6, %xmm5 addss %xmm7, %xmm5 movss %xmm5, 12(%rdi) movss 32(%rsp), %xmm7 # xmm7 = mem[0],zero,zero,zero movss 36(%rsp), %xmm5 # xmm5 = mem[0],zero,zero,zero mulss %xmm7, %xmm8 mulss %xmm5, %xmm9 addss %xmm8, %xmm9 movss 40(%rsp), %xmm8 # xmm8 = mem[0],zero,zero,zero mulss %xmm8, %xmm10 addss %xmm9, %xmm10 movss %xmm10, 24(%rdi) movss 52(%rsp), %xmm10 # xmm10 = mem[0],zero,zero,zero movss 64(%rsp), %xmm9 # xmm9 = mem[0],zero,zero,zero movaps %xmm1, %xmm11 mulss %xmm10, %xmm11 movaps %xmm0, %xmm12 mulss %xmm9, %xmm12 addss %xmm11, %xmm12 movss 76(%rsp), %xmm11 # xmm11 = mem[0],zero,zero,zero movaps %xmm3, %xmm13 mulss %xmm11, %xmm13 addss %xmm12, %xmm13 movss %xmm13, 4(%rdi) movaps %xmm4, %xmm12 mulss %xmm10, %xmm12 movaps %xmm2, %xmm13 mulss %xmm9, %xmm13 addss %xmm12, %xmm13 movaps %xmm6, %xmm12 mulss %xmm11, %xmm12 addss %xmm13, %xmm12 movss %xmm12, 16(%rdi) mulss %xmm7, %xmm10 mulss %xmm5, %xmm9 addss %xmm10, %xmm9 mulss %xmm8, %xmm11 addss %xmm9, %xmm11 movss %xmm11, 28(%rdi) movss 56(%rsp), %xmm9 # xmm9 = mem[0],zero,zero,zero movss 68(%rsp), %xmm10 # xmm10 = mem[0],zero,zero,zero mulss %xmm9, %xmm1 mulss %xmm10, %xmm0 addss %xmm1, %xmm0 movss 80(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero mulss %xmm1, %xmm3 addss %xmm0, %xmm3 movss %xmm3, 8(%rdi) mulss %xmm9, %xmm4 mulss %xmm10, %xmm2 addss %xmm4, %xmm2 mulss %xmm1, %xmm6 addss %xmm2, %xmm6 movss %xmm6, 20(%rdi) mulss %xmm9, %xmm7 mulss %xmm10, %xmm5 addss %xmm7, %xmm5 mulss %xmm1, %xmm8 addss %xmm5, %xmm8 movss %xmm8, 32(%rdi) retq .Lfunc_end3: .size _Z15floatmat3x3_mul11floatmat3x3S_, .Lfunc_end3-_Z15floatmat3x3_mul11floatmat3x3S_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: leaq -36(%rsp), %rax leaq -72(%rsp), %rcx xorl %edx, %edx .p2align 4, 0x90 .LBB4_1: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB4_2 Depth 2 xorl %esi, %esi .p2align 4, 0x90 .LBB4_2: # Parent Loop BB4_1 Depth=1 # => This Inner Loop Header: Depth=2 movl $1065353216, (%rcx,%rsi) # imm = 0x3F800000 movl $1073741824, (%rax,%rsi) # imm = 0x40000000 addq $12, %rsi cmpq $36, %rsi jne .LBB4_2 # %bb.3: # in Loop: Header=BB4_1 Depth=1 incq %rdx addq $4, %rax addq $4, %rcx cmpq $3, %rdx jne .LBB4_1 # %bb.4: movss -36(%rsp), %xmm11 # xmm11 = mem[0],zero,zero,zero movss -32(%rsp), %xmm15 # xmm15 = mem[0],zero,zero,zero movss -28(%rsp), %xmm10 # xmm10 = mem[0],zero,zero,zero movss %xmm10, -128(%rsp) # 4-byte Spill movss -24(%rsp), %xmm7 # xmm7 = mem[0],zero,zero,zero movss -20(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero movss -16(%rsp), %xmm4 # xmm4 = mem[0],zero,zero,zero movss %xmm4, -124(%rsp) # 4-byte Spill movss -12(%rsp), %xmm12 # xmm12 = mem[0],zero,zero,zero movss -8(%rsp), %xmm3 # xmm3 = mem[0],zero,zero,zero movss -4(%rsp), %xmm13 # xmm13 = mem[0],zero,zero,zero movss %xmm13, -112(%rsp) # 4-byte Spill movss -72(%rsp), %xmm8 # xmm8 = mem[0],zero,zero,zero movss %xmm8, -84(%rsp) # 4-byte Spill movss -60(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero movss %xmm0, -88(%rsp) # 4-byte Spill movss -48(%rsp), %xmm5 # xmm5 = mem[0],zero,zero,zero movss %xmm5, -120(%rsp) # 4-byte Spill movaps %xmm11, %xmm2 mulss %xmm8, %xmm2 movaps %xmm15, %xmm6 mulss %xmm0, %xmm6 addss %xmm2, %xmm6 mulss %xmm5, %xmm10 addss %xmm6, %xmm10 movaps %xmm7, %xmm2 movss %xmm7, -116(%rsp) # 4-byte Spill mulss %xmm8, %xmm2 movaps %xmm1, %xmm6 mulss %xmm0, %xmm6 addss %xmm2, %xmm6 movaps %xmm4, %xmm9 mulss %xmm5, %xmm9 addss %xmm6, %xmm9 movaps %xmm12, %xmm2 movaps %xmm12, %xmm4 movss %xmm12, -80(%rsp) # 4-byte Spill mulss %xmm8, %xmm2 movaps %xmm3, %xmm12 mulss %xmm0, %xmm12 addss %xmm2, %xmm12 movaps %xmm13, %xmm6 mulss %xmm5, %xmm6 addss %xmm12, %xmm6 movss -68(%rsp), %xmm5 # xmm5 = mem[0],zero,zero,zero movaps %xmm11, %xmm2 mulss %xmm5, %xmm2 movss -56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero movaps %xmm15, %xmm13 mulss %xmm0, %xmm13 movss %xmm0, -92(%rsp) # 4-byte Spill addss %xmm2, %xmm13 movss -44(%rsp), %xmm14 # xmm14 = mem[0],zero,zero,zero movss -128(%rsp), %xmm12 # 4-byte Reload # xmm12 = mem[0],zero,zero,zero mulss %xmm14, %xmm12 addss %xmm13, %xmm12 movaps %xmm7, %xmm2 movaps %xmm5, %xmm7 movss %xmm5, -108(%rsp) # 4-byte Spill mulss %xmm5, %xmm2 movaps %xmm1, %xmm5 mulss %xmm0, %xmm5 addss %xmm2, %xmm5 movss -124(%rsp), %xmm8 # 4-byte Reload # xmm8 = mem[0],zero,zero,zero mulss %xmm14, %xmm8 movss %xmm14, -96(%rsp) # 4-byte Spill addss %xmm5, %xmm8 movaps %xmm4, %xmm2 mulss %xmm7, %xmm2 movaps %xmm3, %xmm5 mulss %xmm0, %xmm5 addss %xmm2, %xmm5 movss -112(%rsp), %xmm13 # 4-byte Reload # xmm13 = mem[0],zero,zero,zero movaps %xmm13, %xmm7 mulss %xmm14, %xmm7 addss %xmm5, %xmm7 movss -64(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero mulss %xmm2, %xmm11 movaps %xmm2, %xmm0 movss -52(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero mulss %xmm2, %xmm15 movaps %xmm2, %xmm5 movss %xmm2, -104(%rsp) # 4-byte Spill addss %xmm11, %xmm15 movss -40(%rsp), %xmm2 # xmm2 = mem[0],zero,zero,zero movss %xmm2, -100(%rsp) # 4-byte Spill movss -128(%rsp), %xmm4 # 4-byte Reload # xmm4 = mem[0],zero,zero,zero mulss %xmm2, %xmm4 addss %xmm15, %xmm4 movss -116(%rsp), %xmm11 # 4-byte Reload # xmm11 = mem[0],zero,zero,zero mulss %xmm0, %xmm11 movaps %xmm0, %xmm14 movss %xmm0, -76(%rsp) # 4-byte Spill mulss %xmm5, %xmm1 addss %xmm11, %xmm1 movss -124(%rsp), %xmm15 # 4-byte Reload # xmm15 = mem[0],zero,zero,zero mulss %xmm2, %xmm15 addss %xmm1, %xmm15 movss -80(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero mulss %xmm14, %xmm0 mulss %xmm5, %xmm3 addss %xmm0, %xmm3 mulss %xmm2, %xmm13 addss %xmm3, %xmm13 movss %xmm13, -112(%rsp) # 4-byte Spill movss -84(%rsp), %xmm5 # 4-byte Reload # xmm5 = mem[0],zero,zero,zero movaps %xmm5, %xmm0 mulss %xmm10, %xmm0 movss -88(%rsp), %xmm3 # 4-byte Reload # xmm3 = mem[0],zero,zero,zero movaps %xmm3, %xmm1 mulss %xmm12, %xmm1 addss %xmm0, %xmm1 movss -120(%rsp), %xmm2 # 4-byte Reload # xmm2 = mem[0],zero,zero,zero movaps %xmm2, %xmm0 mulss %xmm4, %xmm0 movss %xmm4, -128(%rsp) # 4-byte Spill addss %xmm1, %xmm0 movss %xmm0, -124(%rsp) # 4-byte Spill movaps %xmm5, %xmm0 mulss %xmm9, %xmm0 movaps %xmm3, %xmm1 mulss %xmm8, %xmm1 addss %xmm0, %xmm1 movaps %xmm2, %xmm0 mulss %xmm15, %xmm0 addss %xmm1, %xmm0 movss %xmm0, -116(%rsp) # 4-byte Spill movaps %xmm5, %xmm0 mulss %xmm6, %xmm0 movaps %xmm3, %xmm1 mulss %xmm7, %xmm1 addss %xmm0, %xmm1 movaps %xmm2, %xmm5 mulss %xmm13, %xmm5 addss %xmm1, %xmm5 movss -108(%rsp), %xmm3 # 4-byte Reload # xmm3 = mem[0],zero,zero,zero movaps %xmm3, %xmm0 mulss %xmm10, %xmm0 movss -92(%rsp), %xmm2 # 4-byte Reload # xmm2 = mem[0],zero,zero,zero movaps %xmm2, %xmm1 mulss %xmm12, %xmm1 addss %xmm0, %xmm1 movss -96(%rsp), %xmm11 # 4-byte Reload # xmm11 = mem[0],zero,zero,zero movaps %xmm11, %xmm14 mulss %xmm4, %xmm14 addss %xmm1, %xmm14 movaps %xmm3, %xmm1 movaps %xmm3, %xmm4 mulss %xmm9, %xmm1 movaps %xmm2, %xmm0 movaps %xmm2, %xmm13 mulss %xmm8, %xmm0 addss %xmm1, %xmm0 movaps %xmm11, %xmm2 mulss %xmm15, %xmm2 addss %xmm0, %xmm2 mulss %xmm6, %xmm4 movaps %xmm13, %xmm0 mulss %xmm7, %xmm0 addss %xmm4, %xmm0 movaps %xmm11, %xmm1 movss -112(%rsp), %xmm4 # 4-byte Reload # xmm4 = mem[0],zero,zero,zero mulss %xmm4, %xmm1 addss %xmm0, %xmm1 movss -76(%rsp), %xmm13 # 4-byte Reload # xmm13 = mem[0],zero,zero,zero mulss %xmm13, %xmm10 movss -104(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero mulss %xmm0, %xmm12 addss %xmm10, %xmm12 movss -100(%rsp), %xmm3 # 4-byte Reload # xmm3 = mem[0],zero,zero,zero movss -128(%rsp), %xmm10 # 4-byte Reload # xmm10 = mem[0],zero,zero,zero mulss %xmm3, %xmm10 addss %xmm12, %xmm10 movss %xmm10, -128(%rsp) # 4-byte Spill mulss %xmm13, %xmm9 mulss %xmm0, %xmm8 addss %xmm9, %xmm8 mulss %xmm3, %xmm15 addss %xmm8, %xmm15 mulss %xmm13, %xmm6 mulss %xmm0, %xmm7 addss %xmm6, %xmm7 mulss %xmm3, %xmm4 addss %xmm7, %xmm4 movss -84(%rsp), %xmm9 # 4-byte Reload # xmm9 = mem[0],zero,zero,zero movaps %xmm9, %xmm0 movss -116(%rsp), %xmm11 # 4-byte Reload # xmm11 = mem[0],zero,zero,zero mulss %xmm11, %xmm0 movss -88(%rsp), %xmm7 # 4-byte Reload # xmm7 = mem[0],zero,zero,zero movaps %xmm7, %xmm6 mulss %xmm2, %xmm6 addss %xmm0, %xmm6 movss -120(%rsp), %xmm12 # 4-byte Reload # xmm12 = mem[0],zero,zero,zero movaps %xmm12, %xmm3 mulss %xmm15, %xmm3 addss %xmm6, %xmm3 mulss %xmm5, %xmm9 movaps %xmm7, %xmm6 mulss %xmm1, %xmm6 addss %xmm9, %xmm6 movaps %xmm12, %xmm0 mulss %xmm4, %xmm0 addss %xmm6, %xmm0 movss %xmm0, -120(%rsp) # 4-byte Spill movss -108(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movaps %xmm0, %xmm6 movss -124(%rsp), %xmm8 # 4-byte Reload # xmm8 = mem[0],zero,zero,zero mulss %xmm8, %xmm6 movss -92(%rsp), %xmm10 # 4-byte Reload # xmm10 = mem[0],zero,zero,zero movaps %xmm10, %xmm9 mulss %xmm14, %xmm9 addss %xmm6, %xmm9 movss -96(%rsp), %xmm7 # 4-byte Reload # xmm7 = mem[0],zero,zero,zero movaps %xmm7, %xmm6 movss -128(%rsp), %xmm12 # 4-byte Reload # xmm12 = mem[0],zero,zero,zero mulss %xmm12, %xmm6 addss %xmm9, %xmm6 mulss %xmm0, %xmm5 movaps %xmm0, %xmm9 mulss %xmm10, %xmm1 movaps %xmm11, %xmm0 mulss %xmm11, %xmm9 mulss %xmm2, %xmm10 addss %xmm9, %xmm10 movaps %xmm7, %xmm9 mulss %xmm7, %xmm4 mulss %xmm15, %xmm9 addss %xmm10, %xmm9 addss %xmm5, %xmm1 addss %xmm1, %xmm4 movaps %xmm8, %xmm5 mulss %xmm13, %xmm5 movss -104(%rsp), %xmm1 # 4-byte Reload # xmm1 = mem[0],zero,zero,zero mulss %xmm1, %xmm14 addss %xmm5, %xmm14 movss -100(%rsp), %xmm7 # 4-byte Reload # xmm7 = mem[0],zero,zero,zero mulss %xmm7, %xmm12 addss %xmm14, %xmm12 mulss %xmm13, %xmm0 mulss %xmm1, %xmm2 addss %xmm0, %xmm2 mulss %xmm7, %xmm15 addss %xmm2, %xmm15 movss %xmm6, -68(%rsp) movss %xmm12, -64(%rsp) movss %xmm3, -60(%rsp) movss %xmm9, -56(%rsp) movss %xmm15, -52(%rsp) movss -120(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero movss %xmm0, -48(%rsp) movss %xmm4, -44(%rsp) xorl %eax, %eax retq .Lfunc_end4: .size main, .Lfunc_end4-main .cfi_endproc # -- End function .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#define CUDART_NAN_F __int_as_float(0x7fffffff) #include "math.h" using namespace std; __global__ void impalaFindSmem(const float* list, const float* dataEvent, const int listLength, const int dataLength, int* matches) { int x = blockIdx.x * blockDim.x + threadIdx.x; //int y = blockIdx.y * blockDim.y + threadIdx.y; int temp = 1; //TODO: Implement shared memory //__shared__ float dataEventShared[1024]; //dataEventShared = dataEvent; if(x < listLength) { // For each element in dataEvent for(int y=0; y<dataLength ; ++y){ // Compare to entry in list and set temp to 0 if mismatch, except if NaN if(!isnan(dataEvent[y]) && (list[dataLength*x+y] != dataEvent[y])){ temp = 0; } } matches[x] = temp; } }
code for sm_80 Function : _Z14impalaFindSmemPKfS0_iiPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fe200078e00ff */ /*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */ /* 0x000fc80000000a00 */ /*0080*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */ /* 0x000fe20003f03270 */ /*0090*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fd800078e00ff */ /*00a0*/ @!P0 BRA 0xeb0 ; /* 0x00000e0000008947 */ /* 0x000fea0003800000 */ /*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fe200078e00ff */ /*00c0*/ UMOV UR4, 0x3 ; /* 0x0000000300047882 */ /* 0x000fe20000000000 */ /*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */ /* 0x000fe200078e00ff */ /*00e0*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */ /* 0x000fe40000000800 */ /*00f0*/ IADD3 R0, -R0, c[0x0][0x174], RZ ; /* 0x00005d0000007a10 */ /* 0x000fe20007ffe1ff */ /*0100*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0xc0, !UPT ; /* 0x0000000504047292 */ /* 0x000fc6000f8ec03f */ /*0110*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */ /* 0x000fe20003f06070 */ /*0120*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fd800078e00ff */ /*0130*/ @!P0 BRA 0xd20 ; /* 0x00000be000008947 */ /* 0x000fea0003800000 */ /*0140*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */ /* 0x000fe20000000800 */ /*0150*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x000fe200078e00ff */ /*0160*/ UIADD3 UR5, -UR4, UR5, URZ ; /* 0x0000000504057290 */ /* 0x000fe2000fffe13f */ /*0170*/ IMAD R2, R6, c[0x0][0x174], RZ ; /* 0x00005d0006027a24 */ /* 0x000fe400078e02ff */ /*0180*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fe400078e00ff */ /*0190*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */ /* 0x000fe200078e00ff */ /*01a0*/ ISETP.LT.AND P0, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */ /* 0x000fe2000bf01270 */ /*01b0*/ IMAD.U32 R8, RZ, RZ, UR5 ; /* 0x00000005ff087e24 */ /* 0x000fe4000f8e00ff */ /*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */ /* 0x000fc400078e00ff */ /*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */ /* 0x000fe400078e00ff */ /*01e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */ /* 0x000fcc00078e0203 */ /*01f0*/ @!P0 BRA 0xb50 ; /* 0x0000095000008947 */ /* 0x000fea0003800000 */ /*0200*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */ /* 0x000fe40003f24270 */ /*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fd60003f0f070 */ /*0220*/ @!P1 BRA 0x7c0 ; /* 0x0000059000009947 */ /* 0x000fea0003800000 */ /*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*0240*/ LDG.E R12, [R4.64] ; /* 0x00000006040c7981 */ /* 0x000ea8000c1e1900 */ /*0250*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000406040d7981 */ /* 0x000ee8000c1e1900 */ /*0260*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000806040e7981 */ /* 0x000f28000c1e1900 */ /*0270*/ LDG.E R19, [R4.64+0x10] ; /* 0x0000100604137981 */ /* 0x000f68000c1e1900 */ /*0280*/ LDG.E R20, [R4.64+0x14] ; /* 0x0000140604147981 */ /* 0x000f68000c1e1900 */ /*0290*/ LDG.E R21, [R4.64+0x18] ; /* 0x0000180604157981 */ /* 0x000f68000c1e1900 */ /*02a0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0604127981 */ /* 0x000f68000c1e1900 */ /*02b0*/ LDG.E R22, [R4.64+0x1c] ; /* 0x00001c0604167981 */ /* 0x000f62000c1e1900 */ /*02c0*/ FSETP.GTU.AND P2, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */ /* 0x004fc40003f4c200 */ /*02d0*/ FSETP.GTU.AND P3, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */ /* 0x008fe40003f6c200 */ /*02e0*/ FSETP.GTU.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */ /* 0x010fd20003f2c200 */ /*02f0*/ @!P2 LDG.E R9, [R2.64] ; /* 0x000000060209a981 */ /* 0x000ea8000c1e1900 */ /*0300*/ @!P3 LDG.E R10, [R2.64+0x4] ; /* 0x00000406020ab981 */ /* 0x000ee8000c1e1900 */ /*0310*/ @!P1 LDG.E R11, [R2.64+0x8] ; /* 0x00000806020b9981 */ /* 0x000f22000c1e1900 */ /*0320*/ FSETP.GTU.AND P6, PT, |R19|, +INF , PT ; /* 0x7f8000001300780b */ /* 0x020fe40003fcc200 */ /*0330*/ FSETP.GTU.AND P5, PT, |R20|, +INF , PT ; /* 0x7f8000001400780b */ /* 0x000fc40003fac200 */ /*0340*/ FSETP.GTU.AND P4, PT, |R21|, +INF , PT ; /* 0x7f8000001500780b */ /* 0x000fd60003f8c200 */ /*0350*/ @!P5 LDG.E R15, [R2.64+0x14] ; /* 0x00001406020fd981 */ /* 0x000f68000c1e1900 */ /*0360*/ @!P4 LDG.E R16, [R2.64+0x18] ; /* 0x000018060210c981 */ /* 0x000f62000c1e1900 */ /*0370*/ FSETP.NEU.AND P2, PT, R9, R12, !P2 ; /* 0x0000000c0900720b */ /* 0x004fc6000574d000 */ /*0380*/ LDG.E R12, [R4.64+0x20] ; /* 0x00002006040c7981 */ /* 0x000ea2000c1e1900 */ /*0390*/ FSETP.NEU.AND P3, PT, R10, R13, !P3 ; /* 0x0000000d0a00720b */ /* 0x008fc60005f6d000 */ /*03a0*/ LDG.E R10, [R4.64+0x28] ; /* 0x00002806040a7981 */ /* 0x000ee2000c1e1900 */ /*03b0*/ PLOP3.LUT P3, PT, P3, P2, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40001f65570 */ /*03c0*/ FSETP.GTU.AND P2, PT, |R18|, +INF , PT ; /* 0x7f8000001200780b */ /* 0x000fe20003f4c200 */ /*03d0*/ LDG.E R9, [R4.64+0x2c] ; /* 0x00002c0604097981 */ /* 0x000ea2000c1e1900 */ /*03e0*/ FSETP.NEU.AND P1, PT, R11, R14, !P1 ; /* 0x0000000e0b00720b */ /* 0x010fc60004f2d000 */ /*03f0*/ @!P6 LDG.E R14, [R2.64+0x10] ; /* 0x00001006020ee981 */ /* 0x000f22000c1e1900 */ /*0400*/ PLOP3.LUT P1, PT, P1, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40000f27570 */ /*0410*/ FSETP.GTU.AND P3, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */ /* 0x000fe20003f6c200 */ /*0420*/ LDG.E R11, [R4.64+0x24] ; /* 0x00002406040b7981 */ /* 0x000ea8000c1e1900 */ /*0430*/ @!P2 LDG.E R13, [R2.64+0xc] ; /* 0x00000c06020da981 */ /* 0x000ef0000c1e1900 */ /*0440*/ @!P3 LDG.E R17, [R2.64+0x1c] ; /* 0x00001c060211b981 */ /* 0x000ee2000c1e1900 */ /*0450*/ FSETP.NEU.AND P5, PT, R15, R20, !P5 ; /* 0x000000140f00720b */ /* 0x020fc40006fad000 */ /*0460*/ FSETP.NEU.AND P4, PT, R16, R21, !P4 ; /* 0x000000151000720b */ /* 0x000fe2000678d000 */ /*0470*/ LDG.E R20, [R4.64+0x3c] ; /* 0x00003c0604147981 */ /* 0x000f62000c1e1900 */ /*0480*/ FSETP.NEU.AND P6, PT, R14, R19, !P6 ; /* 0x000000130e00720b */ /* 0x010fc600077cd000 */ /*0490*/ LDG.E R19, [R4.64+0x38] ; /* 0x0000380604137981 */ /* 0x000f22000c1e1900 */ /*04a0*/ PLOP3.LUT P6, PT, P5, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40002fcd570 */ /*04b0*/ FSETP.GTU.AND P5, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */ /* 0x004fe40003fac200 */ /*04c0*/ FSETP.NEU.AND P2, PT, R13, R18, !P2 ; /* 0x000000120d00720b */ /* 0x008fe4000574d000 */ /*04d0*/ PLOP3.LUT P4, PT, P4, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe2000278d570 */ /*04e0*/ LDG.E R18, [R4.64+0x34] ; /* 0x0000340604127981 */ /* 0x000ea2000c1e1900 */ /*04f0*/ FSETP.GTU.AND P6, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */ /* 0x000fe40003fcc200 */ /*0500*/ PLOP3.LUT P1, PT, P2, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40001723570 */ /*0510*/ FSETP.GTU.AND P2, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */ /* 0x000fe40003f4c200 */ /*0520*/ FSETP.NEU.AND P3, PT, R17, R22, !P3 ; /* 0x000000161100720b */ /* 0x000fe20005f6d000 */ /*0530*/ @!P5 LDG.E R13, [R2.64+0x20] ; /* 0x00002006020dd981 */ /* 0x000ee6000c1e1900 */ /*0540*/ PLOP3.LUT P3, PT, P3, P4, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe20001f69570 */ /*0550*/ LDG.E R17, [R4.64+0x30] ; /* 0x0000300604117981 */ /* 0x000ea2000c1e1900 */ /*0560*/ FSETP.GTU.AND P4, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */ /* 0x000fc60003f8c200 */ /*0570*/ @!P6 LDG.E R14, [R2.64+0x24] ; /* 0x00002406020ee981 */ /* 0x000ea8000c1e1900 */ /*0580*/ @!P2 LDG.E R15, [R2.64+0x28] ; /* 0x00002806020fa981 */ /* 0x000f2c000c1e1900 */ /*0590*/ @!P4 LDG.E R16, [R2.64+0x2c] ; /* 0x00002c060210c981 */ /* 0x000f62000c1e1900 */ /*05a0*/ FSETP.NEU.AND P5, PT, R13, R12, !P5 ; /* 0x0000000c0d00720b */ /* 0x008fc40006fad000 */ /*05b0*/ SEL R12, R0, RZ, !P1 ; /* 0x000000ff000c7207 */ /* 0x000fe40004800000 */ /*05c0*/ FSETP.NEU.AND P6, PT, R14, R11, !P6 ; /* 0x0000000b0e00720b */ /* 0x004fe400077cd000 */ /*05d0*/ FSETP.GTU.AND P1, PT, |R17|, +INF , PT ; /* 0x7f8000001100780b */ /* 0x000fe40003f2c200 */ /*05e0*/ FSETP.NEU.AND P2, PT, R15, R10, !P2 ; /* 0x0000000a0f00720b */ /* 0x010fe4000574d000 */ /*05f0*/ PLOP3.LUT P5, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe400037ab570 */ /*0600*/ FSETP.GTU.AND P6, PT, |R18|, +INF , PT ; /* 0x7f8000001200780b */ /* 0x000fc40003fcc200 */ /*0610*/ PLOP3.LUT P5, PT, P2, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe400017ab570 */ /*0620*/ FSETP.GTU.AND P2, PT, |R19|, +INF , PT ; /* 0x7f8000001300780b */ /* 0x000fe40003f4c200 */ /*0630*/ FSETP.NEU.AND P4, PT, R16, R9, !P4 ; /* 0x000000091000720b */ /* 0x020fe2000678d000 */ /*0640*/ @!P1 LDG.E R0, [R2.64+0x30] ; /* 0x0000300602009981 */ /* 0x0000a6000c1e1900 */ /*0650*/ PLOP3.LUT P5, PT, P4, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc600027ab570 */ /*0660*/ @!P6 LDG.E R9, [R2.64+0x34] ; /* 0x000034060209e981 */ /* 0x0000e2000c1e1900 */ /*0670*/ FSETP.GTU.AND P4, PT, |R20|, +INF , PT ; /* 0x7f8000001400780b */ /* 0x000fc60003f8c200 */ /*0680*/ @!P2 LDG.E R10, [R2.64+0x38] ; /* 0x00003806020aa981 */ /* 0x000134000c1e1900 */ /*0690*/ @!P4 LDG.E R11, [R2.64+0x3c] ; /* 0x00003c06020bc981 */ /* 0x000162000c1e1900 */ /*06a0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */ /* 0x000fc40007ffe0ff */ /*06b0*/ SEL R12, R12, RZ, !P3 ; /* 0x000000ff0c0c7207 */ /* 0x000fc80005800000 */ /*06c0*/ SEL R12, R12, RZ, !P5 ; /* 0x000000ff0c0c7207 */ /* 0x000fe40006800000 */ /*06d0*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */ /* 0x001fe40007f7e0ff */ /*06e0*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */ /* 0x000fc60007ffe0ff */ /*06f0*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */ /* 0x000fe200018e0603 */ /*0700*/ FSETP.NEU.AND P1, PT, R0, R17, !P1 ; /* 0x000000110000720b */ /* 0x004fe40004f2d000 */ /*0710*/ FSETP.NEU.AND P6, PT, R9, R18, !P6 ; /* 0x000000120900720b */ /* 0x008fe400077cd000 */ /*0720*/ FSETP.NEU.AND P2, PT, R10, R19, !P2 ; /* 0x000000130a00720b */ /* 0x010fe4000574d000 */ /*0730*/ PLOP3.LUT P1, PT, P6, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc80003723570 */ /*0740*/ PLOP3.LUT P1, PT, P2, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40001723570 */ /*0750*/ ISETP.GT.AND P2, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */ /* 0x000fe40003f44270 */ /*0760*/ FSETP.NEU.AND P4, PT, R11, R20, !P4 ; /* 0x000000140b00720b */ /* 0x020fe4000678d000 */ /*0770*/ IADD3 R4, P6, R4, 0x40, RZ ; /* 0x0000004004047810 */ /* 0x000fe40007fde0ff */ /*0780*/ PLOP3.LUT P1, PT, P4, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc60002723570 */ /*0790*/ IMAD.X R5, RZ, RZ, R5, P6 ; /* 0x000000ffff057224 */ /* 0x000fe200030e0605 */ /*07a0*/ SEL R0, R12, RZ, !P1 ; /* 0x000000ff0c007207 */ /* 0x000fc60004800000 */ /*07b0*/ @P2 BRA 0x240 ; /* 0xfffffa8000002947 */ /* 0x000fea000383ffff */ /*07c0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */ /* 0x000fda0003f24270 */ /*07d0*/ @!P1 BRA 0xb30 ; /* 0x0000035000009947 */ /* 0x000fea0003800000 */ /*07e0*/ LDG.E R14, [R4.64] ; /* 0x00000006040e7981 */ /* 0x000ea8000c1e1900 */ /*07f0*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040604107981 */ /* 0x000ee2000c1e1900 */ /*0800*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */ /* 0x000fc60007f3e0ff */ /*0810*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080604117981 */ /* 0x000f24000c1e1900 */ /*0820*/ IMAD.X R11, RZ, RZ, R5, P1 ; /* 0x000000ffff0b7224 */ /* 0x000fe400008e0605 */ /*0830*/ LDG.E R20, [R4.64+0x10] ; /* 0x0000100604147981 */ /* 0x000f68000c1e1900 */ /*0840*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004060a137981 */ /* 0x000f28000c1e1900 */ /*0850*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0604127981 */ /* 0x000128000c1e1900 */ /*0860*/ LDG.E R22, [R10.64+0x8] ; /* 0x000008060a167981 */ /* 0x000f68000c1e1900 */ /*0870*/ LDG.E R21, [R10.64+0xc] ; /* 0x00000c060a157981 */ /* 0x000f62000c1e1900 */ /*0880*/ FSETP.GTU.AND P2, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */ /* 0x004fc40003f4c200 */ /*0890*/ FSETP.GTU.AND P0, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */ /* 0x008fd60003f0c200 */ /*08a0*/ @!P2 LDG.E R9, [R2.64] ; /* 0x000000060209a981 */ /* 0x000ea8000c1e1900 */ /*08b0*/ @!P0 LDG.E R13, [R2.64+0x4] ; /* 0x00000406020d8981 */ /* 0x000ee2000c1e1900 */ /*08c0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */ /* 0x000fe40007f3e0ff */ /*08d0*/ FSETP.GTU.AND P4, PT, |R17|, +INF , PT ; /* 0x7f8000001100780b */ /* 0x010fe40003f8c200 */ /*08e0*/ FSETP.GTU.AND P5, PT, |R20|, +INF , PT ; /* 0x7f8000001400780b */ /* 0x020fe40003fac200 */ /*08f0*/ FSETP.GTU.AND P6, PT, |R19|, +INF , PT ; /* 0x7f8000001300780b */ /* 0x000fc40003fcc200 */ /*0900*/ FSETP.GTU.AND P3, PT, |R21|, +INF , PT ; /* 0x7f8000001500780b */ /* 0x000fce0003f6c200 */ /*0910*/ @!P4 LDG.E R4, [R2.64+0x8] ; /* 0x000008060204c981 */ /* 0x001f22000c1e1900 */ /*0920*/ FSETP.NEU.AND P2, PT, R9, R14, !P2 ; /* 0x0000000e0900720b */ /* 0x004fc6000574d000 */ /*0930*/ @!P5 LDG.E R9, [R2.64+0x10] ; /* 0x000010060209d981 */ /* 0x000ea2000c1e1900 */ /*0940*/ FSETP.NEU.AND P0, PT, R13, R16, !P0 ; /* 0x000000100d00720b */ /* 0x008fe2000470d000 */ /*0950*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */ /* 0x000fe200008e0603 */ /*0960*/ FSETP.GTU.AND P1, PT, |R18|, +INF , PT ; /* 0x7f8000001200780b */ /* 0x000fe40003f2c200 */ /*0970*/ PLOP3.LUT P0, PT, P0, P2, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40000705570 */ /*0980*/ FSETP.GTU.AND P2, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */ /* 0x000fe20003f4c200 */ /*0990*/ @!P6 LDG.E R14, [R12.64+0x4] ; /* 0x000004060c0ee981 */ /* 0x000ee8000c1e1900 */ /*09a0*/ @!P3 LDG.E R16, [R12.64+0xc] ; /* 0x00000c060c10b981 */ /* 0x000f68000c1e1900 */ /*09b0*/ @!P1 LDG.E R5, [R2.64+0xc] ; /* 0x00000c0602059981 */ /* 0x000f68000c1e1900 */ /*09c0*/ @!P2 LDG.E R15, [R12.64+0x8] ; /* 0x000008060c0fa981 */ /* 0x000f62000c1e1900 */ /*09d0*/ FSETP.NEU.AND P4, PT, R4, R17, !P4 ; /* 0x000000110400720b */ /* 0x010fc8000678d000 */ /*09e0*/ PLOP3.LUT P4, PT, P4, P0, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40002781570 */ /*09f0*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */ /* 0x000fe40007ffe0ff */ /*0a00*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */ /* 0x000fe40007ffe0ff */ /*0a10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*0a20*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */ /* 0x000fe40007ffe0ff */ /*0a30*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */ /* 0x000fc40007ffe0ff */ /*0a40*/ FSETP.NEU.AND P5, PT, R9, R20, !P5 ; /* 0x000000140900720b */ /* 0x004fe40006fad000 */ /*0a50*/ FSETP.NEU.AND P6, PT, R14, R19, !P6 ; /* 0x000000130e00720b */ /* 0x008fc800077cd000 */ /*0a60*/ PLOP3.LUT P5, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe400037ab570 */ /*0a70*/ FSETP.NEU.AND P1, PT, R5, R18, !P1 ; /* 0x000000120500720b */ /* 0x020fe40004f2d000 */ /*0a80*/ FSETP.NEU.AND P2, PT, R15, R22, !P2 ; /* 0x000000160f00720b */ /* 0x000fe4000574d000 */ /*0a90*/ FSETP.NEU.AND P3, PT, R16, R21, !P3 ; /* 0x000000151000720b */ /* 0x000fe40005f6d000 */ /*0aa0*/ PLOP3.LUT P2, PT, P2, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe4000174b570 */ /*0ab0*/ PLOP3.LUT P1, PT, P1, P4, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40000f29570 */ /*0ac0*/ IADD3 R2, P5, R12, 0x10, RZ ; /* 0x000000100c027810 */ /* 0x000fe40007fbe0ff */ /*0ad0*/ IADD3 R4, P4, R10, 0x10, RZ ; /* 0x000000100a047810 */ /* 0x000fe40007f9e0ff */ /*0ae0*/ PLOP3.LUT P2, PT, P3, P2, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40001f45570 */ /*0af0*/ SEL R0, R0, RZ, !P1 ; /* 0x000000ff00007207 */ /* 0x000fe20004800000 */ /*0b00*/ IMAD.X R3, RZ, RZ, R13, P5 ; /* 0x000000ffff037224 */ /* 0x000fe400028e060d */ /*0b10*/ IMAD.X R5, RZ, RZ, R11, P4 ; /* 0x000000ffff057224 */ /* 0x000fe200020e060b */ /*0b20*/ SEL R0, R0, RZ, !P2 ; /* 0x000000ff00007207 */ /* 0x000fc40005000000 */ /*0b30*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */ /* 0x000fda0000705670 */ /*0b40*/ @!P0 BRA 0xd20 ; /* 0x000001d000008947 */ /* 0x000fea0003800000 */ /*0b50*/ LDG.E R14, [R4.64] ; /* 0x00000006040e7981 */ /* 0x000ea8000c1e1900 */ /*0b60*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000406040d7981 */ /* 0x000ee8000c1e1900 */ /*0b70*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080604107981 */ /* 0x000f28000c1e1900 */ /*0b80*/ LDG.E R15, [R4.64+0xc] ; /* 0x00000c06040f7981 */ /* 0x000f62000c1e1900 */ /*0b90*/ FSETP.GTU.AND P2, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */ /* 0x004fc40003f4c200 */ /*0ba0*/ FSETP.GTU.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */ /* 0x008fe40003f2c200 */ /*0bb0*/ FSETP.GTU.AND P3, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */ /* 0x010fe40003f6c200 */ /*0bc0*/ FSETP.GTU.AND P0, PT, |R15|, +INF , PT ; /* 0x7f8000000f00780b */ /* 0x020fce0003f0c200 */ /*0bd0*/ @!P2 LDG.E R9, [R2.64] ; /* 0x000000060209a981 */ /* 0x000ea8000c1e1900 */ /*0be0*/ @!P1 LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a9981 */ /* 0x000ee8000c1e1900 */ /*0bf0*/ @!P3 LDG.E R11, [R2.64+0x8] ; /* 0x00000806020bb981 */ /* 0x000f28000c1e1900 */ /*0c00*/ @!P0 LDG.E R12, [R2.64+0xc] ; /* 0x00000c06020c8981 */ /* 0x000f62000c1e1900 */ /*0c10*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */ /* 0x000fc40007ffe0ff */ /*0c20*/ IADD3 R4, P4, R4, 0x10, RZ ; /* 0x0000001004047810 */ /* 0x000fe40007f9e0ff */ /*0c30*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */ /* 0x000fc60007ffe0ff */ /*0c40*/ IMAD.X R5, RZ, RZ, R5, P4 ; /* 0x000000ffff057224 */ /* 0x000fe200020e0605 */ /*0c50*/ FSETP.NEU.AND P2, PT, R9, R14, !P2 ; /* 0x0000000e0900720b */ /* 0x004fe4000574d000 */ /*0c60*/ FSETP.NEU.AND P1, PT, R10, R13, !P1 ; /* 0x0000000d0a00720b */ /* 0x008fc80004f2d000 */ /*0c70*/ PLOP3.LUT P1, PT, P1, P2, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40000f25570 */ /*0c80*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */ /* 0x000fe40003f45270 */ /*0c90*/ FSETP.NEU.AND P3, PT, R11, R16, !P3 ; /* 0x000000100b00720b */ /* 0x010fe40005f6d000 */ /*0ca0*/ FSETP.NEU.AND P0, PT, R12, R15, !P0 ; /* 0x0000000f0c00720b */ /* 0x020fe4000470d000 */ /*0cb0*/ PLOP3.LUT P1, PT, P3, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40001f23570 */ /*0cc0*/ IADD3 R9, P3, R2, 0x10, RZ ; /* 0x0000001002097810 */ /* 0x000fc40007f7e0ff */ /*0cd0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc60000703570 */ /*0ce0*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */ /* 0x000fe200018e0603 */ /*0cf0*/ SEL R0, R0, RZ, !P0 ; /* 0x000000ff00007207 */ /* 0x000fe20004000000 */ /*0d00*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */ /* 0x000fe200078e0009 */ /*0d10*/ @P2 BRA 0xb50 ; /* 0xfffffe3000002947 */ /* 0x000fea000383ffff */ /*0d20*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */ /* 0x000fda000bf05270 */ /*0d30*/ @!P0 BRA 0xeb0 ; /* 0x0000017000008947 */ /* 0x000fea0003800000 */ /*0d40*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */ /* 0x000fe400078e00ff */ /*0d50*/ IMAD R2, R6, c[0x0][0x174], R7 ; /* 0x00005d0006027a24 */ /* 0x000fc800078e0207 */ /*0d60*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */ /* 0x000fc800078e0204 */ /*0d70*/ IMAD.WIDE R4, R7, R4, c[0x0][0x168] ; /* 0x00005a0007047625 */ /* 0x000fc800078e0204 */ /*0d80*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */ /* 0x000fe400078e0002 */ /*0d90*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */ /* 0x000fe400078e0003 */ /*0da0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */ /* 0x000fc800078e0004 */ /*0db0*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */ /* 0x000fe400078e0007 */ /*0dc0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */ /* 0x000fca00078e0005 */ /*0dd0*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */ /* 0x000ea4000c1e1900 */ /*0de0*/ FSETP.GTU.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */ /* 0x004fda0003f0c200 */ /*0df0*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff028224 */ /* 0x000fe400078e0008 */ /*0e00*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff038224 */ /* 0x000fca00078e0009 */ /*0e10*/ @!P0 LDG.E R4, [R2.64] ; /* 0x0000000602048981 */ /* 0x000ea2000c1e1900 */ /*0e20*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */ /* 0x000fe2000fffe03f */ /*0e30*/ IADD3 R7, P3, R7, 0x4, RZ ; /* 0x0000000407077810 */ /* 0x000fe40007f7e0ff */ /*0e40*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */ /* 0x000fc60007f5e0ff */ /*0e50*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */ /* 0x000fe2000bf25270 */ /*0e60*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */ /* 0x000fe400018e0605 */ /*0e70*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */ /* 0x000fe200010e0609 */ /*0e80*/ FSETP.NEU.AND P0, PT, R4, R11, !P0 ; /* 0x0000000b0400720b */ /* 0x004fc8000470d000 */ /*0e90*/ SEL R0, R0, RZ, !P0 ; /* 0x000000ff00007207 */ /* 0x000fca0004000000 */ /*0ea0*/ @P1 BRA 0xdb0 ; /* 0xffffff0000001947 */ /* 0x000fea000383ffff */ /*0eb0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */ /* 0x000fc800078e00ff */ /*0ec0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */ /* 0x000fca00078e0207 */ /*0ed0*/ STG.E [R6.64], R0 ; /* 0x0000000006007986 */ /* 0x000fe2000c101906 */ /*0ee0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0ef0*/ BRA 0xef0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0f00*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f10*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f20*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f30*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f40*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f50*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#define CUDART_NAN_F __int_as_float(0x7fffffff) #include "math.h" using namespace std; __global__ void impalaFindSmem(const float* list, const float* dataEvent, const int listLength, const int dataLength, int* matches) { int x = blockIdx.x * blockDim.x + threadIdx.x; //int y = blockIdx.y * blockDim.y + threadIdx.y; int temp = 1; //TODO: Implement shared memory //__shared__ float dataEventShared[1024]; //dataEventShared = dataEvent; if(x < listLength) { // For each element in dataEvent for(int y=0; y<dataLength ; ++y){ // Compare to entry in list and set temp to 0 if mismatch, except if NaN if(!isnan(dataEvent[y]) && (list[dataLength*x+y] != dataEvent[y])){ temp = 0; } } matches[x] = temp; } }
.file "tmpxft_0007e3bc_00000000-6_impalaFindSmem.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z42__device_stub__Z14impalaFindSmemPKfS0_iiPiPKfS0_iiPi .type _Z42__device_stub__Z14impalaFindSmemPKfS0_iiPiPKfS0_iiPi, @function _Z42__device_stub__Z14impalaFindSmemPKfS0_iiPiPKfS0_iiPi: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %r8, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z14impalaFindSmemPKfS0_iiPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z42__device_stub__Z14impalaFindSmemPKfS0_iiPiPKfS0_iiPi, .-_Z42__device_stub__Z14impalaFindSmemPKfS0_iiPiPKfS0_iiPi .globl _Z14impalaFindSmemPKfS0_iiPi .type _Z14impalaFindSmemPKfS0_iiPi, @function _Z14impalaFindSmemPKfS0_iiPi: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z42__device_stub__Z14impalaFindSmemPKfS0_iiPiPKfS0_iiPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z14impalaFindSmemPKfS0_iiPi, .-_Z14impalaFindSmemPKfS0_iiPi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z14impalaFindSmemPKfS0_iiPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z14impalaFindSmemPKfS0_iiPi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#define CUDART_NAN_F __int_as_float(0x7fffffff) #include "math.h" using namespace std; __global__ void impalaFindSmem(const float* list, const float* dataEvent, const int listLength, const int dataLength, int* matches) { int x = blockIdx.x * blockDim.x + threadIdx.x; //int y = blockIdx.y * blockDim.y + threadIdx.y; int temp = 1; //TODO: Implement shared memory //__shared__ float dataEventShared[1024]; //dataEventShared = dataEvent; if(x < listLength) { // For each element in dataEvent for(int y=0; y<dataLength ; ++y){ // Compare to entry in list and set temp to 0 if mismatch, except if NaN if(!isnan(dataEvent[y]) && (list[dataLength*x+y] != dataEvent[y])){ temp = 0; } } matches[x] = temp; } }
#define HIP_NAN_F __int_as_float(0x7fffffff) #include <hip/hip_runtime.h> #include "math.h" using namespace std; __global__ void impalaFindSmem(const float* list, const float* dataEvent, const int listLength, const int dataLength, int* matches) { int x = blockIdx.x * blockDim.x + threadIdx.x; //int y = blockIdx.y * blockDim.y + threadIdx.y; int temp = 1; //TODO: Implement shared memory //__shared__ float dataEventShared[1024]; //dataEventShared = dataEvent; if(x < listLength) { // For each element in dataEvent for(int y=0; y<dataLength ; ++y){ // Compare to entry in list and set temp to 0 if mismatch, except if NaN if(!isnan(dataEvent[y]) && (list[dataLength*x+y] != dataEvent[y])){ temp = 0; } } matches[x] = temp; } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#define HIP_NAN_F __int_as_float(0x7fffffff) #include <hip/hip_runtime.h> #include "math.h" using namespace std; __global__ void impalaFindSmem(const float* list, const float* dataEvent, const int listLength, const int dataLength, int* matches) { int x = blockIdx.x * blockDim.x + threadIdx.x; //int y = blockIdx.y * blockDim.y + threadIdx.y; int temp = 1; //TODO: Implement shared memory //__shared__ float dataEventShared[1024]; //dataEventShared = dataEvent; if(x < listLength) { // For each element in dataEvent for(int y=0; y<dataLength ; ++y){ // Compare to entry in list and set temp to 0 if mismatch, except if NaN if(!isnan(dataEvent[y]) && (list[dataLength*x+y] != dataEvent[y])){ temp = 0; } } matches[x] = temp; } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14impalaFindSmemPKfS0_iiPi .globl _Z14impalaFindSmemPKfS0_iiPi .p2align 8 .type _Z14impalaFindSmemPKfS0_iiPi,@function _Z14impalaFindSmemPKfS0_iiPi: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_9 s_load_b32 s2, s[0:1], 0x14 v_mov_b32_e32 v0, 1 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s2, 1 s_cbranch_scc1 .LBB0_8 s_load_b128 s[4:7], s[0:1], 0x0 v_mul_lo_u32 v2, v1, s2 v_mov_b32_e32 v0, 1 .p2align 6 .LBB0_3: s_waitcnt lgkmcnt(0) s_load_b32 s3, s[6:7], 0x0 s_waitcnt lgkmcnt(0) v_cmp_u_f32_e64 s8, s3, s3 s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s8 s_cbranch_vccnz .LBB0_7 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 2, v[2:3] v_add_co_u32 v3, vcc_lo, s4, v3 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo global_load_b32 v3, v[3:4], off s_waitcnt vmcnt(0) v_cmp_neq_f32_e32 vcc_lo, s3, v3 s_and_saveexec_b32 s3, vcc_lo v_mov_b32_e32 v0, 0 s_or_b32 exec_lo, exec_lo, s3 .LBB0_7: v_add_nc_u32_e32 v2, 1, v2 s_add_i32 s2, s2, -1 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_cmp_eq_u32 s2, 0 s_cbranch_scc0 .LBB0_3 .LBB0_8: s_load_b64 s[0:1], s[0:1], 0x18 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v1, vcc_lo, s0, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo global_store_b32 v[1:2], v0, off .LBB0_9: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14impalaFindSmemPKfS0_iiPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14impalaFindSmemPKfS0_iiPi, .Lfunc_end0-_Z14impalaFindSmemPKfS0_iiPi .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14impalaFindSmemPKfS0_iiPi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14impalaFindSmemPKfS0_iiPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#define HIP_NAN_F __int_as_float(0x7fffffff) #include <hip/hip_runtime.h> #include "math.h" using namespace std; __global__ void impalaFindSmem(const float* list, const float* dataEvent, const int listLength, const int dataLength, int* matches) { int x = blockIdx.x * blockDim.x + threadIdx.x; //int y = blockIdx.y * blockDim.y + threadIdx.y; int temp = 1; //TODO: Implement shared memory //__shared__ float dataEventShared[1024]; //dataEventShared = dataEvent; if(x < listLength) { // For each element in dataEvent for(int y=0; y<dataLength ; ++y){ // Compare to entry in list and set temp to 0 if mismatch, except if NaN if(!isnan(dataEvent[y]) && (list[dataLength*x+y] != dataEvent[y])){ temp = 0; } } matches[x] = temp; } }
.text .file "impalaFindSmem.hip" .globl _Z29__device_stub__impalaFindSmemPKfS0_iiPi # -- Begin function _Z29__device_stub__impalaFindSmemPKfS0_iiPi .p2align 4, 0x90 .type _Z29__device_stub__impalaFindSmemPKfS0_iiPi,@function _Z29__device_stub__impalaFindSmemPKfS0_iiPi: # @_Z29__device_stub__impalaFindSmemPKfS0_iiPi .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 4(%rsp) movl %ecx, (%rsp) movq %r8, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movq %rsp, %rax movq %rax, 104(%rsp) leaq 56(%rsp), %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z14impalaFindSmemPKfS0_iiPi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z29__device_stub__impalaFindSmemPKfS0_iiPi, .Lfunc_end0-_Z29__device_stub__impalaFindSmemPKfS0_iiPi .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14impalaFindSmemPKfS0_iiPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z14impalaFindSmemPKfS0_iiPi,@object # @_Z14impalaFindSmemPKfS0_iiPi .section .rodata,"a",@progbits .globl _Z14impalaFindSmemPKfS0_iiPi .p2align 3, 0x0 _Z14impalaFindSmemPKfS0_iiPi: .quad _Z29__device_stub__impalaFindSmemPKfS0_iiPi .size _Z14impalaFindSmemPKfS0_iiPi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z14impalaFindSmemPKfS0_iiPi" .size .L__unnamed_1, 29 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__impalaFindSmemPKfS0_iiPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14impalaFindSmemPKfS0_iiPi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z14impalaFindSmemPKfS0_iiPi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fe200078e00ff */ /*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */ /* 0x000fc80000000a00 */ /*0080*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */ /* 0x000fe20003f03270 */ /*0090*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fd800078e00ff */ /*00a0*/ @!P0 BRA 0xeb0 ; /* 0x00000e0000008947 */ /* 0x000fea0003800000 */ /*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fe200078e00ff */ /*00c0*/ UMOV UR4, 0x3 ; /* 0x0000000300047882 */ /* 0x000fe20000000000 */ /*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */ /* 0x000fe200078e00ff */ /*00e0*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */ /* 0x000fe40000000800 */ /*00f0*/ IADD3 R0, -R0, c[0x0][0x174], RZ ; /* 0x00005d0000007a10 */ /* 0x000fe20007ffe1ff */ /*0100*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0xc0, !UPT ; /* 0x0000000504047292 */ /* 0x000fc6000f8ec03f */ /*0110*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */ /* 0x000fe20003f06070 */ /*0120*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fd800078e00ff */ /*0130*/ @!P0 BRA 0xd20 ; /* 0x00000be000008947 */ /* 0x000fea0003800000 */ /*0140*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */ /* 0x000fe20000000800 */ /*0150*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */ /* 0x000fe200078e00ff */ /*0160*/ UIADD3 UR5, -UR4, UR5, URZ ; /* 0x0000000504057290 */ /* 0x000fe2000fffe13f */ /*0170*/ IMAD R2, R6, c[0x0][0x174], RZ ; /* 0x00005d0006027a24 */ /* 0x000fe400078e02ff */ /*0180*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */ /* 0x000fe400078e00ff */ /*0190*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */ /* 0x000fe200078e00ff */ /*01a0*/ ISETP.LT.AND P0, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */ /* 0x000fe2000bf01270 */ /*01b0*/ IMAD.U32 R8, RZ, RZ, UR5 ; /* 0x00000005ff087e24 */ /* 0x000fe4000f8e00ff */ /*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */ /* 0x000fc400078e00ff */ /*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */ /* 0x000fe400078e00ff */ /*01e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */ /* 0x000fcc00078e0203 */ /*01f0*/ @!P0 BRA 0xb50 ; /* 0x0000095000008947 */ /* 0x000fea0003800000 */ /*0200*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */ /* 0x000fe40003f24270 */ /*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fd60003f0f070 */ /*0220*/ @!P1 BRA 0x7c0 ; /* 0x0000059000009947 */ /* 0x000fea0003800000 */ /*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*0240*/ LDG.E R12, [R4.64] ; /* 0x00000006040c7981 */ /* 0x000ea8000c1e1900 */ /*0250*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000406040d7981 */ /* 0x000ee8000c1e1900 */ /*0260*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000806040e7981 */ /* 0x000f28000c1e1900 */ /*0270*/ LDG.E R19, [R4.64+0x10] ; /* 0x0000100604137981 */ /* 0x000f68000c1e1900 */ /*0280*/ LDG.E R20, [R4.64+0x14] ; /* 0x0000140604147981 */ /* 0x000f68000c1e1900 */ /*0290*/ LDG.E R21, [R4.64+0x18] ; /* 0x0000180604157981 */ /* 0x000f68000c1e1900 */ /*02a0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0604127981 */ /* 0x000f68000c1e1900 */ /*02b0*/ LDG.E R22, [R4.64+0x1c] ; /* 0x00001c0604167981 */ /* 0x000f62000c1e1900 */ /*02c0*/ FSETP.GTU.AND P2, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */ /* 0x004fc40003f4c200 */ /*02d0*/ FSETP.GTU.AND P3, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */ /* 0x008fe40003f6c200 */ /*02e0*/ FSETP.GTU.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */ /* 0x010fd20003f2c200 */ /*02f0*/ @!P2 LDG.E R9, [R2.64] ; /* 0x000000060209a981 */ /* 0x000ea8000c1e1900 */ /*0300*/ @!P3 LDG.E R10, [R2.64+0x4] ; /* 0x00000406020ab981 */ /* 0x000ee8000c1e1900 */ /*0310*/ @!P1 LDG.E R11, [R2.64+0x8] ; /* 0x00000806020b9981 */ /* 0x000f22000c1e1900 */ /*0320*/ FSETP.GTU.AND P6, PT, |R19|, +INF , PT ; /* 0x7f8000001300780b */ /* 0x020fe40003fcc200 */ /*0330*/ FSETP.GTU.AND P5, PT, |R20|, +INF , PT ; /* 0x7f8000001400780b */ /* 0x000fc40003fac200 */ /*0340*/ FSETP.GTU.AND P4, PT, |R21|, +INF , PT ; /* 0x7f8000001500780b */ /* 0x000fd60003f8c200 */ /*0350*/ @!P5 LDG.E R15, [R2.64+0x14] ; /* 0x00001406020fd981 */ /* 0x000f68000c1e1900 */ /*0360*/ @!P4 LDG.E R16, [R2.64+0x18] ; /* 0x000018060210c981 */ /* 0x000f62000c1e1900 */ /*0370*/ FSETP.NEU.AND P2, PT, R9, R12, !P2 ; /* 0x0000000c0900720b */ /* 0x004fc6000574d000 */ /*0380*/ LDG.E R12, [R4.64+0x20] ; /* 0x00002006040c7981 */ /* 0x000ea2000c1e1900 */ /*0390*/ FSETP.NEU.AND P3, PT, R10, R13, !P3 ; /* 0x0000000d0a00720b */ /* 0x008fc60005f6d000 */ /*03a0*/ LDG.E R10, [R4.64+0x28] ; /* 0x00002806040a7981 */ /* 0x000ee2000c1e1900 */ /*03b0*/ PLOP3.LUT P3, PT, P3, P2, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40001f65570 */ /*03c0*/ FSETP.GTU.AND P2, PT, |R18|, +INF , PT ; /* 0x7f8000001200780b */ /* 0x000fe20003f4c200 */ /*03d0*/ LDG.E R9, [R4.64+0x2c] ; /* 0x00002c0604097981 */ /* 0x000ea2000c1e1900 */ /*03e0*/ FSETP.NEU.AND P1, PT, R11, R14, !P1 ; /* 0x0000000e0b00720b */ /* 0x010fc60004f2d000 */ /*03f0*/ @!P6 LDG.E R14, [R2.64+0x10] ; /* 0x00001006020ee981 */ /* 0x000f22000c1e1900 */ /*0400*/ PLOP3.LUT P1, PT, P1, P3, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40000f27570 */ /*0410*/ FSETP.GTU.AND P3, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */ /* 0x000fe20003f6c200 */ /*0420*/ LDG.E R11, [R4.64+0x24] ; /* 0x00002406040b7981 */ /* 0x000ea8000c1e1900 */ /*0430*/ @!P2 LDG.E R13, [R2.64+0xc] ; /* 0x00000c06020da981 */ /* 0x000ef0000c1e1900 */ /*0440*/ @!P3 LDG.E R17, [R2.64+0x1c] ; /* 0x00001c060211b981 */ /* 0x000ee2000c1e1900 */ /*0450*/ FSETP.NEU.AND P5, PT, R15, R20, !P5 ; /* 0x000000140f00720b */ /* 0x020fc40006fad000 */ /*0460*/ FSETP.NEU.AND P4, PT, R16, R21, !P4 ; /* 0x000000151000720b */ /* 0x000fe2000678d000 */ /*0470*/ LDG.E R20, [R4.64+0x3c] ; /* 0x00003c0604147981 */ /* 0x000f62000c1e1900 */ /*0480*/ FSETP.NEU.AND P6, PT, R14, R19, !P6 ; /* 0x000000130e00720b */ /* 0x010fc600077cd000 */ /*0490*/ LDG.E R19, [R4.64+0x38] ; /* 0x0000380604137981 */ /* 0x000f22000c1e1900 */ /*04a0*/ PLOP3.LUT P6, PT, P5, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40002fcd570 */ /*04b0*/ FSETP.GTU.AND P5, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */ /* 0x004fe40003fac200 */ /*04c0*/ FSETP.NEU.AND P2, PT, R13, R18, !P2 ; /* 0x000000120d00720b */ /* 0x008fe4000574d000 */ /*04d0*/ PLOP3.LUT P4, PT, P4, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe2000278d570 */ /*04e0*/ LDG.E R18, [R4.64+0x34] ; /* 0x0000340604127981 */ /* 0x000ea2000c1e1900 */ /*04f0*/ FSETP.GTU.AND P6, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */ /* 0x000fe40003fcc200 */ /*0500*/ PLOP3.LUT P1, PT, P2, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40001723570 */ /*0510*/ FSETP.GTU.AND P2, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */ /* 0x000fe40003f4c200 */ /*0520*/ FSETP.NEU.AND P3, PT, R17, R22, !P3 ; /* 0x000000161100720b */ /* 0x000fe20005f6d000 */ /*0530*/ @!P5 LDG.E R13, [R2.64+0x20] ; /* 0x00002006020dd981 */ /* 0x000ee6000c1e1900 */ /*0540*/ PLOP3.LUT P3, PT, P3, P4, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe20001f69570 */ /*0550*/ LDG.E R17, [R4.64+0x30] ; /* 0x0000300604117981 */ /* 0x000ea2000c1e1900 */ /*0560*/ FSETP.GTU.AND P4, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */ /* 0x000fc60003f8c200 */ /*0570*/ @!P6 LDG.E R14, [R2.64+0x24] ; /* 0x00002406020ee981 */ /* 0x000ea8000c1e1900 */ /*0580*/ @!P2 LDG.E R15, [R2.64+0x28] ; /* 0x00002806020fa981 */ /* 0x000f2c000c1e1900 */ /*0590*/ @!P4 LDG.E R16, [R2.64+0x2c] ; /* 0x00002c060210c981 */ /* 0x000f62000c1e1900 */ /*05a0*/ FSETP.NEU.AND P5, PT, R13, R12, !P5 ; /* 0x0000000c0d00720b */ /* 0x008fc40006fad000 */ /*05b0*/ SEL R12, R0, RZ, !P1 ; /* 0x000000ff000c7207 */ /* 0x000fe40004800000 */ /*05c0*/ FSETP.NEU.AND P6, PT, R14, R11, !P6 ; /* 0x0000000b0e00720b */ /* 0x004fe400077cd000 */ /*05d0*/ FSETP.GTU.AND P1, PT, |R17|, +INF , PT ; /* 0x7f8000001100780b */ /* 0x000fe40003f2c200 */ /*05e0*/ FSETP.NEU.AND P2, PT, R15, R10, !P2 ; /* 0x0000000a0f00720b */ /* 0x010fe4000574d000 */ /*05f0*/ PLOP3.LUT P5, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe400037ab570 */ /*0600*/ FSETP.GTU.AND P6, PT, |R18|, +INF , PT ; /* 0x7f8000001200780b */ /* 0x000fc40003fcc200 */ /*0610*/ PLOP3.LUT P5, PT, P2, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe400017ab570 */ /*0620*/ FSETP.GTU.AND P2, PT, |R19|, +INF , PT ; /* 0x7f8000001300780b */ /* 0x000fe40003f4c200 */ /*0630*/ FSETP.NEU.AND P4, PT, R16, R9, !P4 ; /* 0x000000091000720b */ /* 0x020fe2000678d000 */ /*0640*/ @!P1 LDG.E R0, [R2.64+0x30] ; /* 0x0000300602009981 */ /* 0x0000a6000c1e1900 */ /*0650*/ PLOP3.LUT P5, PT, P4, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc600027ab570 */ /*0660*/ @!P6 LDG.E R9, [R2.64+0x34] ; /* 0x000034060209e981 */ /* 0x0000e2000c1e1900 */ /*0670*/ FSETP.GTU.AND P4, PT, |R20|, +INF , PT ; /* 0x7f8000001400780b */ /* 0x000fc60003f8c200 */ /*0680*/ @!P2 LDG.E R10, [R2.64+0x38] ; /* 0x00003806020aa981 */ /* 0x000134000c1e1900 */ /*0690*/ @!P4 LDG.E R11, [R2.64+0x3c] ; /* 0x00003c06020bc981 */ /* 0x000162000c1e1900 */ /*06a0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */ /* 0x000fc40007ffe0ff */ /*06b0*/ SEL R12, R12, RZ, !P3 ; /* 0x000000ff0c0c7207 */ /* 0x000fc80005800000 */ /*06c0*/ SEL R12, R12, RZ, !P5 ; /* 0x000000ff0c0c7207 */ /* 0x000fe40006800000 */ /*06d0*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */ /* 0x001fe40007f7e0ff */ /*06e0*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */ /* 0x000fc60007ffe0ff */ /*06f0*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */ /* 0x000fe200018e0603 */ /*0700*/ FSETP.NEU.AND P1, PT, R0, R17, !P1 ; /* 0x000000110000720b */ /* 0x004fe40004f2d000 */ /*0710*/ FSETP.NEU.AND P6, PT, R9, R18, !P6 ; /* 0x000000120900720b */ /* 0x008fe400077cd000 */ /*0720*/ FSETP.NEU.AND P2, PT, R10, R19, !P2 ; /* 0x000000130a00720b */ /* 0x010fe4000574d000 */ /*0730*/ PLOP3.LUT P1, PT, P6, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc80003723570 */ /*0740*/ PLOP3.LUT P1, PT, P2, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40001723570 */ /*0750*/ ISETP.GT.AND P2, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */ /* 0x000fe40003f44270 */ /*0760*/ FSETP.NEU.AND P4, PT, R11, R20, !P4 ; /* 0x000000140b00720b */ /* 0x020fe4000678d000 */ /*0770*/ IADD3 R4, P6, R4, 0x40, RZ ; /* 0x0000004004047810 */ /* 0x000fe40007fde0ff */ /*0780*/ PLOP3.LUT P1, PT, P4, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc60002723570 */ /*0790*/ IMAD.X R5, RZ, RZ, R5, P6 ; /* 0x000000ffff057224 */ /* 0x000fe200030e0605 */ /*07a0*/ SEL R0, R12, RZ, !P1 ; /* 0x000000ff0c007207 */ /* 0x000fc60004800000 */ /*07b0*/ @P2 BRA 0x240 ; /* 0xfffffa8000002947 */ /* 0x000fea000383ffff */ /*07c0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */ /* 0x000fda0003f24270 */ /*07d0*/ @!P1 BRA 0xb30 ; /* 0x0000035000009947 */ /* 0x000fea0003800000 */ /*07e0*/ LDG.E R14, [R4.64] ; /* 0x00000006040e7981 */ /* 0x000ea8000c1e1900 */ /*07f0*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040604107981 */ /* 0x000ee2000c1e1900 */ /*0800*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */ /* 0x000fc60007f3e0ff */ /*0810*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080604117981 */ /* 0x000f24000c1e1900 */ /*0820*/ IMAD.X R11, RZ, RZ, R5, P1 ; /* 0x000000ffff0b7224 */ /* 0x000fe400008e0605 */ /*0830*/ LDG.E R20, [R4.64+0x10] ; /* 0x0000100604147981 */ /* 0x000f68000c1e1900 */ /*0840*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004060a137981 */ /* 0x000f28000c1e1900 */ /*0850*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0604127981 */ /* 0x000128000c1e1900 */ /*0860*/ LDG.E R22, [R10.64+0x8] ; /* 0x000008060a167981 */ /* 0x000f68000c1e1900 */ /*0870*/ LDG.E R21, [R10.64+0xc] ; /* 0x00000c060a157981 */ /* 0x000f62000c1e1900 */ /*0880*/ FSETP.GTU.AND P2, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */ /* 0x004fc40003f4c200 */ /*0890*/ FSETP.GTU.AND P0, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */ /* 0x008fd60003f0c200 */ /*08a0*/ @!P2 LDG.E R9, [R2.64] ; /* 0x000000060209a981 */ /* 0x000ea8000c1e1900 */ /*08b0*/ @!P0 LDG.E R13, [R2.64+0x4] ; /* 0x00000406020d8981 */ /* 0x000ee2000c1e1900 */ /*08c0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */ /* 0x000fe40007f3e0ff */ /*08d0*/ FSETP.GTU.AND P4, PT, |R17|, +INF , PT ; /* 0x7f8000001100780b */ /* 0x010fe40003f8c200 */ /*08e0*/ FSETP.GTU.AND P5, PT, |R20|, +INF , PT ; /* 0x7f8000001400780b */ /* 0x020fe40003fac200 */ /*08f0*/ FSETP.GTU.AND P6, PT, |R19|, +INF , PT ; /* 0x7f8000001300780b */ /* 0x000fc40003fcc200 */ /*0900*/ FSETP.GTU.AND P3, PT, |R21|, +INF , PT ; /* 0x7f8000001500780b */ /* 0x000fce0003f6c200 */ /*0910*/ @!P4 LDG.E R4, [R2.64+0x8] ; /* 0x000008060204c981 */ /* 0x001f22000c1e1900 */ /*0920*/ FSETP.NEU.AND P2, PT, R9, R14, !P2 ; /* 0x0000000e0900720b */ /* 0x004fc6000574d000 */ /*0930*/ @!P5 LDG.E R9, [R2.64+0x10] ; /* 0x000010060209d981 */ /* 0x000ea2000c1e1900 */ /*0940*/ FSETP.NEU.AND P0, PT, R13, R16, !P0 ; /* 0x000000100d00720b */ /* 0x008fe2000470d000 */ /*0950*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */ /* 0x000fe200008e0603 */ /*0960*/ FSETP.GTU.AND P1, PT, |R18|, +INF , PT ; /* 0x7f8000001200780b */ /* 0x000fe40003f2c200 */ /*0970*/ PLOP3.LUT P0, PT, P0, P2, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40000705570 */ /*0980*/ FSETP.GTU.AND P2, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */ /* 0x000fe20003f4c200 */ /*0990*/ @!P6 LDG.E R14, [R12.64+0x4] ; /* 0x000004060c0ee981 */ /* 0x000ee8000c1e1900 */ /*09a0*/ @!P3 LDG.E R16, [R12.64+0xc] ; /* 0x00000c060c10b981 */ /* 0x000f68000c1e1900 */ /*09b0*/ @!P1 LDG.E R5, [R2.64+0xc] ; /* 0x00000c0602059981 */ /* 0x000f68000c1e1900 */ /*09c0*/ @!P2 LDG.E R15, [R12.64+0x8] ; /* 0x000008060c0fa981 */ /* 0x000f62000c1e1900 */ /*09d0*/ FSETP.NEU.AND P4, PT, R4, R17, !P4 ; /* 0x000000110400720b */ /* 0x010fc8000678d000 */ /*09e0*/ PLOP3.LUT P4, PT, P4, P0, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40002781570 */ /*09f0*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */ /* 0x000fe40007ffe0ff */ /*0a00*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */ /* 0x000fe40007ffe0ff */ /*0a10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*0a20*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */ /* 0x000fe40007ffe0ff */ /*0a30*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */ /* 0x000fc40007ffe0ff */ /*0a40*/ FSETP.NEU.AND P5, PT, R9, R20, !P5 ; /* 0x000000140900720b */ /* 0x004fe40006fad000 */ /*0a50*/ FSETP.NEU.AND P6, PT, R14, R19, !P6 ; /* 0x000000130e00720b */ /* 0x008fc800077cd000 */ /*0a60*/ PLOP3.LUT P5, PT, P6, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe400037ab570 */ /*0a70*/ FSETP.NEU.AND P1, PT, R5, R18, !P1 ; /* 0x000000120500720b */ /* 0x020fe40004f2d000 */ /*0a80*/ FSETP.NEU.AND P2, PT, R15, R22, !P2 ; /* 0x000000160f00720b */ /* 0x000fe4000574d000 */ /*0a90*/ FSETP.NEU.AND P3, PT, R16, R21, !P3 ; /* 0x000000151000720b */ /* 0x000fe40005f6d000 */ /*0aa0*/ PLOP3.LUT P2, PT, P2, P5, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe4000174b570 */ /*0ab0*/ PLOP3.LUT P1, PT, P1, P4, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40000f29570 */ /*0ac0*/ IADD3 R2, P5, R12, 0x10, RZ ; /* 0x000000100c027810 */ /* 0x000fe40007fbe0ff */ /*0ad0*/ IADD3 R4, P4, R10, 0x10, RZ ; /* 0x000000100a047810 */ /* 0x000fe40007f9e0ff */ /*0ae0*/ PLOP3.LUT P2, PT, P3, P2, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40001f45570 */ /*0af0*/ SEL R0, R0, RZ, !P1 ; /* 0x000000ff00007207 */ /* 0x000fe20004800000 */ /*0b00*/ IMAD.X R3, RZ, RZ, R13, P5 ; /* 0x000000ffff037224 */ /* 0x000fe400028e060d */ /*0b10*/ IMAD.X R5, RZ, RZ, R11, P4 ; /* 0x000000ffff057224 */ /* 0x000fe200020e060b */ /*0b20*/ SEL R0, R0, RZ, !P2 ; /* 0x000000ff00007207 */ /* 0x000fc40005000000 */ /*0b30*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */ /* 0x000fda0000705670 */ /*0b40*/ @!P0 BRA 0xd20 ; /* 0x000001d000008947 */ /* 0x000fea0003800000 */ /*0b50*/ LDG.E R14, [R4.64] ; /* 0x00000006040e7981 */ /* 0x000ea8000c1e1900 */ /*0b60*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000406040d7981 */ /* 0x000ee8000c1e1900 */ /*0b70*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080604107981 */ /* 0x000f28000c1e1900 */ /*0b80*/ LDG.E R15, [R4.64+0xc] ; /* 0x00000c06040f7981 */ /* 0x000f62000c1e1900 */ /*0b90*/ FSETP.GTU.AND P2, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */ /* 0x004fc40003f4c200 */ /*0ba0*/ FSETP.GTU.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */ /* 0x008fe40003f2c200 */ /*0bb0*/ FSETP.GTU.AND P3, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */ /* 0x010fe40003f6c200 */ /*0bc0*/ FSETP.GTU.AND P0, PT, |R15|, +INF , PT ; /* 0x7f8000000f00780b */ /* 0x020fce0003f0c200 */ /*0bd0*/ @!P2 LDG.E R9, [R2.64] ; /* 0x000000060209a981 */ /* 0x000ea8000c1e1900 */ /*0be0*/ @!P1 LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a9981 */ /* 0x000ee8000c1e1900 */ /*0bf0*/ @!P3 LDG.E R11, [R2.64+0x8] ; /* 0x00000806020bb981 */ /* 0x000f28000c1e1900 */ /*0c00*/ @!P0 LDG.E R12, [R2.64+0xc] ; /* 0x00000c06020c8981 */ /* 0x000f62000c1e1900 */ /*0c10*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */ /* 0x000fc40007ffe0ff */ /*0c20*/ IADD3 R4, P4, R4, 0x10, RZ ; /* 0x0000001004047810 */ /* 0x000fe40007f9e0ff */ /*0c30*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */ /* 0x000fc60007ffe0ff */ /*0c40*/ IMAD.X R5, RZ, RZ, R5, P4 ; /* 0x000000ffff057224 */ /* 0x000fe200020e0605 */ /*0c50*/ FSETP.NEU.AND P2, PT, R9, R14, !P2 ; /* 0x0000000e0900720b */ /* 0x004fe4000574d000 */ /*0c60*/ FSETP.NEU.AND P1, PT, R10, R13, !P1 ; /* 0x0000000d0a00720b */ /* 0x008fc80004f2d000 */ /*0c70*/ PLOP3.LUT P1, PT, P1, P2, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40000f25570 */ /*0c80*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */ /* 0x000fe40003f45270 */ /*0c90*/ FSETP.NEU.AND P3, PT, R11, R16, !P3 ; /* 0x000000100b00720b */ /* 0x010fe40005f6d000 */ /*0ca0*/ FSETP.NEU.AND P0, PT, R12, R15, !P0 ; /* 0x0000000f0c00720b */ /* 0x020fe4000470d000 */ /*0cb0*/ PLOP3.LUT P1, PT, P3, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40001f23570 */ /*0cc0*/ IADD3 R9, P3, R2, 0x10, RZ ; /* 0x0000001002097810 */ /* 0x000fc40007f7e0ff */ /*0cd0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc60000703570 */ /*0ce0*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */ /* 0x000fe200018e0603 */ /*0cf0*/ SEL R0, R0, RZ, !P0 ; /* 0x000000ff00007207 */ /* 0x000fe20004000000 */ /*0d00*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */ /* 0x000fe200078e0009 */ /*0d10*/ @P2 BRA 0xb50 ; /* 0xfffffe3000002947 */ /* 0x000fea000383ffff */ /*0d20*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */ /* 0x000fda000bf05270 */ /*0d30*/ @!P0 BRA 0xeb0 ; /* 0x0000017000008947 */ /* 0x000fea0003800000 */ /*0d40*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */ /* 0x000fe400078e00ff */ /*0d50*/ IMAD R2, R6, c[0x0][0x174], R7 ; /* 0x00005d0006027a24 */ /* 0x000fc800078e0207 */ /*0d60*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */ /* 0x000fc800078e0204 */ /*0d70*/ IMAD.WIDE R4, R7, R4, c[0x0][0x168] ; /* 0x00005a0007047625 */ /* 0x000fc800078e0204 */ /*0d80*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */ /* 0x000fe400078e0002 */ /*0d90*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */ /* 0x000fe400078e0003 */ /*0da0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */ /* 0x000fc800078e0004 */ /*0db0*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */ /* 0x000fe400078e0007 */ /*0dc0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */ /* 0x000fca00078e0005 */ /*0dd0*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */ /* 0x000ea4000c1e1900 */ /*0de0*/ FSETP.GTU.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */ /* 0x004fda0003f0c200 */ /*0df0*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff028224 */ /* 0x000fe400078e0008 */ /*0e00*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff038224 */ /* 0x000fca00078e0009 */ /*0e10*/ @!P0 LDG.E R4, [R2.64] ; /* 0x0000000602048981 */ /* 0x000ea2000c1e1900 */ /*0e20*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */ /* 0x000fe2000fffe03f */ /*0e30*/ IADD3 R7, P3, R7, 0x4, RZ ; /* 0x0000000407077810 */ /* 0x000fe40007f7e0ff */ /*0e40*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */ /* 0x000fc60007f5e0ff */ /*0e50*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */ /* 0x000fe2000bf25270 */ /*0e60*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */ /* 0x000fe400018e0605 */ /*0e70*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */ /* 0x000fe200010e0609 */ /*0e80*/ FSETP.NEU.AND P0, PT, R4, R11, !P0 ; /* 0x0000000b0400720b */ /* 0x004fc8000470d000 */ /*0e90*/ SEL R0, R0, RZ, !P0 ; /* 0x000000ff00007207 */ /* 0x000fca0004000000 */ /*0ea0*/ @P1 BRA 0xdb0 ; /* 0xffffff0000001947 */ /* 0x000fea000383ffff */ /*0eb0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */ /* 0x000fc800078e00ff */ /*0ec0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */ /* 0x000fca00078e0207 */ /*0ed0*/ STG.E [R6.64], R0 ; /* 0x0000000006007986 */ /* 0x000fe2000c101906 */ /*0ee0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0ef0*/ BRA 0xef0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0f00*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f10*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f20*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f30*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f40*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f50*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0f70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z14impalaFindSmemPKfS0_iiPi .globl _Z14impalaFindSmemPKfS0_iiPi .p2align 8 .type _Z14impalaFindSmemPKfS0_iiPi,@function _Z14impalaFindSmemPKfS0_iiPi: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x10 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_9 s_load_b32 s2, s[0:1], 0x14 v_mov_b32_e32 v0, 1 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s2, 1 s_cbranch_scc1 .LBB0_8 s_load_b128 s[4:7], s[0:1], 0x0 v_mul_lo_u32 v2, v1, s2 v_mov_b32_e32 v0, 1 .p2align 6 .LBB0_3: s_waitcnt lgkmcnt(0) s_load_b32 s3, s[6:7], 0x0 s_waitcnt lgkmcnt(0) v_cmp_u_f32_e64 s8, s3, s3 s_delay_alu instid0(VALU_DEP_1) s_and_b32 vcc_lo, exec_lo, s8 s_cbranch_vccnz .LBB0_7 v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[3:4], 2, v[2:3] v_add_co_u32 v3, vcc_lo, s4, v3 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo global_load_b32 v3, v[3:4], off s_waitcnt vmcnt(0) v_cmp_neq_f32_e32 vcc_lo, s3, v3 s_and_saveexec_b32 s3, vcc_lo v_mov_b32_e32 v0, 0 s_or_b32 exec_lo, exec_lo, s3 .LBB0_7: v_add_nc_u32_e32 v2, 1, v2 s_add_i32 s2, s2, -1 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_cmp_eq_u32 s2, 0 s_cbranch_scc0 .LBB0_3 .LBB0_8: s_load_b64 s[0:1], s[0:1], 0x18 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[1:2], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v1, vcc_lo, s0, v1 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo global_store_b32 v[1:2], v0, off .LBB0_9: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z14impalaFindSmemPKfS0_iiPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z14impalaFindSmemPKfS0_iiPi, .Lfunc_end0-_Z14impalaFindSmemPKfS0_iiPi .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z14impalaFindSmemPKfS0_iiPi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z14impalaFindSmemPKfS0_iiPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0007e3bc_00000000-6_impalaFindSmem.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z42__device_stub__Z14impalaFindSmemPKfS0_iiPiPKfS0_iiPi .type _Z42__device_stub__Z14impalaFindSmemPKfS0_iiPiPKfS0_iiPi, @function _Z42__device_stub__Z14impalaFindSmemPKfS0_iiPiPKfS0_iiPi: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %r8, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z14impalaFindSmemPKfS0_iiPi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z42__device_stub__Z14impalaFindSmemPKfS0_iiPiPKfS0_iiPi, .-_Z42__device_stub__Z14impalaFindSmemPKfS0_iiPiPKfS0_iiPi .globl _Z14impalaFindSmemPKfS0_iiPi .type _Z14impalaFindSmemPKfS0_iiPi, @function _Z14impalaFindSmemPKfS0_iiPi: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z42__device_stub__Z14impalaFindSmemPKfS0_iiPiPKfS0_iiPi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z14impalaFindSmemPKfS0_iiPi, .-_Z14impalaFindSmemPKfS0_iiPi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z14impalaFindSmemPKfS0_iiPi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z14impalaFindSmemPKfS0_iiPi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "impalaFindSmem.hip" .globl _Z29__device_stub__impalaFindSmemPKfS0_iiPi # -- Begin function _Z29__device_stub__impalaFindSmemPKfS0_iiPi .p2align 4, 0x90 .type _Z29__device_stub__impalaFindSmemPKfS0_iiPi,@function _Z29__device_stub__impalaFindSmemPKfS0_iiPi: # @_Z29__device_stub__impalaFindSmemPKfS0_iiPi .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 4(%rsp) movl %ecx, (%rsp) movq %r8, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 4(%rsp), %rax movq %rax, 96(%rsp) movq %rsp, %rax movq %rax, 104(%rsp) leaq 56(%rsp), %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z14impalaFindSmemPKfS0_iiPi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z29__device_stub__impalaFindSmemPKfS0_iiPi, .Lfunc_end0-_Z29__device_stub__impalaFindSmemPKfS0_iiPi .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z14impalaFindSmemPKfS0_iiPi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z14impalaFindSmemPKfS0_iiPi,@object # @_Z14impalaFindSmemPKfS0_iiPi .section .rodata,"a",@progbits .globl _Z14impalaFindSmemPKfS0_iiPi .p2align 3, 0x0 _Z14impalaFindSmemPKfS0_iiPi: .quad _Z29__device_stub__impalaFindSmemPKfS0_iiPi .size _Z14impalaFindSmemPKfS0_iiPi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z14impalaFindSmemPKfS0_iiPi" .size .L__unnamed_1, 29 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z29__device_stub__impalaFindSmemPKfS0_iiPi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z14impalaFindSmemPKfS0_iiPi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
/* Copiar traspuesta de matriz h_a[F][C] en matriz h_b[C][F] aunque el n.º de hebras de los bloques no divida al n.º de componentes de las matrices */ #include <stdio.h> #define F 25 #define C 43 // matriz original de F filas y C columnas #define H 16 // bloques de H x H hebras (HxH<=512, capacidad cpto. 1.3) __global__ void trspta2(int *dev_a, int *dev_b, int filas, int cols) { __shared__ int s[H*H]; // variable compartida con tantos componentes como hebras tiene un bloque int bbx = blockIdx.x * blockDim.x; // = blockIdx.x * H int bby = blockIdx.y * blockDim.y; // = blockIdx.y * H int ix = bbx + threadIdx.x; int iy = bby + threadIdx.y; int aux; int idt = threadIdx.y * blockDim.x + threadIdx.x; // Identificador de hebra en un bloque int idttr = threadIdx.x * blockDim.y + threadIdx.y; if ((ix<cols)&&(iy<filas)) { /* Si S[H][H] es la matriz representada por s, queremos guardar en S la traspuesta de la submatriz de dev_a leída por el bloque de hebras (para, después, colocar S, en el lugar adecuado de dev_b) */ aux = iy*cols+ix; // Posición (iy,ix) en la matriz representada por dev_a /* Dentro de un bloque, cuando idt aumenta en 1 y threadIdx.y no cambia (threadIdx.x aumenta en 1), aux aumenta en 1. Esto ocurre en turnos de H veces seguidas ya que 0 <= threadIdx.x < blockDim.x = H. Por tanto, usando aux como índice, hay coalescencia en acceso a memoria global cada H accesos. Como la coalescencia máxima es de 16 accesos, conviene que H=16 */ s[idttr] = dev_a[aux]; /* S[threadIdx.x][threadIdx.y]= A[iy][ix] (str[idttr] representa S[threadIdx.x][threadIdx.y]) */ } /* Ahora debemos copiar s a su lugar en dev_b. La esquina superior izda. de s corresponde a la posición (ix,iy) en dev_b con threadIdx.x = threadIdx.y = 0 Es decir, ix*filas+iy con threadIdx.x = threadIdx.y = 0. Esto es, bbx * filas + bby */ int esqsupizda = bbx * filas + bby; /* Si pensamos s como matriz, un recorrido con el índice idt sería un recorrido por filas En S seleccionaríamos S[thr eadIdx.y][threadIdx.x] Por tanto, en dev_b el índice debe ser: esqsupizda + threadIdx.y * filas + threadIdx.x */ __syncthreads(); //Esperar a que todas las hebras lleguen if (((bbx+threadIdx.y)<cols) && ((bby+threadIdx.x)<filas)) dev_b[esqsupizda + threadIdx.y * filas + threadIdx.x] = s[idt]; /* Los límites del if cambian teniendo en cuenta la transposición realizada */ } int main(int argc, char** argv) { int h_a[F][C], h_b[C][F]; int *d_a, *d_b; int i, j, aux, size = F * C * sizeof(int); dim3 hebrasBloque(H, H); // bloques de H x H hebras int numBlf = (F+H-1)/H; // techo de F/H int numBlc = (C+H-1)/H; // techo de C/H dim3 numBloques(numBlc,numBlf); // reservar espacio en el device para d_a y d_b cudaMalloc((void**) &d_a, size); cudaMalloc((void**) &d_b, size); // dar valores a la matriz h_a en la CPU e imprimirlos printf("\nMatriz origen\n"); for (i=0; i<F; i++) { for (j=0; j<C; j++) { aux = i*C+j; h_a[i][j] = aux; printf("%d ", aux); } printf("\n"); } // copiar matriz h_a en d_a cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice); // llamar al kernel que obtiene en d_b la traspuesta de d_a trspta2<<<numBloques, hebrasBloque>>>(d_a, d_b, F, C); // copiar matriz d_b en h_b cudaMemcpy(h_b, d_b, size, cudaMemcpyDeviceToHost); // una vez que tenemos los resultados en el host, comprobamos que son correctos for (i=0; i<F; i++) for (j=0; j<C; j++) if (h_a[i][j]!= h_b[j][i]) {printf("error en componente %d %d de matriz de entrada \n", i,j); break;} // imprimir matriz resultado printf("\nMatriz resultado\n"); for (i=0; i<C; i++) { for (j=0; j<F; j++) printf("%d ", h_b[i][j]); printf("\n"); } printf("\n"); cudaFree(d_a); cudaFree(d_b); return 0; }
code for sm_80 Function : _Z7trspta2PiS_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */ /* 0x000e280000002100 */ /*0040*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */ /* 0x000e680000002200 */ /*0050*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */ /* 0x000e620000002600 */ /*0060*/ IMAD R0, R4, c[0x0][0x0], R6 ; /* 0x0000000004007a24 */ /* 0x001fca00078e0206 */ /*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */ /* 0x000fe20003f06270 */ /*0080*/ IMAD R3, R7, c[0x0][0x4], R9 ; /* 0x0000010007037a24 */ /* 0x002fca00078e0209 */ /*0090*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */ /* 0x000fda0000706670 */ /*00a0*/ @!P0 MOV R2, 0x4 ; /* 0x0000000400028802 */ /* 0x000fe20000000f00 */ /*00b0*/ @!P0 IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003038a24 */ /* 0x000fc800078e0200 */ /*00c0*/ @!P0 IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003028625 */ /* 0x000fcc00078e0202 */ /*00d0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000402028981 */ /* 0x000ea2000c1e1900 */ /*00e0*/ @!P0 IMAD R5, R6, c[0x0][0x4], R9.reuse ; /* 0x0000010006058a24 */ /* 0x100fe400078e0209 */ /*00f0*/ IMAD R0, R4, c[0x0][0x0], R9 ; /* 0x0000000004007a24 */ /* 0x000fe400078e0209 */ /*0100*/ IMAD R7, R7, c[0x0][0x4], R6.reuse ; /* 0x0000010007077a24 */ /* 0x100fe400078e0206 */ /*0110*/ IMAD R4, R9, c[0x0][0x0], R6 ; /* 0x0000000009047a24 */ /* 0x000fe200078e0206 */ /*0120*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */ /* 0x000fc80003f26070 */ /*0130*/ ISETP.GE.U32.OR P1, PT, R7, c[0x0][0x170], P1 ; /* 0x00005c0007007a0c */ /* 0x000fe20000f26470 */ /*0140*/ @!P0 STS [R5.X4], R2 ; /* 0x0000000205008388 */ /* 0x0041e80000004800 */ /*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000ff00000010000 */ /*0160*/ @P1 EXIT ; /* 0x000000000000194d */ /* 0x000fea0003800000 */ /*0170*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */ /* 0x001e220000004800 */ /*0180*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */ /* 0x000fe200000001ff */ /*0190*/ IMAD R2, R0, c[0x0][0x170], R7 ; /* 0x00005c0000027a24 */ /* 0x000fd200078e0207 */ /*01a0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */ /* 0x000fca00078e0003 */ /*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x001fe2000c101904 */ /*01c0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
/* Copiar traspuesta de matriz h_a[F][C] en matriz h_b[C][F] aunque el n.º de hebras de los bloques no divida al n.º de componentes de las matrices */ #include <stdio.h> #define F 25 #define C 43 // matriz original de F filas y C columnas #define H 16 // bloques de H x H hebras (HxH<=512, capacidad cpto. 1.3) __global__ void trspta2(int *dev_a, int *dev_b, int filas, int cols) { __shared__ int s[H*H]; // variable compartida con tantos componentes como hebras tiene un bloque int bbx = blockIdx.x * blockDim.x; // = blockIdx.x * H int bby = blockIdx.y * blockDim.y; // = blockIdx.y * H int ix = bbx + threadIdx.x; int iy = bby + threadIdx.y; int aux; int idt = threadIdx.y * blockDim.x + threadIdx.x; // Identificador de hebra en un bloque int idttr = threadIdx.x * blockDim.y + threadIdx.y; if ((ix<cols)&&(iy<filas)) { /* Si S[H][H] es la matriz representada por s, queremos guardar en S la traspuesta de la submatriz de dev_a leída por el bloque de hebras (para, después, colocar S, en el lugar adecuado de dev_b) */ aux = iy*cols+ix; // Posición (iy,ix) en la matriz representada por dev_a /* Dentro de un bloque, cuando idt aumenta en 1 y threadIdx.y no cambia (threadIdx.x aumenta en 1), aux aumenta en 1. Esto ocurre en turnos de H veces seguidas ya que 0 <= threadIdx.x < blockDim.x = H. Por tanto, usando aux como índice, hay coalescencia en acceso a memoria global cada H accesos. Como la coalescencia máxima es de 16 accesos, conviene que H=16 */ s[idttr] = dev_a[aux]; /* S[threadIdx.x][threadIdx.y]= A[iy][ix] (str[idttr] representa S[threadIdx.x][threadIdx.y]) */ } /* Ahora debemos copiar s a su lugar en dev_b. La esquina superior izda. de s corresponde a la posición (ix,iy) en dev_b con threadIdx.x = threadIdx.y = 0 Es decir, ix*filas+iy con threadIdx.x = threadIdx.y = 0. Esto es, bbx * filas + bby */ int esqsupizda = bbx * filas + bby; /* Si pensamos s como matriz, un recorrido con el índice idt sería un recorrido por filas En S seleccionaríamos S[thr eadIdx.y][threadIdx.x] Por tanto, en dev_b el índice debe ser: esqsupizda + threadIdx.y * filas + threadIdx.x */ __syncthreads(); //Esperar a que todas las hebras lleguen if (((bbx+threadIdx.y)<cols) && ((bby+threadIdx.x)<filas)) dev_b[esqsupizda + threadIdx.y * filas + threadIdx.x] = s[idt]; /* Los límites del if cambian teniendo en cuenta la transposición realizada */ } int main(int argc, char** argv) { int h_a[F][C], h_b[C][F]; int *d_a, *d_b; int i, j, aux, size = F * C * sizeof(int); dim3 hebrasBloque(H, H); // bloques de H x H hebras int numBlf = (F+H-1)/H; // techo de F/H int numBlc = (C+H-1)/H; // techo de C/H dim3 numBloques(numBlc,numBlf); // reservar espacio en el device para d_a y d_b cudaMalloc((void**) &d_a, size); cudaMalloc((void**) &d_b, size); // dar valores a la matriz h_a en la CPU e imprimirlos printf("\nMatriz origen\n"); for (i=0; i<F; i++) { for (j=0; j<C; j++) { aux = i*C+j; h_a[i][j] = aux; printf("%d ", aux); } printf("\n"); } // copiar matriz h_a en d_a cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice); // llamar al kernel que obtiene en d_b la traspuesta de d_a trspta2<<<numBloques, hebrasBloque>>>(d_a, d_b, F, C); // copiar matriz d_b en h_b cudaMemcpy(h_b, d_b, size, cudaMemcpyDeviceToHost); // una vez que tenemos los resultados en el host, comprobamos que son correctos for (i=0; i<F; i++) for (j=0; j<C; j++) if (h_a[i][j]!= h_b[j][i]) {printf("error en componente %d %d de matriz de entrada \n", i,j); break;} // imprimir matriz resultado printf("\nMatriz resultado\n"); for (i=0; i<C; i++) { for (j=0; j<F; j++) printf("%d ", h_b[i][j]); printf("\n"); } printf("\n"); cudaFree(d_a); cudaFree(d_b); return 0; }
.file "tmpxft_0016ab39_00000000-6_traspuesta2.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z30__device_stub__Z7trspta2PiS_iiPiS_ii .type _Z30__device_stub__Z7trspta2PiS_iiPiS_ii, @function _Z30__device_stub__Z7trspta2PiS_iiPiS_ii: .LFB2082: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7trspta2PiS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z30__device_stub__Z7trspta2PiS_iiPiS_ii, .-_Z30__device_stub__Z7trspta2PiS_iiPiS_ii .globl _Z7trspta2PiS_ii .type _Z7trspta2PiS_ii, @function _Z7trspta2PiS_ii: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z7trspta2PiS_iiPiS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z7trspta2PiS_ii, .-_Z7trspta2PiS_ii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "\nMatriz origen\n" .LC1: .string "%d " .LC2: .string "\n" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC3: .string "error en componente %d %d de matriz de entrada \n" .section .rodata.str1.1 .LC4: .string "\nMatriz resultado\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $4096, %rsp .cfi_def_cfa_offset 4152 orq $0, (%rsp) subq $4096, %rsp .cfi_def_cfa_offset 8248 orq $0, (%rsp) subq $488, %rsp .cfi_def_cfa_offset 8736 movq %fs:40, %rax movq %rax, 8664(%rsp) xorl %eax, %eax movl $16, 24(%rsp) movl $16, 28(%rsp) movl $1, 32(%rsp) movl $3, 36(%rsp) movl $2, 40(%rsp) movl $1, 44(%rsp) leaq 8(%rsp), %rdi movl $4300, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4300, %esi call cudaMalloc@PLT leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 48(%rsp), %r14 movq %r14, %r15 movl $43, %r12d leaq .LC1(%rip), %r13 .L12: leal -43(%r12), %ebx movq %r15, %rbp .L13: movl %ebx, 0(%rbp) movl %ebx, %edx movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addl $1, %ebx addq $4, %rbp cmpl %r12d, %ebx jne .L13 leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $172, %r15 addl $43, %r12d cmpl $1118, %r12d jne .L12 leaq 48(%rsp), %rsi movl $1, %ecx movl $4300, %edx movq 8(%rsp), %rdi call cudaMemcpy@PLT movl 32(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 24(%rsp), %rdx movq 36(%rsp), %rdi movl 44(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L29 .L15: leaq 4352(%rsp), %rdi movl $2, %ecx movl $4300, %edx movq 16(%rsp), %rsi call cudaMemcpy@PLT movl $0, %ebx leaq .LC3(%rip), %rbp jmp .L16 .L29: movl $43, %ecx movl $25, %edx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z30__device_stub__Z7trspta2PiS_iiPiS_ii jmp .L15 .L30: movl %ebx, %edx movq %rbp, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L18: addq $1, %rbx addq $172, %r14 cmpq $25, %rbx je .L20 .L16: leaq 4352(%rsp), %r13 leaq 0(%r13,%rbx,4), %rax movl $0, %ecx .L19: movl (%rax), %esi cmpl %esi, (%r14,%rcx,4) jne .L30 addq $1, %rcx addq $100, %rax cmpq $43, %rcx jne .L19 jmp .L18 .L20: leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 100(%r13), %rbp addq $4400, %r13 leaq .LC1(%rip), %r12 leaq .LC2(%rip), %r14 jmp .L21 .L31: movq %r14, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $100, %rbp cmpq %r13, %rbp je .L23 .L21: leaq -100(%rbp), %rbx .L22: movl (%rbx), %edx movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L22 jmp .L31 .L23: leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 8664(%rsp), %rax subq %fs:40, %rax jne .L32 movl $0, %eax addq $8680, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L32: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC5: .string "_Z7trspta2PiS_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _Z7trspta2PiS_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
/* Copiar traspuesta de matriz h_a[F][C] en matriz h_b[C][F] aunque el n.º de hebras de los bloques no divida al n.º de componentes de las matrices */ #include <stdio.h> #define F 25 #define C 43 // matriz original de F filas y C columnas #define H 16 // bloques de H x H hebras (HxH<=512, capacidad cpto. 1.3) __global__ void trspta2(int *dev_a, int *dev_b, int filas, int cols) { __shared__ int s[H*H]; // variable compartida con tantos componentes como hebras tiene un bloque int bbx = blockIdx.x * blockDim.x; // = blockIdx.x * H int bby = blockIdx.y * blockDim.y; // = blockIdx.y * H int ix = bbx + threadIdx.x; int iy = bby + threadIdx.y; int aux; int idt = threadIdx.y * blockDim.x + threadIdx.x; // Identificador de hebra en un bloque int idttr = threadIdx.x * blockDim.y + threadIdx.y; if ((ix<cols)&&(iy<filas)) { /* Si S[H][H] es la matriz representada por s, queremos guardar en S la traspuesta de la submatriz de dev_a leída por el bloque de hebras (para, después, colocar S, en el lugar adecuado de dev_b) */ aux = iy*cols+ix; // Posición (iy,ix) en la matriz representada por dev_a /* Dentro de un bloque, cuando idt aumenta en 1 y threadIdx.y no cambia (threadIdx.x aumenta en 1), aux aumenta en 1. Esto ocurre en turnos de H veces seguidas ya que 0 <= threadIdx.x < blockDim.x = H. Por tanto, usando aux como índice, hay coalescencia en acceso a memoria global cada H accesos. Como la coalescencia máxima es de 16 accesos, conviene que H=16 */ s[idttr] = dev_a[aux]; /* S[threadIdx.x][threadIdx.y]= A[iy][ix] (str[idttr] representa S[threadIdx.x][threadIdx.y]) */ } /* Ahora debemos copiar s a su lugar en dev_b. La esquina superior izda. de s corresponde a la posición (ix,iy) en dev_b con threadIdx.x = threadIdx.y = 0 Es decir, ix*filas+iy con threadIdx.x = threadIdx.y = 0. Esto es, bbx * filas + bby */ int esqsupizda = bbx * filas + bby; /* Si pensamos s como matriz, un recorrido con el índice idt sería un recorrido por filas En S seleccionaríamos S[thr eadIdx.y][threadIdx.x] Por tanto, en dev_b el índice debe ser: esqsupizda + threadIdx.y * filas + threadIdx.x */ __syncthreads(); //Esperar a que todas las hebras lleguen if (((bbx+threadIdx.y)<cols) && ((bby+threadIdx.x)<filas)) dev_b[esqsupizda + threadIdx.y * filas + threadIdx.x] = s[idt]; /* Los límites del if cambian teniendo en cuenta la transposición realizada */ } int main(int argc, char** argv) { int h_a[F][C], h_b[C][F]; int *d_a, *d_b; int i, j, aux, size = F * C * sizeof(int); dim3 hebrasBloque(H, H); // bloques de H x H hebras int numBlf = (F+H-1)/H; // techo de F/H int numBlc = (C+H-1)/H; // techo de C/H dim3 numBloques(numBlc,numBlf); // reservar espacio en el device para d_a y d_b cudaMalloc((void**) &d_a, size); cudaMalloc((void**) &d_b, size); // dar valores a la matriz h_a en la CPU e imprimirlos printf("\nMatriz origen\n"); for (i=0; i<F; i++) { for (j=0; j<C; j++) { aux = i*C+j; h_a[i][j] = aux; printf("%d ", aux); } printf("\n"); } // copiar matriz h_a en d_a cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice); // llamar al kernel que obtiene en d_b la traspuesta de d_a trspta2<<<numBloques, hebrasBloque>>>(d_a, d_b, F, C); // copiar matriz d_b en h_b cudaMemcpy(h_b, d_b, size, cudaMemcpyDeviceToHost); // una vez que tenemos los resultados en el host, comprobamos que son correctos for (i=0; i<F; i++) for (j=0; j<C; j++) if (h_a[i][j]!= h_b[j][i]) {printf("error en componente %d %d de matriz de entrada \n", i,j); break;} // imprimir matriz resultado printf("\nMatriz resultado\n"); for (i=0; i<C; i++) { for (j=0; j<F; j++) printf("%d ", h_b[i][j]); printf("\n"); } printf("\n"); cudaFree(d_a); cudaFree(d_b); return 0; }
/* Copiar traspuesta de matriz h_a[F][C] en matriz h_b[C][F] aunque el n.º de hebras de los bloques no divida al n.º de componentes de las matrices */ #include <hip/hip_runtime.h> #include <stdio.h> #define F 25 #define C 43 // matriz original de F filas y C columnas #define H 16 // bloques de H x H hebras (HxH<=512, capacidad cpto. 1.3) __global__ void trspta2(int *dev_a, int *dev_b, int filas, int cols) { __shared__ int s[H*H]; // variable compartida con tantos componentes como hebras tiene un bloque int bbx = blockIdx.x * blockDim.x; // = blockIdx.x * H int bby = blockIdx.y * blockDim.y; // = blockIdx.y * H int ix = bbx + threadIdx.x; int iy = bby + threadIdx.y; int aux; int idt = threadIdx.y * blockDim.x + threadIdx.x; // Identificador de hebra en un bloque int idttr = threadIdx.x * blockDim.y + threadIdx.y; if ((ix<cols)&&(iy<filas)) { /* Si S[H][H] es la matriz representada por s, queremos guardar en S la traspuesta de la submatriz de dev_a leída por el bloque de hebras (para, después, colocar S, en el lugar adecuado de dev_b) */ aux = iy*cols+ix; // Posición (iy,ix) en la matriz representada por dev_a /* Dentro de un bloque, cuando idt aumenta en 1 y threadIdx.y no cambia (threadIdx.x aumenta en 1), aux aumenta en 1. Esto ocurre en turnos de H veces seguidas ya que 0 <= threadIdx.x < blockDim.x = H. Por tanto, usando aux como índice, hay coalescencia en acceso a memoria global cada H accesos. Como la coalescencia máxima es de 16 accesos, conviene que H=16 */ s[idttr] = dev_a[aux]; /* S[threadIdx.x][threadIdx.y]= A[iy][ix] (str[idttr] representa S[threadIdx.x][threadIdx.y]) */ } /* Ahora debemos copiar s a su lugar en dev_b. La esquina superior izda. de s corresponde a la posición (ix,iy) en dev_b con threadIdx.x = threadIdx.y = 0 Es decir, ix*filas+iy con threadIdx.x = threadIdx.y = 0. Esto es, bbx * filas + bby */ int esqsupizda = bbx * filas + bby; /* Si pensamos s como matriz, un recorrido con el índice idt sería un recorrido por filas En S seleccionaríamos S[thr eadIdx.y][threadIdx.x] Por tanto, en dev_b el índice debe ser: esqsupizda + threadIdx.y * filas + threadIdx.x */ __syncthreads(); //Esperar a que todas las hebras lleguen if (((bbx+threadIdx.y)<cols) && ((bby+threadIdx.x)<filas)) dev_b[esqsupizda + threadIdx.y * filas + threadIdx.x] = s[idt]; /* Los límites del if cambian teniendo en cuenta la transposición realizada */ } int main(int argc, char** argv) { int h_a[F][C], h_b[C][F]; int *d_a, *d_b; int i, j, aux, size = F * C * sizeof(int); dim3 hebrasBloque(H, H); // bloques de H x H hebras int numBlf = (F+H-1)/H; // techo de F/H int numBlc = (C+H-1)/H; // techo de C/H dim3 numBloques(numBlc,numBlf); // reservar espacio en el device para d_a y d_b hipMalloc((void**) &d_a, size); hipMalloc((void**) &d_b, size); // dar valores a la matriz h_a en la CPU e imprimirlos printf("\nMatriz origen\n"); for (i=0; i<F; i++) { for (j=0; j<C; j++) { aux = i*C+j; h_a[i][j] = aux; printf("%d ", aux); } printf("\n"); } // copiar matriz h_a en d_a hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice); // llamar al kernel que obtiene en d_b la traspuesta de d_a trspta2<<<numBloques, hebrasBloque>>>(d_a, d_b, F, C); // copiar matriz d_b en h_b hipMemcpy(h_b, d_b, size, hipMemcpyDeviceToHost); // una vez que tenemos los resultados en el host, comprobamos que son correctos for (i=0; i<F; i++) for (j=0; j<C; j++) if (h_a[i][j]!= h_b[j][i]) {printf("error en componente %d %d de matriz de entrada \n", i,j); break;} // imprimir matriz resultado printf("\nMatriz resultado\n"); for (i=0; i<C; i++) { for (j=0; j<F; j++) printf("%d ", h_b[i][j]); printf("\n"); } printf("\n"); hipFree(d_a); hipFree(d_b); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
/* Copiar traspuesta de matriz h_a[F][C] en matriz h_b[C][F] aunque el n.º de hebras de los bloques no divida al n.º de componentes de las matrices */ #include <hip/hip_runtime.h> #include <stdio.h> #define F 25 #define C 43 // matriz original de F filas y C columnas #define H 16 // bloques de H x H hebras (HxH<=512, capacidad cpto. 1.3) __global__ void trspta2(int *dev_a, int *dev_b, int filas, int cols) { __shared__ int s[H*H]; // variable compartida con tantos componentes como hebras tiene un bloque int bbx = blockIdx.x * blockDim.x; // = blockIdx.x * H int bby = blockIdx.y * blockDim.y; // = blockIdx.y * H int ix = bbx + threadIdx.x; int iy = bby + threadIdx.y; int aux; int idt = threadIdx.y * blockDim.x + threadIdx.x; // Identificador de hebra en un bloque int idttr = threadIdx.x * blockDim.y + threadIdx.y; if ((ix<cols)&&(iy<filas)) { /* Si S[H][H] es la matriz representada por s, queremos guardar en S la traspuesta de la submatriz de dev_a leída por el bloque de hebras (para, después, colocar S, en el lugar adecuado de dev_b) */ aux = iy*cols+ix; // Posición (iy,ix) en la matriz representada por dev_a /* Dentro de un bloque, cuando idt aumenta en 1 y threadIdx.y no cambia (threadIdx.x aumenta en 1), aux aumenta en 1. Esto ocurre en turnos de H veces seguidas ya que 0 <= threadIdx.x < blockDim.x = H. Por tanto, usando aux como índice, hay coalescencia en acceso a memoria global cada H accesos. Como la coalescencia máxima es de 16 accesos, conviene que H=16 */ s[idttr] = dev_a[aux]; /* S[threadIdx.x][threadIdx.y]= A[iy][ix] (str[idttr] representa S[threadIdx.x][threadIdx.y]) */ } /* Ahora debemos copiar s a su lugar en dev_b. La esquina superior izda. de s corresponde a la posición (ix,iy) en dev_b con threadIdx.x = threadIdx.y = 0 Es decir, ix*filas+iy con threadIdx.x = threadIdx.y = 0. Esto es, bbx * filas + bby */ int esqsupizda = bbx * filas + bby; /* Si pensamos s como matriz, un recorrido con el índice idt sería un recorrido por filas En S seleccionaríamos S[thr eadIdx.y][threadIdx.x] Por tanto, en dev_b el índice debe ser: esqsupizda + threadIdx.y * filas + threadIdx.x */ __syncthreads(); //Esperar a que todas las hebras lleguen if (((bbx+threadIdx.y)<cols) && ((bby+threadIdx.x)<filas)) dev_b[esqsupizda + threadIdx.y * filas + threadIdx.x] = s[idt]; /* Los límites del if cambian teniendo en cuenta la transposición realizada */ } int main(int argc, char** argv) { int h_a[F][C], h_b[C][F]; int *d_a, *d_b; int i, j, aux, size = F * C * sizeof(int); dim3 hebrasBloque(H, H); // bloques de H x H hebras int numBlf = (F+H-1)/H; // techo de F/H int numBlc = (C+H-1)/H; // techo de C/H dim3 numBloques(numBlc,numBlf); // reservar espacio en el device para d_a y d_b hipMalloc((void**) &d_a, size); hipMalloc((void**) &d_b, size); // dar valores a la matriz h_a en la CPU e imprimirlos printf("\nMatriz origen\n"); for (i=0; i<F; i++) { for (j=0; j<C; j++) { aux = i*C+j; h_a[i][j] = aux; printf("%d ", aux); } printf("\n"); } // copiar matriz h_a en d_a hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice); // llamar al kernel que obtiene en d_b la traspuesta de d_a trspta2<<<numBloques, hebrasBloque>>>(d_a, d_b, F, C); // copiar matriz d_b en h_b hipMemcpy(h_b, d_b, size, hipMemcpyDeviceToHost); // una vez que tenemos los resultados en el host, comprobamos que son correctos for (i=0; i<F; i++) for (j=0; j<C; j++) if (h_a[i][j]!= h_b[j][i]) {printf("error en componente %d %d de matriz de entrada \n", i,j); break;} // imprimir matriz resultado printf("\nMatriz resultado\n"); for (i=0; i<C; i++) { for (j=0; j<F; j++) printf("%d ", h_b[i][j]); printf("\n"); } printf("\n"); hipFree(d_a); hipFree(d_b); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z7trspta2PiS_ii .globl _Z7trspta2PiS_ii .p2align 8 .type _Z7trspta2PiS_ii,@function _Z7trspta2PiS_ii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b64 s[4:5], s[0:1], 0x10 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v2, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s2, 0xffff s_lshr_b32 s6, s2, 16 s_mul_i32 s14, s14, s3 s_mul_i32 s15, s15, s6 v_add_nc_u32_e32 v0, s14, v1 v_add_nc_u32_e32 v3, s15, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s5, v0 v_cmp_gt_i32_e64 s2, s4, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s7, vcc_lo, s2 s_and_saveexec_b32 s2, s7 s_cbranch_execz .LBB0_2 s_load_b64 s[8:9], s[0:1], 0x0 v_mad_u64_u32 v[4:5], null, v3, s5, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v5, 31, v4 v_lshlrev_b64 v[3:4], 2, v[4:5] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s8, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo global_load_b32 v0, v[3:4], off v_mul_u32_u24_e32 v3, s6, v1 s_delay_alu instid0(VALU_DEP_1) v_add_lshl_u32 v3, v3, v2, 2 s_waitcnt vmcnt(0) ds_store_b32 v3, v0 .LBB0_2: s_or_b32 exec_lo, exec_lo, s2 v_add_nc_u32_e32 v0, s14, v2 v_add_nc_u32_e32 v3, s15, v1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmp_gt_u32_e32 vcc_lo, s5, v0 v_cmp_gt_u32_e64 s2, s4, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_4 v_mul_u32_u24_e32 v2, s3, v2 s_load_b64 s[0:1], s[0:1], 0x8 v_mul_lo_u32 v0, v0, s4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_lshl_u32 v2, v2, v1, 2 v_add3_u32 v0, s15, v1, v0 ds_load_b32 v2, v2 v_mov_b32_e32 v1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7trspta2PiS_ii .amdhsa_group_segment_fixed_size 1024 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z7trspta2PiS_ii, .Lfunc_end0-_Z7trspta2PiS_ii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 1024 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7trspta2PiS_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z7trspta2PiS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
/* Copiar traspuesta de matriz h_a[F][C] en matriz h_b[C][F] aunque el n.º de hebras de los bloques no divida al n.º de componentes de las matrices */ #include <hip/hip_runtime.h> #include <stdio.h> #define F 25 #define C 43 // matriz original de F filas y C columnas #define H 16 // bloques de H x H hebras (HxH<=512, capacidad cpto. 1.3) __global__ void trspta2(int *dev_a, int *dev_b, int filas, int cols) { __shared__ int s[H*H]; // variable compartida con tantos componentes como hebras tiene un bloque int bbx = blockIdx.x * blockDim.x; // = blockIdx.x * H int bby = blockIdx.y * blockDim.y; // = blockIdx.y * H int ix = bbx + threadIdx.x; int iy = bby + threadIdx.y; int aux; int idt = threadIdx.y * blockDim.x + threadIdx.x; // Identificador de hebra en un bloque int idttr = threadIdx.x * blockDim.y + threadIdx.y; if ((ix<cols)&&(iy<filas)) { /* Si S[H][H] es la matriz representada por s, queremos guardar en S la traspuesta de la submatriz de dev_a leída por el bloque de hebras (para, después, colocar S, en el lugar adecuado de dev_b) */ aux = iy*cols+ix; // Posición (iy,ix) en la matriz representada por dev_a /* Dentro de un bloque, cuando idt aumenta en 1 y threadIdx.y no cambia (threadIdx.x aumenta en 1), aux aumenta en 1. Esto ocurre en turnos de H veces seguidas ya que 0 <= threadIdx.x < blockDim.x = H. Por tanto, usando aux como índice, hay coalescencia en acceso a memoria global cada H accesos. Como la coalescencia máxima es de 16 accesos, conviene que H=16 */ s[idttr] = dev_a[aux]; /* S[threadIdx.x][threadIdx.y]= A[iy][ix] (str[idttr] representa S[threadIdx.x][threadIdx.y]) */ } /* Ahora debemos copiar s a su lugar en dev_b. La esquina superior izda. de s corresponde a la posición (ix,iy) en dev_b con threadIdx.x = threadIdx.y = 0 Es decir, ix*filas+iy con threadIdx.x = threadIdx.y = 0. Esto es, bbx * filas + bby */ int esqsupizda = bbx * filas + bby; /* Si pensamos s como matriz, un recorrido con el índice idt sería un recorrido por filas En S seleccionaríamos S[thr eadIdx.y][threadIdx.x] Por tanto, en dev_b el índice debe ser: esqsupizda + threadIdx.y * filas + threadIdx.x */ __syncthreads(); //Esperar a que todas las hebras lleguen if (((bbx+threadIdx.y)<cols) && ((bby+threadIdx.x)<filas)) dev_b[esqsupizda + threadIdx.y * filas + threadIdx.x] = s[idt]; /* Los límites del if cambian teniendo en cuenta la transposición realizada */ } int main(int argc, char** argv) { int h_a[F][C], h_b[C][F]; int *d_a, *d_b; int i, j, aux, size = F * C * sizeof(int); dim3 hebrasBloque(H, H); // bloques de H x H hebras int numBlf = (F+H-1)/H; // techo de F/H int numBlc = (C+H-1)/H; // techo de C/H dim3 numBloques(numBlc,numBlf); // reservar espacio en el device para d_a y d_b hipMalloc((void**) &d_a, size); hipMalloc((void**) &d_b, size); // dar valores a la matriz h_a en la CPU e imprimirlos printf("\nMatriz origen\n"); for (i=0; i<F; i++) { for (j=0; j<C; j++) { aux = i*C+j; h_a[i][j] = aux; printf("%d ", aux); } printf("\n"); } // copiar matriz h_a en d_a hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice); // llamar al kernel que obtiene en d_b la traspuesta de d_a trspta2<<<numBloques, hebrasBloque>>>(d_a, d_b, F, C); // copiar matriz d_b en h_b hipMemcpy(h_b, d_b, size, hipMemcpyDeviceToHost); // una vez que tenemos los resultados en el host, comprobamos que son correctos for (i=0; i<F; i++) for (j=0; j<C; j++) if (h_a[i][j]!= h_b[j][i]) {printf("error en componente %d %d de matriz de entrada \n", i,j); break;} // imprimir matriz resultado printf("\nMatriz resultado\n"); for (i=0; i<C; i++) { for (j=0; j<F; j++) printf("%d ", h_b[i][j]); printf("\n"); } printf("\n"); hipFree(d_a); hipFree(d_b); return 0; }
.text .file "traspuesta2.hip" .globl _Z22__device_stub__trspta2PiS_ii # -- Begin function _Z22__device_stub__trspta2PiS_ii .p2align 4, 0x90 .type _Z22__device_stub__trspta2PiS_ii,@function _Z22__device_stub__trspta2PiS_ii: # @_Z22__device_stub__trspta2PiS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7trspta2PiS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z22__device_stub__trspta2PiS_ii, .Lfunc_end0-_Z22__device_stub__trspta2PiS_ii .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $8712, %rsp # imm = 0x2208 .cfi_def_cfa_offset 8752 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 16(%rsp), %rdi movl $4300, %esi # imm = 0x10CC callq hipMalloc leaq 8(%rsp), %rdi movl $4300, %esi # imm = 0x10CC callq hipMalloc movl $.Lstr, %edi callq puts@PLT xorl %r14d, %r14d xorl %r15d, %r15d .p2align 4, 0x90 .LBB1_1: # %.preheader48 # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 movl $43, %r12d movq %r14, %rbx .p2align 4, 0x90 .LBB1_2: # Parent Loop BB1_1 Depth=1 # => This Inner Loop Header: Depth=2 movl %ebx, 4400(%rsp,%rbx,4) movl $.L.str.1, %edi movl %ebx, %esi xorl %eax, %eax callq printf incq %rbx decq %r12 jne .LBB1_2 # %bb.3: # in Loop: Header=BB1_1 Depth=1 movl $10, %edi callq putchar@PLT incq %r15 addq $43, %r14 cmpq $25, %r15 jne .LBB1_1 # %bb.4: movq 16(%rsp), %rdi leaq 4400(%rsp), %rbx movl $4300, %edx # imm = 0x10CC movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movabsq $8589934595, %rdi # imm = 0x200000003 movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_6 # %bb.5: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movl $25, 28(%rsp) movl $43, 24(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 28(%rsp), %rax movq %rax, 112(%rsp) leaq 24(%rsp), %rax movq %rax, 120(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z7trspta2PiS_ii, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_6: movq 8(%rsp), %rsi leaq 96(%rsp), %r14 movl $4300, %edx # imm = 0x10CC movq %r14, %rdi movl $2, %ecx callq hipMemcpy xorl %r15d, %r15d jmp .LBB1_7 .p2align 4, 0x90 .LBB1_9: # in Loop: Header=BB1_7 Depth=1 movl $.L.str.3, %edi movl %r15d, %esi # kill: def $edx killed $edx killed $rdx xorl %eax, %eax callq printf .LBB1_11: # %.loopexit # in Loop: Header=BB1_7 Depth=1 incq %r15 addq $172, %rbx addq $4, %r14 cmpq $25, %r15 je .LBB1_12 .LBB1_7: # %.preheader47 # =>This Loop Header: Depth=1 # Child Loop BB1_8 Depth 2 movq %r14, %rax xorl %edx, %edx .p2align 4, 0x90 .LBB1_8: # Parent Loop BB1_7 Depth=1 # => This Inner Loop Header: Depth=2 movl (%rbx,%rdx,4), %ecx cmpl (%rax), %ecx jne .LBB1_9 # %bb.10: # in Loop: Header=BB1_8 Depth=2 incq %rdx addq $100, %rax cmpq $43, %rdx jne .LBB1_8 jmp .LBB1_11 .LBB1_12: movl $.Lstr.1, %edi callq puts@PLT leaq 96(%rsp), %rbx xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_13: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_14 Depth 2 xorl %r15d, %r15d .p2align 4, 0x90 .LBB1_14: # Parent Loop BB1_13 Depth=1 # => This Inner Loop Header: Depth=2 movl (%rbx,%r15,4), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r15 cmpq $25, %r15 jne .LBB1_14 # %bb.15: # in Loop: Header=BB1_13 Depth=1 movl $10, %edi callq putchar@PLT incq %r14 addq $100, %rbx cmpq $43, %r14 jne .LBB1_13 # %bb.16: movl $10, %edi callq putchar@PLT movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax addq $8712, %rsp # imm = 0x2208 .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7trspta2PiS_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z7trspta2PiS_ii,@object # @_Z7trspta2PiS_ii .section .rodata,"a",@progbits .globl _Z7trspta2PiS_ii .p2align 3, 0x0 _Z7trspta2PiS_ii: .quad _Z22__device_stub__trspta2PiS_ii .size _Z7trspta2PiS_ii, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "%d " .size .L.str.1, 4 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "error en componente %d %d de matriz de entrada \n" .size .L.str.3, 49 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z7trspta2PiS_ii" .size .L__unnamed_1, 17 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "\nMatriz origen" .size .Lstr, 15 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "\nMatriz resultado" .size .Lstr.1, 18 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__trspta2PiS_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7trspta2PiS_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z7trspta2PiS_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */ /* 0x000e280000002100 */ /*0040*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */ /* 0x000e680000002200 */ /*0050*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */ /* 0x000e620000002600 */ /*0060*/ IMAD R0, R4, c[0x0][0x0], R6 ; /* 0x0000000004007a24 */ /* 0x001fca00078e0206 */ /*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */ /* 0x000fe20003f06270 */ /*0080*/ IMAD R3, R7, c[0x0][0x4], R9 ; /* 0x0000010007037a24 */ /* 0x002fca00078e0209 */ /*0090*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */ /* 0x000fda0000706670 */ /*00a0*/ @!P0 MOV R2, 0x4 ; /* 0x0000000400028802 */ /* 0x000fe20000000f00 */ /*00b0*/ @!P0 IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003038a24 */ /* 0x000fc800078e0200 */ /*00c0*/ @!P0 IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003028625 */ /* 0x000fcc00078e0202 */ /*00d0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000402028981 */ /* 0x000ea2000c1e1900 */ /*00e0*/ @!P0 IMAD R5, R6, c[0x0][0x4], R9.reuse ; /* 0x0000010006058a24 */ /* 0x100fe400078e0209 */ /*00f0*/ IMAD R0, R4, c[0x0][0x0], R9 ; /* 0x0000000004007a24 */ /* 0x000fe400078e0209 */ /*0100*/ IMAD R7, R7, c[0x0][0x4], R6.reuse ; /* 0x0000010007077a24 */ /* 0x100fe400078e0206 */ /*0110*/ IMAD R4, R9, c[0x0][0x0], R6 ; /* 0x0000000009047a24 */ /* 0x000fe200078e0206 */ /*0120*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */ /* 0x000fc80003f26070 */ /*0130*/ ISETP.GE.U32.OR P1, PT, R7, c[0x0][0x170], P1 ; /* 0x00005c0007007a0c */ /* 0x000fe20000f26470 */ /*0140*/ @!P0 STS [R5.X4], R2 ; /* 0x0000000205008388 */ /* 0x0041e80000004800 */ /*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000ff00000010000 */ /*0160*/ @P1 EXIT ; /* 0x000000000000194d */ /* 0x000fea0003800000 */ /*0170*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */ /* 0x001e220000004800 */ /*0180*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */ /* 0x000fe200000001ff */ /*0190*/ IMAD R2, R0, c[0x0][0x170], R7 ; /* 0x00005c0000027a24 */ /* 0x000fd200078e0207 */ /*01a0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */ /* 0x000fca00078e0003 */ /*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x001fe2000c101904 */ /*01c0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z7trspta2PiS_ii .globl _Z7trspta2PiS_ii .p2align 8 .type _Z7trspta2PiS_ii,@function _Z7trspta2PiS_ii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x24 s_load_b64 s[4:5], s[0:1], 0x10 v_and_b32_e32 v1, 0x3ff, v0 v_bfe_u32 v2, v0, 10, 10 s_waitcnt lgkmcnt(0) s_and_b32 s3, s2, 0xffff s_lshr_b32 s6, s2, 16 s_mul_i32 s14, s14, s3 s_mul_i32 s15, s15, s6 v_add_nc_u32_e32 v0, s14, v1 v_add_nc_u32_e32 v3, s15, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s5, v0 v_cmp_gt_i32_e64 s2, s4, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s7, vcc_lo, s2 s_and_saveexec_b32 s2, s7 s_cbranch_execz .LBB0_2 s_load_b64 s[8:9], s[0:1], 0x0 v_mad_u64_u32 v[4:5], null, v3, s5, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v5, 31, v4 v_lshlrev_b64 v[3:4], 2, v[4:5] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v3, vcc_lo, s8, v3 v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo global_load_b32 v0, v[3:4], off v_mul_u32_u24_e32 v3, s6, v1 s_delay_alu instid0(VALU_DEP_1) v_add_lshl_u32 v3, v3, v2, 2 s_waitcnt vmcnt(0) ds_store_b32 v3, v0 .LBB0_2: s_or_b32 exec_lo, exec_lo, s2 v_add_nc_u32_e32 v0, s14, v2 v_add_nc_u32_e32 v3, s15, v1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv v_cmp_gt_u32_e32 vcc_lo, s5, v0 v_cmp_gt_u32_e64 s2, s4, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s5, s2 s_cbranch_execz .LBB0_4 v_mul_u32_u24_e32 v2, s3, v2 s_load_b64 s[0:1], s[0:1], 0x8 v_mul_lo_u32 v0, v0, s4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_lshl_u32 v2, v2, v1, 2 v_add3_u32 v0, s15, v1, v0 ds_load_b32 v2, v2 v_mov_b32_e32 v1, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v2, off .LBB0_4: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z7trspta2PiS_ii .amdhsa_group_segment_fixed_size 1024 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z7trspta2PiS_ii, .Lfunc_end0-_Z7trspta2PiS_ii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 1024 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z7trspta2PiS_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z7trspta2PiS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0016ab39_00000000-6_traspuesta2.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z30__device_stub__Z7trspta2PiS_iiPiS_ii .type _Z30__device_stub__Z7trspta2PiS_iiPiS_ii, @function _Z30__device_stub__Z7trspta2PiS_iiPiS_ii: .LFB2082: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7trspta2PiS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z30__device_stub__Z7trspta2PiS_iiPiS_ii, .-_Z30__device_stub__Z7trspta2PiS_iiPiS_ii .globl _Z7trspta2PiS_ii .type _Z7trspta2PiS_ii, @function _Z7trspta2PiS_ii: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z30__device_stub__Z7trspta2PiS_iiPiS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z7trspta2PiS_ii, .-_Z7trspta2PiS_ii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "\nMatriz origen\n" .LC1: .string "%d " .LC2: .string "\n" .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC3: .string "error en componente %d %d de matriz de entrada \n" .section .rodata.str1.1 .LC4: .string "\nMatriz resultado\n" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $4096, %rsp .cfi_def_cfa_offset 4152 orq $0, (%rsp) subq $4096, %rsp .cfi_def_cfa_offset 8248 orq $0, (%rsp) subq $488, %rsp .cfi_def_cfa_offset 8736 movq %fs:40, %rax movq %rax, 8664(%rsp) xorl %eax, %eax movl $16, 24(%rsp) movl $16, 28(%rsp) movl $1, 32(%rsp) movl $3, 36(%rsp) movl $2, 40(%rsp) movl $1, 44(%rsp) leaq 8(%rsp), %rdi movl $4300, %esi call cudaMalloc@PLT leaq 16(%rsp), %rdi movl $4300, %esi call cudaMalloc@PLT leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 48(%rsp), %r14 movq %r14, %r15 movl $43, %r12d leaq .LC1(%rip), %r13 .L12: leal -43(%r12), %ebx movq %r15, %rbp .L13: movl %ebx, 0(%rbp) movl %ebx, %edx movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addl $1, %ebx addq $4, %rbp cmpl %r12d, %ebx jne .L13 leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $172, %r15 addl $43, %r12d cmpl $1118, %r12d jne .L12 leaq 48(%rsp), %rsi movl $1, %ecx movl $4300, %edx movq 8(%rsp), %rdi call cudaMemcpy@PLT movl 32(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 24(%rsp), %rdx movq 36(%rsp), %rdi movl 44(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L29 .L15: leaq 4352(%rsp), %rdi movl $2, %ecx movl $4300, %edx movq 16(%rsp), %rsi call cudaMemcpy@PLT movl $0, %ebx leaq .LC3(%rip), %rbp jmp .L16 .L29: movl $43, %ecx movl $25, %edx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z30__device_stub__Z7trspta2PiS_iiPiS_ii jmp .L15 .L30: movl %ebx, %edx movq %rbp, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L18: addq $1, %rbx addq $172, %r14 cmpq $25, %rbx je .L20 .L16: leaq 4352(%rsp), %r13 leaq 0(%r13,%rbx,4), %rax movl $0, %ecx .L19: movl (%rax), %esi cmpl %esi, (%r14,%rcx,4) jne .L30 addq $1, %rcx addq $100, %rax cmpq $43, %rcx jne .L19 jmp .L18 .L20: leaq .LC4(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 100(%r13), %rbp addq $4400, %r13 leaq .LC1(%rip), %r12 leaq .LC2(%rip), %r14 jmp .L21 .L31: movq %r14, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $100, %rbp cmpq %r13, %rbp je .L23 .L21: leaq -100(%rbp), %rbx .L22: movl (%rbx), %edx movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L22 jmp .L31 .L23: leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 8664(%rsp), %rax subq %fs:40, %rax jne .L32 movl $0, %eax addq $8680, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L32: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC5: .string "_Z7trspta2PiS_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _Z7trspta2PiS_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "traspuesta2.hip" .globl _Z22__device_stub__trspta2PiS_ii # -- Begin function _Z22__device_stub__trspta2PiS_ii .p2align 4, 0x90 .type _Z22__device_stub__trspta2PiS_ii,@function _Z22__device_stub__trspta2PiS_ii: # @_Z22__device_stub__trspta2PiS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7trspta2PiS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z22__device_stub__trspta2PiS_ii, .Lfunc_end0-_Z22__device_stub__trspta2PiS_ii .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $8712, %rsp # imm = 0x2208 .cfi_def_cfa_offset 8752 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 16(%rsp), %rdi movl $4300, %esi # imm = 0x10CC callq hipMalloc leaq 8(%rsp), %rdi movl $4300, %esi # imm = 0x10CC callq hipMalloc movl $.Lstr, %edi callq puts@PLT xorl %r14d, %r14d xorl %r15d, %r15d .p2align 4, 0x90 .LBB1_1: # %.preheader48 # =>This Loop Header: Depth=1 # Child Loop BB1_2 Depth 2 movl $43, %r12d movq %r14, %rbx .p2align 4, 0x90 .LBB1_2: # Parent Loop BB1_1 Depth=1 # => This Inner Loop Header: Depth=2 movl %ebx, 4400(%rsp,%rbx,4) movl $.L.str.1, %edi movl %ebx, %esi xorl %eax, %eax callq printf incq %rbx decq %r12 jne .LBB1_2 # %bb.3: # in Loop: Header=BB1_1 Depth=1 movl $10, %edi callq putchar@PLT incq %r15 addq $43, %r14 cmpq $25, %r15 jne .LBB1_1 # %bb.4: movq 16(%rsp), %rdi leaq 4400(%rsp), %rbx movl $4300, %edx # imm = 0x10CC movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movabsq $8589934595, %rdi # imm = 0x200000003 movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_6 # %bb.5: movq 16(%rsp), %rax movq 8(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movl $25, 28(%rsp) movl $43, 24(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 28(%rsp), %rax movq %rax, 112(%rsp) leaq 24(%rsp), %rax movq %rax, 120(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z7trspta2PiS_ii, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_6: movq 8(%rsp), %rsi leaq 96(%rsp), %r14 movl $4300, %edx # imm = 0x10CC movq %r14, %rdi movl $2, %ecx callq hipMemcpy xorl %r15d, %r15d jmp .LBB1_7 .p2align 4, 0x90 .LBB1_9: # in Loop: Header=BB1_7 Depth=1 movl $.L.str.3, %edi movl %r15d, %esi # kill: def $edx killed $edx killed $rdx xorl %eax, %eax callq printf .LBB1_11: # %.loopexit # in Loop: Header=BB1_7 Depth=1 incq %r15 addq $172, %rbx addq $4, %r14 cmpq $25, %r15 je .LBB1_12 .LBB1_7: # %.preheader47 # =>This Loop Header: Depth=1 # Child Loop BB1_8 Depth 2 movq %r14, %rax xorl %edx, %edx .p2align 4, 0x90 .LBB1_8: # Parent Loop BB1_7 Depth=1 # => This Inner Loop Header: Depth=2 movl (%rbx,%rdx,4), %ecx cmpl (%rax), %ecx jne .LBB1_9 # %bb.10: # in Loop: Header=BB1_8 Depth=2 incq %rdx addq $100, %rax cmpq $43, %rdx jne .LBB1_8 jmp .LBB1_11 .LBB1_12: movl $.Lstr.1, %edi callq puts@PLT leaq 96(%rsp), %rbx xorl %r14d, %r14d .p2align 4, 0x90 .LBB1_13: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_14 Depth 2 xorl %r15d, %r15d .p2align 4, 0x90 .LBB1_14: # Parent Loop BB1_13 Depth=1 # => This Inner Loop Header: Depth=2 movl (%rbx,%r15,4), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r15 cmpq $25, %r15 jne .LBB1_14 # %bb.15: # in Loop: Header=BB1_13 Depth=1 movl $10, %edi callq putchar@PLT incq %r14 addq $100, %rbx cmpq $43, %r14 jne .LBB1_13 # %bb.16: movl $10, %edi callq putchar@PLT movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax addq $8712, %rsp # imm = 0x2208 .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7trspta2PiS_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z7trspta2PiS_ii,@object # @_Z7trspta2PiS_ii .section .rodata,"a",@progbits .globl _Z7trspta2PiS_ii .p2align 3, 0x0 _Z7trspta2PiS_ii: .quad _Z22__device_stub__trspta2PiS_ii .size _Z7trspta2PiS_ii, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz "%d " .size .L.str.1, 4 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "error en componente %d %d de matriz de entrada \n" .size .L.str.3, 49 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z7trspta2PiS_ii" .size .L__unnamed_1, 17 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "\nMatriz origen" .size .Lstr, 15 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "\nMatriz resultado" .size .Lstr.1, 18 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__trspta2PiS_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7trspta2PiS_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
// CUDA code : Add two float vectors together // Device code ( taken form Cuda SDK ) #include <iostream> __global__ void VecAdd(const float* A, const float* B, float* C, int N) { int i = blockDim.x * blockIdx.x + threadIdx.x; if (i < N) C[i] = A[i] + B[i]; } // C interface wrapper - A B C are cudaMalloc'ed references extern "C" void vecAdd( const float* A, const float* B, float* C, int size ) { int threadsPerBlock = 256; int blocksPerGrid = (size + threadsPerBlock - 1) / threadsPerBlock; VecAdd<<<blocksPerGrid, threadsPerBlock>>>(A, B, C, size); }
code for sm_80 Function : _Z6VecAddPKfS0_Pfi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */ /* 0x000fc800078e0207 */ /*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */ /* 0x0c0fe400078e0207 */ /*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea8000c1e1900 */ /*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea2000c1e1900 */ /*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */ /* 0x000fc800078e0207 */ /*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */ /* 0x004fca0000000000 */ /*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*00f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0100*/ BRA 0x100; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
// CUDA code : Add two float vectors together // Device code ( taken form Cuda SDK ) #include <iostream> __global__ void VecAdd(const float* A, const float* B, float* C, int N) { int i = blockDim.x * blockIdx.x + threadIdx.x; if (i < N) C[i] = A[i] + B[i]; } // C interface wrapper - A B C are cudaMalloc'ed references extern "C" void vecAdd( const float* A, const float* B, float* C, int size ) { int threadsPerBlock = 256; int blocksPerGrid = (size + threadsPerBlock - 1) / threadsPerBlock; VecAdd<<<blocksPerGrid, threadsPerBlock>>>(A, B, C, size); }
.file "tmpxft_0008cf7f_00000000-6_CudaVectorAdd.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi .type _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi, @function _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi: .LFB3694: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6VecAddPKfS0_Pfi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi, .-_Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi .globl _Z6VecAddPKfS0_Pfi .type _Z6VecAddPKfS0_Pfi, @function _Z6VecAddPKfS0_Pfi: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z6VecAddPKfS0_Pfi, .-_Z6VecAddPKfS0_Pfi .globl vecAdd .type vecAdd, @function vecAdd: .LFB3669: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $40, %rsp .cfi_def_cfa_offset 80 movq %rdi, %rbp movq %rsi, %r12 movq %rdx, %r13 movl %ecx, %ebx movl $256, 20(%rsp) movl $1, 24(%rsp) leal 510(%rcx), %eax movl %ecx, %edx addl $255, %edx cmovns %edx, %eax sarl $8, %eax movl %eax, 8(%rsp) movl $1, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L14 .L11: addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state movl %ebx, %ecx movq %r13, %rdx movq %r12, %rsi movq %rbp, %rdi call _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi jmp .L11 .cfi_endproc .LFE3669: .size vecAdd, .-vecAdd .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z6VecAddPKfS0_Pfi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z6VecAddPKfS0_Pfi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
// CUDA code : Add two float vectors together // Device code ( taken form Cuda SDK ) #include <iostream> __global__ void VecAdd(const float* A, const float* B, float* C, int N) { int i = blockDim.x * blockIdx.x + threadIdx.x; if (i < N) C[i] = A[i] + B[i]; } // C interface wrapper - A B C are cudaMalloc'ed references extern "C" void vecAdd( const float* A, const float* B, float* C, int size ) { int threadsPerBlock = 256; int blocksPerGrid = (size + threadsPerBlock - 1) / threadsPerBlock; VecAdd<<<blocksPerGrid, threadsPerBlock>>>(A, B, C, size); }
// CUDA code : Add two float vectors together // Device code ( taken form Cuda SDK ) #include <hip/hip_runtime.h> #include <iostream> __global__ void VecAdd(const float* A, const float* B, float* C, int N) { int i = blockDim.x * blockIdx.x + threadIdx.x; if (i < N) C[i] = A[i] + B[i]; } // C interface wrapper - A B C are cudaMalloc'ed references extern "C" void vecAdd( const float* A, const float* B, float* C, int size ) { int threadsPerBlock = 256; int blocksPerGrid = (size + threadsPerBlock - 1) / threadsPerBlock; VecAdd<<<blocksPerGrid, threadsPerBlock>>>(A, B, C, size); }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
// CUDA code : Add two float vectors together // Device code ( taken form Cuda SDK ) #include <hip/hip_runtime.h> #include <iostream> __global__ void VecAdd(const float* A, const float* B, float* C, int N) { int i = blockDim.x * blockIdx.x + threadIdx.x; if (i < N) C[i] = A[i] + B[i]; } // C interface wrapper - A B C are cudaMalloc'ed references extern "C" void vecAdd( const float* A, const float* B, float* C, int size ) { int threadsPerBlock = 256; int blocksPerGrid = (size + threadsPerBlock - 1) / threadsPerBlock; VecAdd<<<blocksPerGrid, threadsPerBlock>>>(A, B, C, size); }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6VecAddPKfS0_Pfi .globl _Z6VecAddPKfS0_Pfi .p2align 8 .type _Z6VecAddPKfS0_Pfi,@function _Z6VecAddPKfS0_Pfi: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_f32_e32 v2, v2, v3 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6VecAddPKfS0_Pfi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6VecAddPKfS0_Pfi, .Lfunc_end0-_Z6VecAddPKfS0_Pfi .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6VecAddPKfS0_Pfi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6VecAddPKfS0_Pfi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
// CUDA code : Add two float vectors together // Device code ( taken form Cuda SDK ) #include <hip/hip_runtime.h> #include <iostream> __global__ void VecAdd(const float* A, const float* B, float* C, int N) { int i = blockDim.x * blockIdx.x + threadIdx.x; if (i < N) C[i] = A[i] + B[i]; } // C interface wrapper - A B C are cudaMalloc'ed references extern "C" void vecAdd( const float* A, const float* B, float* C, int size ) { int threadsPerBlock = 256; int blocksPerGrid = (size + threadsPerBlock - 1) / threadsPerBlock; VecAdd<<<blocksPerGrid, threadsPerBlock>>>(A, B, C, size); }
.text .file "CudaVectorAdd.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z21__device_stub__VecAddPKfS0_Pfi # -- Begin function _Z21__device_stub__VecAddPKfS0_Pfi .p2align 4, 0x90 .type _Z21__device_stub__VecAddPKfS0_Pfi,@function _Z21__device_stub__VecAddPKfS0_Pfi: # @_Z21__device_stub__VecAddPKfS0_Pfi .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6VecAddPKfS0_Pfi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z21__device_stub__VecAddPKfS0_Pfi, .Lfunc_end0-_Z21__device_stub__VecAddPKfS0_Pfi .cfi_endproc # -- End function .globl vecAdd # -- Begin function vecAdd .p2align 4, 0x90 .type vecAdd,@function vecAdd: # @vecAdd .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $120, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl %ecx, %ebx movq %rdx, %r14 movq %rsi, %r15 movq %rdi, %r12 leal 255(%rbx), %eax leal 510(%rbx), %edi testl %eax, %eax cmovnsl %eax, %edi sarl $8, %edi movabsq $4294967296, %rdx # imm = 0x100000000 orq %rdx, %rdi orq $256, %rdx # imm = 0x100 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq %r12, 72(%rsp) movq %r15, 64(%rsp) movq %r14, 56(%rsp) movl %ebx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6VecAddPKfS0_Pfi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: addq $120, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size vecAdd, .Lfunc_end1-vecAdd .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6VecAddPKfS0_Pfi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z6VecAddPKfS0_Pfi,@object # @_Z6VecAddPKfS0_Pfi .section .rodata,"a",@progbits .globl _Z6VecAddPKfS0_Pfi .p2align 3, 0x0 _Z6VecAddPKfS0_Pfi: .quad _Z21__device_stub__VecAddPKfS0_Pfi .size _Z6VecAddPKfS0_Pfi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z6VecAddPKfS0_Pfi" .size .L__unnamed_1, 19 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__VecAddPKfS0_Pfi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z6VecAddPKfS0_Pfi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z6VecAddPKfS0_Pfi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */ /* 0x000fc800078e0207 */ /*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */ /* 0x0c0fe400078e0207 */ /*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea8000c1e1900 */ /*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea2000c1e1900 */ /*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */ /* 0x000fc800078e0207 */ /*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */ /* 0x004fca0000000000 */ /*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*00f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0100*/ BRA 0x100; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6VecAddPKfS0_Pfi .globl _Z6VecAddPKfS0_Pfi .p2align 8 .type _Z6VecAddPKfS0_Pfi,@function _Z6VecAddPKfS0_Pfi: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_f32_e32 v2, v2, v3 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6VecAddPKfS0_Pfi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6VecAddPKfS0_Pfi, .Lfunc_end0-_Z6VecAddPKfS0_Pfi .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6VecAddPKfS0_Pfi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6VecAddPKfS0_Pfi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0008cf7f_00000000-6_CudaVectorAdd.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi .type _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi, @function _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi: .LFB3694: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6VecAddPKfS0_Pfi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi, .-_Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi .globl _Z6VecAddPKfS0_Pfi .type _Z6VecAddPKfS0_Pfi, @function _Z6VecAddPKfS0_Pfi: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z6VecAddPKfS0_Pfi, .-_Z6VecAddPKfS0_Pfi .globl vecAdd .type vecAdd, @function vecAdd: .LFB3669: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $40, %rsp .cfi_def_cfa_offset 80 movq %rdi, %rbp movq %rsi, %r12 movq %rdx, %r13 movl %ecx, %ebx movl $256, 20(%rsp) movl $1, 24(%rsp) leal 510(%rcx), %eax movl %ecx, %edx addl $255, %edx cmovns %edx, %eax sarl $8, %eax movl %eax, 8(%rsp) movl $1, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L14 .L11: addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state movl %ebx, %ecx movq %r13, %rdx movq %r12, %rsi movq %rbp, %rdi call _Z32__device_stub__Z6VecAddPKfS0_PfiPKfS0_Pfi jmp .L11 .cfi_endproc .LFE3669: .size vecAdd, .-vecAdd .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z6VecAddPKfS0_Pfi" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z6VecAddPKfS0_Pfi(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "CudaVectorAdd.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z21__device_stub__VecAddPKfS0_Pfi # -- Begin function _Z21__device_stub__VecAddPKfS0_Pfi .p2align 4, 0x90 .type _Z21__device_stub__VecAddPKfS0_Pfi,@function _Z21__device_stub__VecAddPKfS0_Pfi: # @_Z21__device_stub__VecAddPKfS0_Pfi .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6VecAddPKfS0_Pfi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z21__device_stub__VecAddPKfS0_Pfi, .Lfunc_end0-_Z21__device_stub__VecAddPKfS0_Pfi .cfi_endproc # -- End function .globl vecAdd # -- Begin function vecAdd .p2align 4, 0x90 .type vecAdd,@function vecAdd: # @vecAdd .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $120, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl %ecx, %ebx movq %rdx, %r14 movq %rsi, %r15 movq %rdi, %r12 leal 255(%rbx), %eax leal 510(%rbx), %edi testl %eax, %eax cmovnsl %eax, %edi sarl $8, %edi movabsq $4294967296, %rdx # imm = 0x100000000 orq %rdx, %rdi orq $256, %rdx # imm = 0x100 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq %r12, 72(%rsp) movq %r15, 64(%rsp) movq %r14, 56(%rsp) movl %ebx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6VecAddPKfS0_Pfi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: addq $120, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size vecAdd, .Lfunc_end1-vecAdd .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6VecAddPKfS0_Pfi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z6VecAddPKfS0_Pfi,@object # @_Z6VecAddPKfS0_Pfi .section .rodata,"a",@progbits .globl _Z6VecAddPKfS0_Pfi .p2align 3, 0x0 _Z6VecAddPKfS0_Pfi: .quad _Z21__device_stub__VecAddPKfS0_Pfi .size _Z6VecAddPKfS0_Pfi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z6VecAddPKfS0_Pfi" .size .L__unnamed_1, 19 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__VecAddPKfS0_Pfi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z6VecAddPKfS0_Pfi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
/*Parallel and Distributed Systems --CUDA KNN Algorithm-- -Author: Mitsios Georgios -September 2014 */ #include <stdio.h> #include <stdlib.h> #include <time.h> #include <sys/time.h> #include <cuda.h> #include <cuda_runtime.h> #include <float.h> #include <math.h> #define CUDA_CHECK_RETURN(value) { \ cudaError_t _m_cudaStat = value; \ if (_m_cudaStat != cudaSuccess) { \ fprintf(stderr, "Error %s at line %d in file %s\n", \ cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \ exit(1); \ } } typedef struct{ double *data; int leading_dim; int secondary_dim; } knn_struct; //1st input option. Random initialization void random_initialization(knn_struct *set, int cal){ int i = 0; int n = set->leading_dim; int m = set->secondary_dim; double *tmp_set = set->data; srand(cal*time(NULL)); /*Generate random floating points [-50 50]*/ for(i=0; i<m*n; i++){ tmp_set[i] = 100 * (double)rand() / RAND_MAX - 50; } } //2nd input option. Import data from benchmark files void initialize(knn_struct *set){ int i = 0; int n = set->leading_dim; int m = set->secondary_dim; float *tmp_set; double *tempArray; tmp_set = (float*)malloc(n*m*sizeof(float)); tempArray = (double*)malloc(n*m*sizeof(double)); FILE *fp; size_t t; if (m>100000){ if ((fp = fopen("baseREAD.bin", "rb")) == NULL){ printf("Can't open output file"); } } else{ if ((fp = fopen("queriesREAD.bin", "rb")) == NULL){ printf("Can't open output file"); } } t = fread(tmp_set, n*m, sizeof(float), fp); fclose(fp); //Convert float input data to doubles for (i=0;i<n*m;i++){ tempArray[i] = (double)tmp_set[i]; } set->data = tempArray; } //This function was used to normalize data from -50 to 50 to match the random points void input_normalisation(knn_struct *base, knn_struct *queries){ int i; int N = base->leading_dim, ni = queries->leading_dim; int M = base->secondary_dim, mi = queries->secondary_dim; double maxVal=0, minVal=1; double *tmp_data = base->data; double *tmp_queries = queries->data; for (i=0;i<N*M;i++){ if (tmp_data[i]>maxVal) { maxVal=tmp_data[i]; } if (tmp_data[i]<minVal) { minVal=tmp_data[i]; } } for (i=0;i<ni*mi;i++){ if (tmp_queries[i]>maxVal) { maxVal=tmp_queries[i]; } if (tmp_queries[i]<minVal) { minVal=tmp_queries[i]; } } if ( minVal<0 ) { minVal = minVal*(-1); } if ( minVal>maxVal) { maxVal = minVal; } for (i=0;i<N*M;i++){ tmp_data[i] = (tmp_data[i]*50)/maxVal; } for (i=0;i<ni*mi;i++){ tmp_queries[i] = (tmp_queries[i]*50)/maxVal; } } void save_d(double* data, char* file, int N, int M){ FILE *outfile; printf("Saving data to file: %s\n", file); if((outfile=fopen(file, "wb")) == NULL){ printf("Can't open output file"); } fwrite(data, sizeof(double), N*M, outfile); fclose(outfile); } void save_int(int* data, char* file, int N, int M){ FILE *outfile; printf("Saving data to file: %s\n", file); if((outfile=fopen(file, "wb")) == NULL){ printf("Can't open output file"); } fwrite(data, sizeof(int), N*M, outfile); fclose(outfile); } void clean(knn_struct* d){ free(d->data); } //This kernel function computes the euclidean distance between queries and objects __global__ void calculate_distance(double* queries, double* dataset, double *dist, int* k, int* n){ int numObj=*n; int index = threadIdx.x + blockIdx.x * blockDim.x; double tmp=0; //Initialize distances to 0 if (threadIdx.x == 0) { for (int i=0; i<numObj; i++){ dist[blockIdx.x*numObj + i] = 0; } } __syncthreads(); //Compute and store euclidean distance for (int ni=0;ni<(numObj);ni++){ tmp = (queries[index] - dataset[threadIdx.x + ni * blockDim.x])*(queries[index] - dataset[threadIdx.x + ni * blockDim.x]); dist[blockIdx.x * numObj + ni] = dist[blockIdx.x * numObj + ni] + tmp; __syncthreads(); } __syncthreads(); } /*This kernel function computes the knn of the temporary set of data (which is only a portion of the original data. The way this function works is better expalined in the report sheet*/ __global__ void compute_knn(double* NNdist, double* dist, int* numObj, int* NNidx, int* bonusID, int *offset, double *tmpDist, int *tmpID, int *N){ int i, n = *numObj, off = *offset, Nol= *N; int start = blockIdx.x * n; int index = threadIdx.x + blockIdx.x*blockDim.x; int position = blockDim.x+threadIdx.x+1; double temp=0; int tmp=0; NNdist[index] = DBL_MAX; NNidx[index] = (-1); bonusID[index] = (-1); __syncthreads(); for (i=start; i<(start+n+blockDim.x);i++){ if ( ((i-position)< (start +n)) && (i-position) >= start ){ if ( NNdist[index] > dist[i - position] ){ temp = NNdist[index]; NNdist[index] = dist[i - position]; dist[i - position] = temp; if (bonusID[index]>=0){ tmp = NNidx[index]; NNidx[index]=bonusID[index]; bonusID[index]= tmp; } else{ bonusID[index] = NNidx[index]; NNidx[index] = (i - position - start) + (off*n); } } __syncthreads(); } __syncthreads(); if (threadIdx.x == 7){ for (int j=0;j<(blockDim.x-1);j++){ bonusID[j+blockIdx.x*blockDim.x] = bonusID[j+blockIdx.x*blockDim.x +1]; } bonusID[index] = (-1); } __syncthreads(); } tmpDist[ off*blockDim.x + blockIdx.x*(Nol*blockDim.x) + threadIdx.x ] = NNdist[index]; tmpID[ off*blockDim.x + blockIdx.x*(Nol*blockDim.x) + threadIdx.x ] = NNidx[index]; __syncthreads(); } /*This is the last kernel function which compares the knns that have been computed from each group of data to find the final knn values and ids. The operation is similar to the "compute_knn" function*/ __global__ void knnSelection(double* NNdist, int* NNidx, int* originalID, double* dist, int* numObj){ int i, n=*numObj; int start = blockIdx.x * n; int index = threadIdx.x + blockIdx.x*blockDim.x; double temp=0; int tmp=0; NNdist[index] = DBL_MAX; NNidx[index] = (-1); __syncthreads(); for (i=start; i<(start+n+blockDim.x);i++){ if ( ((i-blockDim.x+threadIdx.x+1)< (start +n)) && (i-blockDim.x+threadIdx.x+1) >= start ){ if ( NNdist[index] > dist[i - blockDim.x + threadIdx.x + 1] ){ temp = NNdist[index]; NNdist[index] = dist[i - blockDim.x + threadIdx.x + 1]; dist[i - blockDim.x + threadIdx.x + 1] = temp; tmp = NNidx[index]; NNidx[index]=originalID[i - blockDim.x + threadIdx.x + 1]; originalID[i - blockDim.x + threadIdx.x + 1]= tmp; } } __syncthreads(); } __syncthreads(); } int main(int argc, char **argv){ struct timeval first, second, lapsed; struct timezone tzp; int i; int numObjects = atoi(argv[1]); //pow(2,atoi(argv[1])); int numDim = atoi(argv[2]); int numQueries = atoi(argv[3]); int k = atoi(argv[4]); int pi=pow(2,15); int pol; if (numObjects>pi ){pol=numObjects/pi;} else{ pol=1; pi=numObjects; } //Getting GPU memory's info size_t mem_tot_0 = 0; size_t mem_free_0 = 0; cudaMemGetInfo(&mem_free_0, &mem_tot_0); size_t dist_size = numQueries*numObjects*sizeof(double); size_t data_size = numObjects*numDim*sizeof(double); size_t queries_size = numQueries*numDim*sizeof(double); size_t NNdist_size = numQueries*k*sizeof(double); size_t NNidx_size = numQueries*k*sizeof(int); size_t mem_req = dist_size + data_size + queries_size + NNdist_size + NNidx_size; size_t mem_req1 = dist_size + data_size; int nol; int ni; size_t mem_free_n = mem_free_0 - (queries_size -NNdist_size - NNidx_size); printf("\nGPU memory needed : %ld bytes \n", mem_req1); printf("Available GPU memory : %ld bytes \n", mem_free_n); //Computing the number of divisions to the data for proper memory usage if (mem_req> (mem_free_n ) ){ nol = (mem_req1/mem_free_n); int e=0; while (nol>2){ nol=nol/2; e++; } nol=pow(2,e+1); } else {nol=1;} //Value 500 can be reduced to 200 or even 100 for lower memory GPUs if (numQueries>500) { nol = nol*(numQueries/500); } ni = numObjects/nol; printf("Data will be divided into %d groups \n", nol); printf("of %d elements per group for optimal operation\n\n", ni); char *dataset_file = "training_set.bin"; char *query_file = "query_set.bin"; char *KNNdist_file = "KNNdist.bin"; char *KNNidx_file = "KNNidx.bin" ; double *tmpDist; int *tmpID; tmpDist = (double*)malloc(nol*numQueries*k*sizeof(double)); tmpID = (int*)malloc(nol*numQueries*k*sizeof(int)); printf("objects: %d\n", numObjects); printf("dimentions: %d\n", numDim); printf("queries: %d\n", numQueries); printf("k: %d\n", k); knn_struct training_set; knn_struct query_set; double *dist; double *NNdist; int *NNidx; training_set.leading_dim = numDim; training_set.secondary_dim = numObjects; query_set.leading_dim = numDim; query_set.secondary_dim = numQueries; /*======== Memory allocation ======*/ training_set.data = (double*)malloc(numObjects*numDim*sizeof(double)); query_set.data = (double*)malloc(numQueries*numDim*sizeof(double)); NNdist = (double*)malloc(numQueries*k*sizeof(double)); NNidx = (int*)malloc(numQueries*k*sizeof(int)); dist = (double*)malloc(numObjects*numQueries*sizeof(double)); double *d_data; double *d_queries; double *d_dist; double *d_NNdist; int *d_NNidx; int *d_bonusID; int *dev_k, *dev_n; int *dev_nol; double *d_tmpDist; int *d_tmpID; //GPU memory allocation CUDA_CHECK_RETURN(cudaMalloc( (void **)&d_data, ni*numDim*sizeof(double)) ); CUDA_CHECK_RETURN(cudaMalloc( (void **)&d_queries, numQueries*numDim*sizeof(double)) ); CUDA_CHECK_RETURN( cudaMalloc( (void **)&d_NNdist, numQueries*k*sizeof(double)) ); CUDA_CHECK_RETURN( cudaMalloc( (void **)&d_NNidx, numQueries*k*sizeof(int)) ); CUDA_CHECK_RETURN( cudaMalloc( (void **)&d_bonusID, numQueries*k*sizeof(int)) ); CUDA_CHECK_RETURN( cudaMalloc( (void **)&d_tmpDist, nol*numQueries*k*sizeof(double)) ); CUDA_CHECK_RETURN( cudaMalloc( (void **)&d_tmpID, nol*numQueries*k*sizeof(int)) ); CUDA_CHECK_RETURN( cudaMalloc( (void **)&d_dist, numQueries*ni*sizeof(double)) ); CUDA_CHECK_RETURN( cudaMalloc( (void **)&dev_k, sizeof(int)) ); CUDA_CHECK_RETURN( cudaMalloc( (void **)&dev_n, sizeof(int)) ); CUDA_CHECK_RETURN( cudaMalloc( (void **)&dev_nol, sizeof(int)) ); /*======== initialize =========*/ //Input option 1. Create random data random_initialization(&training_set, 1); random_initialization(&query_set, 2); //Input option 2. Import data from file //initialize(&training_set); //initialize(&query_set); /*The following function was used to normalize imported data values from benchmark files to be from -50 to 50, because there was some undefined error in previous compilations. It MAY OR MAY NOT BE USED */ //input_normalisation(&training_set, &query_set); //Copy data to GPU memory CUDA_CHECK_RETURN(cudaMemcpy( d_queries, query_set.data, numQueries*numDim*sizeof(double), cudaMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(cudaMemcpy( dev_k, &k, sizeof(int), cudaMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(cudaMemcpy( dev_nol, &nol, sizeof(int), cudaMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(cudaMemcpy( dev_n, &ni, sizeof(int), cudaMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(cudaMemcpy( d_tmpDist, tmpDist, nol*numQueries*k*sizeof(double), cudaMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(cudaMemcpy( d_tmpID, tmpID, nol*numQueries*k*sizeof(int), cudaMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(cudaMemcpy( d_dist, dist, numQueries*ni*sizeof(double), cudaMemcpyHostToDevice ) ); int offset=0; int *dev_off=0; CUDA_CHECK_RETURN( cudaMalloc( (void **)&dev_off, sizeof(int)) ); gettimeofday(&first, &tzp); /*This for loop is the core of the program. It sends each group of data to the GPU where it computes the distances between each query and each object. Then calls the "compute_knn" kernel function to find the actual KNNs*/ for ( offset=0 ; offset<nol ; offset++ ){ CUDA_CHECK_RETURN(cudaMemcpy( d_data, (training_set.data +offset*ni), ni*numDim*sizeof(double), cudaMemcpyHostToDevice ) ); calculate_distance<<< numQueries, numDim>>> ( d_queries, d_data, d_dist, dev_k, dev_n); CUDA_CHECK_RETURN( cudaPeekAtLastError() ); CUDA_CHECK_RETURN( cudaDeviceSynchronize() ); CUDA_CHECK_RETURN(cudaMemcpy( dev_off, &offset, sizeof(int), cudaMemcpyHostToDevice ) ); compute_knn<<< numQueries, k>>>(d_NNdist, d_dist, dev_n, d_NNidx, d_bonusID, dev_off, d_tmpDist, d_tmpID, dev_nol); CUDA_CHECK_RETURN( cudaPeekAtLastError() ); CUDA_CHECK_RETURN( cudaDeviceSynchronize() ); } CUDA_CHECK_RETURN(cudaMemcpy( tmpDist, d_tmpDist, nol*numQueries*k*sizeof(double), cudaMemcpyDeviceToHost ) ); CUDA_CHECK_RETURN(cudaMemcpy( tmpID, d_tmpID, nol*numQueries*k*sizeof(int), cudaMemcpyDeviceToHost ) ); /*In case of division of the original data, the temporary KNNs are being compared to form the final KNNs*/ if (nol!=1){ pi=nol*k; cudaMemcpy( dev_n, &pi, sizeof(int), cudaMemcpyHostToDevice ) ; knnSelection<<< numQueries, k>>>(d_NNdist, d_NNidx, d_tmpID, d_tmpDist, dev_n); CUDA_CHECK_RETURN( cudaPeekAtLastError() ); } gettimeofday(&second, &tzp); printf("\n---KNN computed--- \n\n"); if(first.tv_usec>second.tv_usec){ second.tv_usec += 1000000; second.tv_sec--; } lapsed.tv_usec = second.tv_usec - first.tv_usec; lapsed.tv_sec = second.tv_sec - first.tv_sec; printf("Time elapsed: %ld, %ld s\n", lapsed.tv_sec, lapsed.tv_usec); CUDA_CHECK_RETURN( cudaMemcpy( NNdist, d_NNdist, numQueries*k*sizeof(double), cudaMemcpyDeviceToHost ) ); CUDA_CHECK_RETURN( cudaMemcpy( NNidx, d_NNidx, numQueries*k*sizeof(int), cudaMemcpyDeviceToHost ) ); save_d(query_set.data, query_file, numQueries, numDim); save_d(training_set.data, dataset_file, numObjects, numDim); save_d(NNdist, KNNdist_file, k, numQueries); save_int(NNidx, KNNidx_file, k, numQueries); /*===== clean memory ========*/ clean(&training_set); clean(&query_set); free(NNdist); free(NNidx); free(dist); cudaFree(d_queries); cudaFree(d_data); cudaFree(d_NNdist); cudaFree(d_NNidx); cudaFree(dev_k); cudaFree(dev_n); cudaFree(d_dist); }
/*Parallel and Distributed Systems --CUDA KNN Algorithm-- -Author: Mitsios Georgios -September 2014 */ #include <stdio.h> #include <stdlib.h> #include <time.h> #include <sys/time.h> #include <hip/hip_runtime.h> #include <float.h> #include <math.h> #define CUDA_CHECK_RETURN(value) { \ hipError_t _m_cudaStat = value; \ if (_m_cudaStat != hipSuccess) { \ fprintf(stderr, "Error %s at line %d in file %s\n", \ hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \ exit(1); \ } } typedef struct{ double *data; int leading_dim; int secondary_dim; } knn_struct; //1st input option. Random initialization void random_initialization(knn_struct *set, int cal){ int i = 0; int n = set->leading_dim; int m = set->secondary_dim; double *tmp_set = set->data; srand(cal*time(NULL)); /*Generate random floating points [-50 50]*/ for(i=0; i<m*n; i++){ tmp_set[i] = 100 * (double)rand() / RAND_MAX - 50; } } //2nd input option. Import data from benchmark files void initialize(knn_struct *set){ int i = 0; int n = set->leading_dim; int m = set->secondary_dim; float *tmp_set; double *tempArray; tmp_set = (float*)malloc(n*m*sizeof(float)); tempArray = (double*)malloc(n*m*sizeof(double)); FILE *fp; size_t t; if (m>100000){ if ((fp = fopen("baseREAD.bin", "rb")) == NULL){ printf("Can't open output file"); } } else{ if ((fp = fopen("queriesREAD.bin", "rb")) == NULL){ printf("Can't open output file"); } } t = fread(tmp_set, n*m, sizeof(float), fp); fclose(fp); //Convert float input data to doubles for (i=0;i<n*m;i++){ tempArray[i] = (double)tmp_set[i]; } set->data = tempArray; } //This function was used to normalize data from -50 to 50 to match the random points void input_normalisation(knn_struct *base, knn_struct *queries){ int i; int N = base->leading_dim, ni = queries->leading_dim; int M = base->secondary_dim, mi = queries->secondary_dim; double maxVal=0, minVal=1; double *tmp_data = base->data; double *tmp_queries = queries->data; for (i=0;i<N*M;i++){ if (tmp_data[i]>maxVal) { maxVal=tmp_data[i]; } if (tmp_data[i]<minVal) { minVal=tmp_data[i]; } } for (i=0;i<ni*mi;i++){ if (tmp_queries[i]>maxVal) { maxVal=tmp_queries[i]; } if (tmp_queries[i]<minVal) { minVal=tmp_queries[i]; } } if ( minVal<0 ) { minVal = minVal*(-1); } if ( minVal>maxVal) { maxVal = minVal; } for (i=0;i<N*M;i++){ tmp_data[i] = (tmp_data[i]*50)/maxVal; } for (i=0;i<ni*mi;i++){ tmp_queries[i] = (tmp_queries[i]*50)/maxVal; } } void save_d(double* data, char* file, int N, int M){ FILE *outfile; printf("Saving data to file: %s\n", file); if((outfile=fopen(file, "wb")) == NULL){ printf("Can't open output file"); } fwrite(data, sizeof(double), N*M, outfile); fclose(outfile); } void save_int(int* data, char* file, int N, int M){ FILE *outfile; printf("Saving data to file: %s\n", file); if((outfile=fopen(file, "wb")) == NULL){ printf("Can't open output file"); } fwrite(data, sizeof(int), N*M, outfile); fclose(outfile); } void clean(knn_struct* d){ free(d->data); } //This kernel function computes the euclidean distance between queries and objects __global__ void calculate_distance(double* queries, double* dataset, double *dist, int* k, int* n){ int numObj=*n; int index = threadIdx.x + blockIdx.x * blockDim.x; double tmp=0; //Initialize distances to 0 if (threadIdx.x == 0) { for (int i=0; i<numObj; i++){ dist[blockIdx.x*numObj + i] = 0; } } __syncthreads(); //Compute and store euclidean distance for (int ni=0;ni<(numObj);ni++){ tmp = (queries[index] - dataset[threadIdx.x + ni * blockDim.x])*(queries[index] - dataset[threadIdx.x + ni * blockDim.x]); dist[blockIdx.x * numObj + ni] = dist[blockIdx.x * numObj + ni] + tmp; __syncthreads(); } __syncthreads(); } /*This kernel function computes the knn of the temporary set of data (which is only a portion of the original data. The way this function works is better expalined in the report sheet*/ __global__ void compute_knn(double* NNdist, double* dist, int* numObj, int* NNidx, int* bonusID, int *offset, double *tmpDist, int *tmpID, int *N){ int i, n = *numObj, off = *offset, Nol= *N; int start = blockIdx.x * n; int index = threadIdx.x + blockIdx.x*blockDim.x; int position = blockDim.x+threadIdx.x+1; double temp=0; int tmp=0; NNdist[index] = DBL_MAX; NNidx[index] = (-1); bonusID[index] = (-1); __syncthreads(); for (i=start; i<(start+n+blockDim.x);i++){ if ( ((i-position)< (start +n)) && (i-position) >= start ){ if ( NNdist[index] > dist[i - position] ){ temp = NNdist[index]; NNdist[index] = dist[i - position]; dist[i - position] = temp; if (bonusID[index]>=0){ tmp = NNidx[index]; NNidx[index]=bonusID[index]; bonusID[index]= tmp; } else{ bonusID[index] = NNidx[index]; NNidx[index] = (i - position - start) + (off*n); } } __syncthreads(); } __syncthreads(); if (threadIdx.x == 7){ for (int j=0;j<(blockDim.x-1);j++){ bonusID[j+blockIdx.x*blockDim.x] = bonusID[j+blockIdx.x*blockDim.x +1]; } bonusID[index] = (-1); } __syncthreads(); } tmpDist[ off*blockDim.x + blockIdx.x*(Nol*blockDim.x) + threadIdx.x ] = NNdist[index]; tmpID[ off*blockDim.x + blockIdx.x*(Nol*blockDim.x) + threadIdx.x ] = NNidx[index]; __syncthreads(); } /*This is the last kernel function which compares the knns that have been computed from each group of data to find the final knn values and ids. The operation is similar to the "compute_knn" function*/ __global__ void knnSelection(double* NNdist, int* NNidx, int* originalID, double* dist, int* numObj){ int i, n=*numObj; int start = blockIdx.x * n; int index = threadIdx.x + blockIdx.x*blockDim.x; double temp=0; int tmp=0; NNdist[index] = DBL_MAX; NNidx[index] = (-1); __syncthreads(); for (i=start; i<(start+n+blockDim.x);i++){ if ( ((i-blockDim.x+threadIdx.x+1)< (start +n)) && (i-blockDim.x+threadIdx.x+1) >= start ){ if ( NNdist[index] > dist[i - blockDim.x + threadIdx.x + 1] ){ temp = NNdist[index]; NNdist[index] = dist[i - blockDim.x + threadIdx.x + 1]; dist[i - blockDim.x + threadIdx.x + 1] = temp; tmp = NNidx[index]; NNidx[index]=originalID[i - blockDim.x + threadIdx.x + 1]; originalID[i - blockDim.x + threadIdx.x + 1]= tmp; } } __syncthreads(); } __syncthreads(); } int main(int argc, char **argv){ struct timeval first, second, lapsed; struct timezone tzp; int i; int numObjects = atoi(argv[1]); //pow(2,atoi(argv[1])); int numDim = atoi(argv[2]); int numQueries = atoi(argv[3]); int k = atoi(argv[4]); int pi=pow(2,15); int pol; if (numObjects>pi ){pol=numObjects/pi;} else{ pol=1; pi=numObjects; } //Getting GPU memory's info size_t mem_tot_0 = 0; size_t mem_free_0 = 0; hipMemGetInfo(&mem_free_0, &mem_tot_0); size_t dist_size = numQueries*numObjects*sizeof(double); size_t data_size = numObjects*numDim*sizeof(double); size_t queries_size = numQueries*numDim*sizeof(double); size_t NNdist_size = numQueries*k*sizeof(double); size_t NNidx_size = numQueries*k*sizeof(int); size_t mem_req = dist_size + data_size + queries_size + NNdist_size + NNidx_size; size_t mem_req1 = dist_size + data_size; int nol; int ni; size_t mem_free_n = mem_free_0 - (queries_size -NNdist_size - NNidx_size); printf("\nGPU memory needed : %ld bytes \n", mem_req1); printf("Available GPU memory : %ld bytes \n", mem_free_n); //Computing the number of divisions to the data for proper memory usage if (mem_req> (mem_free_n ) ){ nol = (mem_req1/mem_free_n); int e=0; while (nol>2){ nol=nol/2; e++; } nol=pow(2,e+1); } else {nol=1;} //Value 500 can be reduced to 200 or even 100 for lower memory GPUs if (numQueries>500) { nol = nol*(numQueries/500); } ni = numObjects/nol; printf("Data will be divided into %d groups \n", nol); printf("of %d elements per group for optimal operation\n\n", ni); char *dataset_file = "training_set.bin"; char *query_file = "query_set.bin"; char *KNNdist_file = "KNNdist.bin"; char *KNNidx_file = "KNNidx.bin" ; double *tmpDist; int *tmpID; tmpDist = (double*)malloc(nol*numQueries*k*sizeof(double)); tmpID = (int*)malloc(nol*numQueries*k*sizeof(int)); printf("objects: %d\n", numObjects); printf("dimentions: %d\n", numDim); printf("queries: %d\n", numQueries); printf("k: %d\n", k); knn_struct training_set; knn_struct query_set; double *dist; double *NNdist; int *NNidx; training_set.leading_dim = numDim; training_set.secondary_dim = numObjects; query_set.leading_dim = numDim; query_set.secondary_dim = numQueries; /*======== Memory allocation ======*/ training_set.data = (double*)malloc(numObjects*numDim*sizeof(double)); query_set.data = (double*)malloc(numQueries*numDim*sizeof(double)); NNdist = (double*)malloc(numQueries*k*sizeof(double)); NNidx = (int*)malloc(numQueries*k*sizeof(int)); dist = (double*)malloc(numObjects*numQueries*sizeof(double)); double *d_data; double *d_queries; double *d_dist; double *d_NNdist; int *d_NNidx; int *d_bonusID; int *dev_k, *dev_n; int *dev_nol; double *d_tmpDist; int *d_tmpID; //GPU memory allocation CUDA_CHECK_RETURN(hipMalloc( (void **)&d_data, ni*numDim*sizeof(double)) ); CUDA_CHECK_RETURN(hipMalloc( (void **)&d_queries, numQueries*numDim*sizeof(double)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&d_NNdist, numQueries*k*sizeof(double)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&d_NNidx, numQueries*k*sizeof(int)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&d_bonusID, numQueries*k*sizeof(int)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&d_tmpDist, nol*numQueries*k*sizeof(double)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&d_tmpID, nol*numQueries*k*sizeof(int)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&d_dist, numQueries*ni*sizeof(double)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&dev_k, sizeof(int)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&dev_n, sizeof(int)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&dev_nol, sizeof(int)) ); /*======== initialize =========*/ //Input option 1. Create random data random_initialization(&training_set, 1); random_initialization(&query_set, 2); //Input option 2. Import data from file //initialize(&training_set); //initialize(&query_set); /*The following function was used to normalize imported data values from benchmark files to be from -50 to 50, because there was some undefined error in previous compilations. It MAY OR MAY NOT BE USED */ //input_normalisation(&training_set, &query_set); //Copy data to GPU memory CUDA_CHECK_RETURN(hipMemcpy( d_queries, query_set.data, numQueries*numDim*sizeof(double), hipMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(hipMemcpy( dev_k, &k, sizeof(int), hipMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(hipMemcpy( dev_nol, &nol, sizeof(int), hipMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(hipMemcpy( dev_n, &ni, sizeof(int), hipMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(hipMemcpy( d_tmpDist, tmpDist, nol*numQueries*k*sizeof(double), hipMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(hipMemcpy( d_tmpID, tmpID, nol*numQueries*k*sizeof(int), hipMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(hipMemcpy( d_dist, dist, numQueries*ni*sizeof(double), hipMemcpyHostToDevice ) ); int offset=0; int *dev_off=0; CUDA_CHECK_RETURN( hipMalloc( (void **)&dev_off, sizeof(int)) ); gettimeofday(&first, &tzp); /*This for loop is the core of the program. It sends each group of data to the GPU where it computes the distances between each query and each object. Then calls the "compute_knn" kernel function to find the actual KNNs*/ for ( offset=0 ; offset<nol ; offset++ ){ CUDA_CHECK_RETURN(hipMemcpy( d_data, (training_set.data +offset*ni), ni*numDim*sizeof(double), hipMemcpyHostToDevice ) ); calculate_distance<<< numQueries, numDim>>> ( d_queries, d_data, d_dist, dev_k, dev_n); CUDA_CHECK_RETURN( hipPeekAtLastError() ); CUDA_CHECK_RETURN( hipDeviceSynchronize() ); CUDA_CHECK_RETURN(hipMemcpy( dev_off, &offset, sizeof(int), hipMemcpyHostToDevice ) ); compute_knn<<< numQueries, k>>>(d_NNdist, d_dist, dev_n, d_NNidx, d_bonusID, dev_off, d_tmpDist, d_tmpID, dev_nol); CUDA_CHECK_RETURN( hipPeekAtLastError() ); CUDA_CHECK_RETURN( hipDeviceSynchronize() ); } CUDA_CHECK_RETURN(hipMemcpy( tmpDist, d_tmpDist, nol*numQueries*k*sizeof(double), hipMemcpyDeviceToHost ) ); CUDA_CHECK_RETURN(hipMemcpy( tmpID, d_tmpID, nol*numQueries*k*sizeof(int), hipMemcpyDeviceToHost ) ); /*In case of division of the original data, the temporary KNNs are being compared to form the final KNNs*/ if (nol!=1){ pi=nol*k; hipMemcpy( dev_n, &pi, sizeof(int), hipMemcpyHostToDevice ) ; knnSelection<<< numQueries, k>>>(d_NNdist, d_NNidx, d_tmpID, d_tmpDist, dev_n); CUDA_CHECK_RETURN( hipPeekAtLastError() ); } gettimeofday(&second, &tzp); printf("\n---KNN computed--- \n\n"); if(first.tv_usec>second.tv_usec){ second.tv_usec += 1000000; second.tv_sec--; } lapsed.tv_usec = second.tv_usec - first.tv_usec; lapsed.tv_sec = second.tv_sec - first.tv_sec; printf("Time elapsed: %ld, %ld s\n", lapsed.tv_sec, lapsed.tv_usec); CUDA_CHECK_RETURN( hipMemcpy( NNdist, d_NNdist, numQueries*k*sizeof(double), hipMemcpyDeviceToHost ) ); CUDA_CHECK_RETURN( hipMemcpy( NNidx, d_NNidx, numQueries*k*sizeof(int), hipMemcpyDeviceToHost ) ); save_d(query_set.data, query_file, numQueries, numDim); save_d(training_set.data, dataset_file, numObjects, numDim); save_d(NNdist, KNNdist_file, k, numQueries); save_int(NNidx, KNNidx_file, k, numQueries); /*===== clean memory ========*/ clean(&training_set); clean(&query_set); free(NNdist); free(NNidx); free(dist); hipFree(d_queries); hipFree(d_data); hipFree(d_NNdist); hipFree(d_NNidx); hipFree(dev_k); hipFree(dev_n); hipFree(d_dist); }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
/*Parallel and Distributed Systems --CUDA KNN Algorithm-- -Author: Mitsios Georgios -September 2014 */ #include <stdio.h> #include <stdlib.h> #include <time.h> #include <sys/time.h> #include <hip/hip_runtime.h> #include <float.h> #include <math.h> #define CUDA_CHECK_RETURN(value) { \ hipError_t _m_cudaStat = value; \ if (_m_cudaStat != hipSuccess) { \ fprintf(stderr, "Error %s at line %d in file %s\n", \ hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \ exit(1); \ } } typedef struct{ double *data; int leading_dim; int secondary_dim; } knn_struct; //1st input option. Random initialization void random_initialization(knn_struct *set, int cal){ int i = 0; int n = set->leading_dim; int m = set->secondary_dim; double *tmp_set = set->data; srand(cal*time(NULL)); /*Generate random floating points [-50 50]*/ for(i=0; i<m*n; i++){ tmp_set[i] = 100 * (double)rand() / RAND_MAX - 50; } } //2nd input option. Import data from benchmark files void initialize(knn_struct *set){ int i = 0; int n = set->leading_dim; int m = set->secondary_dim; float *tmp_set; double *tempArray; tmp_set = (float*)malloc(n*m*sizeof(float)); tempArray = (double*)malloc(n*m*sizeof(double)); FILE *fp; size_t t; if (m>100000){ if ((fp = fopen("baseREAD.bin", "rb")) == NULL){ printf("Can't open output file"); } } else{ if ((fp = fopen("queriesREAD.bin", "rb")) == NULL){ printf("Can't open output file"); } } t = fread(tmp_set, n*m, sizeof(float), fp); fclose(fp); //Convert float input data to doubles for (i=0;i<n*m;i++){ tempArray[i] = (double)tmp_set[i]; } set->data = tempArray; } //This function was used to normalize data from -50 to 50 to match the random points void input_normalisation(knn_struct *base, knn_struct *queries){ int i; int N = base->leading_dim, ni = queries->leading_dim; int M = base->secondary_dim, mi = queries->secondary_dim; double maxVal=0, minVal=1; double *tmp_data = base->data; double *tmp_queries = queries->data; for (i=0;i<N*M;i++){ if (tmp_data[i]>maxVal) { maxVal=tmp_data[i]; } if (tmp_data[i]<minVal) { minVal=tmp_data[i]; } } for (i=0;i<ni*mi;i++){ if (tmp_queries[i]>maxVal) { maxVal=tmp_queries[i]; } if (tmp_queries[i]<minVal) { minVal=tmp_queries[i]; } } if ( minVal<0 ) { minVal = minVal*(-1); } if ( minVal>maxVal) { maxVal = minVal; } for (i=0;i<N*M;i++){ tmp_data[i] = (tmp_data[i]*50)/maxVal; } for (i=0;i<ni*mi;i++){ tmp_queries[i] = (tmp_queries[i]*50)/maxVal; } } void save_d(double* data, char* file, int N, int M){ FILE *outfile; printf("Saving data to file: %s\n", file); if((outfile=fopen(file, "wb")) == NULL){ printf("Can't open output file"); } fwrite(data, sizeof(double), N*M, outfile); fclose(outfile); } void save_int(int* data, char* file, int N, int M){ FILE *outfile; printf("Saving data to file: %s\n", file); if((outfile=fopen(file, "wb")) == NULL){ printf("Can't open output file"); } fwrite(data, sizeof(int), N*M, outfile); fclose(outfile); } void clean(knn_struct* d){ free(d->data); } //This kernel function computes the euclidean distance between queries and objects __global__ void calculate_distance(double* queries, double* dataset, double *dist, int* k, int* n){ int numObj=*n; int index = threadIdx.x + blockIdx.x * blockDim.x; double tmp=0; //Initialize distances to 0 if (threadIdx.x == 0) { for (int i=0; i<numObj; i++){ dist[blockIdx.x*numObj + i] = 0; } } __syncthreads(); //Compute and store euclidean distance for (int ni=0;ni<(numObj);ni++){ tmp = (queries[index] - dataset[threadIdx.x + ni * blockDim.x])*(queries[index] - dataset[threadIdx.x + ni * blockDim.x]); dist[blockIdx.x * numObj + ni] = dist[blockIdx.x * numObj + ni] + tmp; __syncthreads(); } __syncthreads(); } /*This kernel function computes the knn of the temporary set of data (which is only a portion of the original data. The way this function works is better expalined in the report sheet*/ __global__ void compute_knn(double* NNdist, double* dist, int* numObj, int* NNidx, int* bonusID, int *offset, double *tmpDist, int *tmpID, int *N){ int i, n = *numObj, off = *offset, Nol= *N; int start = blockIdx.x * n; int index = threadIdx.x + blockIdx.x*blockDim.x; int position = blockDim.x+threadIdx.x+1; double temp=0; int tmp=0; NNdist[index] = DBL_MAX; NNidx[index] = (-1); bonusID[index] = (-1); __syncthreads(); for (i=start; i<(start+n+blockDim.x);i++){ if ( ((i-position)< (start +n)) && (i-position) >= start ){ if ( NNdist[index] > dist[i - position] ){ temp = NNdist[index]; NNdist[index] = dist[i - position]; dist[i - position] = temp; if (bonusID[index]>=0){ tmp = NNidx[index]; NNidx[index]=bonusID[index]; bonusID[index]= tmp; } else{ bonusID[index] = NNidx[index]; NNidx[index] = (i - position - start) + (off*n); } } __syncthreads(); } __syncthreads(); if (threadIdx.x == 7){ for (int j=0;j<(blockDim.x-1);j++){ bonusID[j+blockIdx.x*blockDim.x] = bonusID[j+blockIdx.x*blockDim.x +1]; } bonusID[index] = (-1); } __syncthreads(); } tmpDist[ off*blockDim.x + blockIdx.x*(Nol*blockDim.x) + threadIdx.x ] = NNdist[index]; tmpID[ off*blockDim.x + blockIdx.x*(Nol*blockDim.x) + threadIdx.x ] = NNidx[index]; __syncthreads(); } /*This is the last kernel function which compares the knns that have been computed from each group of data to find the final knn values and ids. The operation is similar to the "compute_knn" function*/ __global__ void knnSelection(double* NNdist, int* NNidx, int* originalID, double* dist, int* numObj){ int i, n=*numObj; int start = blockIdx.x * n; int index = threadIdx.x + blockIdx.x*blockDim.x; double temp=0; int tmp=0; NNdist[index] = DBL_MAX; NNidx[index] = (-1); __syncthreads(); for (i=start; i<(start+n+blockDim.x);i++){ if ( ((i-blockDim.x+threadIdx.x+1)< (start +n)) && (i-blockDim.x+threadIdx.x+1) >= start ){ if ( NNdist[index] > dist[i - blockDim.x + threadIdx.x + 1] ){ temp = NNdist[index]; NNdist[index] = dist[i - blockDim.x + threadIdx.x + 1]; dist[i - blockDim.x + threadIdx.x + 1] = temp; tmp = NNidx[index]; NNidx[index]=originalID[i - blockDim.x + threadIdx.x + 1]; originalID[i - blockDim.x + threadIdx.x + 1]= tmp; } } __syncthreads(); } __syncthreads(); } int main(int argc, char **argv){ struct timeval first, second, lapsed; struct timezone tzp; int i; int numObjects = atoi(argv[1]); //pow(2,atoi(argv[1])); int numDim = atoi(argv[2]); int numQueries = atoi(argv[3]); int k = atoi(argv[4]); int pi=pow(2,15); int pol; if (numObjects>pi ){pol=numObjects/pi;} else{ pol=1; pi=numObjects; } //Getting GPU memory's info size_t mem_tot_0 = 0; size_t mem_free_0 = 0; hipMemGetInfo(&mem_free_0, &mem_tot_0); size_t dist_size = numQueries*numObjects*sizeof(double); size_t data_size = numObjects*numDim*sizeof(double); size_t queries_size = numQueries*numDim*sizeof(double); size_t NNdist_size = numQueries*k*sizeof(double); size_t NNidx_size = numQueries*k*sizeof(int); size_t mem_req = dist_size + data_size + queries_size + NNdist_size + NNidx_size; size_t mem_req1 = dist_size + data_size; int nol; int ni; size_t mem_free_n = mem_free_0 - (queries_size -NNdist_size - NNidx_size); printf("\nGPU memory needed : %ld bytes \n", mem_req1); printf("Available GPU memory : %ld bytes \n", mem_free_n); //Computing the number of divisions to the data for proper memory usage if (mem_req> (mem_free_n ) ){ nol = (mem_req1/mem_free_n); int e=0; while (nol>2){ nol=nol/2; e++; } nol=pow(2,e+1); } else {nol=1;} //Value 500 can be reduced to 200 or even 100 for lower memory GPUs if (numQueries>500) { nol = nol*(numQueries/500); } ni = numObjects/nol; printf("Data will be divided into %d groups \n", nol); printf("of %d elements per group for optimal operation\n\n", ni); char *dataset_file = "training_set.bin"; char *query_file = "query_set.bin"; char *KNNdist_file = "KNNdist.bin"; char *KNNidx_file = "KNNidx.bin" ; double *tmpDist; int *tmpID; tmpDist = (double*)malloc(nol*numQueries*k*sizeof(double)); tmpID = (int*)malloc(nol*numQueries*k*sizeof(int)); printf("objects: %d\n", numObjects); printf("dimentions: %d\n", numDim); printf("queries: %d\n", numQueries); printf("k: %d\n", k); knn_struct training_set; knn_struct query_set; double *dist; double *NNdist; int *NNidx; training_set.leading_dim = numDim; training_set.secondary_dim = numObjects; query_set.leading_dim = numDim; query_set.secondary_dim = numQueries; /*======== Memory allocation ======*/ training_set.data = (double*)malloc(numObjects*numDim*sizeof(double)); query_set.data = (double*)malloc(numQueries*numDim*sizeof(double)); NNdist = (double*)malloc(numQueries*k*sizeof(double)); NNidx = (int*)malloc(numQueries*k*sizeof(int)); dist = (double*)malloc(numObjects*numQueries*sizeof(double)); double *d_data; double *d_queries; double *d_dist; double *d_NNdist; int *d_NNidx; int *d_bonusID; int *dev_k, *dev_n; int *dev_nol; double *d_tmpDist; int *d_tmpID; //GPU memory allocation CUDA_CHECK_RETURN(hipMalloc( (void **)&d_data, ni*numDim*sizeof(double)) ); CUDA_CHECK_RETURN(hipMalloc( (void **)&d_queries, numQueries*numDim*sizeof(double)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&d_NNdist, numQueries*k*sizeof(double)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&d_NNidx, numQueries*k*sizeof(int)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&d_bonusID, numQueries*k*sizeof(int)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&d_tmpDist, nol*numQueries*k*sizeof(double)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&d_tmpID, nol*numQueries*k*sizeof(int)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&d_dist, numQueries*ni*sizeof(double)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&dev_k, sizeof(int)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&dev_n, sizeof(int)) ); CUDA_CHECK_RETURN( hipMalloc( (void **)&dev_nol, sizeof(int)) ); /*======== initialize =========*/ //Input option 1. Create random data random_initialization(&training_set, 1); random_initialization(&query_set, 2); //Input option 2. Import data from file //initialize(&training_set); //initialize(&query_set); /*The following function was used to normalize imported data values from benchmark files to be from -50 to 50, because there was some undefined error in previous compilations. It MAY OR MAY NOT BE USED */ //input_normalisation(&training_set, &query_set); //Copy data to GPU memory CUDA_CHECK_RETURN(hipMemcpy( d_queries, query_set.data, numQueries*numDim*sizeof(double), hipMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(hipMemcpy( dev_k, &k, sizeof(int), hipMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(hipMemcpy( dev_nol, &nol, sizeof(int), hipMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(hipMemcpy( dev_n, &ni, sizeof(int), hipMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(hipMemcpy( d_tmpDist, tmpDist, nol*numQueries*k*sizeof(double), hipMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(hipMemcpy( d_tmpID, tmpID, nol*numQueries*k*sizeof(int), hipMemcpyHostToDevice ) ); CUDA_CHECK_RETURN(hipMemcpy( d_dist, dist, numQueries*ni*sizeof(double), hipMemcpyHostToDevice ) ); int offset=0; int *dev_off=0; CUDA_CHECK_RETURN( hipMalloc( (void **)&dev_off, sizeof(int)) ); gettimeofday(&first, &tzp); /*This for loop is the core of the program. It sends each group of data to the GPU where it computes the distances between each query and each object. Then calls the "compute_knn" kernel function to find the actual KNNs*/ for ( offset=0 ; offset<nol ; offset++ ){ CUDA_CHECK_RETURN(hipMemcpy( d_data, (training_set.data +offset*ni), ni*numDim*sizeof(double), hipMemcpyHostToDevice ) ); calculate_distance<<< numQueries, numDim>>> ( d_queries, d_data, d_dist, dev_k, dev_n); CUDA_CHECK_RETURN( hipPeekAtLastError() ); CUDA_CHECK_RETURN( hipDeviceSynchronize() ); CUDA_CHECK_RETURN(hipMemcpy( dev_off, &offset, sizeof(int), hipMemcpyHostToDevice ) ); compute_knn<<< numQueries, k>>>(d_NNdist, d_dist, dev_n, d_NNidx, d_bonusID, dev_off, d_tmpDist, d_tmpID, dev_nol); CUDA_CHECK_RETURN( hipPeekAtLastError() ); CUDA_CHECK_RETURN( hipDeviceSynchronize() ); } CUDA_CHECK_RETURN(hipMemcpy( tmpDist, d_tmpDist, nol*numQueries*k*sizeof(double), hipMemcpyDeviceToHost ) ); CUDA_CHECK_RETURN(hipMemcpy( tmpID, d_tmpID, nol*numQueries*k*sizeof(int), hipMemcpyDeviceToHost ) ); /*In case of division of the original data, the temporary KNNs are being compared to form the final KNNs*/ if (nol!=1){ pi=nol*k; hipMemcpy( dev_n, &pi, sizeof(int), hipMemcpyHostToDevice ) ; knnSelection<<< numQueries, k>>>(d_NNdist, d_NNidx, d_tmpID, d_tmpDist, dev_n); CUDA_CHECK_RETURN( hipPeekAtLastError() ); } gettimeofday(&second, &tzp); printf("\n---KNN computed--- \n\n"); if(first.tv_usec>second.tv_usec){ second.tv_usec += 1000000; second.tv_sec--; } lapsed.tv_usec = second.tv_usec - first.tv_usec; lapsed.tv_sec = second.tv_sec - first.tv_sec; printf("Time elapsed: %ld, %ld s\n", lapsed.tv_sec, lapsed.tv_usec); CUDA_CHECK_RETURN( hipMemcpy( NNdist, d_NNdist, numQueries*k*sizeof(double), hipMemcpyDeviceToHost ) ); CUDA_CHECK_RETURN( hipMemcpy( NNidx, d_NNidx, numQueries*k*sizeof(int), hipMemcpyDeviceToHost ) ); save_d(query_set.data, query_file, numQueries, numDim); save_d(training_set.data, dataset_file, numObjects, numDim); save_d(NNdist, KNNdist_file, k, numQueries); save_int(NNidx, KNNidx_file, k, numQueries); /*===== clean memory ========*/ clean(&training_set); clean(&query_set); free(NNdist); free(NNidx); free(dist); hipFree(d_queries); hipFree(d_data); hipFree(d_NNdist); hipFree(d_NNidx); hipFree(dev_k); hipFree(dev_n); hipFree(d_dist); }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z18calculate_distancePdS_S_PiS0_ .globl _Z18calculate_distancePdS_S_PiS0_ .p2align 8 .type _Z18calculate_distancePdS_S_PiS0_,@function _Z18calculate_distancePdS_S_PiS0_: s_clause 0x1 s_load_b64 s[2:3], s[0:1], 0x20 s_load_b32 s7, s[0:1], 0x34 v_cmp_eq_u32_e32 vcc_lo, 0, v0 s_waitcnt lgkmcnt(0) s_load_b32 s8, s[2:3], 0x0 s_load_b64 s[4:5], s[0:1], 0x10 s_mov_b32 s3, 0 s_waitcnt lgkmcnt(0) s_cmp_gt_i32 s8, 0 s_cselect_b32 s2, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s6, s2 s_cbranch_execz .LBB0_3 v_mov_b32_e32 v3, 0 v_mov_b32_e32 v1, 0 s_mul_i32 s2, s8, s15 s_mov_b32 s9, s8 .LBB0_2: s_lshl_b64 s[10:11], s[2:3], 3 s_delay_alu instid0(VALU_DEP_1) v_mov_b32_e32 v2, v1 s_add_u32 s10, s4, s10 s_addc_u32 s11, s5, s11 s_add_i32 s9, s9, -1 s_add_i32 s2, s2, 1 s_cmp_lg_u32 s9, 0 global_store_b64 v3, v[1:2], s[10:11] s_cbranch_scc1 .LBB0_2 .LBB0_3: s_or_b32 exec_lo, exec_lo, s6 s_mul_i32 s6, s8, s15 s_cmp_lt_i32 s8, 1 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_6 s_and_b32 s9, 0xffff, s7 s_load_b128 s[0:3], s[0:1], 0x0 v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1] v_mov_b32_e32 v4, 0 s_mov_b32 s7, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 v_lshlrev_b64 v[2:3], 3, v[1:2] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s0, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo .p2align 6 .LBB0_5: v_mov_b32_e32 v1, 0 s_lshl_b64 s[0:1], s[6:7], 3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) s_add_u32 s0, s4, s0 s_addc_u32 s1, s5, s1 v_lshlrev_b64 v[5:6], 3, v[0:1] v_add_nc_u32_e32 v0, s9, v0 s_add_i32 s8, s8, -1 s_add_i32 s6, s6, 1 s_cmp_eq_u32 s8, 0 s_delay_alu instid0(VALU_DEP_2) v_add_co_u32 v5, vcc_lo, s2, v5 v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo global_load_b64 v[7:8], v[2:3], off global_load_b64 v[5:6], v[5:6], off global_load_b64 v[9:10], v4, s[0:1] s_waitcnt vmcnt(1) v_add_f64 v[5:6], v[7:8], -v[5:6] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[5:6], v[5:6], v[5:6], v[9:10] global_store_b64 v4, v[5:6], s[0:1] s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB0_5 .LBB0_6: s_barrier buffer_gl0_inv s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z18calculate_distancePdS_S_PiS0_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 11 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z18calculate_distancePdS_S_PiS0_, .Lfunc_end0-_Z18calculate_distancePdS_S_PiS0_ .section .AMDGPU.csdata,"",@progbits .text .protected _Z11compute_knnPdS_PiS0_S0_S0_S_S0_S0_ .globl _Z11compute_knnPdS_PiS0_S0_S0_S_S0_S0_ .p2align 8 .type _Z11compute_knnPdS_PiS0_S0_S0_S_S0_S0_,@function _Z11compute_knnPdS_PiS0_S0_S0_S_S0_S0_: s_clause 0x2 s_load_b256 s[4:11], s[0:1], 0x10 s_load_b32 s2, s[0:1], 0x54 s_load_b64 s[18:19], s[0:1], 0x40 v_mov_b32_e32 v7, -1 s_waitcnt lgkmcnt(0) s_load_b32 s3, s[4:5], 0x0 s_load_b64 s[4:5], s[0:1], 0x0 s_and_b32 s12, s2, 0xffff s_load_b32 s13, s[10:11], 0x0 s_load_b32 s14, s[18:19], 0x0 s_mul_i32 s16, s15, s12 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_mov_b32 v8, 0x7fefffff :: v_dual_add_nc_u32 v1, s16, v0 v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_lshlrev_b64 v[3:4], 3, v[1:2] v_lshlrev_b64 v[5:6], 2, v[1:2] s_waitcnt lgkmcnt(0) s_mul_i32 s17, s3, s15 v_add_co_u32 v3, vcc_lo, s4, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo v_add_co_u32 v1, vcc_lo, s6, v5 v_add_co_ci_u32_e32 v2, vcc_lo, s7, v6, vcc_lo v_add_co_u32 v5, vcc_lo, s8, v5 s_add_i32 s18, s17, s3 v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo s_add_i32 s19, s18, s12 global_store_b64 v[3:4], v[7:8], off global_store_b32 v[1:2], v7, off global_store_b32 v[5:6], v7, off s_cmp_ge_u32 s17, s19 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB1_14 s_load_b64 s[4:5], s[0:1], 0x8 v_dual_mov_b32 v16, -1 :: v_dual_add_nc_u32 v7, s12, v0 s_add_i32 s20, s12, -1 s_sub_i32 s22, s13, s15 v_cmp_eq_u32_e64 s2, 7, v0 s_delay_alu instid0(VALU_DEP_2) v_not_b32_e32 v14, v7 v_mov_b32_e32 v15, 0 s_cmp_lg_u32 s20, 0 s_mul_i32 s22, s22, s3 s_cselect_b32 s21, -1, 0 s_mov_b32 s7, 0 s_mov_b32 s23, s17 s_branch .LBB1_4 .LBB1_2: global_store_b32 v[5:6], v16, off .LBB1_3: s_or_b32 exec_lo, exec_lo, s3 s_add_i32 s23, s23, 1 s_waitcnt_vscnt null, 0x0 s_cmp_lg_u32 s23, s19 s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB1_14 .LBB1_4: v_add_nc_u32_e32 v7, s23, v14 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_i32_e32 vcc_lo, s18, v7 v_cmp_le_i32_e64 s3, s17, v7 s_and_b32 s6, vcc_lo, s3 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s6 s_cbranch_execz .LBB1_11 v_ashrrev_i32_e32 v8, 31, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[8:9], 3, v[7:8] s_waitcnt lgkmcnt(0) v_add_co_u32 v8, vcc_lo, s4, v8 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo global_load_b64 v[10:11], v[3:4], off global_load_b64 v[12:13], v[8:9], off s_waitcnt vmcnt(0) v_cmp_gt_f64_e32 vcc_lo, v[10:11], v[12:13] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB1_10 global_load_b32 v18, v[5:6], off global_load_b32 v17, v[1:2], off s_mov_b32 s6, exec_lo global_store_b64 v[3:4], v[12:13], off global_store_b64 v[8:9], v[10:11], off s_waitcnt vmcnt(1) v_cmpx_gt_i32_e32 0, v18 s_xor_b32 s6, exec_lo, s6 s_cbranch_execz .LBB1_8 v_add_nc_u32_e32 v7, s22, v7 s_waitcnt vmcnt(0) global_store_b32 v[5:6], v17, off global_store_b32 v[1:2], v7, off .LBB1_8: s_and_not1_saveexec_b32 s6, s6 s_cbranch_execz .LBB1_10 global_store_b32 v[1:2], v18, off s_waitcnt vmcnt(0) global_store_b32 v[5:6], v17, off .LBB1_10: s_waitcnt vmcnt(0) s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv .LBB1_11: s_or_b32 exec_lo, exec_lo, s3 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB1_3 s_and_not1_b32 vcc_lo, exec_lo, s21 s_mov_b32 s10, s16 s_mov_b32 s24, s20 s_cbranch_vccnz .LBB1_2 .p2align 6 .LBB1_13: s_add_i32 s6, s10, 1 s_mov_b32 s11, s7 s_lshl_b64 s[26:27], s[6:7], 2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s26, s8, s26 s_addc_u32 s27, s9, s27 s_lshl_b64 s[10:11], s[10:11], 2 global_load_b32 v7, v15, s[26:27] s_add_u32 s26, s8, s10 s_addc_u32 s27, s9, s11 s_add_i32 s24, s24, -1 s_mov_b32 s10, s6 s_cmp_eq_u32 s24, 0 s_waitcnt vmcnt(0) global_store_b32 v15, v7, s[26:27] s_cbranch_scc0 .LBB1_13 s_branch .LBB1_2 .LBB1_14: global_load_b64 v[3:4], v[3:4], off global_load_b32 v7, v[1:2], off s_load_b128 s[0:3], s[0:1], 0x30 s_mul_i32 s4, s14, s15 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s4, s4, s13 v_mad_u64_u32 v[1:2], null, s4, s12, v[0:1] v_mov_b32_e32 v2, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_lshlrev_b64 v[5:6], 3, v[1:2] v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v5, vcc_lo, s0, v5 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo v_add_co_u32 v0, vcc_lo, s2, v0 s_delay_alu instid0(VALU_DEP_4) v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo s_waitcnt vmcnt(1) global_store_b64 v[5:6], v[3:4], off s_waitcnt vmcnt(0) global_store_b32 v[0:1], v7, off s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11compute_knnPdS_PiS0_S0_S0_S_S0_S0_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 328 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 19 .amdhsa_next_free_sgpr 28 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z11compute_knnPdS_PiS0_S0_S0_S_S0_S0_, .Lfunc_end1-_Z11compute_knnPdS_PiS0_S0_S0_S_S0_S0_ .section .AMDGPU.csdata,"",@progbits .text .protected _Z12knnSelectionPdPiS0_S_S0_ .globl _Z12knnSelectionPdPiS0_S_S0_ .p2align 8 .type _Z12knnSelectionPdPiS0_S_S0_,@function _Z12knnSelectionPdPiS0_S_S0_: s_clause 0x2 s_load_b64 s[2:3], s[0:1], 0x20 s_load_b32 s9, s[0:1], 0x34 s_load_b128 s[4:7], s[0:1], 0x0 v_dual_mov_b32 v5, -1 :: v_dual_mov_b32 v6, 0x7fefffff s_waitcnt lgkmcnt(0) s_load_b32 s8, s[2:3], 0x0 s_and_b32 s9, s9, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_lshlrev_b64 v[3:4], 3, v[1:2] v_lshlrev_b64 v[7:8], 2, v[1:2] s_waitcnt lgkmcnt(0) s_mul_i32 s2, s8, s15 v_add_co_u32 v1, vcc_lo, s4, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e32 v2, vcc_lo, s5, v4, vcc_lo v_add_co_u32 v3, vcc_lo, s6, v7 s_add_i32 s3, s2, s8 v_add_co_ci_u32_e32 v4, vcc_lo, s7, v8, vcc_lo s_add_i32 s4, s3, s9 global_store_b64 v[1:2], v[5:6], off global_store_b32 v[3:4], v5, off s_cmp_ge_u32 s2, s4 s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB2_6 s_load_b128 s[4:7], s[0:1], 0x10 v_add_nc_u32_e32 v0, s2, v0 s_add_i32 s1, s8, s9 v_mov_b32_e32 v6, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_subrev_nc_u32_e32 v0, s9, v0 v_add_nc_u32_e32 v5, 1, v0 s_set_inst_prefetch_distance 0x1 s_branch .LBB2_3 .p2align 6 .LBB2_2: s_or_b32 exec_lo, exec_lo, s0 v_add_nc_u32_e32 v5, 1, v5 s_add_i32 s1, s1, -1 s_waitcnt lgkmcnt(0) s_waitcnt_vscnt null, 0x0 s_cmp_lg_u32 s1, 0 s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB2_6 .LBB2_3: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_cmp_gt_u32_e32 vcc_lo, s3, v5 v_cmp_le_u32_e64 s0, s2, v5 s_and_b32 s8, vcc_lo, s0 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s0, s8 s_cbranch_execz .LBB2_2 v_lshlrev_b64 v[7:8], 3, v[5:6] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v7, vcc_lo, s6, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo global_load_b64 v[9:10], v[1:2], off global_load_b64 v[11:12], v[7:8], off s_waitcnt vmcnt(0) v_cmp_gt_f64_e32 vcc_lo, v[9:10], v[11:12] s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB2_2 v_lshlrev_b64 v[13:14], 2, v[5:6] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v13, vcc_lo, s4, v13 v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo global_load_b32 v0, v[13:14], off global_load_b32 v15, v[3:4], off global_store_b64 v[1:2], v[11:12], off global_store_b64 v[7:8], v[9:10], off s_waitcnt vmcnt(1) global_store_b32 v[3:4], v0, off s_waitcnt vmcnt(0) global_store_b32 v[13:14], v15, off s_branch .LBB2_2 .LBB2_6: s_set_inst_prefetch_distance 0x2 s_barrier buffer_gl0_inv s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z12knnSelectionPdPiS0_S_S0_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 16 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end2: .size _Z12knnSelectionPdPiS0_S_S0_, .Lfunc_end2-_Z12knnSelectionPdPiS0_S_S0_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z18calculate_distancePdS_S_PiS0_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z18calculate_distancePdS_S_PiS0_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 11 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 56 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .offset: 72 .size: 4 .value_kind: hidden_block_count_x - .offset: 76 .size: 4 .value_kind: hidden_block_count_y - .offset: 80 .size: 4 .value_kind: hidden_block_count_z - .offset: 84 .size: 2 .value_kind: hidden_group_size_x - .offset: 86 .size: 2 .value_kind: hidden_group_size_y - .offset: 88 .size: 2 .value_kind: hidden_group_size_z - .offset: 90 .size: 2 .value_kind: hidden_remainder_x - .offset: 92 .size: 2 .value_kind: hidden_remainder_y - .offset: 94 .size: 2 .value_kind: hidden_remainder_z - .offset: 112 .size: 8 .value_kind: hidden_global_offset_x - .offset: 120 .size: 8 .value_kind: hidden_global_offset_y - .offset: 128 .size: 8 .value_kind: hidden_global_offset_z - .offset: 136 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 328 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11compute_knnPdS_PiS0_S0_S0_S_S0_S0_ .private_segment_fixed_size: 0 .sgpr_count: 30 .sgpr_spill_count: 0 .symbol: _Z11compute_knnPdS_PiS0_S0_S0_S_S0_S0_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 19 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z12knnSelectionPdPiS0_S_S0_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z12knnSelectionPdPiS0_S_S0_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 16 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
/* This is a automatically generated test. Do not modify */ #include <stdio.h> #include <stdlib.h> #include <math.h> __global__ void compute(float comp, int var_1,int var_2,float var_3,float var_4,int var_5,float var_6,float var_7,float var_8,float var_9,float var_10) { if (comp == (+1.1633E-35f / ceilf(var_3 / +1.3331E35f * var_4))) { for (int i=0; i < var_1; ++i) { for (int i=0; i < var_2; ++i) { comp = floorf(-1.1702E36f); for (int i=0; i < var_5; ++i) { comp = logf((+0.0f * (var_6 / (var_7 - -0.0f / -1.0583E13f)))); } if (comp == (-1.2608E34f - var_8)) { float tmp_1 = +1.3991E35f; float tmp_2 = +0.0f / (+1.4080E-43f + var_9); comp = tmp_2 / tmp_1 / sqrtf((-1.7990E36f / var_10)); } } } } printf("%.17g\n", comp); } float* initPointer(float v) { float *ret = (float*) malloc(sizeof(float)*10); for(int i=0; i < 10; ++i) ret[i] = v; return ret; } int main(int argc, char** argv) { /* Program variables */ float tmp_1 = atof(argv[1]); int tmp_2 = atoi(argv[2]); int tmp_3 = atoi(argv[3]); float tmp_4 = atof(argv[4]); float tmp_5 = atof(argv[5]); int tmp_6 = atoi(argv[6]); float tmp_7 = atof(argv[7]); float tmp_8 = atof(argv[8]); float tmp_9 = atof(argv[9]); float tmp_10 = atof(argv[10]); float tmp_11 = atof(argv[11]); compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11); cudaDeviceSynchronize(); return 0; }
.file "tmpxft_0007f4bb_00000000-6_test.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z11initPointerf .type _Z11initPointerf, @function _Z11initPointerf: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movd %xmm0, %ebx movl $40, %edi call malloc@PLT movq %rax, %rdx leaq 40(%rax), %rcx .L4: movl %ebx, (%rdx) addq $4, %rdx cmpq %rcx, %rdx jne .L4 popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z11initPointerf, .-_Z11initPointerf .globl _Z35__device_stub__Z7computefiiffiffffffiiffifffff .type _Z35__device_stub__Z7computefiiffiffffffiiffifffff, @function _Z35__device_stub__Z7computefiiffiffffffiiffifffff: .LFB2083: .cfi_startproc endbr64 subq $216, %rsp .cfi_def_cfa_offset 224 movss %xmm0, 44(%rsp) movl %edi, 40(%rsp) movl %esi, 36(%rsp) movss %xmm1, 32(%rsp) movss %xmm2, 28(%rsp) movl %edx, 24(%rsp) movss %xmm3, 20(%rsp) movss %xmm4, 16(%rsp) movss %xmm5, 12(%rsp) movss %xmm6, 8(%rsp) movss %xmm7, 4(%rsp) movq %fs:40, %rax movq %rax, 200(%rsp) xorl %eax, %eax leaq 44(%rsp), %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rax movq %rax, 120(%rsp) leaq 36(%rsp), %rax movq %rax, 128(%rsp) leaq 32(%rsp), %rax movq %rax, 136(%rsp) leaq 28(%rsp), %rax movq %rax, 144(%rsp) leaq 24(%rsp), %rax movq %rax, 152(%rsp) leaq 20(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 12(%rsp), %rax movq %rax, 176(%rsp) leaq 8(%rsp), %rax movq %rax, 184(%rsp) leaq 4(%rsp), %rax movq %rax, 192(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 200(%rsp), %rax subq %fs:40, %rax jne .L12 addq $216, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 232 pushq 56(%rsp) .cfi_def_cfa_offset 240 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z7computefiiffifffff(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 224 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z35__device_stub__Z7computefiiffiffffffiiffifffff, .-_Z35__device_stub__Z7computefiiffiffffffiiffifffff .globl _Z7computefiiffifffff .type _Z7computefiiffifffff, @function _Z7computefiiffifffff: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z7computefiiffiffffffiiffifffff addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z7computefiiffifffff, .-_Z7computefiiffifffff .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $104, %rsp .cfi_def_cfa_offset 144 movq %rsi, %rbx movq 8(%rsi), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 56(%rsp) movq 16(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %rbp movq 24(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %r12 movq 32(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 48(%rsp) movq 40(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 40(%rsp) movq 48(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %r13 movq 56(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 32(%rsp) movq 64(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 24(%rsp) movq 72(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 16(%rsp) movq 80(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 8(%rsp) movq 88(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, (%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $0, %r9d movl $0, %r8d movq 84(%rsp), %rdx movl $1, %ecx movq 72(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L18 .L16: call cudaDeviceSynchronize@PLT movl $0, %eax addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L18: .cfi_restore_state pxor %xmm0, %xmm0 cvtsd2ss 56(%rsp), %xmm0 pxor %xmm7, %xmm7 cvtsd2ss (%rsp), %xmm7 pxor %xmm6, %xmm6 cvtsd2ss 8(%rsp), %xmm6 pxor %xmm5, %xmm5 cvtsd2ss 16(%rsp), %xmm5 pxor %xmm4, %xmm4 cvtsd2ss 24(%rsp), %xmm4 pxor %xmm3, %xmm3 cvtsd2ss 32(%rsp), %xmm3 movl %r13d, %edx pxor %xmm2, %xmm2 cvtsd2ss 40(%rsp), %xmm2 pxor %xmm1, %xmm1 cvtsd2ss 48(%rsp), %xmm1 movl %r12d, %esi movl %ebp, %edi call _Z35__device_stub__Z7computefiiffiffffffiiffifffff jmp .L16 .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z7computefiiffifffff" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z7computefiiffifffff(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
/* This is a automatically generated test. Do not modify */ #include <stdio.h> #include <stdlib.h> #include <math.h> __global__ void compute(float comp, int var_1,int var_2,float var_3,float var_4,int var_5,float var_6,float var_7,float var_8,float var_9,float var_10) { if (comp == (+1.1633E-35f / ceilf(var_3 / +1.3331E35f * var_4))) { for (int i=0; i < var_1; ++i) { for (int i=0; i < var_2; ++i) { comp = floorf(-1.1702E36f); for (int i=0; i < var_5; ++i) { comp = logf((+0.0f * (var_6 / (var_7 - -0.0f / -1.0583E13f)))); } if (comp == (-1.2608E34f - var_8)) { float tmp_1 = +1.3991E35f; float tmp_2 = +0.0f / (+1.4080E-43f + var_9); comp = tmp_2 / tmp_1 / sqrtf((-1.7990E36f / var_10)); } } } } printf("%.17g\n", comp); } float* initPointer(float v) { float *ret = (float*) malloc(sizeof(float)*10); for(int i=0; i < 10; ++i) ret[i] = v; return ret; } int main(int argc, char** argv) { /* Program variables */ float tmp_1 = atof(argv[1]); int tmp_2 = atoi(argv[2]); int tmp_3 = atoi(argv[3]); float tmp_4 = atof(argv[4]); float tmp_5 = atof(argv[5]); int tmp_6 = atoi(argv[6]); float tmp_7 = atof(argv[7]); float tmp_8 = atof(argv[8]); float tmp_9 = atof(argv[9]); float tmp_10 = atof(argv[10]); float tmp_11 = atof(argv[11]); compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11); cudaDeviceSynchronize(); return 0; }
/* This is a automatically generated test. Do not modify */ #include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <math.h> __global__ void compute(float comp, int var_1,int var_2,float var_3,float var_4,int var_5,float var_6,float var_7,float var_8,float var_9,float var_10) { if (comp == (+1.1633E-35f / ceilf(var_3 / +1.3331E35f * var_4))) { for (int i=0; i < var_1; ++i) { for (int i=0; i < var_2; ++i) { comp = floorf(-1.1702E36f); for (int i=0; i < var_5; ++i) { comp = logf((+0.0f * (var_6 / (var_7 - -0.0f / -1.0583E13f)))); } if (comp == (-1.2608E34f - var_8)) { float tmp_1 = +1.3991E35f; float tmp_2 = +0.0f / (+1.4080E-43f + var_9); comp = tmp_2 / tmp_1 / sqrtf((-1.7990E36f / var_10)); } } } } printf("%.17g\n", comp); } float* initPointer(float v) { float *ret = (float*) malloc(sizeof(float)*10); for(int i=0; i < 10; ++i) ret[i] = v; return ret; } int main(int argc, char** argv) { /* Program variables */ float tmp_1 = atof(argv[1]); int tmp_2 = atoi(argv[2]); int tmp_3 = atoi(argv[3]); float tmp_4 = atof(argv[4]); float tmp_5 = atof(argv[5]); int tmp_6 = atoi(argv[6]); float tmp_7 = atof(argv[7]); float tmp_8 = atof(argv[8]); float tmp_9 = atof(argv[9]); float tmp_10 = atof(argv[10]); float tmp_11 = atof(argv[11]); compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11); hipDeviceSynchronize(); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
/* This is a automatically generated test. Do not modify */ #include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <math.h> __global__ void compute(float comp, int var_1,int var_2,float var_3,float var_4,int var_5,float var_6,float var_7,float var_8,float var_9,float var_10) { if (comp == (+1.1633E-35f / ceilf(var_3 / +1.3331E35f * var_4))) { for (int i=0; i < var_1; ++i) { for (int i=0; i < var_2; ++i) { comp = floorf(-1.1702E36f); for (int i=0; i < var_5; ++i) { comp = logf((+0.0f * (var_6 / (var_7 - -0.0f / -1.0583E13f)))); } if (comp == (-1.2608E34f - var_8)) { float tmp_1 = +1.3991E35f; float tmp_2 = +0.0f / (+1.4080E-43f + var_9); comp = tmp_2 / tmp_1 / sqrtf((-1.7990E36f / var_10)); } } } } printf("%.17g\n", comp); } float* initPointer(float v) { float *ret = (float*) malloc(sizeof(float)*10); for(int i=0; i < 10; ++i) ret[i] = v; return ret; } int main(int argc, char** argv) { /* Program variables */ float tmp_1 = atof(argv[1]); int tmp_2 = atoi(argv[2]); int tmp_3 = atoi(argv[3]); float tmp_4 = atof(argv[4]); float tmp_5 = atof(argv[5]); int tmp_6 = atoi(argv[6]); float tmp_7 = atof(argv[7]); float tmp_8 = atof(argv[8]); float tmp_9 = atof(argv[9]); float tmp_10 = atof(argv[10]); float tmp_11 = atof(argv[11]); compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11); hipDeviceSynchronize(); return 0; }
.text .file "test.hip" .globl _Z22__device_stub__computefiiffifffff # -- Begin function _Z22__device_stub__computefiiffifffff .p2align 4, 0x90 .type _Z22__device_stub__computefiiffifffff,@function _Z22__device_stub__computefiiffifffff: # @_Z22__device_stub__computefiiffifffff .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movss %xmm0, 44(%rsp) movl %edi, 40(%rsp) movl %esi, 36(%rsp) movss %xmm1, 32(%rsp) movss %xmm2, 28(%rsp) movl %edx, 24(%rsp) movss %xmm3, 20(%rsp) movss %xmm4, 16(%rsp) movss %xmm5, 12(%rsp) movss %xmm6, 8(%rsp) movss %xmm7, 4(%rsp) leaq 44(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rax movq %rax, 104(%rsp) leaq 36(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 28(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 20(%rsp), %rax movq %rax, 144(%rsp) leaq 16(%rsp), %rax movq %rax, 152(%rsp) leaq 12(%rsp), %rax movq %rax, 160(%rsp) leaq 8(%rsp), %rax movq %rax, 168(%rsp) leaq 4(%rsp), %rax movq %rax, 176(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi leaq 56(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z7computefiiffifffff, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end0: .size _Z22__device_stub__computefiiffifffff, .Lfunc_end0-_Z22__device_stub__computefiiffifffff .cfi_endproc # -- End function .globl _Z11initPointerf # -- Begin function _Z11initPointerf .p2align 4, 0x90 .type _Z11initPointerf,@function _Z11initPointerf: # @_Z11initPointerf .cfi_startproc # %bb.0: pushq %rax .cfi_def_cfa_offset 16 movss %xmm0, 4(%rsp) # 4-byte Spill movl $40, %edi callq malloc movss 4(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movss %xmm0, (%rax,%rcx,4) incq %rcx cmpq $10, %rcx jne .LBB1_1 # %bb.2: popq %rcx .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $248, %rsp .cfi_def_cfa_offset 288 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rsi, %r15 movq 8(%rsi), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 104(%rsp) # 8-byte Spill movq 16(%r15), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %rbx movq 24(%r15), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r14 movq 32(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 96(%rsp) # 8-byte Spill movq 40(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 88(%rsp) # 8-byte Spill movq 48(%r15), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r12 movq 56(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 80(%rsp) # 8-byte Spill movq 64(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 72(%rsp) # 8-byte Spill movq 72(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 64(%rsp) # 8-byte Spill movq 80(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 56(%rsp) # 8-byte Spill movq 88(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 48(%rsp) # 8-byte Spill movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: movsd 48(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movsd 56(%rsp), %xmm1 # 8-byte Reload # xmm1 = mem[0],zero cvtsd2ss %xmm1, %xmm1 movsd 64(%rsp), %xmm2 # 8-byte Reload # xmm2 = mem[0],zero cvtsd2ss %xmm2, %xmm2 movsd 72(%rsp), %xmm3 # 8-byte Reload # xmm3 = mem[0],zero cvtsd2ss %xmm3, %xmm3 movsd 80(%rsp), %xmm4 # 8-byte Reload # xmm4 = mem[0],zero cvtsd2ss %xmm4, %xmm4 movsd 88(%rsp), %xmm5 # 8-byte Reload # xmm5 = mem[0],zero cvtsd2ss %xmm5, %xmm5 movsd 96(%rsp), %xmm6 # 8-byte Reload # xmm6 = mem[0],zero cvtsd2ss %xmm6, %xmm6 movsd 104(%rsp), %xmm7 # 8-byte Reload # xmm7 = mem[0],zero cvtsd2ss %xmm7, %xmm7 movss %xmm7, 44(%rsp) movl %ebx, 40(%rsp) movl %r14d, 36(%rsp) movss %xmm6, 32(%rsp) movss %xmm5, 28(%rsp) movl %r12d, 24(%rsp) movss %xmm4, 20(%rsp) movss %xmm3, 16(%rsp) movss %xmm2, 12(%rsp) movss %xmm1, 8(%rsp) movss %xmm0, 4(%rsp) leaq 44(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 36(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 28(%rsp), %rax movq %rax, 192(%rsp) leaq 24(%rsp), %rax movq %rax, 200(%rsp) leaq 20(%rsp), %rax movq %rax, 208(%rsp) leaq 16(%rsp), %rax movq %rax, 216(%rsp) leaq 12(%rsp), %rax movq %rax, 224(%rsp) leaq 8(%rsp), %rax movq %rax, 232(%rsp) leaq 4(%rsp), %rax movq %rax, 240(%rsp) leaq 144(%rsp), %rdi leaq 128(%rsp), %rsi leaq 120(%rsp), %rdx leaq 112(%rsp), %rcx callq __hipPopCallConfiguration movq 144(%rsp), %rsi movl 152(%rsp), %edx movq 128(%rsp), %rcx movl 136(%rsp), %r8d leaq 160(%rsp), %r9 movl $_Z7computefiiffifffff, %edi pushq 112(%rsp) .cfi_adjust_cfa_offset 8 pushq 128(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_2: callq hipDeviceSynchronize xorl %eax, %eax addq $248, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7computefiiffifffff, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z7computefiiffifffff,@object # @_Z7computefiiffifffff .section .rodata,"a",@progbits .globl _Z7computefiiffifffff .p2align 3, 0x0 _Z7computefiiffifffff: .quad _Z22__device_stub__computefiiffifffff .size _Z7computefiiffifffff, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z7computefiiffifffff" .size .L__unnamed_1, 22 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__computefiiffifffff .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7computefiiffifffff .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0007f4bb_00000000-6_test.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z11initPointerf .type _Z11initPointerf, @function _Z11initPointerf: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movd %xmm0, %ebx movl $40, %edi call malloc@PLT movq %rax, %rdx leaq 40(%rax), %rcx .L4: movl %ebx, (%rdx) addq $4, %rdx cmpq %rcx, %rdx jne .L4 popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z11initPointerf, .-_Z11initPointerf .globl _Z35__device_stub__Z7computefiiffiffffffiiffifffff .type _Z35__device_stub__Z7computefiiffiffffffiiffifffff, @function _Z35__device_stub__Z7computefiiffiffffffiiffifffff: .LFB2083: .cfi_startproc endbr64 subq $216, %rsp .cfi_def_cfa_offset 224 movss %xmm0, 44(%rsp) movl %edi, 40(%rsp) movl %esi, 36(%rsp) movss %xmm1, 32(%rsp) movss %xmm2, 28(%rsp) movl %edx, 24(%rsp) movss %xmm3, 20(%rsp) movss %xmm4, 16(%rsp) movss %xmm5, 12(%rsp) movss %xmm6, 8(%rsp) movss %xmm7, 4(%rsp) movq %fs:40, %rax movq %rax, 200(%rsp) xorl %eax, %eax leaq 44(%rsp), %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rax movq %rax, 120(%rsp) leaq 36(%rsp), %rax movq %rax, 128(%rsp) leaq 32(%rsp), %rax movq %rax, 136(%rsp) leaq 28(%rsp), %rax movq %rax, 144(%rsp) leaq 24(%rsp), %rax movq %rax, 152(%rsp) leaq 20(%rsp), %rax movq %rax, 160(%rsp) leaq 16(%rsp), %rax movq %rax, 168(%rsp) leaq 12(%rsp), %rax movq %rax, 176(%rsp) leaq 8(%rsp), %rax movq %rax, 184(%rsp) leaq 4(%rsp), %rax movq %rax, 192(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 200(%rsp), %rax subq %fs:40, %rax jne .L12 addq $216, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 232 pushq 56(%rsp) .cfi_def_cfa_offset 240 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z7computefiiffifffff(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 224 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z35__device_stub__Z7computefiiffiffffffiiffifffff, .-_Z35__device_stub__Z7computefiiffiffffffiiffifffff .globl _Z7computefiiffifffff .type _Z7computefiiffifffff, @function _Z7computefiiffifffff: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z7computefiiffiffffffiiffifffff addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z7computefiiffifffff, .-_Z7computefiiffifffff .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $104, %rsp .cfi_def_cfa_offset 144 movq %rsi, %rbx movq 8(%rsi), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 56(%rsp) movq 16(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %rbp movq 24(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %r12 movq 32(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 48(%rsp) movq 40(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 40(%rsp) movq 48(%rbx), %rdi movl $10, %edx movl $0, %esi call __isoc23_strtol@PLT movq %rax, %r13 movq 56(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 32(%rsp) movq 64(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 24(%rsp) movq 72(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 16(%rsp) movq 80(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 8(%rsp) movq 88(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, (%rsp) movl $1, 84(%rsp) movl $1, 88(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $0, %r9d movl $0, %r8d movq 84(%rsp), %rdx movl $1, %ecx movq 72(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L18 .L16: call cudaDeviceSynchronize@PLT movl $0, %eax addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L18: .cfi_restore_state pxor %xmm0, %xmm0 cvtsd2ss 56(%rsp), %xmm0 pxor %xmm7, %xmm7 cvtsd2ss (%rsp), %xmm7 pxor %xmm6, %xmm6 cvtsd2ss 8(%rsp), %xmm6 pxor %xmm5, %xmm5 cvtsd2ss 16(%rsp), %xmm5 pxor %xmm4, %xmm4 cvtsd2ss 24(%rsp), %xmm4 pxor %xmm3, %xmm3 cvtsd2ss 32(%rsp), %xmm3 movl %r13d, %edx pxor %xmm2, %xmm2 cvtsd2ss 40(%rsp), %xmm2 pxor %xmm1, %xmm1 cvtsd2ss 48(%rsp), %xmm1 movl %r12d, %esi movl %ebp, %edi call _Z35__device_stub__Z7computefiiffiffffffiiffifffff jmp .L16 .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z7computefiiffifffff" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z7computefiiffifffff(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "test.hip" .globl _Z22__device_stub__computefiiffifffff # -- Begin function _Z22__device_stub__computefiiffifffff .p2align 4, 0x90 .type _Z22__device_stub__computefiiffifffff,@function _Z22__device_stub__computefiiffifffff: # @_Z22__device_stub__computefiiffifffff .cfi_startproc # %bb.0: subq $184, %rsp .cfi_def_cfa_offset 192 movss %xmm0, 44(%rsp) movl %edi, 40(%rsp) movl %esi, 36(%rsp) movss %xmm1, 32(%rsp) movss %xmm2, 28(%rsp) movl %edx, 24(%rsp) movss %xmm3, 20(%rsp) movss %xmm4, 16(%rsp) movss %xmm5, 12(%rsp) movss %xmm6, 8(%rsp) movss %xmm7, 4(%rsp) leaq 44(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rax movq %rax, 104(%rsp) leaq 36(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 28(%rsp), %rax movq %rax, 128(%rsp) leaq 24(%rsp), %rax movq %rax, 136(%rsp) leaq 20(%rsp), %rax movq %rax, 144(%rsp) leaq 16(%rsp), %rax movq %rax, 152(%rsp) leaq 12(%rsp), %rax movq %rax, 160(%rsp) leaq 8(%rsp), %rax movq %rax, 168(%rsp) leaq 4(%rsp), %rax movq %rax, 176(%rsp) leaq 80(%rsp), %rdi leaq 64(%rsp), %rsi leaq 56(%rsp), %rdx leaq 48(%rsp), %rcx callq __hipPopCallConfiguration movq 80(%rsp), %rsi movl 88(%rsp), %edx movq 64(%rsp), %rcx movl 72(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z7computefiiffifffff, %edi pushq 48(%rsp) .cfi_adjust_cfa_offset 8 pushq 64(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $200, %rsp .cfi_adjust_cfa_offset -200 retq .Lfunc_end0: .size _Z22__device_stub__computefiiffifffff, .Lfunc_end0-_Z22__device_stub__computefiiffifffff .cfi_endproc # -- End function .globl _Z11initPointerf # -- Begin function _Z11initPointerf .p2align 4, 0x90 .type _Z11initPointerf,@function _Z11initPointerf: # @_Z11initPointerf .cfi_startproc # %bb.0: pushq %rax .cfi_def_cfa_offset 16 movss %xmm0, 4(%rsp) # 4-byte Spill movl $40, %edi callq malloc movss 4(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movss %xmm0, (%rax,%rcx,4) incq %rcx cmpq $10, %rcx jne .LBB1_1 # %bb.2: popq %rcx .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r12 .cfi_def_cfa_offset 32 pushq %rbx .cfi_def_cfa_offset 40 subq $248, %rsp .cfi_def_cfa_offset 288 .cfi_offset %rbx, -40 .cfi_offset %r12, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movq %rsi, %r15 movq 8(%rsi), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 104(%rsp) # 8-byte Spill movq 16(%r15), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %rbx movq 24(%r15), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r14 movq 32(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 96(%rsp) # 8-byte Spill movq 40(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 88(%rsp) # 8-byte Spill movq 48(%r15), %rdi xorl %esi, %esi movl $10, %edx callq __isoc23_strtol movq %rax, %r12 movq 56(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 80(%rsp) # 8-byte Spill movq 64(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 72(%rsp) # 8-byte Spill movq 72(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 64(%rsp) # 8-byte Spill movq 80(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 56(%rsp) # 8-byte Spill movq 88(%r15), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 48(%rsp) # 8-byte Spill movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: movsd 48(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movsd 56(%rsp), %xmm1 # 8-byte Reload # xmm1 = mem[0],zero cvtsd2ss %xmm1, %xmm1 movsd 64(%rsp), %xmm2 # 8-byte Reload # xmm2 = mem[0],zero cvtsd2ss %xmm2, %xmm2 movsd 72(%rsp), %xmm3 # 8-byte Reload # xmm3 = mem[0],zero cvtsd2ss %xmm3, %xmm3 movsd 80(%rsp), %xmm4 # 8-byte Reload # xmm4 = mem[0],zero cvtsd2ss %xmm4, %xmm4 movsd 88(%rsp), %xmm5 # 8-byte Reload # xmm5 = mem[0],zero cvtsd2ss %xmm5, %xmm5 movsd 96(%rsp), %xmm6 # 8-byte Reload # xmm6 = mem[0],zero cvtsd2ss %xmm6, %xmm6 movsd 104(%rsp), %xmm7 # 8-byte Reload # xmm7 = mem[0],zero cvtsd2ss %xmm7, %xmm7 movss %xmm7, 44(%rsp) movl %ebx, 40(%rsp) movl %r14d, 36(%rsp) movss %xmm6, 32(%rsp) movss %xmm5, 28(%rsp) movl %r12d, 24(%rsp) movss %xmm4, 20(%rsp) movss %xmm3, 16(%rsp) movss %xmm2, 12(%rsp) movss %xmm1, 8(%rsp) movss %xmm0, 4(%rsp) leaq 44(%rsp), %rax movq %rax, 160(%rsp) leaq 40(%rsp), %rax movq %rax, 168(%rsp) leaq 36(%rsp), %rax movq %rax, 176(%rsp) leaq 32(%rsp), %rax movq %rax, 184(%rsp) leaq 28(%rsp), %rax movq %rax, 192(%rsp) leaq 24(%rsp), %rax movq %rax, 200(%rsp) leaq 20(%rsp), %rax movq %rax, 208(%rsp) leaq 16(%rsp), %rax movq %rax, 216(%rsp) leaq 12(%rsp), %rax movq %rax, 224(%rsp) leaq 8(%rsp), %rax movq %rax, 232(%rsp) leaq 4(%rsp), %rax movq %rax, 240(%rsp) leaq 144(%rsp), %rdi leaq 128(%rsp), %rsi leaq 120(%rsp), %rdx leaq 112(%rsp), %rcx callq __hipPopCallConfiguration movq 144(%rsp), %rsi movl 152(%rsp), %edx movq 128(%rsp), %rcx movl 136(%rsp), %r8d leaq 160(%rsp), %r9 movl $_Z7computefiiffifffff, %edi pushq 112(%rsp) .cfi_adjust_cfa_offset 8 pushq 128(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB2_2: callq hipDeviceSynchronize xorl %eax, %eax addq $248, %rsp .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7computefiiffifffff, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z7computefiiffifffff,@object # @_Z7computefiiffifffff .section .rodata,"a",@progbits .globl _Z7computefiiffifffff .p2align 3, 0x0 _Z7computefiiffifffff: .quad _Z22__device_stub__computefiiffifffff .size _Z7computefiiffifffff, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z7computefiiffifffff" .size .L__unnamed_1, 22 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__computefiiffifffff .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7computefiiffifffff .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void var(int *a,int *b,int n,float mean) { int block=256*blockIdx.x; float sum=0; for(int i=block;i<min(block+256,n);i++) { sum=sum+(a[i]-mean)*(a[i]-mean); } b[blockIdx.x]=sum; }
code for sm_80 Function : _Z3varPiS_if .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0030*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */ /* 0x000fe200000001ff */ /*0040*/ SHF.L.U32 R5, R0, 0x8, RZ ; /* 0x0000000800057819 */ /* 0x001fc800000006ff */ /*0050*/ IADD3 R4, R5, 0x100, RZ ; /* 0x0000010005047810 */ /* 0x000fc80007ffe0ff */ /*0060*/ IMNMX R4, R4, c[0x0][0x170], PT ; /* 0x00005c0004047a17 */ /* 0x000fc80003800200 */ /*0070*/ ISETP.GE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */ /* 0x000fda0003f06270 */ /*0080*/ @P0 BRA 0xab0 ; /* 0x00000a2000000947 */ /* 0x000fea0003800000 */ /*0090*/ LOP3.LUT R2, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff027a12 */ /* 0x000fe400078e33ff */ /*00a0*/ IADD3 R3, -R5, -0x101, RZ ; /* 0xfffffeff05037810 */ /* 0x000fe40007ffe1ff */ /*00b0*/ MOV R6, RZ ; /* 0x000000ff00067202 */ /* 0x000fe40000000f00 */ /*00c0*/ IMNMX R8, R2, R3, !PT ; /* 0x0000000302087217 */ /* 0x000fc80007800200 */ /*00d0*/ LOP3.LUT R2, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308027812 */ /* 0x000fe400078ec0ff */ /*00e0*/ IADD3 R3, -R5, -0x2, -R8 ; /* 0xfffffffe05037810 */ /* 0x000fe40007ffe908 */ /*00f0*/ ISETP.NE.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */ /* 0x000fe40003f25270 */ /*0100*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */ /* 0x000fd60003f06070 */ /*0110*/ @!P1 BRA 0x220 ; /* 0x0000010000009947 */ /* 0x000fea0003800000 */ /*0120*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */ /* 0x000fe200000001ff */ /*0130*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc, !PT ; /* 0x0000000308087812 */ /* 0x000fe200078e0cff */ /*0140*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */ /* 0x000fd000000001ff */ /*0150*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */ /* 0x000fca00078e0202 */ /*0160*/ MOV R9, R2 ; /* 0x0000000200097202 */ /* 0x000fc80000000f00 */ /*0170*/ MOV R2, R9 ; /* 0x0000000900027202 */ /* 0x000fcc0000000f00 */ /*0180*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x0000a2000c1e1900 */ /*0190*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */ /* 0x000fe40007ffe0ff */ /*01a0*/ IADD3 R9, P2, R9, 0x4, RZ ; /* 0x0000000409097810 */ /* 0x000fe40007f5e0ff */ /*01b0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */ /* 0x000fe40003f25270 */ /*01c0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */ /* 0x000fe40007ffe0ff */ /*01d0*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */ /* 0x001fe200017fe4ff */ /*01e0*/ I2F R7, R2 ; /* 0x0000000200077306 */ /* 0x004e240000201400 */ /*01f0*/ FADD R7, R7, -c[0x0][0x174] ; /* 0x80005d0007077621 */ /* 0x001fc80000000000 */ /*0200*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */ /* 0x000fe40000000006 */ /*0210*/ @P1 BRA 0x170 ; /* 0xffffff5000001947 */ /* 0x000fea000383ffff */ /*0220*/ @!P0 BRA 0xab0 ; /* 0x0000088000008947 */ /* 0x000fea0003800000 */ /*0230*/ IADD3 R7, R4, -R5, RZ ; /* 0x8000000504077210 */ /* 0x000fe40007ffe0ff */ /*0240*/ MOV R2, 0x4 ; /* 0x0000000400027802 */ /* 0x000fe40000000f00 */ /*0250*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */ /* 0x000fc60003f24270 */ /*0260*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */ /* 0x000fca00078e0202 */ /*0270*/ IADD3 R2, P0, R2, 0x8, RZ ; /* 0x0000000802027810 */ /* 0x000fc80007f1e0ff */ /*0280*/ IADD3.X R3, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff037210 */ /* 0x000fe400007fe4ff */ /*0290*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fe20003f0f070 */ /*02a0*/ @!P1 BRA 0x720 ; /* 0x0000047000009947 */ /* 0x000fea0003800000 */ /*02b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*02c0*/ IADD3 R8, R4, -0xc, RZ ; /* 0xfffffff404087810 */ /* 0x000fca0007ffe0ff */ /*02d0*/ LDG.E R23, [R2.64+-0x8] ; /* 0xfffff80402177981 */ /* 0x0000a8000c1e1900 */ /*02e0*/ LDG.E R22, [R2.64+-0x4] ; /* 0xfffffc0402167981 */ /* 0x0000e8000c1e1900 */ /*02f0*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */ /* 0x000128000c1e1900 */ /*0300*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040402137981 */ /* 0x000168000c1e1900 */ /*0310*/ LDG.E R18, [R2.64+0x8] ; /* 0x0000080402127981 */ /* 0x000128000c1e1900 */ /*0320*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0402107981 */ /* 0x000168000c1e1900 */ /*0330*/ LDG.E R12, [R2.64+0x10] ; /* 0x00001004020c7981 */ /* 0x000168000c1e1900 */ /*0340*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */ /* 0x000168000c1e1900 */ /*0350*/ LDG.E R20, [R2.64+0x18] ; /* 0x0000180402147981 */ /* 0x000168000c1e1900 */ /*0360*/ LDG.E R17, [R2.64+0x1c] ; /* 0x00001c0402117981 */ /* 0x000168000c1e1900 */ /*0370*/ LDG.E R14, [R2.64+0x20] ; /* 0x00002004020e7981 */ /* 0x000168000c1e1900 */ /*0380*/ LDG.E R13, [R2.64+0x24] ; /* 0x00002404020d7981 */ /* 0x000168000c1e1900 */ /*0390*/ LDG.E R11, [R2.64+0x28] ; /* 0x00002804020b7981 */ /* 0x000168000c1e1900 */ /*03a0*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c04020a7981 */ /* 0x000168000c1e1900 */ /*03b0*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300402097981 */ /* 0x000168000c1e1900 */ /*03c0*/ LDG.E R7, [R2.64+0x34] ; /* 0x0000340402077981 */ /* 0x000162000c1e1900 */ /*03d0*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */ /* 0x000fc80007ffe0ff */ /*03e0*/ ISETP.GE.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */ /* 0x000fe40003f26270 */ /*03f0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */ /* 0x001fc80007f5e0ff */ /*0400*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */ /* 0x000fe200017fe4ff */ /*0410*/ I2F R23, R23 ; /* 0x0000001700177306 */ /* 0x004e300000201400 */ /*0420*/ I2F R22, R22 ; /* 0x0000001600167306 */ /* 0x008e700000201400 */ /*0430*/ I2F R21, R21 ; /* 0x0000001500157306 */ /* 0x010ea20000201400 */ /*0440*/ FADD R25, R23, -c[0x0][0x174] ; /* 0x80005d0017197621 */ /* 0x001fc80000000000 */ /*0450*/ FFMA R6, R25, R25, R6 ; /* 0x0000001919067223 */ /* 0x000fc60000000006 */ /*0460*/ I2F R19, R19 ; /* 0x0000001300137306 */ /* 0x020e220000201400 */ /*0470*/ FADD R25, R22, -c[0x0][0x174] ; /* 0x80005d0016197621 */ /* 0x002fc80000000000 */ /*0480*/ FFMA R6, R25, R25, R6 ; /* 0x0000001919067223 */ /* 0x000fc60000000006 */ /*0490*/ I2F R18, R18 ; /* 0x0000001200127306 */ /* 0x000e620000201400 */ /*04a0*/ FADD R21, R21, -c[0x0][0x174] ; /* 0x80005d0015157621 */ /* 0x004fc80000000000 */ /*04b0*/ FFMA R6, R21, R21, R6 ; /* 0x0000001515067223 */ /* 0x000fc60000000006 */ /*04c0*/ I2F R16, R16 ; /* 0x0000001000107306 */ /* 0x000ea20000201400 */ /*04d0*/ FADD R19, R19, -c[0x0][0x174] ; /* 0x80005d0013137621 */ /* 0x001fc80000000000 */ /*04e0*/ FFMA R6, R19, R19, R6 ; /* 0x0000001313067223 */ /* 0x000fc60000000006 */ /*04f0*/ I2F R12, R12 ; /* 0x0000000c000c7306 */ /* 0x000e220000201400 */ /*0500*/ FADD R19, R18, -c[0x0][0x174] ; /* 0x80005d0012137621 */ /* 0x002fc80000000000 */ /*0510*/ FFMA R6, R19, R19, R6 ; /* 0x0000001313067223 */ /* 0x000fc60000000006 */ /*0520*/ I2F R15, R15 ; /* 0x0000000f000f7306 */ /* 0x000e620000201400 */ /*0530*/ FADD R19, R16, -c[0x0][0x174] ; /* 0x80005d0010137621 */ /* 0x004fc80000000000 */ /*0540*/ FFMA R6, R19, R19, R6 ; /* 0x0000001313067223 */ /* 0x000fc60000000006 */ /*0550*/ I2F R20, R20 ; /* 0x0000001400147306 */ /* 0x000ea20000201400 */ /*0560*/ FADD R19, R12, -c[0x0][0x174] ; /* 0x80005d000c137621 */ /* 0x001fc80000000000 */ /*0570*/ FFMA R6, R19, R19, R6 ; /* 0x0000001313067223 */ /* 0x000fc60000000006 */ /*0580*/ I2F R17, R17 ; /* 0x0000001100117306 */ /* 0x000e220000201400 */ /*0590*/ FADD R15, R15, -c[0x0][0x174] ; /* 0x80005d000f0f7621 */ /* 0x002fc80000000000 */ /*05a0*/ FFMA R6, R15, R15, R6 ; /* 0x0000000f0f067223 */ /* 0x000fc60000000006 */ /*05b0*/ I2F R14, R14 ; /* 0x0000000e000e7306 */ /* 0x000e620000201400 */ /*05c0*/ FADD R15, R20, -c[0x0][0x174] ; /* 0x80005d00140f7621 */ /* 0x004fc80000000000 */ /*05d0*/ FFMA R6, R15, R15, R6 ; /* 0x0000000f0f067223 */ /* 0x000fc60000000006 */ /*05e0*/ I2F R13, R13 ; /* 0x0000000d000d7306 */ /* 0x000ea20000201400 */ /*05f0*/ FADD R17, R17, -c[0x0][0x174] ; /* 0x80005d0011117621 */ /* 0x001fc80000000000 */ /*0600*/ FFMA R6, R17, R17, R6 ; /* 0x0000001111067223 */ /* 0x000fc60000000006 */ /*0610*/ I2F R11, R11 ; /* 0x0000000b000b7306 */ /* 0x000e220000201400 */ /*0620*/ FADD R15, R14, -c[0x0][0x174] ; /* 0x80005d000e0f7621 */ /* 0x002fc80000000000 */ /*0630*/ FFMA R6, R15, R15, R6 ; /* 0x0000000f0f067223 */ /* 0x000fc60000000006 */ /*0640*/ I2F R10, R10 ; /* 0x0000000a000a7306 */ /* 0x000e620000201400 */ /*0650*/ FADD R13, R13, -c[0x0][0x174] ; /* 0x80005d000d0d7621 */ /* 0x004fc80000000000 */ /*0660*/ FFMA R6, R13, R13, R6 ; /* 0x0000000d0d067223 */ /* 0x000fc60000000006 */ /*0670*/ I2F R9, R9 ; /* 0x0000000900097306 */ /* 0x000ea20000201400 */ /*0680*/ FADD R11, R11, -c[0x0][0x174] ; /* 0x80005d000b0b7621 */ /* 0x001fc80000000000 */ /*0690*/ FFMA R6, R11, R11, R6 ; /* 0x0000000b0b067223 */ /* 0x000fc60000000006 */ /*06a0*/ I2F R7, R7 ; /* 0x0000000700077306 */ /* 0x000e220000201400 */ /*06b0*/ FADD R11, R10, -c[0x0][0x174] ; /* 0x80005d000a0b7621 */ /* 0x002fc80000000000 */ /*06c0*/ FFMA R6, R11, R11, R6 ; /* 0x0000000b0b067223 */ /* 0x000fe40000000006 */ /*06d0*/ FADD R11, R9, -c[0x0][0x174] ; /* 0x80005d00090b7621 */ /* 0x004fc80000000000 */ /*06e0*/ FFMA R6, R11, R11, R6 ; /* 0x0000000b0b067223 */ /* 0x000fe40000000006 */ /*06f0*/ FADD R9, R7, -c[0x0][0x174] ; /* 0x80005d0007097621 */ /* 0x001fc80000000000 */ /*0700*/ FFMA R6, R9, R9, R6 ; /* 0x0000000909067223 */ /* 0x000fe20000000006 */ /*0710*/ @!P1 BRA 0x2d0 ; /* 0xfffffbb000009947 */ /* 0x000fea000383ffff */ /*0720*/ IADD3 R7, R4, -R5, RZ ; /* 0x8000000504077210 */ /* 0x000fc80007ffe0ff */ /*0730*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */ /* 0x000fda0003f24270 */ /*0740*/ @!P1 BRA 0x990 ; /* 0x0000024000009947 */ /* 0x000fea0003800000 */ /*0750*/ LDG.E R7, [R2.64+-0x8] ; /* 0xfffff80402077981 */ /* 0x0000a8000c1e1900 */ /*0760*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402087981 */ /* 0x0000e8000c1e1900 */ /*0770*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */ /* 0x000128000c1e1900 */ /*0780*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */ /* 0x000168000c1e1900 */ /*0790*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */ /* 0x000128000c1e1900 */ /*07a0*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */ /* 0x000168000c1e1900 */ /*07b0*/ LDG.E R14, [R2.64+0x10] ; /* 0x00001004020e7981 */ /* 0x000168000c1e1900 */ /*07c0*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */ /* 0x000162000c1e1900 */ /*07d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40003f0e170 */ /*07e0*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */ /* 0x000fe40007ffe0ff */ /*07f0*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */ /* 0x001fc80007f3e0ff */ /*0800*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */ /* 0x000fe20000ffe4ff */ /*0810*/ I2F R7, R7 ; /* 0x0000000700077306 */ /* 0x004e300000201400 */ /*0820*/ I2F R8, R8 ; /* 0x0000000800087306 */ /* 0x008e700000201400 */ /*0830*/ I2F R10, R10 ; /* 0x0000000a000a7306 */ /* 0x010ea20000201400 */ /*0840*/ FADD R9, R7, -c[0x0][0x174] ; /* 0x80005d0007097621 */ /* 0x001fc80000000000 */ /*0850*/ FFMA R6, R9, R9, R6 ; /* 0x0000000909067223 */ /* 0x000fc60000000006 */ /*0860*/ I2F R11, R11 ; /* 0x0000000b000b7306 */ /* 0x020e220000201400 */ /*0870*/ FADD R9, R8, -c[0x0][0x174] ; /* 0x80005d0008097621 */ /* 0x002fc80000000000 */ /*0880*/ FFMA R6, R9, R9, R6 ; /* 0x0000000909067223 */ /* 0x000fc60000000006 */ /*0890*/ I2F R12, R12 ; /* 0x0000000c000c7306 */ /* 0x000e620000201400 */ /*08a0*/ FADD R9, R10, -c[0x0][0x174] ; /* 0x80005d000a097621 */ /* 0x004fc80000000000 */ /*08b0*/ FFMA R6, R9, R9, R6 ; /* 0x0000000909067223 */ /* 0x000fc60000000006 */ /*08c0*/ I2F R13, R13 ; /* 0x0000000d000d7306 */ /* 0x000ea20000201400 */ /*08d0*/ FADD R7, R11, -c[0x0][0x174] ; /* 0x80005d000b077621 */ /* 0x001fc80000000000 */ /*08e0*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */ /* 0x000fc60000000006 */ /*08f0*/ I2F R14, R14 ; /* 0x0000000e000e7306 */ /* 0x000e220000201400 */ /*0900*/ FADD R7, R12, -c[0x0][0x174] ; /* 0x80005d000c077621 */ /* 0x002fc80000000000 */ /*0910*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */ /* 0x000fc60000000006 */ /*0920*/ I2F R15, R15 ; /* 0x0000000f000f7306 */ /* 0x000e620000201400 */ /*0930*/ FADD R13, R13, -c[0x0][0x174] ; /* 0x80005d000d0d7621 */ /* 0x004fc80000000000 */ /*0940*/ FFMA R6, R13, R13, R6 ; /* 0x0000000d0d067223 */ /* 0x000fe40000000006 */ /*0950*/ FADD R7, R14, -c[0x0][0x174] ; /* 0x80005d000e077621 */ /* 0x001fc80000000000 */ /*0960*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */ /* 0x000fe40000000006 */ /*0970*/ FADD R7, R15, -c[0x0][0x174] ; /* 0x80005d000f077621 */ /* 0x002fc80000000000 */ /*0980*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */ /* 0x000fe40000000006 */ /*0990*/ ISETP.LT.OR P0, PT, R5, R4, P0 ; /* 0x000000040500720c */ /* 0x000fda0000701670 */ /*09a0*/ @!P0 BRA 0xab0 ; /* 0x0000010000008947 */ /* 0x000fea0003800000 */ /*09b0*/ LDG.E R4, [R2.64+-0x8] ; /* 0xfffff80402047981 */ /* 0x000ea8000c1e1900 */ /*09c0*/ LDG.E R7, [R2.64+-0x4] ; /* 0xfffffc0402077981 */ /* 0x000ee8000c1e1900 */ /*09d0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */ /* 0x000f28000c1e1900 */ /*09e0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */ /* 0x000f62000c1e1900 */ /*09f0*/ I2F R4, R4 ; /* 0x0000000400047306 */ /* 0x004e300000201400 */ /*0a00*/ I2F R7, R7 ; /* 0x0000000700077306 */ /* 0x008e700000201400 */ /*0a10*/ I2F R8, R8 ; /* 0x0000000800087306 */ /* 0x010ea20000201400 */ /*0a20*/ FADD R5, R4, -c[0x0][0x174] ; /* 0x80005d0004057621 */ /* 0x001fc80000000000 */ /*0a30*/ FFMA R5, R5, R5, R6 ; /* 0x0000000505057223 */ /* 0x000fc60000000006 */ /*0a40*/ I2F R9, R9 ; /* 0x0000000900097306 */ /* 0x020e220000201400 */ /*0a50*/ FADD R6, R7, -c[0x0][0x174] ; /* 0x80005d0007067621 */ /* 0x002fc80000000000 */ /*0a60*/ FFMA R5, R6, R6, R5 ; /* 0x0000000606057223 */ /* 0x000fe40000000005 */ /*0a70*/ FADD R10, R8, -c[0x0][0x174] ; /* 0x80005d00080a7621 */ /* 0x004fc80000000000 */ /*0a80*/ FFMA R5, R10, R10, R5 ; /* 0x0000000a0a057223 */ /* 0x000fe40000000005 */ /*0a90*/ FADD R6, R9, -c[0x0][0x174] ; /* 0x80005d0009067621 */ /* 0x001fc80000000000 */ /*0aa0*/ FFMA R6, R6, R6, R5 ; /* 0x0000000606067223 */ /* 0x000fc80000000005 */ /*0ab0*/ F2I.TRUNC.NTZ R5, R6 ; /* 0x0000000600057305 */ /* 0x000e22000020f100 */ /*0ac0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */ /* 0x000fca0000000f00 */ /*0ad0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */ /* 0x000fca00078e0003 */ /*0ae0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x001fe2000c101904 */ /*0af0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0b10*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b20*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b30*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b40*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b50*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b80*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b90*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ba0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0bb0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0bc0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0bd0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0be0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0bf0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void var(int *a,int *b,int n,float mean) { int block=256*blockIdx.x; float sum=0; for(int i=block;i<min(block+256,n);i++) { sum=sum+(a[i]-mean)*(a[i]-mean); } b[blockIdx.x]=sum; }
.file "tmpxft_00156164_00000000-6_var.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z26__device_stub__Z3varPiS_ifPiS_if .type _Z26__device_stub__Z3varPiS_ifPiS_if, @function _Z26__device_stub__Z3varPiS_ifPiS_if: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movss %xmm0, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z3varPiS_if(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z26__device_stub__Z3varPiS_ifPiS_if, .-_Z26__device_stub__Z3varPiS_ifPiS_if .globl _Z3varPiS_if .type _Z3varPiS_if, @function _Z3varPiS_if: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z3varPiS_ifPiS_if addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z3varPiS_if, .-_Z3varPiS_if .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z3varPiS_if" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z3varPiS_if(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void var(int *a,int *b,int n,float mean) { int block=256*blockIdx.x; float sum=0; for(int i=block;i<min(block+256,n);i++) { sum=sum+(a[i]-mean)*(a[i]-mean); } b[blockIdx.x]=sum; }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void var(int *a,int *b,int n,float mean) { int block=256*blockIdx.x; float sum=0; for(int i=block;i<min(block+256,n);i++) { sum=sum+(a[i]-mean)*(a[i]-mean); } b[blockIdx.x]=sum; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void var(int *a,int *b,int n,float mean) { int block=256*blockIdx.x; float sum=0; for(int i=block;i<min(block+256,n);i++) { sum=sum+(a[i]-mean)*(a[i]-mean); } b[blockIdx.x]=sum; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3varPiS_if .globl _Z3varPiS_if .p2align 8 .type _Z3varPiS_if,@function _Z3varPiS_if: s_load_b32 s6, s[0:1], 0x10 v_mov_b32_e32 v0, 0 s_lshl_b32 s4, s15, 8 s_mov_b32 s2, s15 s_waitcnt lgkmcnt(0) s_cmp_ge_i32 s4, s6 s_cbranch_scc1 .LBB0_4 s_clause 0x1 s_load_b64 s[8:9], s[0:1], 0x0 s_load_b32 s3, s[0:1], 0x14 s_ashr_i32 s5, s4, 31 s_add_i32 s7, s4, 0x100 s_lshl_b64 s[10:11], s[4:5], 2 v_mov_b32_e32 v0, 0 s_min_i32 s5, s7, s6 s_waitcnt lgkmcnt(0) s_add_u32 s6, s8, s10 s_addc_u32 s7, s9, s11 .LBB0_2: s_load_b32 s8, s[6:7], 0x0 s_add_i32 s4, s4, 1 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_cmp_ge_i32 s4, s5 s_waitcnt lgkmcnt(0) v_cvt_f32_i32_e32 v1, s8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_subrev_f32_e32 v1, s3, v1 v_fmac_f32_e32 v0, v1, v1 s_cbranch_scc0 .LBB0_2 s_delay_alu instid0(VALU_DEP_1) v_cvt_i32_f32_e32 v0, v0 .LBB0_4: s_load_b64 s[0:1], s[0:1], 0x8 s_mov_b32 s3, 0 v_mov_b32_e32 v1, 0 s_lshl_b64 s[2:3], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s0, s0, s2 s_addc_u32 s1, s1, s3 global_store_b32 v1, v0, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3varPiS_if .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 16 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3varPiS_if, .Lfunc_end0-_Z3varPiS_if .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3varPiS_if .private_segment_fixed_size: 0 .sgpr_count: 16 .sgpr_spill_count: 0 .symbol: _Z3varPiS_if.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void var(int *a,int *b,int n,float mean) { int block=256*blockIdx.x; float sum=0; for(int i=block;i<min(block+256,n);i++) { sum=sum+(a[i]-mean)*(a[i]-mean); } b[blockIdx.x]=sum; }
.text .file "var.hip" .globl _Z18__device_stub__varPiS_if # -- Begin function _Z18__device_stub__varPiS_if .p2align 4, 0x90 .type _Z18__device_stub__varPiS_if,@function _Z18__device_stub__varPiS_if: # @_Z18__device_stub__varPiS_if .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movss %xmm0, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3varPiS_if, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z18__device_stub__varPiS_if, .Lfunc_end0-_Z18__device_stub__varPiS_if .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3varPiS_if, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z3varPiS_if,@object # @_Z3varPiS_if .section .rodata,"a",@progbits .globl _Z3varPiS_if .p2align 3, 0x0 _Z3varPiS_if: .quad _Z18__device_stub__varPiS_if .size _Z3varPiS_if, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z3varPiS_if" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__varPiS_if .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3varPiS_if .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z3varPiS_if .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0030*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */ /* 0x000fe200000001ff */ /*0040*/ SHF.L.U32 R5, R0, 0x8, RZ ; /* 0x0000000800057819 */ /* 0x001fc800000006ff */ /*0050*/ IADD3 R4, R5, 0x100, RZ ; /* 0x0000010005047810 */ /* 0x000fc80007ffe0ff */ /*0060*/ IMNMX R4, R4, c[0x0][0x170], PT ; /* 0x00005c0004047a17 */ /* 0x000fc80003800200 */ /*0070*/ ISETP.GE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */ /* 0x000fda0003f06270 */ /*0080*/ @P0 BRA 0xab0 ; /* 0x00000a2000000947 */ /* 0x000fea0003800000 */ /*0090*/ LOP3.LUT R2, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff027a12 */ /* 0x000fe400078e33ff */ /*00a0*/ IADD3 R3, -R5, -0x101, RZ ; /* 0xfffffeff05037810 */ /* 0x000fe40007ffe1ff */ /*00b0*/ MOV R6, RZ ; /* 0x000000ff00067202 */ /* 0x000fe40000000f00 */ /*00c0*/ IMNMX R8, R2, R3, !PT ; /* 0x0000000302087217 */ /* 0x000fc80007800200 */ /*00d0*/ LOP3.LUT R2, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308027812 */ /* 0x000fe400078ec0ff */ /*00e0*/ IADD3 R3, -R5, -0x2, -R8 ; /* 0xfffffffe05037810 */ /* 0x000fe40007ffe908 */ /*00f0*/ ISETP.NE.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */ /* 0x000fe40003f25270 */ /*0100*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */ /* 0x000fd60003f06070 */ /*0110*/ @!P1 BRA 0x220 ; /* 0x0000010000009947 */ /* 0x000fea0003800000 */ /*0120*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */ /* 0x000fe200000001ff */ /*0130*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc, !PT ; /* 0x0000000308087812 */ /* 0x000fe200078e0cff */ /*0140*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */ /* 0x000fd000000001ff */ /*0150*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */ /* 0x000fca00078e0202 */ /*0160*/ MOV R9, R2 ; /* 0x0000000200097202 */ /* 0x000fc80000000f00 */ /*0170*/ MOV R2, R9 ; /* 0x0000000900027202 */ /* 0x000fcc0000000f00 */ /*0180*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x0000a2000c1e1900 */ /*0190*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */ /* 0x000fe40007ffe0ff */ /*01a0*/ IADD3 R9, P2, R9, 0x4, RZ ; /* 0x0000000409097810 */ /* 0x000fe40007f5e0ff */ /*01b0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */ /* 0x000fe40003f25270 */ /*01c0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */ /* 0x000fe40007ffe0ff */ /*01d0*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */ /* 0x001fe200017fe4ff */ /*01e0*/ I2F R7, R2 ; /* 0x0000000200077306 */ /* 0x004e240000201400 */ /*01f0*/ FADD R7, R7, -c[0x0][0x174] ; /* 0x80005d0007077621 */ /* 0x001fc80000000000 */ /*0200*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */ /* 0x000fe40000000006 */ /*0210*/ @P1 BRA 0x170 ; /* 0xffffff5000001947 */ /* 0x000fea000383ffff */ /*0220*/ @!P0 BRA 0xab0 ; /* 0x0000088000008947 */ /* 0x000fea0003800000 */ /*0230*/ IADD3 R7, R4, -R5, RZ ; /* 0x8000000504077210 */ /* 0x000fe40007ffe0ff */ /*0240*/ MOV R2, 0x4 ; /* 0x0000000400027802 */ /* 0x000fe40000000f00 */ /*0250*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */ /* 0x000fc60003f24270 */ /*0260*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */ /* 0x000fca00078e0202 */ /*0270*/ IADD3 R2, P0, R2, 0x8, RZ ; /* 0x0000000802027810 */ /* 0x000fc80007f1e0ff */ /*0280*/ IADD3.X R3, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff037210 */ /* 0x000fe400007fe4ff */ /*0290*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fe20003f0f070 */ /*02a0*/ @!P1 BRA 0x720 ; /* 0x0000047000009947 */ /* 0x000fea0003800000 */ /*02b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*02c0*/ IADD3 R8, R4, -0xc, RZ ; /* 0xfffffff404087810 */ /* 0x000fca0007ffe0ff */ /*02d0*/ LDG.E R23, [R2.64+-0x8] ; /* 0xfffff80402177981 */ /* 0x0000a8000c1e1900 */ /*02e0*/ LDG.E R22, [R2.64+-0x4] ; /* 0xfffffc0402167981 */ /* 0x0000e8000c1e1900 */ /*02f0*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */ /* 0x000128000c1e1900 */ /*0300*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040402137981 */ /* 0x000168000c1e1900 */ /*0310*/ LDG.E R18, [R2.64+0x8] ; /* 0x0000080402127981 */ /* 0x000128000c1e1900 */ /*0320*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0402107981 */ /* 0x000168000c1e1900 */ /*0330*/ LDG.E R12, [R2.64+0x10] ; /* 0x00001004020c7981 */ /* 0x000168000c1e1900 */ /*0340*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */ /* 0x000168000c1e1900 */ /*0350*/ LDG.E R20, [R2.64+0x18] ; /* 0x0000180402147981 */ /* 0x000168000c1e1900 */ /*0360*/ LDG.E R17, [R2.64+0x1c] ; /* 0x00001c0402117981 */ /* 0x000168000c1e1900 */ /*0370*/ LDG.E R14, [R2.64+0x20] ; /* 0x00002004020e7981 */ /* 0x000168000c1e1900 */ /*0380*/ LDG.E R13, [R2.64+0x24] ; /* 0x00002404020d7981 */ /* 0x000168000c1e1900 */ /*0390*/ LDG.E R11, [R2.64+0x28] ; /* 0x00002804020b7981 */ /* 0x000168000c1e1900 */ /*03a0*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c04020a7981 */ /* 0x000168000c1e1900 */ /*03b0*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300402097981 */ /* 0x000168000c1e1900 */ /*03c0*/ LDG.E R7, [R2.64+0x34] ; /* 0x0000340402077981 */ /* 0x000162000c1e1900 */ /*03d0*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */ /* 0x000fc80007ffe0ff */ /*03e0*/ ISETP.GE.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */ /* 0x000fe40003f26270 */ /*03f0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */ /* 0x001fc80007f5e0ff */ /*0400*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */ /* 0x000fe200017fe4ff */ /*0410*/ I2F R23, R23 ; /* 0x0000001700177306 */ /* 0x004e300000201400 */ /*0420*/ I2F R22, R22 ; /* 0x0000001600167306 */ /* 0x008e700000201400 */ /*0430*/ I2F R21, R21 ; /* 0x0000001500157306 */ /* 0x010ea20000201400 */ /*0440*/ FADD R25, R23, -c[0x0][0x174] ; /* 0x80005d0017197621 */ /* 0x001fc80000000000 */ /*0450*/ FFMA R6, R25, R25, R6 ; /* 0x0000001919067223 */ /* 0x000fc60000000006 */ /*0460*/ I2F R19, R19 ; /* 0x0000001300137306 */ /* 0x020e220000201400 */ /*0470*/ FADD R25, R22, -c[0x0][0x174] ; /* 0x80005d0016197621 */ /* 0x002fc80000000000 */ /*0480*/ FFMA R6, R25, R25, R6 ; /* 0x0000001919067223 */ /* 0x000fc60000000006 */ /*0490*/ I2F R18, R18 ; /* 0x0000001200127306 */ /* 0x000e620000201400 */ /*04a0*/ FADD R21, R21, -c[0x0][0x174] ; /* 0x80005d0015157621 */ /* 0x004fc80000000000 */ /*04b0*/ FFMA R6, R21, R21, R6 ; /* 0x0000001515067223 */ /* 0x000fc60000000006 */ /*04c0*/ I2F R16, R16 ; /* 0x0000001000107306 */ /* 0x000ea20000201400 */ /*04d0*/ FADD R19, R19, -c[0x0][0x174] ; /* 0x80005d0013137621 */ /* 0x001fc80000000000 */ /*04e0*/ FFMA R6, R19, R19, R6 ; /* 0x0000001313067223 */ /* 0x000fc60000000006 */ /*04f0*/ I2F R12, R12 ; /* 0x0000000c000c7306 */ /* 0x000e220000201400 */ /*0500*/ FADD R19, R18, -c[0x0][0x174] ; /* 0x80005d0012137621 */ /* 0x002fc80000000000 */ /*0510*/ FFMA R6, R19, R19, R6 ; /* 0x0000001313067223 */ /* 0x000fc60000000006 */ /*0520*/ I2F R15, R15 ; /* 0x0000000f000f7306 */ /* 0x000e620000201400 */ /*0530*/ FADD R19, R16, -c[0x0][0x174] ; /* 0x80005d0010137621 */ /* 0x004fc80000000000 */ /*0540*/ FFMA R6, R19, R19, R6 ; /* 0x0000001313067223 */ /* 0x000fc60000000006 */ /*0550*/ I2F R20, R20 ; /* 0x0000001400147306 */ /* 0x000ea20000201400 */ /*0560*/ FADD R19, R12, -c[0x0][0x174] ; /* 0x80005d000c137621 */ /* 0x001fc80000000000 */ /*0570*/ FFMA R6, R19, R19, R6 ; /* 0x0000001313067223 */ /* 0x000fc60000000006 */ /*0580*/ I2F R17, R17 ; /* 0x0000001100117306 */ /* 0x000e220000201400 */ /*0590*/ FADD R15, R15, -c[0x0][0x174] ; /* 0x80005d000f0f7621 */ /* 0x002fc80000000000 */ /*05a0*/ FFMA R6, R15, R15, R6 ; /* 0x0000000f0f067223 */ /* 0x000fc60000000006 */ /*05b0*/ I2F R14, R14 ; /* 0x0000000e000e7306 */ /* 0x000e620000201400 */ /*05c0*/ FADD R15, R20, -c[0x0][0x174] ; /* 0x80005d00140f7621 */ /* 0x004fc80000000000 */ /*05d0*/ FFMA R6, R15, R15, R6 ; /* 0x0000000f0f067223 */ /* 0x000fc60000000006 */ /*05e0*/ I2F R13, R13 ; /* 0x0000000d000d7306 */ /* 0x000ea20000201400 */ /*05f0*/ FADD R17, R17, -c[0x0][0x174] ; /* 0x80005d0011117621 */ /* 0x001fc80000000000 */ /*0600*/ FFMA R6, R17, R17, R6 ; /* 0x0000001111067223 */ /* 0x000fc60000000006 */ /*0610*/ I2F R11, R11 ; /* 0x0000000b000b7306 */ /* 0x000e220000201400 */ /*0620*/ FADD R15, R14, -c[0x0][0x174] ; /* 0x80005d000e0f7621 */ /* 0x002fc80000000000 */ /*0630*/ FFMA R6, R15, R15, R6 ; /* 0x0000000f0f067223 */ /* 0x000fc60000000006 */ /*0640*/ I2F R10, R10 ; /* 0x0000000a000a7306 */ /* 0x000e620000201400 */ /*0650*/ FADD R13, R13, -c[0x0][0x174] ; /* 0x80005d000d0d7621 */ /* 0x004fc80000000000 */ /*0660*/ FFMA R6, R13, R13, R6 ; /* 0x0000000d0d067223 */ /* 0x000fc60000000006 */ /*0670*/ I2F R9, R9 ; /* 0x0000000900097306 */ /* 0x000ea20000201400 */ /*0680*/ FADD R11, R11, -c[0x0][0x174] ; /* 0x80005d000b0b7621 */ /* 0x001fc80000000000 */ /*0690*/ FFMA R6, R11, R11, R6 ; /* 0x0000000b0b067223 */ /* 0x000fc60000000006 */ /*06a0*/ I2F R7, R7 ; /* 0x0000000700077306 */ /* 0x000e220000201400 */ /*06b0*/ FADD R11, R10, -c[0x0][0x174] ; /* 0x80005d000a0b7621 */ /* 0x002fc80000000000 */ /*06c0*/ FFMA R6, R11, R11, R6 ; /* 0x0000000b0b067223 */ /* 0x000fe40000000006 */ /*06d0*/ FADD R11, R9, -c[0x0][0x174] ; /* 0x80005d00090b7621 */ /* 0x004fc80000000000 */ /*06e0*/ FFMA R6, R11, R11, R6 ; /* 0x0000000b0b067223 */ /* 0x000fe40000000006 */ /*06f0*/ FADD R9, R7, -c[0x0][0x174] ; /* 0x80005d0007097621 */ /* 0x001fc80000000000 */ /*0700*/ FFMA R6, R9, R9, R6 ; /* 0x0000000909067223 */ /* 0x000fe20000000006 */ /*0710*/ @!P1 BRA 0x2d0 ; /* 0xfffffbb000009947 */ /* 0x000fea000383ffff */ /*0720*/ IADD3 R7, R4, -R5, RZ ; /* 0x8000000504077210 */ /* 0x000fc80007ffe0ff */ /*0730*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */ /* 0x000fda0003f24270 */ /*0740*/ @!P1 BRA 0x990 ; /* 0x0000024000009947 */ /* 0x000fea0003800000 */ /*0750*/ LDG.E R7, [R2.64+-0x8] ; /* 0xfffff80402077981 */ /* 0x0000a8000c1e1900 */ /*0760*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402087981 */ /* 0x0000e8000c1e1900 */ /*0770*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */ /* 0x000128000c1e1900 */ /*0780*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */ /* 0x000168000c1e1900 */ /*0790*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */ /* 0x000128000c1e1900 */ /*07a0*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */ /* 0x000168000c1e1900 */ /*07b0*/ LDG.E R14, [R2.64+0x10] ; /* 0x00001004020e7981 */ /* 0x000168000c1e1900 */ /*07c0*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */ /* 0x000162000c1e1900 */ /*07d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40003f0e170 */ /*07e0*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */ /* 0x000fe40007ffe0ff */ /*07f0*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */ /* 0x001fc80007f3e0ff */ /*0800*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */ /* 0x000fe20000ffe4ff */ /*0810*/ I2F R7, R7 ; /* 0x0000000700077306 */ /* 0x004e300000201400 */ /*0820*/ I2F R8, R8 ; /* 0x0000000800087306 */ /* 0x008e700000201400 */ /*0830*/ I2F R10, R10 ; /* 0x0000000a000a7306 */ /* 0x010ea20000201400 */ /*0840*/ FADD R9, R7, -c[0x0][0x174] ; /* 0x80005d0007097621 */ /* 0x001fc80000000000 */ /*0850*/ FFMA R6, R9, R9, R6 ; /* 0x0000000909067223 */ /* 0x000fc60000000006 */ /*0860*/ I2F R11, R11 ; /* 0x0000000b000b7306 */ /* 0x020e220000201400 */ /*0870*/ FADD R9, R8, -c[0x0][0x174] ; /* 0x80005d0008097621 */ /* 0x002fc80000000000 */ /*0880*/ FFMA R6, R9, R9, R6 ; /* 0x0000000909067223 */ /* 0x000fc60000000006 */ /*0890*/ I2F R12, R12 ; /* 0x0000000c000c7306 */ /* 0x000e620000201400 */ /*08a0*/ FADD R9, R10, -c[0x0][0x174] ; /* 0x80005d000a097621 */ /* 0x004fc80000000000 */ /*08b0*/ FFMA R6, R9, R9, R6 ; /* 0x0000000909067223 */ /* 0x000fc60000000006 */ /*08c0*/ I2F R13, R13 ; /* 0x0000000d000d7306 */ /* 0x000ea20000201400 */ /*08d0*/ FADD R7, R11, -c[0x0][0x174] ; /* 0x80005d000b077621 */ /* 0x001fc80000000000 */ /*08e0*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */ /* 0x000fc60000000006 */ /*08f0*/ I2F R14, R14 ; /* 0x0000000e000e7306 */ /* 0x000e220000201400 */ /*0900*/ FADD R7, R12, -c[0x0][0x174] ; /* 0x80005d000c077621 */ /* 0x002fc80000000000 */ /*0910*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */ /* 0x000fc60000000006 */ /*0920*/ I2F R15, R15 ; /* 0x0000000f000f7306 */ /* 0x000e620000201400 */ /*0930*/ FADD R13, R13, -c[0x0][0x174] ; /* 0x80005d000d0d7621 */ /* 0x004fc80000000000 */ /*0940*/ FFMA R6, R13, R13, R6 ; /* 0x0000000d0d067223 */ /* 0x000fe40000000006 */ /*0950*/ FADD R7, R14, -c[0x0][0x174] ; /* 0x80005d000e077621 */ /* 0x001fc80000000000 */ /*0960*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */ /* 0x000fe40000000006 */ /*0970*/ FADD R7, R15, -c[0x0][0x174] ; /* 0x80005d000f077621 */ /* 0x002fc80000000000 */ /*0980*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */ /* 0x000fe40000000006 */ /*0990*/ ISETP.LT.OR P0, PT, R5, R4, P0 ; /* 0x000000040500720c */ /* 0x000fda0000701670 */ /*09a0*/ @!P0 BRA 0xab0 ; /* 0x0000010000008947 */ /* 0x000fea0003800000 */ /*09b0*/ LDG.E R4, [R2.64+-0x8] ; /* 0xfffff80402047981 */ /* 0x000ea8000c1e1900 */ /*09c0*/ LDG.E R7, [R2.64+-0x4] ; /* 0xfffffc0402077981 */ /* 0x000ee8000c1e1900 */ /*09d0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */ /* 0x000f28000c1e1900 */ /*09e0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */ /* 0x000f62000c1e1900 */ /*09f0*/ I2F R4, R4 ; /* 0x0000000400047306 */ /* 0x004e300000201400 */ /*0a00*/ I2F R7, R7 ; /* 0x0000000700077306 */ /* 0x008e700000201400 */ /*0a10*/ I2F R8, R8 ; /* 0x0000000800087306 */ /* 0x010ea20000201400 */ /*0a20*/ FADD R5, R4, -c[0x0][0x174] ; /* 0x80005d0004057621 */ /* 0x001fc80000000000 */ /*0a30*/ FFMA R5, R5, R5, R6 ; /* 0x0000000505057223 */ /* 0x000fc60000000006 */ /*0a40*/ I2F R9, R9 ; /* 0x0000000900097306 */ /* 0x020e220000201400 */ /*0a50*/ FADD R6, R7, -c[0x0][0x174] ; /* 0x80005d0007067621 */ /* 0x002fc80000000000 */ /*0a60*/ FFMA R5, R6, R6, R5 ; /* 0x0000000606057223 */ /* 0x000fe40000000005 */ /*0a70*/ FADD R10, R8, -c[0x0][0x174] ; /* 0x80005d00080a7621 */ /* 0x004fc80000000000 */ /*0a80*/ FFMA R5, R10, R10, R5 ; /* 0x0000000a0a057223 */ /* 0x000fe40000000005 */ /*0a90*/ FADD R6, R9, -c[0x0][0x174] ; /* 0x80005d0009067621 */ /* 0x001fc80000000000 */ /*0aa0*/ FFMA R6, R6, R6, R5 ; /* 0x0000000606067223 */ /* 0x000fc80000000005 */ /*0ab0*/ F2I.TRUNC.NTZ R5, R6 ; /* 0x0000000600057305 */ /* 0x000e22000020f100 */ /*0ac0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */ /* 0x000fca0000000f00 */ /*0ad0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */ /* 0x000fca00078e0003 */ /*0ae0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x001fe2000c101904 */ /*0af0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0b10*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b20*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b30*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b40*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b50*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b80*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0b90*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ba0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0bb0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0bc0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0bd0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0be0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0bf0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z3varPiS_if .globl _Z3varPiS_if .p2align 8 .type _Z3varPiS_if,@function _Z3varPiS_if: s_load_b32 s6, s[0:1], 0x10 v_mov_b32_e32 v0, 0 s_lshl_b32 s4, s15, 8 s_mov_b32 s2, s15 s_waitcnt lgkmcnt(0) s_cmp_ge_i32 s4, s6 s_cbranch_scc1 .LBB0_4 s_clause 0x1 s_load_b64 s[8:9], s[0:1], 0x0 s_load_b32 s3, s[0:1], 0x14 s_ashr_i32 s5, s4, 31 s_add_i32 s7, s4, 0x100 s_lshl_b64 s[10:11], s[4:5], 2 v_mov_b32_e32 v0, 0 s_min_i32 s5, s7, s6 s_waitcnt lgkmcnt(0) s_add_u32 s6, s8, s10 s_addc_u32 s7, s9, s11 .LBB0_2: s_load_b32 s8, s[6:7], 0x0 s_add_i32 s4, s4, 1 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_cmp_ge_i32 s4, s5 s_waitcnt lgkmcnt(0) v_cvt_f32_i32_e32 v1, s8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_subrev_f32_e32 v1, s3, v1 v_fmac_f32_e32 v0, v1, v1 s_cbranch_scc0 .LBB0_2 s_delay_alu instid0(VALU_DEP_1) v_cvt_i32_f32_e32 v0, v0 .LBB0_4: s_load_b64 s[0:1], s[0:1], 0x8 s_mov_b32 s3, 0 v_mov_b32_e32 v1, 0 s_lshl_b64 s[2:3], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s0, s0, s2 s_addc_u32 s1, s1, s3 global_store_b32 v1, v0, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z3varPiS_if .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 2 .amdhsa_next_free_sgpr 16 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z3varPiS_if, .Lfunc_end0-_Z3varPiS_if .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z3varPiS_if .private_segment_fixed_size: 0 .sgpr_count: 16 .sgpr_spill_count: 0 .symbol: _Z3varPiS_if.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 2 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00156164_00000000-6_var.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z26__device_stub__Z3varPiS_ifPiS_if .type _Z26__device_stub__Z3varPiS_ifPiS_if, @function _Z26__device_stub__Z3varPiS_ifPiS_if: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movss %xmm0, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z3varPiS_if(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z26__device_stub__Z3varPiS_ifPiS_if, .-_Z26__device_stub__Z3varPiS_ifPiS_if .globl _Z3varPiS_if .type _Z3varPiS_if, @function _Z3varPiS_if: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z26__device_stub__Z3varPiS_ifPiS_if addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z3varPiS_if, .-_Z3varPiS_if .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z3varPiS_if" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z3varPiS_if(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "var.hip" .globl _Z18__device_stub__varPiS_if # -- Begin function _Z18__device_stub__varPiS_if .p2align 4, 0x90 .type _Z18__device_stub__varPiS_if,@function _Z18__device_stub__varPiS_if: # @_Z18__device_stub__varPiS_if .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movss %xmm0, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z3varPiS_if, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z18__device_stub__varPiS_if, .Lfunc_end0-_Z18__device_stub__varPiS_if .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z3varPiS_if, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z3varPiS_if,@object # @_Z3varPiS_if .section .rodata,"a",@progbits .globl _Z3varPiS_if .p2align 3, 0x0 _Z3varPiS_if: .quad _Z18__device_stub__varPiS_if .size _Z3varPiS_if, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z3varPiS_if" .size .L__unnamed_1, 13 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z18__device_stub__varPiS_if .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z3varPiS_if .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include<stdio.h> __global__ void print_indexs() { printf("threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, gridDim.x: %d, gridDim.y: %d, gridDim.z: %d\n", threadIdx.x, threadIdx.y, threadIdx.z, blockIdx.x, blockIdx.y, blockIdx.z, blockDim.x, blockDim.y, blockDim.z, gridDim.x, gridDim.y, gridDim.z); } int main() { int nx = 16; int ny = 16; int nz = 16; dim3 block(8,8,8); dim3 grid(nx/block.x, ny/block.y, nz/block.z); print_indexs<<<grid, block>>>(); cudaDeviceSynchronize(); cudaDeviceReset(); return 0; }
code for sm_80 Function : _Z12print_indexsv .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fc800078e00ff */ /*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */ /* 0x000e220000002500 */ /*0020*/ IADD3 R1, R1, -0x30, RZ ; /* 0xffffffd001017810 */ /* 0x000fe20007ffe0ff */ /*0030*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0e7624 */ /* 0x000fe200078e00ff */ /*0040*/ MOV R18, c[0x0][0x10] ; /* 0x0000040000127a02 */ /* 0x000fe20000000f00 */ /*0050*/ S2R R10, SR_TID.Z ; /* 0x00000000000a7919 */ /* 0x000e220000002300 */ /*0060*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0f7624 */ /* 0x000fe200078e00ff */ /*0070*/ MOV R0, 0x0 ; /* 0x0000000000007802 */ /* 0x000fe20000000f00 */ /*0080*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff107624 */ /* 0x000fe200078e00ff */ /*0090*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */ /* 0x000e220000002200 */ /*00a0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff117624 */ /* 0x000fe200078e00ff */ /*00b0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */ /* 0x0002a20000000a00 */ /*00c0*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x14] ; /* 0x00000500ff137624 */ /* 0x000fe200078e00ff */ /*00d0*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */ /* 0x000e220000002100 */ /*00e0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */ /* 0x000fe20007f1e0ff */ /*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */ /* 0x000fe200078e00ff */ /*0100*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */ /* 0x000fe20000000f00 */ /*0110*/ S2R R13, SR_CTAID.Z ; /* 0x00000000000d7919 */ /* 0x000ee40000002700 */ /*0120*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */ /* 0x000fc400000e06ff */ /*0130*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */ /* 0x000ee80000002600 */ /*0140*/ STL.128 [R1+0x20], R16 ; /* 0x0000201001007387 */ /* 0x0003e80000100c00 */ /*0150*/ STL.128 [R1], R8 ; /* 0x0000000801007387 */ /* 0x0013e80000100c00 */ /*0160*/ STL.128 [R1+0x10], R12 ; /* 0x0000100c01007387 */ /* 0x0083e40000100c00 */ /*0170*/ LEPC R8 ; /* 0x000000000008734e */ /* 0x006fe40000000000 */ /*0180*/ MOV R11, 0x1f0 ; /* 0x000001f0000b7802 */ /* 0x000fe40000000f00 */ /*0190*/ MOV R20, 0x170 ; /* 0x0000017000147802 */ /* 0x000fc40000000f00 */ /*01a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */ /* 0x000fe40000000f00 */ /*01b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */ /* 0x000fe40000000f00 */ /*01c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */ /* 0x000fc8000791e108 */ /*01d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */ /* 0x000fc800007e2509 */ /*01e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */ /* 0x000fea0003c00000 */ /*01f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0200*/ BRA 0x200; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0280*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0290*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include<stdio.h> __global__ void print_indexs() { printf("threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, gridDim.x: %d, gridDim.y: %d, gridDim.z: %d\n", threadIdx.x, threadIdx.y, threadIdx.z, blockIdx.x, blockIdx.y, blockIdx.z, blockDim.x, blockDim.y, blockDim.z, gridDim.x, gridDim.y, gridDim.z); } int main() { int nx = 16; int ny = 16; int nz = 16; dim3 block(8,8,8); dim3 grid(nx/block.x, ny/block.y, nz/block.z); print_indexs<<<grid, block>>>(); cudaDeviceSynchronize(); cudaDeviceReset(); return 0; }
.file "tmpxft_00194645_00000000-6_program_ex1.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z31__device_stub__Z12print_indexsvv .type _Z31__device_stub__Z12print_indexsvv, @function _Z31__device_stub__Z12print_indexsvv: .LFB2082: .cfi_startproc endbr64 subq $88, %rsp .cfi_def_cfa_offset 96 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 16(%rsp) movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 28(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) leaq 8(%rsp), %rcx movq %rsp, %rdx leaq 28(%rsp), %rsi leaq 16(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 72(%rsp), %rax subq %fs:40, %rax jne .L8 addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 8(%rsp) .cfi_def_cfa_offset 104 pushq 8(%rsp) .cfi_def_cfa_offset 112 leaq 80(%rsp), %r9 movq 44(%rsp), %rcx movl 52(%rsp), %r8d movq 32(%rsp), %rsi movl 40(%rsp), %edx leaq _Z12print_indexsv(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 96 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z31__device_stub__Z12print_indexsvv, .-_Z31__device_stub__Z12print_indexsvv .globl _Z12print_indexsv .type _Z12print_indexsv, @function _Z12print_indexsv: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z12print_indexsvv addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z12print_indexsv, .-_Z12print_indexsv .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 subq $40, %rsp .cfi_def_cfa_offset 48 movl $2, 20(%rsp) movl $2, 24(%rsp) movl $8, 8(%rsp) movl $8, 12(%rsp) movl $0, %r9d movl $0, %r8d movq 8(%rsp), %rdx movl $8, %ecx movq 20(%rsp), %rdi movl $2, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L14 .L12: call cudaDeviceSynchronize@PLT call cudaDeviceReset@PLT movl $0, %eax addq $40, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L14: .cfi_restore_state call _Z31__device_stub__Z12print_indexsvv jmp .L12 .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z12print_indexsv" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z12print_indexsv(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4: