system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
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|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <cstring>
using namespace std;
#define N 1024
#define INF 0x03F3F3F
int map[N * N];
int path[N];
__global__ void kernel1(int *nv,int *map,int *cost,int *tmp_cost,bool *visited,int * tmp_path)
{
const int nn = 1024;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//fetch all its neighbour
if(visited[tid])
{
visited[tid] = false;
for(int i = 0; i < *nv; ++i)
{
if(cost[tid] + map[tid * nn + i] < tmp_cost[i])
{
tmp_path[i] = tid;
tmp_cost[i] = cost[tid] + map[tid * N + i];
}
}
}
return;
}
__global__ void kernel2(int *cost,int *tmp_cost,bool *visited,bool *flag,int *tmp_path,int *path)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//some vertex can be updated,means that it is the new one to the queue
if(cost[tid] > tmp_cost[tid])
{
path[tid] = tmp_path[tid];
visited[tid] = true;
cost[tid] = tmp_cost[tid];
*flag = true;
}
tmp_cost[tid] = cost[tid];//if cost[tid] <= tmp_cost[tid]
tmp_path[tid] = path[tid];
return;
}
void print_path(int node,int path[])
{
if(path[node] == -1)
{
printf("%d ",node + 1);
return;
}
else
{
print_path(path[node],path);
printf("%d ",node + 1);
}
return;
}
int main()
{
freopen("input_dijkstra","r",stdin);
int cost[N],tmp_cost[N],path[N],tmp_path[N];
bool visited[N],flag;
int *dev_cost,*dev_tmp_cost,*dev_map,*dev_nv,*dev_path,*dev_tmp_path;
bool *dev_visited,*dev_flag;
int nv,ne;
scanf("%d%d",&nv,&ne);
//initialize
for(int i = 0; i < nv; ++i)
{
cost[i] = INF;
tmp_cost[i] = INF;
visited[i] = false;
for(int j = 0; j < nv; ++j)
map[i * N + j] = map[j * N + i] = INF;
}
//read all the edges
for(int i = 0; i < ne; ++i)
{
int p,q,w;
scanf("%d%d%d",&p,&q,&w);
map[p * N + q] = map[q * N + p] = w;
}
int source;
scanf("%d",&source);
cost[source] = tmp_cost[source] = 0;
visited[source] = true;
flag = true;
path[source] = -1;
tmp_path[source] = -1;
cout<<0<<endl;
cudaMalloc((void**)&dev_cost,N * sizeof(int));
cout<<1<<endl;
cudaMalloc((void**)&dev_tmp_cost,N * sizeof(int));
cudaMalloc((void**)&dev_visited,N * sizeof(bool));
cudaMalloc((void**)&dev_map,N * N * sizeof(int));
cudaMalloc((void**)&dev_flag,sizeof(bool));
cudaMalloc((void**)&dev_nv,sizeof(int));
cudaMalloc((void**)&dev_path,N * sizeof(int));
cudaMalloc((void**)&dev_tmp_path,N * sizeof(int));
cudaMemcpy(dev_cost,cost,N * sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_tmp_cost,tmp_cost,N * sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_visited,visited,N * sizeof(bool),cudaMemcpyHostToDevice);
cudaMemcpy(dev_map,map,N * N * sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_flag,&flag,sizeof(bool),cudaMemcpyHostToDevice);
cudaMemcpy(dev_nv,&nv,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_path,path,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_tmp_path,tmp_path,N*sizeof(int),cudaMemcpyHostToDevice);
while(flag)
{
flag = false;
kernel1<<<1,nv>>>(dev_nv,dev_map,dev_cost,dev_tmp_cost,dev_visited,dev_tmp_path);
cudaMemcpy(dev_flag,&flag,sizeof(bool),cudaMemcpyHostToDevice);
kernel2<<<1,nv>>>(dev_cost,dev_tmp_cost,dev_visited,dev_flag,dev_tmp_path,dev_path);
cudaMemcpy(&flag,dev_flag,sizeof(bool),cudaMemcpyDeviceToHost);
}
cudaMemcpy(cost,dev_cost,N*sizeof(int),cudaMemcpyDeviceToHost);
cudaMemcpy(path,dev_path,N*sizeof(int),cudaMemcpyDeviceToHost);
for(int i = 0; i < nv; ++i)
{
printf("Node %d cost = %2d path: ",i+1,cost[i]);
print_path(i,path);
printf("\n");
}
cout << endl;
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <cstring>
using namespace std;
#define N 1024
#define INF 0x03F3F3F
int map[N * N];
int path[N];
__global__ void kernel1(int *nv,int *map,int *cost,int *tmp_cost,bool *visited,int * tmp_path)
{
const int nn = 1024;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//fetch all its neighbour
if(visited[tid])
{
visited[tid] = false;
for(int i = 0; i < *nv; ++i)
{
if(cost[tid] + map[tid * nn + i] < tmp_cost[i])
{
tmp_path[i] = tid;
tmp_cost[i] = cost[tid] + map[tid * N + i];
}
}
}
return;
}
__global__ void kernel2(int *cost,int *tmp_cost,bool *visited,bool *flag,int *tmp_path,int *path)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//some vertex can be updated,means that it is the new one to the queue
if(cost[tid] > tmp_cost[tid])
{
path[tid] = tmp_path[tid];
visited[tid] = true;
cost[tid] = tmp_cost[tid];
*flag = true;
}
tmp_cost[tid] = cost[tid];//if cost[tid] <= tmp_cost[tid]
tmp_path[tid] = path[tid];
return;
}
void print_path(int node,int path[])
{
if(path[node] == -1)
{
printf("%d ",node + 1);
return;
}
else
{
print_path(path[node],path);
printf("%d ",node + 1);
}
return;
}
int main()
{
freopen("input_dijkstra","r",stdin);
int cost[N],tmp_cost[N],path[N],tmp_path[N];
bool visited[N],flag;
int *dev_cost,*dev_tmp_cost,*dev_map,*dev_nv,*dev_path,*dev_tmp_path;
bool *dev_visited,*dev_flag;
int nv,ne;
scanf("%d%d",&nv,&ne);
//initialize
for(int i = 0; i < nv; ++i)
{
cost[i] = INF;
tmp_cost[i] = INF;
visited[i] = false;
for(int j = 0; j < nv; ++j)
map[i * N + j] = map[j * N + i] = INF;
}
//read all the edges
for(int i = 0; i < ne; ++i)
{
int p,q,w;
scanf("%d%d%d",&p,&q,&w);
map[p * N + q] = map[q * N + p] = w;
}
int source;
scanf("%d",&source);
cost[source] = tmp_cost[source] = 0;
visited[source] = true;
flag = true;
path[source] = -1;
tmp_path[source] = -1;
cout<<0<<endl;
hipMalloc((void**)&dev_cost,N * sizeof(int));
cout<<1<<endl;
hipMalloc((void**)&dev_tmp_cost,N * sizeof(int));
hipMalloc((void**)&dev_visited,N * sizeof(bool));
hipMalloc((void**)&dev_map,N * N * sizeof(int));
hipMalloc((void**)&dev_flag,sizeof(bool));
hipMalloc((void**)&dev_nv,sizeof(int));
hipMalloc((void**)&dev_path,N * sizeof(int));
hipMalloc((void**)&dev_tmp_path,N * sizeof(int));
hipMemcpy(dev_cost,cost,N * sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_tmp_cost,tmp_cost,N * sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_visited,visited,N * sizeof(bool),hipMemcpyHostToDevice);
hipMemcpy(dev_map,map,N * N * sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_flag,&flag,sizeof(bool),hipMemcpyHostToDevice);
hipMemcpy(dev_nv,&nv,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_path,path,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_tmp_path,tmp_path,N*sizeof(int),hipMemcpyHostToDevice);
while(flag)
{
flag = false;
kernel1<<<1,nv>>>(dev_nv,dev_map,dev_cost,dev_tmp_cost,dev_visited,dev_tmp_path);
hipMemcpy(dev_flag,&flag,sizeof(bool),hipMemcpyHostToDevice);
kernel2<<<1,nv>>>(dev_cost,dev_tmp_cost,dev_visited,dev_flag,dev_tmp_path,dev_path);
hipMemcpy(&flag,dev_flag,sizeof(bool),hipMemcpyDeviceToHost);
}
hipMemcpy(cost,dev_cost,N*sizeof(int),hipMemcpyDeviceToHost);
hipMemcpy(path,dev_path,N*sizeof(int),hipMemcpyDeviceToHost);
for(int i = 0; i < nv; ++i)
{
printf("Node %d cost = %2d path: ",i+1,cost[i]);
print_path(i,path);
printf("\n");
}
cout << endl;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <cstring>
using namespace std;
#define N 1024
#define INF 0x03F3F3F
int map[N * N];
int path[N];
__global__ void kernel1(int *nv,int *map,int *cost,int *tmp_cost,bool *visited,int * tmp_path)
{
const int nn = 1024;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//fetch all its neighbour
if(visited[tid])
{
visited[tid] = false;
for(int i = 0; i < *nv; ++i)
{
if(cost[tid] + map[tid * nn + i] < tmp_cost[i])
{
tmp_path[i] = tid;
tmp_cost[i] = cost[tid] + map[tid * N + i];
}
}
}
return;
}
__global__ void kernel2(int *cost,int *tmp_cost,bool *visited,bool *flag,int *tmp_path,int *path)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//some vertex can be updated,means that it is the new one to the queue
if(cost[tid] > tmp_cost[tid])
{
path[tid] = tmp_path[tid];
visited[tid] = true;
cost[tid] = tmp_cost[tid];
*flag = true;
}
tmp_cost[tid] = cost[tid];//if cost[tid] <= tmp_cost[tid]
tmp_path[tid] = path[tid];
return;
}
void print_path(int node,int path[])
{
if(path[node] == -1)
{
printf("%d ",node + 1);
return;
}
else
{
print_path(path[node],path);
printf("%d ",node + 1);
}
return;
}
int main()
{
freopen("input_dijkstra","r",stdin);
int cost[N],tmp_cost[N],path[N],tmp_path[N];
bool visited[N],flag;
int *dev_cost,*dev_tmp_cost,*dev_map,*dev_nv,*dev_path,*dev_tmp_path;
bool *dev_visited,*dev_flag;
int nv,ne;
scanf("%d%d",&nv,&ne);
//initialize
for(int i = 0; i < nv; ++i)
{
cost[i] = INF;
tmp_cost[i] = INF;
visited[i] = false;
for(int j = 0; j < nv; ++j)
map[i * N + j] = map[j * N + i] = INF;
}
//read all the edges
for(int i = 0; i < ne; ++i)
{
int p,q,w;
scanf("%d%d%d",&p,&q,&w);
map[p * N + q] = map[q * N + p] = w;
}
int source;
scanf("%d",&source);
cost[source] = tmp_cost[source] = 0;
visited[source] = true;
flag = true;
path[source] = -1;
tmp_path[source] = -1;
cout<<0<<endl;
hipMalloc((void**)&dev_cost,N * sizeof(int));
cout<<1<<endl;
hipMalloc((void**)&dev_tmp_cost,N * sizeof(int));
hipMalloc((void**)&dev_visited,N * sizeof(bool));
hipMalloc((void**)&dev_map,N * N * sizeof(int));
hipMalloc((void**)&dev_flag,sizeof(bool));
hipMalloc((void**)&dev_nv,sizeof(int));
hipMalloc((void**)&dev_path,N * sizeof(int));
hipMalloc((void**)&dev_tmp_path,N * sizeof(int));
hipMemcpy(dev_cost,cost,N * sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_tmp_cost,tmp_cost,N * sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_visited,visited,N * sizeof(bool),hipMemcpyHostToDevice);
hipMemcpy(dev_map,map,N * N * sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_flag,&flag,sizeof(bool),hipMemcpyHostToDevice);
hipMemcpy(dev_nv,&nv,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_path,path,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_tmp_path,tmp_path,N*sizeof(int),hipMemcpyHostToDevice);
while(flag)
{
flag = false;
kernel1<<<1,nv>>>(dev_nv,dev_map,dev_cost,dev_tmp_cost,dev_visited,dev_tmp_path);
hipMemcpy(dev_flag,&flag,sizeof(bool),hipMemcpyHostToDevice);
kernel2<<<1,nv>>>(dev_cost,dev_tmp_cost,dev_visited,dev_flag,dev_tmp_path,dev_path);
hipMemcpy(&flag,dev_flag,sizeof(bool),hipMemcpyDeviceToHost);
}
hipMemcpy(cost,dev_cost,N*sizeof(int),hipMemcpyDeviceToHost);
hipMemcpy(path,dev_path,N*sizeof(int),hipMemcpyDeviceToHost);
for(int i = 0; i < nv; ++i)
{
printf("Node %d cost = %2d path: ",i+1,cost[i]);
print_path(i,path);
printf("\n");
}
cout << endl;
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1PiS_S_S_PbS_
.globl _Z7kernel1PiS_S_S_PbS_
.p2align 8
.type _Z7kernel1PiS_S_S_PbS_,@function
_Z7kernel1PiS_S_S_PbS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v3, vcc_lo, s2, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
global_load_u8 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v0
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s6, 0
global_store_b8 v[3:4], v0, off
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[8:11], s[0:1], 0x8
v_dual_mov_b32 v0, 0 :: v_dual_lshlrev_b32 v3, 10, v1
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s10, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v6, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v8, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
global_load_b32 v6, v0, s[2:3]
v_add_co_u32 v4, vcc_lo, v4, 4
s_add_i32 s6, s6, 1
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, s6, v6
s_cbranch_vccz .LBB0_6
.LBB0_4:
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
global_load_b32 v8, v0, s[4:5]
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v6, v7, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v6, v8
s_cbranch_execz .LBB0_3
global_store_b32 v0, v1, s[0:1]
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v7, v6
global_store_b32 v0, v6, s[4:5]
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1PiS_S_S_PbS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1PiS_S_S_PbS_, .Lfunc_end0-_Z7kernel1PiS_S_S_PbS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel2PiS_PbS0_S_S_
.globl _Z7kernel2PiS_PbS0_S_S_
.p2align 8
.type _Z7kernel2PiS_PbS0_S_S_,@function
_Z7kernel2PiS_PbS0_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v1, vcc_lo
global_load_b32 v8, v[2:3], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v8, v9
s_cbranch_execz .LBB1_2
v_add_co_u32 v8, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v1, vcc_lo
s_load_b128 s[8:11], s[0:1], 0x10
global_load_b32 v10, v[8:9], off
v_add_co_u32 v8, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v10, off
global_load_b32 v8, v[6:7], off
v_dual_mov_b32 v9, 1 :: v_dual_mov_b32 v10, 0
global_store_b8 v[4:5], v9, off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v8, off
global_store_b8 v10, v9, s[10:11]
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v4, off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2PiS_PbS0_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel2PiS_PbS0_S_S_, .Lfunc_end1-_Z7kernel2PiS_PbS0_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1PiS_S_S_PbS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1PiS_S_S_PbS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2PiS_PbS0_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel2PiS_PbS0_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <cstring>
using namespace std;
#define N 1024
#define INF 0x03F3F3F
int map[N * N];
int path[N];
__global__ void kernel1(int *nv,int *map,int *cost,int *tmp_cost,bool *visited,int * tmp_path)
{
const int nn = 1024;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//fetch all its neighbour
if(visited[tid])
{
visited[tid] = false;
for(int i = 0; i < *nv; ++i)
{
if(cost[tid] + map[tid * nn + i] < tmp_cost[i])
{
tmp_path[i] = tid;
tmp_cost[i] = cost[tid] + map[tid * N + i];
}
}
}
return;
}
__global__ void kernel2(int *cost,int *tmp_cost,bool *visited,bool *flag,int *tmp_path,int *path)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//some vertex can be updated,means that it is the new one to the queue
if(cost[tid] > tmp_cost[tid])
{
path[tid] = tmp_path[tid];
visited[tid] = true;
cost[tid] = tmp_cost[tid];
*flag = true;
}
tmp_cost[tid] = cost[tid];//if cost[tid] <= tmp_cost[tid]
tmp_path[tid] = path[tid];
return;
}
void print_path(int node,int path[])
{
if(path[node] == -1)
{
printf("%d ",node + 1);
return;
}
else
{
print_path(path[node],path);
printf("%d ",node + 1);
}
return;
}
int main()
{
freopen("input_dijkstra","r",stdin);
int cost[N],tmp_cost[N],path[N],tmp_path[N];
bool visited[N],flag;
int *dev_cost,*dev_tmp_cost,*dev_map,*dev_nv,*dev_path,*dev_tmp_path;
bool *dev_visited,*dev_flag;
int nv,ne;
scanf("%d%d",&nv,&ne);
//initialize
for(int i = 0; i < nv; ++i)
{
cost[i] = INF;
tmp_cost[i] = INF;
visited[i] = false;
for(int j = 0; j < nv; ++j)
map[i * N + j] = map[j * N + i] = INF;
}
//read all the edges
for(int i = 0; i < ne; ++i)
{
int p,q,w;
scanf("%d%d%d",&p,&q,&w);
map[p * N + q] = map[q * N + p] = w;
}
int source;
scanf("%d",&source);
cost[source] = tmp_cost[source] = 0;
visited[source] = true;
flag = true;
path[source] = -1;
tmp_path[source] = -1;
cout<<0<<endl;
hipMalloc((void**)&dev_cost,N * sizeof(int));
cout<<1<<endl;
hipMalloc((void**)&dev_tmp_cost,N * sizeof(int));
hipMalloc((void**)&dev_visited,N * sizeof(bool));
hipMalloc((void**)&dev_map,N * N * sizeof(int));
hipMalloc((void**)&dev_flag,sizeof(bool));
hipMalloc((void**)&dev_nv,sizeof(int));
hipMalloc((void**)&dev_path,N * sizeof(int));
hipMalloc((void**)&dev_tmp_path,N * sizeof(int));
hipMemcpy(dev_cost,cost,N * sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_tmp_cost,tmp_cost,N * sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_visited,visited,N * sizeof(bool),hipMemcpyHostToDevice);
hipMemcpy(dev_map,map,N * N * sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_flag,&flag,sizeof(bool),hipMemcpyHostToDevice);
hipMemcpy(dev_nv,&nv,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_path,path,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_tmp_path,tmp_path,N*sizeof(int),hipMemcpyHostToDevice);
while(flag)
{
flag = false;
kernel1<<<1,nv>>>(dev_nv,dev_map,dev_cost,dev_tmp_cost,dev_visited,dev_tmp_path);
hipMemcpy(dev_flag,&flag,sizeof(bool),hipMemcpyHostToDevice);
kernel2<<<1,nv>>>(dev_cost,dev_tmp_cost,dev_visited,dev_flag,dev_tmp_path,dev_path);
hipMemcpy(&flag,dev_flag,sizeof(bool),hipMemcpyDeviceToHost);
}
hipMemcpy(cost,dev_cost,N*sizeof(int),hipMemcpyDeviceToHost);
hipMemcpy(path,dev_path,N*sizeof(int),hipMemcpyDeviceToHost);
for(int i = 0; i < nv; ++i)
{
printf("Node %d cost = %2d path: ",i+1,cost[i]);
print_path(i,path);
printf("\n");
}
cout << endl;
return 0;
}
|
.text
.file "dijkstra.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__kernel1PiS_S_S_PbS_ # -- Begin function _Z22__device_stub__kernel1PiS_S_S_PbS_
.p2align 4, 0x90
.type _Z22__device_stub__kernel1PiS_S_S_PbS_,@function
_Z22__device_stub__kernel1PiS_S_S_PbS_: # @_Z22__device_stub__kernel1PiS_S_S_PbS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kernel1PiS_S_S_PbS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1PiS_S_S_PbS_, .Lfunc_end0-_Z22__device_stub__kernel1PiS_S_S_PbS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel2PiS_PbS0_S_S_ # -- Begin function _Z22__device_stub__kernel2PiS_PbS0_S_S_
.p2align 4, 0x90
.type _Z22__device_stub__kernel2PiS_PbS0_S_S_,@function
_Z22__device_stub__kernel2PiS_PbS0_S_S_: # @_Z22__device_stub__kernel2PiS_PbS0_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kernel2PiS_PbS0_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z22__device_stub__kernel2PiS_PbS0_S_S_, .Lfunc_end1-_Z22__device_stub__kernel2PiS_PbS0_S_S_
.cfi_endproc
# -- End function
.globl _Z10print_pathiPi # -- Begin function _Z10print_pathiPi
.p2align 4, 0x90
.type _Z10print_pathiPi,@function
_Z10print_pathiPi: # @_Z10print_pathiPi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
movslq %edi, %rax
movl (%rsi,%rax,4), %edi
cmpl $-1, %edi
je .LBB2_2
# %bb.1:
callq _Z10print_pathiPi
.LBB2_2:
incl %ebx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end2:
.size _Z10print_pathiPi, .Lfunc_end2-_Z10print_pathiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $17656, %rsp # imm = 0x44F8
.cfi_def_cfa_offset 17712
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq stdin(%rip), %rdx
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq freopen
leaq 16(%rsp), %rsi
leaq 20(%rsp), %rdx
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 16(%rsp), %ebx
testl %ebx, %ebx
jle .LBB3_5
# %bb.1: # %.lr.ph58
leaq 240(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movl $map, %eax
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %r14d, %ecx
andl $4194303, %ecx # imm = 0x3FFFFF
shlq $12, %rcx
movl $4144959, 5360(%rsp,%r14,4) # imm = 0x3F3F3F
movl $4144959, 13552(%rsp,%r14,4) # imm = 0x3F3F3F
movq %rax, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $4144959, (%rdx) # imm = 0x3F3F3F
movl $4144959, map(%rcx,%rsi,4) # imm = 0x3F3F3F
incq %rsi
addq $4096, %rdx # imm = 0x1000
cmpq %rsi, %rbx
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r14
addq $4, %rax
cmpq %rbx, %r14
jne .LBB3_2
.LBB3_5: # %.preheader
cmpl $0, 20(%rsp)
jle .LBB3_8
# %bb.6: # %.lr.ph60.preheader
leaq 1264(%rsp), %rbx
leaq 9456(%rsp), %r14
leaq 192(%rsp), %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_7: # %.lr.ph60
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %edi
movq %rbx, %rsi
movq %r14, %rdx
movq %r15, %rcx
xorl %eax, %eax
callq __isoc23_scanf
movl 192(%rsp), %eax
movl 9456(%rsp), %ecx
movl %ecx, %edx
shll $10, %edx
movl 1264(%rsp), %esi
addl %esi, %edx
movslq %edx, %rdx
movl %eax, map(,%rdx,4)
shll $10, %esi
addl %ecx, %esi
movslq %esi, %rcx
movl %eax, map(,%rcx,4)
incl %ebp
cmpl 20(%rsp), %ebp
jl .LBB3_7
.LBB3_8: # %._crit_edge61
leaq 156(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 156(%rsp), %rax
movl $0, 13552(%rsp,%rax,4)
movl $0, 5360(%rsp,%rax,4)
movb $1, 240(%rsp,%rax)
movb $1, 15(%rsp)
movl $-1, 1264(%rsp,%rax,4)
movl $-1, 9456(%rsp,%rax,4)
movl $_ZSt4cout, %edi
xorl %esi, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB3_12
.LBB3_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movl $_ZSt4cout, %edi
movl $1, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%rbx)
je .LBB3_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB3_16
.LBB3_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 64(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 168(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1, %esi
callq hipMalloc
leaq 160(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 56(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 48(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 32(%rsp), %rdi
leaq 5360(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
leaq 13552(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
leaq 240(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq 168(%rsp), %rdi
movl $map, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 15(%rsp), %rsi
movl $1, %edx
movl $1, %ecx
callq hipMemcpy
movq 160(%rsp), %rdi
leaq 16(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
leaq 1264(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
leaq 9456(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
cmpb $0, 15(%rsp)
je .LBB3_23
# %bb.17: # %.lr.ph63
movabsq $4294967296, %r15 # imm = 0x100000000
leaq 1(%r15), %rbx
leaq 184(%rsp), %r12
leaq 176(%rsp), %r13
leaq 192(%rsp), %rbp
leaq 15(%rsp), %r14
jmp .LBB3_18
.p2align 4, 0x90
.LBB3_22: # in Loop: Header=BB3_18 Depth=1
movq 24(%rsp), %rsi
movl $1, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
cmpb $0, 15(%rsp)
je .LBB3_23
.LBB3_18: # =>This Inner Loop Header: Depth=1
movb $0, 15(%rsp)
movl 16(%rsp), %edx
orq %r15, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_20
# %bb.19: # in Loop: Header=BB3_18 Depth=1
movq 160(%rsp), %rax
movq 168(%rsp), %rcx
movq 32(%rsp), %rdx
movq 64(%rsp), %rsi
movq 40(%rsp), %rdi
movq 48(%rsp), %r8
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movq %rsi, 120(%rsp)
movq %rdi, 112(%rsp)
movq %r8, 104(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 136(%rsp), %rax
movq %rax, 200(%rsp)
leaq 128(%rsp), %rax
movq %rax, 208(%rsp)
leaq 120(%rsp), %rax
movq %rax, 216(%rsp)
leaq 112(%rsp), %rax
movq %rax, 224(%rsp)
leaq 104(%rsp), %rax
movq %rax, 232(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z7kernel1PiS_S_S_PbS_, %edi
movq %rbp, %r9
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_20: # in Loop: Header=BB3_18 Depth=1
movq 24(%rsp), %rdi
movl $1, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl 16(%rsp), %edx
orq %r15, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_22
# %bb.21: # in Loop: Header=BB3_18 Depth=1
movq 32(%rsp), %rax
movq 64(%rsp), %rcx
movq 40(%rsp), %rdx
movq 24(%rsp), %rsi
movq 48(%rsp), %rdi
movq 56(%rsp), %r8
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movq %rsi, 120(%rsp)
movq %rdi, 112(%rsp)
movq %r8, 104(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 136(%rsp), %rax
movq %rax, 200(%rsp)
leaq 128(%rsp), %rax
movq %rax, 208(%rsp)
leaq 120(%rsp), %rax
movq %rax, 216(%rsp)
leaq 112(%rsp), %rax
movq %rax, 224(%rsp)
leaq 104(%rsp), %rax
movq %rax, 232(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z7kernel2PiS_PbS0_S_S_, %edi
movq %rbp, %r9
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_22
.LBB3_23: # %._crit_edge64
movq 32(%rsp), %rsi
leaq 5360(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
movq 56(%rsp), %rsi
leaq 1264(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
cmpl $0, 16(%rsp)
jle .LBB3_26
# %bb.24: # %.lr.ph67.preheader
leaq 1264(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_25: # %.lr.ph67
# =>This Inner Loop Header: Depth=1
leaq 1(%r14), %r15
movl 5360(%rsp,%r14,4), %edx
movl $.L.str.6, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl %r14d, %edi
movq %rbx, %rsi
callq _Z10print_pathiPi
movl $10, %edi
callq putchar@PLT
movslq 16(%rsp), %rax
movq %r15, %r14
cmpq %rax, %r15
jl .LBB3_25
.LBB3_26: # %._crit_edge68
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%rbx)
je .LBB3_29
# %bb.28:
movzbl 67(%rbx), %eax
jmp .LBB3_30
.LBB3_29:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $17656, %rsp # imm = 0x44F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_31:
.cfi_def_cfa_offset 17712
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1PiS_S_S_PbS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2PiS_PbS0_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type map,@object # @map
.bss
.globl map
.p2align 4, 0x0
map:
.zero 4194304
.size map, 4194304
.type path,@object # @path
.globl path
.p2align 4, 0x0
path:
.zero 4096
.size path, 4096
.type _Z7kernel1PiS_S_S_PbS_,@object # @_Z7kernel1PiS_S_S_PbS_
.section .rodata,"a",@progbits
.globl _Z7kernel1PiS_S_S_PbS_
.p2align 3, 0x0
_Z7kernel1PiS_S_S_PbS_:
.quad _Z22__device_stub__kernel1PiS_S_S_PbS_
.size _Z7kernel1PiS_S_S_PbS_, 8
.type _Z7kernel2PiS_PbS0_S_S_,@object # @_Z7kernel2PiS_PbS0_S_S_
.globl _Z7kernel2PiS_PbS0_S_S_
.p2align 3, 0x0
_Z7kernel2PiS_PbS0_S_S_:
.quad _Z22__device_stub__kernel2PiS_PbS0_S_S_
.size _Z7kernel2PiS_PbS0_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "input_dijkstra"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d%d"
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d%d%d"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Node %d cost = %2d path: "
.size .L.str.6, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kernel1PiS_S_S_PbS_"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel2PiS_PbS0_S_S_"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1PiS_S_S_PbS_
.addrsig_sym _Z22__device_stub__kernel2PiS_PbS0_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym map
.addrsig_sym _Z7kernel1PiS_S_S_PbS_
.addrsig_sym _Z7kernel2PiS_PbS0_S_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z7kernel2PiS_PbS0_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0209 */
/*0070*/ IMAD.WIDE R2, R0.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe200078e0209 */
/*0080*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.GT.AND P0, PT, R15, R6, PT ; /* 0x000000060f00720c */
/* 0x004fe20003f04270 */
/*00b0*/ IMAD.WIDE R6, R0, R9, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x000fd800078e0209 */
/*00c0*/ @P0 LDG.E R17, [R6.64] ; /* 0x0000000406110981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ @P0 IADD3 R12, P1, R0.reuse, c[0x0][0x170], RZ ; /* 0x00005c00000c0a10 */
/* 0x040fe20007f3e0ff */
/*00e0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.WIDE R8, R0.reuse, R9, c[0x0][0x188] ; /* 0x0000620000087625 */
/* 0x040fe200078e0209 */
/*0100*/ @P0 LEA.HI.X.SX32 R13, R0, c[0x0][0x174], 0x1, P1 ; /* 0x00005d00000d0a11 */
/* 0x000fe400008f0eff */
/*0110*/ @P0 PRMT R0, R10, 0x7610, R0 ; /* 0x000076100a000816 */
/* 0x000fe40000000000 */
/*0120*/ @P0 STG.E [R8.64], R17 ; /* 0x0000001108000986 */
/* 0x004fe8000c101904 */
/*0130*/ @P0 STG.E.U8 [R12.64], R0 ; /* 0x000000000c000986 */
/* 0x000fe8000c101104 */
/*0140*/ @P0 LDG.E R19, [R4.64] ; /* 0x0000000404130981 */
/* 0x000ea2000c1e1900 */
/*0150*/ @P0 MOV R10, c[0x0][0x178] ; /* 0x00005e00000a0a02 */
/* 0x000fe20000000f00 */
/*0160*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0b0624 */
/* 0x000fc400078e00ff */
/*0170*/ @P0 STG.E [R2.64], R19 ; /* 0x0000001302000986 */
/* 0x004fe8000c101904 */
/*0180*/ @P0 STG.E.U8 [R10.64], R0 ; /* 0x000000000a000986 */
/* 0x000fe8000c101104 */
/*0190*/ @P0 LDG.E R15, [R2.64] ; /* 0x00000004020f0981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x004fe8000c101904 */
/*01b0*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ STG.E [R6.64], R21 ; /* 0x0000001506007986 */
/* 0x004fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel1PiS_S_S_PbS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe40000011400 */
/*0060*/ IADD3 R4, P0, R0, c[0x0][0x180], RZ ; /* 0x0000600000047a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ IADD3.X R5, R7, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610007057a10 */
/* 0x000fca00007fe4ff */
/*0080*/ LDG.E.U8 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea4000c1e1100 */
/*0090*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*00a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*00c0*/ STG.E.U8 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e2000c101104 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*00e0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f06270 */
/*0100*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0110*/ SHF.L.U32 R4, R0, 0xa, RZ ; /* 0x0000000a00047819 */
/* 0x001fe200000006ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0130*/ HFMA2.MMA R13, -RZ, RZ, 0, 0 ; /* 0x00000000ff0d7435 */
/* 0x000fe200000001ff */
/*0140*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0150*/ MOV R19, c[0x0][0x18c] ; /* 0x0000630000137a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0170*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0180*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff107624 */
/* 0x000fe200078e00ff */
/*01a0*/ LEA R4, P0, R0.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c0000047a11 */
/* 0x040fe200078010ff */
/*01b0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0e7624 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff117624 */
/* 0x000fe200078e00ff */
/*01d0*/ LEA.HI.X R5, R0, c[0x0][0x174], R7, 0x2, P0 ; /* 0x00005d0000057a11 */
/* 0x000fc800000f1407 */
/*01e0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000e */
/*01f0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0011 */
/*0210*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ee2000c1e1900 */
/*0230*/ IADD3 R10, R10, R11, RZ ; /* 0x0000000b0a0a7210 */
/* 0x004fc80007ffe0ff */
/*0240*/ ISETP.GE.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x008fda0003f06270 */
/*0250*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a8224 */
/* 0x000fe400078e0010 */
/*0260*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b8224 */
/* 0x000fca00078e0013 */
/*0270*/ @!P0 STG.E [R10.64], R0 ; /* 0x000000000a008986 */
/* 0x0001e8000c101904 */
/*0280*/ @!P0 LDG.E R14, [R8.64] ; /* 0x00000004080e8981 */
/* 0x000ea8000c1e1900 */
/*0290*/ @!P0 LDG.E R15, [R4.64] ; /* 0x00000004040f8981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ @!P0 IADD3 R15, R14, R15, RZ ; /* 0x0000000f0e0f8210 */
/* 0x004fca0007ffe0ff */
/*02b0*/ @!P0 STG.E [R6.64], R15 ; /* 0x0000000f06008986 */
/* 0x0001e8000c101904 */
/*02c0*/ @!P0 LDG.E R12, [R2.64] ; /* 0x00000004020c8981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IADD3 R14, P2, R6, 0x4, RZ ; /* 0x00000004060e7810 */
/* 0x000fe40007f5e0ff */
/*02f0*/ IADD3 R8, P3, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f7e0ff */
/*0300*/ IADD3 R16, P1, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fe20007f3e0ff */
/*0310*/ IMAD.X R17, RZ, RZ, R7, P2 ; /* 0x000000ffff117224 */
/* 0x000fc400010e0607 */
/*0320*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0609 */
/*0330*/ IADD3.X R19, RZ, R19, RZ, P1, !PT ; /* 0x00000013ff137210 */
/* 0x000fe40000ffe4ff */
/*0340*/ ISETP.GE.AND P0, PT, R13, R12, PT ; /* 0x0000000c0d00720c */
/* 0x004fda0003f06270 */
/*0350*/ @!P0 BRA 0x1e0 ; /* 0xfffffe8000008947 */
/* 0x001fea000383ffff */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ BRA 0x370; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1PiS_S_S_PbS_
.globl _Z7kernel1PiS_S_S_PbS_
.p2align 8
.type _Z7kernel1PiS_S_S_PbS_,@function
_Z7kernel1PiS_S_S_PbS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v3, vcc_lo, s2, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
global_load_u8 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v0
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s6, 0
global_store_b8 v[3:4], v0, off
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[8:11], s[0:1], 0x8
v_dual_mov_b32 v0, 0 :: v_dual_lshlrev_b32 v3, 10, v1
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s10, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v6, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v8, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
global_load_b32 v6, v0, s[2:3]
v_add_co_u32 v4, vcc_lo, v4, 4
s_add_i32 s6, s6, 1
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, s6, v6
s_cbranch_vccz .LBB0_6
.LBB0_4:
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
global_load_b32 v8, v0, s[4:5]
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v6, v7, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v6, v8
s_cbranch_execz .LBB0_3
global_store_b32 v0, v1, s[0:1]
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v7, v6
global_store_b32 v0, v6, s[4:5]
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1PiS_S_S_PbS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1PiS_S_S_PbS_, .Lfunc_end0-_Z7kernel1PiS_S_S_PbS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7kernel2PiS_PbS0_S_S_
.globl _Z7kernel2PiS_PbS0_S_S_
.p2align 8
.type _Z7kernel2PiS_PbS0_S_S_,@function
_Z7kernel2PiS_PbS0_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v1, vcc_lo
global_load_b32 v8, v[2:3], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v8, v9
s_cbranch_execz .LBB1_2
v_add_co_u32 v8, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v1, vcc_lo
s_load_b128 s[8:11], s[0:1], 0x10
global_load_b32 v10, v[8:9], off
v_add_co_u32 v8, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v10, off
global_load_b32 v8, v[6:7], off
v_dual_mov_b32 v9, 1 :: v_dual_mov_b32 v10, 0
global_store_b8 v[4:5], v9, off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v8, off
global_store_b8 v10, v9, s[10:11]
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v4, off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel2PiS_PbS0_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7kernel2PiS_PbS0_S_S_, .Lfunc_end1-_Z7kernel2PiS_PbS0_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1PiS_S_S_PbS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel1PiS_S_S_PbS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel2PiS_PbS0_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7kernel2PiS_PbS0_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000cb8ae_00000000-6_dijkstra.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.text
.globl _Z10print_pathiPi
.type _Z10print_pathiPi, @function
_Z10print_pathiPi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
movslq %edi, %rax
movl (%rsi,%rax,4), %edi
cmpl $-1, %edi
je .L7
call _Z10print_pathiPi
leal 1(%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leal 1(%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE3669:
.size _Z10print_pathiPi, .-_Z10print_pathiPi
.globl _Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_
.type _Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_, @function
_Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_:
.LFB3695:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7kernel1PiS_S_S_PbS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_, .-_Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_
.globl _Z7kernel1PiS_S_S_PbS_
.type _Z7kernel1PiS_S_S_PbS_, @function
_Z7kernel1PiS_S_S_PbS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7kernel1PiS_S_S_PbS_, .-_Z7kernel1PiS_S_S_PbS_
.globl _Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_
.type _Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_, @function
_Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7kernel2PiS_PbS0_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_, .-_Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_
.globl _Z7kernel2PiS_PbS0_S_S_
.type _Z7kernel2PiS_PbS0_S_S_, @function
_Z7kernel2PiS_PbS0_S_S_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z7kernel2PiS_PbS0_S_S_, .-_Z7kernel2PiS_PbS0_S_S_
.section .rodata.str1.1
.LC1:
.string "r"
.LC2:
.string "input_dijkstra"
.LC3:
.string "%d%d"
.LC4:
.string "%d%d%d"
.LC5:
.string "%d"
.LC6:
.string "Node %d cost = %2d path: "
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -16384(%rsp), %r11
.cfi_def_cfa 11, 16440
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1160, %rsp
.cfi_def_cfa_offset 17600
movq %fs:40, %rax
movq %rax, 17528(%rsp)
xorl %eax, %eax
movq stdin(%rip), %rdx
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call freopen@PLT
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %r8d
testl %r8d, %r8d
jle .L25
leaq map(%rip), %rdi
movslq %r8d, %r8
movq %r8, %rcx
salq $12, %rcx
addq %rdi, %rcx
movq %r8, %r9
negq %r9
salq $12, %r9
movl $0, %esi
.L27:
movl $4144959, 1136(%rsp,%rsi,4)
movl $4144959, 5232(%rsp,%rsi,4)
movb $0, 112(%rsp,%rsi)
leaq (%rcx,%r9), %rax
movq %rdi, %rdx
.L26:
movl $4144959, (%rax)
movl $4144959, (%rdx)
addq $4096, %rax
addq $4, %rdx
cmpq %rcx, %rax
jne .L26
addq $1, %rsi
addq $4096, %rdi
addq $4, %rcx
cmpq %r8, %rsi
jne .L27
.L25:
cmpl $0, 16(%rsp)
jle .L28
movl $0, %ebx
leaq 100(%rsp), %r14
leaq 88(%rsp), %r13
leaq .LC4(%rip), %r12
leaq map(%rip), %rbp
.L29:
leaq 80(%rsp), %rsi
movq %r14, %rcx
movq %r13, %rdx
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 88(%rsp), %esi
movl 80(%rsp), %eax
movl 100(%rsp), %ecx
movl %esi, %edx
sall $10, %edx
addl %eax, %edx
movslq %edx, %rdx
movl %ecx, 0(%rbp,%rdx,4)
sall $10, %eax
addl %esi, %eax
cltq
movl %ecx, 0(%rbp,%rax,4)
addl $1, %ebx
cmpl %ebx, 16(%rsp)
jg .L29
.L28:
leaq 20(%rsp), %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 20(%rsp), %rax
movl $0, 5232(%rsp,%rax,4)
movl $0, 1136(%rsp,%rax,4)
movb $1, 112(%rsp,%rax)
movb $1, 11(%rsp)
movl $-1, 9328(%rsp,%rax,4)
movl $-1, 13424(%rsp,%rax,4)
movl $0, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $1, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 1136(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 5232(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
leaq map(%rip), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 11(%rsp), %rsi
movl $1, %ecx
movl $1, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq 9328(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 13424(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
cmpb $0, 11(%rsp)
je .L30
leaq 11(%rsp), %rbx
jmp .L33
.L43:
movq 64(%rsp), %r9
movq 72(%rsp), %r8
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_
jmp .L31
.L32:
movl $2, %ecx
movl $1, %edx
movq 80(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
cmpb $0, 11(%rsp)
je .L30
.L33:
movb $0, 11(%rsp)
movl 12(%rsp), %eax
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L31:
movl $1, %ecx
movl $1, %edx
movq %rbx, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq 56(%rsp), %r9
movq 64(%rsp), %r8
movq 80(%rsp), %rcx
movq 72(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_
jmp .L32
.L30:
leaq 1136(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leaq 9328(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq 56(%rsp), %rsi
call cudaMemcpy@PLT
cmpl $0, 12(%rsp)
jle .L34
leaq 1136(%rsp), %rbp
movl $0, %ebx
leaq .LC6(%rip), %r15
leaq 9328(%rsp), %r14
leaq .LC7(%rip), %r13
.L35:
movl %ebx, %r12d
addl $1, %ebx
movl 0(%rbp), %ecx
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rsi
movl %r12d, %edi
call _Z10print_pathiPi
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpl 12(%rsp), %ebx
jl .L35
.L34:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 17528(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $17544, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z7kernel2PiS_PbS0_S_S_"
.LC9:
.string "_Z7kernel1PiS_S_S_PbS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2PiS_PbS0_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1PiS_S_S_PbS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl path
.bss
.align 32
.type path, @object
.size path, 4096
path:
.zero 4096
.globl map
.align 32
.type map, @object
.size map, 4194304
map:
.zero 4194304
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "dijkstra.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__kernel1PiS_S_S_PbS_ # -- Begin function _Z22__device_stub__kernel1PiS_S_S_PbS_
.p2align 4, 0x90
.type _Z22__device_stub__kernel1PiS_S_S_PbS_,@function
_Z22__device_stub__kernel1PiS_S_S_PbS_: # @_Z22__device_stub__kernel1PiS_S_S_PbS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kernel1PiS_S_S_PbS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1PiS_S_S_PbS_, .Lfunc_end0-_Z22__device_stub__kernel1PiS_S_S_PbS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__kernel2PiS_PbS0_S_S_ # -- Begin function _Z22__device_stub__kernel2PiS_PbS0_S_S_
.p2align 4, 0x90
.type _Z22__device_stub__kernel2PiS_PbS0_S_S_,@function
_Z22__device_stub__kernel2PiS_PbS0_S_S_: # @_Z22__device_stub__kernel2PiS_PbS0_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kernel2PiS_PbS0_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z22__device_stub__kernel2PiS_PbS0_S_S_, .Lfunc_end1-_Z22__device_stub__kernel2PiS_PbS0_S_S_
.cfi_endproc
# -- End function
.globl _Z10print_pathiPi # -- Begin function _Z10print_pathiPi
.p2align 4, 0x90
.type _Z10print_pathiPi,@function
_Z10print_pathiPi: # @_Z10print_pathiPi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
movslq %edi, %rax
movl (%rsi,%rax,4), %edi
cmpl $-1, %edi
je .LBB2_2
# %bb.1:
callq _Z10print_pathiPi
.LBB2_2:
incl %ebx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end2:
.size _Z10print_pathiPi, .Lfunc_end2-_Z10print_pathiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $17656, %rsp # imm = 0x44F8
.cfi_def_cfa_offset 17712
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq stdin(%rip), %rdx
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq freopen
leaq 16(%rsp), %rsi
leaq 20(%rsp), %rdx
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 16(%rsp), %ebx
testl %ebx, %ebx
jle .LBB3_5
# %bb.1: # %.lr.ph58
leaq 240(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
movl $map, %eax
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %r14d, %ecx
andl $4194303, %ecx # imm = 0x3FFFFF
shlq $12, %rcx
movl $4144959, 5360(%rsp,%r14,4) # imm = 0x3F3F3F
movl $4144959, 13552(%rsp,%r14,4) # imm = 0x3F3F3F
movq %rax, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $4144959, (%rdx) # imm = 0x3F3F3F
movl $4144959, map(%rcx,%rsi,4) # imm = 0x3F3F3F
incq %rsi
addq $4096, %rdx # imm = 0x1000
cmpq %rsi, %rbx
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r14
addq $4, %rax
cmpq %rbx, %r14
jne .LBB3_2
.LBB3_5: # %.preheader
cmpl $0, 20(%rsp)
jle .LBB3_8
# %bb.6: # %.lr.ph60.preheader
leaq 1264(%rsp), %rbx
leaq 9456(%rsp), %r14
leaq 192(%rsp), %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_7: # %.lr.ph60
# =>This Inner Loop Header: Depth=1
movl $.L.str.4, %edi
movq %rbx, %rsi
movq %r14, %rdx
movq %r15, %rcx
xorl %eax, %eax
callq __isoc23_scanf
movl 192(%rsp), %eax
movl 9456(%rsp), %ecx
movl %ecx, %edx
shll $10, %edx
movl 1264(%rsp), %esi
addl %esi, %edx
movslq %edx, %rdx
movl %eax, map(,%rdx,4)
shll $10, %esi
addl %ecx, %esi
movslq %esi, %rcx
movl %eax, map(,%rcx,4)
incl %ebp
cmpl 20(%rsp), %ebp
jl .LBB3_7
.LBB3_8: # %._crit_edge61
leaq 156(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 156(%rsp), %rax
movl $0, 13552(%rsp,%rax,4)
movl $0, 5360(%rsp,%rax,4)
movb $1, 240(%rsp,%rax)
movb $1, 15(%rsp)
movl $-1, 1264(%rsp,%rax,4)
movl $-1, 9456(%rsp,%rax,4)
movl $_ZSt4cout, %edi
xorl %esi, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB3_12
.LBB3_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movl $_ZSt4cout, %edi
movl $1, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%rbx)
je .LBB3_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB3_16
.LBB3_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 64(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 168(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1, %esi
callq hipMalloc
leaq 160(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 56(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 48(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 32(%rsp), %rdi
leaq 5360(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
leaq 13552(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
leaq 240(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq 168(%rsp), %rdi
movl $map, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 15(%rsp), %rsi
movl $1, %edx
movl $1, %ecx
callq hipMemcpy
movq 160(%rsp), %rdi
leaq 16(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
leaq 1264(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
leaq 9456(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
cmpb $0, 15(%rsp)
je .LBB3_23
# %bb.17: # %.lr.ph63
movabsq $4294967296, %r15 # imm = 0x100000000
leaq 1(%r15), %rbx
leaq 184(%rsp), %r12
leaq 176(%rsp), %r13
leaq 192(%rsp), %rbp
leaq 15(%rsp), %r14
jmp .LBB3_18
.p2align 4, 0x90
.LBB3_22: # in Loop: Header=BB3_18 Depth=1
movq 24(%rsp), %rsi
movl $1, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
cmpb $0, 15(%rsp)
je .LBB3_23
.LBB3_18: # =>This Inner Loop Header: Depth=1
movb $0, 15(%rsp)
movl 16(%rsp), %edx
orq %r15, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_20
# %bb.19: # in Loop: Header=BB3_18 Depth=1
movq 160(%rsp), %rax
movq 168(%rsp), %rcx
movq 32(%rsp), %rdx
movq 64(%rsp), %rsi
movq 40(%rsp), %rdi
movq 48(%rsp), %r8
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movq %rsi, 120(%rsp)
movq %rdi, 112(%rsp)
movq %r8, 104(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 136(%rsp), %rax
movq %rax, 200(%rsp)
leaq 128(%rsp), %rax
movq %rax, 208(%rsp)
leaq 120(%rsp), %rax
movq %rax, 216(%rsp)
leaq 112(%rsp), %rax
movq %rax, 224(%rsp)
leaq 104(%rsp), %rax
movq %rax, 232(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z7kernel1PiS_S_S_PbS_, %edi
movq %rbp, %r9
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_20: # in Loop: Header=BB3_18 Depth=1
movq 24(%rsp), %rdi
movl $1, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl 16(%rsp), %edx
orq %r15, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_22
# %bb.21: # in Loop: Header=BB3_18 Depth=1
movq 32(%rsp), %rax
movq 64(%rsp), %rcx
movq 40(%rsp), %rdx
movq 24(%rsp), %rsi
movq 48(%rsp), %rdi
movq 56(%rsp), %r8
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movq %rsi, 120(%rsp)
movq %rdi, 112(%rsp)
movq %r8, 104(%rsp)
leaq 144(%rsp), %rax
movq %rax, 192(%rsp)
leaq 136(%rsp), %rax
movq %rax, 200(%rsp)
leaq 128(%rsp), %rax
movq %rax, 208(%rsp)
leaq 120(%rsp), %rax
movq %rax, 216(%rsp)
leaq 112(%rsp), %rax
movq %rax, 224(%rsp)
leaq 104(%rsp), %rax
movq %rax, 232(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z7kernel2PiS_PbS0_S_S_, %edi
movq %rbp, %r9
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_22
.LBB3_23: # %._crit_edge64
movq 32(%rsp), %rsi
leaq 5360(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
movq 56(%rsp), %rsi
leaq 1264(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
cmpl $0, 16(%rsp)
jle .LBB3_26
# %bb.24: # %.lr.ph67.preheader
leaq 1264(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_25: # %.lr.ph67
# =>This Inner Loop Header: Depth=1
leaq 1(%r14), %r15
movl 5360(%rsp,%r14,4), %edx
movl $.L.str.6, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl %r14d, %edi
movq %rbx, %rsi
callq _Z10print_pathiPi
movl $10, %edi
callq putchar@PLT
movslq 16(%rsp), %rax
movq %r15, %r14
cmpq %rax, %r15
jl .LBB3_25
.LBB3_26: # %._crit_edge68
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_31
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%rbx)
je .LBB3_29
# %bb.28:
movzbl 67(%rbx), %eax
jmp .LBB3_30
.LBB3_29:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $17656, %rsp # imm = 0x44F8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_31:
.cfi_def_cfa_offset 17712
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1PiS_S_S_PbS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel2PiS_PbS0_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type map,@object # @map
.bss
.globl map
.p2align 4, 0x0
map:
.zero 4194304
.size map, 4194304
.type path,@object # @path
.globl path
.p2align 4, 0x0
path:
.zero 4096
.size path, 4096
.type _Z7kernel1PiS_S_S_PbS_,@object # @_Z7kernel1PiS_S_S_PbS_
.section .rodata,"a",@progbits
.globl _Z7kernel1PiS_S_S_PbS_
.p2align 3, 0x0
_Z7kernel1PiS_S_S_PbS_:
.quad _Z22__device_stub__kernel1PiS_S_S_PbS_
.size _Z7kernel1PiS_S_S_PbS_, 8
.type _Z7kernel2PiS_PbS0_S_S_,@object # @_Z7kernel2PiS_PbS0_S_S_
.globl _Z7kernel2PiS_PbS0_S_S_
.p2align 3, 0x0
_Z7kernel2PiS_PbS0_S_S_:
.quad _Z22__device_stub__kernel2PiS_PbS0_S_S_
.size _Z7kernel2PiS_PbS0_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "input_dijkstra"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d%d"
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d%d%d"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Node %d cost = %2d path: "
.size .L.str.6, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7kernel1PiS_S_S_PbS_"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7kernel2PiS_PbS0_S_S_"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1PiS_S_S_PbS_
.addrsig_sym _Z22__device_stub__kernel2PiS_PbS0_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym map
.addrsig_sym _Z7kernel1PiS_S_S_PbS_
.addrsig_sym _Z7kernel2PiS_PbS0_S_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*!
* \brief Sort.
*/
#include <iostream>
#include <thrust/sort.h>
#include <thrust/device_vector.h>
#define CUDA_CHECK(condition) \
do { \
cudaError_t error = condition; \
if (error != cudaSuccess) { \
fprintf(stderr, "CUDA_CHECK error in line %d of file %s \
: %s \n", __LINE__, __FILE__, cudaGetErrorString(cudaGetLastError()) ); \
exit(EXIT_FAILURE); \
} \
} while(0);
void TestDataInCPU() {
/////////////////////////////////////////////////////
{
const int N = 6;
int arr[N] = { 1, 4, 2, 8, 5, 7 };
thrust::sort(arr, arr + N);
for (int i = 0; i < N; i++)
std::cout << arr[i] << ", ";
}
std::cout << std::endl << "Finish Test1." << std::endl;
/////////////////////////////////////////////////////
{
const int N = 6;
int arr[N] = { 1, 4, 2, 8, 5, 7 };
thrust::stable_sort(arr, arr + N, thrust::greater<int>());
for (int i = 0; i < N; i++)
std::cout << arr[i] << ", ";
}
std::cout << std::endl << "Finish Test2." << std::endl;
/////////////////////////////////////////////////////
{
const int N = 6;
int keys[N] = { 1, 4, 2, 8, 5, 7 };
char values[N] = { 'a', 'b', 'c', 'd', 'e', 'f' };
thrust::sort_by_key(keys, keys + N, values);
for (int i = 0; i < N; i++)
std::cout << values[i] << "(" << keys[i] << "), ";
// keys is now { 1, 2, 4, 5, 7, 8}
// values is now {'a', 'c', 'b', 'e', 'f', 'd'}
}
std::cout << std::endl << "Finish Test3." << std::endl;
}
void TestDataInGPU() {
////////////////////////////////////////
{
const int N = 6;
int arr[N] = { 1, 4, 2, 8, 5, 7 };
thrust::device_vector<int> d_x(6, 1);
for (int i = 0; i < N; i++)
d_x[i] = arr[i];
thrust::sort(d_x.begin(), d_x.end());
for (int i = 0; i < N; i++)
std::cout << d_x[i] << ", ";
}
std::cout << std::endl << "Finish Test4." << std::endl;
/////////////////////////////////////////
{
const int N = 6;
int arr[N] = { 1, 4, 2, 8, 5, 7 };
int *d_x;
CUDA_CHECK(cudaMalloc((void **)&d_x, sizeof(int) * N));
CUDA_CHECK(cudaMemcpy(d_x, arr, sizeof(int) * N, cudaMemcpyHostToDevice));
thrust::device_ptr <int > dev_ptr(d_x);
thrust::sort(dev_ptr, dev_ptr +N);
CUDA_CHECK(cudaMemcpy(arr, d_x, sizeof(int) * N, cudaMemcpyDeviceToHost));
for (int i = 0; i < N; i++)
std::cout << arr[i] << ", ";
CUDA_CHECK(cudaFree(d_x));
}
std::cout << std::endl << "Finish Test5." << std::endl;
}
int main(void) {
TestDataInCPU();
TestDataInGPU();
return 0;
}
|
/*!
* \brief Sort.
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <thrust/sort.h>
#include <thrust/device_vector.h>
#define CUDA_CHECK(condition) \
do { \
hipError_t error = condition; \
if (error != hipSuccess) { \
fprintf(stderr, "CUDA_CHECK error in line %d of file %s \
: %s \n", __LINE__, __FILE__, hipGetErrorString(hipGetLastError()) ); \
exit(EXIT_FAILURE); \
} \
} while(0);
void TestDataInCPU() {
/////////////////////////////////////////////////////
{
const int N = 6;
int arr[N] = { 1, 4, 2, 8, 5, 7 };
thrust::sort(arr, arr + N);
for (int i = 0; i < N; i++)
std::cout << arr[i] << ", ";
}
std::cout << std::endl << "Finish Test1." << std::endl;
/////////////////////////////////////////////////////
{
const int N = 6;
int arr[N] = { 1, 4, 2, 8, 5, 7 };
thrust::stable_sort(arr, arr + N, thrust::greater<int>());
for (int i = 0; i < N; i++)
std::cout << arr[i] << ", ";
}
std::cout << std::endl << "Finish Test2." << std::endl;
/////////////////////////////////////////////////////
{
const int N = 6;
int keys[N] = { 1, 4, 2, 8, 5, 7 };
char values[N] = { 'a', 'b', 'c', 'd', 'e', 'f' };
thrust::sort_by_key(keys, keys + N, values);
for (int i = 0; i < N; i++)
std::cout << values[i] << "(" << keys[i] << "), ";
// keys is now { 1, 2, 4, 5, 7, 8}
// values is now {'a', 'c', 'b', 'e', 'f', 'd'}
}
std::cout << std::endl << "Finish Test3." << std::endl;
}
void TestDataInGPU() {
////////////////////////////////////////
{
const int N = 6;
int arr[N] = { 1, 4, 2, 8, 5, 7 };
thrust::device_vector<int> d_x(6, 1);
for (int i = 0; i < N; i++)
d_x[i] = arr[i];
thrust::sort(d_x.begin(), d_x.end());
for (int i = 0; i < N; i++)
std::cout << d_x[i] << ", ";
}
std::cout << std::endl << "Finish Test4." << std::endl;
/////////////////////////////////////////
{
const int N = 6;
int arr[N] = { 1, 4, 2, 8, 5, 7 };
int *d_x;
CUDA_CHECK(hipMalloc((void **)&d_x, sizeof(int) * N));
CUDA_CHECK(hipMemcpy(d_x, arr, sizeof(int) * N, hipMemcpyHostToDevice));
thrust::device_ptr <int > dev_ptr(d_x);
thrust::sort(dev_ptr, dev_ptr +N);
CUDA_CHECK(hipMemcpy(arr, d_x, sizeof(int) * N, hipMemcpyDeviceToHost));
for (int i = 0; i < N; i++)
std::cout << arr[i] << ", ";
CUDA_CHECK(hipFree(d_x));
}
std::cout << std::endl << "Finish Test5." << std::endl;
}
int main(void) {
TestDataInCPU();
TestDataInGPU();
return 0;
}
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void reduction_kernel_complete_unrolling8_1(int * input, int * temp, int size)
{
int tid = threadIdx.x;
int index = blockDim.x * blockIdx.x * 8 + threadIdx.x;
int * i_data = input + blockDim.x * blockIdx.x * 8;
if ((index + 7 * blockDim.x) < size)
{
int a1 = input[index];
int a2 = input[index + blockDim.x];
int a3 = input[index + 2 * blockDim.x];
int a4 = input[index + 3 * blockDim.x];
int a5 = input[index + 4 * blockDim.x];
int a6 = input[index + 5 * blockDim.x];
int a7 = input[index + 6 * blockDim.x];
int a8 = input[index + 7 * blockDim.x];
input[index] = a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8;
}
__syncthreads();
//complete unrolling manually
//if the block dim == 1024
if (blockDim.x == 1024 && tid < 512)
i_data[tid] += i_data[tid + 512];
__syncthreads();
if (blockDim.x >= 512 && tid < 256)
i_data[tid] += i_data[tid + 256];
__syncthreads();
if (blockDim.x >= 256 && tid < 128)
i_data[tid] += i_data[tid + 128];
__syncthreads();
if (blockDim.x >= 128 && tid < 64)
i_data[tid] += i_data[tid + 64];
__syncthreads();
// warp unrolling
if (tid < 32)
{
volatile int * vsmem = i_data;
vsmem[tid] += vsmem[tid + 32];
vsmem[tid] += vsmem[tid + 16];
vsmem[tid] += vsmem[tid + 8];
vsmem[tid] += vsmem[tid + 4];
vsmem[tid] += vsmem[tid + 2];
vsmem[tid] += vsmem[tid + 1];
}
if (tid == 0)
{
temp[blockIdx.x] = i_data[0];
}
}
|
code for sm_80
Function : _Z38reduction_kernel_complete_unrolling8_1PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0060*/ BSSY B0, 0x350 ; /* 0x000002e000007945 */
/* 0x000fe20003800000 */
/*0070*/ IMAD R2, R0, c[0x0][0x0], RZ ; /* 0x0000000000027a24 */
/* 0x001fc800078e02ff */
/*0080*/ IMAD.SHL.U32 R2, R2, 0x8, RZ ; /* 0x0000000802027824 */
/* 0x000fe200078e00ff */
/*0090*/ ISETP.GT.AND P0, PT, R9.reuse, 0x1ff, PT ; /* 0x000001ff0900780c */
/* 0x042fe40003f04270 */
/*00a0*/ ISETP.GT.AND P1, PT, R9.reuse, 0xff, PT ; /* 0x000000ff0900780c */
/* 0x040fe20003f24270 */
/*00b0*/ IMAD.IADD R4, R2, 0x1, R9 ; /* 0x0000000102047824 */
/* 0x000fe200078e0209 */
/*00c0*/ ISETP.GT.AND P2, PT, R9.reuse, 0x7f, PT ; /* 0x0000007f0900780c */
/* 0x040fe40003f44270 */
/*00d0*/ ISETP.GT.AND P3, PT, R9, 0x3f, PT ; /* 0x0000003f0900780c */
/* 0x000fe20003f64270 */
/*00e0*/ IMAD R6, R3.reuse, 0x7, R4 ; /* 0x0000000703067824 */
/* 0x040fe200078e0204 */
/*00f0*/ ISETP.NE.OR P0, PT, R3.reuse, 0x400, P0 ; /* 0x000004000300780c */
/* 0x040fe40000705670 */
/*0100*/ ISETP.LT.U32.OR P1, PT, R3, 0x200, P1 ; /* 0x000002000300780c */
/* 0x000fc40000f21470 */
/*0110*/ ISETP.GE.U32.AND P4, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f86070 */
/*0120*/ ISETP.LT.U32.OR P2, PT, R3.reuse, 0x100, P2 ; /* 0x000001000300780c */
/* 0x040fe40001741470 */
/*0130*/ ISETP.LT.U32.OR P3, PT, R3, 0x80, P3 ; /* 0x000000800300780c */
/* 0x000fe20001f61470 */
/*0140*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0007 */
/*0150*/ ISETP.GT.AND P5, PT, R9.reuse, 0x1f, PT ; /* 0x0000001f0900780c */
/* 0x040fe40003fa4270 */
/*0160*/ ISETP.NE.AND P6, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fca0003fc5270 */
/*0170*/ @P4 BRA 0x340 ; /* 0x000001c000004947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R22, R4, c[0x0][0x0], RZ ; /* 0x0000000004167a10 */
/* 0x000fe20007ffe0ff */
/*0190*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fc600000001ff */
/*01a0*/ IADD3 R20, R22, c[0x0][0x0], RZ ; /* 0x0000000016147a10 */
/* 0x000fc80007ffe0ff */
/*01b0*/ IADD3 R12, R20, c[0x0][0x0], RZ ; /* 0x00000000140c7a10 */
/* 0x000fc60007ffe0ff */
/*01c0*/ IMAD.WIDE.U32 R20, R20, R11, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fe200078e000b */
/*01d0*/ IADD3 R14, R12, c[0x0][0x0], RZ ; /* 0x000000000c0e7a10 */
/* 0x000fc60007ffe0ff */
/*01e0*/ IMAD.WIDE.U32 R22, R22, R11.reuse, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x080fe200078e000b */
/*01f0*/ IADD3 R16, R14, c[0x0][0x0], RZ ; /* 0x000000000e107a10 */
/* 0x000fe20007ffe0ff */
/*0200*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000ea4000c1e1900 */
/*0210*/ IMAD.WIDE R4, R4, R11.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe200078e020b */
/*0220*/ IADD3 R18, R16, c[0x0][0x0], RZ ; /* 0x0000000010127a10 */
/* 0x000fe20007ffe0ff */
/*0230*/ LDG.E R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD.WIDE.U32 R12, R12, R11.reuse, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x080fe400078e000b */
/*0250*/ LDG.E R24, [R4.64] ; /* 0x0000000404187981 */
/* 0x000ea4000c1e1900 */
/*0260*/ IMAD.WIDE.U32 R14, R14, R11, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc400078e000b */
/*0270*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ee4000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R16, R16, R11.reuse, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x080fe400078e000b */
/*0290*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee4000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R18, R18, R11.reuse, c[0x0][0x160] ; /* 0x0000580012127625 */
/* 0x080fe400078e000b */
/*02b0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000f24000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R10, R6, R11, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fc400078e000b */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f62000c1e1900 */
/*02f0*/ IADD3 R8, R21, R8, R24 ; /* 0x0000000815087210 */
/* 0x004fc80007ffe018 */
/*0300*/ IADD3 R8, R14, R8, R13 ; /* 0x000000080e087210 */
/* 0x008fc80007ffe00d */
/*0310*/ IADD3 R8, R18, R8, R17 ; /* 0x0000000812087210 */
/* 0x010fca0007ffe011 */
/*0320*/ IMAD.IADD R21, R8, 0x1, R11 ; /* 0x0000000108157824 */
/* 0x020fca00078e020b */
/*0330*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0001e4000c101904 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0360*/ IMAD.WIDE R4, R9, 0x4, R2 ; /* 0x0000000409047825 */
/* 0x001fca00078e0202 */
/*0370*/ BSSY B0, 0x3e0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0380*/ @P0 BRA 0x3d0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R9, [R4.64+0x800] ; /* 0x0008000404097981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x004fca00078e0209 */
/*03c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03f0*/ BSSY B0, 0x460 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0400*/ @P1 BRA 0x450 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0410*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R9, [R4.64+0x400] ; /* 0x0004000404097981 */
/* 0x001ea4000c1e1900 */
/*0430*/ IADD3 R9, R6, R9, RZ ; /* 0x0000000906097210 */
/* 0x004fca0007ffe0ff */
/*0440*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ BSSY B0, 0x4e0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0480*/ @P2 BRA 0x4d0 ; /* 0x0000004000002947 */
/* 0x000fea0003800000 */
/*0490*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R9, [R4.64+0x200] ; /* 0x0002000404097981 */
/* 0x001ea4000c1e1900 */
/*04b0*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x004fca00078e0209 */
/*04c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04f0*/ BSSY B0, 0x560 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0500*/ @P3 BRA 0x550 ; /* 0x0000004000003947 */
/* 0x000fea0003800000 */
/*0510*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0520*/ LDG.E R9, [R4.64+0x100] ; /* 0x0001000404097981 */
/* 0x001ea4000c1e1900 */
/*0530*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x004fca00078e0209 */
/*0540*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0550*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0560*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0570*/ BSSY B0, 0x720 ; /* 0x000001a000007945 */
/* 0x000fe20003800000 */
/*0580*/ @P5 BRA 0x710 ; /* 0x0000018000005947 */
/* 0x000fea0003800000 */
/*0590*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1f5900 */
/*05a0*/ LDG.E.STRONG.SYS R9, [R4.64+0x80] ; /* 0x0000800404097981 */
/* 0x001ea4000c1f5900 */
/*05b0*/ IADD3 R9, R6, R9, RZ ; /* 0x0000000906097210 */
/* 0x004fca0007ffe0ff */
/*05c0*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c115904 */
/*05d0*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1f5900 */
/*05e0*/ LDG.E.STRONG.SYS R11, [R4.64+0x40] ; /* 0x00004004040b7981 */
/* 0x000ea4000c1f5900 */
/*05f0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x004fca00078e020b */
/*0600*/ STG.E.STRONG.SYS [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0003e8000c115904 */
/*0610*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1f5900 */
/*0620*/ LDG.E.STRONG.SYS R13, [R4.64+0x20] ; /* 0x00002004040d7981 */
/* 0x000ea4000c1f5900 */
/*0630*/ IMAD.IADD R13, R6, 0x1, R13 ; /* 0x00000001060d7824 */
/* 0x004fca00078e020d */
/*0640*/ STG.E.STRONG.SYS [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0005e8000c115904 */
/*0650*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee8000c1f5900 */
/*0660*/ LDG.E.STRONG.SYS R15, [R4.64+0x10] ; /* 0x00001004040f7981 */
/* 0x000ee4000c1f5900 */
/*0670*/ IADD3 R15, R6, R15, RZ ; /* 0x0000000f060f7210 */
/* 0x008fca0007ffe0ff */
/*0680*/ STG.E.STRONG.SYS [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0005e8000c115904 */
/*0690*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee8000c1f5900 */
/*06a0*/ LDG.E.STRONG.SYS R9, [R4.64+0x8] ; /* 0x0000080404097981 */
/* 0x001ee4000c1f5900 */
/*06b0*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x008fca00078e0209 */
/*06c0*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0005e8000c115904 */
/*06d0*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee8000c1f5900 */
/*06e0*/ LDG.E.STRONG.SYS R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x002ee4000c1f5900 */
/*06f0*/ IADD3 R11, R6, R11, RZ ; /* 0x0000000b060b7210 */
/* 0x008fca0007ffe0ff */
/*0700*/ STG.E.STRONG.SYS [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0005e4000c115904 */
/*0710*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0720*/ @P6 EXIT ; /* 0x000000000000694d */
/* 0x000fea0003800000 */
/*0730*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x005fca00078e0007 */
/*0750*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x008fe2000c101904 */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void reduction_kernel_complete_unrolling8_1(int * input, int * temp, int size)
{
int tid = threadIdx.x;
int index = blockDim.x * blockIdx.x * 8 + threadIdx.x;
int * i_data = input + blockDim.x * blockIdx.x * 8;
if ((index + 7 * blockDim.x) < size)
{
int a1 = input[index];
int a2 = input[index + blockDim.x];
int a3 = input[index + 2 * blockDim.x];
int a4 = input[index + 3 * blockDim.x];
int a5 = input[index + 4 * blockDim.x];
int a6 = input[index + 5 * blockDim.x];
int a7 = input[index + 6 * blockDim.x];
int a8 = input[index + 7 * blockDim.x];
input[index] = a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8;
}
__syncthreads();
//complete unrolling manually
//if the block dim == 1024
if (blockDim.x == 1024 && tid < 512)
i_data[tid] += i_data[tid + 512];
__syncthreads();
if (blockDim.x >= 512 && tid < 256)
i_data[tid] += i_data[tid + 256];
__syncthreads();
if (blockDim.x >= 256 && tid < 128)
i_data[tid] += i_data[tid + 128];
__syncthreads();
if (blockDim.x >= 128 && tid < 64)
i_data[tid] += i_data[tid + 64];
__syncthreads();
// warp unrolling
if (tid < 32)
{
volatile int * vsmem = i_data;
vsmem[tid] += vsmem[tid + 32];
vsmem[tid] += vsmem[tid + 16];
vsmem[tid] += vsmem[tid + 8];
vsmem[tid] += vsmem[tid + 4];
vsmem[tid] += vsmem[tid + 2];
vsmem[tid] += vsmem[tid + 1];
}
if (tid == 0)
{
temp[blockIdx.x] = i_data[0];
}
}
|
.file "tmpxft_0010d62e_00000000-6_reduction_kernel_complete_unrolling8_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__Z38reduction_kernel_complete_unrolling8_1PiS_iPiS_i
.type _Z61__device_stub__Z38reduction_kernel_complete_unrolling8_1PiS_iPiS_i, @function
_Z61__device_stub__Z38reduction_kernel_complete_unrolling8_1PiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z38reduction_kernel_complete_unrolling8_1PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z61__device_stub__Z38reduction_kernel_complete_unrolling8_1PiS_iPiS_i, .-_Z61__device_stub__Z38reduction_kernel_complete_unrolling8_1PiS_iPiS_i
.globl _Z38reduction_kernel_complete_unrolling8_1PiS_i
.type _Z38reduction_kernel_complete_unrolling8_1PiS_i, @function
_Z38reduction_kernel_complete_unrolling8_1PiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z61__device_stub__Z38reduction_kernel_complete_unrolling8_1PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z38reduction_kernel_complete_unrolling8_1PiS_i, .-_Z38reduction_kernel_complete_unrolling8_1PiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z38reduction_kernel_complete_unrolling8_1PiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z38reduction_kernel_complete_unrolling8_1PiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void reduction_kernel_complete_unrolling8_1(int * input, int * temp, int size)
{
int tid = threadIdx.x;
int index = blockDim.x * blockIdx.x * 8 + threadIdx.x;
int * i_data = input + blockDim.x * blockIdx.x * 8;
if ((index + 7 * blockDim.x) < size)
{
int a1 = input[index];
int a2 = input[index + blockDim.x];
int a3 = input[index + 2 * blockDim.x];
int a4 = input[index + 3 * blockDim.x];
int a5 = input[index + 4 * blockDim.x];
int a6 = input[index + 5 * blockDim.x];
int a7 = input[index + 6 * blockDim.x];
int a8 = input[index + 7 * blockDim.x];
input[index] = a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8;
}
__syncthreads();
//complete unrolling manually
//if the block dim == 1024
if (blockDim.x == 1024 && tid < 512)
i_data[tid] += i_data[tid + 512];
__syncthreads();
if (blockDim.x >= 512 && tid < 256)
i_data[tid] += i_data[tid + 256];
__syncthreads();
if (blockDim.x >= 256 && tid < 128)
i_data[tid] += i_data[tid + 128];
__syncthreads();
if (blockDim.x >= 128 && tid < 64)
i_data[tid] += i_data[tid + 64];
__syncthreads();
// warp unrolling
if (tid < 32)
{
volatile int * vsmem = i_data;
vsmem[tid] += vsmem[tid + 32];
vsmem[tid] += vsmem[tid + 16];
vsmem[tid] += vsmem[tid + 8];
vsmem[tid] += vsmem[tid + 4];
vsmem[tid] += vsmem[tid + 2];
vsmem[tid] += vsmem[tid + 1];
}
if (tid == 0)
{
temp[blockIdx.x] = i_data[0];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduction_kernel_complete_unrolling8_1(int * input, int * temp, int size)
{
int tid = threadIdx.x;
int index = blockDim.x * blockIdx.x * 8 + threadIdx.x;
int * i_data = input + blockDim.x * blockIdx.x * 8;
if ((index + 7 * blockDim.x) < size)
{
int a1 = input[index];
int a2 = input[index + blockDim.x];
int a3 = input[index + 2 * blockDim.x];
int a4 = input[index + 3 * blockDim.x];
int a5 = input[index + 4 * blockDim.x];
int a6 = input[index + 5 * blockDim.x];
int a7 = input[index + 6 * blockDim.x];
int a8 = input[index + 7 * blockDim.x];
input[index] = a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8;
}
__syncthreads();
//complete unrolling manually
//if the block dim == 1024
if (blockDim.x == 1024 && tid < 512)
i_data[tid] += i_data[tid + 512];
__syncthreads();
if (blockDim.x >= 512 && tid < 256)
i_data[tid] += i_data[tid + 256];
__syncthreads();
if (blockDim.x >= 256 && tid < 128)
i_data[tid] += i_data[tid + 128];
__syncthreads();
if (blockDim.x >= 128 && tid < 64)
i_data[tid] += i_data[tid + 64];
__syncthreads();
// warp unrolling
if (tid < 32)
{
volatile int * vsmem = i_data;
vsmem[tid] += vsmem[tid + 32];
vsmem[tid] += vsmem[tid + 16];
vsmem[tid] += vsmem[tid + 8];
vsmem[tid] += vsmem[tid + 4];
vsmem[tid] += vsmem[tid + 2];
vsmem[tid] += vsmem[tid + 1];
}
if (tid == 0)
{
temp[blockIdx.x] = i_data[0];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduction_kernel_complete_unrolling8_1(int * input, int * temp, int size)
{
int tid = threadIdx.x;
int index = blockDim.x * blockIdx.x * 8 + threadIdx.x;
int * i_data = input + blockDim.x * blockIdx.x * 8;
if ((index + 7 * blockDim.x) < size)
{
int a1 = input[index];
int a2 = input[index + blockDim.x];
int a3 = input[index + 2 * blockDim.x];
int a4 = input[index + 3 * blockDim.x];
int a5 = input[index + 4 * blockDim.x];
int a6 = input[index + 5 * blockDim.x];
int a7 = input[index + 6 * blockDim.x];
int a8 = input[index + 7 * blockDim.x];
input[index] = a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8;
}
__syncthreads();
//complete unrolling manually
//if the block dim == 1024
if (blockDim.x == 1024 && tid < 512)
i_data[tid] += i_data[tid + 512];
__syncthreads();
if (blockDim.x >= 512 && tid < 256)
i_data[tid] += i_data[tid + 256];
__syncthreads();
if (blockDim.x >= 256 && tid < 128)
i_data[tid] += i_data[tid + 128];
__syncthreads();
if (blockDim.x >= 128 && tid < 64)
i_data[tid] += i_data[tid + 64];
__syncthreads();
// warp unrolling
if (tid < 32)
{
volatile int * vsmem = i_data;
vsmem[tid] += vsmem[tid + 32];
vsmem[tid] += vsmem[tid + 16];
vsmem[tid] += vsmem[tid + 8];
vsmem[tid] += vsmem[tid + 4];
vsmem[tid] += vsmem[tid + 2];
vsmem[tid] += vsmem[tid + 1];
}
if (tid == 0)
{
temp[blockIdx.x] = i_data[0];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z38reduction_kernel_complete_unrolling8_1PiS_i
.globl _Z38reduction_kernel_complete_unrolling8_1PiS_i
.p2align 8
.type _Z38reduction_kernel_complete_unrolling8_1PiS_i,@function
_Z38reduction_kernel_complete_unrolling8_1PiS_i:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x24
s_load_b32 s7, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s3
s_lshl_b32 s6, s6, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s6, v0
v_mad_u64_u32 v[1:2], null, s3, 7, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s7, v1
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v4, 31, v3
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_mad_u64_u32 v[11:12], null, s3, 3, v[3:4]
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_lshl_add_u32 v5, s3, 1, v3
v_mov_b32_e32 v12, v6
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[4:5], 2, v[5:6]
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v13, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v5, vcc_lo
v_lshl_add_u32 v5, s3, 2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_clause 0x3
global_load_b32 v19, v[7:8], off
global_load_b32 v20, v[9:10], off
global_load_b32 v13, v[13:14], off
global_load_b32 v14, v[11:12], off
v_mov_b32_e32 v2, v6
v_mad_u64_u32 v[15:16], null, s3, 5, v[3:4]
v_mov_b32_e32 v16, v6
v_mad_u64_u32 v[17:18], null, s3, 6, v[3:4]
v_mov_b32_e32 v18, v6
v_add_co_u32 v3, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[15:16]
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v5, vcc_lo
v_lshlrev_b64 v[11:12], 2, v[17:18]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_clause 0x3
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
global_load_b32 v5, v[9:10], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(6)
v_add_nc_u32_e32 v2, v20, v19
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v2, v2, v13, v14
s_waitcnt vmcnt(2)
v_add3_u32 v2, v2, v3, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v1, v2, v5, v1
global_store_b32 v[7:8], v1, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
s_mov_b32 s7, 0
v_cmp_eq_u16_e64 s9, 0x400, s8
v_cmp_gt_u32_e32 vcc_lo, 0x200, v0
s_lshl_b64 s[6:7], s[6:7], 2
s_waitcnt_vscnt null, 0x0
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_and_b32 s7, vcc_lo, s9
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s6, s7
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5] offset:2048
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v1, v2, s[4:5]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
v_cmp_lt_u16_e64 s6, 0x1ff, s8
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 s7, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s7
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5] offset:1024
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v1, v2, s[4:5]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s6
v_cmp_gt_u32_e32 vcc_lo, 0x80, v0
s_cmpk_gt_u32 s3, 0xff
s_waitcnt_vscnt null, 0x0
s_cselect_b32 s6, -1, 0
s_barrier
s_and_b32 s7, vcc_lo, s6
buffer_gl0_inv
s_and_saveexec_b32 s6, s7
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5] offset:512
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v1, v2, s[4:5]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
v_cmp_gt_u32_e32 vcc_lo, 64, v0
s_cmpk_gt_u32 s3, 0x7f
s_waitcnt_vscnt null, 0x0
s_cselect_b32 s3, -1, 0
s_barrier
s_and_b32 s6, vcc_lo, s3
buffer_gl0_inv
s_and_saveexec_b32 s3, s6
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5] offset:256
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v1, v2, s[4:5]
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_12
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v1, 0x80, v3
v_add_co_u32 v1, s6, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s5, 0, s6
v_add_co_u32 v3, s6, s4, v3
v_add_co_ci_u32_e64 v4, null, s5, 0, s6
flat_load_b32 v1, v[1:2] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
flat_store_b32 v[3:4], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[3:4] offset:64 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
flat_store_b32 v[3:4], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[3:4] offset:32 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
flat_store_b32 v[3:4], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[3:4] offset:16 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
flat_store_b32 v[3:4], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[3:4] offset:8 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
flat_store_b32 v[3:4], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[3:4] offset:4 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
flat_store_b32 v[3:4], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_14
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
global_load_b32 v1, v0, s[4:5]
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_14:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z38reduction_kernel_complete_unrolling8_1PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z38reduction_kernel_complete_unrolling8_1PiS_i, .Lfunc_end0-_Z38reduction_kernel_complete_unrolling8_1PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z38reduction_kernel_complete_unrolling8_1PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z38reduction_kernel_complete_unrolling8_1PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduction_kernel_complete_unrolling8_1(int * input, int * temp, int size)
{
int tid = threadIdx.x;
int index = blockDim.x * blockIdx.x * 8 + threadIdx.x;
int * i_data = input + blockDim.x * blockIdx.x * 8;
if ((index + 7 * blockDim.x) < size)
{
int a1 = input[index];
int a2 = input[index + blockDim.x];
int a3 = input[index + 2 * blockDim.x];
int a4 = input[index + 3 * blockDim.x];
int a5 = input[index + 4 * blockDim.x];
int a6 = input[index + 5 * blockDim.x];
int a7 = input[index + 6 * blockDim.x];
int a8 = input[index + 7 * blockDim.x];
input[index] = a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8;
}
__syncthreads();
//complete unrolling manually
//if the block dim == 1024
if (blockDim.x == 1024 && tid < 512)
i_data[tid] += i_data[tid + 512];
__syncthreads();
if (blockDim.x >= 512 && tid < 256)
i_data[tid] += i_data[tid + 256];
__syncthreads();
if (blockDim.x >= 256 && tid < 128)
i_data[tid] += i_data[tid + 128];
__syncthreads();
if (blockDim.x >= 128 && tid < 64)
i_data[tid] += i_data[tid + 64];
__syncthreads();
// warp unrolling
if (tid < 32)
{
volatile int * vsmem = i_data;
vsmem[tid] += vsmem[tid + 32];
vsmem[tid] += vsmem[tid + 16];
vsmem[tid] += vsmem[tid + 8];
vsmem[tid] += vsmem[tid + 4];
vsmem[tid] += vsmem[tid + 2];
vsmem[tid] += vsmem[tid + 1];
}
if (tid == 0)
{
temp[blockIdx.x] = i_data[0];
}
}
|
.text
.file "reduction_kernel_complete_unrolling8_1.hip"
.globl _Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i # -- Begin function _Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i
.p2align 4, 0x90
.type _Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i,@function
_Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i: # @_Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z38reduction_kernel_complete_unrolling8_1PiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i, .Lfunc_end0-_Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z38reduction_kernel_complete_unrolling8_1PiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z38reduction_kernel_complete_unrolling8_1PiS_i,@object # @_Z38reduction_kernel_complete_unrolling8_1PiS_i
.section .rodata,"a",@progbits
.globl _Z38reduction_kernel_complete_unrolling8_1PiS_i
.p2align 3, 0x0
_Z38reduction_kernel_complete_unrolling8_1PiS_i:
.quad _Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i
.size _Z38reduction_kernel_complete_unrolling8_1PiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z38reduction_kernel_complete_unrolling8_1PiS_i"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z38reduction_kernel_complete_unrolling8_1PiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z38reduction_kernel_complete_unrolling8_1PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0060*/ BSSY B0, 0x350 ; /* 0x000002e000007945 */
/* 0x000fe20003800000 */
/*0070*/ IMAD R2, R0, c[0x0][0x0], RZ ; /* 0x0000000000027a24 */
/* 0x001fc800078e02ff */
/*0080*/ IMAD.SHL.U32 R2, R2, 0x8, RZ ; /* 0x0000000802027824 */
/* 0x000fe200078e00ff */
/*0090*/ ISETP.GT.AND P0, PT, R9.reuse, 0x1ff, PT ; /* 0x000001ff0900780c */
/* 0x042fe40003f04270 */
/*00a0*/ ISETP.GT.AND P1, PT, R9.reuse, 0xff, PT ; /* 0x000000ff0900780c */
/* 0x040fe20003f24270 */
/*00b0*/ IMAD.IADD R4, R2, 0x1, R9 ; /* 0x0000000102047824 */
/* 0x000fe200078e0209 */
/*00c0*/ ISETP.GT.AND P2, PT, R9.reuse, 0x7f, PT ; /* 0x0000007f0900780c */
/* 0x040fe40003f44270 */
/*00d0*/ ISETP.GT.AND P3, PT, R9, 0x3f, PT ; /* 0x0000003f0900780c */
/* 0x000fe20003f64270 */
/*00e0*/ IMAD R6, R3.reuse, 0x7, R4 ; /* 0x0000000703067824 */
/* 0x040fe200078e0204 */
/*00f0*/ ISETP.NE.OR P0, PT, R3.reuse, 0x400, P0 ; /* 0x000004000300780c */
/* 0x040fe40000705670 */
/*0100*/ ISETP.LT.U32.OR P1, PT, R3, 0x200, P1 ; /* 0x000002000300780c */
/* 0x000fc40000f21470 */
/*0110*/ ISETP.GE.U32.AND P4, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f86070 */
/*0120*/ ISETP.LT.U32.OR P2, PT, R3.reuse, 0x100, P2 ; /* 0x000001000300780c */
/* 0x040fe40001741470 */
/*0130*/ ISETP.LT.U32.OR P3, PT, R3, 0x80, P3 ; /* 0x000000800300780c */
/* 0x000fe20001f61470 */
/*0140*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0007 */
/*0150*/ ISETP.GT.AND P5, PT, R9.reuse, 0x1f, PT ; /* 0x0000001f0900780c */
/* 0x040fe40003fa4270 */
/*0160*/ ISETP.NE.AND P6, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fca0003fc5270 */
/*0170*/ @P4 BRA 0x340 ; /* 0x000001c000004947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R22, R4, c[0x0][0x0], RZ ; /* 0x0000000004167a10 */
/* 0x000fe20007ffe0ff */
/*0190*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fc600000001ff */
/*01a0*/ IADD3 R20, R22, c[0x0][0x0], RZ ; /* 0x0000000016147a10 */
/* 0x000fc80007ffe0ff */
/*01b0*/ IADD3 R12, R20, c[0x0][0x0], RZ ; /* 0x00000000140c7a10 */
/* 0x000fc60007ffe0ff */
/*01c0*/ IMAD.WIDE.U32 R20, R20, R11, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fe200078e000b */
/*01d0*/ IADD3 R14, R12, c[0x0][0x0], RZ ; /* 0x000000000c0e7a10 */
/* 0x000fc60007ffe0ff */
/*01e0*/ IMAD.WIDE.U32 R22, R22, R11.reuse, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x080fe200078e000b */
/*01f0*/ IADD3 R16, R14, c[0x0][0x0], RZ ; /* 0x000000000e107a10 */
/* 0x000fe20007ffe0ff */
/*0200*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000ea4000c1e1900 */
/*0210*/ IMAD.WIDE R4, R4, R11.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe200078e020b */
/*0220*/ IADD3 R18, R16, c[0x0][0x0], RZ ; /* 0x0000000010127a10 */
/* 0x000fe20007ffe0ff */
/*0230*/ LDG.E R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD.WIDE.U32 R12, R12, R11.reuse, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x080fe400078e000b */
/*0250*/ LDG.E R24, [R4.64] ; /* 0x0000000404187981 */
/* 0x000ea4000c1e1900 */
/*0260*/ IMAD.WIDE.U32 R14, R14, R11, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc400078e000b */
/*0270*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ee4000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R16, R16, R11.reuse, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x080fe400078e000b */
/*0290*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee4000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R18, R18, R11.reuse, c[0x0][0x160] ; /* 0x0000580012127625 */
/* 0x080fe400078e000b */
/*02b0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000f24000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R10, R6, R11, c[0x0][0x160] ; /* 0x00005800060a7625 */
/* 0x000fc400078e000b */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000f62000c1e1900 */
/*02f0*/ IADD3 R8, R21, R8, R24 ; /* 0x0000000815087210 */
/* 0x004fc80007ffe018 */
/*0300*/ IADD3 R8, R14, R8, R13 ; /* 0x000000080e087210 */
/* 0x008fc80007ffe00d */
/*0310*/ IADD3 R8, R18, R8, R17 ; /* 0x0000000812087210 */
/* 0x010fca0007ffe011 */
/*0320*/ IMAD.IADD R21, R8, 0x1, R11 ; /* 0x0000000108157824 */
/* 0x020fca00078e020b */
/*0330*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0001e4000c101904 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0360*/ IMAD.WIDE R4, R9, 0x4, R2 ; /* 0x0000000409047825 */
/* 0x001fca00078e0202 */
/*0370*/ BSSY B0, 0x3e0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0380*/ @P0 BRA 0x3d0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R9, [R4.64+0x800] ; /* 0x0008000404097981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x004fca00078e0209 */
/*03c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03f0*/ BSSY B0, 0x460 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0400*/ @P1 BRA 0x450 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0410*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0420*/ LDG.E R9, [R4.64+0x400] ; /* 0x0004000404097981 */
/* 0x001ea4000c1e1900 */
/*0430*/ IADD3 R9, R6, R9, RZ ; /* 0x0000000906097210 */
/* 0x004fca0007ffe0ff */
/*0440*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ BSSY B0, 0x4e0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0480*/ @P2 BRA 0x4d0 ; /* 0x0000004000002947 */
/* 0x000fea0003800000 */
/*0490*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R9, [R4.64+0x200] ; /* 0x0002000404097981 */
/* 0x001ea4000c1e1900 */
/*04b0*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x004fca00078e0209 */
/*04c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04f0*/ BSSY B0, 0x560 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0500*/ @P3 BRA 0x550 ; /* 0x0000004000003947 */
/* 0x000fea0003800000 */
/*0510*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0520*/ LDG.E R9, [R4.64+0x100] ; /* 0x0001000404097981 */
/* 0x001ea4000c1e1900 */
/*0530*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x004fca00078e0209 */
/*0540*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0550*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0560*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0570*/ BSSY B0, 0x720 ; /* 0x000001a000007945 */
/* 0x000fe20003800000 */
/*0580*/ @P5 BRA 0x710 ; /* 0x0000018000005947 */
/* 0x000fea0003800000 */
/*0590*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1f5900 */
/*05a0*/ LDG.E.STRONG.SYS R9, [R4.64+0x80] ; /* 0x0000800404097981 */
/* 0x001ea4000c1f5900 */
/*05b0*/ IADD3 R9, R6, R9, RZ ; /* 0x0000000906097210 */
/* 0x004fca0007ffe0ff */
/*05c0*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c115904 */
/*05d0*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1f5900 */
/*05e0*/ LDG.E.STRONG.SYS R11, [R4.64+0x40] ; /* 0x00004004040b7981 */
/* 0x000ea4000c1f5900 */
/*05f0*/ IMAD.IADD R11, R6, 0x1, R11 ; /* 0x00000001060b7824 */
/* 0x004fca00078e020b */
/*0600*/ STG.E.STRONG.SYS [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0003e8000c115904 */
/*0610*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1f5900 */
/*0620*/ LDG.E.STRONG.SYS R13, [R4.64+0x20] ; /* 0x00002004040d7981 */
/* 0x000ea4000c1f5900 */
/*0630*/ IMAD.IADD R13, R6, 0x1, R13 ; /* 0x00000001060d7824 */
/* 0x004fca00078e020d */
/*0640*/ STG.E.STRONG.SYS [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0005e8000c115904 */
/*0650*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee8000c1f5900 */
/*0660*/ LDG.E.STRONG.SYS R15, [R4.64+0x10] ; /* 0x00001004040f7981 */
/* 0x000ee4000c1f5900 */
/*0670*/ IADD3 R15, R6, R15, RZ ; /* 0x0000000f060f7210 */
/* 0x008fca0007ffe0ff */
/*0680*/ STG.E.STRONG.SYS [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0005e8000c115904 */
/*0690*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee8000c1f5900 */
/*06a0*/ LDG.E.STRONG.SYS R9, [R4.64+0x8] ; /* 0x0000080404097981 */
/* 0x001ee4000c1f5900 */
/*06b0*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x008fca00078e0209 */
/*06c0*/ STG.E.STRONG.SYS [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0005e8000c115904 */
/*06d0*/ LDG.E.STRONG.SYS R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee8000c1f5900 */
/*06e0*/ LDG.E.STRONG.SYS R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x002ee4000c1f5900 */
/*06f0*/ IADD3 R11, R6, R11, RZ ; /* 0x0000000b060b7210 */
/* 0x008fca0007ffe0ff */
/*0700*/ STG.E.STRONG.SYS [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0005e4000c115904 */
/*0710*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0720*/ @P6 EXIT ; /* 0x000000000000694d */
/* 0x000fea0003800000 */
/*0730*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x005fca00078e0007 */
/*0750*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x008fe2000c101904 */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z38reduction_kernel_complete_unrolling8_1PiS_i
.globl _Z38reduction_kernel_complete_unrolling8_1PiS_i
.p2align 8
.type _Z38reduction_kernel_complete_unrolling8_1PiS_i,@function
_Z38reduction_kernel_complete_unrolling8_1PiS_i:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x24
s_load_b32 s7, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s3
s_lshl_b32 s6, s6, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s6, v0
v_mad_u64_u32 v[1:2], null, s3, 7, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s7, v1
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v4, 31, v3
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_mad_u64_u32 v[11:12], null, s3, 3, v[3:4]
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_lshl_add_u32 v5, s3, 1, v3
v_mov_b32_e32 v12, v6
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[4:5], 2, v[5:6]
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v13, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v5, vcc_lo
v_lshl_add_u32 v5, s3, 2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_clause 0x3
global_load_b32 v19, v[7:8], off
global_load_b32 v20, v[9:10], off
global_load_b32 v13, v[13:14], off
global_load_b32 v14, v[11:12], off
v_mov_b32_e32 v2, v6
v_mad_u64_u32 v[15:16], null, s3, 5, v[3:4]
v_mov_b32_e32 v16, v6
v_mad_u64_u32 v[17:18], null, s3, 6, v[3:4]
v_mov_b32_e32 v18, v6
v_add_co_u32 v3, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[15:16]
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v5, vcc_lo
v_lshlrev_b64 v[11:12], 2, v[17:18]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_clause 0x3
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
global_load_b32 v5, v[9:10], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(6)
v_add_nc_u32_e32 v2, v20, v19
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v2, v2, v13, v14
s_waitcnt vmcnt(2)
v_add3_u32 v2, v2, v3, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v1, v2, v5, v1
global_store_b32 v[7:8], v1, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
s_mov_b32 s7, 0
v_cmp_eq_u16_e64 s9, 0x400, s8
v_cmp_gt_u32_e32 vcc_lo, 0x200, v0
s_lshl_b64 s[6:7], s[6:7], 2
s_waitcnt_vscnt null, 0x0
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_and_b32 s7, vcc_lo, s9
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s6, s7
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5] offset:2048
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v1, v2, s[4:5]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
v_cmp_lt_u16_e64 s6, 0x1ff, s8
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 s7, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s7
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5] offset:1024
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v1, v2, s[4:5]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s6
v_cmp_gt_u32_e32 vcc_lo, 0x80, v0
s_cmpk_gt_u32 s3, 0xff
s_waitcnt_vscnt null, 0x0
s_cselect_b32 s6, -1, 0
s_barrier
s_and_b32 s7, vcc_lo, s6
buffer_gl0_inv
s_and_saveexec_b32 s6, s7
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5] offset:512
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v1, v2, s[4:5]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
v_cmp_gt_u32_e32 vcc_lo, 64, v0
s_cmpk_gt_u32 s3, 0x7f
s_waitcnt_vscnt null, 0x0
s_cselect_b32 s3, -1, 0
s_barrier
s_and_b32 s6, vcc_lo, s3
buffer_gl0_inv
s_and_saveexec_b32 s3, s6
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[4:5] offset:256
global_load_b32 v3, v1, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v1, v2, s[4:5]
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_12
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v1, 0x80, v3
v_add_co_u32 v1, s6, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s5, 0, s6
v_add_co_u32 v3, s6, s4, v3
v_add_co_ci_u32_e64 v4, null, s5, 0, s6
flat_load_b32 v1, v[1:2] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
flat_store_b32 v[3:4], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[3:4] offset:64 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
flat_store_b32 v[3:4], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[3:4] offset:32 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
flat_store_b32 v[3:4], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[3:4] offset:16 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
flat_store_b32 v[3:4], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[3:4] offset:8 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
flat_store_b32 v[3:4], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[3:4] offset:4 glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
flat_store_b32 v[3:4], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_14
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
global_load_b32 v1, v0, s[4:5]
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_14:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z38reduction_kernel_complete_unrolling8_1PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z38reduction_kernel_complete_unrolling8_1PiS_i, .Lfunc_end0-_Z38reduction_kernel_complete_unrolling8_1PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z38reduction_kernel_complete_unrolling8_1PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z38reduction_kernel_complete_unrolling8_1PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0010d62e_00000000-6_reduction_kernel_complete_unrolling8_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__Z38reduction_kernel_complete_unrolling8_1PiS_iPiS_i
.type _Z61__device_stub__Z38reduction_kernel_complete_unrolling8_1PiS_iPiS_i, @function
_Z61__device_stub__Z38reduction_kernel_complete_unrolling8_1PiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z38reduction_kernel_complete_unrolling8_1PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z61__device_stub__Z38reduction_kernel_complete_unrolling8_1PiS_iPiS_i, .-_Z61__device_stub__Z38reduction_kernel_complete_unrolling8_1PiS_iPiS_i
.globl _Z38reduction_kernel_complete_unrolling8_1PiS_i
.type _Z38reduction_kernel_complete_unrolling8_1PiS_i, @function
_Z38reduction_kernel_complete_unrolling8_1PiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z61__device_stub__Z38reduction_kernel_complete_unrolling8_1PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z38reduction_kernel_complete_unrolling8_1PiS_i, .-_Z38reduction_kernel_complete_unrolling8_1PiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z38reduction_kernel_complete_unrolling8_1PiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z38reduction_kernel_complete_unrolling8_1PiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "reduction_kernel_complete_unrolling8_1.hip"
.globl _Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i # -- Begin function _Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i
.p2align 4, 0x90
.type _Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i,@function
_Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i: # @_Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z38reduction_kernel_complete_unrolling8_1PiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i, .Lfunc_end0-_Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z38reduction_kernel_complete_unrolling8_1PiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z38reduction_kernel_complete_unrolling8_1PiS_i,@object # @_Z38reduction_kernel_complete_unrolling8_1PiS_i
.section .rodata,"a",@progbits
.globl _Z38reduction_kernel_complete_unrolling8_1PiS_i
.p2align 3, 0x0
_Z38reduction_kernel_complete_unrolling8_1PiS_i:
.quad _Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i
.size _Z38reduction_kernel_complete_unrolling8_1PiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z38reduction_kernel_complete_unrolling8_1PiS_i"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z53__device_stub__reduction_kernel_complete_unrolling8_1PiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z38reduction_kernel_complete_unrolling8_1PiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void average_snips(const double *Params, const int *ioff, const int *id, const float *uproj, const float *cmax, const int *iList, float *cf, float *WU){
int tid, bid, ind, Nspikes, Nfeatures, NfeatW, Nnearest, t;
float xsum = 0.0f, pm;
Nspikes = (int) Params[0];
Nfeatures = (int) Params[1];
pm = (float) Params[3];
NfeatW = (int) Params[4];
Nnearest = (int) Params[6];
tid = threadIdx.x;
bid = blockIdx.x;
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==bid){
xsum = uproj[tid + Nfeatures * ind];
WU[tid + ioff[ind] + NfeatW * bid] = pm * WU[tid + ioff[ind] + NfeatW * bid]
+ (1-pm) * xsum;
// go through the top 10 nearest filters and match them
for (t=0;t<Nnearest;t++)
cf[ind + t*Nspikes] = cmax[ind + Nspikes * iList[t + Nnearest*bid]];
}
}
|
.file "tmpxft_001617c3_00000000-6_average_snips.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_PKdPKiS2_PKfS4_S2_PfS5_
.type _Z54__device_stub__Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_PKdPKiS2_PKfS4_S2_PfS5_, @function
_Z54__device_stub__Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_PKdPKiS2_PKfS4_S2_PfS5_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq 232(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_PKdPKiS2_PKfS4_S2_PfS5_, .-_Z54__device_stub__Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_PKdPKiS2_PKfS4_S2_PfS5_
.globl _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.type _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_, @function
_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_PKdPKiS2_PKfS4_S2_PfS5_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_, .-_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void average_snips(const double *Params, const int *ioff, const int *id, const float *uproj, const float *cmax, const int *iList, float *cf, float *WU){
int tid, bid, ind, Nspikes, Nfeatures, NfeatW, Nnearest, t;
float xsum = 0.0f, pm;
Nspikes = (int) Params[0];
Nfeatures = (int) Params[1];
pm = (float) Params[3];
NfeatW = (int) Params[4];
Nnearest = (int) Params[6];
tid = threadIdx.x;
bid = blockIdx.x;
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==bid){
xsum = uproj[tid + Nfeatures * ind];
WU[tid + ioff[ind] + NfeatW * bid] = pm * WU[tid + ioff[ind] + NfeatW * bid]
+ (1-pm) * xsum;
// go through the top 10 nearest filters and match them
for (t=0;t<Nnearest;t++)
cf[ind + t*Nspikes] = cmax[ind + Nspikes * iList[t + Nnearest*bid]];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void average_snips(const double *Params, const int *ioff, const int *id, const float *uproj, const float *cmax, const int *iList, float *cf, float *WU){
int tid, bid, ind, Nspikes, Nfeatures, NfeatW, Nnearest, t;
float xsum = 0.0f, pm;
Nspikes = (int) Params[0];
Nfeatures = (int) Params[1];
pm = (float) Params[3];
NfeatW = (int) Params[4];
Nnearest = (int) Params[6];
tid = threadIdx.x;
bid = blockIdx.x;
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==bid){
xsum = uproj[tid + Nfeatures * ind];
WU[tid + ioff[ind] + NfeatW * bid] = pm * WU[tid + ioff[ind] + NfeatW * bid]
+ (1-pm) * xsum;
// go through the top 10 nearest filters and match them
for (t=0;t<Nnearest;t++)
cf[ind + t*Nspikes] = cmax[ind + Nspikes * iList[t + Nnearest*bid]];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void average_snips(const double *Params, const int *ioff, const int *id, const float *uproj, const float *cmax, const int *iList, float *cf, float *WU){
int tid, bid, ind, Nspikes, Nfeatures, NfeatW, Nnearest, t;
float xsum = 0.0f, pm;
Nspikes = (int) Params[0];
Nfeatures = (int) Params[1];
pm = (float) Params[3];
NfeatW = (int) Params[4];
Nnearest = (int) Params[6];
tid = threadIdx.x;
bid = blockIdx.x;
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==bid){
xsum = uproj[tid + Nfeatures * ind];
WU[tid + ioff[ind] + NfeatW * bid] = pm * WU[tid + ioff[ind] + NfeatW * bid]
+ (1-pm) * xsum;
// go through the top 10 nearest filters and match them
for (t=0;t<Nnearest;t++)
cf[ind + t*Nspikes] = cmax[ind + Nspikes * iList[t + Nnearest*bid]];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.globl _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.p2align 8
.type _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_,@function
_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_:
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v1, s[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 1, v1
v_readfirstlane_b32 s14, v1
s_cbranch_vccnz .LBB0_6
s_clause 0x2
s_load_b64 s[8:9], s[2:3], 0x30
s_load_b128 s[4:7], s[2:3], 0x18
s_load_b64 s[2:3], s[2:3], 0x8
v_mov_b32_e32 v6, 0
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v3, s[8:9]
v_cvt_i32_f64_e32 v7, s[6:7]
v_cvt_f32_f64_e32 v4, s[4:5]
v_cvt_i32_f64_e32 v5, s[2:3]
s_clause 0x2
s_load_b128 s[16:19], s[0:1], 0x28
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x38
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_cmp_lt_i32_e32 vcc_lo, 0, v3
v_readfirstlane_b32 s0, v3
v_mad_u64_u32 v[1:2], null, s15, v7, v[0:1]
v_sub_f32_e32 v2, 1.0, v4
v_cndmask_b32_e64 v8, 0, 1, vcc_lo
s_mul_i32 s0, s15, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 31
s_lshl_b64 s[20:21], s[0:1], 2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 1, v8
s_waitcnt lgkmcnt(0)
s_add_u32 s16, s16, s20
s_addc_u32 s17, s17, s21
s_mov_b32 s20, s13
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s20, s20, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s20, s14
s_cbranch_scc0 .LBB0_6
.LBB0_3:
s_mov_b32 s21, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[22:23], s[20:21], 2
s_add_u32 s24, s6, s22
s_addc_u32 s25, s7, s23
s_load_b32 s1, s[24:25], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s1, s15
s_cbranch_scc1 .LBB0_2
s_add_u32 s22, s4, s22
s_addc_u32 s23, s5, s23
v_mad_u64_u32 v[9:10], null, s20, v5, v[0:1]
s_load_b32 s1, s[22:23], 0x0
s_mov_b64 s[22:23], s[16:17]
s_mov_b32 s12, s20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v7, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v10, vcc_lo
global_load_b32 v9, v[11:12], off
global_load_b32 v7, v[7:8], off
s_and_b32 vcc_lo, exec_lo, s0
s_waitcnt vmcnt(1)
v_mul_f32_e32 v8, v9, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmac_f32 v8, v2, v7 :: v_dual_mov_b32 v7, v3
global_store_b32 v[11:12], v8, off
s_cbranch_vccnz .LBB0_2
.p2align 6
.LBB0_5:
s_load_b32 s1, s[22:23], 0x0
v_add_nc_u32_e32 v7, -1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v7
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s1, s14
s_add_i32 s24, s1, s20
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s25, s24, 31
s_lshl_b64 s[24:25], s[24:25], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_add_u32 s24, s10, s24
s_addc_u32 s25, s11, s25
global_load_b32 v8, v6, s[24:25]
s_lshl_b64 s[24:25], s[12:13], 2
s_add_u32 s24, s18, s24
s_addc_u32 s25, s19, s25
s_add_i32 s12, s12, s14
s_add_u32 s22, s22, 4
s_addc_u32 s23, s23, 0
s_waitcnt vmcnt(0)
global_store_b32 v6, v8, s[24:25]
s_cbranch_vccnz .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 64
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_, .Lfunc_end0-_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 64
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void average_snips(const double *Params, const int *ioff, const int *id, const float *uproj, const float *cmax, const int *iList, float *cf, float *WU){
int tid, bid, ind, Nspikes, Nfeatures, NfeatW, Nnearest, t;
float xsum = 0.0f, pm;
Nspikes = (int) Params[0];
Nfeatures = (int) Params[1];
pm = (float) Params[3];
NfeatW = (int) Params[4];
Nnearest = (int) Params[6];
tid = threadIdx.x;
bid = blockIdx.x;
for(ind=0; ind<Nspikes;ind++)
if (id[ind]==bid){
xsum = uproj[tid + Nfeatures * ind];
WU[tid + ioff[ind] + NfeatW * bid] = pm * WU[tid + ioff[ind] + NfeatW * bid]
+ (1-pm) * xsum;
// go through the top 10 nearest filters and match them
for (t=0;t<Nnearest;t++)
cf[ind + t*Nspikes] = cmax[ind + Nspikes * iList[t + Nnearest*bid]];
}
}
|
.text
.file "average_snips.hip"
.globl _Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_ # -- Begin function _Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.p2align 4, 0x90
.type _Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_,@function
_Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_: # @_Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_, .Lfunc_end0-_Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_,@object # @_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.section .rodata,"a",@progbits
.globl _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.p2align 3, 0x0
_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_:
.quad _Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.size _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001617c3_00000000-6_average_snips.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_PKdPKiS2_PKfS4_S2_PfS5_
.type _Z54__device_stub__Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_PKdPKiS2_PKfS4_S2_PfS5_, @function
_Z54__device_stub__Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_PKdPKiS2_PKfS4_S2_PfS5_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq 232(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_PKdPKiS2_PKfS4_S2_PfS5_, .-_Z54__device_stub__Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_PKdPKiS2_PKfS4_S2_PfS5_
.globl _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.type _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_, @function
_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_PKdPKiS2_PKfS4_S2_PfS5_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_, .-_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "average_snips.hip"
.globl _Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_ # -- Begin function _Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.p2align 4, 0x90
.type _Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_,@function
_Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_: # @_Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_, .Lfunc_end0-_Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_,@object # @_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.section .rodata,"a",@progbits
.globl _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.p2align 3, 0x0
_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_:
.quad _Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.size _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13average_snipsPKdPKiS2_PKfS4_S2_PfS5_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#define SIZE 64
#define BLOCKS 4
__global__ void device_global(unsigned int *array_a, int num_elements) {
int my_index = blockIdx.x * blockDim.x + threadIdx.x;
array_a[my_index] = my_index % (num_elements/2); // write overlaping indicies
__syncthreads();
int next_index = array_a[my_index]; // use written index
array_a[next_index] = my_index; // cause a write write race
}
int main(void) {
// malloc arrays
unsigned int *host_array = (unsigned int*) malloc(SIZE*sizeof(unsigned int));
unsigned int *device_array_a = 0;
cudaMalloc((void **) &device_array_a, SIZE*sizeof(unsigned int));
// check mallocs
if (host_array == 0) { return 1;}
if (device_array_a == 0) { return 2;}
// init host array to 0
for (int i=0; i<SIZE; i++) {
host_array[i] = 0;
}
// copy to device, call global, and copy output back
cudaMemcpy(device_array_a, host_array, SIZE, cudaMemcpyHostToDevice);
device_global<<<BLOCKS,(SIZE/BLOCKS)>>> (device_array_a, SIZE);
cudaMemcpy(host_array, device_array_a, SIZE, cudaMemcpyDeviceToHost);
// print output
for (int i=0; i<SIZE; i += SIZE/BLOCKS) {
for (int j=0; j<SIZE/BLOCKS; j++){
printf("%d, ", host_array[i+j]);
}
printf("\n");
}
// cleanup
free(host_array);
cudaFree(device_array_a);
}
|
code for sm_80
Function : _Z13device_globalPji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ LEA.HI R0, R0, c[0x0][0x168], RZ, 0x1 ; /* 0x00005a0000007a11 */
/* 0x000fe200078f08ff */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e260000002100 */
/*0060*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc80000011400 */
/*0070*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc80000000000 */
/*0080*/ I2F.RP R4, R8 ; /* 0x0000000800047306 */
/* 0x000e620000209400 */
/*0090*/ IMAD R7, R7, c[0x0][0x0], R6 ; /* 0x0000000007077a24 */
/* 0x001fe200078e0206 */
/*00a0*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fcc0000000000 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e220000001000 */
/*00c0*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f46270 */
/*00d0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fe40007ffe0ff */
/*00e0*/ IABS R4, R7 ; /* 0x0000000700047213 */
/* 0x000fc60000000000 */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0110*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*0120*/ IMAD R5, R5, R8, RZ ; /* 0x0000000805057224 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*0140*/ IMAD.MOV R2, RZ, RZ, -R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0a06 */
/*0150*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD R3, R3, R2, R4 ; /* 0x0000000203037224 */
/* 0x000fe400078e0204 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0180*/ ISETP.GT.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f04070 */
/*0190*/ @!P0 IADD3 R3, R3, -R8, RZ ; /* 0x8000000803038210 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*01b0*/ ISETP.GT.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f24070 */
/*01c0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x0000000103039824 */
/* 0x000fca00078e0a08 */
/*01d0*/ MOV R9, R3 ; /* 0x0000000300097202 */
/* 0x000fe20000000f00 */
/*01e0*/ IMAD.WIDE R2, R7, R5, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fc600078e0205 */
/*01f0*/ @!P2 IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff0909a210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P0 LOP3.LUT R9, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff098212 */
/* 0x000fca00078e33ff */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x004fca00078e0205 */
/*0250*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#define SIZE 64
#define BLOCKS 4
__global__ void device_global(unsigned int *array_a, int num_elements) {
int my_index = blockIdx.x * blockDim.x + threadIdx.x;
array_a[my_index] = my_index % (num_elements/2); // write overlaping indicies
__syncthreads();
int next_index = array_a[my_index]; // use written index
array_a[next_index] = my_index; // cause a write write race
}
int main(void) {
// malloc arrays
unsigned int *host_array = (unsigned int*) malloc(SIZE*sizeof(unsigned int));
unsigned int *device_array_a = 0;
cudaMalloc((void **) &device_array_a, SIZE*sizeof(unsigned int));
// check mallocs
if (host_array == 0) { return 1;}
if (device_array_a == 0) { return 2;}
// init host array to 0
for (int i=0; i<SIZE; i++) {
host_array[i] = 0;
}
// copy to device, call global, and copy output back
cudaMemcpy(device_array_a, host_array, SIZE, cudaMemcpyHostToDevice);
device_global<<<BLOCKS,(SIZE/BLOCKS)>>> (device_array_a, SIZE);
cudaMemcpy(host_array, device_array_a, SIZE, cudaMemcpyDeviceToHost);
// print output
for (int i=0; i<SIZE; i += SIZE/BLOCKS) {
for (int j=0; j<SIZE/BLOCKS; j++){
printf("%d, ", host_array[i+j]);
}
printf("\n");
}
// cleanup
free(host_array);
cudaFree(device_array_a);
}
|
.file "tmpxft_0004d208_00000000-6_race_00.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z13device_globalPjiPji
.type _Z34__device_stub__Z13device_globalPjiPji, @function
_Z34__device_stub__Z13device_globalPjiPji:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13device_globalPji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z13device_globalPjiPji, .-_Z34__device_stub__Z13device_globalPjiPji
.globl _Z13device_globalPji
.type _Z13device_globalPji, @function
_Z13device_globalPji:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13device_globalPjiPji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13device_globalPji, .-_Z13device_globalPji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d, "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $256, %edi
call malloc@PLT
movq %rax, %r13
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
testq %r13, %r13
je .L19
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L20
leaq 256(%r13), %rdx
movq %r13, %rax
.L13:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
movl $1, %ecx
movl $64, %edx
movq %r13, %rsi
call cudaMemcpy@PLT
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L14:
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 64(%r13), %rbp
movl $0, %r14d
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r15
.L15:
leaq -64(%rbp), %rbx
.L16:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L16
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $16, %r14d
addq $64, %rbp
cmpl $64, %r14d
jne .L15
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L25
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $64, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z13device_globalPjiPji
jmp .L14
.L19:
movl $1, %eax
jmp .L11
.L20:
movl $2, %eax
jmp .L11
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13device_globalPji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13device_globalPji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#define SIZE 64
#define BLOCKS 4
__global__ void device_global(unsigned int *array_a, int num_elements) {
int my_index = blockIdx.x * blockDim.x + threadIdx.x;
array_a[my_index] = my_index % (num_elements/2); // write overlaping indicies
__syncthreads();
int next_index = array_a[my_index]; // use written index
array_a[next_index] = my_index; // cause a write write race
}
int main(void) {
// malloc arrays
unsigned int *host_array = (unsigned int*) malloc(SIZE*sizeof(unsigned int));
unsigned int *device_array_a = 0;
cudaMalloc((void **) &device_array_a, SIZE*sizeof(unsigned int));
// check mallocs
if (host_array == 0) { return 1;}
if (device_array_a == 0) { return 2;}
// init host array to 0
for (int i=0; i<SIZE; i++) {
host_array[i] = 0;
}
// copy to device, call global, and copy output back
cudaMemcpy(device_array_a, host_array, SIZE, cudaMemcpyHostToDevice);
device_global<<<BLOCKS,(SIZE/BLOCKS)>>> (device_array_a, SIZE);
cudaMemcpy(host_array, device_array_a, SIZE, cudaMemcpyDeviceToHost);
// print output
for (int i=0; i<SIZE; i += SIZE/BLOCKS) {
for (int j=0; j<SIZE/BLOCKS; j++){
printf("%d, ", host_array[i+j]);
}
printf("\n");
}
// cleanup
free(host_array);
cudaFree(device_array_a);
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 64
#define BLOCKS 4
__global__ void device_global(unsigned int *array_a, int num_elements) {
int my_index = blockIdx.x * blockDim.x + threadIdx.x;
array_a[my_index] = my_index % (num_elements/2); // write overlaping indicies
__syncthreads();
int next_index = array_a[my_index]; // use written index
array_a[next_index] = my_index; // cause a write write race
}
int main(void) {
// malloc arrays
unsigned int *host_array = (unsigned int*) malloc(SIZE*sizeof(unsigned int));
unsigned int *device_array_a = 0;
hipMalloc((void **) &device_array_a, SIZE*sizeof(unsigned int));
// check mallocs
if (host_array == 0) { return 1;}
if (device_array_a == 0) { return 2;}
// init host array to 0
for (int i=0; i<SIZE; i++) {
host_array[i] = 0;
}
// copy to device, call global, and copy output back
hipMemcpy(device_array_a, host_array, SIZE, hipMemcpyHostToDevice);
device_global<<<BLOCKS,(SIZE/BLOCKS)>>> (device_array_a, SIZE);
hipMemcpy(host_array, device_array_a, SIZE, hipMemcpyDeviceToHost);
// print output
for (int i=0; i<SIZE; i += SIZE/BLOCKS) {
for (int j=0; j<SIZE/BLOCKS; j++){
printf("%d, ", host_array[i+j]);
}
printf("\n");
}
// cleanup
free(host_array);
hipFree(device_array_a);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 64
#define BLOCKS 4
__global__ void device_global(unsigned int *array_a, int num_elements) {
int my_index = blockIdx.x * blockDim.x + threadIdx.x;
array_a[my_index] = my_index % (num_elements/2); // write overlaping indicies
__syncthreads();
int next_index = array_a[my_index]; // use written index
array_a[next_index] = my_index; // cause a write write race
}
int main(void) {
// malloc arrays
unsigned int *host_array = (unsigned int*) malloc(SIZE*sizeof(unsigned int));
unsigned int *device_array_a = 0;
hipMalloc((void **) &device_array_a, SIZE*sizeof(unsigned int));
// check mallocs
if (host_array == 0) { return 1;}
if (device_array_a == 0) { return 2;}
// init host array to 0
for (int i=0; i<SIZE; i++) {
host_array[i] = 0;
}
// copy to device, call global, and copy output back
hipMemcpy(device_array_a, host_array, SIZE, hipMemcpyHostToDevice);
device_global<<<BLOCKS,(SIZE/BLOCKS)>>> (device_array_a, SIZE);
hipMemcpy(host_array, device_array_a, SIZE, hipMemcpyDeviceToHost);
// print output
for (int i=0; i<SIZE; i += SIZE/BLOCKS) {
for (int j=0; j<SIZE/BLOCKS; j++){
printf("%d, ", host_array[i+j]);
}
printf("\n");
}
// cleanup
free(host_array);
hipFree(device_array_a);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13device_globalPji
.globl _Z13device_globalPji
.p2align 8
.type _Z13device_globalPji,@function
_Z13device_globalPji:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_ashr_i32 s4, s2, 1
s_ashr_i32 s2, s2, 31
s_add_i32 s4, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s4, s2
v_cvt_f32_u32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v4
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
v_sub_nc_u32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_xor_b32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13device_globalPji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13device_globalPji, .Lfunc_end0-_Z13device_globalPji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13device_globalPji
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13device_globalPji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 64
#define BLOCKS 4
__global__ void device_global(unsigned int *array_a, int num_elements) {
int my_index = blockIdx.x * blockDim.x + threadIdx.x;
array_a[my_index] = my_index % (num_elements/2); // write overlaping indicies
__syncthreads();
int next_index = array_a[my_index]; // use written index
array_a[next_index] = my_index; // cause a write write race
}
int main(void) {
// malloc arrays
unsigned int *host_array = (unsigned int*) malloc(SIZE*sizeof(unsigned int));
unsigned int *device_array_a = 0;
hipMalloc((void **) &device_array_a, SIZE*sizeof(unsigned int));
// check mallocs
if (host_array == 0) { return 1;}
if (device_array_a == 0) { return 2;}
// init host array to 0
for (int i=0; i<SIZE; i++) {
host_array[i] = 0;
}
// copy to device, call global, and copy output back
hipMemcpy(device_array_a, host_array, SIZE, hipMemcpyHostToDevice);
device_global<<<BLOCKS,(SIZE/BLOCKS)>>> (device_array_a, SIZE);
hipMemcpy(host_array, device_array_a, SIZE, hipMemcpyDeviceToHost);
// print output
for (int i=0; i<SIZE; i += SIZE/BLOCKS) {
for (int j=0; j<SIZE/BLOCKS; j++){
printf("%d, ", host_array[i+j]);
}
printf("\n");
}
// cleanup
free(host_array);
hipFree(device_array_a);
}
|
.text
.file "race_00.hip"
.globl _Z28__device_stub__device_globalPji # -- Begin function _Z28__device_stub__device_globalPji
.p2align 4, 0x90
.type _Z28__device_stub__device_globalPji,@function
_Z28__device_stub__device_globalPji: # @_Z28__device_stub__device_globalPji
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13device_globalPji, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__device_globalPji, .Lfunc_end0-_Z28__device_stub__device_globalPji
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
testq %rbx, %rbx
je .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.4: # %.preheader24.preheader
xorps %xmm0, %xmm0
movups %xmm0, 240(%rbx)
movups %xmm0, 224(%rbx)
movups %xmm0, 208(%rbx)
movups %xmm0, 192(%rbx)
movups %xmm0, 176(%rbx)
movups %xmm0, 160(%rbx)
movups %xmm0, 144(%rbx)
movups %xmm0, 128(%rbx)
movups %xmm0, 112(%rbx)
movups %xmm0, 96(%rbx)
movups %xmm0, 80(%rbx)
movups %xmm0, 64(%rbx)
movups %xmm0, 48(%rbx)
movups %xmm0, 32(%rbx)
movups %xmm0, 16(%rbx)
movups %xmm0, (%rbx)
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 12(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $64, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13device_globalPji, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $16, %r12
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 16(%r15), %rax
addq $64, %r14
cmpq $48, %r15
movq %rax, %r15
jb .LBB1_7
# %bb.10:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB1_11
.LBB1_1:
movl $1, %eax
jmp .LBB1_11
.LBB1_3:
movl $2, %eax
.LBB1_11:
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13device_globalPji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13device_globalPji,@object # @_Z13device_globalPji
.section .rodata,"a",@progbits
.globl _Z13device_globalPji
.p2align 3, 0x0
_Z13device_globalPji:
.quad _Z28__device_stub__device_globalPji
.size _Z13device_globalPji, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13device_globalPji"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__device_globalPji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13device_globalPji
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z13device_globalPji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ LEA.HI R0, R0, c[0x0][0x168], RZ, 0x1 ; /* 0x00005a0000007a11 */
/* 0x000fe200078f08ff */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e260000002100 */
/*0060*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc80000011400 */
/*0070*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc80000000000 */
/*0080*/ I2F.RP R4, R8 ; /* 0x0000000800047306 */
/* 0x000e620000209400 */
/*0090*/ IMAD R7, R7, c[0x0][0x0], R6 ; /* 0x0000000007077a24 */
/* 0x001fe200078e0206 */
/*00a0*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fcc0000000000 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e220000001000 */
/*00c0*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f46270 */
/*00d0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fe40007ffe0ff */
/*00e0*/ IABS R4, R7 ; /* 0x0000000700047213 */
/* 0x000fc60000000000 */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0110*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*0120*/ IMAD R5, R5, R8, RZ ; /* 0x0000000805057224 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*0140*/ IMAD.MOV R2, RZ, RZ, -R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0a06 */
/*0150*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD R3, R3, R2, R4 ; /* 0x0000000203037224 */
/* 0x000fe400078e0204 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0180*/ ISETP.GT.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f04070 */
/*0190*/ @!P0 IADD3 R3, R3, -R8, RZ ; /* 0x8000000803038210 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*01b0*/ ISETP.GT.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f24070 */
/*01c0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x0000000103039824 */
/* 0x000fca00078e0a08 */
/*01d0*/ MOV R9, R3 ; /* 0x0000000300097202 */
/* 0x000fe20000000f00 */
/*01e0*/ IMAD.WIDE R2, R7, R5, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fc600078e0205 */
/*01f0*/ @!P2 IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff0909a210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P0 LOP3.LUT R9, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff098212 */
/* 0x000fca00078e33ff */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x004fca00078e0205 */
/*0250*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13device_globalPji
.globl _Z13device_globalPji
.p2align 8
.type _Z13device_globalPji,@function
_Z13device_globalPji:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_ashr_i32 s4, s2, 1
s_ashr_i32 s2, s2, 31
s_add_i32 s4, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s4, s2
v_cvt_f32_u32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v4
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
v_sub_nc_u32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_xor_b32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13device_globalPji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13device_globalPji, .Lfunc_end0-_Z13device_globalPji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13device_globalPji
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13device_globalPji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0004d208_00000000-6_race_00.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z13device_globalPjiPji
.type _Z34__device_stub__Z13device_globalPjiPji, @function
_Z34__device_stub__Z13device_globalPjiPji:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13device_globalPji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z13device_globalPjiPji, .-_Z34__device_stub__Z13device_globalPjiPji
.globl _Z13device_globalPji
.type _Z13device_globalPji, @function
_Z13device_globalPji:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13device_globalPjiPji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13device_globalPji, .-_Z13device_globalPji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d, "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $256, %edi
call malloc@PLT
movq %rax, %r13
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
testq %r13, %r13
je .L19
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L20
leaq 256(%r13), %rdx
movq %r13, %rax
.L13:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
movl $1, %ecx
movl $64, %edx
movq %r13, %rsi
call cudaMemcpy@PLT
movl $16, 28(%rsp)
movl $1, 32(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L14:
movl $2, %ecx
movl $64, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 64(%r13), %rbp
movl $0, %r14d
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r15
.L15:
leaq -64(%rbp), %rbx
.L16:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L16
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $16, %r14d
addq $64, %rbp
cmpl $64, %r14d
jne .L15
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L25
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $64, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z13device_globalPjiPji
jmp .L14
.L19:
movl $1, %eax
jmp .L11
.L20:
movl $2, %eax
jmp .L11
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13device_globalPji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13device_globalPji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "race_00.hip"
.globl _Z28__device_stub__device_globalPji # -- Begin function _Z28__device_stub__device_globalPji
.p2align 4, 0x90
.type _Z28__device_stub__device_globalPji,@function
_Z28__device_stub__device_globalPji: # @_Z28__device_stub__device_globalPji
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13device_globalPji, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__device_globalPji, .Lfunc_end0-_Z28__device_stub__device_globalPji
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
testq %rbx, %rbx
je .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.4: # %.preheader24.preheader
xorps %xmm0, %xmm0
movups %xmm0, 240(%rbx)
movups %xmm0, 224(%rbx)
movups %xmm0, 208(%rbx)
movups %xmm0, 192(%rbx)
movups %xmm0, 176(%rbx)
movups %xmm0, 160(%rbx)
movups %xmm0, 144(%rbx)
movups %xmm0, 128(%rbx)
movups %xmm0, 112(%rbx)
movups %xmm0, 96(%rbx)
movups %xmm0, 80(%rbx)
movups %xmm0, 64(%rbx)
movups %xmm0, 48(%rbx)
movups %xmm0, 32(%rbx)
movups %xmm0, 16(%rbx)
movups %xmm0, (%rbx)
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 12(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $64, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13device_globalPji, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $16, %r12
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 16(%r15), %rax
addq $64, %r14
cmpq $48, %r15
movq %rax, %r15
jb .LBB1_7
# %bb.10:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB1_11
.LBB1_1:
movl $1, %eax
jmp .LBB1_11
.LBB1_3:
movl $2, %eax
.LBB1_11:
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13device_globalPji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13device_globalPji,@object # @_Z13device_globalPji
.section .rodata,"a",@progbits
.globl _Z13device_globalPji
.p2align 3, 0x0
_Z13device_globalPji:
.quad _Z28__device_stub__device_globalPji
.size _Z13device_globalPji, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13device_globalPji"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__device_globalPji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13device_globalPji
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void __pairmult2(int nrows, int bncols, int brows1, int brows2, float *A, int lda, float *A2, int lda2, float *Bdata, int *Bir, int *Bjc, int broff, int bcoff, float *C, int ldc, int transpose) {}
|
code for sm_80
Function : _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void __pairmult2(int nrows, int bncols, int brows1, int brows2, float *A, int lda, float *A2, int lda2, float *Bdata, int *Bir, int *Bjc, int broff, int bcoff, float *C, int ldc, int transpose) {}
|
.file "tmpxft_001ba4e6_00000000-6___pairmult2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_iiiiiiPfiS_iS_PiS0_iiS_ii
.type _Z52__device_stub__Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_iiiiiiPfiS_iS_PiS0_iiS_ii, @function
_Z52__device_stub__Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_iiiiiiPfiS_iS_PiS0_iiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movl %edi, 76(%rsp)
movl %esi, 72(%rsp)
movl %edx, 68(%rsp)
movl %ecx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 52(%rsp)
movq 304(%rsp), %rax
movq %rax, 40(%rsp)
movq 320(%rsp), %rax
movq %rax, 32(%rsp)
movq 328(%rsp), %rax
movq %rax, 24(%rsp)
movq 336(%rsp), %rax
movq %rax, 16(%rsp)
movq 360(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 68(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 32(%rsp), %rax
movq %rax, 208(%rsp)
leaq 24(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 352(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
leaq 368(%rsp), %rax
movq %rax, 256(%rsp)
leaq 376(%rsp), %rax
movq %rax, 264(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 312
pushq 88(%rsp)
.cfi_def_cfa_offset 320
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_iiiiiiPfiS_iS_PiS0_iiS_ii, .-_Z52__device_stub__Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_iiiiiiPfiS_iS_PiS0_iiS_ii
.globl _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.type _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii, @function
_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z52__device_stub__Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_iiiiiiPfiS_iS_PiS0_iiS_ii
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii, .-_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void __pairmult2(int nrows, int bncols, int brows1, int brows2, float *A, int lda, float *A2, int lda2, float *Bdata, int *Bir, int *Bjc, int broff, int bcoff, float *C, int ldc, int transpose) {}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __pairmult2(int nrows, int bncols, int brows1, int brows2, float *A, int lda, float *A2, int lda2, float *Bdata, int *Bir, int *Bjc, int broff, int bcoff, float *C, int ldc, int transpose) {}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __pairmult2(int nrows, int bncols, int brows1, int brows2, float *A, int lda, float *A2, int lda2, float *Bdata, int *Bir, int *Bjc, int broff, int bcoff, float *C, int ldc, int transpose) {}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.globl _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.p2align 8
.type _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii,@function
_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 96
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii, .Lfunc_end0-_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .offset: 88
.size: 4
.value_kind: by_value
- .offset: 92
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 96
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __pairmult2(int nrows, int bncols, int brows1, int brows2, float *A, int lda, float *A2, int lda2, float *Bdata, int *Bir, int *Bjc, int broff, int bcoff, float *C, int ldc, int transpose) {}
|
.text
.file "__pairmult2.hip"
.globl _Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii # -- Begin function _Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.p2align 4, 0x90
.type _Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii,@function
_Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii: # @_Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 224(%rsp), %rax
movq %rax, 128(%rsp)
leaq 232(%rsp), %rax
movq %rax, 136(%rsp)
leaq 240(%rsp), %rax
movq %rax, 144(%rsp)
leaq 248(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii, .Lfunc_end0-_Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii,@object # @_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.section .rodata,"a",@progbits
.globl _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.p2align 3, 0x0
_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii:
.quad _Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.size _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.globl _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.p2align 8
.type _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii,@function
_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 96
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii, .Lfunc_end0-_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .offset: 88
.size: 4
.value_kind: by_value
- .offset: 92
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 96
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001ba4e6_00000000-6___pairmult2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_iiiiiiPfiS_iS_PiS0_iiS_ii
.type _Z52__device_stub__Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_iiiiiiPfiS_iS_PiS0_iiS_ii, @function
_Z52__device_stub__Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_iiiiiiPfiS_iS_PiS0_iiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movl %edi, 76(%rsp)
movl %esi, 72(%rsp)
movl %edx, 68(%rsp)
movl %ecx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 52(%rsp)
movq 304(%rsp), %rax
movq %rax, 40(%rsp)
movq 320(%rsp), %rax
movq %rax, 32(%rsp)
movq 328(%rsp), %rax
movq %rax, 24(%rsp)
movq 336(%rsp), %rax
movq %rax, 16(%rsp)
movq 360(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 68(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 32(%rsp), %rax
movq %rax, 208(%rsp)
leaq 24(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 352(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
leaq 368(%rsp), %rax
movq %rax, 256(%rsp)
leaq 376(%rsp), %rax
movq %rax, 264(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 312
pushq 88(%rsp)
.cfi_def_cfa_offset 320
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_iiiiiiPfiS_iS_PiS0_iiS_ii, .-_Z52__device_stub__Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_iiiiiiPfiS_iS_PiS0_iiS_ii
.globl _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.type _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii, @function
_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 88(%rsp)
.cfi_def_cfa_offset 40
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z52__device_stub__Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_iiiiiiPfiS_iS_PiS0_iiS_ii
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii, .-_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "__pairmult2.hip"
.globl _Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii # -- Begin function _Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.p2align 4, 0x90
.type _Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii,@function
_Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii: # @_Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 224(%rsp), %rax
movq %rax, 128(%rsp)
leaq 232(%rsp), %rax
movq %rax, 136(%rsp)
leaq 240(%rsp), %rax
movq %rax, 144(%rsp)
leaq 248(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii, .Lfunc_end0-_Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii,@object # @_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.section .rodata,"a",@progbits
.globl _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.p2align 3, 0x0
_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii:
.quad _Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.size _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub____pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11__pairmult2iiiiPfiS_iS_PiS0_iiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/////// Bom para quando maiores pq o discard n precisa contar varios.
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/functional.h>
#include <thrust/transform.h>
#include <iostream>
#include <math.h>
#include <thrust/iterator/counting_iterator.h>
#include <thrust/random/uniform_real_distribution.h>
#include <thrust/random/linear_congruential_engine.h>
#include <thrust/random.h>
struct rng_gpu{
int SEED;
__device__ __host__
double operator()(const int &i){
thrust::default_random_engine eng(i*SEED);
thrust:: uniform_real_distribution<double> d(0.0,1.0);
eng.discard(100);
return d(eng);
}
};
int main() {
thrust::default_random_engine eng(10);
thrust::uniform_real_distribution<double> dist(25,40);
for(int i =0;i<10;i++){
std::cout<< dist(eng) <<"\n";
}
rng_gpu rg = {.SEED =10};
thrust::device_vector<double> D(10);
thrust::transform(thrust::make_counting_iterator<int>(0),
thrust::make_counting_iterator<int>(10),
D.begin(), rg);
for(int i = 0; i < 10; i++){
std::cout << D[i] << "\n";
}
}
|
/////// Bom para quando maiores pq o discard n precisa contar varios.
#include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/functional.h>
#include <thrust/transform.h>
#include <iostream>
#include <math.h>
#include <thrust/iterator/counting_iterator.h>
#include <thrust/random/uniform_real_distribution.h>
#include <thrust/random/linear_congruential_engine.h>
#include <thrust/random.h>
struct rng_gpu{
int SEED;
__device__ __host__
double operator()(const int &i){
thrust::default_random_engine eng(i*SEED);
thrust:: uniform_real_distribution<double> d(0.0,1.0);
eng.discard(100);
return d(eng);
}
};
int main() {
thrust::default_random_engine eng(10);
thrust::uniform_real_distribution<double> dist(25,40);
for(int i =0;i<10;i++){
std::cout<< dist(eng) <<"\n";
}
rng_gpu rg = {.SEED =10};
thrust::device_vector<double> D(10);
thrust::transform(thrust::make_counting_iterator<int>(0),
thrust::make_counting_iterator<int>(10),
D.begin(), rg);
for(int i = 0; i < 10; i++){
std::cout << D[i] << "\n";
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/////// Bom para quando maiores pq o discard n precisa contar varios.
#include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/functional.h>
#include <thrust/transform.h>
#include <iostream>
#include <math.h>
#include <thrust/iterator/counting_iterator.h>
#include <thrust/random/uniform_real_distribution.h>
#include <thrust/random/linear_congruential_engine.h>
#include <thrust/random.h>
struct rng_gpu{
int SEED;
__device__ __host__
double operator()(const int &i){
thrust::default_random_engine eng(i*SEED);
thrust:: uniform_real_distribution<double> d(0.0,1.0);
eng.discard(100);
return d(eng);
}
};
int main() {
thrust::default_random_engine eng(10);
thrust::uniform_real_distribution<double> dist(25,40);
for(int i =0;i<10;i++){
std::cout<< dist(eng) <<"\n";
}
rng_gpu rg = {.SEED =10};
thrust::device_vector<double> D(10);
thrust::transform(thrust::make_counting_iterator<int>(0),
thrust::make_counting_iterator<int>(10),
D.begin(), rg);
for(int i = 0; i < 10; i++){
std::cout << D[i] << "\n";
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 3, v0
s_lshl_b64 s[0:1], s[2:3], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
flat_store_b64 v[0:1], v[2:3]
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_:
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b32 s12, s[0:1], 0x0
s_load_b32 s13, s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s14, s2, s6
s_addc_u32 s15, 0, s7
s_sub_u32 s2, s4, s14
s_subb_u32 s3, s5, s15
s_mov_b32 s4, 0
v_cmp_gt_i64_e64 s3, 0x100, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, exec_lo
s_cselect_b32 s2, s2, 0x100
s_cmpk_lg_i32 s2, 0x100
s_cbranch_scc0 .LBB1_7
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_mov_b32 s16, 0
s_and_saveexec_b32 s17, vcc_lo
s_cbranch_execz .LBB1_11
s_mov_b64 s[6:7], 0x64
s_mov_b64 s[8:9], 0xbc8f
s_mov_b64 s[2:3], 1
s_mov_b32 s5, 0
.LBB1_3:
s_and_b32 s4, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[4:5], 0
s_cbranch_scc1 .LBB1_5
s_mul_i32 s3, s8, s3
s_mul_hi_u32 s4, s8, s2
s_movk_i32 s10, 0x401
s_add_i32 s3, s4, s3
s_mul_i32 s4, s9, s2
s_mul_i32 s2, s8, s2
s_add_i32 s3, s3, s4
s_add_u32 s4, 0x402, s10
s_addc_u32 s10, 0, 0
v_add_co_u32 v1, s4, s4, 0xfffff800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
s_addc_u32 s10, s10, 1
v_readfirstlane_b32 s4, v1
s_mul_i32 s11, s10, 0x80000001
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s18, s4, 0x80000001
s_mul_i32 s19, s4, 0x80000001
s_sub_i32 s18, s18, s4
s_mul_hi_u32 s20, s4, s19
s_add_i32 s18, s18, s11
s_mul_hi_u32 s21, s10, s19
s_mul_i32 s11, s10, s19
s_mul_hi_u32 s19, s4, s18
s_mul_i32 s4, s4, s18
s_mul_hi_u32 s22, s10, s18
s_add_u32 s4, s20, s4
s_addc_u32 s19, 0, s19
s_add_u32 s4, s4, s11
s_mul_i32 s18, s10, s18
s_addc_u32 s4, s19, s21
s_addc_u32 s11, s22, 0
s_add_u32 s4, s4, s18
s_addc_u32 s11, 0, s11
v_add_co_u32 v1, s4, v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
s_addc_u32 s4, s10, s11
v_readfirstlane_b32 s10, v1
s_mul_i32 s18, s2, s4
s_mul_hi_u32 s11, s2, s4
s_mul_hi_u32 s19, s3, s4
s_mul_i32 s4, s3, s4
s_mul_hi_u32 s20, s2, s10
s_mul_hi_u32 s21, s3, s10
s_mul_i32 s10, s3, s10
s_add_u32 s18, s20, s18
s_addc_u32 s11, 0, s11
s_add_u32 s10, s18, s10
s_addc_u32 s10, s11, s21
s_addc_u32 s11, s19, 0
s_add_u32 s4, s10, s4
s_addc_u32 s10, 0, s11
s_mul_hi_u32 s11, s4, 0x7fffffff
s_mul_i32 s4, s4, 0x7fffffff
s_mul_i32 s10, s10, 0x7fffffff
v_sub_co_u32 v1, s2, s2, s4
s_add_i32 s11, s11, s10
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_co_u32 v2, s2, v1, 0x7fffffff
s_subb_u32 s3, s3, s11
s_cmp_lg_u32 s2, 0
v_readfirstlane_b32 s19, v1
v_sub_co_u32 v3, s2, v2, 0x7fffffff
v_readfirstlane_b32 s4, v2
s_subb_u32 s10, s3, 0
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_2)
v_readfirstlane_b32 s18, v3
s_subb_u32 s2, s10, 0
s_cmp_gt_u32 s4, 0x7ffffffe
s_cselect_b32 s11, -1, 0
s_cmp_eq_u32 s10, 0
s_cselect_b32 s11, s11, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s11, 0
s_cselect_b32 s2, s2, s10
s_cselect_b32 s4, s18, s4
s_cmp_gt_u32 s19, 0x7ffffffe
s_cselect_b32 s10, -1, 0
s_cmp_eq_u32 s3, 0
s_cselect_b32 s10, s10, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s10, 0
s_cselect_b32 s3, s2, s3
s_cselect_b32 s2, s4, s19
.LBB1_5:
s_mul_i32 s4, s8, s9
s_mul_hi_u32 s9, s8, s8
s_movk_i32 s18, 0x401
s_add_i32 s9, s9, s4
s_lshr_b64 s[10:11], s[6:7], 1
s_add_i32 s4, s9, s4
s_add_u32 s9, 0x402, s18
s_addc_u32 s18, 0, 0
v_add_co_u32 v1, s9, s9, 0xfffff800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s9, 0
s_mul_i32 s8, s8, s8
s_addc_u32 s18, s18, 1
v_readfirstlane_b32 s9, v1
s_mul_i32 s19, s18, 0x80000001
v_cmp_gt_u64_e64 s6, s[6:7], 1
s_delay_alu instid0(VALU_DEP_2)
s_mul_hi_u32 s20, s9, 0x80000001
s_mul_i32 s21, s9, 0x80000001
s_sub_i32 s20, s20, s9
s_mul_hi_u32 s22, s9, s21
s_add_i32 s20, s20, s19
s_mul_hi_u32 s23, s18, s21
s_mul_i32 s19, s18, s21
s_mul_hi_u32 s21, s9, s20
s_mul_i32 s9, s9, s20
s_mul_hi_u32 s24, s18, s20
s_add_u32 s9, s22, s9
s_addc_u32 s21, 0, s21
s_add_u32 s9, s9, s19
s_mul_i32 s20, s18, s20
s_addc_u32 s9, s21, s23
s_addc_u32 s19, s24, 0
s_add_u32 s9, s9, s20
s_addc_u32 s19, 0, s19
v_add_co_u32 v1, s9, v1, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s9, 0
s_addc_u32 s9, s18, s19
v_readfirstlane_b32 s18, v1
s_mul_i32 s20, s8, s9
s_mul_hi_u32 s19, s8, s9
s_mul_hi_u32 s21, s4, s9
s_mul_i32 s9, s4, s9
s_mul_hi_u32 s22, s8, s18
s_mul_hi_u32 s23, s4, s18
s_mul_i32 s18, s4, s18
s_add_u32 s20, s22, s20
s_addc_u32 s19, 0, s19
s_add_u32 s18, s20, s18
s_addc_u32 s18, s19, s23
s_addc_u32 s19, s21, 0
s_add_u32 s9, s18, s9
s_addc_u32 s18, 0, s19
s_mul_hi_u32 s19, s9, 0x7fffffff
s_mul_i32 s9, s9, 0x7fffffff
s_mul_i32 s18, s18, 0x7fffffff
v_sub_co_u32 v1, s8, s8, s9
s_add_i32 s19, s19, s18
s_cmp_lg_u32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_co_u32 v2, s8, v1, 0x7fffffff
s_subb_u32 s4, s4, s19
s_cmp_lg_u32 s8, 0
v_readfirstlane_b32 s21, v1
v_sub_co_u32 v3, s8, v2, 0x7fffffff
v_readfirstlane_b32 s9, v2
s_subb_u32 s18, s4, 0
s_cmp_lg_u32 s8, 0
s_delay_alu instid0(VALU_DEP_2)
v_readfirstlane_b32 s20, v3
s_subb_u32 s8, s18, 0
s_cmp_gt_u32 s9, 0x7ffffffe
s_cselect_b32 s19, -1, 0
s_cmp_eq_u32 s18, 0
s_cselect_b32 s19, s19, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s19, 0
s_cselect_b32 s8, s8, s18
s_cselect_b32 s18, s20, s9
s_cmp_gt_u32 s21, 0x7ffffffe
s_cselect_b32 s9, -1, 0
s_cmp_eq_u32 s4, 0
s_cselect_b32 s9, s9, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s9, 0
s_cselect_b32 s9, s8, s4
s_cselect_b32 s8, s18, s21
s_and_b32 vcc_lo, exec_lo, s6
s_cbranch_vccz .LBB1_10
s_mov_b64 s[6:7], s[10:11]
s_branch .LBB1_3
.LBB1_7:
s_cbranch_execnz .LBB1_12
.LBB1_8:
s_and_saveexec_b32 s3, s4
s_cbranch_execz .LBB1_18
.LBB1_9:
v_xor_b32_e32 v0, 0x7fffffff, v4
v_sub_nc_u32_e32 v4, 0, v4
s_mov_b32 s3, 0x41dfffff
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, v4, v0, s2
s_mov_b32 s2, 0xff800000
v_add3_u32 v0, v3, v0, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f64_u32_e32 v[3:4], v0
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_div_scale_f64 v[5:6], null, s[2:3], s[2:3], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[7:8], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_div_scale_f64 v[9:10], vcc_lo, v[3:4], s[2:3], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[9:10], v[7:8]
v_fma_f64 v[5:6], -v[5:6], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f64 v[3:4], v[5:6], s[2:3], v[3:4]
flat_store_b64 v[0:1], v[3:4]
s_endpgm
.LBB1_10:
v_add_co_u32 v1, s5, s14, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v2, null, s15, 0, s5
s_movk_i32 s5, 0x401
v_add_nc_u32_e32 v3, s12, v1
s_add_u32 s5, 0x402, s5
s_addc_u32 s6, 0, 0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s13, v3
v_mul_hi_u32 v4, v3, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v3, v4
v_lshrrev_b32_e32 v5, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v5, v4
v_add_co_u32 v5, s5, s5, 0xfffff800
s_cmp_lg_u32 s5, 0
s_addc_u32 s6, s6, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v4, 30, v4
v_readfirstlane_b32 s5, v5
s_mul_i32 s7, s6, 0x80000001
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v4, 0x7fffffff
s_mul_hi_u32 s8, s5, 0x80000001
s_mul_i32 s9, s5, 0x80000001
s_sub_i32 s8, s8, s5
s_mul_hi_u32 s10, s5, s9
s_add_i32 s8, s8, s7
s_mul_hi_u32 s11, s6, s9
s_mul_i32 s7, s6, s9
v_sub_nc_u32_e32 v3, v3, v4
s_mul_hi_u32 s9, s5, s8
s_mul_i32 s5, s5, s8
s_mul_hi_u32 s18, s6, s8
s_add_u32 s5, s10, s5
v_max_u32_e32 v7, 1, v3
s_addc_u32 s9, 0, s9
s_mul_i32 s8, s6, s8
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s2, v7, 0
s_add_u32 s2, s5, s7
s_addc_u32 s2, s9, s11
s_addc_u32 s5, s18, 0
s_add_u32 s2, s2, s8
s_addc_u32 s5, 0, s5
v_add_co_u32 v10, s2, v5, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s2, 0
v_mad_u64_u32 v[5:6], null, s3, v7, v[4:5]
s_addc_u32 s2, s6, s5
v_mul_hi_u32 v4, v3, v10
v_mad_u64_u32 v[6:7], null, v3, s2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v5, v10, 0
v_add_co_u32 v4, vcc_lo, v4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v7, vcc_lo
v_mad_u64_u32 v[6:7], null, v5, s2, 0
v_add_co_u32 v4, vcc_lo, v4, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, v10, v9, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v6
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v4, 0x7fffffff, 0
v_mov_b32_e32 v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v3, vcc_lo, v3, v6
v_mad_u64_u32 v[7:8], null, v9, 0x7fffffff, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_co_ci_u32_e32 v4, vcc_lo, v5, v7, vcc_lo
v_sub_co_u32 v5, vcc_lo, v3, 0x7fffffff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 0x7ffffffe, v5
v_cndmask_b32_e64 v7, 0, -1, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 0x7ffffffe, v3
v_cndmask_b32_e64 v8, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v6, -1, v7 :: v_dual_add_nc_u32 v7, 0x80000001, v5
v_cmp_eq_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v4, -1, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ne_u32_e32 vcc_lo, 0, v6
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, 0xbc8f1391
v_lshrrev_b32_e32 v4, 15, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_u32_u24_e32 v5, 0xadc8, v4
v_mul_u32_u24_e32 v4, 0xd47, v4
v_sub_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, 0xbc8f
v_cmp_lt_u32_e32 vcc_lo, v3, v4
s_and_b32 s2, vcc_lo, exec_lo
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s16
s_cbranch_vccz .LBB1_8
.LBB1_12:
s_mov_b64 s[6:7], 0x64
s_mov_b64 s[8:9], 0xbc8f
s_mov_b64 s[2:3], 1
s_mov_b32 s5, 0
.LBB1_13:
s_and_b32 s4, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[4:5], 0
s_cbranch_scc1 .LBB1_15
s_mul_i32 s3, s8, s3
s_mul_hi_u32 s4, s8, s2
s_movk_i32 s10, 0x401
s_add_i32 s3, s4, s3
s_mul_i32 s4, s9, s2
s_mul_i32 s2, s8, s2
s_add_i32 s3, s3, s4
s_add_u32 s4, 0x402, s10
s_addc_u32 s10, 0, 0
v_add_co_u32 v1, s4, s4, 0xfffff800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
s_addc_u32 s10, s10, 1
v_readfirstlane_b32 s4, v1
s_mul_i32 s11, s10, 0x80000001
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s16, s4, 0x80000001
s_mul_i32 s17, s4, 0x80000001
s_sub_i32 s16, s16, s4
s_mul_hi_u32 s18, s4, s17
s_add_i32 s16, s16, s11
s_mul_hi_u32 s19, s10, s17
s_mul_i32 s11, s10, s17
s_mul_hi_u32 s17, s4, s16
s_mul_i32 s4, s4, s16
s_mul_hi_u32 s20, s10, s16
s_add_u32 s4, s18, s4
s_addc_u32 s17, 0, s17
s_add_u32 s4, s4, s11
s_mul_i32 s16, s10, s16
s_addc_u32 s4, s17, s19
s_addc_u32 s11, s20, 0
s_add_u32 s4, s4, s16
s_addc_u32 s11, 0, s11
v_add_co_u32 v1, s4, v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
s_addc_u32 s4, s10, s11
v_readfirstlane_b32 s10, v1
s_mul_i32 s16, s2, s4
s_mul_hi_u32 s11, s2, s4
s_mul_hi_u32 s17, s3, s4
s_mul_i32 s4, s3, s4
s_mul_hi_u32 s18, s2, s10
s_mul_hi_u32 s19, s3, s10
s_mul_i32 s10, s3, s10
s_add_u32 s16, s18, s16
s_addc_u32 s11, 0, s11
s_add_u32 s10, s16, s10
s_addc_u32 s10, s11, s19
s_addc_u32 s11, s17, 0
s_add_u32 s4, s10, s4
s_addc_u32 s10, 0, s11
s_mul_hi_u32 s11, s4, 0x7fffffff
s_mul_i32 s4, s4, 0x7fffffff
s_mul_i32 s10, s10, 0x7fffffff
v_sub_co_u32 v1, s2, s2, s4
s_add_i32 s11, s11, s10
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_co_u32 v2, s2, v1, 0x7fffffff
s_subb_u32 s3, s3, s11
s_cmp_lg_u32 s2, 0
v_readfirstlane_b32 s17, v1
v_sub_co_u32 v3, s2, v2, 0x7fffffff
v_readfirstlane_b32 s4, v2
s_subb_u32 s10, s3, 0
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_2)
v_readfirstlane_b32 s16, v3
s_subb_u32 s2, s10, 0
s_cmp_gt_u32 s4, 0x7ffffffe
s_cselect_b32 s11, -1, 0
s_cmp_eq_u32 s10, 0
s_cselect_b32 s11, s11, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s11, 0
s_cselect_b32 s2, s2, s10
s_cselect_b32 s4, s16, s4
s_cmp_gt_u32 s17, 0x7ffffffe
s_cselect_b32 s10, -1, 0
s_cmp_eq_u32 s3, 0
s_cselect_b32 s10, s10, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s10, 0
s_cselect_b32 s3, s2, s3
s_cselect_b32 s2, s4, s17
.LBB1_15:
s_mul_i32 s4, s8, s9
s_mul_hi_u32 s9, s8, s8
s_movk_i32 s16, 0x401
s_add_i32 s9, s9, s4
s_lshr_b64 s[10:11], s[6:7], 1
s_add_i32 s4, s9, s4
s_add_u32 s9, 0x402, s16
s_addc_u32 s16, 0, 0
v_add_co_u32 v1, s9, s9, 0xfffff800
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s9, 0
s_mul_i32 s8, s8, s8
s_addc_u32 s16, s16, 1
v_readfirstlane_b32 s9, v1
s_mul_i32 s17, s16, 0x80000001
v_cmp_gt_u64_e64 s6, s[6:7], 1
s_delay_alu instid0(VALU_DEP_2)
s_mul_hi_u32 s18, s9, 0x80000001
s_mul_i32 s19, s9, 0x80000001
s_sub_i32 s18, s18, s9
s_mul_hi_u32 s20, s9, s19
s_add_i32 s18, s18, s17
s_mul_hi_u32 s21, s16, s19
s_mul_i32 s17, s16, s19
s_mul_hi_u32 s19, s9, s18
s_mul_i32 s9, s9, s18
s_mul_hi_u32 s22, s16, s18
s_add_u32 s9, s20, s9
s_addc_u32 s19, 0, s19
s_add_u32 s9, s9, s17
s_mul_i32 s18, s16, s18
s_addc_u32 s9, s19, s21
s_addc_u32 s17, s22, 0
s_add_u32 s9, s9, s18
s_addc_u32 s17, 0, s17
v_add_co_u32 v1, s9, v1, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s9, 0
s_addc_u32 s9, s16, s17
v_readfirstlane_b32 s16, v1
s_mul_i32 s18, s8, s9
s_mul_hi_u32 s17, s8, s9
s_mul_hi_u32 s19, s4, s9
s_mul_i32 s9, s4, s9
s_mul_hi_u32 s20, s8, s16
s_mul_hi_u32 s21, s4, s16
s_mul_i32 s16, s4, s16
s_add_u32 s18, s20, s18
s_addc_u32 s17, 0, s17
s_add_u32 s16, s18, s16
s_addc_u32 s16, s17, s21
s_addc_u32 s17, s19, 0
s_add_u32 s9, s16, s9
s_addc_u32 s16, 0, s17
s_mul_hi_u32 s17, s9, 0x7fffffff
s_mul_i32 s9, s9, 0x7fffffff
s_mul_i32 s16, s16, 0x7fffffff
v_sub_co_u32 v1, s8, s8, s9
s_add_i32 s17, s17, s16
s_cmp_lg_u32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_co_u32 v2, s8, v1, 0x7fffffff
s_subb_u32 s4, s4, s17
s_cmp_lg_u32 s8, 0
v_readfirstlane_b32 s19, v1
v_sub_co_u32 v3, s8, v2, 0x7fffffff
v_readfirstlane_b32 s9, v2
s_subb_u32 s16, s4, 0
s_cmp_lg_u32 s8, 0
s_delay_alu instid0(VALU_DEP_2)
v_readfirstlane_b32 s18, v3
s_subb_u32 s8, s16, 0
s_cmp_gt_u32 s9, 0x7ffffffe
s_cselect_b32 s17, -1, 0
s_cmp_eq_u32 s16, 0
s_cselect_b32 s17, s17, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s17, 0
s_cselect_b32 s8, s8, s16
s_cselect_b32 s16, s18, s9
s_cmp_gt_u32 s19, 0x7ffffffe
s_cselect_b32 s9, -1, 0
s_cmp_eq_u32 s4, 0
s_cselect_b32 s9, s9, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s9, 0
s_cselect_b32 s9, s8, s4
s_cselect_b32 s8, s16, s19
s_and_b32 vcc_lo, exec_lo, s6
s_cbranch_vccz .LBB1_17
s_mov_b64 s[6:7], s[10:11]
s_branch .LBB1_13
.LBB1_17:
v_add_co_u32 v1, s4, s14, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v2, null, s15, 0, s4
s_movk_i32 s4, 0x401
v_add_nc_u32_e32 v0, s12, v1
s_add_u32 s4, 0x402, s4
s_addc_u32 s5, 0, 0
v_add_co_u32 v5, s4, s4, 0xfffff800
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, s13, v0
s_cmp_lg_u32 s4, 0
v_readfirstlane_b32 s4, v5
s_addc_u32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s6, s5, 0x80000001
s_mul_hi_u32 s7, s4, 0x80000001
s_delay_alu instid0(VALU_DEP_2)
v_mul_hi_u32 v3, v0, 3
s_sub_i32 s7, s7, s4
s_mul_i32 s8, s4, 0x80000001
s_add_i32 s7, s7, s6
s_mul_hi_u32 s9, s4, s8
s_mul_hi_u32 s10, s5, s8
s_mul_i32 s6, s5, s8
s_mul_hi_u32 s8, s4, s7
v_sub_nc_u32_e32 v4, v0, v3
s_mul_i32 s4, s4, s7
s_mul_hi_u32 s11, s5, s7
s_add_u32 s4, s9, s4
s_addc_u32 s8, 0, s8
v_lshrrev_b32_e32 v4, 1, v4
s_mul_i32 s7, s5, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v4, v3
v_lshrrev_b32_e32 v3, 30, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, 0x7fffffff
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_u32_e32 v6, 1, v0
v_mad_u64_u32 v[3:4], null, s2, v6, 0
s_add_u32 s2, s4, s6
s_addc_u32 s2, s8, s10
s_addc_u32 s4, s11, 0
s_add_u32 s2, s2, s7
s_addc_u32 s4, 0, s4
v_add_co_u32 v9, s2, v5, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v4
s_cmp_lg_u32 s2, 0
s_addc_u32 s2, s5, s4
s_mov_b32 s4, -1
v_mad_u64_u32 v[4:5], null, s3, v6, v[0:1]
v_mad_u64_u32 v[5:6], null, v3, s2, 0
v_mul_hi_u32 v0, v3, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v4, v9, 0
v_add_co_u32 v0, vcc_lo, v0, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v6, vcc_lo
v_mad_u64_u32 v[5:6], null, v4, s2, 0
v_add_co_u32 v0, vcc_lo, v0, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v0, vcc_lo, v9, v8, vcc_lo
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v5
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v0, 0x7fffffff, 0
v_mov_b32_e32 v0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[6:7], null, v8, 0x7fffffff, v[0:1]
v_sub_co_u32 v0, vcc_lo, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_ci_u32_e32 v3, vcc_lo, v4, v6, vcc_lo
v_sub_co_u32 v4, vcc_lo, v0, 0x7fffffff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 0x7ffffffe, v4
v_cndmask_b32_e64 v6, 0, -1, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 0x7ffffffe, v0
v_cndmask_b32_e64 v7, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, -1, v6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v3
v_dual_cndmask_b32 v3, -1, v7 :: v_dual_add_nc_u32 v6, 0x80000001, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v5
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, 0xbc8f1391
v_lshrrev_b32_e32 v4, 15, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_u32_u24_e32 v3, 0xadc8, v4
v_mul_u32_u24_e32 v4, 0xd47, v4
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, 0xbc8f
v_cmp_lt_u32_e64 s2, v3, v4
s_and_saveexec_b32 s3, s4
s_cbranch_execnz .LBB1_9
.LBB1_18:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIdEEdEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIiNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIdEEEENS3_14no_stencil_tagE7rng_gpuNS3_21always_true_predicateEEElLj1EEEvT0_T1_SI_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void atomic_red(const float *gdata, float *out){
size_t idx = threadIdx.x+blockDim.x*blockIdx.x;
if (idx < N) atomicAdd(out, gdata[idx]);
}
|
code for sm_80
Function : _Z10atomic_redPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R2, 0xfff, PT ; /* 0x00000fff0200780c */
/* 0x000fda0003f04070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe40000000f00 */
/*00b0*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fca0000000f00 */
/*00c0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R3 ; /* 0x000000030400798e */
/* 0x004fe2000c10e784 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void atomic_red(const float *gdata, float *out){
size_t idx = threadIdx.x+blockDim.x*blockIdx.x;
if (idx < N) atomicAdd(out, gdata[idx]);
}
|
.file "tmpxft_00173484_00000000-6_atomic_red.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10atomic_redPKfPfPKfPf
.type _Z33__device_stub__Z10atomic_redPKfPfPKfPf, @function
_Z33__device_stub__Z10atomic_redPKfPfPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10atomic_redPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10atomic_redPKfPfPKfPf, .-_Z33__device_stub__Z10atomic_redPKfPfPKfPf
.globl _Z10atomic_redPKfPf
.type _Z10atomic_redPKfPf, @function
_Z10atomic_redPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10atomic_redPKfPfPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10atomic_redPKfPf, .-_Z10atomic_redPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10atomic_redPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10atomic_redPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void atomic_red(const float *gdata, float *out){
size_t idx = threadIdx.x+blockDim.x*blockIdx.x;
if (idx < N) atomicAdd(out, gdata[idx]);
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void atomic_red(const float *gdata, float *out){
size_t idx = threadIdx.x+blockDim.x*blockIdx.x;
if (idx < N) atomicAdd(out, gdata[idx]);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void atomic_red(const float *gdata, float *out){
size_t idx = threadIdx.x+blockDim.x*blockIdx.x;
if (idx < N) atomicAdd(out, gdata[idx]);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10atomic_redPKfPf
.globl _Z10atomic_redPKfPf
.p2align 8
.type _Z10atomic_redPKfPf,@function
_Z10atomic_redPKfPf:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x1000, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_bfrev_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
.LBB0_2:
s_ctz_i32_b32 s3, s2
s_waitcnt vmcnt(0)
v_readlane_b32 s4, v0, s3
s_lshl_b32 s3, 1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, s3
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, s4, v2
s_cbranch_scc1 .LBB0_2
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s3
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v2
global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10atomic_redPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10atomic_redPKfPf, .Lfunc_end0-_Z10atomic_redPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10atomic_redPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10atomic_redPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void atomic_red(const float *gdata, float *out){
size_t idx = threadIdx.x+blockDim.x*blockIdx.x;
if (idx < N) atomicAdd(out, gdata[idx]);
}
|
.text
.file "atomic_red.hip"
.globl _Z25__device_stub__atomic_redPKfPf # -- Begin function _Z25__device_stub__atomic_redPKfPf
.p2align 4, 0x90
.type _Z25__device_stub__atomic_redPKfPf,@function
_Z25__device_stub__atomic_redPKfPf: # @_Z25__device_stub__atomic_redPKfPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10atomic_redPKfPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__atomic_redPKfPf, .Lfunc_end0-_Z25__device_stub__atomic_redPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10atomic_redPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10atomic_redPKfPf,@object # @_Z10atomic_redPKfPf
.section .rodata,"a",@progbits
.globl _Z10atomic_redPKfPf
.p2align 3, 0x0
_Z10atomic_redPKfPf:
.quad _Z25__device_stub__atomic_redPKfPf
.size _Z10atomic_redPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10atomic_redPKfPf"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__atomic_redPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10atomic_redPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z10atomic_redPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R2, 0xfff, PT ; /* 0x00000fff0200780c */
/* 0x000fda0003f04070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe40000000f00 */
/*00b0*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fca0000000f00 */
/*00c0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R3 ; /* 0x000000030400798e */
/* 0x004fe2000c10e784 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10atomic_redPKfPf
.globl _Z10atomic_redPKfPf
.p2align 8
.type _Z10atomic_redPKfPf,@function
_Z10atomic_redPKfPf:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x1000, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_bfrev_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
.LBB0_2:
s_ctz_i32_b32 s3, s2
s_waitcnt vmcnt(0)
v_readlane_b32 s4, v0, s3
s_lshl_b32 s3, 1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, s3
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, s4, v2
s_cbranch_scc1 .LBB0_2
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s3
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v2
global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10atomic_redPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10atomic_redPKfPf, .Lfunc_end0-_Z10atomic_redPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10atomic_redPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10atomic_redPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00173484_00000000-6_atomic_red.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10atomic_redPKfPfPKfPf
.type _Z33__device_stub__Z10atomic_redPKfPfPKfPf, @function
_Z33__device_stub__Z10atomic_redPKfPfPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10atomic_redPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10atomic_redPKfPfPKfPf, .-_Z33__device_stub__Z10atomic_redPKfPfPKfPf
.globl _Z10atomic_redPKfPf
.type _Z10atomic_redPKfPf, @function
_Z10atomic_redPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10atomic_redPKfPfPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10atomic_redPKfPf, .-_Z10atomic_redPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10atomic_redPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10atomic_redPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "atomic_red.hip"
.globl _Z25__device_stub__atomic_redPKfPf # -- Begin function _Z25__device_stub__atomic_redPKfPf
.p2align 4, 0x90
.type _Z25__device_stub__atomic_redPKfPf,@function
_Z25__device_stub__atomic_redPKfPf: # @_Z25__device_stub__atomic_redPKfPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10atomic_redPKfPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__atomic_redPKfPf, .Lfunc_end0-_Z25__device_stub__atomic_redPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10atomic_redPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10atomic_redPKfPf,@object # @_Z10atomic_redPKfPf
.section .rodata,"a",@progbits
.globl _Z10atomic_redPKfPf
.p2align 3, 0x0
_Z10atomic_redPKfPf:
.quad _Z25__device_stub__atomic_redPKfPf
.size _Z10atomic_redPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10atomic_redPKfPf"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__atomic_redPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10atomic_redPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#include <math.h>
#include <chrono>
__global__ void init(int length, float *a, float *b)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < length; i += stride)
{
a[i] = 2.3423;
b[i] = 1.4214;
}
}
__global__ void mMultiply(int length, float *a, float *b, float *output)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < length; i += stride)
{
output[i] = (a[i] * b[i]);
}
for (int i = index; i < length; i += stride)
{
output[i] = (output[i] * a[i]);
}
for (int i = index; i < length; i += stride)
{
output[i] = (output[i] * b[i]);
}
}
int main(void)
{
std::cout << "Starting CUDA example... Array 10m entries" << std::endl;
std::cout << "Creating array" << std::endl;
const int number = 10000000;
float *testA;
float *testB;
float *outputC;
cudaMallocManaged(&testA, number * sizeof(float));
cudaMallocManaged(&testB, number * sizeof(float));
cudaMallocManaged(&outputC, number * sizeof(float));
// init<<<9766, 1024>>>(number, testA, testB);
init<<<9766, 1024>>>(number, testA, testB);
cudaDeviceSynchronize();
std::cout << "Completed array creation." << std::endl;
std::cout << "Calculating..." << std::endl;
auto time1 = std::chrono::high_resolution_clock::now();
mMultiply<<<9766, 1024>>>(number, testA, testB, outputC);
cudaDeviceSynchronize();
auto time2 = std::chrono::high_resolution_clock::now();
auto dur = std::chrono::duration_cast<std::chrono::microseconds>(time2 - time1).count();
std::cout << "[CUDA] Time taken: " << (dur / 1000.00) << "ms";
cudaFree(testA);
cudaFree(testB);
cudaFree(outputC);
return 0;
}
|
code for sm_80
Function : _Z9mMultiplyiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xa30 ; /* 0x000009f000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0203 */
/*0060*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fc80000000f00 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R3, R3, c[0x0][0xc], RZ ; /* 0x0000030003037a24 */
/* 0x000fd800078e02ff */
/*0090*/ @P0 BRA 0xa20 ; /* 0x0000098000000947 */
/* 0x000fea0003800000 */
/*00a0*/ I2F.U32.RP R2, R3 ; /* 0x0000000300027306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R9, RZ, -R3.reuse, RZ ; /* 0x80000003ff097210 */
/* 0x080fe20007ffe0ff */
/*00c0*/ IMAD.IADD R4, R3.reuse, 0x1, R0 ; /* 0x0000000103047824 */
/* 0x040fe200078e0200 */
/*00d0*/ IADD3 R11, RZ, -R3, RZ ; /* 0x80000003ff0b7210 */
/* 0x000fe20007ffe0ff */
/*00e0*/ BSSY B1, 0x4e0 ; /* 0x000003f000017945 */
/* 0x000fe20003800000 */
/*00f0*/ ISETP.NE.U32.AND P3, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720c */
/* 0x040fe40003f65070 */
/*0100*/ ISETP.NE.U32.AND P6, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003fc5070 */
/*0110*/ I2F.U32.RP R8, R3 ; /* 0x0000000300087306 */
/* 0x000e700000209000 */
/*0120*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e300000001000 */
/*0130*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e620000001000 */
/*0140*/ IADD3 R6, R2, 0xffffffe, RZ ; /* 0x0ffffffe02067810 */
/* 0x001fc40007ffe0ff */
/*0150*/ IADD3 R2, R3, R0, RZ ; /* 0x0000000003027210 */
/* 0x000fca0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0000a2000021f000 */
/*0170*/ LOP3.LUT R2, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff027212 */
/* 0x000fe400078e33ff */
/*0180*/ IADD3 R5, R8, 0xffffffe, RZ ; /* 0x0ffffffe08057810 */
/* 0x002fe40007ffe0ff */
/*0190*/ IADD3 R2, R2, c[0x0][0x160], R3 ; /* 0x0000580002027a10 */
/* 0x000fe20007ffe003 */
/*01a0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x001fc600000001ff */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e22000021f000 */
/*01c0*/ IMAD R9, R9, R7, RZ ; /* 0x0000000709097224 */
/* 0x004fcc00078e02ff */
/*01d0*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fe200078e0006 */
/*01e0*/ LOP3.LUT R6, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff067212 */
/* 0x000fe400078e33ff */
/*01f0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0200*/ IADD3 R6, R6, c[0x0][0x160], R3 ; /* 0x0000580006067a10 */
/* 0x000fe20007ffe003 */
/*0210*/ IMAD R9, R11, R5, RZ ; /* 0x000000050b097224 */
/* 0x001fe400078e02ff */
/*0220*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.HI.U32 R9, R5, R9, R4 ; /* 0x0000000905097227 */
/* 0x000fe200078e0004 */
/*0240*/ IADD3 R4, -R7, RZ, RZ ; /* 0x000000ff07047210 */
/* 0x000fca0007ffe1ff */
/*0250*/ IMAD R2, R3, R4, R2 ; /* 0x0000000403027224 */
/* 0x000fe400078e0202 */
/*0260*/ IMAD.HI.U32 R9, R9, R6, RZ ; /* 0x0000000609097227 */
/* 0x000fc600078e00ff */
/*0270*/ ISETP.GE.U32.AND P1, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe40003f26070 */
/*0280*/ IADD3 R5, -R9, RZ, RZ ; /* 0x000000ff09057210 */
/* 0x000fca0007ffe1ff */
/*0290*/ IMAD R6, R3, R5, R6 ; /* 0x0000000503067224 */
/* 0x000fca00078e0206 */
/*02a0*/ ISETP.GE.U32.AND P4, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe20003f86070 */
/*02b0*/ @P1 IMAD.IADD R2, R2, 0x1, -R3 ; /* 0x0000000102021824 */
/* 0x000fe200078e0a03 */
/*02c0*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fc80007ffe0ff */
/*02d0*/ ISETP.GE.U32.AND P2, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fce0003f46070 */
/*02e0*/ @P4 IADD3 R6, -R3, R6, RZ ; /* 0x0000000603064210 */
/* 0x000fe40007ffe1ff */
/*02f0*/ @P4 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109094810 */
/* 0x000fe40007ffe0ff */
/*0300*/ ISETP.GE.U32.AND P5, PT, R6, R3.reuse, PT ; /* 0x000000030600720c */
/* 0x080fe40003fa6070 */
/*0310*/ @P2 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107072810 */
/* 0x000fe40007ffe0ff */
/*0320*/ @!P3 LOP3.LUT R7, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff07b212 */
/* 0x000fc800078e33ff */
/*0330*/ IADD3 R2, R7.reuse, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x040fe40007ffe0ff */
/*0340*/ ISETP.GE.U32.AND P3, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f66070 */
/*0350*/ LOP3.LUT P2, R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe4000784c0ff */
/*0360*/ @P5 IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109095810 */
/* 0x000fe40007ffe0ff */
/*0370*/ @!P6 LOP3.LUT R9, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff09e212 */
/* 0x000fc800078e33ff */
/*0380*/ IADD3 R4, R9.reuse, 0x1, RZ ; /* 0x0000000109047810 */
/* 0x040fe40007ffe0ff */
/*0390*/ ISETP.GE.U32.AND P1, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fe40003f26070 */
/*03a0*/ LOP3.LUT P4, R2, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304027812 */
/* 0x000fe4000788c0ff */
/*03b0*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fe20000000f00 */
/*03c0*/ @!P2 BRA 0x4d0 ; /* 0x000001000000a947 */
/* 0x000fea0003800000 */
/*03d0*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe40000000f00 */
/*03e0*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fc60000000f00 */
/*03f0*/ IMAD.WIDE R6, R0, R11, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fc800078e020b */
/*0400*/ IMAD.WIDE R8, R0, R11, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fc800078e020b */
/*0410*/ IMAD.WIDE R10, R0, R11, c[0x0][0x168] ; /* 0x00005a00000a7625 */
/* 0x000fc800078e020b */
/*0420*/ LDG.E R12, [R8.64] ; /* 0x00000004080c7981 */
/* 0x0000a8000c1e1900 */
/*0430*/ LDG.E R13, [R10.64] ; /* 0x000000040a0d7981 */
/* 0x0002a2000c1e1900 */
/*0440*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*0450*/ IMAD.IADD R4, R3, 0x1, R4 ; /* 0x0000000103047824 */
/* 0x000fc600078e0204 */
/*0460*/ ISETP.NE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f45270 */
/*0470*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x001fc800078e0208 */
/*0480*/ IMAD.WIDE R10, R3, 0x4, R10 ; /* 0x00000004030a7825 */
/* 0x002fc800078e020a */
/*0490*/ FMUL R13, R12, R13 ; /* 0x0000000d0c0d7220 */
/* 0x004fca0000400000 */
/*04a0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e4000c101904 */
/*04b0*/ IMAD.WIDE R6, R3, 0x4, R6 ; /* 0x0000000403067825 */
/* 0x001fe200078e0206 */
/*04c0*/ @P2 BRA 0x420 ; /* 0xffffff5000002947 */
/* 0x000fea000383ffff */
/*04d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04e0*/ BSSY B1, 0x720 ; /* 0x0000023000017945 */
/* 0x000fe20003800000 */
/*04f0*/ @!P3 BRA 0x710 ; /* 0x000002100000b947 */
/* 0x000fea0003800000 */
/*0500*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fd400000001ff */
/*0510*/ IMAD.WIDE R8, R4, R11, c[0x0][0x170] ; /* 0x00005c0004087625 */
/* 0x000fc800078e020b */
/*0520*/ IMAD.WIDE R6, R4.reuse, R11.reuse, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x0c0fe200078e020b */
/*0530*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x002ea8000c1e1900 */
/*0540*/ LDG.E R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IMAD.WIDE R10, R4, R11, c[0x0][0x178] ; /* 0x00005e00040a7625 */
/* 0x000fc800078e020b */
/*0560*/ IMAD.WIDE R14, R3, 0x4, R8 ; /* 0x00000004030e7825 */
/* 0x000fc800078e0208 */
/*0570*/ FMUL R5, R5, R12 ; /* 0x0000000c05057220 */
/* 0x004fe40000400000 */
/*0580*/ IMAD.WIDE R12, R3, 0x4, R6 ; /* 0x00000004030c7825 */
/* 0x000fc600078e0206 */
/*0590*/ STG.E [R10.64], R5 ; /* 0x000000050a007986 */
/* 0x0001e8000c101904 */
/*05a0*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ea8000c1e1900 */
/*05b0*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IMAD.WIDE R16, R3, 0x4, R10 ; /* 0x0000000403107825 */
/* 0x000fc800078e020a */
/*05d0*/ IMAD.WIDE R8, R3, 0x4, R14 ; /* 0x0000000403087825 */
/* 0x000fc800078e020e */
/*05e0*/ IMAD.WIDE R6, R3, 0x4, R12 ; /* 0x0000000403067825 */
/* 0x000fc800078e020c */
/*05f0*/ FMUL R21, R18, R19 ; /* 0x0000001312157220 */
/* 0x004fca0000400000 */
/*0600*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0003e8000c101904 */
/*0610*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0620*/ LDG.E R23, [R6.64] ; /* 0x0000000406177981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IMAD.WIDE R18, R3, 0x4, R16 ; /* 0x0000000403127825 */
/* 0x000fc800078e0210 */
/*0640*/ IMAD.WIDE R14, R3, 0x4, R8 ; /* 0x00000004030e7825 */
/* 0x000fc800078e0208 */
/*0650*/ IMAD.WIDE R10, R3, 0x4, R6 ; /* 0x00000004030a7825 */
/* 0x001fc800078e0206 */
/*0660*/ FMUL R23, R20, R23 ; /* 0x0000001714177220 */
/* 0x004fca0000400000 */
/*0670*/ STG.E [R18.64], R23 ; /* 0x0000001712007986 */
/* 0x0003e8000c101904 */
/*0680*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1900 */
/*06a0*/ IMAD.WIDE R12, R3.reuse, 0x4, R18 ; /* 0x00000004030c7825 */
/* 0x040fe200078e0212 */
/*06b0*/ IADD3 R4, R3, R4, R3 ; /* 0x0000000403047210 */
/* 0x000fc80007ffe003 */
/*06c0*/ IADD3 R4, R3, R4, R3 ; /* 0x0000000403047210 */
/* 0x000fc80007ffe003 */
/*06d0*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fe20003f46270 */
/*06e0*/ FMUL R5, R14, R11 ; /* 0x0000000b0e057220 */
/* 0x004fca0000400000 */
/*06f0*/ STG.E [R12.64], R5 ; /* 0x000000050c007986 */
/* 0x0003ee000c101904 */
/*0700*/ @!P2 BRA 0x500 ; /* 0xfffffdf00000a947 */
/* 0x000fea000383ffff */
/*0710*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0720*/ BSSY B1, 0x840 ; /* 0x0000011000017945 */
/* 0x000fe20003800000 */
/*0730*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fe20000000f00 */
/*0740*/ @!P4 BRA 0x830 ; /* 0x000000e00000c947 */
/* 0x000fea0003800000 */
/*0750*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0760*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fd20000000f00 */
/*0770*/ IMAD.WIDE R6, R0, R9, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e0209 */
/*0780*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc800078e0209 */
/*0790*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x0020a8000c1e1900 */
/*07a0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ IMAD.IADD R4, R3, 0x1, R4 ; /* 0x0000000103047824 */
/* 0x000fc600078e0204 */
/*07d0*/ ISETP.NE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f45270 */
/*07e0*/ IMAD.WIDE R6, R3, 0x4, R6 ; /* 0x0000000403067825 */
/* 0x001fc800078e0206 */
/*07f0*/ FMUL R5, R5, R10 ; /* 0x0000000a05057220 */
/* 0x004fca0000400000 */
/*0800*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x0001e4000c101904 */
/*0810*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x001fe200078e0208 */
/*0820*/ @P2 BRA 0x790 ; /* 0xffffff6000002947 */
/* 0x000fea000383ffff */
/*0830*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0840*/ @!P1 BRA 0xa20 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*0850*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fd400000001ff */
/*0860*/ IMAD.WIDE R6, R4, R9, c[0x0][0x178] ; /* 0x00005e0004067625 */
/* 0x002fc800078e0209 */
/*0870*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fe200078e0209 */
/*0880*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x002ea8000c1e1900 */
/*0890*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000ea2000c1e1900 */
/*08a0*/ IMAD.WIDE R12, R3, 0x4, R8 ; /* 0x00000004030c7825 */
/* 0x000fc800078e0208 */
/*08b0*/ IMAD.WIDE R10, R3, 0x4, R6 ; /* 0x00000004030a7825 */
/* 0x000fc800078e0206 */
/*08c0*/ FMUL R5, R2, R5 ; /* 0x0000000502057220 */
/* 0x004fca0000400000 */
/*08d0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0001e8000c101904 */
/*08e0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*08f0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000ea2000c1e1900 */
/*0900*/ IMAD.WIDE R16, R3, 0x4, R12 ; /* 0x0000000403107825 */
/* 0x000fc800078e020c */
/*0910*/ FMUL R19, R2, R15 ; /* 0x0000000f02137220 */
/* 0x004fe40000400000 */
/*0920*/ IMAD.WIDE R14, R3, 0x4, R10 ; /* 0x00000004030e7825 */
/* 0x000fc600078e020a */
/*0930*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0940*/ LDG.E R2, [R16.64] ; /* 0x0000000410027981 */
/* 0x000ea8000c1e1900 */
/*0950*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x000ea2000c1e1900 */
/*0960*/ IMAD.WIDE R6, R3, 0x4, R14 ; /* 0x0000000403067825 */
/* 0x001fc800078e020e */
/*0970*/ FMUL R21, R2, R9 ; /* 0x0000000902157220 */
/* 0x004fe40000400000 */
/*0980*/ IMAD.WIDE R8, R3, 0x4, R16 ; /* 0x0000000403087825 */
/* 0x000fc600078e0210 */
/*0990*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*09a0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x000ea2000c1e1900 */
/*09c0*/ IADD3 R4, R3, R4, R3 ; /* 0x0000000403047210 */
/* 0x000fc80007ffe003 */
/*09d0*/ IADD3 R4, R3, R4, R3 ; /* 0x0000000403047210 */
/* 0x000fc80007ffe003 */
/*09e0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fe20003f26270 */
/*09f0*/ FMUL R5, R8, R5 ; /* 0x0000000508057220 */
/* 0x004fca0000400000 */
/*0a00*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0003ee000c101904 */
/*0a10*/ @!P1 BRA 0x850 ; /* 0xfffffe3000009947 */
/* 0x000fea000383ffff */
/*0a20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a30*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0a40*/ I2F.U32.RP R6, R3 ; /* 0x0000000300067306 */
/* 0x002e220000209000 */
/*0a50*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x000fe20007ffe0ff */
/*0a60*/ BSSY B0, 0xcc0 ; /* 0x0000025000007945 */
/* 0x000fe20003800000 */
/*0a70*/ IADD3 R2, R3, R0, RZ ; /* 0x0000000003027210 */
/* 0x000fc40007ffe0ff */
/*0a80*/ ISETP.NE.U32.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f45070 */
/*0a90*/ LOP3.LUT R2, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff027212 */
/* 0x000fc800078e33ff */
/*0aa0*/ IADD3 R2, R2, c[0x0][0x160], R3 ; /* 0x0000580002027a10 */
/* 0x000fe20007ffe003 */
/*0ab0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0ac0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0ad0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0ae0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x001fe20000000f00 */
/*0af0*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*0b00*/ IMAD.HI.U32 R7, R5, R7, R4 ; /* 0x0000000705077227 */
/* 0x000fcc00078e0004 */
/*0b10*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x000fc800078e00ff */
/*0b20*/ IMAD.MOV R5, RZ, RZ, -R7 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a07 */
/*0b30*/ IMAD R2, R3, R5, R2 ; /* 0x0000000503027224 */
/* 0x000fca00078e0202 */
/*0b40*/ ISETP.GE.U32.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f06070 */
/*0b50*/ @P0 IADD3 R2, -R3, R2, RZ ; /* 0x0000000203020210 */
/* 0x000fe40007ffe1ff */
/*0b60*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*0b70*/ ISETP.GE.U32.AND P1, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f26070 */
/*0b80*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0b90*/ @!P2 LOP3.LUT R7, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff07a212 */
/* 0x000fc800078e33ff */
/*0ba0*/ IADD3 R2, R7.reuse, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x040fe40007ffe0ff */
/*0bb0*/ ISETP.GE.U32.AND P1, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f26070 */
/*0bc0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0bd0*/ @!P0 BRA 0xcb0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0be0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fd400000001ff */
/*0bf0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*0c00*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fc800078e0207 */
/*0c10*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0000a8000c1e1900 */
/*0c20*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea2000c1e1900 */
/*0c30*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0c40*/ IADD3 R0, R3.reuse, R0, RZ ; /* 0x0000000003007210 */
/* 0x040fe40007ffe0ff */
/*0c50*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0c60*/ IMAD.WIDE R4, R3, 0x4, R4 ; /* 0x0000000403047825 */
/* 0x001fc800078e0204 */
/*0c70*/ FMUL R9, R8, R9 ; /* 0x0000000908097220 */
/* 0x004fca0000400000 */
/*0c80*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e4000c101904 */
/*0c90*/ IMAD.WIDE R6, R3, 0x4, R6 ; /* 0x0000000403067825 */
/* 0x001fe200078e0206 */
/*0ca0*/ @P0 BRA 0xc10 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0cb0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0cc0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0cd0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fca0000000f00 */
/*0ce0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x002fc800078e0207 */
/*0cf0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0d00*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0d10*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0d20*/ IMAD.WIDE R10, R3, 0x4, R6 ; /* 0x00000004030a7825 */
/* 0x000fc800078e0206 */
/*0d30*/ FMUL R17, R2, R9 ; /* 0x0000000902117220 */
/* 0x004fe40000400000 */
/*0d40*/ IMAD.WIDE R8, R3, 0x4, R4 ; /* 0x0000000403087825 */
/* 0x000fc600078e0204 */
/*0d50*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x0001e8000c101904 */
/*0d60*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*0d70*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*0d80*/ IMAD.WIDE R14, R3, 0x4, R10 ; /* 0x00000004030e7825 */
/* 0x000fc800078e020a */
/*0d90*/ FMUL R19, R2, R13 ; /* 0x0000000d02137220 */
/* 0x004fe40000400000 */
/*0da0*/ IMAD.WIDE R12, R3, 0x4, R8 ; /* 0x00000004030c7825 */
/* 0x000fc600078e0208 */
/*0db0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0003e8000c101904 */
/*0dc0*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*0dd0*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x000ea2000c1e1900 */
/*0de0*/ IMAD.WIDE R4, R3, 0x4, R12 ; /* 0x0000000403047825 */
/* 0x001fc800078e020c */
/*0df0*/ FMUL R21, R2, R7 ; /* 0x0000000702157220 */
/* 0x004fe40000400000 */
/*0e00*/ IMAD.WIDE R6, R3, 0x4, R14 ; /* 0x0000000403067825 */
/* 0x000fc600078e020e */
/*0e10*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0003e8000c101904 */
/*0e20*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0e30*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0e40*/ IADD3 R0, R3, R0, R3 ; /* 0x0000000003007210 */
/* 0x000fc80007ffe003 */
/*0e50*/ IADD3 R0, R3, R0, R3 ; /* 0x0000000003007210 */
/* 0x000fc80007ffe003 */
/*0e60*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*0e70*/ FMUL R11, R6, R11 ; /* 0x0000000b060b7220 */
/* 0x004fca0000400000 */
/*0e80*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0003ee000c101904 */
/*0e90*/ @!P0 BRA 0xcd0 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0ea0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0eb0*/ BRA 0xeb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4initiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0250*/ MOV R9, 0x4015e83e ; /* 0x4015e83e00097802 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fb5f06f ; /* 0x3fb5f06fff0b7424 */
/* 0x000fce00078e00ff */
/*0270*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0280*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c101904 */
/*02b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0003e2000c101904 */
/*02e0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x002fce00078e0204 */
/*0300*/ @P0 BRA 0x290 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R21, -RZ, RZ, 2.041015625, -2172 ; /* 0x4015e83eff157435 */
/* 0x000fe200000001ff */
/*0340*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0350*/ IMAD.MOV.U32 R23, RZ, RZ, 0x3fb5f06f ; /* 0x3fb5f06fff177424 */
/* 0x000fe400078e00ff */
/*0360*/ IMAD.WIDE R4, R3, R2, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x001fc800078e0202 */
/*0370*/ IMAD.WIDE R6, R3, R2, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fe200078e0202 */
/*0380*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0001e2000c101904 */
/*0390*/ IADD3 R3, R0.reuse, R3, R0 ; /* 0x0000000300037210 */
/* 0x040fe40007ffe000 */
/*03a0*/ IMAD.WIDE R8, R0.reuse, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x040fe200078e0204 */
/*03b0*/ STG.E [R6.64], R23 ; /* 0x0000001706007986 */
/* 0x0001e2000c101904 */
/*03c0*/ IADD3 R3, R0.reuse, R3, R0 ; /* 0x0000000300037210 */
/* 0x040fe40007ffe000 */
/*03d0*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0206 */
/*03e0*/ STG.E [R8.64], R21 ; /* 0x0000001508007986 */
/* 0x0001e2000c101904 */
/*03f0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fc40003f06270 */
/*0400*/ IMAD.WIDE R12, R0.reuse, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x040fe200078e0208 */
/*0410*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0001e6000c101904 */
/*0420*/ IMAD.WIDE R14, R0.reuse, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020a */
/*0430*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0001e6000c101904 */
/*0440*/ IMAD.WIDE R16, R0.reuse, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x040fe200078e020c */
/*0450*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0001e6000c101904 */
/*0460*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fe200078e020e */
/*0470*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0001e8000c101904 */
/*0480*/ STG.E [R18.64], R23 ; /* 0x0000001712007986 */
/* 0x0001e2000c101904 */
/*0490*/ @!P0 BRA 0x360 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include <math.h>
#include <chrono>
__global__ void init(int length, float *a, float *b)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < length; i += stride)
{
a[i] = 2.3423;
b[i] = 1.4214;
}
}
__global__ void mMultiply(int length, float *a, float *b, float *output)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < length; i += stride)
{
output[i] = (a[i] * b[i]);
}
for (int i = index; i < length; i += stride)
{
output[i] = (output[i] * a[i]);
}
for (int i = index; i < length; i += stride)
{
output[i] = (output[i] * b[i]);
}
}
int main(void)
{
std::cout << "Starting CUDA example... Array 10m entries" << std::endl;
std::cout << "Creating array" << std::endl;
const int number = 10000000;
float *testA;
float *testB;
float *outputC;
cudaMallocManaged(&testA, number * sizeof(float));
cudaMallocManaged(&testB, number * sizeof(float));
cudaMallocManaged(&outputC, number * sizeof(float));
// init<<<9766, 1024>>>(number, testA, testB);
init<<<9766, 1024>>>(number, testA, testB);
cudaDeviceSynchronize();
std::cout << "Completed array creation." << std::endl;
std::cout << "Calculating..." << std::endl;
auto time1 = std::chrono::high_resolution_clock::now();
mMultiply<<<9766, 1024>>>(number, testA, testB, outputC);
cudaDeviceSynchronize();
auto time2 = std::chrono::high_resolution_clock::now();
auto dur = std::chrono::duration_cast<std::chrono::microseconds>(time2 - time1).count();
std::cout << "[CUDA] Time taken: " << (dur / 1000.00) << "ms";
cudaFree(testA);
cudaFree(testB);
cudaFree(outputC);
return 0;
}
|
.file "tmpxft_0006cfaa_00000000-6_Array10m.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3773:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3773:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4initiPfS_iPfS_
.type _Z26__device_stub__Z4initiPfS_iPfS_, @function
_Z26__device_stub__Z4initiPfS_iPfS_:
.LFB3795:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4initiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3795:
.size _Z26__device_stub__Z4initiPfS_iPfS_, .-_Z26__device_stub__Z4initiPfS_iPfS_
.globl _Z4initiPfS_
.type _Z4initiPfS_, @function
_Z4initiPfS_:
.LFB3796:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4initiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3796:
.size _Z4initiPfS_, .-_Z4initiPfS_
.globl _Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_
.type _Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_, @function
_Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_:
.LFB3797:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9mMultiplyiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3797:
.size _Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_, .-_Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_
.globl _Z9mMultiplyiPfS_S_
.type _Z9mMultiplyiPfS_S_, @function
_Z9mMultiplyiPfS_S_:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _Z9mMultiplyiPfS_S_, .-_Z9mMultiplyiPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Starting CUDA example... Array 10m entries"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Creating array"
.LC2:
.string "Completed array creation."
.LC3:
.string "Calculating..."
.LC4:
.string "[CUDA] Time taken: "
.LC6:
.string "ms"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $9766, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $9766, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rbx
subq %rcx, %rbx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC5(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $10000000, %edi
call _Z26__device_stub__Z4initiPfS_iPfS_
jmp .L20
.L25:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $10000000, %edi
call _Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9mMultiplyiPfS_S_"
.LC8:
.string "_Z4initiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3800:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mMultiplyiPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initiPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <math.h>
#include <chrono>
__global__ void init(int length, float *a, float *b)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < length; i += stride)
{
a[i] = 2.3423;
b[i] = 1.4214;
}
}
__global__ void mMultiply(int length, float *a, float *b, float *output)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < length; i += stride)
{
output[i] = (a[i] * b[i]);
}
for (int i = index; i < length; i += stride)
{
output[i] = (output[i] * a[i]);
}
for (int i = index; i < length; i += stride)
{
output[i] = (output[i] * b[i]);
}
}
int main(void)
{
std::cout << "Starting CUDA example... Array 10m entries" << std::endl;
std::cout << "Creating array" << std::endl;
const int number = 10000000;
float *testA;
float *testB;
float *outputC;
cudaMallocManaged(&testA, number * sizeof(float));
cudaMallocManaged(&testB, number * sizeof(float));
cudaMallocManaged(&outputC, number * sizeof(float));
// init<<<9766, 1024>>>(number, testA, testB);
init<<<9766, 1024>>>(number, testA, testB);
cudaDeviceSynchronize();
std::cout << "Completed array creation." << std::endl;
std::cout << "Calculating..." << std::endl;
auto time1 = std::chrono::high_resolution_clock::now();
mMultiply<<<9766, 1024>>>(number, testA, testB, outputC);
cudaDeviceSynchronize();
auto time2 = std::chrono::high_resolution_clock::now();
auto dur = std::chrono::duration_cast<std::chrono::microseconds>(time2 - time1).count();
std::cout << "[CUDA] Time taken: " << (dur / 1000.00) << "ms";
cudaFree(testA);
cudaFree(testB);
cudaFree(outputC);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <chrono>
__global__ void init(int length, float *a, float *b)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < length; i += stride)
{
a[i] = 2.3423;
b[i] = 1.4214;
}
}
__global__ void mMultiply(int length, float *a, float *b, float *output)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < length; i += stride)
{
output[i] = (a[i] * b[i]);
}
for (int i = index; i < length; i += stride)
{
output[i] = (output[i] * a[i]);
}
for (int i = index; i < length; i += stride)
{
output[i] = (output[i] * b[i]);
}
}
int main(void)
{
std::cout << "Starting CUDA example... Array 10m entries" << std::endl;
std::cout << "Creating array" << std::endl;
const int number = 10000000;
float *testA;
float *testB;
float *outputC;
hipMallocManaged(&testA, number * sizeof(float));
hipMallocManaged(&testB, number * sizeof(float));
hipMallocManaged(&outputC, number * sizeof(float));
// init<<<9766, 1024>>>(number, testA, testB);
init<<<9766, 1024>>>(number, testA, testB);
hipDeviceSynchronize();
std::cout << "Completed array creation." << std::endl;
std::cout << "Calculating..." << std::endl;
auto time1 = std::chrono::high_resolution_clock::now();
mMultiply<<<9766, 1024>>>(number, testA, testB, outputC);
hipDeviceSynchronize();
auto time2 = std::chrono::high_resolution_clock::now();
auto dur = std::chrono::duration_cast<std::chrono::microseconds>(time2 - time1).count();
std::cout << "[CUDA] Time taken: " << (dur / 1000.00) << "ms";
hipFree(testA);
hipFree(testB);
hipFree(outputC);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <chrono>
__global__ void init(int length, float *a, float *b)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < length; i += stride)
{
a[i] = 2.3423;
b[i] = 1.4214;
}
}
__global__ void mMultiply(int length, float *a, float *b, float *output)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < length; i += stride)
{
output[i] = (a[i] * b[i]);
}
for (int i = index; i < length; i += stride)
{
output[i] = (output[i] * a[i]);
}
for (int i = index; i < length; i += stride)
{
output[i] = (output[i] * b[i]);
}
}
int main(void)
{
std::cout << "Starting CUDA example... Array 10m entries" << std::endl;
std::cout << "Creating array" << std::endl;
const int number = 10000000;
float *testA;
float *testB;
float *outputC;
hipMallocManaged(&testA, number * sizeof(float));
hipMallocManaged(&testB, number * sizeof(float));
hipMallocManaged(&outputC, number * sizeof(float));
// init<<<9766, 1024>>>(number, testA, testB);
init<<<9766, 1024>>>(number, testA, testB);
hipDeviceSynchronize();
std::cout << "Completed array creation." << std::endl;
std::cout << "Calculating..." << std::endl;
auto time1 = std::chrono::high_resolution_clock::now();
mMultiply<<<9766, 1024>>>(number, testA, testB, outputC);
hipDeviceSynchronize();
auto time2 = std::chrono::high_resolution_clock::now();
auto dur = std::chrono::duration_cast<std::chrono::microseconds>(time2 - time1).count();
std::cout << "[CUDA] Time taken: " << (dur / 1000.00) << "ms";
hipFree(testA);
hipFree(testB);
hipFree(outputC);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4initiPfS_
.globl _Z4initiPfS_
.p2align 8
.type _Z4initiPfS_,@function
_Z4initiPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0x4015e83e
v_mov_b32_e32 v4, 0x3fb5f06f
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s10, v1
v_add_co_u32 v2, s0, v2, s8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s1, vcc_lo, s1
global_store_b32 v[5:6], v0, off
global_store_b32 v[7:8], v4, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4initiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4initiPfS_, .Lfunc_end0-_Z4initiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9mMultiplyiPfS_S_
.globl _Z9mMultiplyiPfS_S_
.p2align 8
.type _Z9mMultiplyiPfS_S_,@function
_Z9mMultiplyiPfS_S_:
s_clause 0x4
s_load_b32 s8, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x0
s_load_b32 s9, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mul_i32 s8, s9, s0
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB1_3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, v1
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[10:11], s[8:9], 2
s_mov_b32 s9, 0
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
global_load_b32 v9, v[5:6], off
global_load_b32 v7, v[7:8], off
v_add_nc_u32_e32 v0, s8, v0
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s10
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, v9, v7
v_cmp_le_i32_e64 s0, s12, v0
global_store_b32 v[5:6], v7, off
s_or_b32 s9, s0, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s1, exec_lo
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB1_6
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, v1
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
s_mov_b32 s9, 0
.p2align 6
.LBB1_5:
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s10
global_load_b32 v9, v[5:6], off
global_load_b32 v7, v[7:8], off
v_add_nc_u32_e32 v0, s8, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v7, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s12, v0
global_store_b32 v[5:6], v7, off
s_or_b32 s9, s0, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB1_5
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB1_9
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_ashr_i32 s9, s8, 31
s_mov_b32 s1, 0
s_lshl_b64 s[4:5], s[8:9], 2
.p2align 6
.LBB1_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s4
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v0, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_8
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9mMultiplyiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9mMultiplyiPfS_S_, .Lfunc_end1-_Z9mMultiplyiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4initiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4initiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9mMultiplyiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9mMultiplyiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <chrono>
__global__ void init(int length, float *a, float *b)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < length; i += stride)
{
a[i] = 2.3423;
b[i] = 1.4214;
}
}
__global__ void mMultiply(int length, float *a, float *b, float *output)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < length; i += stride)
{
output[i] = (a[i] * b[i]);
}
for (int i = index; i < length; i += stride)
{
output[i] = (output[i] * a[i]);
}
for (int i = index; i < length; i += stride)
{
output[i] = (output[i] * b[i]);
}
}
int main(void)
{
std::cout << "Starting CUDA example... Array 10m entries" << std::endl;
std::cout << "Creating array" << std::endl;
const int number = 10000000;
float *testA;
float *testB;
float *outputC;
hipMallocManaged(&testA, number * sizeof(float));
hipMallocManaged(&testB, number * sizeof(float));
hipMallocManaged(&outputC, number * sizeof(float));
// init<<<9766, 1024>>>(number, testA, testB);
init<<<9766, 1024>>>(number, testA, testB);
hipDeviceSynchronize();
std::cout << "Completed array creation." << std::endl;
std::cout << "Calculating..." << std::endl;
auto time1 = std::chrono::high_resolution_clock::now();
mMultiply<<<9766, 1024>>>(number, testA, testB, outputC);
hipDeviceSynchronize();
auto time2 = std::chrono::high_resolution_clock::now();
auto dur = std::chrono::duration_cast<std::chrono::microseconds>(time2 - time1).count();
std::cout << "[CUDA] Time taken: " << (dur / 1000.00) << "ms";
hipFree(testA);
hipFree(testB);
hipFree(outputC);
return 0;
}
|
.text
.file "Array10m.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__initiPfS_ # -- Begin function _Z19__device_stub__initiPfS_
.p2align 4, 0x90
.type _Z19__device_stub__initiPfS_,@function
_Z19__device_stub__initiPfS_: # @_Z19__device_stub__initiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4initiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__initiPfS_, .Lfunc_end0-_Z19__device_stub__initiPfS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__mMultiplyiPfS_S_ # -- Begin function _Z24__device_stub__mMultiplyiPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__mMultiplyiPfS_S_,@function
_Z24__device_stub__mMultiplyiPfS_S_: # @_Z24__device_stub__mMultiplyiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9mMultiplyiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__mMultiplyiPfS_S_, .Lfunc_end1-_Z24__device_stub__mMultiplyiPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $42, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB2_4
.LBB2_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
cmpb $0, 56(%rbx)
je .LBB2_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB2_8
.LBB2_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
movabsq $4294968320, %rbx # imm = 0x100000400
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 16(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
leaq 104(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
leaq 8742(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $10000000, 24(%rsp) # imm = 0x989680
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z4initiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_21
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
cmpb $0, 56(%r14)
je .LBB2_13
# %bb.12:
movzbl 67(%r14), %eax
jmp .LBB2_14
.LBB2_13:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_21
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
cmpb $0, 56(%r14)
je .LBB2_17
# %bb.16:
movzbl 67(%r14), %eax
jmp .LBB2_18
.LBB2_17:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
leaq 8742(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_20
# %bb.19:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 104(%rsp), %rdx
movl $10000000, 100(%rsp) # imm = 0x989680
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 100(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9mMultiplyiPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_20:
callq hipDeviceSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rbx
movq %rdx, %rax
shrq $63, %rax
sarq $7, %rbx
addq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2sd %rbx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_21:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mMultiplyiPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initiPfS_,@object # @_Z4initiPfS_
.section .rodata,"a",@progbits
.globl _Z4initiPfS_
.p2align 3, 0x0
_Z4initiPfS_:
.quad _Z19__device_stub__initiPfS_
.size _Z4initiPfS_, 8
.type _Z9mMultiplyiPfS_S_,@object # @_Z9mMultiplyiPfS_S_
.globl _Z9mMultiplyiPfS_S_
.p2align 3, 0x0
_Z9mMultiplyiPfS_S_:
.quad _Z24__device_stub__mMultiplyiPfS_S_
.size _Z9mMultiplyiPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Starting CUDA example... Array 10m entries"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Creating array"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Completed array creation."
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Calculating..."
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[CUDA] Time taken: "
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ms"
.size .L.str.5, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initiPfS_"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9mMultiplyiPfS_S_"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initiPfS_
.addrsig_sym _Z24__device_stub__mMultiplyiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initiPfS_
.addrsig_sym _Z9mMultiplyiPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0006cfaa_00000000-6_Array10m.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3773:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3773:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4initiPfS_iPfS_
.type _Z26__device_stub__Z4initiPfS_iPfS_, @function
_Z26__device_stub__Z4initiPfS_iPfS_:
.LFB3795:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4initiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3795:
.size _Z26__device_stub__Z4initiPfS_iPfS_, .-_Z26__device_stub__Z4initiPfS_iPfS_
.globl _Z4initiPfS_
.type _Z4initiPfS_, @function
_Z4initiPfS_:
.LFB3796:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4initiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3796:
.size _Z4initiPfS_, .-_Z4initiPfS_
.globl _Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_
.type _Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_, @function
_Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_:
.LFB3797:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9mMultiplyiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3797:
.size _Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_, .-_Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_
.globl _Z9mMultiplyiPfS_S_
.type _Z9mMultiplyiPfS_S_, @function
_Z9mMultiplyiPfS_S_:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _Z9mMultiplyiPfS_S_, .-_Z9mMultiplyiPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Starting CUDA example... Array 10m entries"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Creating array"
.LC2:
.string "Completed array creation."
.LC3:
.string "Calculating..."
.LC4:
.string "[CUDA] Time taken: "
.LC6:
.string "ms"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $9766, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $9766, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rbx
subq %rcx, %rbx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC5(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $10000000, %edi
call _Z26__device_stub__Z4initiPfS_iPfS_
jmp .L20
.L25:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $10000000, %edi
call _Z33__device_stub__Z9mMultiplyiPfS_S_iPfS_S_
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9mMultiplyiPfS_S_"
.LC8:
.string "_Z4initiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3800:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mMultiplyiPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initiPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "Array10m.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__initiPfS_ # -- Begin function _Z19__device_stub__initiPfS_
.p2align 4, 0x90
.type _Z19__device_stub__initiPfS_,@function
_Z19__device_stub__initiPfS_: # @_Z19__device_stub__initiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4initiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__initiPfS_, .Lfunc_end0-_Z19__device_stub__initiPfS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__mMultiplyiPfS_S_ # -- Begin function _Z24__device_stub__mMultiplyiPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__mMultiplyiPfS_S_,@function
_Z24__device_stub__mMultiplyiPfS_S_: # @_Z24__device_stub__mMultiplyiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9mMultiplyiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__mMultiplyiPfS_S_, .Lfunc_end1-_Z24__device_stub__mMultiplyiPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $42, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB2_4
.LBB2_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
cmpb $0, 56(%rbx)
je .LBB2_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB2_8
.LBB2_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
movabsq $4294968320, %rbx # imm = 0x100000400
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 16(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
leaq 104(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
leaq 8742(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $10000000, 24(%rsp) # imm = 0x989680
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z4initiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_21
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
cmpb $0, 56(%r14)
je .LBB2_13
# %bb.12:
movzbl 67(%r14), %eax
jmp .LBB2_14
.LBB2_13:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_21
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
cmpb $0, 56(%r14)
je .LBB2_17
# %bb.16:
movzbl 67(%r14), %eax
jmp .LBB2_18
.LBB2_17:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
leaq 8742(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_20
# %bb.19:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 104(%rsp), %rdx
movl $10000000, 100(%rsp) # imm = 0x989680
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 100(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9mMultiplyiPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_20:
callq hipDeviceSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rbx
movq %rdx, %rax
shrq $63, %rax
sarq $7, %rbx
addq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2sd %rbx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_21:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mMultiplyiPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initiPfS_,@object # @_Z4initiPfS_
.section .rodata,"a",@progbits
.globl _Z4initiPfS_
.p2align 3, 0x0
_Z4initiPfS_:
.quad _Z19__device_stub__initiPfS_
.size _Z4initiPfS_, 8
.type _Z9mMultiplyiPfS_S_,@object # @_Z9mMultiplyiPfS_S_
.globl _Z9mMultiplyiPfS_S_
.p2align 3, 0x0
_Z9mMultiplyiPfS_S_:
.quad _Z24__device_stub__mMultiplyiPfS_S_
.size _Z9mMultiplyiPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Starting CUDA example... Array 10m entries"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Creating array"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Completed array creation."
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Calculating..."
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[CUDA] Time taken: "
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ms"
.size .L.str.5, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initiPfS_"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9mMultiplyiPfS_S_"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initiPfS_
.addrsig_sym _Z24__device_stub__mMultiplyiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initiPfS_
.addrsig_sym _Z9mMultiplyiPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void vecAdd (int *a, int *b, int *c)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < N){
c[index] = a[index] + b[index];
}
}
|
code for sm_80
Function : _Z6vecAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x4af, PT ; /* 0x000004af0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void vecAdd (int *a, int *b, int *c)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < N){
c[index] = a[index] + b[index];
}
}
|
.file "tmpxft_001ade97_00000000-6_vecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.type _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6vecAddPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, .-_Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.globl _Z6vecAddPiS_S_
.type _Z6vecAddPiS_S_, @function
_Z6vecAddPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecAddPiS_S_, .-_Z6vecAddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void vecAdd (int *a, int *b, int *c)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < N){
c[index] = a[index] + b[index];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecAdd (int *a, int *b, int *c)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < N){
c[index] = a[index] + b[index];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecAdd (int *a, int *b, int *c)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < N){
c[index] = a[index] + b[index];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPiS_S_
.globl _Z6vecAddPiS_S_
.p2align 8
.type _Z6vecAddPiS_S_,@function
_Z6vecAddPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x4b0, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPiS_S_, .Lfunc_end0-_Z6vecAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecAdd (int *a, int *b, int *c)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < N){
c[index] = a[index] + b[index];
}
}
|
.text
.file "vecAdd.hip"
.globl _Z21__device_stub__vecAddPiS_S_ # -- Begin function _Z21__device_stub__vecAddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPiS_S_,@function
_Z21__device_stub__vecAddPiS_S_: # @_Z21__device_stub__vecAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPiS_S_, .Lfunc_end0-_Z21__device_stub__vecAddPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPiS_S_,@object # @_Z6vecAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPiS_S_
.p2align 3, 0x0
_Z6vecAddPiS_S_:
.quad _Z21__device_stub__vecAddPiS_S_
.size _Z6vecAddPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecAddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z6vecAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x4af, PT ; /* 0x000004af0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPiS_S_
.globl _Z6vecAddPiS_S_
.p2align 8
.type _Z6vecAddPiS_S_,@function
_Z6vecAddPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x4b0, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPiS_S_, .Lfunc_end0-_Z6vecAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001ade97_00000000-6_vecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.type _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6vecAddPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, .-_Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.globl _Z6vecAddPiS_S_
.type _Z6vecAddPiS_S_, @function
_Z6vecAddPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecAddPiS_S_, .-_Z6vecAddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "vecAdd.hip"
.globl _Z21__device_stub__vecAddPiS_S_ # -- Begin function _Z21__device_stub__vecAddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPiS_S_,@function
_Z21__device_stub__vecAddPiS_S_: # @_Z21__device_stub__vecAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPiS_S_, .Lfunc_end0-_Z21__device_stub__vecAddPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPiS_S_,@object # @_Z6vecAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPiS_S_
.p2align 3, 0x0
_Z6vecAddPiS_S_:
.quad _Z21__device_stub__vecAddPiS_S_
.size _Z6vecAddPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecAddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
//M and N number of threads (grid and block)
void secuential(const int a[] ,const int b[], unsigned long int c[], const int sqrt_dim);
__global__ void multiply( const int a[] ,const int b[], unsigned long int c[] , const int sqrt_dim,const int thread_number)
{
unsigned long int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
unsigned long int index = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x) + threadIdx.x;
//convert global index to column and row (index_i and index_j) of matrix
unsigned long int index_i = index < sqrt_dim ? index : (int)index%sqrt_dim;
unsigned long int index_j = (index-index_i)/sqrt_dim;
unsigned int dim=sqrt_dim*sqrt_dim;
//printf("index= %i \t", index);
if(index<dim){
c[index]=0;
if(dim<=thread_number){ //if more threads than array size
//printf("Thread %i; Modifying value of index %i\n ", index, index);
c[index]= b[index]; //c= b
c[index]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(int i=0; i<sqrt_dim;i++){ //row of first matrix
c[index]+=a[i+index_j * sqrt_dim ]*b[i + index_i*sqrt_dim]; //c+= a*b^t
}
}
else{ //if less threads than array size
if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
for(unsigned long int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
//printf("Thread %i; Modifying value of index %i \n", index, i);
index_i = (int)i%sqrt_dim;
index_j = (i-index_i)/sqrt_dim;
c[i]= b[i]; //c= b
c[i]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(unsigned long int j=0; j<sqrt_dim;j++){ //row of first matrix
c[i]+=a[j+index_j * sqrt_dim ]*b[j+ index_i*sqrt_dim]; //c+= a*b^t
}
}
}
else{ //if last thread deal with all remaining array entries
for(unsigned long int i=index*(int)(dim/thread_number); i< dim; i++){
//printf("Thread %i; Modifying value of index %i\n",index, i );
index_i = (int)i%sqrt_dim;
index_j = (i-index_i)/sqrt_dim;
c[i]= b[i]; //c= b
c[i]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(unsigned long int j=0;j<sqrt_dim;j++){ //row of first matrix
c[i]+=a[j+index_j * sqrt_dim ]*b[j + index_i*sqrt_dim]; //c+= a*b^t
}
}
}
}
}
}
int main(int argc, char *argv[]){
//Measure time
clock_t time_begin;
// pointers to host & device arrays
int *d_array1 = 0,*d_array2 = 0; unsigned long int *d_array3 = 0;
int *h_array1 = 0,*h_array2 = 0;unsigned long int*h_array3 = 0;
unsigned long int *h_array_sec= 0;
unsigned int size_array=191*191; //here, size_array =L has to be a square
bool verbose=false;
int N=1;
if(argc == 3){
size_array=atoi(argv[1]) * atoi(argv[1]) ;
N=atoi(argv[2]);
}
else if(argc==4){
size_array=atoi(argv[1]) * atoi(argv[1]) ;
N=atoi(argv[2]);
verbose=(argv[3][0]=='v');
}
// malloc columns of host arrays
h_array1 = (int*)malloc( size_array * sizeof(int));
h_array_sec= (unsigned long int*)malloc( size_array * sizeof(unsigned long int));
h_array2 = (int*)malloc( size_array * sizeof(int));
h_array3 = (unsigned long int*)malloc( size_array * sizeof(unsigned long int));
//printf("Array A:\n");
for(unsigned long int i=0; i<size_array; i++){
h_array1[i]=1;//rand()%10;
// printf("%i\t", h_array1[i]);
//if((i+1)%(int)sqrt((float)size_array)==0)
// printf("\n");
}
//printf("\n");
//printf("Array B:\n");
for(unsigned int i=0; i<size_array; i++){
h_array2[i]=1;//rand()%10;
//printf("%i\t", h_array2[i]);
//if((i+1)%(int)sqrt((float)size_array)==0)
// printf("\n");
}
//printf("\n");
// cudaMalloc a device array
cudaMalloc(&d_array1,size_array * sizeof(int));
cudaMalloc(&d_array2,size_array * sizeof(int));
cudaMalloc(&d_array3,size_array * sizeof(unsigned long int));
// download and inspect the result on the host:
cudaMemcpy(d_array1, h_array1, sizeof(int)*size_array, cudaMemcpyHostToDevice);
cudaMemcpy(d_array2, h_array2, sizeof(int)*size_array, cudaMemcpyHostToDevice);
dim3 bloque(N,N); //Bloque bidimensional de N*N hilos (max 512 threads in a block)
dim3 grid(1,1); //Grid bidimensional de M*M bloques
int thread_number= N*N;
if (N*N > 512){
bloque.x = 512;
bloque.y = 512;
grid.x = ceil(double(N)/double(bloque.x));
grid.y = ceil(double(N)/double(bloque.y));
}
printf("%i threads, %ix%i matrix\n", thread_number, (int)sqrt((float)size_array), (int)sqrt((float)size_array));
time_begin=clock();
multiply<<<grid, bloque>>>(d_array1, d_array2 , d_array3,sqrt((float)size_array), thread_number);
cudaThreadSynchronize();
// download and inspect the result on the host:
cudaMemcpy(h_array3, d_array3, sizeof(unsigned long int)*size_array, cudaMemcpyDeviceToHost);
//printf("GPU time: %f seconds\n", clock() - time_begin);
//windows time
printf("GPU time, %i threads: %f seconds\n", thread_number,(((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.18s
if(verbose){
printf("Array C=B + AB^t + A^t :\n");
for(int i=0; i<size_array; i++){
printf("%i\t", h_array3[i]);
if((i+1)%(int)(sqrt((float)size_array))==0)
printf("\n");
}
printf("\n");
}
time_begin=clock();
secuential(h_array1, h_array2, h_array_sec, sqrt((float)size_array));
//printf("CPU time: %f seconds\n", clock() - time_begin);
//windows time
printf("CPU time: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.18s
// deallocate memory
bool b=true;
for(int i=0; i<size_array; i++){
if(h_array_sec[i] != h_array3[i]){
printf("GPU and CPU have different results (at least) at position %i\n", i);
b=false;
break;
}
}
if(b)
printf("GPU and CPU have the same results\n");
free(h_array3); free(h_array2); free(h_array1); free(h_array_sec);
cudaFree(d_array3);cudaFree(d_array2);cudaFree(d_array1);
system("pause");
}
void secuential(const int a[] ,const int b[], unsigned long int c[], const int sqrt_dim){
int dim = sqrt_dim* sqrt_dim;
int index_i, index_j;
//int *c= (int *)malloc ( dim * sizeof(int));
for(int i=0; i< dim; i++){
index_i = (int)i%sqrt_dim;
index_j = (i-index_i)/sqrt_dim;
c[i]= b[i]; //c= b
c[i]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(int j=0;j<sqrt_dim;j++){ //row of first matrix
c[i]+=a[j+index_j * sqrt_dim ]*b[j + index_i*sqrt_dim]; //c+= a*b^t
}
}
/*printf("Sequential result: Array C=B + AB^t + A^t :\n");
for(int i=0; i<dim; i++){
printf("%i\t", c[i]);
if((i+1)%(int)(sqrt((float)dim))==0)
printf("\n");
}
printf("\n");*/
//free(c);
}
|
.file "tmpxft_0012c4e7_00000000-6_entrega1_1_windows.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10secuentialPKiS0_Pmi
.type _Z10secuentialPKiS0_Pmi, @function
_Z10secuentialPKiS0_Pmi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %ecx, %ebx
imull %ecx, %ebx
testl %ebx, %ebx
jle .L3
movq %rdi, %r10
movq %rsi, %r11
movl %ecx, %edi
movq %rdx, %r9
movslq %ebx, %rbx
movslq %ecx, %rsi
salq $2, %rsi
movl $0, %r8d
.L7:
movl %r8d, %eax
cltd
idivl %edi
movl %edx, %ebp
movl %r8d, %eax
subl %edx, %eax
cltd
idivl %edi
movslq (%r11,%r8,4), %r12
movq %r9, %rcx
movq %r12, (%r9)
movl %ebp, %edx
imull %edi, %edx
leal (%rdx,%rax), %ebp
movslq %ebp, %rbp
movslq (%r10,%rbp,4), %rbp
addq %r12, %rbp
movq %rbp, (%r9)
testl %edi, %edi
jle .L5
imull %edi, %eax
cltq
leaq (%r10,%rax,4), %r12
movslq %edx, %rdx
leaq (%r11,%rdx,4), %rbp
movl $0, %edx
.L6:
movl (%r12,%rdx), %eax
imull 0(%rbp,%rdx), %eax
cltq
addq %rax, (%rcx)
addq $4, %rdx
cmpq %rsi, %rdx
jne .L6
.L5:
addq $1, %r8
addq $8, %r9
cmpq %rbx, %r8
jne .L7
.L3:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10secuentialPKiS0_Pmi, .-_Z10secuentialPKiS0_Pmi
.globl _Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii
.type _Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii, @function
_Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPKiS0_Pmii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii, .-_Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii
.globl _Z8multiplyPKiS0_Pmii
.type _Z8multiplyPKiS0_Pmii, @function
_Z8multiplyPKiS0_Pmii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8multiplyPKiS0_Pmii, .-_Z8multiplyPKiS0_Pmii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%i threads, %ix%i matrix\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "GPU time, %i threads: %f seconds\n"
.section .rodata.str1.1
.LC6:
.string "Array C=B + AB^t + A^t :\n"
.LC7:
.string "%i\t"
.LC8:
.string "\n"
.LC9:
.string "CPU time: %f seconds\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "GPU and CPU have different results (at least) at position %i\n"
.align 8
.LC11:
.string "GPU and CPU have the same results\n"
.section .rodata.str1.1
.LC12:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
cmpl $3, %edi
je .L62
cmpl $4, %edi
je .L63
movl $145924, %edi
call malloc@PLT
movq %rax, %r14
movl $291848, %edi
call malloc@PLT
movq %rax, %rbp
movl $145924, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $291848, %edi
call malloc@PLT
movq %rax, %rbx
movl $1, %r12d
movb $0, 47(%rsp)
movl $36481, 40(%rsp)
movq $291848, 24(%rsp)
movl $145924, %r15d
movl $36481, %r13d
.L48:
movq %r14, %rax
leaq (%r15,%r14), %rdx
.L24:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L24
movq 16(%rsp), %rcx
movq %rcx, %rax
leaq (%rcx,%r15), %rdx
.L25:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L25
.L23:
leaq 56(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq 24(%rsp), %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl %r12d, %r15d
imull %r12d, %r15d
cmpl $512, %r15d
jle .L27
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
mulsd .LC0(%rip), %xmm0
call ceil@PLT
cvttsd2siq %xmm0, %rax
movl %eax, 92(%rsp)
movl %eax, 96(%rsp)
movl $512, %r12d
.L27:
movl 40(%rsp), %eax
pxor %xmm4, %xmm4
cvtsi2ssq %rax, %xmm4
movss %xmm4, 12(%rsp)
pxor %xmm0, %xmm0
ucomiss %xmm4, %xmm0
ja .L57
sqrtss %xmm4, %xmm4
movaps %xmm4, %xmm0
cvttss2sil %xmm4, %eax
movl %eax, 32(%rsp)
.L32:
cvttss2sil %xmm0, %ecx
movl 32(%rsp), %r8d
movl %r15d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, 32(%rsp)
movl %r12d, 80(%rsp)
movl %r12d, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L33:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq 24(%rsp), %rdx
movq 72(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq 32(%rsp), %xmm1
subss %xmm1, %xmm0
divss .LC3(%rip), %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r15d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpb $0, 47(%rsp)
jne .L65
.L34:
call clock@PLT
movq %rax, %r12
pxor %xmm0, %xmm0
movss 12(%rsp), %xmm5
ucomiss %xmm5, %xmm0
ja .L59
sqrtss %xmm5, %xmm5
movaps %xmm5, %xmm0
.L43:
cvttss2sil %xmm0, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call _Z10secuentialPKiS0_Pmi
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r12, %xmm1
subss %xmm1, %xmm0
divss .LC3(%rip), %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 40(%rsp)
je .L44
movl $0, %edx
.L47:
movq (%rbx,%rdx,8), %rax
cmpq %rax, 0(%rbp,%rdx,8)
jne .L66
addq $1, %rdx
cmpq %rdx, %r13
jne .L47
.L44:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L46:
movq %rbx, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq .LC12(%rip), %rdi
call system@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
imull %ebp, %eax
movl %eax, 40(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
movb $0, 47(%rsp)
.L21:
movl 40(%rsp), %r13d
leaq 0(,%r13,4), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
leaq 0(,%r13,8), %rbx
movq %rbx, 24(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r15, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
testq %r13, %r13
jne .L48
jmp .L23
.L63:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
imull %ebp, %eax
movl %eax, 40(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
movq 24(%rbx), %rax
cmpb $118, (%rax)
sete 47(%rsp)
jmp .L21
.L57:
movss 12(%rsp), %xmm0
call sqrtf@PLT
cvttss2sil %xmm0, %eax
movl %eax, 32(%rsp)
movss 12(%rsp), %xmm0
call sqrtf@PLT
jmp .L32
.L64:
movss 12(%rsp), %xmm0
call sqrtf@PLT
cvttss2sil %xmm0, %ecx
movl %r15d, %r8d
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii
jmp .L33
.L65:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 40(%rsp)
je .L35
movl $1, %r12d
leaq .LC7(%rip), %r15
movq %r14, 24(%rsp)
jmp .L40
.L58:
movss 12(%rsp), %xmm0
call sqrtf@PLT
jmp .L38
.L39:
leaq 1(%r12), %rax
cmpq %r12, %r13
je .L68
movq %rax, %r12
.L40:
movq -8(%rbx,%r12,8), %rdx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %r14d
pxor %xmm3, %xmm3
movss 12(%rsp), %xmm2
ucomiss %xmm2, %xmm3
ja .L58
sqrtss %xmm2, %xmm2
movaps %xmm2, %xmm0
.L38:
cvttss2sil %xmm0, %ecx
movl %r14d, %eax
cltd
idivl %ecx
testl %edx, %edx
jne .L39
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L68:
movq 24(%rsp), %r14
.L35:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L34
.L59:
movss 12(%rsp), %xmm0
call sqrtf@PLT
jmp .L43
.L66:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L46
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8multiplyPKiS0_Pmii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPKiS0_Pmii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1063256064
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1232348160
.align 4
.LC4:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
//M and N number of threads (grid and block)
void secuential(const int a[] ,const int b[], unsigned long int c[], const int sqrt_dim);
__global__ void multiply( const int a[] ,const int b[], unsigned long int c[] , const int sqrt_dim,const int thread_number)
{
unsigned long int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
unsigned long int index = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x) + threadIdx.x;
//convert global index to column and row (index_i and index_j) of matrix
unsigned long int index_i = index < sqrt_dim ? index : (int)index%sqrt_dim;
unsigned long int index_j = (index-index_i)/sqrt_dim;
unsigned int dim=sqrt_dim*sqrt_dim;
//printf("index= %i \t", index);
if(index<dim){
c[index]=0;
if(dim<=thread_number){ //if more threads than array size
//printf("Thread %i; Modifying value of index %i\n ", index, index);
c[index]= b[index]; //c= b
c[index]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(int i=0; i<sqrt_dim;i++){ //row of first matrix
c[index]+=a[i+index_j * sqrt_dim ]*b[i + index_i*sqrt_dim]; //c+= a*b^t
}
}
else{ //if less threads than array size
if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
for(unsigned long int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
//printf("Thread %i; Modifying value of index %i \n", index, i);
index_i = (int)i%sqrt_dim;
index_j = (i-index_i)/sqrt_dim;
c[i]= b[i]; //c= b
c[i]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(unsigned long int j=0; j<sqrt_dim;j++){ //row of first matrix
c[i]+=a[j+index_j * sqrt_dim ]*b[j+ index_i*sqrt_dim]; //c+= a*b^t
}
}
}
else{ //if last thread deal with all remaining array entries
for(unsigned long int i=index*(int)(dim/thread_number); i< dim; i++){
//printf("Thread %i; Modifying value of index %i\n",index, i );
index_i = (int)i%sqrt_dim;
index_j = (i-index_i)/sqrt_dim;
c[i]= b[i]; //c= b
c[i]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(unsigned long int j=0;j<sqrt_dim;j++){ //row of first matrix
c[i]+=a[j+index_j * sqrt_dim ]*b[j + index_i*sqrt_dim]; //c+= a*b^t
}
}
}
}
}
}
int main(int argc, char *argv[]){
//Measure time
clock_t time_begin;
// pointers to host & device arrays
int *d_array1 = 0,*d_array2 = 0; unsigned long int *d_array3 = 0;
int *h_array1 = 0,*h_array2 = 0;unsigned long int*h_array3 = 0;
unsigned long int *h_array_sec= 0;
unsigned int size_array=191*191; //here, size_array =L has to be a square
bool verbose=false;
int N=1;
if(argc == 3){
size_array=atoi(argv[1]) * atoi(argv[1]) ;
N=atoi(argv[2]);
}
else if(argc==4){
size_array=atoi(argv[1]) * atoi(argv[1]) ;
N=atoi(argv[2]);
verbose=(argv[3][0]=='v');
}
// malloc columns of host arrays
h_array1 = (int*)malloc( size_array * sizeof(int));
h_array_sec= (unsigned long int*)malloc( size_array * sizeof(unsigned long int));
h_array2 = (int*)malloc( size_array * sizeof(int));
h_array3 = (unsigned long int*)malloc( size_array * sizeof(unsigned long int));
//printf("Array A:\n");
for(unsigned long int i=0; i<size_array; i++){
h_array1[i]=1;//rand()%10;
// printf("%i\t", h_array1[i]);
//if((i+1)%(int)sqrt((float)size_array)==0)
// printf("\n");
}
//printf("\n");
//printf("Array B:\n");
for(unsigned int i=0; i<size_array; i++){
h_array2[i]=1;//rand()%10;
//printf("%i\t", h_array2[i]);
//if((i+1)%(int)sqrt((float)size_array)==0)
// printf("\n");
}
//printf("\n");
// cudaMalloc a device array
cudaMalloc(&d_array1,size_array * sizeof(int));
cudaMalloc(&d_array2,size_array * sizeof(int));
cudaMalloc(&d_array3,size_array * sizeof(unsigned long int));
// download and inspect the result on the host:
cudaMemcpy(d_array1, h_array1, sizeof(int)*size_array, cudaMemcpyHostToDevice);
cudaMemcpy(d_array2, h_array2, sizeof(int)*size_array, cudaMemcpyHostToDevice);
dim3 bloque(N,N); //Bloque bidimensional de N*N hilos (max 512 threads in a block)
dim3 grid(1,1); //Grid bidimensional de M*M bloques
int thread_number= N*N;
if (N*N > 512){
bloque.x = 512;
bloque.y = 512;
grid.x = ceil(double(N)/double(bloque.x));
grid.y = ceil(double(N)/double(bloque.y));
}
printf("%i threads, %ix%i matrix\n", thread_number, (int)sqrt((float)size_array), (int)sqrt((float)size_array));
time_begin=clock();
multiply<<<grid, bloque>>>(d_array1, d_array2 , d_array3,sqrt((float)size_array), thread_number);
cudaThreadSynchronize();
// download and inspect the result on the host:
cudaMemcpy(h_array3, d_array3, sizeof(unsigned long int)*size_array, cudaMemcpyDeviceToHost);
//printf("GPU time: %f seconds\n", clock() - time_begin);
//windows time
printf("GPU time, %i threads: %f seconds\n", thread_number,(((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.18s
if(verbose){
printf("Array C=B + AB^t + A^t :\n");
for(int i=0; i<size_array; i++){
printf("%i\t", h_array3[i]);
if((i+1)%(int)(sqrt((float)size_array))==0)
printf("\n");
}
printf("\n");
}
time_begin=clock();
secuential(h_array1, h_array2, h_array_sec, sqrt((float)size_array));
//printf("CPU time: %f seconds\n", clock() - time_begin);
//windows time
printf("CPU time: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.18s
// deallocate memory
bool b=true;
for(int i=0; i<size_array; i++){
if(h_array_sec[i] != h_array3[i]){
printf("GPU and CPU have different results (at least) at position %i\n", i);
b=false;
break;
}
}
if(b)
printf("GPU and CPU have the same results\n");
free(h_array3); free(h_array2); free(h_array1); free(h_array_sec);
cudaFree(d_array3);cudaFree(d_array2);cudaFree(d_array1);
system("pause");
}
void secuential(const int a[] ,const int b[], unsigned long int c[], const int sqrt_dim){
int dim = sqrt_dim* sqrt_dim;
int index_i, index_j;
//int *c= (int *)malloc ( dim * sizeof(int));
for(int i=0; i< dim; i++){
index_i = (int)i%sqrt_dim;
index_j = (i-index_i)/sqrt_dim;
c[i]= b[i]; //c= b
c[i]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(int j=0;j<sqrt_dim;j++){ //row of first matrix
c[i]+=a[j+index_j * sqrt_dim ]*b[j + index_i*sqrt_dim]; //c+= a*b^t
}
}
/*printf("Sequential result: Array C=B + AB^t + A^t :\n");
for(int i=0; i<dim; i++){
printf("%i\t", c[i]);
if((i+1)%(int)(sqrt((float)dim))==0)
printf("\n");
}
printf("\n");*/
//free(c);
}
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
//M and N number of threads (grid and block)
void secuential(const int a[] ,const int b[], unsigned long int c[], const int sqrt_dim);
__global__ void multiply( const int a[] ,const int b[], unsigned long int c[] , const int sqrt_dim,const int thread_number)
{
unsigned long int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
unsigned long int index = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x) + threadIdx.x;
//convert global index to column and row (index_i and index_j) of matrix
unsigned long int index_i = index < sqrt_dim ? index : (int)index%sqrt_dim;
unsigned long int index_j = (index-index_i)/sqrt_dim;
unsigned int dim=sqrt_dim*sqrt_dim;
//printf("index= %i \t", index);
if(index<dim){
c[index]=0;
if(dim<=thread_number){ //if more threads than array size
//printf("Thread %i; Modifying value of index %i\n ", index, index);
c[index]= b[index]; //c= b
c[index]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(int i=0; i<sqrt_dim;i++){ //row of first matrix
c[index]+=a[i+index_j * sqrt_dim ]*b[i + index_i*sqrt_dim]; //c+= a*b^t
}
}
else{ //if less threads than array size
if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
for(unsigned long int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
//printf("Thread %i; Modifying value of index %i \n", index, i);
index_i = (int)i%sqrt_dim;
index_j = (i-index_i)/sqrt_dim;
c[i]= b[i]; //c= b
c[i]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(unsigned long int j=0; j<sqrt_dim;j++){ //row of first matrix
c[i]+=a[j+index_j * sqrt_dim ]*b[j+ index_i*sqrt_dim]; //c+= a*b^t
}
}
}
else{ //if last thread deal with all remaining array entries
for(unsigned long int i=index*(int)(dim/thread_number); i< dim; i++){
//printf("Thread %i; Modifying value of index %i\n",index, i );
index_i = (int)i%sqrt_dim;
index_j = (i-index_i)/sqrt_dim;
c[i]= b[i]; //c= b
c[i]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(unsigned long int j=0;j<sqrt_dim;j++){ //row of first matrix
c[i]+=a[j+index_j * sqrt_dim ]*b[j + index_i*sqrt_dim]; //c+= a*b^t
}
}
}
}
}
}
int main(int argc, char *argv[]){
//Measure time
clock_t time_begin;
// pointers to host & device arrays
int *d_array1 = 0,*d_array2 = 0; unsigned long int *d_array3 = 0;
int *h_array1 = 0,*h_array2 = 0;unsigned long int*h_array3 = 0;
unsigned long int *h_array_sec= 0;
unsigned int size_array=191*191; //here, size_array =L has to be a square
bool verbose=false;
int N=1;
if(argc == 3){
size_array=atoi(argv[1]) * atoi(argv[1]) ;
N=atoi(argv[2]);
}
else if(argc==4){
size_array=atoi(argv[1]) * atoi(argv[1]) ;
N=atoi(argv[2]);
verbose=(argv[3][0]=='v');
}
// malloc columns of host arrays
h_array1 = (int*)malloc( size_array * sizeof(int));
h_array_sec= (unsigned long int*)malloc( size_array * sizeof(unsigned long int));
h_array2 = (int*)malloc( size_array * sizeof(int));
h_array3 = (unsigned long int*)malloc( size_array * sizeof(unsigned long int));
//printf("Array A:\n");
for(unsigned long int i=0; i<size_array; i++){
h_array1[i]=1;//rand()%10;
// printf("%i\t", h_array1[i]);
//if((i+1)%(int)sqrt((float)size_array)==0)
// printf("\n");
}
//printf("\n");
//printf("Array B:\n");
for(unsigned int i=0; i<size_array; i++){
h_array2[i]=1;//rand()%10;
//printf("%i\t", h_array2[i]);
//if((i+1)%(int)sqrt((float)size_array)==0)
// printf("\n");
}
//printf("\n");
// cudaMalloc a device array
hipMalloc(&d_array1,size_array * sizeof(int));
hipMalloc(&d_array2,size_array * sizeof(int));
hipMalloc(&d_array3,size_array * sizeof(unsigned long int));
// download and inspect the result on the host:
hipMemcpy(d_array1, h_array1, sizeof(int)*size_array, hipMemcpyHostToDevice);
hipMemcpy(d_array2, h_array2, sizeof(int)*size_array, hipMemcpyHostToDevice);
dim3 bloque(N,N); //Bloque bidimensional de N*N hilos (max 512 threads in a block)
dim3 grid(1,1); //Grid bidimensional de M*M bloques
int thread_number= N*N;
if (N*N > 512){
bloque.x = 512;
bloque.y = 512;
grid.x = ceil(double(N)/double(bloque.x));
grid.y = ceil(double(N)/double(bloque.y));
}
printf("%i threads, %ix%i matrix\n", thread_number, (int)sqrt((float)size_array), (int)sqrt((float)size_array));
time_begin=clock();
multiply<<<grid, bloque>>>(d_array1, d_array2 , d_array3,sqrt((float)size_array), thread_number);
hipDeviceSynchronize();
// download and inspect the result on the host:
hipMemcpy(h_array3, d_array3, sizeof(unsigned long int)*size_array, hipMemcpyDeviceToHost);
//printf("GPU time: %f seconds\n", clock() - time_begin);
//windows time
printf("GPU time, %i threads: %f seconds\n", thread_number,(((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.18s
if(verbose){
printf("Array C=B + AB^t + A^t :\n");
for(int i=0; i<size_array; i++){
printf("%i\t", h_array3[i]);
if((i+1)%(int)(sqrt((float)size_array))==0)
printf("\n");
}
printf("\n");
}
time_begin=clock();
secuential(h_array1, h_array2, h_array_sec, sqrt((float)size_array));
//printf("CPU time: %f seconds\n", clock() - time_begin);
//windows time
printf("CPU time: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.18s
// deallocate memory
bool b=true;
for(int i=0; i<size_array; i++){
if(h_array_sec[i] != h_array3[i]){
printf("GPU and CPU have different results (at least) at position %i\n", i);
b=false;
break;
}
}
if(b)
printf("GPU and CPU have the same results\n");
free(h_array3); free(h_array2); free(h_array1); free(h_array_sec);
hipFree(d_array3);hipFree(d_array2);hipFree(d_array1);
system("pause");
}
void secuential(const int a[] ,const int b[], unsigned long int c[], const int sqrt_dim){
int dim = sqrt_dim* sqrt_dim;
int index_i, index_j;
//int *c= (int *)malloc ( dim * sizeof(int));
for(int i=0; i< dim; i++){
index_i = (int)i%sqrt_dim;
index_j = (i-index_i)/sqrt_dim;
c[i]= b[i]; //c= b
c[i]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(int j=0;j<sqrt_dim;j++){ //row of first matrix
c[i]+=a[j+index_j * sqrt_dim ]*b[j + index_i*sqrt_dim]; //c+= a*b^t
}
}
/*printf("Sequential result: Array C=B + AB^t + A^t :\n");
for(int i=0; i<dim; i++){
printf("%i\t", c[i]);
if((i+1)%(int)(sqrt((float)dim))==0)
printf("\n");
}
printf("\n");*/
//free(c);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
//M and N number of threads (grid and block)
void secuential(const int a[] ,const int b[], unsigned long int c[], const int sqrt_dim);
__global__ void multiply( const int a[] ,const int b[], unsigned long int c[] , const int sqrt_dim,const int thread_number)
{
unsigned long int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
unsigned long int index = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x) + threadIdx.x;
//convert global index to column and row (index_i and index_j) of matrix
unsigned long int index_i = index < sqrt_dim ? index : (int)index%sqrt_dim;
unsigned long int index_j = (index-index_i)/sqrt_dim;
unsigned int dim=sqrt_dim*sqrt_dim;
//printf("index= %i \t", index);
if(index<dim){
c[index]=0;
if(dim<=thread_number){ //if more threads than array size
//printf("Thread %i; Modifying value of index %i\n ", index, index);
c[index]= b[index]; //c= b
c[index]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(int i=0; i<sqrt_dim;i++){ //row of first matrix
c[index]+=a[i+index_j * sqrt_dim ]*b[i + index_i*sqrt_dim]; //c+= a*b^t
}
}
else{ //if less threads than array size
if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
for(unsigned long int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
//printf("Thread %i; Modifying value of index %i \n", index, i);
index_i = (int)i%sqrt_dim;
index_j = (i-index_i)/sqrt_dim;
c[i]= b[i]; //c= b
c[i]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(unsigned long int j=0; j<sqrt_dim;j++){ //row of first matrix
c[i]+=a[j+index_j * sqrt_dim ]*b[j+ index_i*sqrt_dim]; //c+= a*b^t
}
}
}
else{ //if last thread deal with all remaining array entries
for(unsigned long int i=index*(int)(dim/thread_number); i< dim; i++){
//printf("Thread %i; Modifying value of index %i\n",index, i );
index_i = (int)i%sqrt_dim;
index_j = (i-index_i)/sqrt_dim;
c[i]= b[i]; //c= b
c[i]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(unsigned long int j=0;j<sqrt_dim;j++){ //row of first matrix
c[i]+=a[j+index_j * sqrt_dim ]*b[j + index_i*sqrt_dim]; //c+= a*b^t
}
}
}
}
}
}
int main(int argc, char *argv[]){
//Measure time
clock_t time_begin;
// pointers to host & device arrays
int *d_array1 = 0,*d_array2 = 0; unsigned long int *d_array3 = 0;
int *h_array1 = 0,*h_array2 = 0;unsigned long int*h_array3 = 0;
unsigned long int *h_array_sec= 0;
unsigned int size_array=191*191; //here, size_array =L has to be a square
bool verbose=false;
int N=1;
if(argc == 3){
size_array=atoi(argv[1]) * atoi(argv[1]) ;
N=atoi(argv[2]);
}
else if(argc==4){
size_array=atoi(argv[1]) * atoi(argv[1]) ;
N=atoi(argv[2]);
verbose=(argv[3][0]=='v');
}
// malloc columns of host arrays
h_array1 = (int*)malloc( size_array * sizeof(int));
h_array_sec= (unsigned long int*)malloc( size_array * sizeof(unsigned long int));
h_array2 = (int*)malloc( size_array * sizeof(int));
h_array3 = (unsigned long int*)malloc( size_array * sizeof(unsigned long int));
//printf("Array A:\n");
for(unsigned long int i=0; i<size_array; i++){
h_array1[i]=1;//rand()%10;
// printf("%i\t", h_array1[i]);
//if((i+1)%(int)sqrt((float)size_array)==0)
// printf("\n");
}
//printf("\n");
//printf("Array B:\n");
for(unsigned int i=0; i<size_array; i++){
h_array2[i]=1;//rand()%10;
//printf("%i\t", h_array2[i]);
//if((i+1)%(int)sqrt((float)size_array)==0)
// printf("\n");
}
//printf("\n");
// cudaMalloc a device array
hipMalloc(&d_array1,size_array * sizeof(int));
hipMalloc(&d_array2,size_array * sizeof(int));
hipMalloc(&d_array3,size_array * sizeof(unsigned long int));
// download and inspect the result on the host:
hipMemcpy(d_array1, h_array1, sizeof(int)*size_array, hipMemcpyHostToDevice);
hipMemcpy(d_array2, h_array2, sizeof(int)*size_array, hipMemcpyHostToDevice);
dim3 bloque(N,N); //Bloque bidimensional de N*N hilos (max 512 threads in a block)
dim3 grid(1,1); //Grid bidimensional de M*M bloques
int thread_number= N*N;
if (N*N > 512){
bloque.x = 512;
bloque.y = 512;
grid.x = ceil(double(N)/double(bloque.x));
grid.y = ceil(double(N)/double(bloque.y));
}
printf("%i threads, %ix%i matrix\n", thread_number, (int)sqrt((float)size_array), (int)sqrt((float)size_array));
time_begin=clock();
multiply<<<grid, bloque>>>(d_array1, d_array2 , d_array3,sqrt((float)size_array), thread_number);
hipDeviceSynchronize();
// download and inspect the result on the host:
hipMemcpy(h_array3, d_array3, sizeof(unsigned long int)*size_array, hipMemcpyDeviceToHost);
//printf("GPU time: %f seconds\n", clock() - time_begin);
//windows time
printf("GPU time, %i threads: %f seconds\n", thread_number,(((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.18s
if(verbose){
printf("Array C=B + AB^t + A^t :\n");
for(int i=0; i<size_array; i++){
printf("%i\t", h_array3[i]);
if((i+1)%(int)(sqrt((float)size_array))==0)
printf("\n");
}
printf("\n");
}
time_begin=clock();
secuential(h_array1, h_array2, h_array_sec, sqrt((float)size_array));
//printf("CPU time: %f seconds\n", clock() - time_begin);
//windows time
printf("CPU time: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.18s
// deallocate memory
bool b=true;
for(int i=0; i<size_array; i++){
if(h_array_sec[i] != h_array3[i]){
printf("GPU and CPU have different results (at least) at position %i\n", i);
b=false;
break;
}
}
if(b)
printf("GPU and CPU have the same results\n");
free(h_array3); free(h_array2); free(h_array1); free(h_array_sec);
hipFree(d_array3);hipFree(d_array2);hipFree(d_array1);
system("pause");
}
void secuential(const int a[] ,const int b[], unsigned long int c[], const int sqrt_dim){
int dim = sqrt_dim* sqrt_dim;
int index_i, index_j;
//int *c= (int *)malloc ( dim * sizeof(int));
for(int i=0; i< dim; i++){
index_i = (int)i%sqrt_dim;
index_j = (i-index_i)/sqrt_dim;
c[i]= b[i]; //c= b
c[i]+= a[index_j+ index_i * sqrt_dim]; //c+= a^t
for(int j=0;j<sqrt_dim;j++){ //row of first matrix
c[i]+=a[j+index_j * sqrt_dim ]*b[j + index_i*sqrt_dim]; //c+= a*b^t
}
}
/*printf("Sequential result: Array C=B + AB^t + A^t :\n");
for(int i=0; i<dim; i++){
printf("%i\t", c[i]);
if((i+1)%(int)(sqrt((float)dim))==0)
printf("\n");
}
printf("\n");*/
//free(c);
}
|
.text
.file "entrega1_1_windows.hip"
.globl _Z23__device_stub__multiplyPKiS0_Pmii # -- Begin function _Z23__device_stub__multiplyPKiS0_Pmii
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPKiS0_Pmii,@function
_Z23__device_stub__multiplyPKiS0_Pmii: # @_Z23__device_stub__multiplyPKiS0_Pmii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPKiS0_Pmii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPKiS0_Pmii, .Lfunc_end0-_Z23__device_stub__multiplyPKiS0_Pmii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f60000000000000 # double 0.001953125
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0x49742400 # float 1.0E+6
.LCPI1_2:
.long 0x447a0000 # float 1000
.LCPI1_3:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 64(%rsp)
movq $0, 56(%rsp)
movq $0, 48(%rsp)
cmpl $4, %edi
je .LBB1_4
# %bb.1:
cmpl $3, %edi
jne .LBB1_2
# %bb.3:
movq 8(%rsi), %rdi
xorl %eax, %eax
movq %rax, 88(%rsp) # 8-byte Spill
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
imull %r14d, %r14d
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
jmp .LBB1_6
.LBB1_4:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
imull %r14d, %r14d
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
movq 24(%rbx), %rax
cmpb $118, (%rax)
sete %al
jmp .LBB1_5
.LBB1_2:
movl $36481, %r14d # imm = 0x8E81
movl $1, %eax
movq %rax, 8(%rsp) # 8-byte Spill
xorl %eax, %eax
.LBB1_5:
movq %rax, 88(%rsp) # 8-byte Spill
.LBB1_6:
movq %r14, 80(%rsp) # 8-byte Spill
movl %r14d, %r12d
leaq (,%r12,4), %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
leaq (,%r12,8), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %r13, 32(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
cmpl $0, 80(%rsp) # 4-byte Folded Reload
je .LBB1_11
# %bb.7: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_8: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq %rax, %r12
jne .LBB1_8
# %bb.9: # %.lr.ph108.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_10: # %.lr.ph108
# =>This Inner Loop Header: Depth=1
movl $1, (%r15,%rax,4)
incq %rax
cmpq %rax, %r12
jne .LBB1_10
.LBB1_11: # %._crit_edge
movabsq $4294967297, %r13 # imm = 0x100000001
leaq 64(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
callq hipMalloc
movq 64(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rcx # 8-byte Reload
movl %ecx, %eax
imull %ecx, %eax
cmpl $512, %eax # imm = 0x200
movl %eax, 80(%rsp) # 4-byte Spill
jbe .LBB1_12
# %bb.13:
cvtsi2sd %ecx, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %eax
imulq %rax, %r13
movq %r13, 24(%rsp) # 8-byte Spill
movabsq $2199023256064, %rax # imm = 0x20000000200
movq %rax, 16(%rsp) # 8-byte Spill
jmp .LBB1_14
.LBB1_12:
movq %r13, 24(%rsp) # 8-byte Spill
movl %ecx, %eax
movq %rax, %rcx
shlq $32, %rcx
orq %rax, %rcx
movq %rcx, 16(%rsp) # 8-byte Spill
.LBB1_14:
cvtsi2ss %r12d, %xmm1
sqrtss %xmm1, %xmm2
xorps %xmm3, %xmm3
ucomiss %xmm3, %xmm1
movaps %xmm2, %xmm0
movss %xmm1, 8(%rsp) # 4-byte Spill
jae .LBB1_16
# %bb.15: # %call.sqrt
movaps %xmm1, %xmm0
movss %xmm2, 72(%rsp) # 4-byte Spill
callq sqrtf
xorps %xmm3, %xmm3
movss 72(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
.LBB1_16: # %.split
cvttss2si %xmm0, %ebp
ucomiss %xmm3, %xmm1
jae .LBB1_18
# %bb.17: # %call.sqrt144
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq sqrtf
movaps %xmm0, %xmm2
.LBB1_18: # %.split.split
cvttss2si %xmm2, %ecx
movl $.L.str, %edi
movl 80(%rsp), %r13d # 4-byte Reload
movl %r13d, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
callq clock
movq %rax, %rbp
movq 24(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 16(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_23
# %bb.19:
movq %rbp, 24(%rsp) # 8-byte Spill
movl %r13d, %ebp
movq 64(%rsp), %r13
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
xorps %xmm1, %xmm1
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jb .LBB1_21
# %bb.20:
sqrtss %xmm0, %xmm0
jmp .LBB1_22
.LBB1_21: # %call.sqrt146
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, 72(%rsp) # 8-byte Spill
callq sqrtf
movq 72(%rsp), %rsi # 8-byte Reload
movq 16(%rsp), %rdx # 8-byte Reload
.LBB1_22: # %.split145
cvttss2si %xmm0, %eax
movq %r13, 168(%rsp)
movq %rdx, 160(%rsp)
movq %rsi, 152(%rsp)
movl %eax, 100(%rsp)
movl %ebp, 96(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 100(%rsp), %rax
movq %rax, 200(%rsp)
leaq 96(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
movl %ebp, %r13d
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z8multiplyPKiS0_Pmii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movq 24(%rsp), %rbp # 8-byte Reload
.LBB1_23:
callq hipDeviceSynchronize
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi # 8-byte Reload
movq 32(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %rbp, %xmm1
subss %xmm1, %xmm0
divss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r13d, %esi
movb $1, %al
callq printf
cmpb $0, 88(%rsp) # 1-byte Folded Reload
je .LBB1_32
# %bb.24:
movl $.Lstr, %edi
callq puts@PLT
testq %r12, %r12
je .LBB1_31
# %bb.25: # %.lr.ph111.preheader
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
sqrtss %xmm0, %xmm0
movss %xmm0, 32(%rsp) # 4-byte Spill
xorl %r13d, %r13d
jmp .LBB1_26
.p2align 4, 0x90
.LBB1_28: # %.lr.ph111.split
# in Loop: Header=BB1_26 Depth=1
cvttss2si %xmm0, %ecx
leal 1(%r13), %eax
cltd
idivl %ecx
testl %edx, %edx
je .LBB1_29
.LBB1_30: # in Loop: Header=BB1_26 Depth=1
incq %r13
cmpq %r13, %r12
je .LBB1_31
.LBB1_26: # %.lr.ph111
# =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rax # 8-byte Reload
movq (%rax,%r13,8), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI1_3(%rip), %xmm0
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
jae .LBB1_28
# %bb.27: # %call.sqrt147
# in Loop: Header=BB1_26 Depth=1
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq sqrtf
jmp .LBB1_28
.p2align 4, 0x90
.LBB1_29: # in Loop: Header=BB1_26 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_30
.LBB1_31: # %._crit_edge112
movl $10, %edi
callq putchar@PLT
.LBB1_32:
callq clock
movq %rax, %r13
xorps %xmm1, %xmm1
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jb .LBB1_34
# %bb.33:
sqrtss %xmm0, %xmm0
jmp .LBB1_35
.LBB1_34: # %call.sqrt149
callq sqrtf
.LBB1_35: # %.split148
cvttss2si %xmm0, %esi
testl %esi, %esi
je .LBB1_42
# %bb.36: # %.lr.ph37.i
movl %esi, %edi
imull %edi, %edi
cmpl $1, %edi
adcl $0, %edi
movl %esi, %r8d
xorl %ecx, %ecx
jmp .LBB1_37
.p2align 4, 0x90
.LBB1_41: # in Loop: Header=BB1_37 Depth=1
incq %rcx
cmpq %rdi, %rcx
je .LBB1_42
.LBB1_37: # =>This Loop Header: Depth=1
# Child Loop BB1_39 Depth 2
movl %ecx, %eax
cltd
idivl %esi
# kill: def $eax killed $eax def $rax
# kill: def $edx killed $edx def $rdx
movslq (%r15,%rcx,4), %r10
movq %r10, (%r14,%rcx,8)
imull %esi, %edx
leal (%rax,%rdx), %r9d
movslq %r9d, %r9
movslq (%rbx,%r9,4), %r9
addq %r10, %r9
movq %r9, (%r14,%rcx,8)
testl %esi, %esi
jle .LBB1_41
# %bb.38: # %.lr.ph.i
# in Loop: Header=BB1_37 Depth=1
imull %esi, %eax
movl %edx, %edx
leaq (%rbx,%rax,4), %rax
leaq (%r15,%rdx,4), %rdx
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_39: # Parent Loop BB1_37 Depth=1
# => This Inner Loop Header: Depth=2
movslq (%rax,%r10,4), %r11
movslq (%rdx,%r10,4), %rbp
imulq %r11, %rbp
addq %rbp, %r9
incq %r10
cmpq %r10, %r8
jne .LBB1_39
# %bb.40: # %._crit_edge.i
# in Loop: Header=BB1_37 Depth=1
movq %r9, (%r14,%rcx,8)
jmp .LBB1_41
.LBB1_42: # %_Z10secuentialPKiS0_Pmi.exit
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %r13, %xmm1
subss %xmm1, %xmm0
divss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
testq %r12, %r12
je .LBB1_47
# %bb.43: # %.lr.ph117.preheader
xorl %esi, %esi
movq 40(%rsp), %rcx # 8-byte Reload
.p2align 4, 0x90
.LBB1_44: # %.lr.ph117
# =>This Inner Loop Header: Depth=1
movq (%r14,%rsi,8), %rax
cmpq (%rcx,%rsi,8), %rax
jne .LBB1_45
# %bb.46: # in Loop: Header=BB1_44 Depth=1
incq %rsi
cmpq %rsi, %r12
jne .LBB1_44
.LBB1_47: # %.critedge
movl $.Lstr.1, %edi
callq puts@PLT
jmp .LBB1_48
.LBB1_45:
movl $.L.str.6, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
.LBB1_48:
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movl $.L.str.8, %edi
callq system
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z10secuentialPKiS0_Pmi # -- Begin function _Z10secuentialPKiS0_Pmi
.p2align 4, 0x90
.type _Z10secuentialPKiS0_Pmi,@function
_Z10secuentialPKiS0_Pmi: # @_Z10secuentialPKiS0_Pmi
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
je .LBB2_8
# %bb.1: # %.lr.ph37
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r8
movl %ecx, %r10d
imull %r10d, %r10d
cmpl $1, %r10d
adcl $0, %r10d
movl %ecx, %r11d
xorl %r9d, %r9d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_2 Depth=1
incq %r9
cmpq %r10, %r9
je .LBB2_7
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
movl %r9d, %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
# kill: def $edx killed $edx def $rdx
movslq (%rsi,%r9,4), %rbx
movq %rbx, (%r8,%r9,8)
imull %ecx, %edx
leal (%rax,%rdx), %ebp
movslq %ebp, %r14
movslq (%rdi,%r14,4), %r14
addq %rbx, %r14
movq %r14, (%r8,%r9,8)
testl %ecx, %ecx
jle .LBB2_6
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
imull %ecx, %eax
movq (%r8,%r9,8), %rbx
movl %edx, %edx
leaq (%rdi,%rax,4), %rax
leaq (%rsi,%rdx,4), %rdx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movslq (%rax,%r14,4), %r15
movslq (%rdx,%r14,4), %r12
imulq %r15, %r12
addq %r12, %rbx
incq %r14
cmpq %r14, %r11
jne .LBB2_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq %rbx, (%r8,%r9,8)
jmp .LBB2_6
.LBB2_7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB2_8: # %._crit_edge38
retq
.Lfunc_end2:
.size _Z10secuentialPKiS0_Pmi, .Lfunc_end2-_Z10secuentialPKiS0_Pmi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPKiS0_Pmii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPKiS0_Pmii,@object # @_Z8multiplyPKiS0_Pmii
.section .rodata,"a",@progbits
.globl _Z8multiplyPKiS0_Pmii
.p2align 3, 0x0
_Z8multiplyPKiS0_Pmii:
.quad _Z23__device_stub__multiplyPKiS0_Pmii
.size _Z8multiplyPKiS0_Pmii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i threads, %ix%i matrix\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU time, %i threads: %f seconds\n"
.size .L.str.1, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%i\t"
.size .L.str.3, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CPU time: %f seconds\n"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU and CPU have different results (at least) at position %i\n"
.size .L.str.6, 62
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "pause"
.size .L.str.8, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPKiS0_Pmii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Array C=B + AB^t + A^t :"
.size .Lstr, 25
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "GPU and CPU have the same results"
.size .Lstr.1, 34
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPKiS0_Pmii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPKiS0_Pmii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0012c4e7_00000000-6_entrega1_1_windows.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10secuentialPKiS0_Pmi
.type _Z10secuentialPKiS0_Pmi, @function
_Z10secuentialPKiS0_Pmi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %ecx, %ebx
imull %ecx, %ebx
testl %ebx, %ebx
jle .L3
movq %rdi, %r10
movq %rsi, %r11
movl %ecx, %edi
movq %rdx, %r9
movslq %ebx, %rbx
movslq %ecx, %rsi
salq $2, %rsi
movl $0, %r8d
.L7:
movl %r8d, %eax
cltd
idivl %edi
movl %edx, %ebp
movl %r8d, %eax
subl %edx, %eax
cltd
idivl %edi
movslq (%r11,%r8,4), %r12
movq %r9, %rcx
movq %r12, (%r9)
movl %ebp, %edx
imull %edi, %edx
leal (%rdx,%rax), %ebp
movslq %ebp, %rbp
movslq (%r10,%rbp,4), %rbp
addq %r12, %rbp
movq %rbp, (%r9)
testl %edi, %edi
jle .L5
imull %edi, %eax
cltq
leaq (%r10,%rax,4), %r12
movslq %edx, %rdx
leaq (%r11,%rdx,4), %rbp
movl $0, %edx
.L6:
movl (%r12,%rdx), %eax
imull 0(%rbp,%rdx), %eax
cltq
addq %rax, (%rcx)
addq $4, %rdx
cmpq %rsi, %rdx
jne .L6
.L5:
addq $1, %r8
addq $8, %r9
cmpq %rbx, %r8
jne .L7
.L3:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10secuentialPKiS0_Pmi, .-_Z10secuentialPKiS0_Pmi
.globl _Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii
.type _Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii, @function
_Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPKiS0_Pmii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii, .-_Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii
.globl _Z8multiplyPKiS0_Pmii
.type _Z8multiplyPKiS0_Pmii, @function
_Z8multiplyPKiS0_Pmii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8multiplyPKiS0_Pmii, .-_Z8multiplyPKiS0_Pmii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%i threads, %ix%i matrix\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "GPU time, %i threads: %f seconds\n"
.section .rodata.str1.1
.LC6:
.string "Array C=B + AB^t + A^t :\n"
.LC7:
.string "%i\t"
.LC8:
.string "\n"
.LC9:
.string "CPU time: %f seconds\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "GPU and CPU have different results (at least) at position %i\n"
.align 8
.LC11:
.string "GPU and CPU have the same results\n"
.section .rodata.str1.1
.LC12:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
cmpl $3, %edi
je .L62
cmpl $4, %edi
je .L63
movl $145924, %edi
call malloc@PLT
movq %rax, %r14
movl $291848, %edi
call malloc@PLT
movq %rax, %rbp
movl $145924, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $291848, %edi
call malloc@PLT
movq %rax, %rbx
movl $1, %r12d
movb $0, 47(%rsp)
movl $36481, 40(%rsp)
movq $291848, 24(%rsp)
movl $145924, %r15d
movl $36481, %r13d
.L48:
movq %r14, %rax
leaq (%r15,%r14), %rdx
.L24:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L24
movq 16(%rsp), %rcx
movq %rcx, %rax
leaq (%rcx,%r15), %rdx
.L25:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L25
.L23:
leaq 56(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq 24(%rsp), %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl %r12d, %r15d
imull %r12d, %r15d
cmpl $512, %r15d
jle .L27
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
mulsd .LC0(%rip), %xmm0
call ceil@PLT
cvttsd2siq %xmm0, %rax
movl %eax, 92(%rsp)
movl %eax, 96(%rsp)
movl $512, %r12d
.L27:
movl 40(%rsp), %eax
pxor %xmm4, %xmm4
cvtsi2ssq %rax, %xmm4
movss %xmm4, 12(%rsp)
pxor %xmm0, %xmm0
ucomiss %xmm4, %xmm0
ja .L57
sqrtss %xmm4, %xmm4
movaps %xmm4, %xmm0
cvttss2sil %xmm4, %eax
movl %eax, 32(%rsp)
.L32:
cvttss2sil %xmm0, %ecx
movl 32(%rsp), %r8d
movl %r15d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, 32(%rsp)
movl %r12d, 80(%rsp)
movl %r12d, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L33:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq 24(%rsp), %rdx
movq 72(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq 32(%rsp), %xmm1
subss %xmm1, %xmm0
divss .LC3(%rip), %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r15d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpb $0, 47(%rsp)
jne .L65
.L34:
call clock@PLT
movq %rax, %r12
pxor %xmm0, %xmm0
movss 12(%rsp), %xmm5
ucomiss %xmm5, %xmm0
ja .L59
sqrtss %xmm5, %xmm5
movaps %xmm5, %xmm0
.L43:
cvttss2sil %xmm0, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call _Z10secuentialPKiS0_Pmi
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r12, %xmm1
subss %xmm1, %xmm0
divss .LC3(%rip), %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 40(%rsp)
je .L44
movl $0, %edx
.L47:
movq (%rbx,%rdx,8), %rax
cmpq %rax, 0(%rbp,%rdx,8)
jne .L66
addq $1, %rdx
cmpq %rdx, %r13
jne .L47
.L44:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L46:
movq %rbx, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq .LC12(%rip), %rdi
call system@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
imull %ebp, %eax
movl %eax, 40(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
movb $0, 47(%rsp)
.L21:
movl 40(%rsp), %r13d
leaq 0(,%r13,4), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
leaq 0(,%r13,8), %rbx
movq %rbx, 24(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r15, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
testq %r13, %r13
jne .L48
jmp .L23
.L63:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
imull %ebp, %eax
movl %eax, 40(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
movq 24(%rbx), %rax
cmpb $118, (%rax)
sete 47(%rsp)
jmp .L21
.L57:
movss 12(%rsp), %xmm0
call sqrtf@PLT
cvttss2sil %xmm0, %eax
movl %eax, 32(%rsp)
movss 12(%rsp), %xmm0
call sqrtf@PLT
jmp .L32
.L64:
movss 12(%rsp), %xmm0
call sqrtf@PLT
cvttss2sil %xmm0, %ecx
movl %r15d, %r8d
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z8multiplyPKiS0_PmiiPKiS0_Pmii
jmp .L33
.L65:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 40(%rsp)
je .L35
movl $1, %r12d
leaq .LC7(%rip), %r15
movq %r14, 24(%rsp)
jmp .L40
.L58:
movss 12(%rsp), %xmm0
call sqrtf@PLT
jmp .L38
.L39:
leaq 1(%r12), %rax
cmpq %r12, %r13
je .L68
movq %rax, %r12
.L40:
movq -8(%rbx,%r12,8), %rdx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %r14d
pxor %xmm3, %xmm3
movss 12(%rsp), %xmm2
ucomiss %xmm2, %xmm3
ja .L58
sqrtss %xmm2, %xmm2
movaps %xmm2, %xmm0
.L38:
cvttss2sil %xmm0, %ecx
movl %r14d, %eax
cltd
idivl %ecx
testl %edx, %edx
jne .L39
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L68:
movq 24(%rsp), %r14
.L35:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L34
.L59:
movss 12(%rsp), %xmm0
call sqrtf@PLT
jmp .L43
.L66:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L46
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z8multiplyPKiS0_Pmii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPKiS0_Pmii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1063256064
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1232348160
.align 4
.LC4:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "entrega1_1_windows.hip"
.globl _Z23__device_stub__multiplyPKiS0_Pmii # -- Begin function _Z23__device_stub__multiplyPKiS0_Pmii
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPKiS0_Pmii,@function
_Z23__device_stub__multiplyPKiS0_Pmii: # @_Z23__device_stub__multiplyPKiS0_Pmii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPKiS0_Pmii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPKiS0_Pmii, .Lfunc_end0-_Z23__device_stub__multiplyPKiS0_Pmii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f60000000000000 # double 0.001953125
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0x49742400 # float 1.0E+6
.LCPI1_2:
.long 0x447a0000 # float 1000
.LCPI1_3:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 64(%rsp)
movq $0, 56(%rsp)
movq $0, 48(%rsp)
cmpl $4, %edi
je .LBB1_4
# %bb.1:
cmpl $3, %edi
jne .LBB1_2
# %bb.3:
movq 8(%rsi), %rdi
xorl %eax, %eax
movq %rax, 88(%rsp) # 8-byte Spill
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
imull %r14d, %r14d
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
jmp .LBB1_6
.LBB1_4:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
imull %r14d, %r14d
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
movq 24(%rbx), %rax
cmpb $118, (%rax)
sete %al
jmp .LBB1_5
.LBB1_2:
movl $36481, %r14d # imm = 0x8E81
movl $1, %eax
movq %rax, 8(%rsp) # 8-byte Spill
xorl %eax, %eax
.LBB1_5:
movq %rax, 88(%rsp) # 8-byte Spill
.LBB1_6:
movq %r14, 80(%rsp) # 8-byte Spill
movl %r14d, %r12d
leaq (,%r12,4), %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
leaq (,%r12,8), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %r13, 32(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
cmpl $0, 80(%rsp) # 4-byte Folded Reload
je .LBB1_11
# %bb.7: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_8: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq %rax, %r12
jne .LBB1_8
# %bb.9: # %.lr.ph108.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_10: # %.lr.ph108
# =>This Inner Loop Header: Depth=1
movl $1, (%r15,%rax,4)
incq %rax
cmpq %rax, %r12
jne .LBB1_10
.LBB1_11: # %._crit_edge
movabsq $4294967297, %r13 # imm = 0x100000001
leaq 64(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
callq hipMalloc
movq 64(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rcx # 8-byte Reload
movl %ecx, %eax
imull %ecx, %eax
cmpl $512, %eax # imm = 0x200
movl %eax, 80(%rsp) # 4-byte Spill
jbe .LBB1_12
# %bb.13:
cvtsi2sd %ecx, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %eax
imulq %rax, %r13
movq %r13, 24(%rsp) # 8-byte Spill
movabsq $2199023256064, %rax # imm = 0x20000000200
movq %rax, 16(%rsp) # 8-byte Spill
jmp .LBB1_14
.LBB1_12:
movq %r13, 24(%rsp) # 8-byte Spill
movl %ecx, %eax
movq %rax, %rcx
shlq $32, %rcx
orq %rax, %rcx
movq %rcx, 16(%rsp) # 8-byte Spill
.LBB1_14:
cvtsi2ss %r12d, %xmm1
sqrtss %xmm1, %xmm2
xorps %xmm3, %xmm3
ucomiss %xmm3, %xmm1
movaps %xmm2, %xmm0
movss %xmm1, 8(%rsp) # 4-byte Spill
jae .LBB1_16
# %bb.15: # %call.sqrt
movaps %xmm1, %xmm0
movss %xmm2, 72(%rsp) # 4-byte Spill
callq sqrtf
xorps %xmm3, %xmm3
movss 72(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
.LBB1_16: # %.split
cvttss2si %xmm0, %ebp
ucomiss %xmm3, %xmm1
jae .LBB1_18
# %bb.17: # %call.sqrt144
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq sqrtf
movaps %xmm0, %xmm2
.LBB1_18: # %.split.split
cvttss2si %xmm2, %ecx
movl $.L.str, %edi
movl 80(%rsp), %r13d # 4-byte Reload
movl %r13d, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
callq clock
movq %rax, %rbp
movq 24(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 16(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_23
# %bb.19:
movq %rbp, 24(%rsp) # 8-byte Spill
movl %r13d, %ebp
movq 64(%rsp), %r13
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
xorps %xmm1, %xmm1
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jb .LBB1_21
# %bb.20:
sqrtss %xmm0, %xmm0
jmp .LBB1_22
.LBB1_21: # %call.sqrt146
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, 72(%rsp) # 8-byte Spill
callq sqrtf
movq 72(%rsp), %rsi # 8-byte Reload
movq 16(%rsp), %rdx # 8-byte Reload
.LBB1_22: # %.split145
cvttss2si %xmm0, %eax
movq %r13, 168(%rsp)
movq %rdx, 160(%rsp)
movq %rsi, 152(%rsp)
movl %eax, 100(%rsp)
movl %ebp, 96(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 100(%rsp), %rax
movq %rax, 200(%rsp)
leaq 96(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
movl %ebp, %r13d
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z8multiplyPKiS0_Pmii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movq 24(%rsp), %rbp # 8-byte Reload
.LBB1_23:
callq hipDeviceSynchronize
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi # 8-byte Reload
movq 32(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %rbp, %xmm1
subss %xmm1, %xmm0
divss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r13d, %esi
movb $1, %al
callq printf
cmpb $0, 88(%rsp) # 1-byte Folded Reload
je .LBB1_32
# %bb.24:
movl $.Lstr, %edi
callq puts@PLT
testq %r12, %r12
je .LBB1_31
# %bb.25: # %.lr.ph111.preheader
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
sqrtss %xmm0, %xmm0
movss %xmm0, 32(%rsp) # 4-byte Spill
xorl %r13d, %r13d
jmp .LBB1_26
.p2align 4, 0x90
.LBB1_28: # %.lr.ph111.split
# in Loop: Header=BB1_26 Depth=1
cvttss2si %xmm0, %ecx
leal 1(%r13), %eax
cltd
idivl %ecx
testl %edx, %edx
je .LBB1_29
.LBB1_30: # in Loop: Header=BB1_26 Depth=1
incq %r13
cmpq %r13, %r12
je .LBB1_31
.LBB1_26: # %.lr.ph111
# =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rax # 8-byte Reload
movq (%rax,%r13,8), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI1_3(%rip), %xmm0
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
jae .LBB1_28
# %bb.27: # %call.sqrt147
# in Loop: Header=BB1_26 Depth=1
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq sqrtf
jmp .LBB1_28
.p2align 4, 0x90
.LBB1_29: # in Loop: Header=BB1_26 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_30
.LBB1_31: # %._crit_edge112
movl $10, %edi
callq putchar@PLT
.LBB1_32:
callq clock
movq %rax, %r13
xorps %xmm1, %xmm1
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jb .LBB1_34
# %bb.33:
sqrtss %xmm0, %xmm0
jmp .LBB1_35
.LBB1_34: # %call.sqrt149
callq sqrtf
.LBB1_35: # %.split148
cvttss2si %xmm0, %esi
testl %esi, %esi
je .LBB1_42
# %bb.36: # %.lr.ph37.i
movl %esi, %edi
imull %edi, %edi
cmpl $1, %edi
adcl $0, %edi
movl %esi, %r8d
xorl %ecx, %ecx
jmp .LBB1_37
.p2align 4, 0x90
.LBB1_41: # in Loop: Header=BB1_37 Depth=1
incq %rcx
cmpq %rdi, %rcx
je .LBB1_42
.LBB1_37: # =>This Loop Header: Depth=1
# Child Loop BB1_39 Depth 2
movl %ecx, %eax
cltd
idivl %esi
# kill: def $eax killed $eax def $rax
# kill: def $edx killed $edx def $rdx
movslq (%r15,%rcx,4), %r10
movq %r10, (%r14,%rcx,8)
imull %esi, %edx
leal (%rax,%rdx), %r9d
movslq %r9d, %r9
movslq (%rbx,%r9,4), %r9
addq %r10, %r9
movq %r9, (%r14,%rcx,8)
testl %esi, %esi
jle .LBB1_41
# %bb.38: # %.lr.ph.i
# in Loop: Header=BB1_37 Depth=1
imull %esi, %eax
movl %edx, %edx
leaq (%rbx,%rax,4), %rax
leaq (%r15,%rdx,4), %rdx
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_39: # Parent Loop BB1_37 Depth=1
# => This Inner Loop Header: Depth=2
movslq (%rax,%r10,4), %r11
movslq (%rdx,%r10,4), %rbp
imulq %r11, %rbp
addq %rbp, %r9
incq %r10
cmpq %r10, %r8
jne .LBB1_39
# %bb.40: # %._crit_edge.i
# in Loop: Header=BB1_37 Depth=1
movq %r9, (%r14,%rcx,8)
jmp .LBB1_41
.LBB1_42: # %_Z10secuentialPKiS0_Pmi.exit
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %r13, %xmm1
subss %xmm1, %xmm0
divss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
testq %r12, %r12
je .LBB1_47
# %bb.43: # %.lr.ph117.preheader
xorl %esi, %esi
movq 40(%rsp), %rcx # 8-byte Reload
.p2align 4, 0x90
.LBB1_44: # %.lr.ph117
# =>This Inner Loop Header: Depth=1
movq (%r14,%rsi,8), %rax
cmpq (%rcx,%rsi,8), %rax
jne .LBB1_45
# %bb.46: # in Loop: Header=BB1_44 Depth=1
incq %rsi
cmpq %rsi, %r12
jne .LBB1_44
.LBB1_47: # %.critedge
movl $.Lstr.1, %edi
callq puts@PLT
jmp .LBB1_48
.LBB1_45:
movl $.L.str.6, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
.LBB1_48:
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movl $.L.str.8, %edi
callq system
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z10secuentialPKiS0_Pmi # -- Begin function _Z10secuentialPKiS0_Pmi
.p2align 4, 0x90
.type _Z10secuentialPKiS0_Pmi,@function
_Z10secuentialPKiS0_Pmi: # @_Z10secuentialPKiS0_Pmi
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
je .LBB2_8
# %bb.1: # %.lr.ph37
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r8
movl %ecx, %r10d
imull %r10d, %r10d
cmpl $1, %r10d
adcl $0, %r10d
movl %ecx, %r11d
xorl %r9d, %r9d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_2 Depth=1
incq %r9
cmpq %r10, %r9
je .LBB2_7
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
movl %r9d, %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
# kill: def $edx killed $edx def $rdx
movslq (%rsi,%r9,4), %rbx
movq %rbx, (%r8,%r9,8)
imull %ecx, %edx
leal (%rax,%rdx), %ebp
movslq %ebp, %r14
movslq (%rdi,%r14,4), %r14
addq %rbx, %r14
movq %r14, (%r8,%r9,8)
testl %ecx, %ecx
jle .LBB2_6
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
imull %ecx, %eax
movq (%r8,%r9,8), %rbx
movl %edx, %edx
leaq (%rdi,%rax,4), %rax
leaq (%rsi,%rdx,4), %rdx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movslq (%rax,%r14,4), %r15
movslq (%rdx,%r14,4), %r12
imulq %r15, %r12
addq %r12, %rbx
incq %r14
cmpq %r14, %r11
jne .LBB2_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq %rbx, (%r8,%r9,8)
jmp .LBB2_6
.LBB2_7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB2_8: # %._crit_edge38
retq
.Lfunc_end2:
.size _Z10secuentialPKiS0_Pmi, .Lfunc_end2-_Z10secuentialPKiS0_Pmi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPKiS0_Pmii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPKiS0_Pmii,@object # @_Z8multiplyPKiS0_Pmii
.section .rodata,"a",@progbits
.globl _Z8multiplyPKiS0_Pmii
.p2align 3, 0x0
_Z8multiplyPKiS0_Pmii:
.quad _Z23__device_stub__multiplyPKiS0_Pmii
.size _Z8multiplyPKiS0_Pmii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i threads, %ix%i matrix\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU time, %i threads: %f seconds\n"
.size .L.str.1, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%i\t"
.size .L.str.3, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CPU time: %f seconds\n"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU and CPU have different results (at least) at position %i\n"
.size .L.str.6, 62
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "pause"
.size .L.str.8, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPKiS0_Pmii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Array C=B + AB^t + A^t :"
.size .Lstr, 25
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "GPU and CPU have the same results"
.size .Lstr.1, 34
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPKiS0_Pmii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPKiS0_Pmii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
//#include <stdio.h>
//#include "Cublas.h"
//
//
//// Allocates a matrix with random float entries.
//void randomInit(float *data, int size)
//{
// for (int i = 0; i < size; ++i)
// data[i] = rand() / (float)RAND_MAX;
//}
//
//
//////////////////////////////////////////////////////////////////////////////////
//// Program main
//////////////////////////////////////////////////////////////////////////////////
//int main(int argc, char **argv)
//{
// int seed = 123;
// int arrayLen = 10;
// printf("Hi");
// curandGenerator_t *g1 = (curandGenerator_t *)malloc(sizeof(curandGenerator_t));
// BSTR res = DllMakeCublasHandle((void **)&g1);
//
// int[] aa = new int
//
//
//
// res = DllDestroyCublasHandle((void *)g1);
//}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
//#include <stdio.h>
//#include "Cublas.h"
//
//
//// Allocates a matrix with random float entries.
//void randomInit(float *data, int size)
//{
// for (int i = 0; i < size; ++i)
// data[i] = rand() / (float)RAND_MAX;
//}
//
//
//////////////////////////////////////////////////////////////////////////////////
//// Program main
//////////////////////////////////////////////////////////////////////////////////
//int main(int argc, char **argv)
//{
// int seed = 123;
// int arrayLen = 10;
// printf("Hi");
// curandGenerator_t *g1 = (curandGenerator_t *)malloc(sizeof(curandGenerator_t));
// BSTR res = DllMakeCublasHandle((void **)&g1);
//
// int[] aa = new int
//
//
//
// res = DllDestroyCublasHandle((void *)g1);
//}
|
.file "tmpxft_00041dd4_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
//#include <stdio.h>
//#include "Cublas.h"
//
//
//// Allocates a matrix with random float entries.
//void randomInit(float *data, int size)
//{
// for (int i = 0; i < size; ++i)
// data[i] = rand() / (float)RAND_MAX;
//}
//
//
//////////////////////////////////////////////////////////////////////////////////
//// Program main
//////////////////////////////////////////////////////////////////////////////////
//int main(int argc, char **argv)
//{
// int seed = 123;
// int arrayLen = 10;
// printf("Hi");
// curandGenerator_t *g1 = (curandGenerator_t *)malloc(sizeof(curandGenerator_t));
// BSTR res = DllMakeCublasHandle((void **)&g1);
//
// int[] aa = new int
//
//
//
// res = DllDestroyCublasHandle((void *)g1);
//}
|
#include <hip/hip_runtime.h>
//#include <stdio.h>
//#include "Cublas.h"
//
//
//// Allocates a matrix with random float entries.
//void randomInit(float *data, int size)
//{
// for (int i = 0; i < size; ++i)
// data[i] = rand() / (float)RAND_MAX;
//}
//
//
//////////////////////////////////////////////////////////////////////////////////
//// Program main
//////////////////////////////////////////////////////////////////////////////////
//int main(int argc, char **argv)
//{
// int seed = 123;
// int arrayLen = 10;
// printf("Hi");
// curandGenerator_t *g1 = (curandGenerator_t *)malloc(sizeof(curandGenerator_t));
// BSTR res = DllMakeCublasHandle((void **)&g1);
//
// int[] aa = new int
//
//
//
// res = DllDestroyCublasHandle((void *)g1);
//}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
//#include <stdio.h>
//#include "Cublas.h"
//
//
//// Allocates a matrix with random float entries.
//void randomInit(float *data, int size)
//{
// for (int i = 0; i < size; ++i)
// data[i] = rand() / (float)RAND_MAX;
//}
//
//
//////////////////////////////////////////////////////////////////////////////////
//// Program main
//////////////////////////////////////////////////////////////////////////////////
//int main(int argc, char **argv)
//{
// int seed = 123;
// int arrayLen = 10;
// printf("Hi");
// curandGenerator_t *g1 = (curandGenerator_t *)malloc(sizeof(curandGenerator_t));
// BSTR res = DllMakeCublasHandle((void **)&g1);
//
// int[] aa = new int
//
//
//
// res = DllDestroyCublasHandle((void *)g1);
//}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
//#include <stdio.h>
//#include "Cublas.h"
//
//
//// Allocates a matrix with random float entries.
//void randomInit(float *data, int size)
//{
// for (int i = 0; i < size; ++i)
// data[i] = rand() / (float)RAND_MAX;
//}
//
//
//////////////////////////////////////////////////////////////////////////////////
//// Program main
//////////////////////////////////////////////////////////////////////////////////
//int main(int argc, char **argv)
//{
// int seed = 123;
// int arrayLen = 10;
// printf("Hi");
// curandGenerator_t *g1 = (curandGenerator_t *)malloc(sizeof(curandGenerator_t));
// BSTR res = DllMakeCublasHandle((void **)&g1);
//
// int[] aa = new int
//
//
//
// res = DllDestroyCublasHandle((void *)g1);
//}
|
.text
.file "main.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00041dd4_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "main.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void getPredicate_kernel(unsigned int * d_inVal, unsigned int * d_predVal, unsigned int numElems, unsigned int bitMask)
{
unsigned int gIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (gIdx < numElems)
{
// if bitmask matches inputvale then assign 1 to the position otherwise set to 0
// we'll need to run an inclusive scan later to get the position
d_predVal[gIdx] = ((d_inVal[gIdx] & bitMask) == bitMask) ? 1 : 0;
//d_npredVal[gIdx] = ((d_inVal[gIdx] & bitMask) == bitMask) ? 0 : 1;
}
}
|
code for sm_80
Function : _Z19getPredicate_kernelPjS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0005 */
/*00b0*/ LOP3.LUT R0, R2, c[0x0][0x174], RZ, 0xc0, !PT ; /* 0x00005d0002007a12 */
/* 0x004fc800078ec0ff */
/*00c0*/ ISETP.NE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fc80003f05270 */
/*00d0*/ SEL R7, RZ, 0x1, P0 ; /* 0x00000001ff077807 */
/* 0x000fca0000000000 */
/*00e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void getPredicate_kernel(unsigned int * d_inVal, unsigned int * d_predVal, unsigned int numElems, unsigned int bitMask)
{
unsigned int gIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (gIdx < numElems)
{
// if bitmask matches inputvale then assign 1 to the position otherwise set to 0
// we'll need to run an inclusive scan later to get the position
d_predVal[gIdx] = ((d_inVal[gIdx] & bitMask) == bitMask) ? 1 : 0;
//d_npredVal[gIdx] = ((d_inVal[gIdx] & bitMask) == bitMask) ? 0 : 1;
}
}
|
.file "tmpxft_001b4714_00000000-6_getPredicate_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z19getPredicate_kernelPjS_jjPjS_jj
.type _Z43__device_stub__Z19getPredicate_kernelPjS_jjPjS_jj, @function
_Z43__device_stub__Z19getPredicate_kernelPjS_jjPjS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19getPredicate_kernelPjS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z19getPredicate_kernelPjS_jjPjS_jj, .-_Z43__device_stub__Z19getPredicate_kernelPjS_jjPjS_jj
.globl _Z19getPredicate_kernelPjS_jj
.type _Z19getPredicate_kernelPjS_jj, @function
_Z19getPredicate_kernelPjS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19getPredicate_kernelPjS_jjPjS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19getPredicate_kernelPjS_jj, .-_Z19getPredicate_kernelPjS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19getPredicate_kernelPjS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19getPredicate_kernelPjS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void getPredicate_kernel(unsigned int * d_inVal, unsigned int * d_predVal, unsigned int numElems, unsigned int bitMask)
{
unsigned int gIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (gIdx < numElems)
{
// if bitmask matches inputvale then assign 1 to the position otherwise set to 0
// we'll need to run an inclusive scan later to get the position
d_predVal[gIdx] = ((d_inVal[gIdx] & bitMask) == bitMask) ? 1 : 0;
//d_npredVal[gIdx] = ((d_inVal[gIdx] & bitMask) == bitMask) ? 0 : 1;
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void getPredicate_kernel(unsigned int * d_inVal, unsigned int * d_predVal, unsigned int numElems, unsigned int bitMask)
{
unsigned int gIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (gIdx < numElems)
{
// if bitmask matches inputvale then assign 1 to the position otherwise set to 0
// we'll need to run an inclusive scan later to get the position
d_predVal[gIdx] = ((d_inVal[gIdx] & bitMask) == bitMask) ? 1 : 0;
//d_npredVal[gIdx] = ((d_inVal[gIdx] & bitMask) == bitMask) ? 0 : 1;
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void getPredicate_kernel(unsigned int * d_inVal, unsigned int * d_predVal, unsigned int numElems, unsigned int bitMask)
{
unsigned int gIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (gIdx < numElems)
{
// if bitmask matches inputvale then assign 1 to the position otherwise set to 0
// we'll need to run an inclusive scan later to get the position
d_predVal[gIdx] = ((d_inVal[gIdx] & bitMask) == bitMask) ? 1 : 0;
//d_npredVal[gIdx] = ((d_inVal[gIdx] & bitMask) == bitMask) ? 0 : 1;
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19getPredicate_kernelPjS_jj
.globl _Z19getPredicate_kernelPjS_jj
.p2align 8
.type _Z19getPredicate_kernelPjS_jj,@function
_Z19getPredicate_kernelPjS_jj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b32 s0, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, s0, v2
v_cmp_eq_u32_e32 vcc_lo, s0, v2
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19getPredicate_kernelPjS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19getPredicate_kernelPjS_jj, .Lfunc_end0-_Z19getPredicate_kernelPjS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19getPredicate_kernelPjS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19getPredicate_kernelPjS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void getPredicate_kernel(unsigned int * d_inVal, unsigned int * d_predVal, unsigned int numElems, unsigned int bitMask)
{
unsigned int gIdx = blockIdx.x * blockDim.x + threadIdx.x;
if (gIdx < numElems)
{
// if bitmask matches inputvale then assign 1 to the position otherwise set to 0
// we'll need to run an inclusive scan later to get the position
d_predVal[gIdx] = ((d_inVal[gIdx] & bitMask) == bitMask) ? 1 : 0;
//d_npredVal[gIdx] = ((d_inVal[gIdx] & bitMask) == bitMask) ? 0 : 1;
}
}
|
.text
.file "getPredicate_kernel.hip"
.globl _Z34__device_stub__getPredicate_kernelPjS_jj # -- Begin function _Z34__device_stub__getPredicate_kernelPjS_jj
.p2align 4, 0x90
.type _Z34__device_stub__getPredicate_kernelPjS_jj,@function
_Z34__device_stub__getPredicate_kernelPjS_jj: # @_Z34__device_stub__getPredicate_kernelPjS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19getPredicate_kernelPjS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__getPredicate_kernelPjS_jj, .Lfunc_end0-_Z34__device_stub__getPredicate_kernelPjS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19getPredicate_kernelPjS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19getPredicate_kernelPjS_jj,@object # @_Z19getPredicate_kernelPjS_jj
.section .rodata,"a",@progbits
.globl _Z19getPredicate_kernelPjS_jj
.p2align 3, 0x0
_Z19getPredicate_kernelPjS_jj:
.quad _Z34__device_stub__getPredicate_kernelPjS_jj
.size _Z19getPredicate_kernelPjS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19getPredicate_kernelPjS_jj"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__getPredicate_kernelPjS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19getPredicate_kernelPjS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z19getPredicate_kernelPjS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0005 */
/*00b0*/ LOP3.LUT R0, R2, c[0x0][0x174], RZ, 0xc0, !PT ; /* 0x00005d0002007a12 */
/* 0x004fc800078ec0ff */
/*00c0*/ ISETP.NE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fc80003f05270 */
/*00d0*/ SEL R7, RZ, 0x1, P0 ; /* 0x00000001ff077807 */
/* 0x000fca0000000000 */
/*00e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19getPredicate_kernelPjS_jj
.globl _Z19getPredicate_kernelPjS_jj
.p2align 8
.type _Z19getPredicate_kernelPjS_jj,@function
_Z19getPredicate_kernelPjS_jj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b32 s0, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, s0, v2
v_cmp_eq_u32_e32 vcc_lo, s0, v2
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19getPredicate_kernelPjS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19getPredicate_kernelPjS_jj, .Lfunc_end0-_Z19getPredicate_kernelPjS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19getPredicate_kernelPjS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19getPredicate_kernelPjS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001b4714_00000000-6_getPredicate_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z19getPredicate_kernelPjS_jjPjS_jj
.type _Z43__device_stub__Z19getPredicate_kernelPjS_jjPjS_jj, @function
_Z43__device_stub__Z19getPredicate_kernelPjS_jjPjS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19getPredicate_kernelPjS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z19getPredicate_kernelPjS_jjPjS_jj, .-_Z43__device_stub__Z19getPredicate_kernelPjS_jjPjS_jj
.globl _Z19getPredicate_kernelPjS_jj
.type _Z19getPredicate_kernelPjS_jj, @function
_Z19getPredicate_kernelPjS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19getPredicate_kernelPjS_jjPjS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19getPredicate_kernelPjS_jj, .-_Z19getPredicate_kernelPjS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19getPredicate_kernelPjS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19getPredicate_kernelPjS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "getPredicate_kernel.hip"
.globl _Z34__device_stub__getPredicate_kernelPjS_jj # -- Begin function _Z34__device_stub__getPredicate_kernelPjS_jj
.p2align 4, 0x90
.type _Z34__device_stub__getPredicate_kernelPjS_jj,@function
_Z34__device_stub__getPredicate_kernelPjS_jj: # @_Z34__device_stub__getPredicate_kernelPjS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19getPredicate_kernelPjS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__getPredicate_kernelPjS_jj, .Lfunc_end0-_Z34__device_stub__getPredicate_kernelPjS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19getPredicate_kernelPjS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19getPredicate_kernelPjS_jj,@object # @_Z19getPredicate_kernelPjS_jj
.section .rodata,"a",@progbits
.globl _Z19getPredicate_kernelPjS_jj
.p2align 3, 0x0
_Z19getPredicate_kernelPjS_jj:
.quad _Z34__device_stub__getPredicate_kernelPjS_jj
.size _Z19getPredicate_kernelPjS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19getPredicate_kernelPjS_jj"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__getPredicate_kernelPjS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19getPredicate_kernelPjS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
// Temporizador de un Kernel
#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
# define N 24
// Funcion que suma de dos vectores de n elementos
__global__
void suma(int *vector_1, int *vector_2, int*vector_suma, int n)
{
// identificador de hilo
int myID = threadIdx.x;
// obtenemos el vector invertido
vector_2[myID] = vector_1[n -1 - myID];
// escritura de resultados
vector_suma[myID] = vector_1[myID] + vector_2[myID];
}
int main(int argc, char** argv) {
// declaraciones
int *hst_vector1, *hst_vector2, *hst_resultado;
int *dev_vector1, *dev_vector2, *dev_resultado;
// reserva en el host
hst_vector1 = (int*)malloc(N * sizeof(int));
hst_vector2 = (int*)malloc(N * sizeof(int));
hst_resultado = (int*)malloc(N * sizeof(int));
// reserva en el device
cudaMalloc((void**)&dev_vector1, N * sizeof(int));
cudaMalloc((void**)&dev_vector2, N * sizeof(int));
cudaMalloc((void**)&dev_resultado, N * sizeof(int));
// inicializacion de vectores
for (int i=0; i<N; i++) {
hst_vector1[i] = rand() % 10;
hst_vector2[i] = 0;
}
printf("> Vector de %d elementos\n", N);
printf("> Lanzamiento con %d bloque de %d hilos\n", 1, N);
// Temporizacion
// Declaracion de eventos
cudaEvent_t start;
cudaEvent_t stop;
// Creacion de eventos
cudaEventCreate(&start);
cudaEventCreate(&stop);
// copia de datos hacia el device
cudaMemcpy(dev_vector1, hst_vector1, N*sizeof(int), cudaMemcpyHostToDevice);
// marca de inicio
cudaEventRecord(start, 0);
// Lanzamos Kernel de un solo bloque y 24 hilos
suma <<< 1, N >>> (dev_vector1, dev_vector2, dev_resultado, N);
// marca de final
cudaEventRecord(stop, 0);
// recogida de datos desde el device
cudaMemcpy(hst_vector2, dev_vector2, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(hst_resultado, dev_resultado, N*sizeof(int), cudaMemcpyDeviceToHost);
// sincronizacion GPU-CPU
cudaEventSynchronize(stop);
// Calculo del tiempo en milisegundos
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("\n> Tiempo de ejecucion: %f ms\n", elapsedTime);
// impresion de resultados
printf("VECTOR 1:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_vector1[i]);
}
printf("\n");
printf("VECTOR 2:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_vector2[i]);
}
printf("\n");
printf("SUMA:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_resultado[i]);
}
printf("\n");
printf("****");
printf("<pulsa [INTRO] para finalizar>");
getchar();
return 0;
}
|
code for sm_80
Function : _Z4sumaPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ LOP3.LUT R0, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff007212 */
/* 0x001fc800078e33ff */
/*0050*/ IADD3 R0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R6, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008067625 */
/* 0x0c0fe200078e0209 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fea000c101904 */
/*00b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ IADD3 R11, R3, R6, RZ ; /* 0x00000006030b7210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// Temporizador de un Kernel
#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
# define N 24
// Funcion que suma de dos vectores de n elementos
__global__
void suma(int *vector_1, int *vector_2, int*vector_suma, int n)
{
// identificador de hilo
int myID = threadIdx.x;
// obtenemos el vector invertido
vector_2[myID] = vector_1[n -1 - myID];
// escritura de resultados
vector_suma[myID] = vector_1[myID] + vector_2[myID];
}
int main(int argc, char** argv) {
// declaraciones
int *hst_vector1, *hst_vector2, *hst_resultado;
int *dev_vector1, *dev_vector2, *dev_resultado;
// reserva en el host
hst_vector1 = (int*)malloc(N * sizeof(int));
hst_vector2 = (int*)malloc(N * sizeof(int));
hst_resultado = (int*)malloc(N * sizeof(int));
// reserva en el device
cudaMalloc((void**)&dev_vector1, N * sizeof(int));
cudaMalloc((void**)&dev_vector2, N * sizeof(int));
cudaMalloc((void**)&dev_resultado, N * sizeof(int));
// inicializacion de vectores
for (int i=0; i<N; i++) {
hst_vector1[i] = rand() % 10;
hst_vector2[i] = 0;
}
printf("> Vector de %d elementos\n", N);
printf("> Lanzamiento con %d bloque de %d hilos\n", 1, N);
// Temporizacion
// Declaracion de eventos
cudaEvent_t start;
cudaEvent_t stop;
// Creacion de eventos
cudaEventCreate(&start);
cudaEventCreate(&stop);
// copia de datos hacia el device
cudaMemcpy(dev_vector1, hst_vector1, N*sizeof(int), cudaMemcpyHostToDevice);
// marca de inicio
cudaEventRecord(start, 0);
// Lanzamos Kernel de un solo bloque y 24 hilos
suma <<< 1, N >>> (dev_vector1, dev_vector2, dev_resultado, N);
// marca de final
cudaEventRecord(stop, 0);
// recogida de datos desde el device
cudaMemcpy(hst_vector2, dev_vector2, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(hst_resultado, dev_resultado, N*sizeof(int), cudaMemcpyDeviceToHost);
// sincronizacion GPU-CPU
cudaEventSynchronize(stop);
// Calculo del tiempo en milisegundos
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("\n> Tiempo de ejecucion: %f ms\n", elapsedTime);
// impresion de resultados
printf("VECTOR 1:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_vector1[i]);
}
printf("\n");
printf("VECTOR 2:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_vector2[i]);
}
printf("\n");
printf("SUMA:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_resultado[i]);
}
printf("\n");
printf("****");
printf("<pulsa [INTRO] para finalizar>");
getchar();
return 0;
}
|
.file "tmpxft_0004c61f_00000000-6_ejemplo5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4sumaPiS_S_iPiS_S_i
.type _Z28__device_stub__Z4sumaPiS_S_iPiS_S_i, @function
_Z28__device_stub__Z4sumaPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sumaPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z4sumaPiS_S_iPiS_S_i, .-_Z28__device_stub__Z4sumaPiS_S_iPiS_S_i
.globl _Z4sumaPiS_S_i
.type _Z4sumaPiS_S_i, @function
_Z4sumaPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4sumaPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4sumaPiS_S_i, .-_Z4sumaPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "> Vector de %d elementos\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "> Lanzamiento con %d bloque de %d hilos\n"
.align 8
.LC2:
.string "\n> Tiempo de ejecucion: %f ms\n"
.section .rodata.str1.1
.LC3:
.string "VECTOR 1:\n"
.LC4:
.string "%.2d "
.LC5:
.string "\n"
.LC6:
.string "VECTOR 2:\n"
.LC7:
.string "SUMA:\n"
.LC8:
.string "****"
.section .rodata.str1.8
.align 8
.LC9:
.string "<pulsa [INTRO] para finalizar>"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $96, %edi
call malloc@PLT
movq %rax, %r12
movl $96, %edi
call malloc@PLT
movq %rax, %rbp
movl $96, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
movl $0, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $96, %rbx
jne .L12
movl $24, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $24, %ecx
movl $1, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movl $96, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $24, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $96, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $96, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbx
addq $96, %r12
leaq .LC4(%rip), %r14
.L14:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $96, %rbp
leaq .LC4(%rip), %r12
.L15:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
addq $96, %r13
leaq .LC4(%rip), %rbp
.L16:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L16
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $24, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z4sumaPiS_S_iPiS_S_i
jmp .L13
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z4sumaPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sumaPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// Temporizador de un Kernel
#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
# define N 24
// Funcion que suma de dos vectores de n elementos
__global__
void suma(int *vector_1, int *vector_2, int*vector_suma, int n)
{
// identificador de hilo
int myID = threadIdx.x;
// obtenemos el vector invertido
vector_2[myID] = vector_1[n -1 - myID];
// escritura de resultados
vector_suma[myID] = vector_1[myID] + vector_2[myID];
}
int main(int argc, char** argv) {
// declaraciones
int *hst_vector1, *hst_vector2, *hst_resultado;
int *dev_vector1, *dev_vector2, *dev_resultado;
// reserva en el host
hst_vector1 = (int*)malloc(N * sizeof(int));
hst_vector2 = (int*)malloc(N * sizeof(int));
hst_resultado = (int*)malloc(N * sizeof(int));
// reserva en el device
cudaMalloc((void**)&dev_vector1, N * sizeof(int));
cudaMalloc((void**)&dev_vector2, N * sizeof(int));
cudaMalloc((void**)&dev_resultado, N * sizeof(int));
// inicializacion de vectores
for (int i=0; i<N; i++) {
hst_vector1[i] = rand() % 10;
hst_vector2[i] = 0;
}
printf("> Vector de %d elementos\n", N);
printf("> Lanzamiento con %d bloque de %d hilos\n", 1, N);
// Temporizacion
// Declaracion de eventos
cudaEvent_t start;
cudaEvent_t stop;
// Creacion de eventos
cudaEventCreate(&start);
cudaEventCreate(&stop);
// copia de datos hacia el device
cudaMemcpy(dev_vector1, hst_vector1, N*sizeof(int), cudaMemcpyHostToDevice);
// marca de inicio
cudaEventRecord(start, 0);
// Lanzamos Kernel de un solo bloque y 24 hilos
suma <<< 1, N >>> (dev_vector1, dev_vector2, dev_resultado, N);
// marca de final
cudaEventRecord(stop, 0);
// recogida de datos desde el device
cudaMemcpy(hst_vector2, dev_vector2, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(hst_resultado, dev_resultado, N*sizeof(int), cudaMemcpyDeviceToHost);
// sincronizacion GPU-CPU
cudaEventSynchronize(stop);
// Calculo del tiempo en milisegundos
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("\n> Tiempo de ejecucion: %f ms\n", elapsedTime);
// impresion de resultados
printf("VECTOR 1:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_vector1[i]);
}
printf("\n");
printf("VECTOR 2:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_vector2[i]);
}
printf("\n");
printf("SUMA:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_resultado[i]);
}
printf("\n");
printf("****");
printf("<pulsa [INTRO] para finalizar>");
getchar();
return 0;
}
|
// Temporizador de un Kernel
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
# define N 24
// Funcion que suma de dos vectores de n elementos
__global__
void suma(int *vector_1, int *vector_2, int*vector_suma, int n)
{
// identificador de hilo
int myID = threadIdx.x;
// obtenemos el vector invertido
vector_2[myID] = vector_1[n -1 - myID];
// escritura de resultados
vector_suma[myID] = vector_1[myID] + vector_2[myID];
}
int main(int argc, char** argv) {
// declaraciones
int *hst_vector1, *hst_vector2, *hst_resultado;
int *dev_vector1, *dev_vector2, *dev_resultado;
// reserva en el host
hst_vector1 = (int*)malloc(N * sizeof(int));
hst_vector2 = (int*)malloc(N * sizeof(int));
hst_resultado = (int*)malloc(N * sizeof(int));
// reserva en el device
hipMalloc((void**)&dev_vector1, N * sizeof(int));
hipMalloc((void**)&dev_vector2, N * sizeof(int));
hipMalloc((void**)&dev_resultado, N * sizeof(int));
// inicializacion de vectores
for (int i=0; i<N; i++) {
hst_vector1[i] = rand() % 10;
hst_vector2[i] = 0;
}
printf("> Vector de %d elementos\n", N);
printf("> Lanzamiento con %d bloque de %d hilos\n", 1, N);
// Temporizacion
// Declaracion de eventos
hipEvent_t start;
hipEvent_t stop;
// Creacion de eventos
hipEventCreate(&start);
hipEventCreate(&stop);
// copia de datos hacia el device
hipMemcpy(dev_vector1, hst_vector1, N*sizeof(int), hipMemcpyHostToDevice);
// marca de inicio
hipEventRecord(start, 0);
// Lanzamos Kernel de un solo bloque y 24 hilos
suma <<< 1, N >>> (dev_vector1, dev_vector2, dev_resultado, N);
// marca de final
hipEventRecord(stop, 0);
// recogida de datos desde el device
hipMemcpy(hst_vector2, dev_vector2, N*sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(hst_resultado, dev_resultado, N*sizeof(int), hipMemcpyDeviceToHost);
// sincronizacion GPU-CPU
hipEventSynchronize(stop);
// Calculo del tiempo en milisegundos
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("\n> Tiempo de ejecucion: %f ms\n", elapsedTime);
// impresion de resultados
printf("VECTOR 1:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_vector1[i]);
}
printf("\n");
printf("VECTOR 2:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_vector2[i]);
}
printf("\n");
printf("SUMA:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_resultado[i]);
}
printf("\n");
printf("****");
printf("<pulsa [INTRO] para finalizar>");
getchar();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
// Temporizador de un Kernel
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
# define N 24
// Funcion que suma de dos vectores de n elementos
__global__
void suma(int *vector_1, int *vector_2, int*vector_suma, int n)
{
// identificador de hilo
int myID = threadIdx.x;
// obtenemos el vector invertido
vector_2[myID] = vector_1[n -1 - myID];
// escritura de resultados
vector_suma[myID] = vector_1[myID] + vector_2[myID];
}
int main(int argc, char** argv) {
// declaraciones
int *hst_vector1, *hst_vector2, *hst_resultado;
int *dev_vector1, *dev_vector2, *dev_resultado;
// reserva en el host
hst_vector1 = (int*)malloc(N * sizeof(int));
hst_vector2 = (int*)malloc(N * sizeof(int));
hst_resultado = (int*)malloc(N * sizeof(int));
// reserva en el device
hipMalloc((void**)&dev_vector1, N * sizeof(int));
hipMalloc((void**)&dev_vector2, N * sizeof(int));
hipMalloc((void**)&dev_resultado, N * sizeof(int));
// inicializacion de vectores
for (int i=0; i<N; i++) {
hst_vector1[i] = rand() % 10;
hst_vector2[i] = 0;
}
printf("> Vector de %d elementos\n", N);
printf("> Lanzamiento con %d bloque de %d hilos\n", 1, N);
// Temporizacion
// Declaracion de eventos
hipEvent_t start;
hipEvent_t stop;
// Creacion de eventos
hipEventCreate(&start);
hipEventCreate(&stop);
// copia de datos hacia el device
hipMemcpy(dev_vector1, hst_vector1, N*sizeof(int), hipMemcpyHostToDevice);
// marca de inicio
hipEventRecord(start, 0);
// Lanzamos Kernel de un solo bloque y 24 hilos
suma <<< 1, N >>> (dev_vector1, dev_vector2, dev_resultado, N);
// marca de final
hipEventRecord(stop, 0);
// recogida de datos desde el device
hipMemcpy(hst_vector2, dev_vector2, N*sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(hst_resultado, dev_resultado, N*sizeof(int), hipMemcpyDeviceToHost);
// sincronizacion GPU-CPU
hipEventSynchronize(stop);
// Calculo del tiempo en milisegundos
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("\n> Tiempo de ejecucion: %f ms\n", elapsedTime);
// impresion de resultados
printf("VECTOR 1:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_vector1[i]);
}
printf("\n");
printf("VECTOR 2:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_vector2[i]);
}
printf("\n");
printf("SUMA:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_resultado[i]);
}
printf("\n");
printf("****");
printf("<pulsa [INTRO] para finalizar>");
getchar();
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sumaPiS_S_i
.globl _Z4sumaPiS_S_i
.p2align 8
.type _Z4sumaPiS_S_i,@function
_Z4sumaPiS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_xad_u32 v1, v0, -1, s2
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[6:7]
global_load_b32 v2, v0, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sumaPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sumaPiS_S_i, .Lfunc_end0-_Z4sumaPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sumaPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z4sumaPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
// Temporizador de un Kernel
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
# define N 24
// Funcion que suma de dos vectores de n elementos
__global__
void suma(int *vector_1, int *vector_2, int*vector_suma, int n)
{
// identificador de hilo
int myID = threadIdx.x;
// obtenemos el vector invertido
vector_2[myID] = vector_1[n -1 - myID];
// escritura de resultados
vector_suma[myID] = vector_1[myID] + vector_2[myID];
}
int main(int argc, char** argv) {
// declaraciones
int *hst_vector1, *hst_vector2, *hst_resultado;
int *dev_vector1, *dev_vector2, *dev_resultado;
// reserva en el host
hst_vector1 = (int*)malloc(N * sizeof(int));
hst_vector2 = (int*)malloc(N * sizeof(int));
hst_resultado = (int*)malloc(N * sizeof(int));
// reserva en el device
hipMalloc((void**)&dev_vector1, N * sizeof(int));
hipMalloc((void**)&dev_vector2, N * sizeof(int));
hipMalloc((void**)&dev_resultado, N * sizeof(int));
// inicializacion de vectores
for (int i=0; i<N; i++) {
hst_vector1[i] = rand() % 10;
hst_vector2[i] = 0;
}
printf("> Vector de %d elementos\n", N);
printf("> Lanzamiento con %d bloque de %d hilos\n", 1, N);
// Temporizacion
// Declaracion de eventos
hipEvent_t start;
hipEvent_t stop;
// Creacion de eventos
hipEventCreate(&start);
hipEventCreate(&stop);
// copia de datos hacia el device
hipMemcpy(dev_vector1, hst_vector1, N*sizeof(int), hipMemcpyHostToDevice);
// marca de inicio
hipEventRecord(start, 0);
// Lanzamos Kernel de un solo bloque y 24 hilos
suma <<< 1, N >>> (dev_vector1, dev_vector2, dev_resultado, N);
// marca de final
hipEventRecord(stop, 0);
// recogida de datos desde el device
hipMemcpy(hst_vector2, dev_vector2, N*sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(hst_resultado, dev_resultado, N*sizeof(int), hipMemcpyDeviceToHost);
// sincronizacion GPU-CPU
hipEventSynchronize(stop);
// Calculo del tiempo en milisegundos
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("\n> Tiempo de ejecucion: %f ms\n", elapsedTime);
// impresion de resultados
printf("VECTOR 1:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_vector1[i]);
}
printf("\n");
printf("VECTOR 2:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_vector2[i]);
}
printf("\n");
printf("SUMA:\n");
for (int i=0; i<N; i++) {
printf("%.2d ", hst_resultado[i]);
}
printf("\n");
printf("****");
printf("<pulsa [INTRO] para finalizar>");
getchar();
return 0;
}
|
.text
.file "ejemplo5.hip"
.globl _Z19__device_stub__sumaPiS_S_i # -- Begin function _Z19__device_stub__sumaPiS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__sumaPiS_S_i,@function
_Z19__device_stub__sumaPiS_S_i: # @_Z19__device_stub__sumaPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sumaPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__sumaPiS_S_i, .Lfunc_end0-_Z19__device_stub__sumaPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $96, %edi
callq malloc
movq %rax, %r15
movl $96, %edi
callq malloc
movq %rax, %r14
movl $96, %edi
callq malloc
movq %rax, %rbx
leaq 48(%rsp), %rdi
movl $96, %esi
callq hipMalloc
leaq 40(%rsp), %rdi
movl $96, %esi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $96, %esi
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r15,%r12,4)
movl $0, (%r14,%r12,4)
incq %r12
cmpq $24, %r12
jne .LBB1_1
# %bb.2:
movl $.L.str, %edi
movl $24, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $1, %esi
movl $24, %edx
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
movl $96, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 23(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $24, 20(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4sumaPiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rsi
movl $96, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movl $96, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $24, %r12
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $24, %r15
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $24, %r14
jne .LBB1_9
# %bb.10:
movl $10, %edi
callq putchar@PLT
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sumaPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4sumaPiS_S_i,@object # @_Z4sumaPiS_S_i
.section .rodata,"a",@progbits
.globl _Z4sumaPiS_S_i
.p2align 3, 0x0
_Z4sumaPiS_S_i:
.quad _Z19__device_stub__sumaPiS_S_i
.size _Z4sumaPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "> Vector de %d elementos\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "> Lanzamiento con %d bloque de %d hilos\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n> Tiempo de ejecucion: %f ms\n"
.size .L.str.2, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%.2d "
.size .L.str.4, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "****"
.size .L.str.8, 5
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "<pulsa [INTRO] para finalizar>"
.size .L.str.9, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4sumaPiS_S_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "VECTOR 1:"
.size .Lstr, 10
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "VECTOR 2:"
.size .Lstr.1, 10
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "SUMA:"
.size .Lstr.2, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__sumaPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4sumaPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z4sumaPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ LOP3.LUT R0, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff007212 */
/* 0x001fc800078e33ff */
/*0050*/ IADD3 R0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000007a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R6, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008067625 */
/* 0x0c0fe200078e0209 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fea000c101904 */
/*00b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ IADD3 R11, R3, R6, RZ ; /* 0x00000006030b7210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sumaPiS_S_i
.globl _Z4sumaPiS_S_i
.p2align 8
.type _Z4sumaPiS_S_i,@function
_Z4sumaPiS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_xad_u32 v1, v0, -1, s2
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[6:7]
global_load_b32 v2, v0, s[4:5]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sumaPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sumaPiS_S_i, .Lfunc_end0-_Z4sumaPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sumaPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z4sumaPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0004c61f_00000000-6_ejemplo5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4sumaPiS_S_iPiS_S_i
.type _Z28__device_stub__Z4sumaPiS_S_iPiS_S_i, @function
_Z28__device_stub__Z4sumaPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sumaPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z4sumaPiS_S_iPiS_S_i, .-_Z28__device_stub__Z4sumaPiS_S_iPiS_S_i
.globl _Z4sumaPiS_S_i
.type _Z4sumaPiS_S_i, @function
_Z4sumaPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4sumaPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4sumaPiS_S_i, .-_Z4sumaPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "> Vector de %d elementos\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "> Lanzamiento con %d bloque de %d hilos\n"
.align 8
.LC2:
.string "\n> Tiempo de ejecucion: %f ms\n"
.section .rodata.str1.1
.LC3:
.string "VECTOR 1:\n"
.LC4:
.string "%.2d "
.LC5:
.string "\n"
.LC6:
.string "VECTOR 2:\n"
.LC7:
.string "SUMA:\n"
.LC8:
.string "****"
.section .rodata.str1.8
.align 8
.LC9:
.string "<pulsa [INTRO] para finalizar>"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $96, %edi
call malloc@PLT
movq %rax, %r12
movl $96, %edi
call malloc@PLT
movq %rax, %rbp
movl $96, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $96, %esi
call cudaMalloc@PLT
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
movl $0, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $96, %rbx
jne .L12
movl $24, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $24, %ecx
movl $1, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movl $96, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $24, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $96, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $96, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbx
addq $96, %r12
leaq .LC4(%rip), %r14
.L14:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $96, %rbp
leaq .LC4(%rip), %r12
.L15:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
addq $96, %r13
leaq .LC4(%rip), %rbp
.L16:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L16
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $24, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z4sumaPiS_S_iPiS_S_i
jmp .L13
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z4sumaPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sumaPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "ejemplo5.hip"
.globl _Z19__device_stub__sumaPiS_S_i # -- Begin function _Z19__device_stub__sumaPiS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__sumaPiS_S_i,@function
_Z19__device_stub__sumaPiS_S_i: # @_Z19__device_stub__sumaPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sumaPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__sumaPiS_S_i, .Lfunc_end0-_Z19__device_stub__sumaPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $96, %edi
callq malloc
movq %rax, %r15
movl $96, %edi
callq malloc
movq %rax, %r14
movl $96, %edi
callq malloc
movq %rax, %rbx
leaq 48(%rsp), %rdi
movl $96, %esi
callq hipMalloc
leaq 40(%rsp), %rdi
movl $96, %esi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $96, %esi
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r15,%r12,4)
movl $0, (%r14,%r12,4)
incq %r12
cmpq $24, %r12
jne .LBB1_1
# %bb.2:
movl $.L.str, %edi
movl $24, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $1, %esi
movl $24, %edx
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
movl $96, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 23(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $24, 20(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4sumaPiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rsi
movl $96, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movl $96, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $24, %r12
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $24, %r15
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $24, %r14
jne .LBB1_9
# %bb.10:
movl $10, %edi
callq putchar@PLT
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sumaPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4sumaPiS_S_i,@object # @_Z4sumaPiS_S_i
.section .rodata,"a",@progbits
.globl _Z4sumaPiS_S_i
.p2align 3, 0x0
_Z4sumaPiS_S_i:
.quad _Z19__device_stub__sumaPiS_S_i
.size _Z4sumaPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "> Vector de %d elementos\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "> Lanzamiento con %d bloque de %d hilos\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n> Tiempo de ejecucion: %f ms\n"
.size .L.str.2, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%.2d "
.size .L.str.4, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "****"
.size .L.str.8, 5
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "<pulsa [INTRO] para finalizar>"
.size .L.str.9, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4sumaPiS_S_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "VECTOR 1:"
.size .Lstr, 10
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "VECTOR 2:"
.size .Lstr.1, 10
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "SUMA:"
.size .Lstr.2, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__sumaPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4sumaPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>
#define MAXN 6000 /* Matrix size */
int numThreads; //number of threads
int numBlocks; //number of blocks
int N; //Matrix Size
int row, col;
/* Matrices */
float A[MAXN*MAXN], B[MAXN*MAXN];
//int *ptrA;
float *ptrA = A;
float *ptrB = B;
size_t sizeOfMatrix = sizeof(float) * N *N;
/* returns a seed for srand based on the time */
unsigned int time_seed() {
struct timeval t;
struct timezone tzdummy;
gettimeofday(&t, &tzdummy);
return (unsigned int)(t.tv_usec);
}
/* Set the program parameters from the command-line arguments */
void parameters(int argc, char **argv) {
int seed = 0; /* Random seed */
// char uid[32]; /*User name */
/* Read command-line arguments */
srand(time_seed()); /* Randomize */
//changed count to 5 so that user can insert number of grid blocks
if (argc == 5) {
seed = atoi(argv[2]);
srand(seed);
numThreads=atoi(argv[3]);
numBlocks=atoi(argv[4]); //insert argument for number of blocks
printf("Random seed = %i\n", seed);
}
if (argc >= 2) {
N = atoi(argv[1]);
// if (N < 1 || N > MAXN) {
// printf("N = %i is out of range.\n", N);
// exit(0);
// }
}
else {
printf("Usage: %s <matrix_dimension> [random seed] [number of threads] [number of blocks]\n",
argv[0]);
exit(0);
}
/* Print parameters */
printf("\nMatrix dimension N = %i.\n", N);
printf("\nNumber of blocks = %i.\n", numBlocks);
printf("\nNumber of threads = %i.\n", numThreads);
}
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[col*N+row] = (float)rand() / 32768.0;
B[col*N+row] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs() {
int row, col;
if (N < 10) {
printf("\nA =\n\t");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
printf("%5.2f%s", A[col*N+row], (col < N-1) ? ", " : ";\n\t");
}
printf("\nB = [");
for (col = 0; col < N; col++) {
printf("%5.2f%s", B[col], (col < N-1) ? "; " : "]\n");
}
}
}
}
//using reduction algorithm to calculate first two steps
__global__ void matrixNorm(float *f_A, float *f_B, int matSize){
float mu, sigma;
//declare the dimensions x-axis and y-axis (row and col)
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
// int index = col + row * n;
//we want to check to make sure we don't have an excess number of threads
if(row<matSize && col<matSize){
for(col = 0; col < matSize; col++){
mu = 0.0;
for(row = 0; row < matSize; row++)
mu+= f_A[matSize * col + row];
mu /= (float) matSize;
//you cannot calculate sigma without the mean, so we need some synchronization heree
//to make sure threads have calculated the mean before getting to this step
__syncthreads();
sigma = 0.0;
for(row = 0; row < matSize; row++){
sigma += powf(f_A[matSize*col+row] - mu, 2.0);
sigma /= (float) matSize;
sigma = sqrt(sigma);
//again, we need to make sure that sigma has been calculated in order to result the normalized matrix
__syncthreads();
for (row = 0; row < matSize; row++){
if(sigma == 0.0)
f_B[matSize*col+row] = 0.0;
else
f_B[matSize*col+row] = (f_A[matSize*col+row] - mu) / sigma;
}
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval etstart, etstop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
//unsigned long long runtime;
unsigned long long usecstart, usecstop;
struct tms cputstart, cputstop;
/* Process program parameters */
parameters(argc, argv);
/* Initialize A and B */
initialize_inputs();
/* Print input matrices */
print_inputs();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&etstart, &tzdummy);
times(&cputstart);
/* declare arrays */
/* Allocate memory of the matrix in device and copy the matrix from host to device to do work */
//first, declare size of the matrix
sizeOfMatrix = N * N * sizeof(float);
//create pointer to matrix
float *f_A, *f_B;
//cuda malloc the matrix (make room for it in memory
cudaMalloc((void**)&f_A, sizeOfMatrix);
cudaMalloc((void**)&f_B, sizeOfMatrix);
//initialize start and stop
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//copy data from host to device
cudaMemcpy(f_A, &ptrA, sizeOfMatrix, cudaMemcpyHostToDevice);
//*m_A = &A[N][N];
cudaMemcpy(f_B, &ptrB, sizeOfMatrix, cudaMemcpyHostToDevice);
//use cuda checks to make sure the allocation was successful
cudaEventRecord(start);
/* Matrix Normalization */
matrixNorm<<<numBlocks, numThreads>>>(f_A, f_B, N);
cudaMemcpy(&ptrB, f_B, sizeOfMatrix, cudaMemcpyDeviceToHost);
cudaError_t err = cudaGetLastError();
if(err != cudaSuccess){
printf("CUDA Error: %s\n", cudaGetErrorString(err));
exit(-1);
}
cudaEventRecord(stop);
/* Free Cuda */
cudaFree(f_A);
cudaFree(f_B);
/* Stop Clock */
//gettimeofday(&stop, &tzdummy);
// runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
/* Stop Clock CPU Times */
gettimeofday(&etstop, &tzdummy);
times(&cputstop);
printf("Stopped clock.\n");
usecstart = (unsigned long long)etstart.tv_sec * 1000000 + etstart.tv_usec;
usecstop = (unsigned long long)etstop.tv_sec * 1000000 + etstop.tv_usec;
/* Display timing results */
//printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
/* Display other timing results */
printf("\nElapsed time = %g ms.\n",
(float)(usecstop - usecstart)/(float)1000);
printf("(CPU times are accurate to the nearest %g ms)\n",
1.0/(float)CLOCKS_PER_SEC * 1000.0);
printf("My total CPU time for parent = %g ms.\n",
(float)( (cputstop.tms_utime + cputstop.tms_stime) -
(cputstart.tms_utime + cputstart.tms_stime) ) /
(float)CLOCKS_PER_SEC * 1000);
printf("My system CPU time for parent = %g ms.\n",
(float)(cputstop.tms_stime - cputstart.tms_stime) /
(float)CLOCKS_PER_SEC * 1000);
printf("My total CPU time for child processes = %g ms.\n",
(float)( (cputstop.tms_cutime + cputstop.tms_cstime) -
(cputstart.tms_cutime + cputstart.tms_cstime) ) /
(float)CLOCKS_PER_SEC * 1000);
/* Contrary to the man pages, this appears not to include the parent */
printf("--------------------------------------------\n");
exit(0);
}
|
.file "tmpxft_001276bc_00000000-6_matrixNorm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9time_seedv
.type _Z9time_seedv, @function
_Z9time_seedv:
.LFB2070:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
movl 24(%rsp), %eax
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z9time_seedv, .-_Z9time_seedv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Random seed = %i\n"
.LC1:
.string "\nMatrix dimension N = %i.\n"
.LC2:
.string "\nNumber of blocks = %i.\n"
.LC3:
.string "\nNumber of threads = %i.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Usage: %s <matrix_dimension> [random seed] [number of threads] [number of blocks]\n"
.text
.globl _Z10parametersiPPc
.type _Z10parametersiPPc, @function
_Z10parametersiPPc:
.LFB2071:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movq %rsi, %rbp
call _Z9time_seedv
movl %eax, %edi
call srand@PLT
cmpl $5, %ebx
je .L13
cmpl $1, %ebx
jg .L9
movq 0(%rbp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L13:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
movl %eax, %edi
call srand@PLT
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, numThreads(%rip)
movq 32(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, numBlocks(%rip)
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L9:
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edx
movl %eax, N(%rip)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl numBlocks(%rip), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl numThreads(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z10parametersiPPc, .-_Z10parametersiPPc
.globl _Z17initialize_inputsv
.type _Z17initialize_inputsv, @function
_Z17initialize_inputsv:
.LFB2072:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0, %ebp
leaq A(%rip), %r13
leaq B(%rip), %r12
cmpl $0, N(%rip)
jg .L15
.L14:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call rand@PLT
movl %eax, %ecx
movl N(%rip), %edx
movl %edx, %eax
imull %ebx, %eax
addl %ebp, %eax
cltq
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss .LC5(%rip), %xmm0
movss %xmm0, 0(%r13,%rax,4)
movl $0x00000000, (%r12,%rax,4)
addl $1, %ebx
cmpl %ebx, %edx
jg .L17
.L18:
addl $1, %ebp
cmpl %ebp, N(%rip)
jle .L14
.L15:
movl $0, %ebx
cmpl $0, N(%rip)
jg .L17
jmp .L18
.cfi_endproc
.LFE2072:
.size _Z17initialize_inputsv, .-_Z17initialize_inputsv
.section .rodata.str1.1
.LC7:
.string ", "
.LC8:
.string ";\n\t"
.LC9:
.string "; "
.LC10:
.string "]\n"
.LC11:
.string "\nA =\n\t"
.LC12:
.string "%5.2f%s"
.LC13:
.string "\nB = ["
.text
.globl _Z12print_inputsv
.type _Z12print_inputsv, @function
_Z12print_inputsv:
.LFB2073:
.cfi_startproc
endbr64
cmpl $9, N(%rip)
jle .L46
ret
.L46:
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq A(%rip), %r15
leaq .LC12(%rip), %rbp
cmpl $0, N(%rip)
jg .L27
.L25:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
leal -1(%rax), %edx
cmpl %ebx, %edx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rcx
cmovle %rcx, %rdx
imull %ebx, %eax
addl %r12d, %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rax,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
movl N(%rip), %eax
cmpl %ebx, %eax
jg .L29
.L33:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl N(%rip), %eax
testl %eax, %eax
jle .L30
movl $0, %ebx
leaq .LC10(%rip), %r14
leaq B(%rip), %r13
.L32:
subl $1, %eax
cmpl %ebx, %eax
leaq .LC9(%rip), %rdx
cmovle %r14, %rdx
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl N(%rip), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L32
.L30:
addl $1, %r12d
cmpl %r12d, N(%rip)
jle .L25
.L27:
movl N(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L29
jmp .L33
.cfi_endproc
.LFE2073:
.size _Z12print_inputsv, .-_Z12print_inputsv
.globl _Z33__device_stub__Z10matrixNormPfS_iPfS_i
.type _Z33__device_stub__Z10matrixNormPfS_iPfS_i, @function
_Z33__device_stub__Z10matrixNormPfS_iPfS_i:
.LFB2099:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixNormPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2099:
.size _Z33__device_stub__Z10matrixNormPfS_iPfS_i, .-_Z33__device_stub__Z10matrixNormPfS_iPfS_i
.globl _Z10matrixNormPfS_i
.type _Z10matrixNormPfS_i, @function
_Z10matrixNormPfS_i:
.LFB2100:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10matrixNormPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _Z10matrixNormPfS_i, .-_Z10matrixNormPfS_i
.section .rodata.str1.8
.align 8
.LC14:
.string "\n---------------------------------------------\n"
.section .rodata.str1.1
.LC15:
.string "Matrix size N = %d"
.LC16:
.string "\nStarting clock.\n\n"
.LC17:
.string "CUDA Error: %s\n"
.LC18:
.string "Stopped clock.\n"
.LC19:
.string "\nStopped clock."
.LC21:
.string "\nElapsed time = %g ms.\n"
.section .rodata.str1.8
.align 8
.LC23:
.string "(CPU times are accurate to the nearest %g ms)\n"
.align 8
.LC25:
.string "My total CPU time for parent = %g ms.\n"
.align 8
.LC26:
.string "My system CPU time for parent = %g ms.\n"
.align 8
.LC27:
.string "My total CPU time for child processes = %g ms.\n"
.align 8
.LC28:
.string "--------------------------------------------\n"
.text
.globl main
.type main, @function
main:
.LFB2074:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $160, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
call _Z10parametersiPPc
call _Z17initialize_inputsv
call _Z12print_inputsv
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl N(%rip), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
leaq 80(%rsp), %rdi
call times@PLT
movl N(%rip), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $2, %rsi
movq %rsi, sizeOfMatrix(%rip)
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq sizeOfMatrix(%rip), %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movq sizeOfMatrix(%rip), %rdx
leaq ptrA(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq sizeOfMatrix(%rip), %rdx
leaq ptrB(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl numThreads(%rip), %eax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl numBlocks(%rip), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L56:
movl $2, %ecx
movq sizeOfMatrix(%rip), %rdx
movq 16(%rsp), %rsi
leaq ptrB(%rip), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
je .L57
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L62:
movl N(%rip), %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z10matrixNormPfS_iPfS_i
jmp .L56
.L57:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 40(%rsp), %rsi
leaq 64(%rsp), %rdi
call gettimeofday@PLT
leaq 112(%rsp), %rdi
call times@PLT
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
imulq $1000000, 48(%rsp), %r12
movq 72(%rsp), %rbx
imulq $1000000, 64(%rsp), %rbp
subq 56(%rsp), %rbp
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq (%rbx,%rbp), %rax
subq %r12, %rax
js .L58
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L59:
divss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC22(%rip), %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 120(%rsp), %rax
addq 112(%rsp), %rax
subq 88(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC24(%rip), %xmm0
mulss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 120(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC24(%rip), %xmm0
mulss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 136(%rsp), %rax
addq 128(%rsp), %rax
subq 104(%rsp), %rax
subq 96(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC24(%rip), %xmm0
mulss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L58:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L59
.cfi_endproc
.LFE2074:
.size main, .-main
.section .rodata.str1.1
.LC29:
.string "_Z10matrixNormPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2102:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixNormPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2102:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_numThreads, @function
_GLOBAL__sub_I_numThreads:
.LFB2219:
.cfi_startproc
endbr64
movslq N(%rip), %rax
imulq %rax, %rax
salq $2, %rax
movq %rax, sizeOfMatrix(%rip)
ret
.cfi_endproc
.LFE2219:
.size _GLOBAL__sub_I_numThreads, .-_GLOBAL__sub_I_numThreads
.section .init_array
.align 8
.quad _GLOBAL__sub_I_numThreads
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl sizeOfMatrix
.bss
.align 8
.type sizeOfMatrix, @object
.size sizeOfMatrix, 8
sizeOfMatrix:
.zero 8
.globl ptrB
.section .data.rel.local,"aw"
.align 8
.type ptrB, @object
.size ptrB, 8
ptrB:
.quad B
.globl ptrA
.align 8
.type ptrA, @object
.size ptrA, 8
ptrA:
.quad A
.globl B
.bss
.align 32
.type B, @object
.size B, 144000000
B:
.zero 144000000
.globl A
.align 32
.type A, @object
.size A, 144000000
A:
.zero 144000000
.globl col
.align 4
.type col, @object
.size col, 4
col:
.zero 4
.globl row
.align 4
.type row, @object
.size row, 4
row:
.zero 4
.globl N
.align 4
.type N, @object
.size N, 4
N:
.zero 4
.globl numBlocks
.align 4
.type numBlocks, @object
.size numBlocks, 4
numBlocks:
.zero 4
.globl numThreads
.align 4
.type numThreads, @object
.size numThreads, 4
numThreads:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 939524096
.align 4
.LC20:
.long 1148846080
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC22:
.long -755914244
.long 1062232653
.section .rodata.cst4
.align 4
.LC24:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>
#define MAXN 6000 /* Matrix size */
int numThreads; //number of threads
int numBlocks; //number of blocks
int N; //Matrix Size
int row, col;
/* Matrices */
float A[MAXN*MAXN], B[MAXN*MAXN];
//int *ptrA;
float *ptrA = A;
float *ptrB = B;
size_t sizeOfMatrix = sizeof(float) * N *N;
/* returns a seed for srand based on the time */
unsigned int time_seed() {
struct timeval t;
struct timezone tzdummy;
gettimeofday(&t, &tzdummy);
return (unsigned int)(t.tv_usec);
}
/* Set the program parameters from the command-line arguments */
void parameters(int argc, char **argv) {
int seed = 0; /* Random seed */
// char uid[32]; /*User name */
/* Read command-line arguments */
srand(time_seed()); /* Randomize */
//changed count to 5 so that user can insert number of grid blocks
if (argc == 5) {
seed = atoi(argv[2]);
srand(seed);
numThreads=atoi(argv[3]);
numBlocks=atoi(argv[4]); //insert argument for number of blocks
printf("Random seed = %i\n", seed);
}
if (argc >= 2) {
N = atoi(argv[1]);
// if (N < 1 || N > MAXN) {
// printf("N = %i is out of range.\n", N);
// exit(0);
// }
}
else {
printf("Usage: %s <matrix_dimension> [random seed] [number of threads] [number of blocks]\n",
argv[0]);
exit(0);
}
/* Print parameters */
printf("\nMatrix dimension N = %i.\n", N);
printf("\nNumber of blocks = %i.\n", numBlocks);
printf("\nNumber of threads = %i.\n", numThreads);
}
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[col*N+row] = (float)rand() / 32768.0;
B[col*N+row] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs() {
int row, col;
if (N < 10) {
printf("\nA =\n\t");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
printf("%5.2f%s", A[col*N+row], (col < N-1) ? ", " : ";\n\t");
}
printf("\nB = [");
for (col = 0; col < N; col++) {
printf("%5.2f%s", B[col], (col < N-1) ? "; " : "]\n");
}
}
}
}
//using reduction algorithm to calculate first two steps
__global__ void matrixNorm(float *f_A, float *f_B, int matSize){
float mu, sigma;
//declare the dimensions x-axis and y-axis (row and col)
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
// int index = col + row * n;
//we want to check to make sure we don't have an excess number of threads
if(row<matSize && col<matSize){
for(col = 0; col < matSize; col++){
mu = 0.0;
for(row = 0; row < matSize; row++)
mu+= f_A[matSize * col + row];
mu /= (float) matSize;
//you cannot calculate sigma without the mean, so we need some synchronization heree
//to make sure threads have calculated the mean before getting to this step
__syncthreads();
sigma = 0.0;
for(row = 0; row < matSize; row++){
sigma += powf(f_A[matSize*col+row] - mu, 2.0);
sigma /= (float) matSize;
sigma = sqrt(sigma);
//again, we need to make sure that sigma has been calculated in order to result the normalized matrix
__syncthreads();
for (row = 0; row < matSize; row++){
if(sigma == 0.0)
f_B[matSize*col+row] = 0.0;
else
f_B[matSize*col+row] = (f_A[matSize*col+row] - mu) / sigma;
}
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval etstart, etstop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
//unsigned long long runtime;
unsigned long long usecstart, usecstop;
struct tms cputstart, cputstop;
/* Process program parameters */
parameters(argc, argv);
/* Initialize A and B */
initialize_inputs();
/* Print input matrices */
print_inputs();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&etstart, &tzdummy);
times(&cputstart);
/* declare arrays */
/* Allocate memory of the matrix in device and copy the matrix from host to device to do work */
//first, declare size of the matrix
sizeOfMatrix = N * N * sizeof(float);
//create pointer to matrix
float *f_A, *f_B;
//cuda malloc the matrix (make room for it in memory
cudaMalloc((void**)&f_A, sizeOfMatrix);
cudaMalloc((void**)&f_B, sizeOfMatrix);
//initialize start and stop
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//copy data from host to device
cudaMemcpy(f_A, &ptrA, sizeOfMatrix, cudaMemcpyHostToDevice);
//*m_A = &A[N][N];
cudaMemcpy(f_B, &ptrB, sizeOfMatrix, cudaMemcpyHostToDevice);
//use cuda checks to make sure the allocation was successful
cudaEventRecord(start);
/* Matrix Normalization */
matrixNorm<<<numBlocks, numThreads>>>(f_A, f_B, N);
cudaMemcpy(&ptrB, f_B, sizeOfMatrix, cudaMemcpyDeviceToHost);
cudaError_t err = cudaGetLastError();
if(err != cudaSuccess){
printf("CUDA Error: %s\n", cudaGetErrorString(err));
exit(-1);
}
cudaEventRecord(stop);
/* Free Cuda */
cudaFree(f_A);
cudaFree(f_B);
/* Stop Clock */
//gettimeofday(&stop, &tzdummy);
// runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
/* Stop Clock CPU Times */
gettimeofday(&etstop, &tzdummy);
times(&cputstop);
printf("Stopped clock.\n");
usecstart = (unsigned long long)etstart.tv_sec * 1000000 + etstart.tv_usec;
usecstop = (unsigned long long)etstop.tv_sec * 1000000 + etstop.tv_usec;
/* Display timing results */
//printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
/* Display other timing results */
printf("\nElapsed time = %g ms.\n",
(float)(usecstop - usecstart)/(float)1000);
printf("(CPU times are accurate to the nearest %g ms)\n",
1.0/(float)CLOCKS_PER_SEC * 1000.0);
printf("My total CPU time for parent = %g ms.\n",
(float)( (cputstop.tms_utime + cputstop.tms_stime) -
(cputstart.tms_utime + cputstart.tms_stime) ) /
(float)CLOCKS_PER_SEC * 1000);
printf("My system CPU time for parent = %g ms.\n",
(float)(cputstop.tms_stime - cputstart.tms_stime) /
(float)CLOCKS_PER_SEC * 1000);
printf("My total CPU time for child processes = %g ms.\n",
(float)( (cputstop.tms_cutime + cputstop.tms_cstime) -
(cputstart.tms_cutime + cputstart.tms_cstime) ) /
(float)CLOCKS_PER_SEC * 1000);
/* Contrary to the man pages, this appears not to include the parent */
printf("--------------------------------------------\n");
exit(0);
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>
#define MAXN 6000 /* Matrix size */
int numThreads; //number of threads
int numBlocks; //number of blocks
int N; //Matrix Size
int row, col;
/* Matrices */
float A[MAXN*MAXN], B[MAXN*MAXN];
//int *ptrA;
float *ptrA = A;
float *ptrB = B;
size_t sizeOfMatrix = sizeof(float) * N *N;
/* returns a seed for srand based on the time */
unsigned int time_seed() {
struct timeval t;
struct timezone tzdummy;
gettimeofday(&t, &tzdummy);
return (unsigned int)(t.tv_usec);
}
/* Set the program parameters from the command-line arguments */
void parameters(int argc, char **argv) {
int seed = 0; /* Random seed */
// char uid[32]; /*User name */
/* Read command-line arguments */
srand(time_seed()); /* Randomize */
//changed count to 5 so that user can insert number of grid blocks
if (argc == 5) {
seed = atoi(argv[2]);
srand(seed);
numThreads=atoi(argv[3]);
numBlocks=atoi(argv[4]); //insert argument for number of blocks
printf("Random seed = %i\n", seed);
}
if (argc >= 2) {
N = atoi(argv[1]);
// if (N < 1 || N > MAXN) {
// printf("N = %i is out of range.\n", N);
// exit(0);
// }
}
else {
printf("Usage: %s <matrix_dimension> [random seed] [number of threads] [number of blocks]\n",
argv[0]);
exit(0);
}
/* Print parameters */
printf("\nMatrix dimension N = %i.\n", N);
printf("\nNumber of blocks = %i.\n", numBlocks);
printf("\nNumber of threads = %i.\n", numThreads);
}
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[col*N+row] = (float)rand() / 32768.0;
B[col*N+row] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs() {
int row, col;
if (N < 10) {
printf("\nA =\n\t");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
printf("%5.2f%s", A[col*N+row], (col < N-1) ? ", " : ";\n\t");
}
printf("\nB = [");
for (col = 0; col < N; col++) {
printf("%5.2f%s", B[col], (col < N-1) ? "; " : "]\n");
}
}
}
}
//using reduction algorithm to calculate first two steps
__global__ void matrixNorm(float *f_A, float *f_B, int matSize){
float mu, sigma;
//declare the dimensions x-axis and y-axis (row and col)
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
// int index = col + row * n;
//we want to check to make sure we don't have an excess number of threads
if(row<matSize && col<matSize){
for(col = 0; col < matSize; col++){
mu = 0.0;
for(row = 0; row < matSize; row++)
mu+= f_A[matSize * col + row];
mu /= (float) matSize;
//you cannot calculate sigma without the mean, so we need some synchronization heree
//to make sure threads have calculated the mean before getting to this step
__syncthreads();
sigma = 0.0;
for(row = 0; row < matSize; row++){
sigma += powf(f_A[matSize*col+row] - mu, 2.0);
sigma /= (float) matSize;
sigma = sqrt(sigma);
//again, we need to make sure that sigma has been calculated in order to result the normalized matrix
__syncthreads();
for (row = 0; row < matSize; row++){
if(sigma == 0.0)
f_B[matSize*col+row] = 0.0;
else
f_B[matSize*col+row] = (f_A[matSize*col+row] - mu) / sigma;
}
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval etstart, etstop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
//unsigned long long runtime;
unsigned long long usecstart, usecstop;
struct tms cputstart, cputstop;
/* Process program parameters */
parameters(argc, argv);
/* Initialize A and B */
initialize_inputs();
/* Print input matrices */
print_inputs();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&etstart, &tzdummy);
times(&cputstart);
/* declare arrays */
/* Allocate memory of the matrix in device and copy the matrix from host to device to do work */
//first, declare size of the matrix
sizeOfMatrix = N * N * sizeof(float);
//create pointer to matrix
float *f_A, *f_B;
//cuda malloc the matrix (make room for it in memory
hipMalloc((void**)&f_A, sizeOfMatrix);
hipMalloc((void**)&f_B, sizeOfMatrix);
//initialize start and stop
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
//copy data from host to device
hipMemcpy(f_A, &ptrA, sizeOfMatrix, hipMemcpyHostToDevice);
//*m_A = &A[N][N];
hipMemcpy(f_B, &ptrB, sizeOfMatrix, hipMemcpyHostToDevice);
//use cuda checks to make sure the allocation was successful
hipEventRecord(start);
/* Matrix Normalization */
matrixNorm<<<numBlocks, numThreads>>>(f_A, f_B, N);
hipMemcpy(&ptrB, f_B, sizeOfMatrix, hipMemcpyDeviceToHost);
hipError_t err = hipGetLastError();
if(err != hipSuccess){
printf("CUDA Error: %s\n", hipGetErrorString(err));
exit(-1);
}
hipEventRecord(stop);
/* Free Cuda */
hipFree(f_A);
hipFree(f_B);
/* Stop Clock */
//gettimeofday(&stop, &tzdummy);
// runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
/* Stop Clock CPU Times */
gettimeofday(&etstop, &tzdummy);
times(&cputstop);
printf("Stopped clock.\n");
usecstart = (unsigned long long)etstart.tv_sec * 1000000 + etstart.tv_usec;
usecstop = (unsigned long long)etstop.tv_sec * 1000000 + etstop.tv_usec;
/* Display timing results */
//printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
/* Display other timing results */
printf("\nElapsed time = %g ms.\n",
(float)(usecstop - usecstart)/(float)1000);
printf("(CPU times are accurate to the nearest %g ms)\n",
1.0/(float)CLOCKS_PER_SEC * 1000.0);
printf("My total CPU time for parent = %g ms.\n",
(float)( (cputstop.tms_utime + cputstop.tms_stime) -
(cputstart.tms_utime + cputstart.tms_stime) ) /
(float)CLOCKS_PER_SEC * 1000);
printf("My system CPU time for parent = %g ms.\n",
(float)(cputstop.tms_stime - cputstart.tms_stime) /
(float)CLOCKS_PER_SEC * 1000);
printf("My total CPU time for child processes = %g ms.\n",
(float)( (cputstop.tms_cutime + cputstop.tms_cstime) -
(cputstart.tms_cutime + cputstart.tms_cstime) ) /
(float)CLOCKS_PER_SEC * 1000);
/* Contrary to the man pages, this appears not to include the parent */
printf("--------------------------------------------\n");
exit(0);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>
#define MAXN 6000 /* Matrix size */
int numThreads; //number of threads
int numBlocks; //number of blocks
int N; //Matrix Size
int row, col;
/* Matrices */
float A[MAXN*MAXN], B[MAXN*MAXN];
//int *ptrA;
float *ptrA = A;
float *ptrB = B;
size_t sizeOfMatrix = sizeof(float) * N *N;
/* returns a seed for srand based on the time */
unsigned int time_seed() {
struct timeval t;
struct timezone tzdummy;
gettimeofday(&t, &tzdummy);
return (unsigned int)(t.tv_usec);
}
/* Set the program parameters from the command-line arguments */
void parameters(int argc, char **argv) {
int seed = 0; /* Random seed */
// char uid[32]; /*User name */
/* Read command-line arguments */
srand(time_seed()); /* Randomize */
//changed count to 5 so that user can insert number of grid blocks
if (argc == 5) {
seed = atoi(argv[2]);
srand(seed);
numThreads=atoi(argv[3]);
numBlocks=atoi(argv[4]); //insert argument for number of blocks
printf("Random seed = %i\n", seed);
}
if (argc >= 2) {
N = atoi(argv[1]);
// if (N < 1 || N > MAXN) {
// printf("N = %i is out of range.\n", N);
// exit(0);
// }
}
else {
printf("Usage: %s <matrix_dimension> [random seed] [number of threads] [number of blocks]\n",
argv[0]);
exit(0);
}
/* Print parameters */
printf("\nMatrix dimension N = %i.\n", N);
printf("\nNumber of blocks = %i.\n", numBlocks);
printf("\nNumber of threads = %i.\n", numThreads);
}
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[col*N+row] = (float)rand() / 32768.0;
B[col*N+row] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs() {
int row, col;
if (N < 10) {
printf("\nA =\n\t");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
printf("%5.2f%s", A[col*N+row], (col < N-1) ? ", " : ";\n\t");
}
printf("\nB = [");
for (col = 0; col < N; col++) {
printf("%5.2f%s", B[col], (col < N-1) ? "; " : "]\n");
}
}
}
}
//using reduction algorithm to calculate first two steps
__global__ void matrixNorm(float *f_A, float *f_B, int matSize){
float mu, sigma;
//declare the dimensions x-axis and y-axis (row and col)
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
// int index = col + row * n;
//we want to check to make sure we don't have an excess number of threads
if(row<matSize && col<matSize){
for(col = 0; col < matSize; col++){
mu = 0.0;
for(row = 0; row < matSize; row++)
mu+= f_A[matSize * col + row];
mu /= (float) matSize;
//you cannot calculate sigma without the mean, so we need some synchronization heree
//to make sure threads have calculated the mean before getting to this step
__syncthreads();
sigma = 0.0;
for(row = 0; row < matSize; row++){
sigma += powf(f_A[matSize*col+row] - mu, 2.0);
sigma /= (float) matSize;
sigma = sqrt(sigma);
//again, we need to make sure that sigma has been calculated in order to result the normalized matrix
__syncthreads();
for (row = 0; row < matSize; row++){
if(sigma == 0.0)
f_B[matSize*col+row] = 0.0;
else
f_B[matSize*col+row] = (f_A[matSize*col+row] - mu) / sigma;
}
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval etstart, etstop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
//unsigned long long runtime;
unsigned long long usecstart, usecstop;
struct tms cputstart, cputstop;
/* Process program parameters */
parameters(argc, argv);
/* Initialize A and B */
initialize_inputs();
/* Print input matrices */
print_inputs();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&etstart, &tzdummy);
times(&cputstart);
/* declare arrays */
/* Allocate memory of the matrix in device and copy the matrix from host to device to do work */
//first, declare size of the matrix
sizeOfMatrix = N * N * sizeof(float);
//create pointer to matrix
float *f_A, *f_B;
//cuda malloc the matrix (make room for it in memory
hipMalloc((void**)&f_A, sizeOfMatrix);
hipMalloc((void**)&f_B, sizeOfMatrix);
//initialize start and stop
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
//copy data from host to device
hipMemcpy(f_A, &ptrA, sizeOfMatrix, hipMemcpyHostToDevice);
//*m_A = &A[N][N];
hipMemcpy(f_B, &ptrB, sizeOfMatrix, hipMemcpyHostToDevice);
//use cuda checks to make sure the allocation was successful
hipEventRecord(start);
/* Matrix Normalization */
matrixNorm<<<numBlocks, numThreads>>>(f_A, f_B, N);
hipMemcpy(&ptrB, f_B, sizeOfMatrix, hipMemcpyDeviceToHost);
hipError_t err = hipGetLastError();
if(err != hipSuccess){
printf("CUDA Error: %s\n", hipGetErrorString(err));
exit(-1);
}
hipEventRecord(stop);
/* Free Cuda */
hipFree(f_A);
hipFree(f_B);
/* Stop Clock */
//gettimeofday(&stop, &tzdummy);
// runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
/* Stop Clock CPU Times */
gettimeofday(&etstop, &tzdummy);
times(&cputstop);
printf("Stopped clock.\n");
usecstart = (unsigned long long)etstart.tv_sec * 1000000 + etstart.tv_usec;
usecstop = (unsigned long long)etstop.tv_sec * 1000000 + etstop.tv_usec;
/* Display timing results */
//printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
/* Display other timing results */
printf("\nElapsed time = %g ms.\n",
(float)(usecstop - usecstart)/(float)1000);
printf("(CPU times are accurate to the nearest %g ms)\n",
1.0/(float)CLOCKS_PER_SEC * 1000.0);
printf("My total CPU time for parent = %g ms.\n",
(float)( (cputstop.tms_utime + cputstop.tms_stime) -
(cputstart.tms_utime + cputstart.tms_stime) ) /
(float)CLOCKS_PER_SEC * 1000);
printf("My system CPU time for parent = %g ms.\n",
(float)(cputstop.tms_stime - cputstart.tms_stime) /
(float)CLOCKS_PER_SEC * 1000);
printf("My total CPU time for child processes = %g ms.\n",
(float)( (cputstop.tms_cutime + cputstop.tms_cstime) -
(cputstart.tms_cutime + cputstart.tms_cstime) ) /
(float)CLOCKS_PER_SEC * 1000);
/* Contrary to the man pages, this appears not to include the parent */
printf("--------------------------------------------\n");
exit(0);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixNormPfS_i
.globl _Z10matrixNormPfS_i
.p2align 8
.type _Z10matrixNormPfS_i,@function
_Z10matrixNormPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_13
s_load_b32 s3, s[4:5], 0xc
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s14, s3, v[0:1]
s_mov_b32 s14, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v0, 0, v1
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_13
s_load_b128 s[4:7], s[0:1], 0x0
v_cvt_f32_i32_e32 v0, s2
v_mov_b32_e32 v1, 0
s_ashr_i32 s3, s2, 31
s_mov_b32 s15, 0x3e76c4e1
s_lshl_b64 s[8:9], s[2:3], 2
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[10:11], s[4:5]
s_branch .LBB0_4
.LBB0_3:
s_add_i32 s3, s3, 1
s_add_u32 s10, s10, s8
s_addc_u32 s11, s11, s9
s_add_i32 s14, s14, s2
s_cmp_lg_u32 s3, s2
s_cbranch_scc0 .LBB0_13
.LBB0_4:
v_mov_b32_e32 v2, 0
s_mov_b64 s[0:1], s[10:11]
s_mov_b32 s12, s2
.LBB0_5:
global_load_b32 v3, v1, s[0:1]
s_add_i32 s12, s12, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s12, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
s_cbranch_scc1 .LBB0_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v0, v0, v2
v_div_scale_f32 v6, vcc_lo, v2, v0, v2
s_mul_i32 s16, s3, s2
v_rcp_f32_e32 v4, v3
s_mov_b32 s0, 0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v3, v0, v2
v_mov_b32_e32 v3, 0
s_branch .LBB0_8
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_add_i32 s0, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s0, s2
s_cbranch_scc0 .LBB0_3
.LBB0_8:
s_add_i32 s0, s0, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 31
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
global_load_b32 v4, v1, s[0:1]
s_waitcnt vmcnt(0)
v_sub_f32_e32 v4, v4, v2
v_frexp_mant_f32_e64 v5, |v4|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
v_ldexp_f32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, -1.0, v5
v_add_f32_e32 v6, 1.0, v5
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v11, v6, v9 :: v_dual_add_f32 v10, -1.0, v6
v_fma_f32 v6, v9, v6, -v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v10
v_fmac_f32_e32 v6, v9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v11, v6
v_dual_sub_f32 v10, v8, v5 :: v_dual_sub_f32 v11, v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v11, v6
v_sub_f32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v8, v5
v_add_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v10, v5
v_mul_f32_e32 v5, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v9, v5
v_mul_f32_e32 v8, v6, v6
v_sub_f32_e32 v7, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v5, v5, v7
v_fma_f32 v7, v6, v6, -v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v5, v5
v_fmac_f32_e32 v7, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v8, v7
v_fmaak_f32 v10, s15, v9, 0x3e91f4c4
v_sub_f32_e32 v8, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v10, v9, v10, 0x3ecccdef :: v_dual_sub_f32 v7, v7, v8
v_mul_f32_e32 v11, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, v9, v10, -v11
v_fmac_f32_e32 v8, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v11, v8
v_dual_sub_f32 v11, v10, v11 :: v_dual_add_f32 v12, 0x3f2aaaaa, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v13, v6, v9 :: v_dual_sub_f32 v8, v8, v11
v_fma_f32 v14, v9, v6, -v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v11, 0xbf2aaaaa, v12
v_add_f32_e32 v8, 0x31739010, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v14, v9, v5
v_sub_f32_e32 v10, v10, v11
v_ldexp_f32 v5, v5, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v14, v7, v6
v_ldexp_f32 v6, v6, 1
v_add_f32_e32 v9, v13, v14
v_add_f32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v12, v8
v_sub_f32_e32 v10, v12, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v11, v9, v7
v_sub_f32_e32 v12, v9, v13
v_add_f32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v10, v9, v7, -v11
v_sub_f32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v10, v9, v8
v_frexp_exp_i32_f32_e32 v8, v4
v_fmac_f32_e32 v10, v12, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 1.0, v4
v_add_f32_e32 v8, v11, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v7, v7
v_sub_f32_e32 v11, v8, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v12, 0x3f317218, v7 :: v_dual_add_f32 v9, v6, v8
v_sub_f32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, v7, 0x3f317218, -v12
v_add_f32_e32 v5, v5, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v11, 0xb102e308, v7 :: v_dual_sub_f32 v6, v9, v6
v_sub_f32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v6
v_dual_add_f32 v7, v9, v5 :: v_dual_add_f32 v6, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v7, v9 :: v_dual_add_f32 v8, v6, v7
v_dual_sub_f32 v5, v5, v9 :: v_dual_sub_f32 v10, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v13, v8, v10
v_dual_sub_f32 v7, v7, v10 :: v_dual_sub_f32 v12, v6, v12
v_dual_sub_f32 v6, v6, v13 :: v_dual_sub_f32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v7, v6
v_add_f32_e32 v9, v11, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v7, v9, v11
v_add_f32_e32 v6, v9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v9, v7
v_sub_f32_e32 v5, v5, v7
v_dual_sub_f32 v7, v11, v9 :: v_dual_add_f32 v10, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v5, v5, v7 :: v_dual_sub_f32 v8, v10, v8
v_cndmask_b32_e64 v7, 2.0, 1.0, vcc_lo
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v6
v_add_f32_e32 v6, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v7, v6
v_sub_f32_e32 v8, v6, v10
v_fma_f32 v6, v7, v6, -v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v5, v8
v_cmp_class_f32_e64 vcc_lo, v9, 0x204
v_fmac_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v9, v6
v_cndmask_b32_e32 v8, v5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v8
v_cndmask_b32_e64 v10, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v8|
v_sub_f32_e32 v11, v8, v10
v_trunc_f32_e32 v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, 0x3fb8aa3b, v11
v_fma_f32 v13, v11, 0x3fb8aa3b, -v12
v_rndne_f32_e32 v14, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v13, 0x32a5705f, v11 :: v_dual_sub_f32 v12, v12, v14
v_add_f32_e32 v12, v12, v13
v_sub_f32_e32 v5, v5, v9
v_cvt_i32_f32_e32 v9, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_exp_f32_e32 v12, v12
v_sub_f32_e32 v5, v6, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v12, v9
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mul_f32 v9, 0.5, v7 :: v_dual_cndmask_b32 v6, 0, v6
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
v_trunc_f32_e32 v12, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_add_f32 v5, v10, v5 :: v_dual_cndmask_b32 v6, 0x7f800000, v6
v_cmp_eq_f32_e32 vcc_lo, v8, v7
v_cmp_neq_f32_e64 s0, v12, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v5, v6, v5, v6
v_cmp_eq_f32_e64 s1, 0x7f800000, v6
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_cndmask_b32_e64 v7, 1.0, v4, s0
s_waitcnt_vscnt null, 0x0
s_barrier
v_cndmask_b32_e64 v5, v5, v6, s1
v_cmp_eq_f32_e64 s1, 0, v4
buffer_gl0_inv
v_bfi_b32 v5, 0x7fffffff, v5, v7
v_cndmask_b32_e64 v6, 0x7f800000, 0, s1
v_cndmask_b32_e64 v7, 0, v4, s0
v_cmp_class_f32_e64 s0, v4, 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v8, 0x7fc00000, v5, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v4
v_bfi_b32 v6, 0x7fffffff, v6, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
s_or_b32 vcc_lo, s1, s0
s_mov_b32 s1, 0
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, 0x7fc00000, v5, vcc_lo
v_add_f32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v0, v0, v3
v_div_scale_f32 v7, vcc_lo, v3, v0, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v3, v4, v0, v3
v_mul_f32_e32 v4, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v4, v3
v_fma_f32 v8, -v6, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v7
v_cndmask_b32_e64 v4, v4, v5, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v8
v_cndmask_b32_e64 v4, v4, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x37800000, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
v_cmp_neq_f32_e64 s0, 0, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_11
.p2align 6
.LBB0_9:
s_lshl_b64 s[18:19], s[12:13], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_u32 s18, s4, s18
s_addc_u32 s19, s5, s19
global_load_b32 v4, v1, s[18:19]
s_waitcnt vmcnt(0)
v_sub_f32_e32 v4, v4, v2
v_div_scale_f32 v5, null, v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v7, vcc_lo, v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v7, v6
v_fma_f32 v9, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v6
v_fma_f32 v5, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v6, v8
v_div_fixup_f32 v4, v5, v3, v4
.LBB0_10:
s_lshl_b64 s[12:13], s[12:13], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s12, s6, s12
s_addc_u32 s13, s7, s13
s_add_i32 s1, s1, 1
global_store_b32 v1, v4, s[12:13]
s_cmp_lg_u32 s2, s1
s_cbranch_scc0 .LBB0_7
.LBB0_11:
s_add_i32 s12, s14, s1
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_ashr_i32 s13, s12, 31
s_cbranch_vccz .LBB0_9
v_mov_b32_e32 v4, 0
s_branch .LBB0_10
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixNormPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixNormPfS_i, .Lfunc_end0-_Z10matrixNormPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixNormPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z10matrixNormPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>
#define MAXN 6000 /* Matrix size */
int numThreads; //number of threads
int numBlocks; //number of blocks
int N; //Matrix Size
int row, col;
/* Matrices */
float A[MAXN*MAXN], B[MAXN*MAXN];
//int *ptrA;
float *ptrA = A;
float *ptrB = B;
size_t sizeOfMatrix = sizeof(float) * N *N;
/* returns a seed for srand based on the time */
unsigned int time_seed() {
struct timeval t;
struct timezone tzdummy;
gettimeofday(&t, &tzdummy);
return (unsigned int)(t.tv_usec);
}
/* Set the program parameters from the command-line arguments */
void parameters(int argc, char **argv) {
int seed = 0; /* Random seed */
// char uid[32]; /*User name */
/* Read command-line arguments */
srand(time_seed()); /* Randomize */
//changed count to 5 so that user can insert number of grid blocks
if (argc == 5) {
seed = atoi(argv[2]);
srand(seed);
numThreads=atoi(argv[3]);
numBlocks=atoi(argv[4]); //insert argument for number of blocks
printf("Random seed = %i\n", seed);
}
if (argc >= 2) {
N = atoi(argv[1]);
// if (N < 1 || N > MAXN) {
// printf("N = %i is out of range.\n", N);
// exit(0);
// }
}
else {
printf("Usage: %s <matrix_dimension> [random seed] [number of threads] [number of blocks]\n",
argv[0]);
exit(0);
}
/* Print parameters */
printf("\nMatrix dimension N = %i.\n", N);
printf("\nNumber of blocks = %i.\n", numBlocks);
printf("\nNumber of threads = %i.\n", numThreads);
}
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[col*N+row] = (float)rand() / 32768.0;
B[col*N+row] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs() {
int row, col;
if (N < 10) {
printf("\nA =\n\t");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
printf("%5.2f%s", A[col*N+row], (col < N-1) ? ", " : ";\n\t");
}
printf("\nB = [");
for (col = 0; col < N; col++) {
printf("%5.2f%s", B[col], (col < N-1) ? "; " : "]\n");
}
}
}
}
//using reduction algorithm to calculate first two steps
__global__ void matrixNorm(float *f_A, float *f_B, int matSize){
float mu, sigma;
//declare the dimensions x-axis and y-axis (row and col)
int row = blockDim.y * blockIdx.y + threadIdx.y;
int col = blockDim.x * blockIdx.x + threadIdx.x;
// int index = col + row * n;
//we want to check to make sure we don't have an excess number of threads
if(row<matSize && col<matSize){
for(col = 0; col < matSize; col++){
mu = 0.0;
for(row = 0; row < matSize; row++)
mu+= f_A[matSize * col + row];
mu /= (float) matSize;
//you cannot calculate sigma without the mean, so we need some synchronization heree
//to make sure threads have calculated the mean before getting to this step
__syncthreads();
sigma = 0.0;
for(row = 0; row < matSize; row++){
sigma += powf(f_A[matSize*col+row] - mu, 2.0);
sigma /= (float) matSize;
sigma = sqrt(sigma);
//again, we need to make sure that sigma has been calculated in order to result the normalized matrix
__syncthreads();
for (row = 0; row < matSize; row++){
if(sigma == 0.0)
f_B[matSize*col+row] = 0.0;
else
f_B[matSize*col+row] = (f_A[matSize*col+row] - mu) / sigma;
}
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval etstart, etstop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
//unsigned long long runtime;
unsigned long long usecstart, usecstop;
struct tms cputstart, cputstop;
/* Process program parameters */
parameters(argc, argv);
/* Initialize A and B */
initialize_inputs();
/* Print input matrices */
print_inputs();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&etstart, &tzdummy);
times(&cputstart);
/* declare arrays */
/* Allocate memory of the matrix in device and copy the matrix from host to device to do work */
//first, declare size of the matrix
sizeOfMatrix = N * N * sizeof(float);
//create pointer to matrix
float *f_A, *f_B;
//cuda malloc the matrix (make room for it in memory
hipMalloc((void**)&f_A, sizeOfMatrix);
hipMalloc((void**)&f_B, sizeOfMatrix);
//initialize start and stop
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
//copy data from host to device
hipMemcpy(f_A, &ptrA, sizeOfMatrix, hipMemcpyHostToDevice);
//*m_A = &A[N][N];
hipMemcpy(f_B, &ptrB, sizeOfMatrix, hipMemcpyHostToDevice);
//use cuda checks to make sure the allocation was successful
hipEventRecord(start);
/* Matrix Normalization */
matrixNorm<<<numBlocks, numThreads>>>(f_A, f_B, N);
hipMemcpy(&ptrB, f_B, sizeOfMatrix, hipMemcpyDeviceToHost);
hipError_t err = hipGetLastError();
if(err != hipSuccess){
printf("CUDA Error: %s\n", hipGetErrorString(err));
exit(-1);
}
hipEventRecord(stop);
/* Free Cuda */
hipFree(f_A);
hipFree(f_B);
/* Stop Clock */
//gettimeofday(&stop, &tzdummy);
// runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
/* Stop Clock CPU Times */
gettimeofday(&etstop, &tzdummy);
times(&cputstop);
printf("Stopped clock.\n");
usecstart = (unsigned long long)etstart.tv_sec * 1000000 + etstart.tv_usec;
usecstop = (unsigned long long)etstop.tv_sec * 1000000 + etstop.tv_usec;
/* Display timing results */
//printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
/* Display other timing results */
printf("\nElapsed time = %g ms.\n",
(float)(usecstop - usecstart)/(float)1000);
printf("(CPU times are accurate to the nearest %g ms)\n",
1.0/(float)CLOCKS_PER_SEC * 1000.0);
printf("My total CPU time for parent = %g ms.\n",
(float)( (cputstop.tms_utime + cputstop.tms_stime) -
(cputstart.tms_utime + cputstart.tms_stime) ) /
(float)CLOCKS_PER_SEC * 1000);
printf("My system CPU time for parent = %g ms.\n",
(float)(cputstop.tms_stime - cputstart.tms_stime) /
(float)CLOCKS_PER_SEC * 1000);
printf("My total CPU time for child processes = %g ms.\n",
(float)( (cputstop.tms_cutime + cputstop.tms_cstime) -
(cputstart.tms_cutime + cputstart.tms_cstime) ) /
(float)CLOCKS_PER_SEC * 1000);
/* Contrary to the man pages, this appears not to include the parent */
printf("--------------------------------------------\n");
exit(0);
}
|
.text
.file "matrixNorm.hip"
.globl _Z9time_seedv # -- Begin function _Z9time_seedv
.p2align 4, 0x90
.type _Z9time_seedv,@function
_Z9time_seedv: # @_Z9time_seedv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
movl 8(%rsp), %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9time_seedv, .Lfunc_end0-_Z9time_seedv
.cfi_endproc
# -- End function
.globl _Z10parametersiPPc # -- Begin function _Z10parametersiPPc
.p2align 4, 0x90
.type _Z10parametersiPPc,@function
_Z10parametersiPPc: # @_Z10parametersiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
callq gettimeofday
movl 16(%rsp), %edi
callq srand
cmpl $5, %ebp
jne .LBB1_2
# %bb.1:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl %r14d, %edi
callq srand
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, numThreads(%rip)
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, numBlocks(%rip)
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
.LBB1_2:
cmpl $2, %ebp
jl .LBB1_4
# %bb.3:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, N(%rip)
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl numBlocks(%rip), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl numThreads(%rip), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB1_4:
.cfi_def_cfa_offset 64
movq (%rbx), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z10parametersiPPc, .Lfunc_end1-_Z10parametersiPPc
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17initialize_inputsv
.LCPI2_0:
.long 0x38000000 # float 3.05175781E-5
.text
.globl _Z17initialize_inputsv
.p2align 4, 0x90
.type _Z17initialize_inputsv,@function
_Z17initialize_inputsv: # @_Z17initialize_inputsv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
cmpl $0, N(%rip)
jg .LBB2_1
.LBB2_5: # %._crit_edge11
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.p2align 4, 0x90
.LBB2_4: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
.cfi_def_cfa_offset 32
incl %ebx
cmpl N(%rip), %ebx
jge .LBB2_5
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
cmpl $0, N(%rip)
jle .LBB2_4
# %bb.2: # %.lr.ph.preheader
# in Loop: Header=BB2_1 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movl N(%rip), %eax
imull %ebp, %eax
addl %ebx, %eax
cltq
movss %xmm0, A(,%rax,4)
movl $0, B(,%rax,4)
incl %ebp
cmpl N(%rip), %ebp
jl .LBB2_3
jmp .LBB2_4
.Lfunc_end2:
.size _Z17initialize_inputsv, .Lfunc_end2-_Z17initialize_inputsv
.cfi_endproc
# -- End function
.globl _Z12print_inputsv # -- Begin function _Z12print_inputsv
.p2align 4, 0x90
.type _Z12print_inputsv,@function
_Z12print_inputsv: # @_Z12print_inputsv
.cfi_startproc
# %bb.0:
cmpl $9, N(%rip)
jg .LBB3_11
# %bb.1:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
cmpl $0, N(%rip)
jle .LBB3_10
# %bb.2: # %.preheader.preheader
movl $.L.str.7, %ebx
movl $.L.str.10, %r14d
xorl %ebp, %ebp
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_9: # %._crit_edge18
# in Loop: Header=BB3_3 Depth=1
incl %ebp
cmpl N(%rip), %ebp
jge .LBB3_10
.LBB3_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
# Child Loop BB3_8 Depth 2
movl N(%rip), %eax
testl %eax, %eax
jle .LBB3_6
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB3_3 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph
# Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movl %eax, %ecx
imull %r15d, %ecx
addl %ebp, %ecx
movslq %ecx, %rcx
movss A(,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
decl %eax
cmpl %eax, %r15d
movl $.L.str.8, %esi
cmovlq %rbx, %rsi
movl $.L.str.6, %edi
movb $1, %al
callq printf
incl %r15d
movl N(%rip), %eax
cmpl %eax, %r15d
jl .LBB3_5
.LBB3_6: # %._crit_edge
# in Loop: Header=BB3_3 Depth=1
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl N(%rip), %eax
testl %eax, %eax
jle .LBB3_9
# %bb.7: # %.lr.ph17.preheader
# in Loop: Header=BB3_3 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_8: # %.lr.ph17
# Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movss B(,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
decl %eax
cltq
cmpq %rax, %r15
movl $.L.str.11, %esi
cmovlq %r14, %rsi
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r15
movslq N(%rip), %rax
cmpq %rax, %r15
jl .LBB3_8
jmp .LBB3_9
.LBB3_10:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB3_11: # %.loopexit
retq
.Lfunc_end3:
.size _Z12print_inputsv, .Lfunc_end3-_Z12print_inputsv
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matrixNormPfS_i # -- Begin function _Z25__device_stub__matrixNormPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixNormPfS_i,@function
_Z25__device_stub__matrixNormPfS_i: # @_Z25__device_stub__matrixNormPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixNormPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z25__device_stub__matrixNormPfS_i, .Lfunc_end4-_Z25__device_stub__matrixNormPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x38000000 # float 3.05175781E-5
.LCPI5_1:
.long 0x447a0000 # float 1000
.LCPI5_3:
.long 0x49742400 # float 1.0E+6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_2:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $208, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
callq _Z10parametersiPPc
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
cmpl $0, N(%rip)
jg .LBB5_1
.LBB5_5: # %_Z17initialize_inputsv.exit
callq _Z12print_inputsv
movl $.Lstr.3, %edi
callq puts@PLT
movl N(%rip), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
leaq 160(%rsp), %rdi
leaq 152(%rsp), %rsi
callq gettimeofday
leaq 176(%rsp), %rdi
callq times
movl N(%rip), %esi
imull %esi, %esi
shlq $2, %rsi
movq %rsi, sizeOfMatrix(%rip)
leaq 16(%rsp), %rdi
callq hipMalloc
movq sizeOfMatrix(%rip), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
movq sizeOfMatrix(%rip), %rdx
movl $ptrA, %esi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq sizeOfMatrix(%rip), %rdx
movl $ptrB, %esi
movl $1, %ecx
callq hipMemcpy
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl numBlocks(%rip), %edi
movl numThreads(%rip), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl N(%rip), %edx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %edx, 28(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 28(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10matrixNormPfS_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_7:
movq 8(%rsp), %rsi
movq sizeOfMatrix(%rip), %rdx
movl $ptrB, %edi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB5_12
# %bb.8:
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
leaq 32(%rsp), %rdi
leaq 152(%rsp), %rsi
callq gettimeofday
leaq 48(%rsp), %rdi
callq times
movl $.Lstr.2, %edi
callq puts@PLT
movq 32(%rsp), %rbx
movq 40(%rsp), %r14
subq 160(%rsp), %rbx
subq 168(%rsp), %r14
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
imulq $1000000, %rbx, %rax # imm = 0xF4240
addq %r14, %rax
js .LBB5_9
# %bb.10:
cvtsi2ss %rax, %xmm0
jmp .LBB5_11
.p2align 4, 0x90
.LBB5_4: # %._crit_edge.i
# in Loop: Header=BB5_1 Depth=1
incl %ebx
cmpl N(%rip), %ebx
jge .LBB5_5
.LBB5_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
cmpl $0, N(%rip)
jle .LBB5_4
# %bb.2: # %.lr.ph.i.preheader
# in Loop: Header=BB5_1 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_3: # %.lr.ph.i
# Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI5_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movl N(%rip), %eax
movl %eax, %ecx
imull %ebp, %ecx
addl %ebx, %ecx
movslq %ecx, %rcx
movss %xmm0, A(,%rcx,4)
movl $0, B(,%rcx,4)
incl %ebp
cmpl %eax, %ebp
jl .LBB5_3
jmp .LBB5_4
.LBB5_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB5_9:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB5_11:
divss .LCPI5_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
movsd .LCPI5_2(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.19, %edi
movb $1, %al
callq printf
movq 56(%rsp), %rbx
movq 184(%rsp), %r14
movq 48(%rsp), %rax
addq %rbx, %rax
movq 176(%rsp), %rcx
addq %r14, %rcx
subq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI5_3(%rip), %xmm0
mulss .LCPI5_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.20, %edi
movb $1, %al
callq printf
subq %r14, %rbx
xorps %xmm0, %xmm0
cvtsi2ss %rbx, %xmm0
divss .LCPI5_3(%rip), %xmm0
mulss .LCPI5_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.21, %edi
movb $1, %al
callq printf
movq 72(%rsp), %rax
movq 192(%rsp), %rcx
addq 64(%rsp), %rax
addq 200(%rsp), %rcx
subq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI5_3(%rip), %xmm0
mulss .LCPI5_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.22, %edi
movb $1, %al
callq printf
movl $.Lstr.4, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixNormPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type numThreads,@object # @numThreads
.bss
.globl numThreads
.p2align 2, 0x0
numThreads:
.long 0 # 0x0
.size numThreads, 4
.type numBlocks,@object # @numBlocks
.globl numBlocks
.p2align 2, 0x0
numBlocks:
.long 0 # 0x0
.size numBlocks, 4
.type N,@object # @N
.globl N
.p2align 2, 0x0
N:
.long 0 # 0x0
.size N, 4
.type row,@object # @row
.globl row
.p2align 2, 0x0
row:
.long 0 # 0x0
.size row, 4
.type col,@object # @col
.globl col
.p2align 2, 0x0
col:
.long 0 # 0x0
.size col, 4
.type A,@object # @A
.globl A
.p2align 4, 0x0
A:
.zero 144000000
.size A, 144000000
.type B,@object # @B
.globl B
.p2align 4, 0x0
B:
.zero 144000000
.size B, 144000000
.type ptrA,@object # @ptrA
.data
.globl ptrA
.p2align 3, 0x0
ptrA:
.quad A
.size ptrA, 8
.type ptrB,@object # @ptrB
.globl ptrB
.p2align 3, 0x0
ptrB:
.quad B
.size ptrB, 8
.type sizeOfMatrix,@object # @sizeOfMatrix
.bss
.globl sizeOfMatrix
.p2align 3, 0x0
sizeOfMatrix:
.quad 0 # 0x0
.size sizeOfMatrix, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Random seed = %i\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Usage: %s <matrix_dimension> [random seed] [number of threads] [number of blocks]\n"
.size .L.str.1, 83
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nMatrix dimension N = %i.\n"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nNumber of blocks = %i.\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nNumber of threads = %i.\n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nA =\n\t"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%5.2f%s"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz ", "
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nB = ["
.size .L.str.9, 7
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "
.size .L.str.10, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "]\n"
.size .L.str.11, 3
.type _Z10matrixNormPfS_i,@object # @_Z10matrixNormPfS_i
.section .rodata,"a",@progbits
.globl _Z10matrixNormPfS_i
.p2align 3, 0x0
_Z10matrixNormPfS_i:
.quad _Z25__device_stub__matrixNormPfS_i
.size _Z10matrixNormPfS_i, 8
.type .L.str.13,@object # @.str.13
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.13:
.asciz "Matrix size N = %d"
.size .L.str.13, 19
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "CUDA Error: %s\n"
.size .L.str.15, 16
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "\nStopped clock."
.size .L.str.17, 16
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "\nElapsed time = %g ms.\n"
.size .L.str.18, 24
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "(CPU times are accurate to the nearest %g ms)\n"
.size .L.str.19, 47
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "My total CPU time for parent = %g ms.\n"
.size .L.str.20, 39
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "My system CPU time for parent = %g ms.\n"
.size .L.str.21, 40
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "My total CPU time for child processes = %g ms.\n"
.size .L.str.22, 48
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixNormPfS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\nStarting clock.\n"
.size .Lstr.1, 18
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Stopped clock."
.size .Lstr.2, 15
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n---------------------------------------------"
.size .Lstr.3, 47
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "--------------------------------------------"
.size .Lstr.4, 45
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixNormPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym A
.addrsig_sym B
.addrsig_sym ptrA
.addrsig_sym ptrB
.addrsig_sym _Z10matrixNormPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001276bc_00000000-6_matrixNorm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9time_seedv
.type _Z9time_seedv, @function
_Z9time_seedv:
.LFB2070:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
movl 24(%rsp), %eax
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z9time_seedv, .-_Z9time_seedv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Random seed = %i\n"
.LC1:
.string "\nMatrix dimension N = %i.\n"
.LC2:
.string "\nNumber of blocks = %i.\n"
.LC3:
.string "\nNumber of threads = %i.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Usage: %s <matrix_dimension> [random seed] [number of threads] [number of blocks]\n"
.text
.globl _Z10parametersiPPc
.type _Z10parametersiPPc, @function
_Z10parametersiPPc:
.LFB2071:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movq %rsi, %rbp
call _Z9time_seedv
movl %eax, %edi
call srand@PLT
cmpl $5, %ebx
je .L13
cmpl $1, %ebx
jg .L9
movq 0(%rbp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L13:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
movl %eax, %edi
call srand@PLT
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, numThreads(%rip)
movq 32(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, numBlocks(%rip)
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L9:
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edx
movl %eax, N(%rip)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl numBlocks(%rip), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl numThreads(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z10parametersiPPc, .-_Z10parametersiPPc
.globl _Z17initialize_inputsv
.type _Z17initialize_inputsv, @function
_Z17initialize_inputsv:
.LFB2072:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0, %ebp
leaq A(%rip), %r13
leaq B(%rip), %r12
cmpl $0, N(%rip)
jg .L15
.L14:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call rand@PLT
movl %eax, %ecx
movl N(%rip), %edx
movl %edx, %eax
imull %ebx, %eax
addl %ebp, %eax
cltq
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss .LC5(%rip), %xmm0
movss %xmm0, 0(%r13,%rax,4)
movl $0x00000000, (%r12,%rax,4)
addl $1, %ebx
cmpl %ebx, %edx
jg .L17
.L18:
addl $1, %ebp
cmpl %ebp, N(%rip)
jle .L14
.L15:
movl $0, %ebx
cmpl $0, N(%rip)
jg .L17
jmp .L18
.cfi_endproc
.LFE2072:
.size _Z17initialize_inputsv, .-_Z17initialize_inputsv
.section .rodata.str1.1
.LC7:
.string ", "
.LC8:
.string ";\n\t"
.LC9:
.string "; "
.LC10:
.string "]\n"
.LC11:
.string "\nA =\n\t"
.LC12:
.string "%5.2f%s"
.LC13:
.string "\nB = ["
.text
.globl _Z12print_inputsv
.type _Z12print_inputsv, @function
_Z12print_inputsv:
.LFB2073:
.cfi_startproc
endbr64
cmpl $9, N(%rip)
jle .L46
ret
.L46:
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq A(%rip), %r15
leaq .LC12(%rip), %rbp
cmpl $0, N(%rip)
jg .L27
.L25:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
leal -1(%rax), %edx
cmpl %ebx, %edx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rcx
cmovle %rcx, %rdx
imull %ebx, %eax
addl %r12d, %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rax,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
movl N(%rip), %eax
cmpl %ebx, %eax
jg .L29
.L33:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl N(%rip), %eax
testl %eax, %eax
jle .L30
movl $0, %ebx
leaq .LC10(%rip), %r14
leaq B(%rip), %r13
.L32:
subl $1, %eax
cmpl %ebx, %eax
leaq .LC9(%rip), %rdx
cmovle %r14, %rdx
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl N(%rip), %eax
addq $1, %rbx
cmpl %ebx, %eax
jg .L32
.L30:
addl $1, %r12d
cmpl %r12d, N(%rip)
jle .L25
.L27:
movl N(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L29
jmp .L33
.cfi_endproc
.LFE2073:
.size _Z12print_inputsv, .-_Z12print_inputsv
.globl _Z33__device_stub__Z10matrixNormPfS_iPfS_i
.type _Z33__device_stub__Z10matrixNormPfS_iPfS_i, @function
_Z33__device_stub__Z10matrixNormPfS_iPfS_i:
.LFB2099:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixNormPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2099:
.size _Z33__device_stub__Z10matrixNormPfS_iPfS_i, .-_Z33__device_stub__Z10matrixNormPfS_iPfS_i
.globl _Z10matrixNormPfS_i
.type _Z10matrixNormPfS_i, @function
_Z10matrixNormPfS_i:
.LFB2100:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10matrixNormPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _Z10matrixNormPfS_i, .-_Z10matrixNormPfS_i
.section .rodata.str1.8
.align 8
.LC14:
.string "\n---------------------------------------------\n"
.section .rodata.str1.1
.LC15:
.string "Matrix size N = %d"
.LC16:
.string "\nStarting clock.\n\n"
.LC17:
.string "CUDA Error: %s\n"
.LC18:
.string "Stopped clock.\n"
.LC19:
.string "\nStopped clock."
.LC21:
.string "\nElapsed time = %g ms.\n"
.section .rodata.str1.8
.align 8
.LC23:
.string "(CPU times are accurate to the nearest %g ms)\n"
.align 8
.LC25:
.string "My total CPU time for parent = %g ms.\n"
.align 8
.LC26:
.string "My system CPU time for parent = %g ms.\n"
.align 8
.LC27:
.string "My total CPU time for child processes = %g ms.\n"
.align 8
.LC28:
.string "--------------------------------------------\n"
.text
.globl main
.type main, @function
main:
.LFB2074:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $160, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
call _Z10parametersiPPc
call _Z17initialize_inputsv
call _Z12print_inputsv
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl N(%rip), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
leaq 80(%rsp), %rdi
call times@PLT
movl N(%rip), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $2, %rsi
movq %rsi, sizeOfMatrix(%rip)
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq sizeOfMatrix(%rip), %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movq sizeOfMatrix(%rip), %rdx
leaq ptrA(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq sizeOfMatrix(%rip), %rdx
leaq ptrB(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl numThreads(%rip), %eax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl numBlocks(%rip), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 112(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L56:
movl $2, %ecx
movq sizeOfMatrix(%rip), %rdx
movq 16(%rsp), %rsi
leaq ptrB(%rip), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
je .L57
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L62:
movl N(%rip), %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z10matrixNormPfS_iPfS_i
jmp .L56
.L57:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 40(%rsp), %rsi
leaq 64(%rsp), %rdi
call gettimeofday@PLT
leaq 112(%rsp), %rdi
call times@PLT
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
imulq $1000000, 48(%rsp), %r12
movq 72(%rsp), %rbx
imulq $1000000, 64(%rsp), %rbp
subq 56(%rsp), %rbp
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq (%rbx,%rbp), %rax
subq %r12, %rax
js .L58
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L59:
divss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC22(%rip), %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 120(%rsp), %rax
addq 112(%rsp), %rax
subq 88(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC24(%rip), %xmm0
mulss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 120(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC24(%rip), %xmm0
mulss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 136(%rsp), %rax
addq 128(%rsp), %rax
subq 104(%rsp), %rax
subq 96(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC24(%rip), %xmm0
mulss .LC20(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L58:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L59
.cfi_endproc
.LFE2074:
.size main, .-main
.section .rodata.str1.1
.LC29:
.string "_Z10matrixNormPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2102:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixNormPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2102:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_numThreads, @function
_GLOBAL__sub_I_numThreads:
.LFB2219:
.cfi_startproc
endbr64
movslq N(%rip), %rax
imulq %rax, %rax
salq $2, %rax
movq %rax, sizeOfMatrix(%rip)
ret
.cfi_endproc
.LFE2219:
.size _GLOBAL__sub_I_numThreads, .-_GLOBAL__sub_I_numThreads
.section .init_array
.align 8
.quad _GLOBAL__sub_I_numThreads
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl sizeOfMatrix
.bss
.align 8
.type sizeOfMatrix, @object
.size sizeOfMatrix, 8
sizeOfMatrix:
.zero 8
.globl ptrB
.section .data.rel.local,"aw"
.align 8
.type ptrB, @object
.size ptrB, 8
ptrB:
.quad B
.globl ptrA
.align 8
.type ptrA, @object
.size ptrA, 8
ptrA:
.quad A
.globl B
.bss
.align 32
.type B, @object
.size B, 144000000
B:
.zero 144000000
.globl A
.align 32
.type A, @object
.size A, 144000000
A:
.zero 144000000
.globl col
.align 4
.type col, @object
.size col, 4
col:
.zero 4
.globl row
.align 4
.type row, @object
.size row, 4
row:
.zero 4
.globl N
.align 4
.type N, @object
.size N, 4
N:
.zero 4
.globl numBlocks
.align 4
.type numBlocks, @object
.size numBlocks, 4
numBlocks:
.zero 4
.globl numThreads
.align 4
.type numThreads, @object
.size numThreads, 4
numThreads:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 939524096
.align 4
.LC20:
.long 1148846080
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC22:
.long -755914244
.long 1062232653
.section .rodata.cst4
.align 4
.LC24:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "matrixNorm.hip"
.globl _Z9time_seedv # -- Begin function _Z9time_seedv
.p2align 4, 0x90
.type _Z9time_seedv,@function
_Z9time_seedv: # @_Z9time_seedv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
movl 8(%rsp), %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9time_seedv, .Lfunc_end0-_Z9time_seedv
.cfi_endproc
# -- End function
.globl _Z10parametersiPPc # -- Begin function _Z10parametersiPPc
.p2align 4, 0x90
.type _Z10parametersiPPc,@function
_Z10parametersiPPc: # @_Z10parametersiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
callq gettimeofday
movl 16(%rsp), %edi
callq srand
cmpl $5, %ebp
jne .LBB1_2
# %bb.1:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl %r14d, %edi
callq srand
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, numThreads(%rip)
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, numBlocks(%rip)
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
.LBB1_2:
cmpl $2, %ebp
jl .LBB1_4
# %bb.3:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, N(%rip)
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl numBlocks(%rip), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl numThreads(%rip), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB1_4:
.cfi_def_cfa_offset 64
movq (%rbx), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z10parametersiPPc, .Lfunc_end1-_Z10parametersiPPc
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17initialize_inputsv
.LCPI2_0:
.long 0x38000000 # float 3.05175781E-5
.text
.globl _Z17initialize_inputsv
.p2align 4, 0x90
.type _Z17initialize_inputsv,@function
_Z17initialize_inputsv: # @_Z17initialize_inputsv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
cmpl $0, N(%rip)
jg .LBB2_1
.LBB2_5: # %._crit_edge11
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.p2align 4, 0x90
.LBB2_4: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
.cfi_def_cfa_offset 32
incl %ebx
cmpl N(%rip), %ebx
jge .LBB2_5
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
cmpl $0, N(%rip)
jle .LBB2_4
# %bb.2: # %.lr.ph.preheader
# in Loop: Header=BB2_1 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movl N(%rip), %eax
imull %ebp, %eax
addl %ebx, %eax
cltq
movss %xmm0, A(,%rax,4)
movl $0, B(,%rax,4)
incl %ebp
cmpl N(%rip), %ebp
jl .LBB2_3
jmp .LBB2_4
.Lfunc_end2:
.size _Z17initialize_inputsv, .Lfunc_end2-_Z17initialize_inputsv
.cfi_endproc
# -- End function
.globl _Z12print_inputsv # -- Begin function _Z12print_inputsv
.p2align 4, 0x90
.type _Z12print_inputsv,@function
_Z12print_inputsv: # @_Z12print_inputsv
.cfi_startproc
# %bb.0:
cmpl $9, N(%rip)
jg .LBB3_11
# %bb.1:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
cmpl $0, N(%rip)
jle .LBB3_10
# %bb.2: # %.preheader.preheader
movl $.L.str.7, %ebx
movl $.L.str.10, %r14d
xorl %ebp, %ebp
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_9: # %._crit_edge18
# in Loop: Header=BB3_3 Depth=1
incl %ebp
cmpl N(%rip), %ebp
jge .LBB3_10
.LBB3_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
# Child Loop BB3_8 Depth 2
movl N(%rip), %eax
testl %eax, %eax
jle .LBB3_6
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB3_3 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph
# Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movl %eax, %ecx
imull %r15d, %ecx
addl %ebp, %ecx
movslq %ecx, %rcx
movss A(,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
decl %eax
cmpl %eax, %r15d
movl $.L.str.8, %esi
cmovlq %rbx, %rsi
movl $.L.str.6, %edi
movb $1, %al
callq printf
incl %r15d
movl N(%rip), %eax
cmpl %eax, %r15d
jl .LBB3_5
.LBB3_6: # %._crit_edge
# in Loop: Header=BB3_3 Depth=1
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl N(%rip), %eax
testl %eax, %eax
jle .LBB3_9
# %bb.7: # %.lr.ph17.preheader
# in Loop: Header=BB3_3 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_8: # %.lr.ph17
# Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movss B(,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
decl %eax
cltq
cmpq %rax, %r15
movl $.L.str.11, %esi
cmovlq %r14, %rsi
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r15
movslq N(%rip), %rax
cmpq %rax, %r15
jl .LBB3_8
jmp .LBB3_9
.LBB3_10:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB3_11: # %.loopexit
retq
.Lfunc_end3:
.size _Z12print_inputsv, .Lfunc_end3-_Z12print_inputsv
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matrixNormPfS_i # -- Begin function _Z25__device_stub__matrixNormPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixNormPfS_i,@function
_Z25__device_stub__matrixNormPfS_i: # @_Z25__device_stub__matrixNormPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixNormPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z25__device_stub__matrixNormPfS_i, .Lfunc_end4-_Z25__device_stub__matrixNormPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x38000000 # float 3.05175781E-5
.LCPI5_1:
.long 0x447a0000 # float 1000
.LCPI5_3:
.long 0x49742400 # float 1.0E+6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_2:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $208, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
callq _Z10parametersiPPc
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
cmpl $0, N(%rip)
jg .LBB5_1
.LBB5_5: # %_Z17initialize_inputsv.exit
callq _Z12print_inputsv
movl $.Lstr.3, %edi
callq puts@PLT
movl N(%rip), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
leaq 160(%rsp), %rdi
leaq 152(%rsp), %rsi
callq gettimeofday
leaq 176(%rsp), %rdi
callq times
movl N(%rip), %esi
imull %esi, %esi
shlq $2, %rsi
movq %rsi, sizeOfMatrix(%rip)
leaq 16(%rsp), %rdi
callq hipMalloc
movq sizeOfMatrix(%rip), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
movq sizeOfMatrix(%rip), %rdx
movl $ptrA, %esi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq sizeOfMatrix(%rip), %rdx
movl $ptrB, %esi
movl $1, %ecx
callq hipMemcpy
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl numBlocks(%rip), %edi
movl numThreads(%rip), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl N(%rip), %edx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %edx, 28(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 28(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10matrixNormPfS_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_7:
movq 8(%rsp), %rsi
movq sizeOfMatrix(%rip), %rdx
movl $ptrB, %edi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB5_12
# %bb.8:
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
leaq 32(%rsp), %rdi
leaq 152(%rsp), %rsi
callq gettimeofday
leaq 48(%rsp), %rdi
callq times
movl $.Lstr.2, %edi
callq puts@PLT
movq 32(%rsp), %rbx
movq 40(%rsp), %r14
subq 160(%rsp), %rbx
subq 168(%rsp), %r14
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
imulq $1000000, %rbx, %rax # imm = 0xF4240
addq %r14, %rax
js .LBB5_9
# %bb.10:
cvtsi2ss %rax, %xmm0
jmp .LBB5_11
.p2align 4, 0x90
.LBB5_4: # %._crit_edge.i
# in Loop: Header=BB5_1 Depth=1
incl %ebx
cmpl N(%rip), %ebx
jge .LBB5_5
.LBB5_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
cmpl $0, N(%rip)
jle .LBB5_4
# %bb.2: # %.lr.ph.i.preheader
# in Loop: Header=BB5_1 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_3: # %.lr.ph.i
# Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI5_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movl N(%rip), %eax
movl %eax, %ecx
imull %ebp, %ecx
addl %ebx, %ecx
movslq %ecx, %rcx
movss %xmm0, A(,%rcx,4)
movl $0, B(,%rcx,4)
incl %ebp
cmpl %eax, %ebp
jl .LBB5_3
jmp .LBB5_4
.LBB5_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB5_9:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB5_11:
divss .LCPI5_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
movsd .LCPI5_2(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.19, %edi
movb $1, %al
callq printf
movq 56(%rsp), %rbx
movq 184(%rsp), %r14
movq 48(%rsp), %rax
addq %rbx, %rax
movq 176(%rsp), %rcx
addq %r14, %rcx
subq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI5_3(%rip), %xmm0
mulss .LCPI5_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.20, %edi
movb $1, %al
callq printf
subq %r14, %rbx
xorps %xmm0, %xmm0
cvtsi2ss %rbx, %xmm0
divss .LCPI5_3(%rip), %xmm0
mulss .LCPI5_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.21, %edi
movb $1, %al
callq printf
movq 72(%rsp), %rax
movq 192(%rsp), %rcx
addq 64(%rsp), %rax
addq 200(%rsp), %rcx
subq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI5_3(%rip), %xmm0
mulss .LCPI5_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.22, %edi
movb $1, %al
callq printf
movl $.Lstr.4, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixNormPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type numThreads,@object # @numThreads
.bss
.globl numThreads
.p2align 2, 0x0
numThreads:
.long 0 # 0x0
.size numThreads, 4
.type numBlocks,@object # @numBlocks
.globl numBlocks
.p2align 2, 0x0
numBlocks:
.long 0 # 0x0
.size numBlocks, 4
.type N,@object # @N
.globl N
.p2align 2, 0x0
N:
.long 0 # 0x0
.size N, 4
.type row,@object # @row
.globl row
.p2align 2, 0x0
row:
.long 0 # 0x0
.size row, 4
.type col,@object # @col
.globl col
.p2align 2, 0x0
col:
.long 0 # 0x0
.size col, 4
.type A,@object # @A
.globl A
.p2align 4, 0x0
A:
.zero 144000000
.size A, 144000000
.type B,@object # @B
.globl B
.p2align 4, 0x0
B:
.zero 144000000
.size B, 144000000
.type ptrA,@object # @ptrA
.data
.globl ptrA
.p2align 3, 0x0
ptrA:
.quad A
.size ptrA, 8
.type ptrB,@object # @ptrB
.globl ptrB
.p2align 3, 0x0
ptrB:
.quad B
.size ptrB, 8
.type sizeOfMatrix,@object # @sizeOfMatrix
.bss
.globl sizeOfMatrix
.p2align 3, 0x0
sizeOfMatrix:
.quad 0 # 0x0
.size sizeOfMatrix, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Random seed = %i\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Usage: %s <matrix_dimension> [random seed] [number of threads] [number of blocks]\n"
.size .L.str.1, 83
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nMatrix dimension N = %i.\n"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nNumber of blocks = %i.\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nNumber of threads = %i.\n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nA =\n\t"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%5.2f%s"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz ", "
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nB = ["
.size .L.str.9, 7
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "
.size .L.str.10, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "]\n"
.size .L.str.11, 3
.type _Z10matrixNormPfS_i,@object # @_Z10matrixNormPfS_i
.section .rodata,"a",@progbits
.globl _Z10matrixNormPfS_i
.p2align 3, 0x0
_Z10matrixNormPfS_i:
.quad _Z25__device_stub__matrixNormPfS_i
.size _Z10matrixNormPfS_i, 8
.type .L.str.13,@object # @.str.13
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.13:
.asciz "Matrix size N = %d"
.size .L.str.13, 19
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "CUDA Error: %s\n"
.size .L.str.15, 16
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "\nStopped clock."
.size .L.str.17, 16
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "\nElapsed time = %g ms.\n"
.size .L.str.18, 24
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "(CPU times are accurate to the nearest %g ms)\n"
.size .L.str.19, 47
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "My total CPU time for parent = %g ms.\n"
.size .L.str.20, 39
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "My system CPU time for parent = %g ms.\n"
.size .L.str.21, 40
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "My total CPU time for child processes = %g ms.\n"
.size .L.str.22, 48
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixNormPfS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\nStarting clock.\n"
.size .Lstr.1, 18
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Stopped clock."
.size .Lstr.2, 15
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n---------------------------------------------"
.size .Lstr.3, 47
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "--------------------------------------------"
.size .Lstr.4, 45
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixNormPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym A
.addrsig_sym B
.addrsig_sym ptrA
.addrsig_sym ptrB
.addrsig_sym _Z10matrixNormPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
// incrementArray.cu
#include <stdio.h>
#include <time.h>
#include <sys/types.h>
#include <unistd.h>
void incrementArrayOnHost(float *a, int N)
{
int i;
for (i=0; i < N; i++) a[i] = a[i]+1.f;
}
__global__ void incrementArrayOnDevice(float *a, int N)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx]+1.f;
}
void printarray(float *a, int n)
{
int i = 0;
for (i = 0; i < n; i++) printf("%f ", a[i]);
printf("\n");
}
// http://www.concentric.net/~Ttwang/tech/inthash.htm
unsigned long mix(unsigned long a, unsigned long b, unsigned long c)
{
a=a-b; a=a-c; a=a^(c >> 13);
b=b-c; b=b-a; b=b^(a << 8);
c=c-a; c=c-b; c=c^(b >> 13);
a=a-b; a=a-c; a=a^(c >> 12);
b=b-c; b=b-a; b=b^(a << 16);
c=c-a; c=c-b; c=c^(b >> 5);
a=a-b; a=a-c; a=a^(c >> 3);
b=b-c; b=b-a; b=b^(a << 10);
c=c-a; c=c-b; c=c^(b >> 15);
return c;
}
int main(int argc, char** argv)
{
// program args
if (argc < 2) {
printf("usage: incrementArrayRandom [max_size] [repetitions]\n");
return EXIT_SUCCESS;
}
int max_size = atoi(argv[1]);
int repetitions = atoi(argv[2]);
// randomize within same run
srand(mix(clock(), time(NULL), getpid()));
float *a_h, *b_h; // pointers to host memory
float *a_d; // pointer to device memory
int i, epoch = 0;
int N = 0;
int total_success = 0;
for (epoch = 0; epoch < repetitions; epoch++) {
N = rand() % max_size;
size_t size = N*sizeof(float);
// allocate arrays on host
a_h = (float *)malloc(size);
b_h = (float *)malloc(size);
// allocate array on device
cudaMalloc((void **) &a_d, size);
// initialization of host data
for (i=0; i<N; i++) a_h[i] = (float)i;
// copy data from host to device
cudaMemcpy(a_d, a_h, sizeof(float)*N, cudaMemcpyHostToDevice);
// do calculation on host
incrementArrayOnHost(a_h, N);
// printarray(a_h, N);
// do calculation on device:
// Part 1 of 2. Compute execution configuration
int blockSize = 4;
int nBlocks = N/blockSize + (N%blockSize == 0?0:1);
// Part 2 of 2. Call incrementArrayOnDevice kernel
incrementArrayOnDevice <<< nBlocks, blockSize >>> (a_d, N);
// Retrieve result from device and store in b_h
cudaMemcpy(b_h, a_d, sizeof(float)*N, cudaMemcpyDeviceToHost);
// check results
// printarray(b_h, N);
int success = 1;
for (i=0; i<N; i++) {
if (a_h[i] != b_h[i]) {
success = 0;
break;
}
}
printf("epoch %d a[%d] = %s\n", epoch, N, (success == 1) ? "true" : "false");
if (success == 1) total_success += 1;
}
printf("\nsuccess rate: %f%%\n", total_success / ((float)repetitions) * 100.0);
// cleanup
free(a_h); free(b_h); cudaFree(a_d);
return EXIT_SUCCESS;
}
|
code for sm_80
Function : _Z22incrementArrayOnDevicePfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FADD R5, R0, 1 ; /* 0x3f80000000057421 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// incrementArray.cu
#include <stdio.h>
#include <time.h>
#include <sys/types.h>
#include <unistd.h>
void incrementArrayOnHost(float *a, int N)
{
int i;
for (i=0; i < N; i++) a[i] = a[i]+1.f;
}
__global__ void incrementArrayOnDevice(float *a, int N)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx]+1.f;
}
void printarray(float *a, int n)
{
int i = 0;
for (i = 0; i < n; i++) printf("%f ", a[i]);
printf("\n");
}
// http://www.concentric.net/~Ttwang/tech/inthash.htm
unsigned long mix(unsigned long a, unsigned long b, unsigned long c)
{
a=a-b; a=a-c; a=a^(c >> 13);
b=b-c; b=b-a; b=b^(a << 8);
c=c-a; c=c-b; c=c^(b >> 13);
a=a-b; a=a-c; a=a^(c >> 12);
b=b-c; b=b-a; b=b^(a << 16);
c=c-a; c=c-b; c=c^(b >> 5);
a=a-b; a=a-c; a=a^(c >> 3);
b=b-c; b=b-a; b=b^(a << 10);
c=c-a; c=c-b; c=c^(b >> 15);
return c;
}
int main(int argc, char** argv)
{
// program args
if (argc < 2) {
printf("usage: incrementArrayRandom [max_size] [repetitions]\n");
return EXIT_SUCCESS;
}
int max_size = atoi(argv[1]);
int repetitions = atoi(argv[2]);
// randomize within same run
srand(mix(clock(), time(NULL), getpid()));
float *a_h, *b_h; // pointers to host memory
float *a_d; // pointer to device memory
int i, epoch = 0;
int N = 0;
int total_success = 0;
for (epoch = 0; epoch < repetitions; epoch++) {
N = rand() % max_size;
size_t size = N*sizeof(float);
// allocate arrays on host
a_h = (float *)malloc(size);
b_h = (float *)malloc(size);
// allocate array on device
cudaMalloc((void **) &a_d, size);
// initialization of host data
for (i=0; i<N; i++) a_h[i] = (float)i;
// copy data from host to device
cudaMemcpy(a_d, a_h, sizeof(float)*N, cudaMemcpyHostToDevice);
// do calculation on host
incrementArrayOnHost(a_h, N);
// printarray(a_h, N);
// do calculation on device:
// Part 1 of 2. Compute execution configuration
int blockSize = 4;
int nBlocks = N/blockSize + (N%blockSize == 0?0:1);
// Part 2 of 2. Call incrementArrayOnDevice kernel
incrementArrayOnDevice <<< nBlocks, blockSize >>> (a_d, N);
// Retrieve result from device and store in b_h
cudaMemcpy(b_h, a_d, sizeof(float)*N, cudaMemcpyDeviceToHost);
// check results
// printarray(b_h, N);
int success = 1;
for (i=0; i<N; i++) {
if (a_h[i] != b_h[i]) {
success = 0;
break;
}
}
printf("epoch %d a[%d] = %s\n", epoch, N, (success == 1) ? "true" : "false");
if (success == 1) total_success += 1;
}
printf("\nsuccess rate: %f%%\n", total_success / ((float)repetitions) * 100.0);
// cleanup
free(a_h); free(b_h); cudaFree(a_d);
return EXIT_SUCCESS;
}
|
.file "tmpxft_001b2223_00000000-6_incrementArrayRan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20incrementArrayOnHostPfi
.type _Z20incrementArrayOnHostPfi, @function
_Z20incrementArrayOnHostPfi:
.LFB2070:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
movss .LC0(%rip), %xmm1
.L5:
movaps %xmm1, %xmm0
addss (%rax), %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2070:
.size _Z20incrementArrayOnHostPfi, .-_Z20incrementArrayOnHostPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f "
.LC2:
.string "\n"
.text
.globl _Z10printarrayPfi
.type _Z10printarrayPfi, @function
_Z10printarrayPfi:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L8
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC1(%rip), %rbp
.L9:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L9
.L8:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z10printarrayPfi, .-_Z10printarrayPfi
.globl _Z3mixmmm
.type _Z3mixmmm, @function
_Z3mixmmm:
.LFB2072:
.cfi_startproc
endbr64
subq %rsi, %rdi
movq %rdi, %rax
subq %rdx, %rax
movq %rdx, %rdi
shrq $13, %rdi
xorq %rax, %rdi
subq %rdx, %rsi
movq %rsi, %rax
subq %rdi, %rax
movq %rdi, %rsi
salq $8, %rsi
xorq %rax, %rsi
subq %rdi, %rdx
movq %rdx, %rax
subq %rsi, %rax
movq %rsi, %rdx
shrq $13, %rdx
xorq %rax, %rdx
subq %rsi, %rdi
subq %rdx, %rdi
movq %rdx, %rcx
shrq $12, %rcx
xorq %rdi, %rcx
subq %rdx, %rsi
subq %rcx, %rsi
movq %rcx, %rax
salq $16, %rax
xorq %rsi, %rax
subq %rcx, %rdx
movq %rdx, %rsi
subq %rax, %rsi
movq %rax, %rdx
shrq $5, %rdx
xorq %rsi, %rdx
subq %rax, %rcx
subq %rdx, %rcx
movq %rdx, %rsi
shrq $3, %rsi
xorq %rcx, %rsi
subq %rdx, %rax
subq %rsi, %rax
movq %rsi, %rcx
salq $10, %rcx
xorq %rcx, %rax
subq %rsi, %rdx
subq %rax, %rdx
shrq $15, %rax
xorq %rdx, %rax
ret
.cfi_endproc
.LFE2072:
.size _Z3mixmmm, .-_Z3mixmmm
.globl _Z43__device_stub__Z22incrementArrayOnDevicePfiPfi
.type _Z43__device_stub__Z22incrementArrayOnDevicePfiPfi, @function
_Z43__device_stub__Z22incrementArrayOnDevicePfiPfi:
.LFB2098:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22incrementArrayOnDevicePfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z43__device_stub__Z22incrementArrayOnDevicePfiPfi, .-_Z43__device_stub__Z22incrementArrayOnDevicePfiPfi
.globl _Z22incrementArrayOnDevicePfi
.type _Z22incrementArrayOnDevicePfi, @function
_Z22incrementArrayOnDevicePfi:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z22incrementArrayOnDevicePfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z22incrementArrayOnDevicePfi, .-_Z22incrementArrayOnDevicePfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "usage: incrementArrayRandom [max_size] [repetitions]\n"
.section .rodata.str1.1
.LC5:
.string "\nsuccess rate: %f%%\n"
.LC6:
.string "true"
.LC7:
.string "epoch %d a[%d] = %s\n"
.LC8:
.string "false"
.text
.globl main
.type main, @function
main:
.LFB2073:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L42
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 16(%rsp)
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 12(%rsp)
call getpid@PLT
movl %eax, %r12d
movl $0, %edi
call time@PLT
movq %rax, %r13
call clock@PLT
movq %rax, %rdi
movslq %r12d, %rdx
movq %r13, %rsi
call _Z3mixmmm
movl %eax, %edi
call srand@PLT
testl %r14d, %r14d
jle .L35
movl $0, 20(%rsp)
movl $0, %r15d
movq %r14, 24(%rsp)
jmp .L32
.L42:
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L23
.L45:
movl %r13d, %esi
movq 40(%rsp), %rdi
call _Z43__device_stub__Z22incrementArrayOnDevicePfiPfi
jmp .L27
.L44:
movq 24(%rsp), %r14
.L24:
pxor %xmm0, %xmm0
cvtsi2ssl 20(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r14d, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
.L23:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl $0, 20(%rsp)
jmp .L24
.L29:
leaq .LC8(%rip), %r8
movl %r13d, %ecx
movl %r15d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L33:
addl $1, %r15d
movl 12(%rsp), %eax
cmpl %eax, %r15d
je .L44
.L32:
call rand@PLT
cltd
idivl 16(%rsp)
movl %edx, %r13d
movslq %edx, %r14
leaq 0(,%r14,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %r13d, %r13d
jle .L25
movl $0, %eax
.L26:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq %rax, %r14
jne .L26
.L25:
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, %esi
movq %rbx, %rdi
call _Z20incrementArrayOnHostPfi
movl $4, 60(%rsp)
movl $1, 64(%rsp)
testb $3, %r13b
setne %dl
movzbl %dl, %edx
leal 3(%r13), %eax
testl %r13d, %r13d
cmovns %r13d, %eax
sarl $2, %eax
addl %edx, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L27:
movl $2, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L28
movl $0, %eax
.L31:
movss (%rbx,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L29
jne .L29
addq $4, %rax
cmpq %r12, %rax
jne .L31
.L28:
leaq .LC6(%rip), %r8
movl %r13d, %ecx
movl %r15d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, 20(%rsp)
jmp .L33
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z22incrementArrayOnDevicePfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z22incrementArrayOnDevicePfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// incrementArray.cu
#include <stdio.h>
#include <time.h>
#include <sys/types.h>
#include <unistd.h>
void incrementArrayOnHost(float *a, int N)
{
int i;
for (i=0; i < N; i++) a[i] = a[i]+1.f;
}
__global__ void incrementArrayOnDevice(float *a, int N)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx]+1.f;
}
void printarray(float *a, int n)
{
int i = 0;
for (i = 0; i < n; i++) printf("%f ", a[i]);
printf("\n");
}
// http://www.concentric.net/~Ttwang/tech/inthash.htm
unsigned long mix(unsigned long a, unsigned long b, unsigned long c)
{
a=a-b; a=a-c; a=a^(c >> 13);
b=b-c; b=b-a; b=b^(a << 8);
c=c-a; c=c-b; c=c^(b >> 13);
a=a-b; a=a-c; a=a^(c >> 12);
b=b-c; b=b-a; b=b^(a << 16);
c=c-a; c=c-b; c=c^(b >> 5);
a=a-b; a=a-c; a=a^(c >> 3);
b=b-c; b=b-a; b=b^(a << 10);
c=c-a; c=c-b; c=c^(b >> 15);
return c;
}
int main(int argc, char** argv)
{
// program args
if (argc < 2) {
printf("usage: incrementArrayRandom [max_size] [repetitions]\n");
return EXIT_SUCCESS;
}
int max_size = atoi(argv[1]);
int repetitions = atoi(argv[2]);
// randomize within same run
srand(mix(clock(), time(NULL), getpid()));
float *a_h, *b_h; // pointers to host memory
float *a_d; // pointer to device memory
int i, epoch = 0;
int N = 0;
int total_success = 0;
for (epoch = 0; epoch < repetitions; epoch++) {
N = rand() % max_size;
size_t size = N*sizeof(float);
// allocate arrays on host
a_h = (float *)malloc(size);
b_h = (float *)malloc(size);
// allocate array on device
cudaMalloc((void **) &a_d, size);
// initialization of host data
for (i=0; i<N; i++) a_h[i] = (float)i;
// copy data from host to device
cudaMemcpy(a_d, a_h, sizeof(float)*N, cudaMemcpyHostToDevice);
// do calculation on host
incrementArrayOnHost(a_h, N);
// printarray(a_h, N);
// do calculation on device:
// Part 1 of 2. Compute execution configuration
int blockSize = 4;
int nBlocks = N/blockSize + (N%blockSize == 0?0:1);
// Part 2 of 2. Call incrementArrayOnDevice kernel
incrementArrayOnDevice <<< nBlocks, blockSize >>> (a_d, N);
// Retrieve result from device and store in b_h
cudaMemcpy(b_h, a_d, sizeof(float)*N, cudaMemcpyDeviceToHost);
// check results
// printarray(b_h, N);
int success = 1;
for (i=0; i<N; i++) {
if (a_h[i] != b_h[i]) {
success = 0;
break;
}
}
printf("epoch %d a[%d] = %s\n", epoch, N, (success == 1) ? "true" : "false");
if (success == 1) total_success += 1;
}
printf("\nsuccess rate: %f%%\n", total_success / ((float)repetitions) * 100.0);
// cleanup
free(a_h); free(b_h); cudaFree(a_d);
return EXIT_SUCCESS;
}
|
// incrementArray.cu
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <sys/types.h>
#include <unistd.h>
void incrementArrayOnHost(float *a, int N)
{
int i;
for (i=0; i < N; i++) a[i] = a[i]+1.f;
}
__global__ void incrementArrayOnDevice(float *a, int N)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx]+1.f;
}
void printarray(float *a, int n)
{
int i = 0;
for (i = 0; i < n; i++) printf("%f ", a[i]);
printf("\n");
}
// http://www.concentric.net/~Ttwang/tech/inthash.htm
unsigned long mix(unsigned long a, unsigned long b, unsigned long c)
{
a=a-b; a=a-c; a=a^(c >> 13);
b=b-c; b=b-a; b=b^(a << 8);
c=c-a; c=c-b; c=c^(b >> 13);
a=a-b; a=a-c; a=a^(c >> 12);
b=b-c; b=b-a; b=b^(a << 16);
c=c-a; c=c-b; c=c^(b >> 5);
a=a-b; a=a-c; a=a^(c >> 3);
b=b-c; b=b-a; b=b^(a << 10);
c=c-a; c=c-b; c=c^(b >> 15);
return c;
}
int main(int argc, char** argv)
{
// program args
if (argc < 2) {
printf("usage: incrementArrayRandom [max_size] [repetitions]\n");
return EXIT_SUCCESS;
}
int max_size = atoi(argv[1]);
int repetitions = atoi(argv[2]);
// randomize within same run
srand(mix(clock(), time(NULL), getpid()));
float *a_h, *b_h; // pointers to host memory
float *a_d; // pointer to device memory
int i, epoch = 0;
int N = 0;
int total_success = 0;
for (epoch = 0; epoch < repetitions; epoch++) {
N = rand() % max_size;
size_t size = N*sizeof(float);
// allocate arrays on host
a_h = (float *)malloc(size);
b_h = (float *)malloc(size);
// allocate array on device
hipMalloc((void **) &a_d, size);
// initialization of host data
for (i=0; i<N; i++) a_h[i] = (float)i;
// copy data from host to device
hipMemcpy(a_d, a_h, sizeof(float)*N, hipMemcpyHostToDevice);
// do calculation on host
incrementArrayOnHost(a_h, N);
// printarray(a_h, N);
// do calculation on device:
// Part 1 of 2. Compute execution configuration
int blockSize = 4;
int nBlocks = N/blockSize + (N%blockSize == 0?0:1);
// Part 2 of 2. Call incrementArrayOnDevice kernel
incrementArrayOnDevice <<< nBlocks, blockSize >>> (a_d, N);
// Retrieve result from device and store in b_h
hipMemcpy(b_h, a_d, sizeof(float)*N, hipMemcpyDeviceToHost);
// check results
// printarray(b_h, N);
int success = 1;
for (i=0; i<N; i++) {
if (a_h[i] != b_h[i]) {
success = 0;
break;
}
}
printf("epoch %d a[%d] = %s\n", epoch, N, (success == 1) ? "true" : "false");
if (success == 1) total_success += 1;
}
printf("\nsuccess rate: %f%%\n", total_success / ((float)repetitions) * 100.0);
// cleanup
free(a_h); free(b_h); hipFree(a_d);
return EXIT_SUCCESS;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
// incrementArray.cu
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <sys/types.h>
#include <unistd.h>
void incrementArrayOnHost(float *a, int N)
{
int i;
for (i=0; i < N; i++) a[i] = a[i]+1.f;
}
__global__ void incrementArrayOnDevice(float *a, int N)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx]+1.f;
}
void printarray(float *a, int n)
{
int i = 0;
for (i = 0; i < n; i++) printf("%f ", a[i]);
printf("\n");
}
// http://www.concentric.net/~Ttwang/tech/inthash.htm
unsigned long mix(unsigned long a, unsigned long b, unsigned long c)
{
a=a-b; a=a-c; a=a^(c >> 13);
b=b-c; b=b-a; b=b^(a << 8);
c=c-a; c=c-b; c=c^(b >> 13);
a=a-b; a=a-c; a=a^(c >> 12);
b=b-c; b=b-a; b=b^(a << 16);
c=c-a; c=c-b; c=c^(b >> 5);
a=a-b; a=a-c; a=a^(c >> 3);
b=b-c; b=b-a; b=b^(a << 10);
c=c-a; c=c-b; c=c^(b >> 15);
return c;
}
int main(int argc, char** argv)
{
// program args
if (argc < 2) {
printf("usage: incrementArrayRandom [max_size] [repetitions]\n");
return EXIT_SUCCESS;
}
int max_size = atoi(argv[1]);
int repetitions = atoi(argv[2]);
// randomize within same run
srand(mix(clock(), time(NULL), getpid()));
float *a_h, *b_h; // pointers to host memory
float *a_d; // pointer to device memory
int i, epoch = 0;
int N = 0;
int total_success = 0;
for (epoch = 0; epoch < repetitions; epoch++) {
N = rand() % max_size;
size_t size = N*sizeof(float);
// allocate arrays on host
a_h = (float *)malloc(size);
b_h = (float *)malloc(size);
// allocate array on device
hipMalloc((void **) &a_d, size);
// initialization of host data
for (i=0; i<N; i++) a_h[i] = (float)i;
// copy data from host to device
hipMemcpy(a_d, a_h, sizeof(float)*N, hipMemcpyHostToDevice);
// do calculation on host
incrementArrayOnHost(a_h, N);
// printarray(a_h, N);
// do calculation on device:
// Part 1 of 2. Compute execution configuration
int blockSize = 4;
int nBlocks = N/blockSize + (N%blockSize == 0?0:1);
// Part 2 of 2. Call incrementArrayOnDevice kernel
incrementArrayOnDevice <<< nBlocks, blockSize >>> (a_d, N);
// Retrieve result from device and store in b_h
hipMemcpy(b_h, a_d, sizeof(float)*N, hipMemcpyDeviceToHost);
// check results
// printarray(b_h, N);
int success = 1;
for (i=0; i<N; i++) {
if (a_h[i] != b_h[i]) {
success = 0;
break;
}
}
printf("epoch %d a[%d] = %s\n", epoch, N, (success == 1) ? "true" : "false");
if (success == 1) total_success += 1;
}
printf("\nsuccess rate: %f%%\n", total_success / ((float)repetitions) * 100.0);
// cleanup
free(a_h); free(b_h); hipFree(a_d);
return EXIT_SUCCESS;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22incrementArrayOnDevicePfi
.globl _Z22incrementArrayOnDevicePfi
.p2align 8
.type _Z22incrementArrayOnDevicePfi,@function
_Z22incrementArrayOnDevicePfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22incrementArrayOnDevicePfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22incrementArrayOnDevicePfi, .Lfunc_end0-_Z22incrementArrayOnDevicePfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22incrementArrayOnDevicePfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22incrementArrayOnDevicePfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
// incrementArray.cu
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#include <sys/types.h>
#include <unistd.h>
void incrementArrayOnHost(float *a, int N)
{
int i;
for (i=0; i < N; i++) a[i] = a[i]+1.f;
}
__global__ void incrementArrayOnDevice(float *a, int N)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx]+1.f;
}
void printarray(float *a, int n)
{
int i = 0;
for (i = 0; i < n; i++) printf("%f ", a[i]);
printf("\n");
}
// http://www.concentric.net/~Ttwang/tech/inthash.htm
unsigned long mix(unsigned long a, unsigned long b, unsigned long c)
{
a=a-b; a=a-c; a=a^(c >> 13);
b=b-c; b=b-a; b=b^(a << 8);
c=c-a; c=c-b; c=c^(b >> 13);
a=a-b; a=a-c; a=a^(c >> 12);
b=b-c; b=b-a; b=b^(a << 16);
c=c-a; c=c-b; c=c^(b >> 5);
a=a-b; a=a-c; a=a^(c >> 3);
b=b-c; b=b-a; b=b^(a << 10);
c=c-a; c=c-b; c=c^(b >> 15);
return c;
}
int main(int argc, char** argv)
{
// program args
if (argc < 2) {
printf("usage: incrementArrayRandom [max_size] [repetitions]\n");
return EXIT_SUCCESS;
}
int max_size = atoi(argv[1]);
int repetitions = atoi(argv[2]);
// randomize within same run
srand(mix(clock(), time(NULL), getpid()));
float *a_h, *b_h; // pointers to host memory
float *a_d; // pointer to device memory
int i, epoch = 0;
int N = 0;
int total_success = 0;
for (epoch = 0; epoch < repetitions; epoch++) {
N = rand() % max_size;
size_t size = N*sizeof(float);
// allocate arrays on host
a_h = (float *)malloc(size);
b_h = (float *)malloc(size);
// allocate array on device
hipMalloc((void **) &a_d, size);
// initialization of host data
for (i=0; i<N; i++) a_h[i] = (float)i;
// copy data from host to device
hipMemcpy(a_d, a_h, sizeof(float)*N, hipMemcpyHostToDevice);
// do calculation on host
incrementArrayOnHost(a_h, N);
// printarray(a_h, N);
// do calculation on device:
// Part 1 of 2. Compute execution configuration
int blockSize = 4;
int nBlocks = N/blockSize + (N%blockSize == 0?0:1);
// Part 2 of 2. Call incrementArrayOnDevice kernel
incrementArrayOnDevice <<< nBlocks, blockSize >>> (a_d, N);
// Retrieve result from device and store in b_h
hipMemcpy(b_h, a_d, sizeof(float)*N, hipMemcpyDeviceToHost);
// check results
// printarray(b_h, N);
int success = 1;
for (i=0; i<N; i++) {
if (a_h[i] != b_h[i]) {
success = 0;
break;
}
}
printf("epoch %d a[%d] = %s\n", epoch, N, (success == 1) ? "true" : "false");
if (success == 1) total_success += 1;
}
printf("\nsuccess rate: %f%%\n", total_success / ((float)repetitions) * 100.0);
// cleanup
free(a_h); free(b_h); hipFree(a_d);
return EXIT_SUCCESS;
}
|
.text
.file "incrementArrayRan.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z20incrementArrayOnHostPfi
.LCPI0_0:
.long 0x3f800000 # float 1
.text
.globl _Z20incrementArrayOnHostPfi
.p2align 4, 0x90
.type _Z20incrementArrayOnHostPfi,@function
_Z20incrementArrayOnHostPfi: # @_Z20incrementArrayOnHostPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z20incrementArrayOnHostPfi, .Lfunc_end0-_Z20incrementArrayOnHostPfi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__incrementArrayOnDevicePfi # -- Begin function _Z37__device_stub__incrementArrayOnDevicePfi
.p2align 4, 0x90
.type _Z37__device_stub__incrementArrayOnDevicePfi,@function
_Z37__device_stub__incrementArrayOnDevicePfi: # @_Z37__device_stub__incrementArrayOnDevicePfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z22incrementArrayOnDevicePfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z37__device_stub__incrementArrayOnDevicePfi, .Lfunc_end1-_Z37__device_stub__incrementArrayOnDevicePfi
.cfi_endproc
# -- End function
.globl _Z10printarrayPfi # -- Begin function _Z10printarrayPfi
.p2align 4, 0x90
.type _Z10printarrayPfi,@function
_Z10printarrayPfi: # @_Z10printarrayPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z10printarrayPfi, .Lfunc_end2-_Z10printarrayPfi
.cfi_endproc
# -- End function
.globl _Z3mixmmm # -- Begin function _Z3mixmmm
.p2align 4, 0x90
.type _Z3mixmmm,@function
_Z3mixmmm: # @_Z3mixmmm
.cfi_startproc
# %bb.0:
subq %rsi, %rdi
subq %rdx, %rdi
movq %rdx, %rax
shrq $13, %rax
xorq %rdi, %rax
subq %rax, %rsi
subq %rdx, %rsi
movq %rax, %rcx
shlq $8, %rcx
xorq %rsi, %rcx
subq %rax, %rdx
subq %rcx, %rdx
movq %rcx, %rsi
shrq $13, %rsi
xorq %rdx, %rsi
subq %rcx, %rax
subq %rsi, %rax
movq %rsi, %rdx
shrq $12, %rdx
xorq %rax, %rdx
subq %rsi, %rcx
subq %rdx, %rcx
movq %rdx, %rdi
shlq $16, %rdi
xorq %rcx, %rdi
subq %rdx, %rsi
subq %rdi, %rsi
movq %rdi, %rcx
shrq $5, %rcx
xorq %rsi, %rcx
subq %rdi, %rdx
subq %rcx, %rdx
movq %rcx, %rsi
shrq $3, %rsi
xorq %rdx, %rsi
subq %rcx, %rdi
subq %rsi, %rdi
movq %rsi, %rax
shlq $10, %rax
xorq %rdi, %rax
addq %rax, %rsi
subq %rsi, %rcx
shrq $15, %rax
xorq %rcx, %rax
retq
.Lfunc_end3:
.size _Z3mixmmm, .Lfunc_end3-_Z3mixmmm
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x3f800000 # float 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x4059000000000000 # double 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jg .LBB4_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB4_25
.LBB4_2:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 32(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
callq clock
movq %rax, %rbx
xorl %edi, %edi
callq time
movq %rax, %r14
callq getpid
cltq
subq %r14, %rbx
subq %rax, %rbx
movq %rax, %rcx
shrq $13, %rcx
xorq %rbx, %rcx
subq %rcx, %r14
subq %rax, %r14
movq %rcx, %rdx
shlq $8, %rdx
xorq %r14, %rdx
subq %rcx, %rax
subq %rdx, %rax
movq %rdx, %rsi
shrq $13, %rsi
xorq %rax, %rsi
subq %rdx, %rcx
subq %rsi, %rcx
movq %rsi, %rax
shrq $12, %rax
xorq %rcx, %rax
subq %rsi, %rdx
subq %rax, %rdx
movq %rax, %rcx
shlq $16, %rcx
xorq %rdx, %rcx
subq %rax, %rsi
subq %rcx, %rsi
movq %rcx, %rdx
shrq $5, %rdx
xorq %rsi, %rdx
subq %rcx, %rax
subq %rdx, %rax
movq %rdx, %rsi
shrq $3, %rsi
xorq %rax, %rsi
subq %rdx, %rcx
subq %rsi, %rcx
movq %rsi, %rdi
shlq $10, %rdi
xorq %rcx, %rdi
addl %edi, %esi
subl %esi, %edx
shrq $15, %rdi
xorl %edx, %edi
# kill: def $edi killed $edi killed $rdi
callq srand
movq %r15, 16(%rsp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB4_3
# %bb.4: # %.lr.ph93
movabsq $4294967296, %rax # imm = 0x100000000
addq $4, %rax
movq %rax, 24(%rsp) # 8-byte Spill
xorl %r15d, %r15d
xorl %eax, %eax
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_14: # in Loop: Header=BB4_5 Depth=1
movl $.L.str.4, %ecx
.LBB4_22: # %._crit_edge85
# in Loop: Header=BB4_5 Depth=1
movl $.L.str.3, %edi
movl %r15d, %esi
movl %r14d, %edx
xorl %eax, %eax
callq printf
movzbl %bl, %eax
movl 8(%rsp), %ecx # 4-byte Reload
addl %eax, %ecx
movl %ecx, %eax
incl %r15d
cmpl 16(%rsp), %r15d # 4-byte Folded Reload
je .LBB4_23
.LBB4_5: # =>This Loop Header: Depth=1
# Child Loop BB4_7 Depth 2
# Child Loop BB4_10 Depth 2
# Child Loop BB4_17 Depth 2
movl %eax, 8(%rsp) # 4-byte Spill
callq rand
cltd
idivl 32(%rsp) # 4-byte Folded Reload
movl %edx, %r14d
movslq %edx, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movl %r14d, %r12d
testl %r14d, %r14d
jle .LBB4_8
# %bb.6: # %.lr.ph.preheader
# in Loop: Header=BB4_5 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_7: # %.lr.ph
# Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%rax,4)
incq %rax
cmpq %rax, %r12
jne .LBB4_7
.LBB4_8: # %._crit_edge
# in Loop: Header=BB4_5 Depth=1
movq (%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %r14d, %r14d
movss .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
jle .LBB4_11
# %bb.9: # %.lr.ph.preheader.i
# in Loop: Header=BB4_5 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_10: # %.lr.ph.i
# Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, (%r13,%rax,4)
incq %rax
cmpq %rax, %r12
jne .LBB4_10
.LBB4_11: # %_Z20incrementArrayOnHostPfi.exit
# in Loop: Header=BB4_5 Depth=1
leal 3(%r14), %edi
testl %r14d, %r14d
cmovnsl %r14d, %edi
sarl $2, %edi
movl %r14d, %eax
andl $3, %eax
cmpl $1, %eax
sbbl $-1, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq 24(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12: # in Loop: Header=BB4_5 Depth=1
movq (%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z22incrementArrayOnDevicePfi, %edi
leaq 96(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_13: # in Loop: Header=BB4_5 Depth=1
movq (%rsp), %rsi
movq %rbp, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r14d, %r14d
setle %bl
jle .LBB4_14
# %bb.15: # %.lr.ph84.preheader
# in Loop: Header=BB4_5 Depth=1
movss (%r13), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $.L.str.5, %ecx
ucomiss (%rbp), %xmm0
jne .LBB4_22
jp .LBB4_22
# %bb.16: # %.lr.ph107.preheader
# in Loop: Header=BB4_5 Depth=1
movl $1, %ecx
.p2align 4, 0x90
.LBB4_17: # %.lr.ph107
# Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movq %rcx, %rax
cmpq %rcx, %r12
je .LBB4_18
# %bb.19: # %.lr.ph84
# in Loop: Header=BB4_17 Depth=2
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leaq 1(%rax), %rcx
ucomiss (%rbp,%rax,4), %xmm0
jne .LBB4_20
jnp .LBB4_17
.LBB4_20: # in Loop: Header=BB4_5 Depth=1
movl $.L.str.5, %ecx
jmp .LBB4_21
.LBB4_18: # in Loop: Header=BB4_5 Depth=1
movl $.L.str.4, %ecx
.LBB4_21: # %._crit_edge85.loopexit
# in Loop: Header=BB4_5 Depth=1
cmpq %r12, %rax
setae %bl
jmp .LBB4_22
.LBB4_23: # %._crit_edge94.loopexit
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
jmp .LBB4_24
.LBB4_3:
xorps %xmm0, %xmm0
# implicit-def: $rbp
# implicit-def: $r13
.LBB4_24: # %._crit_edge94
xorps %xmm1, %xmm1
cvtsi2ssl 16(%rsp), %xmm1 # 4-byte Folded Reload
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
.LBB4_25:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22incrementArrayOnDevicePfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22incrementArrayOnDevicePfi,@object # @_Z22incrementArrayOnDevicePfi
.section .rodata,"a",@progbits
.globl _Z22incrementArrayOnDevicePfi
.p2align 3, 0x0
_Z22incrementArrayOnDevicePfi:
.quad _Z37__device_stub__incrementArrayOnDevicePfi
.size _Z22incrementArrayOnDevicePfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "epoch %d a[%d] = %s\n"
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "true"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "false"
.size .L.str.5, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\nsuccess rate: %f%%\n"
.size .L.str.6, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22incrementArrayOnDevicePfi"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: incrementArrayRandom [max_size] [repetitions]"
.size .Lstr, 53
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__incrementArrayOnDevicePfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22incrementArrayOnDevicePfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z22incrementArrayOnDevicePfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FADD R5, R0, 1 ; /* 0x3f80000000057421 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22incrementArrayOnDevicePfi
.globl _Z22incrementArrayOnDevicePfi
.p2align 8
.type _Z22incrementArrayOnDevicePfi,@function
_Z22incrementArrayOnDevicePfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22incrementArrayOnDevicePfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22incrementArrayOnDevicePfi, .Lfunc_end0-_Z22incrementArrayOnDevicePfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22incrementArrayOnDevicePfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22incrementArrayOnDevicePfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001b2223_00000000-6_incrementArrayRan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20incrementArrayOnHostPfi
.type _Z20incrementArrayOnHostPfi, @function
_Z20incrementArrayOnHostPfi:
.LFB2070:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
movss .LC0(%rip), %xmm1
.L5:
movaps %xmm1, %xmm0
addss (%rax), %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2070:
.size _Z20incrementArrayOnHostPfi, .-_Z20incrementArrayOnHostPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f "
.LC2:
.string "\n"
.text
.globl _Z10printarrayPfi
.type _Z10printarrayPfi, @function
_Z10printarrayPfi:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L8
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC1(%rip), %rbp
.L9:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L9
.L8:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z10printarrayPfi, .-_Z10printarrayPfi
.globl _Z3mixmmm
.type _Z3mixmmm, @function
_Z3mixmmm:
.LFB2072:
.cfi_startproc
endbr64
subq %rsi, %rdi
movq %rdi, %rax
subq %rdx, %rax
movq %rdx, %rdi
shrq $13, %rdi
xorq %rax, %rdi
subq %rdx, %rsi
movq %rsi, %rax
subq %rdi, %rax
movq %rdi, %rsi
salq $8, %rsi
xorq %rax, %rsi
subq %rdi, %rdx
movq %rdx, %rax
subq %rsi, %rax
movq %rsi, %rdx
shrq $13, %rdx
xorq %rax, %rdx
subq %rsi, %rdi
subq %rdx, %rdi
movq %rdx, %rcx
shrq $12, %rcx
xorq %rdi, %rcx
subq %rdx, %rsi
subq %rcx, %rsi
movq %rcx, %rax
salq $16, %rax
xorq %rsi, %rax
subq %rcx, %rdx
movq %rdx, %rsi
subq %rax, %rsi
movq %rax, %rdx
shrq $5, %rdx
xorq %rsi, %rdx
subq %rax, %rcx
subq %rdx, %rcx
movq %rdx, %rsi
shrq $3, %rsi
xorq %rcx, %rsi
subq %rdx, %rax
subq %rsi, %rax
movq %rsi, %rcx
salq $10, %rcx
xorq %rcx, %rax
subq %rsi, %rdx
subq %rax, %rdx
shrq $15, %rax
xorq %rdx, %rax
ret
.cfi_endproc
.LFE2072:
.size _Z3mixmmm, .-_Z3mixmmm
.globl _Z43__device_stub__Z22incrementArrayOnDevicePfiPfi
.type _Z43__device_stub__Z22incrementArrayOnDevicePfiPfi, @function
_Z43__device_stub__Z22incrementArrayOnDevicePfiPfi:
.LFB2098:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22incrementArrayOnDevicePfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z43__device_stub__Z22incrementArrayOnDevicePfiPfi, .-_Z43__device_stub__Z22incrementArrayOnDevicePfiPfi
.globl _Z22incrementArrayOnDevicePfi
.type _Z22incrementArrayOnDevicePfi, @function
_Z22incrementArrayOnDevicePfi:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z22incrementArrayOnDevicePfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z22incrementArrayOnDevicePfi, .-_Z22incrementArrayOnDevicePfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "usage: incrementArrayRandom [max_size] [repetitions]\n"
.section .rodata.str1.1
.LC5:
.string "\nsuccess rate: %f%%\n"
.LC6:
.string "true"
.LC7:
.string "epoch %d a[%d] = %s\n"
.LC8:
.string "false"
.text
.globl main
.type main, @function
main:
.LFB2073:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L42
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 16(%rsp)
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 12(%rsp)
call getpid@PLT
movl %eax, %r12d
movl $0, %edi
call time@PLT
movq %rax, %r13
call clock@PLT
movq %rax, %rdi
movslq %r12d, %rdx
movq %r13, %rsi
call _Z3mixmmm
movl %eax, %edi
call srand@PLT
testl %r14d, %r14d
jle .L35
movl $0, 20(%rsp)
movl $0, %r15d
movq %r14, 24(%rsp)
jmp .L32
.L42:
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L23
.L45:
movl %r13d, %esi
movq 40(%rsp), %rdi
call _Z43__device_stub__Z22incrementArrayOnDevicePfiPfi
jmp .L27
.L44:
movq 24(%rsp), %r14
.L24:
pxor %xmm0, %xmm0
cvtsi2ssl 20(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r14d, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
.L23:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl $0, 20(%rsp)
jmp .L24
.L29:
leaq .LC8(%rip), %r8
movl %r13d, %ecx
movl %r15d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L33:
addl $1, %r15d
movl 12(%rsp), %eax
cmpl %eax, %r15d
je .L44
.L32:
call rand@PLT
cltd
idivl 16(%rsp)
movl %edx, %r13d
movslq %edx, %r14
leaq 0(,%r14,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %r13d, %r13d
jle .L25
movl $0, %eax
.L26:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq %rax, %r14
jne .L26
.L25:
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, %esi
movq %rbx, %rdi
call _Z20incrementArrayOnHostPfi
movl $4, 60(%rsp)
movl $1, 64(%rsp)
testb $3, %r13b
setne %dl
movzbl %dl, %edx
leal 3(%r13), %eax
testl %r13d, %r13d
cmovns %r13d, %eax
sarl $2, %eax
addl %edx, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L27:
movl $2, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L28
movl $0, %eax
.L31:
movss (%rbx,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L29
jne .L29
addq $4, %rax
cmpq %r12, %rax
jne .L31
.L28:
leaq .LC6(%rip), %r8
movl %r13d, %ecx
movl %r15d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, 20(%rsp)
jmp .L33
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z22incrementArrayOnDevicePfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z22incrementArrayOnDevicePfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "incrementArrayRan.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z20incrementArrayOnHostPfi
.LCPI0_0:
.long 0x3f800000 # float 1
.text
.globl _Z20incrementArrayOnHostPfi
.p2align 4, 0x90
.type _Z20incrementArrayOnHostPfi,@function
_Z20incrementArrayOnHostPfi: # @_Z20incrementArrayOnHostPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z20incrementArrayOnHostPfi, .Lfunc_end0-_Z20incrementArrayOnHostPfi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__incrementArrayOnDevicePfi # -- Begin function _Z37__device_stub__incrementArrayOnDevicePfi
.p2align 4, 0x90
.type _Z37__device_stub__incrementArrayOnDevicePfi,@function
_Z37__device_stub__incrementArrayOnDevicePfi: # @_Z37__device_stub__incrementArrayOnDevicePfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z22incrementArrayOnDevicePfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z37__device_stub__incrementArrayOnDevicePfi, .Lfunc_end1-_Z37__device_stub__incrementArrayOnDevicePfi
.cfi_endproc
# -- End function
.globl _Z10printarrayPfi # -- Begin function _Z10printarrayPfi
.p2align 4, 0x90
.type _Z10printarrayPfi,@function
_Z10printarrayPfi: # @_Z10printarrayPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size _Z10printarrayPfi, .Lfunc_end2-_Z10printarrayPfi
.cfi_endproc
# -- End function
.globl _Z3mixmmm # -- Begin function _Z3mixmmm
.p2align 4, 0x90
.type _Z3mixmmm,@function
_Z3mixmmm: # @_Z3mixmmm
.cfi_startproc
# %bb.0:
subq %rsi, %rdi
subq %rdx, %rdi
movq %rdx, %rax
shrq $13, %rax
xorq %rdi, %rax
subq %rax, %rsi
subq %rdx, %rsi
movq %rax, %rcx
shlq $8, %rcx
xorq %rsi, %rcx
subq %rax, %rdx
subq %rcx, %rdx
movq %rcx, %rsi
shrq $13, %rsi
xorq %rdx, %rsi
subq %rcx, %rax
subq %rsi, %rax
movq %rsi, %rdx
shrq $12, %rdx
xorq %rax, %rdx
subq %rsi, %rcx
subq %rdx, %rcx
movq %rdx, %rdi
shlq $16, %rdi
xorq %rcx, %rdi
subq %rdx, %rsi
subq %rdi, %rsi
movq %rdi, %rcx
shrq $5, %rcx
xorq %rsi, %rcx
subq %rdi, %rdx
subq %rcx, %rdx
movq %rcx, %rsi
shrq $3, %rsi
xorq %rdx, %rsi
subq %rcx, %rdi
subq %rsi, %rdi
movq %rsi, %rax
shlq $10, %rax
xorq %rdi, %rax
addq %rax, %rsi
subq %rsi, %rcx
shrq $15, %rax
xorq %rcx, %rax
retq
.Lfunc_end3:
.size _Z3mixmmm, .Lfunc_end3-_Z3mixmmm
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x3f800000 # float 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x4059000000000000 # double 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jg .LBB4_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB4_25
.LBB4_2:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 32(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
callq clock
movq %rax, %rbx
xorl %edi, %edi
callq time
movq %rax, %r14
callq getpid
cltq
subq %r14, %rbx
subq %rax, %rbx
movq %rax, %rcx
shrq $13, %rcx
xorq %rbx, %rcx
subq %rcx, %r14
subq %rax, %r14
movq %rcx, %rdx
shlq $8, %rdx
xorq %r14, %rdx
subq %rcx, %rax
subq %rdx, %rax
movq %rdx, %rsi
shrq $13, %rsi
xorq %rax, %rsi
subq %rdx, %rcx
subq %rsi, %rcx
movq %rsi, %rax
shrq $12, %rax
xorq %rcx, %rax
subq %rsi, %rdx
subq %rax, %rdx
movq %rax, %rcx
shlq $16, %rcx
xorq %rdx, %rcx
subq %rax, %rsi
subq %rcx, %rsi
movq %rcx, %rdx
shrq $5, %rdx
xorq %rsi, %rdx
subq %rcx, %rax
subq %rdx, %rax
movq %rdx, %rsi
shrq $3, %rsi
xorq %rax, %rsi
subq %rdx, %rcx
subq %rsi, %rcx
movq %rsi, %rdi
shlq $10, %rdi
xorq %rcx, %rdi
addl %edi, %esi
subl %esi, %edx
shrq $15, %rdi
xorl %edx, %edi
# kill: def $edi killed $edi killed $rdi
callq srand
movq %r15, 16(%rsp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB4_3
# %bb.4: # %.lr.ph93
movabsq $4294967296, %rax # imm = 0x100000000
addq $4, %rax
movq %rax, 24(%rsp) # 8-byte Spill
xorl %r15d, %r15d
xorl %eax, %eax
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_14: # in Loop: Header=BB4_5 Depth=1
movl $.L.str.4, %ecx
.LBB4_22: # %._crit_edge85
# in Loop: Header=BB4_5 Depth=1
movl $.L.str.3, %edi
movl %r15d, %esi
movl %r14d, %edx
xorl %eax, %eax
callq printf
movzbl %bl, %eax
movl 8(%rsp), %ecx # 4-byte Reload
addl %eax, %ecx
movl %ecx, %eax
incl %r15d
cmpl 16(%rsp), %r15d # 4-byte Folded Reload
je .LBB4_23
.LBB4_5: # =>This Loop Header: Depth=1
# Child Loop BB4_7 Depth 2
# Child Loop BB4_10 Depth 2
# Child Loop BB4_17 Depth 2
movl %eax, 8(%rsp) # 4-byte Spill
callq rand
cltd
idivl 32(%rsp) # 4-byte Folded Reload
movl %edx, %r14d
movslq %edx, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movl %r14d, %r12d
testl %r14d, %r14d
jle .LBB4_8
# %bb.6: # %.lr.ph.preheader
# in Loop: Header=BB4_5 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_7: # %.lr.ph
# Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r13,%rax,4)
incq %rax
cmpq %rax, %r12
jne .LBB4_7
.LBB4_8: # %._crit_edge
# in Loop: Header=BB4_5 Depth=1
movq (%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %r14d, %r14d
movss .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
jle .LBB4_11
# %bb.9: # %.lr.ph.preheader.i
# in Loop: Header=BB4_5 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_10: # %.lr.ph.i
# Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, (%r13,%rax,4)
incq %rax
cmpq %rax, %r12
jne .LBB4_10
.LBB4_11: # %_Z20incrementArrayOnHostPfi.exit
# in Loop: Header=BB4_5 Depth=1
leal 3(%r14), %edi
testl %r14d, %r14d
cmovnsl %r14d, %edi
sarl $2, %edi
movl %r14d, %eax
andl $3, %eax
cmpl $1, %eax
sbbl $-1, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq 24(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12: # in Loop: Header=BB4_5 Depth=1
movq (%rsp), %rax
movq %rax, 88(%rsp)
movl %r14d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z22incrementArrayOnDevicePfi, %edi
leaq 96(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_13: # in Loop: Header=BB4_5 Depth=1
movq (%rsp), %rsi
movq %rbp, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r14d, %r14d
setle %bl
jle .LBB4_14
# %bb.15: # %.lr.ph84.preheader
# in Loop: Header=BB4_5 Depth=1
movss (%r13), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $.L.str.5, %ecx
ucomiss (%rbp), %xmm0
jne .LBB4_22
jp .LBB4_22
# %bb.16: # %.lr.ph107.preheader
# in Loop: Header=BB4_5 Depth=1
movl $1, %ecx
.p2align 4, 0x90
.LBB4_17: # %.lr.ph107
# Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movq %rcx, %rax
cmpq %rcx, %r12
je .LBB4_18
# %bb.19: # %.lr.ph84
# in Loop: Header=BB4_17 Depth=2
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leaq 1(%rax), %rcx
ucomiss (%rbp,%rax,4), %xmm0
jne .LBB4_20
jnp .LBB4_17
.LBB4_20: # in Loop: Header=BB4_5 Depth=1
movl $.L.str.5, %ecx
jmp .LBB4_21
.LBB4_18: # in Loop: Header=BB4_5 Depth=1
movl $.L.str.4, %ecx
.LBB4_21: # %._crit_edge85.loopexit
# in Loop: Header=BB4_5 Depth=1
cmpq %r12, %rax
setae %bl
jmp .LBB4_22
.LBB4_23: # %._crit_edge94.loopexit
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
jmp .LBB4_24
.LBB4_3:
xorps %xmm0, %xmm0
# implicit-def: $rbp
# implicit-def: $r13
.LBB4_24: # %._crit_edge94
xorps %xmm1, %xmm1
cvtsi2ssl 16(%rsp), %xmm1 # 4-byte Folded Reload
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI4_1(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
.LBB4_25:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22incrementArrayOnDevicePfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22incrementArrayOnDevicePfi,@object # @_Z22incrementArrayOnDevicePfi
.section .rodata,"a",@progbits
.globl _Z22incrementArrayOnDevicePfi
.p2align 3, 0x0
_Z22incrementArrayOnDevicePfi:
.quad _Z37__device_stub__incrementArrayOnDevicePfi
.size _Z22incrementArrayOnDevicePfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "epoch %d a[%d] = %s\n"
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "true"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "false"
.size .L.str.5, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\nsuccess rate: %f%%\n"
.size .L.str.6, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22incrementArrayOnDevicePfi"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: incrementArrayRandom [max_size] [repetitions]"
.size .Lstr, 53
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__incrementArrayOnDevicePfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22incrementArrayOnDevicePfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/* *********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
void check_param(void);
void printfinal (void);
int nsteps ,/* number of time steps */
tpoints ,/* total points along string */
rcode;/* generic return code */
/* *********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points , number of iterations */
while (( tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: " ,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if (( tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n", MINPOINTS , MAXPOINTS);
}
while (( nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints , nsteps);
}
/* **********************************************************************
Initialize points on line
*********************************************************************/
__global__ void init_line_kernel(float* oldval, float* values, int tpoints) {
int j;
float x, fac , k, tmp;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_num = blockDim.x * gridDim.x;
/* Calculate initial values based on sine curve */
fac = 2.0 * PI;
tmp = (float)(tpoints - 1);
for (j = thread_id; j <= tpoints; j += thread_num) {
if (j >= 0){
k = (float)(j - 1);
x = k/tmp;
values[j] = __sinf(fac * x); //GPU內建 __sinf
oldval[j] = values[j];
}
}
}
/* **********************************************************************
Update all values along line a specified number of times
*********************************************************************/
__global__ void update_kernel(float* oldval, float* values, float* newval, int nsteps, int tpoints){
int i, j;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_num = blockDim.x * gridDim.x;
/* Update values for each time step */
for (i = 1; i <= nsteps; i++) {
/* Update points along line for this time step */
for (j = thread_id; j <= tpoints; j += thread_num) {
/* global endpoints */
if ((j == 1) || (j == tpoints)){
newval[j] = 0.0;
}else {
/***********************************************************************
Calculate new values using wave equation
*********************************************************************/
float dtime , c, dx, tau , sqtau;
dtime = 0.3;
c = 1.0;
dx = 1.0;
tau = (c * dtime / dx);
sqtau = tau * tau;
newval[j] = (2.0 * values[j]) - oldval[j] + (sqtau * ( -2.0)*values[j]);
}
oldval[j] = values[j];
values[j] = newval[j];
}
}
}
/* **********************************************************************
Print final results
*********************************************************************/
void printfinal (float* values, int tpoints) {
int i;
for (i = 1; i <= tpoints; i++) {
printf("%6.4f ", values[i]);
if (i%10 == 0)
printf("\n");
}
}
/* **********************************************************************
Main program
*********************************************************************/
int main(int argc , char *argv []) {
sscanf(argv[1],"%d" ,&tpoints);
sscanf(argv[2],"%d" ,&nsteps);
check_param();
int threadinblock = 512;
int blocknum = (tpoints + threadinblock - 1)/threadinblock; // 無條件補上
//Host
float *oldval, *values, *newval;
oldval = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time (t-dt) */
values = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time t */
newval = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time (t+dt) */
//Device
float *gpu_oldval, *gpu_values, *gpu_newval;
cudaMalloc(&gpu_oldval, (tpoints + 2) * sizeof(float));
cudaMalloc(&gpu_values, (tpoints + 2) * sizeof(float));
cudaMalloc(&gpu_newval, (tpoints + 2) * sizeof(float));
printf("Initializing points on the line ...\n");
init_line_kernel <<<blocknum, threadinblock>>> (gpu_oldval, gpu_values, tpoints);
printf("Updating all points for all time steps ...\n");
update_kernel <<<blocknum, threadinblock>>> (gpu_oldval, gpu_values, gpu_newval, nsteps, tpoints);
//把資料送回Host
cudaMemcpy(oldval, gpu_oldval, (tpoints + 2) * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(values, gpu_values, (tpoints + 2) * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(newval, gpu_newval, (tpoints + 2) * sizeof(float), cudaMemcpyDeviceToHost);
printf("Printing final results ...\n");
printfinal(values, tpoints);
printf("\nDone .\n\n");
return 0;
}
|
code for sm_80
Function : _Z13update_kernelPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e640000002100 */
/*0040*/ ISETP.LE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fda0003f03270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x003fe200078e0203 */
/*0070*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f04270 */
/*00a0*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x001fe2000f8e00ff */
/*00b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*00c0*/ BSSY B0, 0x2b0 ; /* 0x000001e000007945 */
/* 0x000fe60003800000 */
/*00d0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fce0003f26270 */
/*00e0*/ @P0 BRA 0x2a0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R12, R0 ; /* 0x00000000000c7202 */
/* 0x000fc80000000f00 */
/*0100*/ ISETP.NE.AND P0, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f05270 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fc600078e00ff */
/*0120*/ ISETP.EQ.OR P0, PT, R12.reuse, 0x1, !P0 ; /* 0x000000010c00780c */
/* 0x040fe20004702670 */
/*0130*/ IMAD.WIDE R2, R12, R5, c[0x0][0x168] ; /* 0x00005a000c027625 */
/* 0x000fc800078e0205 */
/*0140*/ IMAD.WIDE R4, R12, R5, c[0x0][0x160] ; /* 0x000058000c047625 */
/* 0x000fd000078e0205 */
/*0150*/ @!P0 LDG.E R13, [R2.64] ; /* 0x00000006020d8981 */
/* 0x000ea8000c1e1900 */
/*0160*/ @!P0 LDG.E R10, [R4.64] ; /* 0x00000006040a8981 */
/* 0x000ee2000c1e1900 */
/*0170*/ @!P0 F2F.F64.F32 R6, R13 ; /* 0x0000000d00068310 */
/* 0x004e300000201800 */
/*0180*/ @!P0 F2F.F64.F32 R10, R10 ; /* 0x0000000a000a8310 */
/* 0x008e620000201800 */
/*0190*/ @!P0 DADD R8, R6, R6 ; /* 0x0000000006088229 */
/* 0x001e4c0000000006 */
/*01a0*/ @!P0 DADD R8, R8, -R10 ; /* 0x0000000008088229 */
/* 0x002e0c000000080a */
/*01b0*/ @!P0 DFMA R8, R6, c[0x2][0x0], R8 ; /* 0x0080000006088a2b */
/* 0x0010640000000008 */
/*01c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R12 ; /* 0x0000001fff077819 */
/* 0x001fe4000001140c */
/*01d0*/ LEA R6, P2, R12.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c000c067a11 */
/* 0x040fe400078410ff */
/*01e0*/ @!P0 F2F.F32.F64 R11, R8 ; /* 0x00000008000b8310 */
/* 0x002e240000301000 */
/*01f0*/ LEA.HI.X R7, R12, c[0x0][0x174], R7, 0x2, P2 ; /* 0x00005d000c077a11 */
/* 0x000fe200010f1407 */
/*0200*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b0224 */
/* 0x000fca00078e00ff */
/*0210*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0011e8000c101906 */
/*0220*/ LDG.E R13, [R2.64] ; /* 0x00000006020d7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ MOV R17, c[0x0][0x0] ; /* 0x0000000000117a02 */
/* 0x000fc60000000f00 */
/*0240*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0041e8000c101906 */
/*0250*/ LDG.E R15, [R6.64] ; /* 0x00000006060f7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD R12, R17, c[0x0][0xc], R12 ; /* 0x00000300110c7a24 */
/* 0x000fca00078e020c */
/*0270*/ ISETP.GT.AND P0, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f04270 */
/*0280*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0041d8000c101906 */
/*0290*/ @!P0 BRA 0x100 ; /* 0xfffffe6000008947 */
/* 0x000fea000383ffff */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ @!P1 BRA 0x90 ; /* 0xfffffdd000009947 */
/* 0x000fea000383ffff */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16init_line_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fd2000fffe03f */
/*0080*/ I2F R0, UR4 ; /* 0x0000000400007d06 */
/* 0x000e220008201400 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*00a0*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f06270 */
/*00b0*/ BSSY B0, 0x250 ; /* 0x0000019000007945 */
/* 0x000fd80003800000 */
/*00c0*/ @!P0 BRA 0x240 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R2, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x001e220000001000 */
/*00f0*/ BSSY B1, 0x1c0 ; /* 0x000000c000017945 */
/* 0x000fee0003800000 */
/*0100*/ I2F R9, R3 ; /* 0x0000000300097306 */
/* 0x000e620000201400 */
/*0110*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x001fc80000000105 */
/*0120*/ FFMA R4, R5, R4, R5 ; /* 0x0000000405047223 */
/* 0x000fc60000000005 */
/*0130*/ FCHK P0, R9, R0 ; /* 0x0000000009007302 */
/* 0x002e220000000000 */
/*0140*/ FFMA R5, R9, R4, RZ ; /* 0x0000000409057223 */
/* 0x000fc800000000ff */
/*0150*/ FFMA R6, -R0, R5, R9 ; /* 0x0000000500067223 */
/* 0x000fc80000000109 */
/*0160*/ FFMA R4, R4, R6, R5 ; /* 0x0000000604047223 */
/* 0x000fe20000000005 */
/*0170*/ @!P0 BRA 0x1b0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0180*/ MOV R4, 0x1a0 ; /* 0x000001a000047802 */
/* 0x000fe40000000f00 */
/*0190*/ CALL.REL.NOINC 0x2a0 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*01b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01c0*/ FMUL R4, R4, 6.2831854820251464844 ; /* 0x40c90fdb04047820 */
/* 0x000fe40000400000 */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*01e0*/ FMUL.RZ R3, R4, 0.15915493667125701904 ; /* 0x3e22f98304037820 */
/* 0x000fe4000040c000 */
/*01f0*/ IMAD.WIDE R4, R2, R7, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0207 */
/*0200*/ MUFU.SIN R3, R3 ; /* 0x0000000300037308 */
/* 0x000e220000000400 */
/*0210*/ IMAD.WIDE R6, R2, R7, c[0x0][0x160] ; /* 0x0000580002067625 */
/* 0x000fe200078e0207 */
/*0220*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0011e8000c101904 */
/*0230*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0001e4000c101904 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*0260*/ IMAD R2, R3, c[0x0][0xc], R2 ; /* 0x0000030003027a24 */
/* 0x000fca00078e0202 */
/*0270*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f04270 */
/*0280*/ @!P0 BRA 0xa0 ; /* 0xfffffe1000008947 */
/* 0x000fea000383ffff */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ SHF.R.U32.HI R5, RZ, 0x17, R0.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011600 */
/*02b0*/ BSSY B2, 0x910 ; /* 0x0000065000027945 */
/* 0x000fe20003800000 */
/*02c0*/ SHF.R.U32.HI R3, RZ, 0x17, R9.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011609 */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0009 */
/*02e0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe200078ec0ff */
/*02f0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0300*/ LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030b7812 */
/* 0x000fe400078ec0ff */
/*0310*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fe40007ffe0ff */
/*0320*/ IADD3 R12, R11, -0x1, RZ ; /* 0xffffffff0b0c7810 */
/* 0x000fc40007ffe0ff */
/*0330*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*0340*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0350*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0360*/ @!P0 BRA 0x4f0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0370*/ FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe20003f3c200 */
/*0380*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0390*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f1c200 */
/*03a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*03b0*/ @P0 BRA 0x8f0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*03c0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*03d0*/ @!P0 BRA 0x8d0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*03e0*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*03f0*/ FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe40003f3d200 */
/*0400*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*0410*/ @!P1 BRA !P2, 0x8d0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0420*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*0430*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0440*/ @P1 BRA 0x8b0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0450*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0460*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0470*/ @P0 BRA 0x880 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0480*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0490*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*04a0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*04b0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*04c0*/ @!P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003068823 */
/* 0x000fe400000000ff */
/*04d0*/ @!P1 FFMA R7, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000079823 */
/* 0x000fe200000000ff */
/*04e0*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ LEA R10, R5, 0xc0800000, 0x17 ; /* 0xc0800000050a7811 */
/* 0x000fe200078eb8ff */
/*0500*/ BSSY B3, 0x870 ; /* 0x0000036000037945 */
/* 0x000fe80003800000 */
/*0510*/ IMAD.IADD R10, R7, 0x1, -R10 ; /* 0x00000001070a7824 */
/* 0x000fe200078e0a0a */
/*0520*/ IADD3 R7, R11, -0x7f, RZ ; /* 0xffffff810b077810 */
/* 0x000fc60007ffe0ff */
/*0530*/ MUFU.RCP R3, R10 ; /* 0x0000000a00037308 */
/* 0x000e220000001000 */
/*0540*/ FADD.FTZ R9, -R10, -RZ ; /* 0x800000ff0a097221 */
/* 0x000fe40000010100 */
/*0550*/ IMAD R6, R7.reuse, -0x800000, R6 ; /* 0xff80000007067824 */
/* 0x040fe200078e0206 */
/*0560*/ IADD3 R7, R7, 0x7f, -R5 ; /* 0x0000007f07077810 */
/* 0x000fca0007ffe805 */
/*0570*/ IMAD.IADD R8, R7, 0x1, R8 ; /* 0x0000000107087824 */
/* 0x000fe400078e0208 */
/*0580*/ FFMA R12, R3, R9, 1 ; /* 0x3f800000030c7423 */
/* 0x001fc80000000009 */
/*0590*/ FFMA R11, R3, R12, R3 ; /* 0x0000000c030b7223 */
/* 0x000fc80000000003 */
/*05a0*/ FFMA R3, R6, R11, RZ ; /* 0x0000000b06037223 */
/* 0x000fc800000000ff */
/*05b0*/ FFMA R12, R9, R3, R6 ; /* 0x00000003090c7223 */
/* 0x000fc80000000006 */
/*05c0*/ FFMA R12, R11, R12, R3 ; /* 0x0000000c0b0c7223 */
/* 0x000fc80000000003 */
/*05d0*/ FFMA R6, R9, R12, R6 ; /* 0x0000000c09067223 */
/* 0x000fc80000000006 */
/*05e0*/ FFMA R3, R11, R6, R12 ; /* 0x000000060b037223 */
/* 0x000fca000000000c */
/*05f0*/ SHF.R.U32.HI R5, RZ, 0x17, R3 ; /* 0x00000017ff057819 */
/* 0x000fc80000011603 */
/*0600*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0610*/ IMAD.IADD R9, R5, 0x1, R8 ; /* 0x0000000105097824 */
/* 0x000fca00078e0208 */
/*0620*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0630*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0640*/ @!P0 BRA 0x850 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0650*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0660*/ @P0 BRA 0x820 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0670*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0680*/ @P0 BRA 0x860 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0690*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*06a0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*06b0*/ @!P0 BRA 0x860 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*06c0*/ FFMA.RZ R5, R11, R6.reuse, R12.reuse ; /* 0x000000060b057223 */
/* 0x180fe2000000c00c */
/*06d0*/ IADD3 R8, R9.reuse, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x040fe40007ffe0ff */
/*06e0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*06f0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0700*/ FFMA.RP R5, R11, R6.reuse, R12.reuse ; /* 0x000000060b057223 */
/* 0x180fe2000000800c */
/*0710*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*0720*/ FFMA.RM R6, R11, R6, R12 ; /* 0x000000060b067223 */
/* 0x000fe2000000400c */
/*0730*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe200078efcff */
/*0740*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0a09 */
/*0750*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0760*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fe40003f1d000 */
/*0770*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0780*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0790*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*07a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*07b0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fe40000011606 */
/*07c0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*07d0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*07e0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*07f0*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*0800*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*0810*/ BRA 0x860 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0830*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0840*/ BRA 0x860 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0850*/ IMAD R3, R8, 0x800000, R3 ; /* 0x0080000008037824 */
/* 0x000fe400078e0203 */
/*0860*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0870*/ BRA 0x900 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0880*/ LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007037812 */
/* 0x000fc800078e4806 */
/*0890*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*08a0*/ BRA 0x900 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08b0*/ LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007037812 */
/* 0x000fe200078e4806 */
/*08c0*/ BRA 0x900 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*08d0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*08e0*/ BRA 0x900 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08f0*/ FADD.FTZ R3, R3, R0 ; /* 0x0000000003037221 */
/* 0x000fe40000010000 */
/*0900*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0910*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0920*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff6d004007950 */
/* 0x000fea0003c3ffff */
/*0930*/ BRA 0x930; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/* *********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
void check_param(void);
void printfinal (void);
int nsteps ,/* number of time steps */
tpoints ,/* total points along string */
rcode;/* generic return code */
/* *********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points , number of iterations */
while (( tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: " ,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if (( tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n", MINPOINTS , MAXPOINTS);
}
while (( nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints , nsteps);
}
/* **********************************************************************
Initialize points on line
*********************************************************************/
__global__ void init_line_kernel(float* oldval, float* values, int tpoints) {
int j;
float x, fac , k, tmp;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_num = blockDim.x * gridDim.x;
/* Calculate initial values based on sine curve */
fac = 2.0 * PI;
tmp = (float)(tpoints - 1);
for (j = thread_id; j <= tpoints; j += thread_num) {
if (j >= 0){
k = (float)(j - 1);
x = k/tmp;
values[j] = __sinf(fac * x); //GPU內建 __sinf
oldval[j] = values[j];
}
}
}
/* **********************************************************************
Update all values along line a specified number of times
*********************************************************************/
__global__ void update_kernel(float* oldval, float* values, float* newval, int nsteps, int tpoints){
int i, j;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_num = blockDim.x * gridDim.x;
/* Update values for each time step */
for (i = 1; i <= nsteps; i++) {
/* Update points along line for this time step */
for (j = thread_id; j <= tpoints; j += thread_num) {
/* global endpoints */
if ((j == 1) || (j == tpoints)){
newval[j] = 0.0;
}else {
/***********************************************************************
Calculate new values using wave equation
*********************************************************************/
float dtime , c, dx, tau , sqtau;
dtime = 0.3;
c = 1.0;
dx = 1.0;
tau = (c * dtime / dx);
sqtau = tau * tau;
newval[j] = (2.0 * values[j]) - oldval[j] + (sqtau * ( -2.0)*values[j]);
}
oldval[j] = values[j];
values[j] = newval[j];
}
}
}
/* **********************************************************************
Print final results
*********************************************************************/
void printfinal (float* values, int tpoints) {
int i;
for (i = 1; i <= tpoints; i++) {
printf("%6.4f ", values[i]);
if (i%10 == 0)
printf("\n");
}
}
/* **********************************************************************
Main program
*********************************************************************/
int main(int argc , char *argv []) {
sscanf(argv[1],"%d" ,&tpoints);
sscanf(argv[2],"%d" ,&nsteps);
check_param();
int threadinblock = 512;
int blocknum = (tpoints + threadinblock - 1)/threadinblock; // 無條件補上
//Host
float *oldval, *values, *newval;
oldval = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time (t-dt) */
values = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time t */
newval = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time (t+dt) */
//Device
float *gpu_oldval, *gpu_values, *gpu_newval;
cudaMalloc(&gpu_oldval, (tpoints + 2) * sizeof(float));
cudaMalloc(&gpu_values, (tpoints + 2) * sizeof(float));
cudaMalloc(&gpu_newval, (tpoints + 2) * sizeof(float));
printf("Initializing points on the line ...\n");
init_line_kernel <<<blocknum, threadinblock>>> (gpu_oldval, gpu_values, tpoints);
printf("Updating all points for all time steps ...\n");
update_kernel <<<blocknum, threadinblock>>> (gpu_oldval, gpu_values, gpu_newval, nsteps, tpoints);
//把資料送回Host
cudaMemcpy(oldval, gpu_oldval, (tpoints + 2) * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(values, gpu_values, (tpoints + 2) * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(newval, gpu_newval, (tpoints + 2) * sizeof(float), cudaMemcpyDeviceToHost);
printf("Printing final results ...\n");
printfinal(values, tpoints);
printf("\nDone .\n\n");
return 0;
}
|
.file "tmpxft_0005fa31_00000000-6_0513404.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter number of points along vibrating string [%d-%d]: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s"
.section .rodata.str1.8
.align 8
.LC2:
.string "Invalid. Please enter value between %d and %d\n"
.align 8
.LC3:
.string "Enter number of time steps [1-%d]: "
.align 8
.LC4:
.string "Invalid. Please enter value between 1 and %d\n"
.align 8
.LC5:
.string "Using points = %d, steps = %d\n"
.text
.globl _Z11check_paramv
.type _Z11check_paramv, @function
_Z11check_paramv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L5:
movl tpoints(%rip), %eax
subl $20, %eax
cmpl $999980, %eax
jbe .L14
movl $1000000, %ecx
movl $20, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, tpoints(%rip)
subl $20, %eax
cmpl $999980, %eax
jbe .L5
movl $1000000, %ecx
movl $20, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L14:
leaq .LC3(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L8:
movl nsteps(%rip), %ecx
leal -1(%rcx), %eax
cmpl $999999, %eax
jbe .L15
movl $1000000, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, nsteps(%rip)
subl $1, %eax
cmpl $999999, %eax
jbe .L8
movl $1000000, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L15:
movl tpoints(%rip), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_paramv, .-_Z11check_paramv
.section .rodata.str1.1
.LC6:
.string "%6.4f "
.LC7:
.string "\n"
.text
.globl _Z10printfinalPfi
.type _Z10printfinalPfi, @function
_Z10printfinalPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L23
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movl %esi, %ebp
movl $1, %ebx
leaq .LC6(%rip), %r13
leaq .LC7(%rip), %r14
jmp .L20
.L19:
addq $1, %rbx
cmpl %ebx, %ebp
jl .L26
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %ebx, %eax
jne .L19
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L26:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2058:
.size _Z10printfinalPfi, .-_Z10printfinalPfi
.globl _Z39__device_stub__Z16init_line_kernelPfS_iPfS_i
.type _Z39__device_stub__Z16init_line_kernelPfS_iPfS_i, @function
_Z39__device_stub__Z16init_line_kernelPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16init_line_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z16init_line_kernelPfS_iPfS_i, .-_Z39__device_stub__Z16init_line_kernelPfS_iPfS_i
.globl _Z16init_line_kernelPfS_i
.type _Z16init_line_kernelPfS_i, @function
_Z16init_line_kernelPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16init_line_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16init_line_kernelPfS_i, .-_Z16init_line_kernelPfS_i
.globl _Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii
.type _Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii, @function
_Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13update_kernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii, .-_Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii
.globl _Z13update_kernelPfS_S_ii
.type _Z13update_kernelPfS_S_ii, @function
_Z13update_kernelPfS_S_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13update_kernelPfS_S_ii, .-_Z13update_kernelPfS_S_ii
.section .rodata.str1.1
.LC8:
.string "%d"
.section .rodata.str1.8
.align 8
.LC9:
.string "Initializing points on the line ...\n"
.align 8
.LC10:
.string "Updating all points for all time steps ...\n"
.section .rodata.str1.1
.LC11:
.string "Printing final results ...\n"
.LC12:
.string "\nDone .\n\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
leaq tpoints(%rip), %rdx
leaq .LC8(%rip), %rbp
movq %rbp, %rsi
call __isoc23_sscanf@PLT
movq 16(%rbx), %rdi
leaq nsteps(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
call _Z11check_paramv
movl tpoints(%rip), %r14d
leal 2(%r14), %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl tpoints(%rip), %eax
leal 2(%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl tpoints(%rip), %eax
leal 2(%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 1022(%r14), %eax
addl $511, %r14d
cmovs %eax, %r14d
sarl $9, %r14d
movl %r14d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r14d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movl tpoints(%rip), %eax
leal 2(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl tpoints(%rip), %eax
leal 2(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl tpoints(%rip), %eax
leal 2(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl tpoints(%rip), %esi
movq %rbp, %rdi
call _Z10printfinalPfi
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movl tpoints(%rip), %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z16init_line_kernelPfS_iPfS_i
jmp .L44
.L49:
movl tpoints(%rip), %r8d
movl nsteps(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z13update_kernelPfS_S_ii"
.LC14:
.string "_Z16init_line_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z13update_kernelPfS_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z16init_line_kernelPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl rcode
.bss
.align 4
.type rcode, @object
.size rcode, 4
rcode:
.zero 4
.globl tpoints
.align 4
.type tpoints, @object
.size tpoints, 4
tpoints:
.zero 4
.globl nsteps
.align 4
.type nsteps, @object
.size nsteps, 4
nsteps:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/* *********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
void check_param(void);
void printfinal (void);
int nsteps ,/* number of time steps */
tpoints ,/* total points along string */
rcode;/* generic return code */
/* *********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points , number of iterations */
while (( tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: " ,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if (( tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n", MINPOINTS , MAXPOINTS);
}
while (( nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints , nsteps);
}
/* **********************************************************************
Initialize points on line
*********************************************************************/
__global__ void init_line_kernel(float* oldval, float* values, int tpoints) {
int j;
float x, fac , k, tmp;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_num = blockDim.x * gridDim.x;
/* Calculate initial values based on sine curve */
fac = 2.0 * PI;
tmp = (float)(tpoints - 1);
for (j = thread_id; j <= tpoints; j += thread_num) {
if (j >= 0){
k = (float)(j - 1);
x = k/tmp;
values[j] = __sinf(fac * x); //GPU內建 __sinf
oldval[j] = values[j];
}
}
}
/* **********************************************************************
Update all values along line a specified number of times
*********************************************************************/
__global__ void update_kernel(float* oldval, float* values, float* newval, int nsteps, int tpoints){
int i, j;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_num = blockDim.x * gridDim.x;
/* Update values for each time step */
for (i = 1; i <= nsteps; i++) {
/* Update points along line for this time step */
for (j = thread_id; j <= tpoints; j += thread_num) {
/* global endpoints */
if ((j == 1) || (j == tpoints)){
newval[j] = 0.0;
}else {
/***********************************************************************
Calculate new values using wave equation
*********************************************************************/
float dtime , c, dx, tau , sqtau;
dtime = 0.3;
c = 1.0;
dx = 1.0;
tau = (c * dtime / dx);
sqtau = tau * tau;
newval[j] = (2.0 * values[j]) - oldval[j] + (sqtau * ( -2.0)*values[j]);
}
oldval[j] = values[j];
values[j] = newval[j];
}
}
}
/* **********************************************************************
Print final results
*********************************************************************/
void printfinal (float* values, int tpoints) {
int i;
for (i = 1; i <= tpoints; i++) {
printf("%6.4f ", values[i]);
if (i%10 == 0)
printf("\n");
}
}
/* **********************************************************************
Main program
*********************************************************************/
int main(int argc , char *argv []) {
sscanf(argv[1],"%d" ,&tpoints);
sscanf(argv[2],"%d" ,&nsteps);
check_param();
int threadinblock = 512;
int blocknum = (tpoints + threadinblock - 1)/threadinblock; // 無條件補上
//Host
float *oldval, *values, *newval;
oldval = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time (t-dt) */
values = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time t */
newval = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time (t+dt) */
//Device
float *gpu_oldval, *gpu_values, *gpu_newval;
cudaMalloc(&gpu_oldval, (tpoints + 2) * sizeof(float));
cudaMalloc(&gpu_values, (tpoints + 2) * sizeof(float));
cudaMalloc(&gpu_newval, (tpoints + 2) * sizeof(float));
printf("Initializing points on the line ...\n");
init_line_kernel <<<blocknum, threadinblock>>> (gpu_oldval, gpu_values, tpoints);
printf("Updating all points for all time steps ...\n");
update_kernel <<<blocknum, threadinblock>>> (gpu_oldval, gpu_values, gpu_newval, nsteps, tpoints);
//把資料送回Host
cudaMemcpy(oldval, gpu_oldval, (tpoints + 2) * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(values, gpu_values, (tpoints + 2) * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(newval, gpu_newval, (tpoints + 2) * sizeof(float), cudaMemcpyDeviceToHost);
printf("Printing final results ...\n");
printfinal(values, tpoints);
printf("\nDone .\n\n");
return 0;
}
|
/* *********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
void check_param(void);
void printfinal (void);
int nsteps ,/* number of time steps */
tpoints ,/* total points along string */
rcode;/* generic return code */
/* *********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points , number of iterations */
while (( tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: " ,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if (( tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n", MINPOINTS , MAXPOINTS);
}
while (( nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints , nsteps);
}
/* **********************************************************************
Initialize points on line
*********************************************************************/
__global__ void init_line_kernel(float* oldval, float* values, int tpoints) {
int j;
float x, fac , k, tmp;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_num = blockDim.x * gridDim.x;
/* Calculate initial values based on sine curve */
fac = 2.0 * PI;
tmp = (float)(tpoints - 1);
for (j = thread_id; j <= tpoints; j += thread_num) {
if (j >= 0){
k = (float)(j - 1);
x = k/tmp;
values[j] = __sinf(fac * x); //GPU內建 __sinf
oldval[j] = values[j];
}
}
}
/* **********************************************************************
Update all values along line a specified number of times
*********************************************************************/
__global__ void update_kernel(float* oldval, float* values, float* newval, int nsteps, int tpoints){
int i, j;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_num = blockDim.x * gridDim.x;
/* Update values for each time step */
for (i = 1; i <= nsteps; i++) {
/* Update points along line for this time step */
for (j = thread_id; j <= tpoints; j += thread_num) {
/* global endpoints */
if ((j == 1) || (j == tpoints)){
newval[j] = 0.0;
}else {
/***********************************************************************
Calculate new values using wave equation
*********************************************************************/
float dtime , c, dx, tau , sqtau;
dtime = 0.3;
c = 1.0;
dx = 1.0;
tau = (c * dtime / dx);
sqtau = tau * tau;
newval[j] = (2.0 * values[j]) - oldval[j] + (sqtau * ( -2.0)*values[j]);
}
oldval[j] = values[j];
values[j] = newval[j];
}
}
}
/* **********************************************************************
Print final results
*********************************************************************/
void printfinal (float* values, int tpoints) {
int i;
for (i = 1; i <= tpoints; i++) {
printf("%6.4f ", values[i]);
if (i%10 == 0)
printf("\n");
}
}
/* **********************************************************************
Main program
*********************************************************************/
int main(int argc , char *argv []) {
sscanf(argv[1],"%d" ,&tpoints);
sscanf(argv[2],"%d" ,&nsteps);
check_param();
int threadinblock = 512;
int blocknum = (tpoints + threadinblock - 1)/threadinblock; // 無條件補上
//Host
float *oldval, *values, *newval;
oldval = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time (t-dt) */
values = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time t */
newval = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time (t+dt) */
//Device
float *gpu_oldval, *gpu_values, *gpu_newval;
hipMalloc(&gpu_oldval, (tpoints + 2) * sizeof(float));
hipMalloc(&gpu_values, (tpoints + 2) * sizeof(float));
hipMalloc(&gpu_newval, (tpoints + 2) * sizeof(float));
printf("Initializing points on the line ...\n");
init_line_kernel <<<blocknum, threadinblock>>> (gpu_oldval, gpu_values, tpoints);
printf("Updating all points for all time steps ...\n");
update_kernel <<<blocknum, threadinblock>>> (gpu_oldval, gpu_values, gpu_newval, nsteps, tpoints);
//把資料送回Host
hipMemcpy(oldval, gpu_oldval, (tpoints + 2) * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(values, gpu_values, (tpoints + 2) * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(newval, gpu_newval, (tpoints + 2) * sizeof(float), hipMemcpyDeviceToHost);
printf("Printing final results ...\n");
printfinal(values, tpoints);
printf("\nDone .\n\n");
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/* *********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
void check_param(void);
void printfinal (void);
int nsteps ,/* number of time steps */
tpoints ,/* total points along string */
rcode;/* generic return code */
/* *********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points , number of iterations */
while (( tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: " ,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if (( tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n", MINPOINTS , MAXPOINTS);
}
while (( nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints , nsteps);
}
/* **********************************************************************
Initialize points on line
*********************************************************************/
__global__ void init_line_kernel(float* oldval, float* values, int tpoints) {
int j;
float x, fac , k, tmp;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_num = blockDim.x * gridDim.x;
/* Calculate initial values based on sine curve */
fac = 2.0 * PI;
tmp = (float)(tpoints - 1);
for (j = thread_id; j <= tpoints; j += thread_num) {
if (j >= 0){
k = (float)(j - 1);
x = k/tmp;
values[j] = __sinf(fac * x); //GPU內建 __sinf
oldval[j] = values[j];
}
}
}
/* **********************************************************************
Update all values along line a specified number of times
*********************************************************************/
__global__ void update_kernel(float* oldval, float* values, float* newval, int nsteps, int tpoints){
int i, j;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_num = blockDim.x * gridDim.x;
/* Update values for each time step */
for (i = 1; i <= nsteps; i++) {
/* Update points along line for this time step */
for (j = thread_id; j <= tpoints; j += thread_num) {
/* global endpoints */
if ((j == 1) || (j == tpoints)){
newval[j] = 0.0;
}else {
/***********************************************************************
Calculate new values using wave equation
*********************************************************************/
float dtime , c, dx, tau , sqtau;
dtime = 0.3;
c = 1.0;
dx = 1.0;
tau = (c * dtime / dx);
sqtau = tau * tau;
newval[j] = (2.0 * values[j]) - oldval[j] + (sqtau * ( -2.0)*values[j]);
}
oldval[j] = values[j];
values[j] = newval[j];
}
}
}
/* **********************************************************************
Print final results
*********************************************************************/
void printfinal (float* values, int tpoints) {
int i;
for (i = 1; i <= tpoints; i++) {
printf("%6.4f ", values[i]);
if (i%10 == 0)
printf("\n");
}
}
/* **********************************************************************
Main program
*********************************************************************/
int main(int argc , char *argv []) {
sscanf(argv[1],"%d" ,&tpoints);
sscanf(argv[2],"%d" ,&nsteps);
check_param();
int threadinblock = 512;
int blocknum = (tpoints + threadinblock - 1)/threadinblock; // 無條件補上
//Host
float *oldval, *values, *newval;
oldval = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time (t-dt) */
values = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time t */
newval = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time (t+dt) */
//Device
float *gpu_oldval, *gpu_values, *gpu_newval;
hipMalloc(&gpu_oldval, (tpoints + 2) * sizeof(float));
hipMalloc(&gpu_values, (tpoints + 2) * sizeof(float));
hipMalloc(&gpu_newval, (tpoints + 2) * sizeof(float));
printf("Initializing points on the line ...\n");
init_line_kernel <<<blocknum, threadinblock>>> (gpu_oldval, gpu_values, tpoints);
printf("Updating all points for all time steps ...\n");
update_kernel <<<blocknum, threadinblock>>> (gpu_oldval, gpu_values, gpu_newval, nsteps, tpoints);
//把資料送回Host
hipMemcpy(oldval, gpu_oldval, (tpoints + 2) * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(values, gpu_values, (tpoints + 2) * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(newval, gpu_newval, (tpoints + 2) * sizeof(float), hipMemcpyDeviceToHost);
printf("Printing final results ...\n");
printfinal(values, tpoints);
printf("\nDone .\n\n");
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16init_line_kernelPfS_i
.globl _Z16init_line_kernelPfS_i
.p2align 8
.type _Z16init_line_kernelPfS_i,@function
_Z16init_line_kernelPfS_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_ge_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b32 s6, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
s_add_i32 s7, s4, -1
v_mov_b32_e32 v2, 0
v_cvt_f32_i32_e32 v0, s7
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s6, s5
s_mov_b32 s6, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, s4, v1
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_5
.LBB0_3:
s_mov_b32 s7, exec_lo
v_cmpx_lt_i32_e32 -1, v1
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v3, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v3, v3
v_div_scale_f32 v4, null, v0, v0, v3
v_div_scale_f32 v7, vcc_lo, v3, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v6
v_div_fixup_f32 v3, v4, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x40c90fdb, v3
v_mul_f32_e32 v5, 0.15915494, v3
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sin_f32_e32 v7, v5
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[5:6], v7, off
global_store_b32 v[3:4], v7, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16init_line_kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16init_line_kernelPfS_i, .Lfunc_end0-_Z16init_line_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13update_kernelPfS_S_ii
.globl _Z13update_kernelPfS_S_ii
.p2align 8
.type _Z13update_kernelPfS_S_ii,@function
_Z13update_kernelPfS_S_ii:
s_load_b32 s16, s[0:1], 0x18
s_mov_b32 s17, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s16, 1
s_cbranch_scc1 .LBB1_8
s_clause 0x3
s_load_b32 s10, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_brev_b32 s14, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s10, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mul_i32 s10, s3, s0
s_mov_b32 s15, 0xbfc70a3d
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[12:13], s[10:11], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_ge_i32_e32 vcc_lo, s2, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s0, s17, 1
s_cmp_lg_u32 s17, s16
s_mov_b32 s17, s0
s_cbranch_scc0 .LBB1_8
.LBB1_3:
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
v_mov_b32_e32 v0, v1
s_mov_b32 s11, 0
s_branch .LBB1_6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s1
v_add_co_u32 v7, s0, s8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s9, v5, s0
v_add_co_u32 v9, s0, s6, v4
v_add_co_ci_u32_e64 v10, s0, s7, v5, s0
global_store_b32 v[7:8], v6, off
v_add_co_u32 v11, s0, s4, v4
global_load_b32 v6, v[9:10], off
v_add_co_ci_u32_e64 v12, s0, s5, v5, s0
v_add_nc_u32_e32 v0, s10, v0
v_add_co_u32 v4, s1, v4, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s1, s13, v5, s1
v_cmp_lt_i32_e64 s0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s11, s0, s11
s_waitcnt vmcnt(0)
global_store_b32 v[11:12], v6, off
global_load_b32 v6, v[7:8], off
s_waitcnt vmcnt(0)
global_store_b32 v[9:10], v6, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB1_2
.LBB1_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s0, 1, v0
v_cmp_ne_u32_e64 s1, s2, v0
v_mov_b32_e32 v6, 0
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_5
v_add_co_u32 v6, s0, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s7, v5, s0
v_add_co_u32 v8, s0, s4, v4
v_add_co_ci_u32_e64 v9, s0, s5, v5, s0
global_load_b32 v6, v[6:7], off
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[6:7], v6
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], 2.0, -v[8:9]
v_fma_f64 v[6:7], v[6:7], s[14:15], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v6, v[6:7]
s_branch .LBB1_5
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13update_kernelPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13update_kernelPfS_S_ii, .Lfunc_end1-_Z13update_kernelPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16init_line_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16init_line_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13update_kernelPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z13update_kernelPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/* *********************************************************************
* DESCRIPTION:
* Serial Concurrent Wave Equation - C Version
* This program implements the concurrent wave equation
*********************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#define MAXPOINTS 1000000
#define MAXSTEPS 1000000
#define MINPOINTS 20
#define PI 3.14159265
void check_param(void);
void printfinal (void);
int nsteps ,/* number of time steps */
tpoints ,/* total points along string */
rcode;/* generic return code */
/* *********************************************************************
* Checks input values from parameters
*********************************************************************/
void check_param(void)
{
char tchar[20];
/* check number of points , number of iterations */
while (( tpoints < MINPOINTS) || (tpoints > MAXPOINTS)) {
printf("Enter number of points along vibrating string [%d-%d]: " ,MINPOINTS, MAXPOINTS);
scanf("%s", tchar);
tpoints = atoi(tchar);
if (( tpoints < MINPOINTS) || (tpoints > MAXPOINTS))
printf("Invalid. Please enter value between %d and %d\n", MINPOINTS , MAXPOINTS);
}
while (( nsteps < 1) || (nsteps > MAXSTEPS)) {
printf("Enter number of time steps [1-%d]: ", MAXSTEPS);
scanf("%s", tchar);
nsteps = atoi(tchar);
if ((nsteps < 1) || (nsteps > MAXSTEPS))
printf("Invalid. Please enter value between 1 and %d\n", MAXSTEPS);
}
printf("Using points = %d, steps = %d\n", tpoints , nsteps);
}
/* **********************************************************************
Initialize points on line
*********************************************************************/
__global__ void init_line_kernel(float* oldval, float* values, int tpoints) {
int j;
float x, fac , k, tmp;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_num = blockDim.x * gridDim.x;
/* Calculate initial values based on sine curve */
fac = 2.0 * PI;
tmp = (float)(tpoints - 1);
for (j = thread_id; j <= tpoints; j += thread_num) {
if (j >= 0){
k = (float)(j - 1);
x = k/tmp;
values[j] = __sinf(fac * x); //GPU內建 __sinf
oldval[j] = values[j];
}
}
}
/* **********************************************************************
Update all values along line a specified number of times
*********************************************************************/
__global__ void update_kernel(float* oldval, float* values, float* newval, int nsteps, int tpoints){
int i, j;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int thread_num = blockDim.x * gridDim.x;
/* Update values for each time step */
for (i = 1; i <= nsteps; i++) {
/* Update points along line for this time step */
for (j = thread_id; j <= tpoints; j += thread_num) {
/* global endpoints */
if ((j == 1) || (j == tpoints)){
newval[j] = 0.0;
}else {
/***********************************************************************
Calculate new values using wave equation
*********************************************************************/
float dtime , c, dx, tau , sqtau;
dtime = 0.3;
c = 1.0;
dx = 1.0;
tau = (c * dtime / dx);
sqtau = tau * tau;
newval[j] = (2.0 * values[j]) - oldval[j] + (sqtau * ( -2.0)*values[j]);
}
oldval[j] = values[j];
values[j] = newval[j];
}
}
}
/* **********************************************************************
Print final results
*********************************************************************/
void printfinal (float* values, int tpoints) {
int i;
for (i = 1; i <= tpoints; i++) {
printf("%6.4f ", values[i]);
if (i%10 == 0)
printf("\n");
}
}
/* **********************************************************************
Main program
*********************************************************************/
int main(int argc , char *argv []) {
sscanf(argv[1],"%d" ,&tpoints);
sscanf(argv[2],"%d" ,&nsteps);
check_param();
int threadinblock = 512;
int blocknum = (tpoints + threadinblock - 1)/threadinblock; // 無條件補上
//Host
float *oldval, *values, *newval;
oldval = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time (t-dt) */
values = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time t */
newval = (float*)malloc((tpoints + 2) * sizeof(float)); /* values at time (t+dt) */
//Device
float *gpu_oldval, *gpu_values, *gpu_newval;
hipMalloc(&gpu_oldval, (tpoints + 2) * sizeof(float));
hipMalloc(&gpu_values, (tpoints + 2) * sizeof(float));
hipMalloc(&gpu_newval, (tpoints + 2) * sizeof(float));
printf("Initializing points on the line ...\n");
init_line_kernel <<<blocknum, threadinblock>>> (gpu_oldval, gpu_values, tpoints);
printf("Updating all points for all time steps ...\n");
update_kernel <<<blocknum, threadinblock>>> (gpu_oldval, gpu_values, gpu_newval, nsteps, tpoints);
//把資料送回Host
hipMemcpy(oldval, gpu_oldval, (tpoints + 2) * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(values, gpu_values, (tpoints + 2) * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(newval, gpu_newval, (tpoints + 2) * sizeof(float), hipMemcpyDeviceToHost);
printf("Printing final results ...\n");
printfinal(values, tpoints);
printf("\nDone .\n\n");
return 0;
}
|
.text
.file "0513404.hip"
.globl _Z11check_paramv # -- Begin function _Z11check_paramv
.p2align 4, 0x90
.type _Z11check_paramv,@function
_Z11check_paramv: # @_Z11check_paramv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $-1000001, %ebp # imm = 0xFFF0BDBF
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_5
# %bb.1:
movq %rsp, %rbx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999981, %eax # imm = 0xFFF0BDD3
jae .LBB0_5
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, tpoints(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $.L.str.2, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_4
.LBB0_5: # %.preheader
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_10
# %bb.6:
movq %rsp, %rbx
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000000, %eax # imm = 0xFFF0BDC0
jae .LBB0_10
.LBB0_7: # %.lr.ph4
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, nsteps(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_9
# %bb.8: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.4, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_9
.LBB0_10: # %._crit_edge
movl tpoints(%rip), %esi
movl $.L.str.5, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11check_paramv, .Lfunc_end0-_Z11check_paramv
.cfi_endproc
# -- End function
.globl _Z31__device_stub__init_line_kernelPfS_i # -- Begin function _Z31__device_stub__init_line_kernelPfS_i
.p2align 4, 0x90
.type _Z31__device_stub__init_line_kernelPfS_i,@function
_Z31__device_stub__init_line_kernelPfS_i: # @_Z31__device_stub__init_line_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16init_line_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z31__device_stub__init_line_kernelPfS_i, .Lfunc_end1-_Z31__device_stub__init_line_kernelPfS_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__update_kernelPfS_S_ii # -- Begin function _Z28__device_stub__update_kernelPfS_S_ii
.p2align 4, 0x90
.type _Z28__device_stub__update_kernelPfS_S_ii,@function
_Z28__device_stub__update_kernelPfS_S_ii: # @_Z28__device_stub__update_kernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13update_kernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__update_kernelPfS_S_ii, .Lfunc_end2-_Z28__device_stub__update_kernelPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z10printfinalPfi # -- Begin function _Z10printfinalPfi
.p2align 4, 0x90
.type _Z10printfinalPfi,@function
_Z10printfinalPfi: # @_Z10printfinalPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_6
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl %esi, %eax
leaq 4(,%rax,4), %r14
movl $4, %r15d
movl $-1, %ebp
movl $1, %r12d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
addq $4, %r15
decl %ebp
incl %r12d
cmpq %r15, %r14
je .LBB3_5
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
movl $3435973837, %ecx # imm = 0xCCCCCCCD
imulq %rcx, %rax
shrq $35, %rax
leal (%rax,%rax,4), %r13d
addl %r13d, %r13d
movss (%rbx,%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
addl %ebp, %r13d
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_4
.LBB3_5:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB3_6: # %._crit_edge
retq
.Lfunc_end3:
.size _Z10printfinalPfi, .Lfunc_end3-_Z10printfinalPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movabsq $4294967808, %r12 # imm = 0x100000200
movq 8(%rsi), %rdi
movl $.L.str.8, %esi
movl $tpoints, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%rbx), %rdi
movl $.L.str.8, %esi
movl $nsteps, %edx
xorl %eax, %eax
callq __isoc23_sscanf
callq _Z11check_paramv
movslq tpoints(%rip), %rax
leal 511(%rax), %ecx
leal 1022(%rax), %ebp
testl %ecx, %ecx
cmovnsl %ecx, %ebp
sarl $9, %ebp
leaq 8(,%rax,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
callq malloc
movq %rax, 96(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movslq tpoints(%rip), %rax
leaq 8(,%rax,4), %rsi
movq %rsp, %rdi
callq hipMalloc
movslq tpoints(%rip), %rax
leaq 8(,%rax,4), %rsi
leaq 104(%rsp), %rdi
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
leaq (%r12,%rbp), %r13
addq $-512, %r13 # imm = 0xFE00
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movl tpoints(%rip), %edx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl %edx, 16(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16init_line_kernelPfS_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movl $.Lstr.1, %edi
callq puts@PLT
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 104(%rsp), %rdx
movl nsteps(%rip), %esi
movl tpoints(%rip), %edi
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl %esi, 92(%rsp)
movl %edi, 88(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 92(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13update_kernelPfS_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
movq 8(%rsp), %rsi
movslq tpoints(%rip), %rax
leaq 8(,%rax,4), %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movslq tpoints(%rip), %rax
leaq 8(,%rax,4), %rdx
movq 96(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 104(%rsp), %rsi
movslq tpoints(%rip), %rax
leaq 8(,%rax,4), %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movl tpoints(%rip), %eax
testl %eax, %eax
jle .LBB4_9
# %bb.5: # %.lr.ph.preheader.i
leaq 4(,%rax,4), %r14
movl $4, %r15d
movl $-1, %ebp
movl $1, %r12d
movl $3435973837, %r13d # imm = 0xCCCCCCCD
jmp .LBB4_6
.p2align 4, 0x90
.LBB4_8: # in Loop: Header=BB4_6 Depth=1
addq $4, %r15
decl %ebp
incl %r12d
cmpq %r15, %r14
je .LBB4_9
.LBB4_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
imulq %r13, %rax
shrq $35, %rax
leal (%rax,%rax,4), %ebx
addl %ebx, %ebx
movq 96(%rsp), %rax # 8-byte Reload
movss (%rax,%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
addl %ebp, %ebx
jne .LBB4_8
# %bb.7: # in Loop: Header=BB4_6 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB4_8
.LBB4_9: # %_Z10printfinalPfi.exit
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16init_line_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13update_kernelPfS_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type nsteps,@object # @nsteps
.bss
.globl nsteps
.p2align 2, 0x0
nsteps:
.long 0 # 0x0
.size nsteps, 4
.type tpoints,@object # @tpoints
.globl tpoints
.p2align 2, 0x0
tpoints:
.long 0 # 0x0
.size tpoints, 4
.type rcode,@object # @rcode
.globl rcode
.p2align 2, 0x0
rcode:
.long 0 # 0x0
.size rcode, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter number of points along vibrating string [%d-%d]: "
.size .L.str, 56
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid. Please enter value between %d and %d\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Enter number of time steps [1-%d]: "
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Invalid. Please enter value between 1 and %d\n"
.size .L.str.4, 46
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Using points = %d, steps = %d\n"
.size .L.str.5, 31
.type _Z16init_line_kernelPfS_i,@object # @_Z16init_line_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z16init_line_kernelPfS_i
.p2align 3, 0x0
_Z16init_line_kernelPfS_i:
.quad _Z31__device_stub__init_line_kernelPfS_i
.size _Z16init_line_kernelPfS_i, 8
.type _Z13update_kernelPfS_S_ii,@object # @_Z13update_kernelPfS_S_ii
.globl _Z13update_kernelPfS_S_ii
.p2align 3, 0x0
_Z13update_kernelPfS_S_ii:
.quad _Z28__device_stub__update_kernelPfS_S_ii
.size _Z13update_kernelPfS_S_ii, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "%6.4f "
.size .L.str.6, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d"
.size .L.str.8, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16init_line_kernelPfS_i"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13update_kernelPfS_S_ii"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initializing points on the line ..."
.size .Lstr, 36
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Updating all points for all time steps ..."
.size .Lstr.1, 43
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing final results ..."
.size .Lstr.2, 27
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nDone .\n"
.size .Lstr.3, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__init_line_kernelPfS_i
.addrsig_sym _Z28__device_stub__update_kernelPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym nsteps
.addrsig_sym tpoints
.addrsig_sym _Z16init_line_kernelPfS_i
.addrsig_sym _Z13update_kernelPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z13update_kernelPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e640000002100 */
/*0040*/ ISETP.LE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fda0003f03270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x003fe200078e0203 */
/*0070*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f04270 */
/*00a0*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x001fe2000f8e00ff */
/*00b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*00c0*/ BSSY B0, 0x2b0 ; /* 0x000001e000007945 */
/* 0x000fe60003800000 */
/*00d0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fce0003f26270 */
/*00e0*/ @P0 BRA 0x2a0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R12, R0 ; /* 0x00000000000c7202 */
/* 0x000fc80000000f00 */
/*0100*/ ISETP.NE.AND P0, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f05270 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fc600078e00ff */
/*0120*/ ISETP.EQ.OR P0, PT, R12.reuse, 0x1, !P0 ; /* 0x000000010c00780c */
/* 0x040fe20004702670 */
/*0130*/ IMAD.WIDE R2, R12, R5, c[0x0][0x168] ; /* 0x00005a000c027625 */
/* 0x000fc800078e0205 */
/*0140*/ IMAD.WIDE R4, R12, R5, c[0x0][0x160] ; /* 0x000058000c047625 */
/* 0x000fd000078e0205 */
/*0150*/ @!P0 LDG.E R13, [R2.64] ; /* 0x00000006020d8981 */
/* 0x000ea8000c1e1900 */
/*0160*/ @!P0 LDG.E R10, [R4.64] ; /* 0x00000006040a8981 */
/* 0x000ee2000c1e1900 */
/*0170*/ @!P0 F2F.F64.F32 R6, R13 ; /* 0x0000000d00068310 */
/* 0x004e300000201800 */
/*0180*/ @!P0 F2F.F64.F32 R10, R10 ; /* 0x0000000a000a8310 */
/* 0x008e620000201800 */
/*0190*/ @!P0 DADD R8, R6, R6 ; /* 0x0000000006088229 */
/* 0x001e4c0000000006 */
/*01a0*/ @!P0 DADD R8, R8, -R10 ; /* 0x0000000008088229 */
/* 0x002e0c000000080a */
/*01b0*/ @!P0 DFMA R8, R6, c[0x2][0x0], R8 ; /* 0x0080000006088a2b */
/* 0x0010640000000008 */
/*01c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R12 ; /* 0x0000001fff077819 */
/* 0x001fe4000001140c */
/*01d0*/ LEA R6, P2, R12.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c000c067a11 */
/* 0x040fe400078410ff */
/*01e0*/ @!P0 F2F.F32.F64 R11, R8 ; /* 0x00000008000b8310 */
/* 0x002e240000301000 */
/*01f0*/ LEA.HI.X R7, R12, c[0x0][0x174], R7, 0x2, P2 ; /* 0x00005d000c077a11 */
/* 0x000fe200010f1407 */
/*0200*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b0224 */
/* 0x000fca00078e00ff */
/*0210*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0011e8000c101906 */
/*0220*/ LDG.E R13, [R2.64] ; /* 0x00000006020d7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ MOV R17, c[0x0][0x0] ; /* 0x0000000000117a02 */
/* 0x000fc60000000f00 */
/*0240*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0041e8000c101906 */
/*0250*/ LDG.E R15, [R6.64] ; /* 0x00000006060f7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD R12, R17, c[0x0][0xc], R12 ; /* 0x00000300110c7a24 */
/* 0x000fca00078e020c */
/*0270*/ ISETP.GT.AND P0, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f04270 */
/*0280*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0041d8000c101906 */
/*0290*/ @!P0 BRA 0x100 ; /* 0xfffffe6000008947 */
/* 0x000fea000383ffff */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ @!P1 BRA 0x90 ; /* 0xfffffdd000009947 */
/* 0x000fea000383ffff */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16init_line_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fd2000fffe03f */
/*0080*/ I2F R0, UR4 ; /* 0x0000000400007d06 */
/* 0x000e220008201400 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*00a0*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f06270 */
/*00b0*/ BSSY B0, 0x250 ; /* 0x0000019000007945 */
/* 0x000fd80003800000 */
/*00c0*/ @!P0 BRA 0x240 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R2, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x001e220000001000 */
/*00f0*/ BSSY B1, 0x1c0 ; /* 0x000000c000017945 */
/* 0x000fee0003800000 */
/*0100*/ I2F R9, R3 ; /* 0x0000000300097306 */
/* 0x000e620000201400 */
/*0110*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x001fc80000000105 */
/*0120*/ FFMA R4, R5, R4, R5 ; /* 0x0000000405047223 */
/* 0x000fc60000000005 */
/*0130*/ FCHK P0, R9, R0 ; /* 0x0000000009007302 */
/* 0x002e220000000000 */
/*0140*/ FFMA R5, R9, R4, RZ ; /* 0x0000000409057223 */
/* 0x000fc800000000ff */
/*0150*/ FFMA R6, -R0, R5, R9 ; /* 0x0000000500067223 */
/* 0x000fc80000000109 */
/*0160*/ FFMA R4, R4, R6, R5 ; /* 0x0000000604047223 */
/* 0x000fe20000000005 */
/*0170*/ @!P0 BRA 0x1b0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0180*/ MOV R4, 0x1a0 ; /* 0x000001a000047802 */
/* 0x000fe40000000f00 */
/*0190*/ CALL.REL.NOINC 0x2a0 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*01b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01c0*/ FMUL R4, R4, 6.2831854820251464844 ; /* 0x40c90fdb04047820 */
/* 0x000fe40000400000 */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*01e0*/ FMUL.RZ R3, R4, 0.15915493667125701904 ; /* 0x3e22f98304037820 */
/* 0x000fe4000040c000 */
/*01f0*/ IMAD.WIDE R4, R2, R7, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0207 */
/*0200*/ MUFU.SIN R3, R3 ; /* 0x0000000300037308 */
/* 0x000e220000000400 */
/*0210*/ IMAD.WIDE R6, R2, R7, c[0x0][0x160] ; /* 0x0000580002067625 */
/* 0x000fe200078e0207 */
/*0220*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0011e8000c101904 */
/*0230*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0001e4000c101904 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*0260*/ IMAD R2, R3, c[0x0][0xc], R2 ; /* 0x0000030003027a24 */
/* 0x000fca00078e0202 */
/*0270*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f04270 */
/*0280*/ @!P0 BRA 0xa0 ; /* 0xfffffe1000008947 */
/* 0x000fea000383ffff */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ SHF.R.U32.HI R5, RZ, 0x17, R0.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011600 */
/*02b0*/ BSSY B2, 0x910 ; /* 0x0000065000027945 */
/* 0x000fe20003800000 */
/*02c0*/ SHF.R.U32.HI R3, RZ, 0x17, R9.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011609 */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0009 */
/*02e0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe200078ec0ff */
/*02f0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0300*/ LOP3.LUT R11, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff030b7812 */
/* 0x000fe400078ec0ff */
/*0310*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fe40007ffe0ff */
/*0320*/ IADD3 R12, R11, -0x1, RZ ; /* 0xffffffff0b0c7810 */
/* 0x000fc40007ffe0ff */
/*0330*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*0340*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0350*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0360*/ @!P0 BRA 0x4f0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0370*/ FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe20003f3c200 */
/*0380*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0390*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f1c200 */
/*03a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*03b0*/ @P0 BRA 0x8f0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*03c0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*03d0*/ @!P0 BRA 0x8d0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*03e0*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*03f0*/ FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe40003f3d200 */
/*0400*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*0410*/ @!P1 BRA !P2, 0x8d0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0420*/ LOP3.LUT P2, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000784c0ff */
/*0430*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0440*/ @P1 BRA 0x8b0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0450*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0460*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0470*/ @P0 BRA 0x880 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0480*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0490*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*04a0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*04b0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, -0x40 ; /* 0xffffffc0ff088424 */
/* 0x000fe400078e00ff */
/*04c0*/ @!P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003068823 */
/* 0x000fe400000000ff */
/*04d0*/ @!P1 FFMA R7, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000079823 */
/* 0x000fe200000000ff */
/*04e0*/ @!P1 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008089810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ LEA R10, R5, 0xc0800000, 0x17 ; /* 0xc0800000050a7811 */
/* 0x000fe200078eb8ff */
/*0500*/ BSSY B3, 0x870 ; /* 0x0000036000037945 */
/* 0x000fe80003800000 */
/*0510*/ IMAD.IADD R10, R7, 0x1, -R10 ; /* 0x00000001070a7824 */
/* 0x000fe200078e0a0a */
/*0520*/ IADD3 R7, R11, -0x7f, RZ ; /* 0xffffff810b077810 */
/* 0x000fc60007ffe0ff */
/*0530*/ MUFU.RCP R3, R10 ; /* 0x0000000a00037308 */
/* 0x000e220000001000 */
/*0540*/ FADD.FTZ R9, -R10, -RZ ; /* 0x800000ff0a097221 */
/* 0x000fe40000010100 */
/*0550*/ IMAD R6, R7.reuse, -0x800000, R6 ; /* 0xff80000007067824 */
/* 0x040fe200078e0206 */
/*0560*/ IADD3 R7, R7, 0x7f, -R5 ; /* 0x0000007f07077810 */
/* 0x000fca0007ffe805 */
/*0570*/ IMAD.IADD R8, R7, 0x1, R8 ; /* 0x0000000107087824 */
/* 0x000fe400078e0208 */
/*0580*/ FFMA R12, R3, R9, 1 ; /* 0x3f800000030c7423 */
/* 0x001fc80000000009 */
/*0590*/ FFMA R11, R3, R12, R3 ; /* 0x0000000c030b7223 */
/* 0x000fc80000000003 */
/*05a0*/ FFMA R3, R6, R11, RZ ; /* 0x0000000b06037223 */
/* 0x000fc800000000ff */
/*05b0*/ FFMA R12, R9, R3, R6 ; /* 0x00000003090c7223 */
/* 0x000fc80000000006 */
/*05c0*/ FFMA R12, R11, R12, R3 ; /* 0x0000000c0b0c7223 */
/* 0x000fc80000000003 */
/*05d0*/ FFMA R6, R9, R12, R6 ; /* 0x0000000c09067223 */
/* 0x000fc80000000006 */
/*05e0*/ FFMA R3, R11, R6, R12 ; /* 0x000000060b037223 */
/* 0x000fca000000000c */
/*05f0*/ SHF.R.U32.HI R5, RZ, 0x17, R3 ; /* 0x00000017ff057819 */
/* 0x000fc80000011603 */
/*0600*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0610*/ IMAD.IADD R9, R5, 0x1, R8 ; /* 0x0000000105097824 */
/* 0x000fca00078e0208 */
/*0620*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0630*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0640*/ @!P0 BRA 0x850 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0650*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0660*/ @P0 BRA 0x820 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0670*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0680*/ @P0 BRA 0x860 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0690*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*06a0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*06b0*/ @!P0 BRA 0x860 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*06c0*/ FFMA.RZ R5, R11, R6.reuse, R12.reuse ; /* 0x000000060b057223 */
/* 0x180fe2000000c00c */
/*06d0*/ IADD3 R8, R9.reuse, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x040fe40007ffe0ff */
/*06e0*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*06f0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0700*/ FFMA.RP R5, R11, R6.reuse, R12.reuse ; /* 0x000000060b057223 */
/* 0x180fe2000000800c */
/*0710*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*0720*/ FFMA.RM R6, R11, R6, R12 ; /* 0x000000060b067223 */
/* 0x000fe2000000400c */
/*0730*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe200078efcff */
/*0740*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0a09 */
/*0750*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0760*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fe40003f1d000 */
/*0770*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0780*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0790*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*07a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*07b0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fe40000011606 */
/*07c0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*07d0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*07e0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*07f0*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*0800*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*0810*/ BRA 0x860 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0830*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0840*/ BRA 0x860 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0850*/ IMAD R3, R8, 0x800000, R3 ; /* 0x0080000008037824 */
/* 0x000fe400078e0203 */
/*0860*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0870*/ BRA 0x900 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0880*/ LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007037812 */
/* 0x000fc800078e4806 */
/*0890*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*08a0*/ BRA 0x900 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08b0*/ LOP3.LUT R3, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007037812 */
/* 0x000fe200078e4806 */
/*08c0*/ BRA 0x900 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*08d0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*08e0*/ BRA 0x900 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08f0*/ FADD.FTZ R3, R3, R0 ; /* 0x0000000003037221 */
/* 0x000fe40000010000 */
/*0900*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0910*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0920*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff6d004007950 */
/* 0x000fea0003c3ffff */
/*0930*/ BRA 0x930; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16init_line_kernelPfS_i
.globl _Z16init_line_kernelPfS_i
.p2align 8
.type _Z16init_line_kernelPfS_i,@function
_Z16init_line_kernelPfS_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_ge_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b32 s6, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
s_add_i32 s7, s4, -1
v_mov_b32_e32 v2, 0
v_cvt_f32_i32_e32 v0, s7
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s6, s5
s_mov_b32 s6, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, s4, v1
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_5
.LBB0_3:
s_mov_b32 s7, exec_lo
v_cmpx_lt_i32_e32 -1, v1
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v3, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v3, v3
v_div_scale_f32 v4, null, v0, v0, v3
v_div_scale_f32 v7, vcc_lo, v3, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v6
v_div_fixup_f32 v3, v4, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x40c90fdb, v3
v_mul_f32_e32 v5, 0.15915494, v3
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sin_f32_e32 v7, v5
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[5:6], v7, off
global_store_b32 v[3:4], v7, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16init_line_kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16init_line_kernelPfS_i, .Lfunc_end0-_Z16init_line_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13update_kernelPfS_S_ii
.globl _Z13update_kernelPfS_S_ii
.p2align 8
.type _Z13update_kernelPfS_S_ii,@function
_Z13update_kernelPfS_S_ii:
s_load_b32 s16, s[0:1], 0x18
s_mov_b32 s17, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s16, 1
s_cbranch_scc1 .LBB1_8
s_clause 0x3
s_load_b32 s10, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_brev_b32 s14, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s10, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
s_mul_i32 s10, s3, s0
s_mov_b32 s15, 0xbfc70a3d
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[12:13], s[10:11], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_ge_i32_e32 vcc_lo, s2, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s0, s17, 1
s_cmp_lg_u32 s17, s16
s_mov_b32 s17, s0
s_cbranch_scc0 .LBB1_8
.LBB1_3:
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
v_mov_b32_e32 v0, v1
s_mov_b32 s11, 0
s_branch .LBB1_6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s1
v_add_co_u32 v7, s0, s8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s9, v5, s0
v_add_co_u32 v9, s0, s6, v4
v_add_co_ci_u32_e64 v10, s0, s7, v5, s0
global_store_b32 v[7:8], v6, off
v_add_co_u32 v11, s0, s4, v4
global_load_b32 v6, v[9:10], off
v_add_co_ci_u32_e64 v12, s0, s5, v5, s0
v_add_nc_u32_e32 v0, s10, v0
v_add_co_u32 v4, s1, v4, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s1, s13, v5, s1
v_cmp_lt_i32_e64 s0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s11, s0, s11
s_waitcnt vmcnt(0)
global_store_b32 v[11:12], v6, off
global_load_b32 v6, v[7:8], off
s_waitcnt vmcnt(0)
global_store_b32 v[9:10], v6, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB1_2
.LBB1_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s0, 1, v0
v_cmp_ne_u32_e64 s1, s2, v0
v_mov_b32_e32 v6, 0
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_5
v_add_co_u32 v6, s0, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s7, v5, s0
v_add_co_u32 v8, s0, s4, v4
v_add_co_ci_u32_e64 v9, s0, s5, v5, s0
global_load_b32 v6, v[6:7], off
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[6:7], v6
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], 2.0, -v[8:9]
v_fma_f64 v[6:7], v[6:7], s[14:15], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v6, v[6:7]
s_branch .LBB1_5
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13update_kernelPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13update_kernelPfS_S_ii, .Lfunc_end1-_Z13update_kernelPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16init_line_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16init_line_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13update_kernelPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z13update_kernelPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0005fa31_00000000-6_0513404.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter number of points along vibrating string [%d-%d]: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s"
.section .rodata.str1.8
.align 8
.LC2:
.string "Invalid. Please enter value between %d and %d\n"
.align 8
.LC3:
.string "Enter number of time steps [1-%d]: "
.align 8
.LC4:
.string "Invalid. Please enter value between 1 and %d\n"
.align 8
.LC5:
.string "Using points = %d, steps = %d\n"
.text
.globl _Z11check_paramv
.type _Z11check_paramv, @function
_Z11check_paramv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L5:
movl tpoints(%rip), %eax
subl $20, %eax
cmpl $999980, %eax
jbe .L14
movl $1000000, %ecx
movl $20, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, tpoints(%rip)
subl $20, %eax
cmpl $999980, %eax
jbe .L5
movl $1000000, %ecx
movl $20, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L14:
leaq .LC3(%rip), %r12
movq %rsp, %rbx
leaq .LC1(%rip), %rbp
.L8:
movl nsteps(%rip), %ecx
leal -1(%rcx), %eax
cmpl $999999, %eax
jbe .L15
movl $1000000, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
movl %eax, nsteps(%rip)
subl $1, %eax
cmpl $999999, %eax
jbe .L8
movl $1000000, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L15:
movl tpoints(%rip), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11check_paramv, .-_Z11check_paramv
.section .rodata.str1.1
.LC6:
.string "%6.4f "
.LC7:
.string "\n"
.text
.globl _Z10printfinalPfi
.type _Z10printfinalPfi, @function
_Z10printfinalPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L23
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movl %esi, %ebp
movl $1, %ebx
leaq .LC6(%rip), %r13
leaq .LC7(%rip), %r14
jmp .L20
.L19:
addq $1, %rbx
cmpl %ebx, %ebp
jl .L26
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %ebx, %eax
jne .L19
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L26:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2058:
.size _Z10printfinalPfi, .-_Z10printfinalPfi
.globl _Z39__device_stub__Z16init_line_kernelPfS_iPfS_i
.type _Z39__device_stub__Z16init_line_kernelPfS_iPfS_i, @function
_Z39__device_stub__Z16init_line_kernelPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16init_line_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z16init_line_kernelPfS_iPfS_i, .-_Z39__device_stub__Z16init_line_kernelPfS_iPfS_i
.globl _Z16init_line_kernelPfS_i
.type _Z16init_line_kernelPfS_i, @function
_Z16init_line_kernelPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16init_line_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16init_line_kernelPfS_i, .-_Z16init_line_kernelPfS_i
.globl _Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii
.type _Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii, @function
_Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13update_kernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii, .-_Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii
.globl _Z13update_kernelPfS_S_ii
.type _Z13update_kernelPfS_S_ii, @function
_Z13update_kernelPfS_S_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13update_kernelPfS_S_ii, .-_Z13update_kernelPfS_S_ii
.section .rodata.str1.1
.LC8:
.string "%d"
.section .rodata.str1.8
.align 8
.LC9:
.string "Initializing points on the line ...\n"
.align 8
.LC10:
.string "Updating all points for all time steps ...\n"
.section .rodata.str1.1
.LC11:
.string "Printing final results ...\n"
.LC12:
.string "\nDone .\n\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
leaq tpoints(%rip), %rdx
leaq .LC8(%rip), %rbp
movq %rbp, %rsi
call __isoc23_sscanf@PLT
movq 16(%rbx), %rdi
leaq nsteps(%rip), %rdx
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
call _Z11check_paramv
movl tpoints(%rip), %r14d
leal 2(%r14), %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl tpoints(%rip), %eax
leal 2(%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl tpoints(%rip), %eax
leal 2(%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 1022(%r14), %eax
addl $511, %r14d
cmovs %eax, %r14d
sarl $9, %r14d
movl %r14d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r14d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movl tpoints(%rip), %eax
leal 2(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl tpoints(%rip), %eax
leal 2(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl tpoints(%rip), %eax
leal 2(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl tpoints(%rip), %esi
movq %rbp, %rdi
call _Z10printfinalPfi
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movl tpoints(%rip), %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z16init_line_kernelPfS_iPfS_i
jmp .L44
.L49:
movl tpoints(%rip), %r8d
movl nsteps(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z13update_kernelPfS_S_iiPfS_S_ii
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z13update_kernelPfS_S_ii"
.LC14:
.string "_Z16init_line_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z13update_kernelPfS_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z16init_line_kernelPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl rcode
.bss
.align 4
.type rcode, @object
.size rcode, 4
rcode:
.zero 4
.globl tpoints
.align 4
.type tpoints, @object
.size tpoints, 4
tpoints:
.zero 4
.globl nsteps
.align 4
.type nsteps, @object
.size nsteps, 4
nsteps:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "0513404.hip"
.globl _Z11check_paramv # -- Begin function _Z11check_paramv
.p2align 4, 0x90
.type _Z11check_paramv,@function
_Z11check_paramv: # @_Z11check_paramv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $-1000001, %ebp # imm = 0xFFF0BDBF
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_5
# %bb.1:
movq %rsp, %rbx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl tpoints(%rip), %eax
addl %ebp, %eax
cmpl $-999981, %eax # imm = 0xFFF0BDD3
jae .LBB0_5
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, tpoints(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-999982, %eax # imm = 0xFFF0BDD2
ja .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $.L.str.2, %edi
movl $20, %esi
movl $1000000, %edx # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_4
.LBB0_5: # %.preheader
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_10
# %bb.6:
movq %rsp, %rbx
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_7 Depth=1
movl nsteps(%rip), %edx
leal -1000001(%rdx), %eax
cmpl $-1000000, %eax # imm = 0xFFF0BDC0
jae .LBB0_10
.LBB0_7: # %.lr.ph4
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, nsteps(%rip)
addl $-1000001, %eax # imm = 0xFFF0BDBF
cmpl $-1000001, %eax # imm = 0xFFF0BDBF
ja .LBB0_9
# %bb.8: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.4, %edi
movl $1000000, %esi # imm = 0xF4240
xorl %eax, %eax
callq printf
jmp .LBB0_9
.LBB0_10: # %._crit_edge
movl tpoints(%rip), %esi
movl $.L.str.5, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11check_paramv, .Lfunc_end0-_Z11check_paramv
.cfi_endproc
# -- End function
.globl _Z31__device_stub__init_line_kernelPfS_i # -- Begin function _Z31__device_stub__init_line_kernelPfS_i
.p2align 4, 0x90
.type _Z31__device_stub__init_line_kernelPfS_i,@function
_Z31__device_stub__init_line_kernelPfS_i: # @_Z31__device_stub__init_line_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16init_line_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z31__device_stub__init_line_kernelPfS_i, .Lfunc_end1-_Z31__device_stub__init_line_kernelPfS_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__update_kernelPfS_S_ii # -- Begin function _Z28__device_stub__update_kernelPfS_S_ii
.p2align 4, 0x90
.type _Z28__device_stub__update_kernelPfS_S_ii,@function
_Z28__device_stub__update_kernelPfS_S_ii: # @_Z28__device_stub__update_kernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13update_kernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__update_kernelPfS_S_ii, .Lfunc_end2-_Z28__device_stub__update_kernelPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z10printfinalPfi # -- Begin function _Z10printfinalPfi
.p2align 4, 0x90
.type _Z10printfinalPfi,@function
_Z10printfinalPfi: # @_Z10printfinalPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_6
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl %esi, %eax
leaq 4(,%rax,4), %r14
movl $4, %r15d
movl $-1, %ebp
movl $1, %r12d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
addq $4, %r15
decl %ebp
incl %r12d
cmpq %r15, %r14
je .LBB3_5
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
movl $3435973837, %ecx # imm = 0xCCCCCCCD
imulq %rcx, %rax
shrq $35, %rax
leal (%rax,%rax,4), %r13d
addl %r13d, %r13d
movss (%rbx,%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
addl %ebp, %r13d
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_4
.LBB3_5:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB3_6: # %._crit_edge
retq
.Lfunc_end3:
.size _Z10printfinalPfi, .Lfunc_end3-_Z10printfinalPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movabsq $4294967808, %r12 # imm = 0x100000200
movq 8(%rsi), %rdi
movl $.L.str.8, %esi
movl $tpoints, %edx
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%rbx), %rdi
movl $.L.str.8, %esi
movl $nsteps, %edx
xorl %eax, %eax
callq __isoc23_sscanf
callq _Z11check_paramv
movslq tpoints(%rip), %rax
leal 511(%rax), %ecx
leal 1022(%rax), %ebp
testl %ecx, %ecx
cmovnsl %ecx, %ebp
sarl $9, %ebp
leaq 8(,%rax,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
callq malloc
movq %rax, 96(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movslq tpoints(%rip), %rax
leaq 8(,%rax,4), %rsi
movq %rsp, %rdi
callq hipMalloc
movslq tpoints(%rip), %rax
leaq 8(,%rax,4), %rsi
leaq 104(%rsp), %rdi
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
leaq (%r12,%rbp), %r13
addq $-512, %r13 # imm = 0xFE00
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movl tpoints(%rip), %edx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl %edx, 16(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16init_line_kernelPfS_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movl $.Lstr.1, %edi
callq puts@PLT
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 104(%rsp), %rdx
movl nsteps(%rip), %esi
movl tpoints(%rip), %edi
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl %esi, 92(%rsp)
movl %edi, 88(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 92(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13update_kernelPfS_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
movq 8(%rsp), %rsi
movslq tpoints(%rip), %rax
leaq 8(,%rax,4), %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movslq tpoints(%rip), %rax
leaq 8(,%rax,4), %rdx
movq 96(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 104(%rsp), %rsi
movslq tpoints(%rip), %rax
leaq 8(,%rax,4), %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movl tpoints(%rip), %eax
testl %eax, %eax
jle .LBB4_9
# %bb.5: # %.lr.ph.preheader.i
leaq 4(,%rax,4), %r14
movl $4, %r15d
movl $-1, %ebp
movl $1, %r12d
movl $3435973837, %r13d # imm = 0xCCCCCCCD
jmp .LBB4_6
.p2align 4, 0x90
.LBB4_8: # in Loop: Header=BB4_6 Depth=1
addq $4, %r15
decl %ebp
incl %r12d
cmpq %r15, %r14
je .LBB4_9
.LBB4_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
imulq %r13, %rax
shrq $35, %rax
leal (%rax,%rax,4), %ebx
addl %ebx, %ebx
movq 96(%rsp), %rax # 8-byte Reload
movss (%rax,%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
addl %ebp, %ebx
jne .LBB4_8
# %bb.7: # in Loop: Header=BB4_6 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB4_8
.LBB4_9: # %_Z10printfinalPfi.exit
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16init_line_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13update_kernelPfS_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type nsteps,@object # @nsteps
.bss
.globl nsteps
.p2align 2, 0x0
nsteps:
.long 0 # 0x0
.size nsteps, 4
.type tpoints,@object # @tpoints
.globl tpoints
.p2align 2, 0x0
tpoints:
.long 0 # 0x0
.size tpoints, 4
.type rcode,@object # @rcode
.globl rcode
.p2align 2, 0x0
rcode:
.long 0 # 0x0
.size rcode, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter number of points along vibrating string [%d-%d]: "
.size .L.str, 56
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid. Please enter value between %d and %d\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Enter number of time steps [1-%d]: "
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Invalid. Please enter value between 1 and %d\n"
.size .L.str.4, 46
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Using points = %d, steps = %d\n"
.size .L.str.5, 31
.type _Z16init_line_kernelPfS_i,@object # @_Z16init_line_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z16init_line_kernelPfS_i
.p2align 3, 0x0
_Z16init_line_kernelPfS_i:
.quad _Z31__device_stub__init_line_kernelPfS_i
.size _Z16init_line_kernelPfS_i, 8
.type _Z13update_kernelPfS_S_ii,@object # @_Z13update_kernelPfS_S_ii
.globl _Z13update_kernelPfS_S_ii
.p2align 3, 0x0
_Z13update_kernelPfS_S_ii:
.quad _Z28__device_stub__update_kernelPfS_S_ii
.size _Z13update_kernelPfS_S_ii, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "%6.4f "
.size .L.str.6, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d"
.size .L.str.8, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16init_line_kernelPfS_i"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13update_kernelPfS_S_ii"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initializing points on the line ..."
.size .Lstr, 36
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Updating all points for all time steps ..."
.size .Lstr.1, 43
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Printing final results ..."
.size .Lstr.2, 27
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nDone .\n"
.size .Lstr.3, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__init_line_kernelPfS_i
.addrsig_sym _Z28__device_stub__update_kernelPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym nsteps
.addrsig_sym tpoints
.addrsig_sym _Z16init_line_kernelPfS_i
.addrsig_sym _Z13update_kernelPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <cstdio>
#include <cuda.h>
static const int ThreadsPerBlock = 512;
static int* d_maxlen;
static __global__ void collatz(const long start, const long stop, int* const maxlen)
{
// todo: process odd values from start (assume start to be odd) to stop (inclusively if stop is odd) with one thread per value (based on code from previous project)
const long i = threadIdx.x + blockIdx.x * (long)blockDim.x;
if(i+start < stop ) // Each thread does work if and only if less than the stop value
{
long val = 2*(i +((start-1)/2))+1;
int len = 1;
while(val != 1){
len++;
if((val % 2) == 0)//even
{val = val / 2;}
else //Odd
{val = 3 * val +1;}
} if(len > *maxlen){ atomicMax(maxlen, len);} // If greater than greatest length, becomes new max len;
}
}
void GPU_Init()
{
int maxlen = 0;
if (cudaSuccess != cudaMalloc((void **)&d_maxlen, sizeof(int))) {fprintf(stderr, "ERROR: could not allocate memory\n"); exit(-1);}
if (cudaSuccess != cudaMemcpy(d_maxlen, &maxlen, sizeof(int), cudaMemcpyHostToDevice)) {fprintf(stderr, "ERROR: copying to device failed\n"); exit(-1);}
}
void GPU_Exec(const long start, const long stop)
{
if (start <= stop) {
collatz<<<((stop - start + 2) / 2 + ThreadsPerBlock - 1) / ThreadsPerBlock, ThreadsPerBlock>>>(start, stop, d_maxlen);
}
}
int GPU_Fini()
{
int maxlen;
// todo: copy the result from the device to the host and free the device memory
if(cudaSuccess != cudaMemcpy(&maxlen, d_maxlen, sizeof(int), cudaMemcpyDeviceToHost)){fprintf(stderr, "Error: copying to host failed\n"); exit(-1);}
cudaFree(d_maxlen);
return maxlen;
}
|
code for sm_80
Function : _Z7collatzllPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0040*/ IMAD.WIDE.U32 R4, R5, c[0x0][0x0], R2 ; /* 0x0000000005047a25 */
/* 0x001fca00078e0002 */
/*0050*/ IADD3 R0, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004007a10 */
/* 0x000fc80007f3e0ff */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0070*/ IADD3.X R0, R5, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005007a10 */
/* 0x000fc80000ffe4ff */
/*0080*/ ISETP.GE.AND.EX P0, PT, R0, c[0x0][0x16c], PT, P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06300 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*00d0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*00e0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x000162000c1e1900 */
/*0100*/ UIADD3 UR4, UP0, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe2000ff1e13f */
/*0110*/ BSSY B0, 0x310 ; /* 0x000001f000007945 */
/* 0x000fe20003800000 */
/*0120*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fc400078e00ff */
/*0130*/ UIADD3.X UR5, UR7, -0x1, URZ, UP0, !UPT ; /* 0xffffffff07057890 */
/* 0x000fc800087fe43f */
/*0140*/ ULEA.HI UR4, UP0, UR5, UR4, URZ, 0x1 ; /* 0x0000000405047291 */
/* 0x000fc8000f81083f */
/*0150*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fc800087fe43f */
/*0160*/ USHF.R.S64 UR4, UR4, 0x1, UR5 ; /* 0x0000000104047899 */
/* 0x000fe40008001005 */
/*0170*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fc80008011405 */
/*0180*/ IADD3 R8, P0, R4, UR4, RZ ; /* 0x0000000404087c10 */
/* 0x000fc8000ff1e0ff */
/*0190*/ IADD3.X R5, R5, UR5, RZ, P0, !PT ; /* 0x0000000505057c10 */
/* 0x000fe400087fe4ff */
/*01a0*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*01b0*/ ISETP.NE.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0003f05300 */
/*01c0*/ @!P0 BRA 0x300 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.SHL.U32 R4, R8.reuse, 0x2, RZ ; /* 0x0000000208047824 */
/* 0x041fe200078e00ff */
/*01e0*/ SHF.L.U64.HI R8, R8, 0x1, R5 ; /* 0x0000000108087819 */
/* 0x000fe20000010205 */
/*01f0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fc600078e00ff */
/*0200*/ LOP3.LUT R4, R4, 0x1, RZ, 0xfc, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078efcff */
/*0210*/ LOP3.LUT R5, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104057812 */
/* 0x000fe400078ec0ff */
/*0220*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.NE.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fc80003f05070 */
/*0240*/ ISETP.NE.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05100 */
/*0250*/ @P0 LEA.HI R6, P1, R8.reuse, R4, RZ, 0x1 ; /* 0x0000000408060211 */
/* 0x040fe200078308ff */
/*0260*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x3 ; /* 0x00000003ff058424 */
/* 0x000fe400078e00ff */
/*0270*/ @!P0 IMAD R11, R8, 0x3, RZ ; /* 0x00000003080b8824 */
/* 0x000fe400078e02ff */
/*0280*/ @P0 IMAD.X R9, RZ, RZ, R8, P1 ; /* 0x000000ffff090224 */
/* 0x000fe400008e0608 */
/*0290*/ @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x2][0x0] ; /* 0x0080000004048625 */
/* 0x000fc600078e0005 */
/*02a0*/ @P0 SHF.R.S64 R4, R6, 0x1, R9 ; /* 0x0000000106040819 */
/* 0x000fe20000001009 */
/*02b0*/ @!P0 IMAD.IADD R8, R5, 0x1, R11 ; /* 0x0000000105088824 */
/* 0x000fe200078e020b */
/*02c0*/ @P0 SHF.R.S32.HI R8, RZ, 0x1, R9 ; /* 0x00000001ff080819 */
/* 0x000fe40000011409 */
/*02d0*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc80003f05070 */
/*02e0*/ ISETP.NE.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f05300 */
/*02f0*/ @P0 BRA 0x210 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0310*/ ISETP.GT.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f04270 */
/*0320*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0330*/ S2R R4, SR_LANEID ; /* 0x0000000000047919 */
/* 0x000e220000000000 */
/*0340*/ REDUX.MAX.S32 UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000e620000014200 */
/*0350*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0360*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*0370*/ ISETP.EQ.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x001fe2000bf02070 */
/*0380*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x002fd8000f8e00ff */
/*0390*/ @P0 RED.E.MAX.S32.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x000fe2000d10e388 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cstdio>
#include <cuda.h>
static const int ThreadsPerBlock = 512;
static int* d_maxlen;
static __global__ void collatz(const long start, const long stop, int* const maxlen)
{
// todo: process odd values from start (assume start to be odd) to stop (inclusively if stop is odd) with one thread per value (based on code from previous project)
const long i = threadIdx.x + blockIdx.x * (long)blockDim.x;
if(i+start < stop ) // Each thread does work if and only if less than the stop value
{
long val = 2*(i +((start-1)/2))+1;
int len = 1;
while(val != 1){
len++;
if((val % 2) == 0)//even
{val = val / 2;}
else //Odd
{val = 3 * val +1;}
} if(len > *maxlen){ atomicMax(maxlen, len);} // If greater than greatest length, becomes new max len;
}
}
void GPU_Init()
{
int maxlen = 0;
if (cudaSuccess != cudaMalloc((void **)&d_maxlen, sizeof(int))) {fprintf(stderr, "ERROR: could not allocate memory\n"); exit(-1);}
if (cudaSuccess != cudaMemcpy(d_maxlen, &maxlen, sizeof(int), cudaMemcpyHostToDevice)) {fprintf(stderr, "ERROR: copying to device failed\n"); exit(-1);}
}
void GPU_Exec(const long start, const long stop)
{
if (start <= stop) {
collatz<<<((stop - start + 2) / 2 + ThreadsPerBlock - 1) / ThreadsPerBlock, ThreadsPerBlock>>>(start, stop, d_maxlen);
}
}
int GPU_Fini()
{
int maxlen;
// todo: copy the result from the device to the host and free the device memory
if(cudaSuccess != cudaMemcpy(&maxlen, d_maxlen, sizeof(int), cudaMemcpyDeviceToHost)){fprintf(stderr, "Error: copying to host failed\n"); exit(-1);}
cudaFree(d_maxlen);
return maxlen;
}
|
.file "tmpxft_000234b5_00000000-6_collatz_hyb.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL28__device_stub__Z7collatzllPillPi, @function
_ZL28__device_stub__Z7collatzllPillPi:
.LFB2084:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL7collatzllPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _ZL28__device_stub__Z7collatzllPillPi, .-_ZL28__device_stub__Z7collatzllPillPi
.type _ZL7collatzllPi, @function
_ZL7collatzllPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL28__device_stub__Z7collatzllPillPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL7collatzllPi, .-_ZL7collatzllPi
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "ERROR: could not allocate memory\n"
.align 8
.LC1:
.string "ERROR: copying to device failed\n"
.text
.globl _Z8GPU_Initv
.type _Z8GPU_Initv, @function
_Z8GPU_Initv:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
movl $4, %esi
leaq _ZL8d_maxlen(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L16
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq _ZL8d_maxlen(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L17
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L17:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8GPU_Initv, .-_Z8GPU_Initv
.globl _Z8GPU_Execll
.type _Z8GPU_Execll, @function
_Z8GPU_Execll:
.LFB2058:
.cfi_startproc
endbr64
cmpq %rsi, %rdi
jle .L26
ret
.L26:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movq %rsi, %rdx
subq %rdi, %rdx
addq $2, %rdx
movq %rdx, %rax
shrq $63, %rax
addq %rdx, %rax
sarq %rax
leaq 1022(%rax), %rdx
addq $511, %rax
cmovs %rdx, %rax
sarq $9, %rax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L19:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq _ZL8d_maxlen(%rip), %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZL28__device_stub__Z7collatzllPillPi
jmp .L19
.cfi_endproc
.LFE2058:
.size _Z8GPU_Execll, .-_Z8GPU_Execll
.section .rodata.str1.8
.align 8
.LC2:
.string "Error: copying to host failed\n"
.text
.globl _Z8GPU_Finiv
.type _Z8GPU_Finiv, @function
_Z8GPU_Finiv:
.LFB2059:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq _ZL8d_maxlen(%rip), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
movq _ZL8d_maxlen(%rip), %rdi
call cudaFree@PLT
movl 4(%rsp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L33
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z8GPU_Finiv, .-_Z8GPU_Finiv
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z7collatzllPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7collatzllPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8d_maxlen
.comm _ZL8d_maxlen,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
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