system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
__global__ void print_indexs() {
printf("threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, gridDim.x: %d, gridDim.y: %d, gridDim.z: %d\n",
threadIdx.x, threadIdx.y, threadIdx.z, blockIdx.x, blockIdx.y, blockIdx.z, blockDim.x, blockDim.y, blockDim.z, gridDim.x, gridDim.y, gridDim.z);
}
int main() {
int nx = 16;
int ny = 16;
int nz = 16;
dim3 block(8,8,8);
dim3 grid(nx/block.x, ny/block.y, nz/block.z);
print_indexs<<<grid, block>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void print_indexs() {
printf("threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, gridDim.x: %d, gridDim.y: %d, gridDim.z: %d\n",
threadIdx.x, threadIdx.y, threadIdx.z, blockIdx.x, blockIdx.y, blockIdx.z, blockDim.x, blockDim.y, blockDim.z, gridDim.x, gridDim.y, gridDim.z);
}
int main() {
int nx = 16;
int ny = 16;
int nz = 16;
dim3 block(8,8,8);
dim3 grid(nx/block.x, ny/block.y, nz/block.z);
print_indexs<<<grid, block>>>();
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void print_indexs() {
printf("threadIdx.x: %d, threadIdx.y: %d, threadIdx.z: %d, blockIdx.x: %d, blockIdx.y: %d, blockIdx.z: %d, blockDim.x: %d, blockDim.y: %d, blockDim.z: %d, gridDim.x: %d, gridDim.y: %d, gridDim.z: %d\n",
threadIdx.x, threadIdx.y, threadIdx.z, blockIdx.x, blockIdx.y, blockIdx.z, blockDim.x, blockDim.y, blockDim.z, gridDim.x, gridDim.y, gridDim.z);
}
int main() {
int nx = 16;
int ny = 16;
int nz = 16;
dim3 block(8,8,8);
dim3 grid(nx/block.x, ny/block.y, nz/block.z);
print_indexs<<<grid, block>>>();
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} | .text
.file "program_ex1.hip"
.globl _Z27__device_stub__print_indexsv # -- Begin function _Z27__device_stub__print_indexsv
.p2align 4, 0x90
.type _Z27__device_stub__print_indexsv,@function
_Z27__device_stub__print_indexsv: # @_Z27__device_stub__print_indexsv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12print_indexsv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__print_indexsv, .Lfunc_end0-_Z27__device_stub__print_indexsv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $34359738376, %rdx # imm = 0x800000008
movl $2, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12print_indexsv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12print_indexsv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12print_indexsv,@object # @_Z12print_indexsv
.section .rodata,"a",@progbits
.globl _Z12print_indexsv
.p2align 3, 0x0
_Z12print_indexsv:
.quad _Z27__device_stub__print_indexsv
.size _Z12print_indexsv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12print_indexsv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__print_indexsv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12print_indexsv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00194645_00000000-6_program_ex1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12print_indexsvv
.type _Z31__device_stub__Z12print_indexsvv, @function
_Z31__device_stub__Z12print_indexsvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12print_indexsv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12print_indexsvv, .-_Z31__device_stub__Z12print_indexsvv
.globl _Z12print_indexsv
.type _Z12print_indexsv, @function
_Z12print_indexsv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12print_indexsvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12print_indexsv, .-_Z12print_indexsv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $8, 8(%rsp)
movl $8, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $8, %ecx
movq 20(%rsp), %rdi
movl $2, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12print_indexsvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12print_indexsv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12print_indexsv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "program_ex1.hip"
.globl _Z27__device_stub__print_indexsv # -- Begin function _Z27__device_stub__print_indexsv
.p2align 4, 0x90
.type _Z27__device_stub__print_indexsv,@function
_Z27__device_stub__print_indexsv: # @_Z27__device_stub__print_indexsv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12print_indexsv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__print_indexsv, .Lfunc_end0-_Z27__device_stub__print_indexsv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $34359738376, %rdx # imm = 0x800000008
movl $2, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12print_indexsv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12print_indexsv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12print_indexsv,@object # @_Z12print_indexsv
.section .rodata,"a",@progbits
.globl _Z12print_indexsv
.p2align 3, 0x0
_Z12print_indexsv:
.quad _Z27__device_stub__print_indexsv
.size _Z12print_indexsv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12print_indexsv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__print_indexsv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12print_indexsv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#define tile_width 16
using namespace std;
__global__ void Mat_Mul_Shared(float *d_A, float *d_B, float *d_C, int width) {
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float M[tile_width][tile_width];
__shared__ float N[tile_width][tile_width];
int n_tile = width / tile_width; //number of tiles
float value = 0;
for(int m=0; m < n_tile; m++ ){ // m loop of tiles
// copy from globalb memory to shared memory
M[threadIdx.y][threadIdx.x] = d_A[i*width + m*tile_width + threadIdx.x];
N[threadIdx.y][threadIdx.x] = d_B[(m*tile_width + threadIdx.y)*width + j];
__syncthreads(); // wait all threads finish copying
for(int k=0; k < tile_width; k++){ // k loop within a tile, in the m loop of tiles: together loop over width to perfomr the dot product of a row of d_A and a coloumn of d_B
value += M[threadIdx.y][k] * N[k][threadIdx.x]; // scalar value is in the register of a thread
}
__syncthreads(); // wait ll threads finish partial dot product
}
d_C[i*width + j] = value; // assign value in register of every thread to corresponding elements of d_C in global memory
}
int main(){
int n;
cin >> n;
int size = n*n*sizeof(float);
//float *A, *B, *C;
float *A = (float *) malloc( size ); // allocate CPU memory
float *B = (float *) malloc( size );
float *C = (float *) malloc( size );
for(int i=0; i<n; i++)
for(int j=0; j<n; j++){
int idx = i*n + j;
A[idx] = 1.;
B[idx] = 2.;
C[idx] = 0.;
}
float *d_A, *d_B, *d_C;
cudaMalloc(&d_A, size); // allocate GPU memory
cudaMalloc(&d_B, size);
cudaMalloc(&d_C, size);
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
int block_width = tile_width;
int grid_width = ceil(n/block_width);
// dim3 is a CUDA built-in struct
dim3 dim_grid(grid_width, grid_width); // num of blocks = (int(n/16) + 1)^2, efficient if > 6.
dim3 dim_block(block_width, block_width); // number of theads per block = 16*16 =256
Mat_Mul_Shared<<<dim_grid, dim_block>>> (d_A, d_B, d_C, n); // lauch kenel
cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost);
for(int i=0; i<n; i++)
for(int j=0; j<n; j++){
cout<<i<<" "<<j<<" "<<C[i*n+j]<<endl;
}
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);
free(A); free(B); free(C);
} | code for sm_80
Function : _Z14Mat_Mul_SharedPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R16, c[0x0][0x178] ; /* 0x00005e0000107a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R16, 0x10, PT ; /* 0x000000101000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e680000002600 */
/*0080*/ S2R R19, SR_TID.Y ; /* 0x0000000000137919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R4, R3, c[0x0][0x0], R0 ; /* 0x0000000003047a24 */
/* 0x001fe200078e0200 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R17, R17, c[0x0][0x4], R19 ; /* 0x0000010011117a24 */
/* 0x002fc800078e0213 */
/*00c0*/ IMAD R2, R17, c[0x0][0x178], R4 ; /* 0x00005e0011027a24 */
/* 0x000fca00078e0204 */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*00e0*/ @!P0 BRA 0x4a0 ; /* 0x000003b000008947 */
/* 0x000fea0003800000 */
/*00f0*/ SHF.R.S32.HI R5, RZ, 0x1f, R16 ; /* 0x0000001fff057819 */
/* 0x000fe20000011410 */
/*0100*/ IMAD R21, R19.reuse, c[0x0][0x178], R4 ; /* 0x00005e0013157a24 */
/* 0x040fe200078e0204 */
/*0110*/ SHF.L.U32 R19, R19, 0x6, RZ ; /* 0x0000000613137819 */
/* 0x000fe200000006ff */
/*0120*/ IMAD R17, R17, c[0x0][0x178], R0 ; /* 0x00005e0011117a24 */
/* 0x000fe200078e0200 */
/*0130*/ LEA.HI R5, R5, c[0x0][0x178], RZ, 0x4 ; /* 0x00005e0005057a11 */
/* 0x000fe200078f20ff */
/*0140*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0150*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0160*/ LEA R20, R0, R19, 0x2 ; /* 0x0000001300147211 */
/* 0x000fe400078e10ff */
/*0170*/ SHF.R.S32.HI R18, RZ, 0x4, R5 ; /* 0x00000004ff127819 */
/* 0x000fc40000011405 */
/*0180*/ MOV R10, 0x4 ; /* 0x00000004000a7802 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE.U32 R4, R17, R10, c[0x0][0x160] ; /* 0x0000580011047625 */
/* 0x000fc800078e000a */
/*01a0*/ IMAD.WIDE.U32 R10, R21, R10, c[0x0][0x168] ; /* 0x00005a00150a7625 */
/* 0x000fe200078e000a */
/*01b0*/ LDG.E R23, [R4.64] ; /* 0x0000000604177981 */
/* 0x000eaa000c1e1900 */
/*01c0*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000ee2000c1e1900 */
/*01d0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*01e0*/ IADD3 R17, R17, 0x10, RZ ; /* 0x0000001011117810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ LEA R21, R16, R21, 0x4 ; /* 0x0000001510157211 */
/* 0x000fc600078e20ff */
/*0200*/ ISETP.LE.AND P0, PT, R18, UR4, PT ; /* 0x0000000412007c0c */
/* 0x000fe2000bf03270 */
/*0210*/ STS [R20], R23 ; /* 0x0000001714007388 */
/* 0x004fe80000000800 */
/*0220*/ STS [R20+0x400], R11 ; /* 0x0004000b14007388 */
/* 0x008fe80000000800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ LDS R8, [R0.X4+0x400] ; /* 0x0004000000087984 */
/* 0x000fe80000004800 */
/*0250*/ LDS.128 R12, [R19] ; /* 0x00000000130c7984 */
/* 0x000e280000000c00 */
/*0260*/ LDS R25, [R0.X4+0x440] ; /* 0x0004400000197984 */
/* 0x000e680000004800 */
/*0270*/ LDS R28, [R0.X4+0x480] ; /* 0x00048000001c7984 */
/* 0x000ea80000004800 */
/*0280*/ LDS R26, [R0.X4+0x4c0] ; /* 0x0004c000001a7984 */
/* 0x000ee80000004800 */
/*0290*/ LDS R27, [R0.X4+0x500] ; /* 0x00050000001b7984 */
/* 0x000fe80000004800 */
/*02a0*/ LDS.128 R4, [R19+0x10] ; /* 0x0000100013047984 */
/* 0x000f280000000c00 */
/*02b0*/ LDS R24, [R0.X4+0x540] ; /* 0x0005400000187984 */
/* 0x000f680000004800 */
/*02c0*/ LDS R23, [R0.X4+0x580] ; /* 0x0005800000177984 */
/* 0x000f680000004800 */
/*02d0*/ LDS R22, [R0.X4+0x5c0] ; /* 0x0005c00000167984 */
/* 0x000f620000004800 */
/*02e0*/ FFMA R8, R8, R12, R9 ; /* 0x0000000c08087223 */
/* 0x001fc80000000009 */
/*02f0*/ FFMA R13, R25, R13, R8 ; /* 0x0000000d190d7223 */
/* 0x002fe40000000008 */
/*0300*/ LDS R25, [R0.X4+0x600] ; /* 0x0006000000197984 */
/* 0x000fe40000004800 */
/*0310*/ FFMA R13, R28, R14, R13 ; /* 0x0000000e1c0d7223 */
/* 0x004fe4000000000d */
/*0320*/ LDS.128 R8, [R19+0x20] ; /* 0x0000200013087984 */
/* 0x000e240000000c00 */
/*0330*/ FFMA R13, R26, R15, R13 ; /* 0x0000000f1a0d7223 */
/* 0x008fe4000000000d */
/*0340*/ LDS R26, [R0.X4+0x640] ; /* 0x00064000001a7984 */
/* 0x000e640000004800 */
/*0350*/ FFMA R4, R27, R4, R13 ; /* 0x000000041b047223 */
/* 0x010fc4000000000d */
/*0360*/ LDS R27, [R0.X4+0x680] ; /* 0x00068000001b7984 */
/* 0x000ea40000004800 */
/*0370*/ FFMA R5, R24, R5, R4 ; /* 0x0000000518057223 */
/* 0x020fe40000000004 */
/*0380*/ LDS R4, [R0.X4+0x6c0] ; /* 0x0006c00000047984 */
/* 0x000ee40000004800 */
/*0390*/ FFMA R6, R23, R6, R5 ; /* 0x0000000617067223 */
/* 0x000fe40000000005 */
/*03a0*/ LDS R5, [R0.X4+0x700] ; /* 0x0007000000057984 */
/* 0x000fe40000004800 */
/*03b0*/ FFMA R23, R22, R7, R6 ; /* 0x0000000716177223 */
/* 0x000fc40000000006 */
/*03c0*/ LDS.128 R12, [R19+0x30] ; /* 0x00003000130c7984 */
/* 0x000f280000000c00 */
/*03d0*/ LDS R22, [R0.X4+0x740] ; /* 0x0007400000167984 */
/* 0x000f680000004800 */
/*03e0*/ LDS R7, [R0.X4+0x780] ; /* 0x0007800000077984 */
/* 0x000f680000004800 */
/*03f0*/ LDS R6, [R0.X4+0x7c0] ; /* 0x0007c00000067984 */
/* 0x000f620000004800 */
/*0400*/ FFMA R8, R25, R8, R23 ; /* 0x0000000819087223 */
/* 0x001fc80000000017 */
/*0410*/ FFMA R8, R26, R9, R8 ; /* 0x000000091a087223 */
/* 0x002fc80000000008 */
/*0420*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*0430*/ FFMA R4, R4, R11, R8 ; /* 0x0000000b04047223 */
/* 0x008fc80000000008 */
/*0440*/ FFMA R4, R5, R12, R4 ; /* 0x0000000c05047223 */
/* 0x010fc80000000004 */
/*0450*/ FFMA R4, R22, R13, R4 ; /* 0x0000000d16047223 */
/* 0x020fc80000000004 */
/*0460*/ FFMA R4, R7, R14, R4 ; /* 0x0000000e07047223 */
/* 0x000fc80000000004 */
/*0470*/ FFMA R9, R6, R15, R4 ; /* 0x0000000f06097223 */
/* 0x000fe20000000004 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @!P0 BRA 0x180 ; /* 0xfffffce000008947 */
/* 0x000fea000383ffff */
/*04a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#define tile_width 16
using namespace std;
__global__ void Mat_Mul_Shared(float *d_A, float *d_B, float *d_C, int width) {
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float M[tile_width][tile_width];
__shared__ float N[tile_width][tile_width];
int n_tile = width / tile_width; //number of tiles
float value = 0;
for(int m=0; m < n_tile; m++ ){ // m loop of tiles
// copy from globalb memory to shared memory
M[threadIdx.y][threadIdx.x] = d_A[i*width + m*tile_width + threadIdx.x];
N[threadIdx.y][threadIdx.x] = d_B[(m*tile_width + threadIdx.y)*width + j];
__syncthreads(); // wait all threads finish copying
for(int k=0; k < tile_width; k++){ // k loop within a tile, in the m loop of tiles: together loop over width to perfomr the dot product of a row of d_A and a coloumn of d_B
value += M[threadIdx.y][k] * N[k][threadIdx.x]; // scalar value is in the register of a thread
}
__syncthreads(); // wait ll threads finish partial dot product
}
d_C[i*width + j] = value; // assign value in register of every thread to corresponding elements of d_C in global memory
}
int main(){
int n;
cin >> n;
int size = n*n*sizeof(float);
//float *A, *B, *C;
float *A = (float *) malloc( size ); // allocate CPU memory
float *B = (float *) malloc( size );
float *C = (float *) malloc( size );
for(int i=0; i<n; i++)
for(int j=0; j<n; j++){
int idx = i*n + j;
A[idx] = 1.;
B[idx] = 2.;
C[idx] = 0.;
}
float *d_A, *d_B, *d_C;
cudaMalloc(&d_A, size); // allocate GPU memory
cudaMalloc(&d_B, size);
cudaMalloc(&d_C, size);
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
int block_width = tile_width;
int grid_width = ceil(n/block_width);
// dim3 is a CUDA built-in struct
dim3 dim_grid(grid_width, grid_width); // num of blocks = (int(n/16) + 1)^2, efficient if > 6.
dim3 dim_block(block_width, block_width); // number of theads per block = 16*16 =256
Mat_Mul_Shared<<<dim_grid, dim_block>>> (d_A, d_B, d_C, n); // lauch kenel
cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost);
for(int i=0; i<n; i++)
for(int j=0; j<n; j++){
cout<<i<<" "<<j<<" "<<C[i*n+j]<<endl;
}
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);
free(A); free(B); free(C);
} | .file "tmpxft_001590aa_00000000-6_mat_mul_tile.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14Mat_Mul_SharedPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i
.globl _Z14Mat_Mul_SharedPfS_S_i
.type _Z14Mat_Mul_SharedPfS_S_i, @function
_Z14Mat_Mul_SharedPfS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14Mat_Mul_SharedPfS_S_i, .-_Z14Mat_Mul_SharedPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 20(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 20(%rsp), %ebp
movl %ebp, %ebx
imull %ebp, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebp, %ebp
jle .L12
movslq %ebp, %rsi
leaq 0(,%rsi,4), %rdi
negq %rsi
salq $2, %rsi
movq %rdi, %rdx
movl $0, %ecx
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L13:
leaq (%rdx,%rsi), %rax
.L14:
movq (%rsp), %r10
movss %xmm1, (%r10,%rax)
movq 8(%rsp), %r11
movss %xmm0, (%r11,%rax)
movl $0x00000000, (%r14,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L14
addl $1, %ecx
addq %rdi, %rdx
cmpl %ecx, %ebp
jne .L13
.L12:
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 20(%rsp), %edx
leal 15(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 48(%rsp)
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L15:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %r13d
leaq .LC3(%rip), %r15
cmpl $0, 20(%rsp)
jg .L16
.L17:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl 20(%rsp), %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i
jmp .L15
.L35:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L34
call _ZSt16__throw_bad_castv@PLT
.L34:
call __stack_chk_fail@PLT
.L36:
movzbl 67(%r12), %esi
.L21:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
cmpl %ebp, 20(%rsp)
jle .L23
.L22:
movl %r13d, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %eax
imull 20(%rsp), %eax
addl %ebp, %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rax,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L35
cmpb $0, 56(%r12)
jne .L36
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L21
.L23:
addl $1, %r13d
cmpl %r13d, 20(%rsp)
jle .L17
.L16:
movl $0, %ebp
cmpl $0, 20(%rsp)
jg .L22
jmp .L23
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z14Mat_Mul_SharedPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14Mat_Mul_SharedPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#define tile_width 16
using namespace std;
__global__ void Mat_Mul_Shared(float *d_A, float *d_B, float *d_C, int width) {
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float M[tile_width][tile_width];
__shared__ float N[tile_width][tile_width];
int n_tile = width / tile_width; //number of tiles
float value = 0;
for(int m=0; m < n_tile; m++ ){ // m loop of tiles
// copy from globalb memory to shared memory
M[threadIdx.y][threadIdx.x] = d_A[i*width + m*tile_width + threadIdx.x];
N[threadIdx.y][threadIdx.x] = d_B[(m*tile_width + threadIdx.y)*width + j];
__syncthreads(); // wait all threads finish copying
for(int k=0; k < tile_width; k++){ // k loop within a tile, in the m loop of tiles: together loop over width to perfomr the dot product of a row of d_A and a coloumn of d_B
value += M[threadIdx.y][k] * N[k][threadIdx.x]; // scalar value is in the register of a thread
}
__syncthreads(); // wait ll threads finish partial dot product
}
d_C[i*width + j] = value; // assign value in register of every thread to corresponding elements of d_C in global memory
}
int main(){
int n;
cin >> n;
int size = n*n*sizeof(float);
//float *A, *B, *C;
float *A = (float *) malloc( size ); // allocate CPU memory
float *B = (float *) malloc( size );
float *C = (float *) malloc( size );
for(int i=0; i<n; i++)
for(int j=0; j<n; j++){
int idx = i*n + j;
A[idx] = 1.;
B[idx] = 2.;
C[idx] = 0.;
}
float *d_A, *d_B, *d_C;
cudaMalloc(&d_A, size); // allocate GPU memory
cudaMalloc(&d_B, size);
cudaMalloc(&d_C, size);
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
int block_width = tile_width;
int grid_width = ceil(n/block_width);
// dim3 is a CUDA built-in struct
dim3 dim_grid(grid_width, grid_width); // num of blocks = (int(n/16) + 1)^2, efficient if > 6.
dim3 dim_block(block_width, block_width); // number of theads per block = 16*16 =256
Mat_Mul_Shared<<<dim_grid, dim_block>>> (d_A, d_B, d_C, n); // lauch kenel
cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost);
for(int i=0; i<n; i++)
for(int j=0; j<n; j++){
cout<<i<<" "<<j<<" "<<C[i*n+j]<<endl;
}
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);
free(A); free(B); free(C);
} | #include <hip/hip_runtime.h>
#include<iostream>
#define tile_width 16
using namespace std;
__global__ void Mat_Mul_Shared(float *d_A, float *d_B, float *d_C, int width) {
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float M[tile_width][tile_width];
__shared__ float N[tile_width][tile_width];
int n_tile = width / tile_width; //number of tiles
float value = 0;
for(int m=0; m < n_tile; m++ ){ // m loop of tiles
// copy from globalb memory to shared memory
M[threadIdx.y][threadIdx.x] = d_A[i*width + m*tile_width + threadIdx.x];
N[threadIdx.y][threadIdx.x] = d_B[(m*tile_width + threadIdx.y)*width + j];
__syncthreads(); // wait all threads finish copying
for(int k=0; k < tile_width; k++){ // k loop within a tile, in the m loop of tiles: together loop over width to perfomr the dot product of a row of d_A and a coloumn of d_B
value += M[threadIdx.y][k] * N[k][threadIdx.x]; // scalar value is in the register of a thread
}
__syncthreads(); // wait ll threads finish partial dot product
}
d_C[i*width + j] = value; // assign value in register of every thread to corresponding elements of d_C in global memory
}
int main(){
int n;
cin >> n;
int size = n*n*sizeof(float);
//float *A, *B, *C;
float *A = (float *) malloc( size ); // allocate CPU memory
float *B = (float *) malloc( size );
float *C = (float *) malloc( size );
for(int i=0; i<n; i++)
for(int j=0; j<n; j++){
int idx = i*n + j;
A[idx] = 1.;
B[idx] = 2.;
C[idx] = 0.;
}
float *d_A, *d_B, *d_C;
hipMalloc(&d_A, size); // allocate GPU memory
hipMalloc(&d_B, size);
hipMalloc(&d_C, size);
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
int block_width = tile_width;
int grid_width = ceil(n/block_width);
// dim3 is a CUDA built-in struct
dim3 dim_grid(grid_width, grid_width); // num of blocks = (int(n/16) + 1)^2, efficient if > 6.
dim3 dim_block(block_width, block_width); // number of theads per block = 16*16 =256
Mat_Mul_Shared<<<dim_grid, dim_block>>> (d_A, d_B, d_C, n); // lauch kenel
hipMemcpy(C, d_C, size, hipMemcpyDeviceToHost);
for(int i=0; i<n; i++)
for(int j=0; j<n; j++){
cout<<i<<" "<<j<<" "<<C[i*n+j]<<endl;
}
hipFree(d_A); hipFree(d_B); hipFree(d_C);
free(A); free(B); free(C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#define tile_width 16
using namespace std;
__global__ void Mat_Mul_Shared(float *d_A, float *d_B, float *d_C, int width) {
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float M[tile_width][tile_width];
__shared__ float N[tile_width][tile_width];
int n_tile = width / tile_width; //number of tiles
float value = 0;
for(int m=0; m < n_tile; m++ ){ // m loop of tiles
// copy from globalb memory to shared memory
M[threadIdx.y][threadIdx.x] = d_A[i*width + m*tile_width + threadIdx.x];
N[threadIdx.y][threadIdx.x] = d_B[(m*tile_width + threadIdx.y)*width + j];
__syncthreads(); // wait all threads finish copying
for(int k=0; k < tile_width; k++){ // k loop within a tile, in the m loop of tiles: together loop over width to perfomr the dot product of a row of d_A and a coloumn of d_B
value += M[threadIdx.y][k] * N[k][threadIdx.x]; // scalar value is in the register of a thread
}
__syncthreads(); // wait ll threads finish partial dot product
}
d_C[i*width + j] = value; // assign value in register of every thread to corresponding elements of d_C in global memory
}
int main(){
int n;
cin >> n;
int size = n*n*sizeof(float);
//float *A, *B, *C;
float *A = (float *) malloc( size ); // allocate CPU memory
float *B = (float *) malloc( size );
float *C = (float *) malloc( size );
for(int i=0; i<n; i++)
for(int j=0; j<n; j++){
int idx = i*n + j;
A[idx] = 1.;
B[idx] = 2.;
C[idx] = 0.;
}
float *d_A, *d_B, *d_C;
hipMalloc(&d_A, size); // allocate GPU memory
hipMalloc(&d_B, size);
hipMalloc(&d_C, size);
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
int block_width = tile_width;
int grid_width = ceil(n/block_width);
// dim3 is a CUDA built-in struct
dim3 dim_grid(grid_width, grid_width); // num of blocks = (int(n/16) + 1)^2, efficient if > 6.
dim3 dim_block(block_width, block_width); // number of theads per block = 16*16 =256
Mat_Mul_Shared<<<dim_grid, dim_block>>> (d_A, d_B, d_C, n); // lauch kenel
hipMemcpy(C, d_C, size, hipMemcpyDeviceToHost);
for(int i=0; i<n; i++)
for(int j=0; j<n; j++){
cout<<i<<" "<<j<<" "<<C[i*n+j]<<endl;
}
hipFree(d_A); hipFree(d_B); hipFree(d_C);
free(A); free(B); free(C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14Mat_Mul_SharedPfS_S_i
.globl _Z14Mat_Mul_SharedPfS_S_i
.p2align 8
.type _Z14Mat_Mul_SharedPfS_S_i,@function
_Z14Mat_Mul_SharedPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v6, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s4, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s3, v[6:7]
v_mov_b32_e32 v2, 0
s_cmp_lt_i32 s2, 16
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v6
v_lshlrev_b32_e32 v7, 6, v3
s_ashr_i32 s3, s2, 31
s_mov_b32 s8, 0
s_lshr_b32 s3, s3, 28
v_add_nc_u32_e32 v8, 0x400, v2
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, v7, v2
v_mad_u64_u32 v[4:5], null, v0, s2, v[6:7]
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v10, v8, v7
s_add_i32 s3, s2, s3
s_ashr_i32 s3, s3, 4
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, s9, v3
v_add_nc_u32_e32 v5, s9, v4
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v13, s2, v[1:2]
v_mov_b32_e32 v12, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 2, v[5:6]
v_mov_b32_e32 v5, v8
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v13, v[13:14], off
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(1)
ds_store_b32 v9, v13
s_waitcnt vmcnt(0)
ds_store_b32 v10, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v11, s9, v7
s_add_i32 s9, s9, 4
ds_load_b32 v12, v5
ds_load_b32 v11, v11
v_add_nc_u32_e32 v5, 64, v5
s_cmp_eq_u32 s9, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v11, v12
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14Mat_Mul_SharedPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14Mat_Mul_SharedPfS_S_i, .Lfunc_end0-_Z14Mat_Mul_SharedPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14Mat_Mul_SharedPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14Mat_Mul_SharedPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#define tile_width 16
using namespace std;
__global__ void Mat_Mul_Shared(float *d_A, float *d_B, float *d_C, int width) {
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float M[tile_width][tile_width];
__shared__ float N[tile_width][tile_width];
int n_tile = width / tile_width; //number of tiles
float value = 0;
for(int m=0; m < n_tile; m++ ){ // m loop of tiles
// copy from globalb memory to shared memory
M[threadIdx.y][threadIdx.x] = d_A[i*width + m*tile_width + threadIdx.x];
N[threadIdx.y][threadIdx.x] = d_B[(m*tile_width + threadIdx.y)*width + j];
__syncthreads(); // wait all threads finish copying
for(int k=0; k < tile_width; k++){ // k loop within a tile, in the m loop of tiles: together loop over width to perfomr the dot product of a row of d_A and a coloumn of d_B
value += M[threadIdx.y][k] * N[k][threadIdx.x]; // scalar value is in the register of a thread
}
__syncthreads(); // wait ll threads finish partial dot product
}
d_C[i*width + j] = value; // assign value in register of every thread to corresponding elements of d_C in global memory
}
int main(){
int n;
cin >> n;
int size = n*n*sizeof(float);
//float *A, *B, *C;
float *A = (float *) malloc( size ); // allocate CPU memory
float *B = (float *) malloc( size );
float *C = (float *) malloc( size );
for(int i=0; i<n; i++)
for(int j=0; j<n; j++){
int idx = i*n + j;
A[idx] = 1.;
B[idx] = 2.;
C[idx] = 0.;
}
float *d_A, *d_B, *d_C;
hipMalloc(&d_A, size); // allocate GPU memory
hipMalloc(&d_B, size);
hipMalloc(&d_C, size);
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
int block_width = tile_width;
int grid_width = ceil(n/block_width);
// dim3 is a CUDA built-in struct
dim3 dim_grid(grid_width, grid_width); // num of blocks = (int(n/16) + 1)^2, efficient if > 6.
dim3 dim_block(block_width, block_width); // number of theads per block = 16*16 =256
Mat_Mul_Shared<<<dim_grid, dim_block>>> (d_A, d_B, d_C, n); // lauch kenel
hipMemcpy(C, d_C, size, hipMemcpyDeviceToHost);
for(int i=0; i<n; i++)
for(int j=0; j<n; j++){
cout<<i<<" "<<j<<" "<<C[i*n+j]<<endl;
}
hipFree(d_A); hipFree(d_B); hipFree(d_C);
free(A); free(B); free(C);
} | .text
.file "mat_mul_tile.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__Mat_Mul_SharedPfS_S_i # -- Begin function _Z29__device_stub__Mat_Mul_SharedPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__Mat_Mul_SharedPfS_S_i,@function
_Z29__device_stub__Mat_Mul_SharedPfS_S_i: # @_Z29__device_stub__Mat_Mul_SharedPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14Mat_Mul_SharedPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__Mat_Mul_SharedPfS_S_i, .Lfunc_end0-_Z29__device_stub__Mat_Mul_SharedPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 4(%rsp), %ebx
movl %ebx, %eax
imull %ebx, %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %r14, 56(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, %r15
testl %ebx, %ebx
jle .LBB1_5
# %bb.1: # %.preheader53.lr.ph
leaq (,%rbx,4), %rax
movq %rax, 64(%rsp) # 8-byte Spill
xorl %ebp, %ebp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.preheader53
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
movl %ebx, %eax
imull %r12d, %eax
leaq (%r15,%rax,4), %rdi
xorl %esi, %esi
movq 64(%rsp), %rdx # 8-byte Reload
callq memset@PLT
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%r13,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq %rax, %rbx
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r12
addl %ebx, %ebp
cmpq %rbx, %r12
jne .LBB1_2
.LBB1_5: # %._crit_edge56
leaq 40(%rsp), %rdi
movq 56(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
leal 15(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
movq %rcx, %rdi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movl 4(%rsp), %esi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %esi, 52(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z14Mat_Mul_SharedPfS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 24(%rsp), %rsi
movq %r15, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 4(%rsp)
jle .LBB1_14
# %bb.8: # %.preheader.preheader
xorl %ebx, %ebx
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_13: # %._crit_edge59
# in Loop: Header=BB1_9 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB1_14
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
cmpl $0, 4(%rsp)
jle .LBB1_13
# %bb.10: # %.lr.ph58.preheader
# in Loop: Header=BB1_9 Depth=1
movslq %ebx, %r12
xorl %r13d, %r13d
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_11 Depth=2
movq %rbp, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_11 Depth=2
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
cmpl 4(%rsp), %r13d
jge .LBB1_13
.LBB1_11: # %.lr.ph58
# Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %rbp
movl $.L.str, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbp, %rdi
movl %r13d, %esi
callq _ZNSolsEi
movq %rax, %rbp
movl $.L.str, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 4(%rsp), %rax
imulq %r12, %rax
addq %r13, %rax
movss (%r15,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbp
testq %rbp, %rbp
je .LBB1_12
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_11 Depth=2
cmpb $0, 56(%rbp)
je .LBB1_17
# %bb.16: # in Loop: Header=BB1_11 Depth=2
movzbl 67(%rbp), %ecx
jmp .LBB1_18
.LBB1_14: # %._crit_edge61
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14Mat_Mul_SharedPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14Mat_Mul_SharedPfS_S_i,@object # @_Z14Mat_Mul_SharedPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14Mat_Mul_SharedPfS_S_i
.p2align 3, 0x0
_Z14Mat_Mul_SharedPfS_S_i:
.quad _Z29__device_stub__Mat_Mul_SharedPfS_S_i
.size _Z14Mat_Mul_SharedPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14Mat_Mul_SharedPfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__Mat_Mul_SharedPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14Mat_Mul_SharedPfS_S_i
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14Mat_Mul_SharedPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R16, c[0x0][0x178] ; /* 0x00005e0000107a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R16, 0x10, PT ; /* 0x000000101000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e680000002600 */
/*0080*/ S2R R19, SR_TID.Y ; /* 0x0000000000137919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R4, R3, c[0x0][0x0], R0 ; /* 0x0000000003047a24 */
/* 0x001fe200078e0200 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R17, R17, c[0x0][0x4], R19 ; /* 0x0000010011117a24 */
/* 0x002fc800078e0213 */
/*00c0*/ IMAD R2, R17, c[0x0][0x178], R4 ; /* 0x00005e0011027a24 */
/* 0x000fca00078e0204 */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*00e0*/ @!P0 BRA 0x4a0 ; /* 0x000003b000008947 */
/* 0x000fea0003800000 */
/*00f0*/ SHF.R.S32.HI R5, RZ, 0x1f, R16 ; /* 0x0000001fff057819 */
/* 0x000fe20000011410 */
/*0100*/ IMAD R21, R19.reuse, c[0x0][0x178], R4 ; /* 0x00005e0013157a24 */
/* 0x040fe200078e0204 */
/*0110*/ SHF.L.U32 R19, R19, 0x6, RZ ; /* 0x0000000613137819 */
/* 0x000fe200000006ff */
/*0120*/ IMAD R17, R17, c[0x0][0x178], R0 ; /* 0x00005e0011117a24 */
/* 0x000fe200078e0200 */
/*0130*/ LEA.HI R5, R5, c[0x0][0x178], RZ, 0x4 ; /* 0x00005e0005057a11 */
/* 0x000fe200078f20ff */
/*0140*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0150*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0160*/ LEA R20, R0, R19, 0x2 ; /* 0x0000001300147211 */
/* 0x000fe400078e10ff */
/*0170*/ SHF.R.S32.HI R18, RZ, 0x4, R5 ; /* 0x00000004ff127819 */
/* 0x000fc40000011405 */
/*0180*/ MOV R10, 0x4 ; /* 0x00000004000a7802 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE.U32 R4, R17, R10, c[0x0][0x160] ; /* 0x0000580011047625 */
/* 0x000fc800078e000a */
/*01a0*/ IMAD.WIDE.U32 R10, R21, R10, c[0x0][0x168] ; /* 0x00005a00150a7625 */
/* 0x000fe200078e000a */
/*01b0*/ LDG.E R23, [R4.64] ; /* 0x0000000604177981 */
/* 0x000eaa000c1e1900 */
/*01c0*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000ee2000c1e1900 */
/*01d0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*01e0*/ IADD3 R17, R17, 0x10, RZ ; /* 0x0000001011117810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ LEA R21, R16, R21, 0x4 ; /* 0x0000001510157211 */
/* 0x000fc600078e20ff */
/*0200*/ ISETP.LE.AND P0, PT, R18, UR4, PT ; /* 0x0000000412007c0c */
/* 0x000fe2000bf03270 */
/*0210*/ STS [R20], R23 ; /* 0x0000001714007388 */
/* 0x004fe80000000800 */
/*0220*/ STS [R20+0x400], R11 ; /* 0x0004000b14007388 */
/* 0x008fe80000000800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ LDS R8, [R0.X4+0x400] ; /* 0x0004000000087984 */
/* 0x000fe80000004800 */
/*0250*/ LDS.128 R12, [R19] ; /* 0x00000000130c7984 */
/* 0x000e280000000c00 */
/*0260*/ LDS R25, [R0.X4+0x440] ; /* 0x0004400000197984 */
/* 0x000e680000004800 */
/*0270*/ LDS R28, [R0.X4+0x480] ; /* 0x00048000001c7984 */
/* 0x000ea80000004800 */
/*0280*/ LDS R26, [R0.X4+0x4c0] ; /* 0x0004c000001a7984 */
/* 0x000ee80000004800 */
/*0290*/ LDS R27, [R0.X4+0x500] ; /* 0x00050000001b7984 */
/* 0x000fe80000004800 */
/*02a0*/ LDS.128 R4, [R19+0x10] ; /* 0x0000100013047984 */
/* 0x000f280000000c00 */
/*02b0*/ LDS R24, [R0.X4+0x540] ; /* 0x0005400000187984 */
/* 0x000f680000004800 */
/*02c0*/ LDS R23, [R0.X4+0x580] ; /* 0x0005800000177984 */
/* 0x000f680000004800 */
/*02d0*/ LDS R22, [R0.X4+0x5c0] ; /* 0x0005c00000167984 */
/* 0x000f620000004800 */
/*02e0*/ FFMA R8, R8, R12, R9 ; /* 0x0000000c08087223 */
/* 0x001fc80000000009 */
/*02f0*/ FFMA R13, R25, R13, R8 ; /* 0x0000000d190d7223 */
/* 0x002fe40000000008 */
/*0300*/ LDS R25, [R0.X4+0x600] ; /* 0x0006000000197984 */
/* 0x000fe40000004800 */
/*0310*/ FFMA R13, R28, R14, R13 ; /* 0x0000000e1c0d7223 */
/* 0x004fe4000000000d */
/*0320*/ LDS.128 R8, [R19+0x20] ; /* 0x0000200013087984 */
/* 0x000e240000000c00 */
/*0330*/ FFMA R13, R26, R15, R13 ; /* 0x0000000f1a0d7223 */
/* 0x008fe4000000000d */
/*0340*/ LDS R26, [R0.X4+0x640] ; /* 0x00064000001a7984 */
/* 0x000e640000004800 */
/*0350*/ FFMA R4, R27, R4, R13 ; /* 0x000000041b047223 */
/* 0x010fc4000000000d */
/*0360*/ LDS R27, [R0.X4+0x680] ; /* 0x00068000001b7984 */
/* 0x000ea40000004800 */
/*0370*/ FFMA R5, R24, R5, R4 ; /* 0x0000000518057223 */
/* 0x020fe40000000004 */
/*0380*/ LDS R4, [R0.X4+0x6c0] ; /* 0x0006c00000047984 */
/* 0x000ee40000004800 */
/*0390*/ FFMA R6, R23, R6, R5 ; /* 0x0000000617067223 */
/* 0x000fe40000000005 */
/*03a0*/ LDS R5, [R0.X4+0x700] ; /* 0x0007000000057984 */
/* 0x000fe40000004800 */
/*03b0*/ FFMA R23, R22, R7, R6 ; /* 0x0000000716177223 */
/* 0x000fc40000000006 */
/*03c0*/ LDS.128 R12, [R19+0x30] ; /* 0x00003000130c7984 */
/* 0x000f280000000c00 */
/*03d0*/ LDS R22, [R0.X4+0x740] ; /* 0x0007400000167984 */
/* 0x000f680000004800 */
/*03e0*/ LDS R7, [R0.X4+0x780] ; /* 0x0007800000077984 */
/* 0x000f680000004800 */
/*03f0*/ LDS R6, [R0.X4+0x7c0] ; /* 0x0007c00000067984 */
/* 0x000f620000004800 */
/*0400*/ FFMA R8, R25, R8, R23 ; /* 0x0000000819087223 */
/* 0x001fc80000000017 */
/*0410*/ FFMA R8, R26, R9, R8 ; /* 0x000000091a087223 */
/* 0x002fc80000000008 */
/*0420*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*0430*/ FFMA R4, R4, R11, R8 ; /* 0x0000000b04047223 */
/* 0x008fc80000000008 */
/*0440*/ FFMA R4, R5, R12, R4 ; /* 0x0000000c05047223 */
/* 0x010fc80000000004 */
/*0450*/ FFMA R4, R22, R13, R4 ; /* 0x0000000d16047223 */
/* 0x020fc80000000004 */
/*0460*/ FFMA R4, R7, R14, R4 ; /* 0x0000000e07047223 */
/* 0x000fc80000000004 */
/*0470*/ FFMA R9, R6, R15, R4 ; /* 0x0000000f06097223 */
/* 0x000fe20000000004 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @!P0 BRA 0x180 ; /* 0xfffffce000008947 */
/* 0x000fea000383ffff */
/*04a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14Mat_Mul_SharedPfS_S_i
.globl _Z14Mat_Mul_SharedPfS_S_i
.p2align 8
.type _Z14Mat_Mul_SharedPfS_S_i,@function
_Z14Mat_Mul_SharedPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v6, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s4, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s3, v[6:7]
v_mov_b32_e32 v2, 0
s_cmp_lt_i32 s2, 16
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v6
v_lshlrev_b32_e32 v7, 6, v3
s_ashr_i32 s3, s2, 31
s_mov_b32 s8, 0
s_lshr_b32 s3, s3, 28
v_add_nc_u32_e32 v8, 0x400, v2
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, v7, v2
v_mad_u64_u32 v[4:5], null, v0, s2, v[6:7]
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v10, v8, v7
s_add_i32 s3, s2, s3
s_ashr_i32 s3, s3, 4
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_lshl_b32 s9, s8, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, s9, v3
v_add_nc_u32_e32 v5, s9, v4
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v13, s2, v[1:2]
v_mov_b32_e32 v12, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 2, v[5:6]
v_mov_b32_e32 v5, v8
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v13, v[13:14], off
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(1)
ds_store_b32 v9, v13
s_waitcnt vmcnt(0)
ds_store_b32 v10, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v11, s9, v7
s_add_i32 s9, s9, 4
ds_load_b32 v12, v5
ds_load_b32 v11, v11
v_add_nc_u32_e32 v5, 64, v5
s_cmp_eq_u32 s9, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v11, v12
s_cbranch_scc0 .LBB0_3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14Mat_Mul_SharedPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14Mat_Mul_SharedPfS_S_i, .Lfunc_end0-_Z14Mat_Mul_SharedPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14Mat_Mul_SharedPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14Mat_Mul_SharedPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001590aa_00000000-6_mat_mul_tile.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14Mat_Mul_SharedPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i
.globl _Z14Mat_Mul_SharedPfS_S_i
.type _Z14Mat_Mul_SharedPfS_S_i, @function
_Z14Mat_Mul_SharedPfS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14Mat_Mul_SharedPfS_S_i, .-_Z14Mat_Mul_SharedPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 20(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 20(%rsp), %ebp
movl %ebp, %ebx
imull %ebp, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebp, %ebp
jle .L12
movslq %ebp, %rsi
leaq 0(,%rsi,4), %rdi
negq %rsi
salq $2, %rsi
movq %rdi, %rdx
movl $0, %ecx
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L13:
leaq (%rdx,%rsi), %rax
.L14:
movq (%rsp), %r10
movss %xmm1, (%r10,%rax)
movq 8(%rsp), %r11
movss %xmm0, (%r11,%rax)
movl $0x00000000, (%r14,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L14
addl $1, %ecx
addq %rdi, %rdx
cmpl %ecx, %ebp
jne .L13
.L12:
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 20(%rsp), %edx
leal 15(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 48(%rsp)
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L15:
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %r13d
leaq .LC3(%rip), %r15
cmpl $0, 20(%rsp)
jg .L16
.L17:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl 20(%rsp), %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z39__device_stub__Z14Mat_Mul_SharedPfS_S_iPfS_S_i
jmp .L15
.L35:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L34
call _ZSt16__throw_bad_castv@PLT
.L34:
call __stack_chk_fail@PLT
.L36:
movzbl 67(%r12), %esi
.L21:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
cmpl %ebp, 20(%rsp)
jle .L23
.L22:
movl %r13d, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %eax
imull 20(%rsp), %eax
addl %ebp, %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rax,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L35
cmpb $0, 56(%r12)
jne .L36
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L21
.L23:
addl $1, %r13d
cmpl %r13d, 20(%rsp)
jle .L17
.L16:
movl $0, %ebp
cmpl $0, 20(%rsp)
jg .L22
jmp .L23
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z14Mat_Mul_SharedPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14Mat_Mul_SharedPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_mul_tile.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__Mat_Mul_SharedPfS_S_i # -- Begin function _Z29__device_stub__Mat_Mul_SharedPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__Mat_Mul_SharedPfS_S_i,@function
_Z29__device_stub__Mat_Mul_SharedPfS_S_i: # @_Z29__device_stub__Mat_Mul_SharedPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14Mat_Mul_SharedPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__Mat_Mul_SharedPfS_S_i, .Lfunc_end0-_Z29__device_stub__Mat_Mul_SharedPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 4(%rsp), %ebx
movl %ebx, %eax
imull %ebx, %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %r14, 56(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, %r15
testl %ebx, %ebx
jle .LBB1_5
# %bb.1: # %.preheader53.lr.ph
leaq (,%rbx,4), %rax
movq %rax, 64(%rsp) # 8-byte Spill
xorl %ebp, %ebp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.preheader53
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
movl %ebx, %eax
imull %r12d, %eax
leaq (%r15,%rax,4), %rdi
xorl %esi, %esi
movq 64(%rsp), %rdx # 8-byte Reload
callq memset@PLT
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%r13,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq %rax, %rbx
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r12
addl %ebx, %ebp
cmpq %rbx, %r12
jne .LBB1_2
.LBB1_5: # %._crit_edge56
leaq 40(%rsp), %rdi
movq 56(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
leal 15(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
movq %rcx, %rdi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movl 4(%rsp), %esi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %esi, 52(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z14Mat_Mul_SharedPfS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
movq 24(%rsp), %rsi
movq %r15, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 4(%rsp)
jle .LBB1_14
# %bb.8: # %.preheader.preheader
xorl %ebx, %ebx
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_13: # %._crit_edge59
# in Loop: Header=BB1_9 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB1_14
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
cmpl $0, 4(%rsp)
jle .LBB1_13
# %bb.10: # %.lr.ph58.preheader
# in Loop: Header=BB1_9 Depth=1
movslq %ebx, %r12
xorl %r13d, %r13d
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_11 Depth=2
movq %rbp, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_11 Depth=2
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
cmpl 4(%rsp), %r13d
jge .LBB1_13
.LBB1_11: # %.lr.ph58
# Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %rbp
movl $.L.str, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbp, %rdi
movl %r13d, %esi
callq _ZNSolsEi
movq %rax, %rbp
movl $.L.str, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 4(%rsp), %rax
imulq %r12, %rax
addq %r13, %rax
movss (%r15,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbp
testq %rbp, %rbp
je .LBB1_12
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_11 Depth=2
cmpb $0, 56(%rbp)
je .LBB1_17
# %bb.16: # in Loop: Header=BB1_11 Depth=2
movzbl 67(%rbp), %ecx
jmp .LBB1_18
.LBB1_14: # %._crit_edge61
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14Mat_Mul_SharedPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14Mat_Mul_SharedPfS_S_i,@object # @_Z14Mat_Mul_SharedPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14Mat_Mul_SharedPfS_S_i
.p2align 3, 0x0
_Z14Mat_Mul_SharedPfS_S_i:
.quad _Z29__device_stub__Mat_Mul_SharedPfS_S_i
.size _Z14Mat_Mul_SharedPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14Mat_Mul_SharedPfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__Mat_Mul_SharedPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14Mat_Mul_SharedPfS_S_i
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
const char TRUE = 1;
const char FALSE = 0;
int bruteIncrement(char* brute, int alphabetLen, int wordLen, int incrementBy) {
int i = 0;
while(incrementBy > 0 && i < wordLen) {
int add = incrementBy + brute[i];
brute[i] = (char)(add % alphabetLen);
incrementBy = add / alphabetLen;
i++;
}
return incrementBy == 0;
}
__device__ void cudaStrCmp(char *a, char *b, int len, int* res) {
int workerId = threadIdx.x;
for (int i = 0; i < len; i++) {
if (a[i] != b[i]) {
*res = 0;
return;
}
}
}
__device__ void k_bruteIncrement(char* brute, int alphabetLen, int wordLen, int incrementBy, int *incRes) {
int i = 0;
int workerId = threadIdx.x;
while(incrementBy > 0 && i < wordLen) {
int add = incrementBy + brute[i];
brute[i] = (char)(add % alphabetLen);
incrementBy = add / alphabetLen;
i++;
}
*incRes = incrementBy == 0;
}
__device__ void bruteToString(char *brute, int wordLen, char *alphabet, char *out){
for(int i=0;i<wordLen;i++){
out[i]=alphabet[brute[i]];
}
out[wordLen]='\0';
}
int any(int *list, int listSize){
for(int i=0;i<listSize;i++){
if(list[i])return TRUE;
}
return FALSE;
}
__global__ void searchPart(char *targetString, char *alphabet, char *brutePart, int workSize, int wordLen, int alphabetLen, int* results){
int workerId = threadIdx.x;
results[workerId] = 0;
int incRes = FALSE;
// Receive start of latest section (WORKER * WORKSIZE), create local copy
char* t_brutePart = (char *) malloc((wordLen)* sizeof(char));
for (int i = 0; i < wordLen; i++) t_brutePart[i] = brutePart[i];
// Increment to start of this thread's chunk (WORKSIZE)
k_bruteIncrement(t_brutePart, alphabetLen, wordLen, workSize*workerId, &incRes);
if(!incRes){
return;
}
int count = 0;
char* out = (char *) malloc((wordLen + 1)* sizeof(char));
// Increment by one and compare strs after every iteration
while(1) {
if(count>=workSize) {
break;
}
bruteToString(t_brutePart, wordLen, alphabet, out);
int cmpRes = 1;
cudaStrCmp(out, targetString, wordLen, &cmpRes);
if(cmpRes == 1) {
results[workerId] = 1;
break;
}
count +=1;
incRes = 0;
k_bruteIncrement(t_brutePart, alphabetLen, wordLen, 1, &incRes);
if(!incRes) {
break;
}
}
free(out);
free(t_brutePart);
}
int search(char *targetString, char *alphabet, int numWorkers, int workSize){
int wordLen = strlen(targetString);
int alphabetLen = strlen(alphabet);
int size = wordLen*sizeof(char);
int alphabetSize = alphabetLen*sizeof(char);
char *k_alphabet;
int *k_alphabetLen;
int *k_wordLen;
char *k_targetString;
cudaMallocManaged(&k_alphabet, alphabetSize);
cudaMallocManaged(&k_alphabetLen, sizeof(int));
cudaMallocManaged(&k_wordLen, sizeof(int));
cudaMallocManaged(&k_targetString, size);
cudaMemcpy(k_alphabet, alphabet, alphabetSize, cudaMemcpyDefault );
cudaMemcpy(k_targetString, targetString, size, cudaMemcpyDefault );
*k_alphabetLen = strlen(alphabet);
*k_wordLen = strlen(targetString);
char brute [wordLen];
for(int i=0;i<wordLen;i++)brute[i]=0;
char* k_brutePart;
cudaMalloc(&k_brutePart, size);
int* k_results;
cudaMallocManaged(&k_results, numWorkers* sizeof(int));
int* results = (int*)malloc(sizeof(int) * numWorkers);
// Every iteration, increment brute (WORKERS * WORKSIZE) times
while(1){
cudaMemcpy(k_brutePart, brute, size, cudaMemcpyDefault );
for(int i=0;i<numWorkers;i++) k_results[i] = 0;
// Divide the section into chunks to be worked on in parallel
searchPart<<<1, numWorkers>>>(k_targetString, k_alphabet, k_brutePart, workSize, *k_wordLen, *k_alphabetLen, k_results);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
if(any(k_results, numWorkers)) return 1;
// advance to the next major chunk of work
if(!bruteIncrement(brute, alphabetLen, wordLen, workSize*numWorkers)){
break;
}
}
cudaFree(k_alphabet);
cudaFree(k_alphabetLen);
cudaFree(k_wordLen);
cudaFree(k_targetString);
cudaFree(k_brutePart);
cudaFree(k_results);
return 0;
}
int main( int argc, char** argv) {
char *targetString = argv[1];
char *alphabet = argv[2];
int numWorkers = atoi(argv[3]);
int workSize = atoi(argv[4]);
printf("Looking for %s in [%s]...\n", targetString, alphabet);
if(search(targetString, alphabet, numWorkers, workSize)){
printf("Found\n");
} else {
printf("Notfound\n");
}
return 0;
} | .file "tmpxft_001ba0b7_00000000-6_Search.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14bruteIncrementPciii
.type _Z14bruteIncrementPciii, @function
_Z14bruteIncrementPciii:
.LFB2057:
.cfi_startproc
endbr64
movl %esi, %r8d
movl %edx, %r9d
testl %ecx, %ecx
jle .L4
testl %edx, %edx
jle .L4
movl $1, %esi
.L5:
movsbl -1(%rdi,%rsi), %eax
addl %ecx, %eax
cltd
idivl %r8d
movb %dl, -1(%rdi,%rsi)
movl %eax, %ecx
testl %eax, %eax
setg %dl
cmpl %esi, %r9d
setg %al
addq $1, %rsi
testb %al, %dl
jne .L5
.L4:
testl %ecx, %ecx
sete %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z14bruteIncrementPciii, .-_Z14bruteIncrementPciii
.globl _Z10cudaStrCmpPcS_iPi
.type _Z10cudaStrCmpPcS_iPi, @function
_Z10cudaStrCmpPcS_iPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10cudaStrCmpPcS_iPi, .-_Z10cudaStrCmpPcS_iPi
.globl _Z16k_bruteIncrementPciiiPi
.type _Z16k_bruteIncrementPciiiPi, @function
_Z16k_bruteIncrementPciiiPi:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z16k_bruteIncrementPciiiPi, .-_Z16k_bruteIncrementPciiiPi
.globl _Z13bruteToStringPciS_S_
.type _Z13bruteToStringPciS_S_, @function
_Z13bruteToStringPciS_S_:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z13bruteToStringPciS_S_, .-_Z13bruteToStringPciS_S_
.globl _Z3anyPii
.type _Z3anyPii, @function
_Z3anyPii:
.LFB2061:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
.L15:
movl (%rax), %edx
testl %edx, %edx
jne .L17
addq $4, %rax
cmpq %rcx, %rax
jne .L15
jmp .L13
.L16:
movl $0, %edx
jmp .L13
.L17:
movl $1, %edx
.L13:
movl %edx, %eax
ret
.cfi_endproc
.LFE2061:
.size _Z3anyPii, .-_Z3anyPii
.globl _Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi
.type _Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi, @function
_Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10searchPartPcS_S_iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi, .-_Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi
.globl _Z10searchPartPcS_S_iiiPi
.type _Z10searchPartPcS_S_iiiPi, @function
_Z10searchPartPcS_S_iiiPi:
.LFB2089:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z10searchPartPcS_S_iiiPi, .-_Z10searchPartPcS_S_iiiPi
.globl _Z6searchPcS_ii
.type _Z6searchPcS_ii, @function
_Z6searchPcS_ii:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, %r14
movl %edx, %r13d
movl %ecx, -148(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq %rdi, -136(%rbp)
call strlen@PLT
movq %rax, %rbx
movl %eax, -140(%rbp)
movq %r14, %rdi
call strlen@PLT
movl %eax, -144(%rbp)
movslq %eax, %r12
leaq -128(%rbp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq -120(%rbp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq -112(%rbp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movslq %ebx, %r15
leaq -104(%rbp), %rdi
movl $1, %edx
movq %r15, %rsi
call cudaMallocManaged@PLT
movl $4, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq -128(%rbp), %rdi
call cudaMemcpy@PLT
movl $4, %ecx
movq %r15, %rdx
movq -136(%rbp), %r12
movq %r12, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
movq %r14, %rdi
call strlen@PLT
movq -120(%rbp), %rdx
movl %eax, (%rdx)
movq %r12, %rdi
call strlen@PLT
movq -112(%rbp), %rdx
movl %eax, (%rdx)
leaq 15(%r15), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L28:
cmpq %rdx, %rsp
je .L29
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L28
.L29:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L30
orq $0, -8(%rsp,%rax)
.L30:
movq %rsp, %r14
testl %ebx, %ebx
jle .L31
movq %r14, %rax
leal -1(%rbx), %edx
leaq 1(%r14,%rdx), %rdx
.L32:
movb $0, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L32
.L31:
leaq -96(%rbp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movslq %r13d, %rbx
salq $2, %rbx
leaq -88(%rbp), %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
movl -148(%rbp), %eax
imull %r13d, %eax
movl %eax, -136(%rbp)
jmp .L37
.L35:
call cudaDeviceSynchronize@PLT
movl %r13d, %esi
movq -88(%rbp), %rdi
call _Z3anyPii
testl %eax, %eax
jne .L39
movl -136(%rbp), %ecx
movl -140(%rbp), %edx
movl -144(%rbp), %esi
movq %r14, %rdi
call _Z14bruteIncrementPciii
movl %eax, %r12d
testl %eax, %eax
je .L44
.L37:
movl $4, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L33
movl $0, %eax
.L34:
movq -88(%rbp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq %rax, %rbx
jne .L34
.L33:
movl %r13d, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L35
movq -120(%rbp), %rax
movl (%rax), %r9d
movq -112(%rbp), %rax
movl (%rax), %r8d
subq $8, %rsp
pushq -88(%rbp)
movl -148(%rbp), %ecx
movq -96(%rbp), %rdx
movq -128(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi
addq $16, %rsp
jmp .L35
.L44:
movq -128(%rbp), %rdi
call cudaFree@PLT
movq -120(%rbp), %rdi
call cudaFree@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
jmp .L27
.L39:
movl $1, %r12d
.L27:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L45
movl %r12d, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L45:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z6searchPcS_ii, .-_Z6searchPcS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Looking for %s in [%s]...\n"
.LC1:
.string "Found\n"
.LC2:
.string "Notfound\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbx
movq 8(%rsi), %r12
movq 16(%rsi), %r13
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq %r13, %rcx
movq %r12, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movl %ebp, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z6searchPcS_ii
testl %eax, %eax
je .L47
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L48:
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10searchPartPcS_S_iiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10searchPartPcS_S_iiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
const char TRUE = 1;
const char FALSE = 0;
int bruteIncrement(char* brute, int alphabetLen, int wordLen, int incrementBy) {
int i = 0;
while(incrementBy > 0 && i < wordLen) {
int add = incrementBy + brute[i];
brute[i] = (char)(add % alphabetLen);
incrementBy = add / alphabetLen;
i++;
}
return incrementBy == 0;
}
__device__ void cudaStrCmp(char *a, char *b, int len, int* res) {
int workerId = threadIdx.x;
for (int i = 0; i < len; i++) {
if (a[i] != b[i]) {
*res = 0;
return;
}
}
}
__device__ void k_bruteIncrement(char* brute, int alphabetLen, int wordLen, int incrementBy, int *incRes) {
int i = 0;
int workerId = threadIdx.x;
while(incrementBy > 0 && i < wordLen) {
int add = incrementBy + brute[i];
brute[i] = (char)(add % alphabetLen);
incrementBy = add / alphabetLen;
i++;
}
*incRes = incrementBy == 0;
}
__device__ void bruteToString(char *brute, int wordLen, char *alphabet, char *out){
for(int i=0;i<wordLen;i++){
out[i]=alphabet[brute[i]];
}
out[wordLen]='\0';
}
int any(int *list, int listSize){
for(int i=0;i<listSize;i++){
if(list[i])return TRUE;
}
return FALSE;
}
__global__ void searchPart(char *targetString, char *alphabet, char *brutePart, int workSize, int wordLen, int alphabetLen, int* results){
int workerId = threadIdx.x;
results[workerId] = 0;
int incRes = FALSE;
// Receive start of latest section (WORKER * WORKSIZE), create local copy
char* t_brutePart = (char *) malloc((wordLen)* sizeof(char));
for (int i = 0; i < wordLen; i++) t_brutePart[i] = brutePart[i];
// Increment to start of this thread's chunk (WORKSIZE)
k_bruteIncrement(t_brutePart, alphabetLen, wordLen, workSize*workerId, &incRes);
if(!incRes){
return;
}
int count = 0;
char* out = (char *) malloc((wordLen + 1)* sizeof(char));
// Increment by one and compare strs after every iteration
while(1) {
if(count>=workSize) {
break;
}
bruteToString(t_brutePart, wordLen, alphabet, out);
int cmpRes = 1;
cudaStrCmp(out, targetString, wordLen, &cmpRes);
if(cmpRes == 1) {
results[workerId] = 1;
break;
}
count +=1;
incRes = 0;
k_bruteIncrement(t_brutePart, alphabetLen, wordLen, 1, &incRes);
if(!incRes) {
break;
}
}
free(out);
free(t_brutePart);
}
int search(char *targetString, char *alphabet, int numWorkers, int workSize){
int wordLen = strlen(targetString);
int alphabetLen = strlen(alphabet);
int size = wordLen*sizeof(char);
int alphabetSize = alphabetLen*sizeof(char);
char *k_alphabet;
int *k_alphabetLen;
int *k_wordLen;
char *k_targetString;
cudaMallocManaged(&k_alphabet, alphabetSize);
cudaMallocManaged(&k_alphabetLen, sizeof(int));
cudaMallocManaged(&k_wordLen, sizeof(int));
cudaMallocManaged(&k_targetString, size);
cudaMemcpy(k_alphabet, alphabet, alphabetSize, cudaMemcpyDefault );
cudaMemcpy(k_targetString, targetString, size, cudaMemcpyDefault );
*k_alphabetLen = strlen(alphabet);
*k_wordLen = strlen(targetString);
char brute [wordLen];
for(int i=0;i<wordLen;i++)brute[i]=0;
char* k_brutePart;
cudaMalloc(&k_brutePart, size);
int* k_results;
cudaMallocManaged(&k_results, numWorkers* sizeof(int));
int* results = (int*)malloc(sizeof(int) * numWorkers);
// Every iteration, increment brute (WORKERS * WORKSIZE) times
while(1){
cudaMemcpy(k_brutePart, brute, size, cudaMemcpyDefault );
for(int i=0;i<numWorkers;i++) k_results[i] = 0;
// Divide the section into chunks to be worked on in parallel
searchPart<<<1, numWorkers>>>(k_targetString, k_alphabet, k_brutePart, workSize, *k_wordLen, *k_alphabetLen, k_results);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
if(any(k_results, numWorkers)) return 1;
// advance to the next major chunk of work
if(!bruteIncrement(brute, alphabetLen, wordLen, workSize*numWorkers)){
break;
}
}
cudaFree(k_alphabet);
cudaFree(k_alphabetLen);
cudaFree(k_wordLen);
cudaFree(k_targetString);
cudaFree(k_brutePart);
cudaFree(k_results);
return 0;
}
int main( int argc, char** argv) {
char *targetString = argv[1];
char *alphabet = argv[2];
int numWorkers = atoi(argv[3]);
int workSize = atoi(argv[4]);
printf("Looking for %s in [%s]...\n", targetString, alphabet);
if(search(targetString, alphabet, numWorkers, workSize)){
printf("Found\n");
} else {
printf("Notfound\n");
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
const char TRUE = 1;
const char FALSE = 0;
int bruteIncrement(char* brute, int alphabetLen, int wordLen, int incrementBy) {
int i = 0;
while(incrementBy > 0 && i < wordLen) {
int add = incrementBy + brute[i];
brute[i] = (char)(add % alphabetLen);
incrementBy = add / alphabetLen;
i++;
}
return incrementBy == 0;
}
__device__ void cudaStrCmp(char *a, char *b, int len, int* res) {
int workerId = threadIdx.x;
for (int i = 0; i < len; i++) {
if (a[i] != b[i]) {
*res = 0;
return;
}
}
}
__device__ void k_bruteIncrement(char* brute, int alphabetLen, int wordLen, int incrementBy, int *incRes) {
int i = 0;
int workerId = threadIdx.x;
while(incrementBy > 0 && i < wordLen) {
int add = incrementBy + brute[i];
brute[i] = (char)(add % alphabetLen);
incrementBy = add / alphabetLen;
i++;
}
*incRes = incrementBy == 0;
}
__device__ void bruteToString(char *brute, int wordLen, char *alphabet, char *out){
for(int i=0;i<wordLen;i++){
out[i]=alphabet[brute[i]];
}
out[wordLen]='\0';
}
int any(int *list, int listSize){
for(int i=0;i<listSize;i++){
if(list[i])return TRUE;
}
return FALSE;
}
__global__ void searchPart(char *targetString, char *alphabet, char *brutePart, int workSize, int wordLen, int alphabetLen, int* results){
int workerId = threadIdx.x;
results[workerId] = 0;
int incRes = FALSE;
// Receive start of latest section (WORKER * WORKSIZE), create local copy
char* t_brutePart = (char *) malloc((wordLen)* sizeof(char));
for (int i = 0; i < wordLen; i++) t_brutePart[i] = brutePart[i];
// Increment to start of this thread's chunk (WORKSIZE)
k_bruteIncrement(t_brutePart, alphabetLen, wordLen, workSize*workerId, &incRes);
if(!incRes){
return;
}
int count = 0;
char* out = (char *) malloc((wordLen + 1)* sizeof(char));
// Increment by one and compare strs after every iteration
while(1) {
if(count>=workSize) {
break;
}
bruteToString(t_brutePart, wordLen, alphabet, out);
int cmpRes = 1;
cudaStrCmp(out, targetString, wordLen, &cmpRes);
if(cmpRes == 1) {
results[workerId] = 1;
break;
}
count +=1;
incRes = 0;
k_bruteIncrement(t_brutePart, alphabetLen, wordLen, 1, &incRes);
if(!incRes) {
break;
}
}
free(out);
free(t_brutePart);
}
int search(char *targetString, char *alphabet, int numWorkers, int workSize){
int wordLen = strlen(targetString);
int alphabetLen = strlen(alphabet);
int size = wordLen*sizeof(char);
int alphabetSize = alphabetLen*sizeof(char);
char *k_alphabet;
int *k_alphabetLen;
int *k_wordLen;
char *k_targetString;
hipMallocManaged(&k_alphabet, alphabetSize);
hipMallocManaged(&k_alphabetLen, sizeof(int));
hipMallocManaged(&k_wordLen, sizeof(int));
hipMallocManaged(&k_targetString, size);
hipMemcpy(k_alphabet, alphabet, alphabetSize, hipMemcpyDefault );
hipMemcpy(k_targetString, targetString, size, hipMemcpyDefault );
*k_alphabetLen = strlen(alphabet);
*k_wordLen = strlen(targetString);
char brute [wordLen];
for(int i=0;i<wordLen;i++)brute[i]=0;
char* k_brutePart;
hipMalloc(&k_brutePart, size);
int* k_results;
hipMallocManaged(&k_results, numWorkers* sizeof(int));
int* results = (int*)malloc(sizeof(int) * numWorkers);
// Every iteration, increment brute (WORKERS * WORKSIZE) times
while(1){
hipMemcpy(k_brutePart, brute, size, hipMemcpyDefault );
for(int i=0;i<numWorkers;i++) k_results[i] = 0;
// Divide the section into chunks to be worked on in parallel
searchPart<<<1, numWorkers>>>(k_targetString, k_alphabet, k_brutePart, workSize, *k_wordLen, *k_alphabetLen, k_results);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
if(any(k_results, numWorkers)) return 1;
// advance to the next major chunk of work
if(!bruteIncrement(brute, alphabetLen, wordLen, workSize*numWorkers)){
break;
}
}
hipFree(k_alphabet);
hipFree(k_alphabetLen);
hipFree(k_wordLen);
hipFree(k_targetString);
hipFree(k_brutePart);
hipFree(k_results);
return 0;
}
int main( int argc, char** argv) {
char *targetString = argv[1];
char *alphabet = argv[2];
int numWorkers = atoi(argv[3]);
int workSize = atoi(argv[4]);
printf("Looking for %s in [%s]...\n", targetString, alphabet);
if(search(targetString, alphabet, numWorkers, workSize)){
printf("Found\n");
} else {
printf("Notfound\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
const char TRUE = 1;
const char FALSE = 0;
int bruteIncrement(char* brute, int alphabetLen, int wordLen, int incrementBy) {
int i = 0;
while(incrementBy > 0 && i < wordLen) {
int add = incrementBy + brute[i];
brute[i] = (char)(add % alphabetLen);
incrementBy = add / alphabetLen;
i++;
}
return incrementBy == 0;
}
__device__ void cudaStrCmp(char *a, char *b, int len, int* res) {
int workerId = threadIdx.x;
for (int i = 0; i < len; i++) {
if (a[i] != b[i]) {
*res = 0;
return;
}
}
}
__device__ void k_bruteIncrement(char* brute, int alphabetLen, int wordLen, int incrementBy, int *incRes) {
int i = 0;
int workerId = threadIdx.x;
while(incrementBy > 0 && i < wordLen) {
int add = incrementBy + brute[i];
brute[i] = (char)(add % alphabetLen);
incrementBy = add / alphabetLen;
i++;
}
*incRes = incrementBy == 0;
}
__device__ void bruteToString(char *brute, int wordLen, char *alphabet, char *out){
for(int i=0;i<wordLen;i++){
out[i]=alphabet[brute[i]];
}
out[wordLen]='\0';
}
int any(int *list, int listSize){
for(int i=0;i<listSize;i++){
if(list[i])return TRUE;
}
return FALSE;
}
__global__ void searchPart(char *targetString, char *alphabet, char *brutePart, int workSize, int wordLen, int alphabetLen, int* results){
int workerId = threadIdx.x;
results[workerId] = 0;
int incRes = FALSE;
// Receive start of latest section (WORKER * WORKSIZE), create local copy
char* t_brutePart = (char *) malloc((wordLen)* sizeof(char));
for (int i = 0; i < wordLen; i++) t_brutePart[i] = brutePart[i];
// Increment to start of this thread's chunk (WORKSIZE)
k_bruteIncrement(t_brutePart, alphabetLen, wordLen, workSize*workerId, &incRes);
if(!incRes){
return;
}
int count = 0;
char* out = (char *) malloc((wordLen + 1)* sizeof(char));
// Increment by one and compare strs after every iteration
while(1) {
if(count>=workSize) {
break;
}
bruteToString(t_brutePart, wordLen, alphabet, out);
int cmpRes = 1;
cudaStrCmp(out, targetString, wordLen, &cmpRes);
if(cmpRes == 1) {
results[workerId] = 1;
break;
}
count +=1;
incRes = 0;
k_bruteIncrement(t_brutePart, alphabetLen, wordLen, 1, &incRes);
if(!incRes) {
break;
}
}
free(out);
free(t_brutePart);
}
int search(char *targetString, char *alphabet, int numWorkers, int workSize){
int wordLen = strlen(targetString);
int alphabetLen = strlen(alphabet);
int size = wordLen*sizeof(char);
int alphabetSize = alphabetLen*sizeof(char);
char *k_alphabet;
int *k_alphabetLen;
int *k_wordLen;
char *k_targetString;
hipMallocManaged(&k_alphabet, alphabetSize);
hipMallocManaged(&k_alphabetLen, sizeof(int));
hipMallocManaged(&k_wordLen, sizeof(int));
hipMallocManaged(&k_targetString, size);
hipMemcpy(k_alphabet, alphabet, alphabetSize, hipMemcpyDefault );
hipMemcpy(k_targetString, targetString, size, hipMemcpyDefault );
*k_alphabetLen = strlen(alphabet);
*k_wordLen = strlen(targetString);
char brute [wordLen];
for(int i=0;i<wordLen;i++)brute[i]=0;
char* k_brutePart;
hipMalloc(&k_brutePart, size);
int* k_results;
hipMallocManaged(&k_results, numWorkers* sizeof(int));
int* results = (int*)malloc(sizeof(int) * numWorkers);
// Every iteration, increment brute (WORKERS * WORKSIZE) times
while(1){
hipMemcpy(k_brutePart, brute, size, hipMemcpyDefault );
for(int i=0;i<numWorkers;i++) k_results[i] = 0;
// Divide the section into chunks to be worked on in parallel
searchPart<<<1, numWorkers>>>(k_targetString, k_alphabet, k_brutePart, workSize, *k_wordLen, *k_alphabetLen, k_results);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
if(any(k_results, numWorkers)) return 1;
// advance to the next major chunk of work
if(!bruteIncrement(brute, alphabetLen, wordLen, workSize*numWorkers)){
break;
}
}
hipFree(k_alphabet);
hipFree(k_alphabetLen);
hipFree(k_wordLen);
hipFree(k_targetString);
hipFree(k_brutePart);
hipFree(k_results);
return 0;
}
int main( int argc, char** argv) {
char *targetString = argv[1];
char *alphabet = argv[2];
int numWorkers = atoi(argv[3]);
int workSize = atoi(argv[4]);
printf("Looking for %s in [%s]...\n", targetString, alphabet);
if(search(targetString, alphabet, numWorkers, workSize)){
printf("Found\n");
} else {
printf("Notfound\n");
}
return 0;
} | .text
.file "Search.hip"
.globl _Z14bruteIncrementPciii # -- Begin function _Z14bruteIncrementPciii
.p2align 4, 0x90
.type _Z14bruteIncrementPciii,@function
_Z14bruteIncrementPciii: # @_Z14bruteIncrementPciii
.cfi_startproc
# %bb.0:
movl %ecx, %eax
testl %ecx, %ecx
jle .LBB0_5
# %bb.1:
testl %edx, %edx
jle .LBB0_5
# %bb.2: # %.lr.ph.preheader
movslq %edx, %r8
movl $1, %r9d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsbl -1(%rdi,%r9), %ecx
addl %eax, %ecx
movl %ecx, %eax
cltd
idivl %esi
movb %dl, -1(%rdi,%r9)
testl %eax, %eax
jle .LBB0_5
# %bb.4: # %.lr.ph
# in Loop: Header=BB0_3 Depth=1
leaq 1(%r9), %rcx
cmpq %r8, %r9
movq %rcx, %r9
jl .LBB0_3
.LBB0_5: # %._crit_edge
xorl %ecx, %ecx
testl %eax, %eax
sete %cl
movl %ecx, %eax
retq
.Lfunc_end0:
.size _Z14bruteIncrementPciii, .Lfunc_end0-_Z14bruteIncrementPciii
.cfi_endproc
# -- End function
.globl _Z3anyPii # -- Begin function _Z3anyPii
.p2align 4, 0x90
.type _Z3anyPii,@function
_Z3anyPii: # @_Z3anyPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
setg %al
jle .LBB1_6
# %bb.1: # %.lr.ph.preheader
cmpl $0, (%rdi)
je .LBB1_2
.LBB1_6: # %._crit_edge
movzbl %al, %eax
retq
.LBB1_2: # %.lr.ph16.preheader
movl %esi, %eax
movl $1, %edx
.p2align 4, 0x90
.LBB1_3: # %.lr.ph16
# =>This Inner Loop Header: Depth=1
movq %rdx, %rcx
cmpq %rdx, %rax
je .LBB1_5
# %bb.4: # %.lr.ph
# in Loop: Header=BB1_3 Depth=1
leaq 1(%rcx), %rdx
cmpl $0, (%rdi,%rcx,4)
je .LBB1_3
.LBB1_5: # %._crit_edge.loopexit
cmpq %rax, %rcx
setb %al
movzbl %al, %eax
retq
.Lfunc_end1:
.size _Z3anyPii, .Lfunc_end1-_Z3anyPii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__searchPartPcS_S_iiiPi # -- Begin function _Z25__device_stub__searchPartPcS_S_iiiPi
.p2align 4, 0x90
.type _Z25__device_stub__searchPartPcS_S_iiiPi,@function
_Z25__device_stub__searchPartPcS_S_iiiPi: # @_Z25__device_stub__searchPartPcS_S_iiiPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10searchPartPcS_S_iiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z25__device_stub__searchPartPcS_S_iiiPi, .Lfunc_end2-_Z25__device_stub__searchPartPcS_S_iiiPi
.cfi_endproc
# -- End function
.globl _Z6searchPcS_ii # -- Begin function _Z6searchPcS_ii
.p2align 4, 0x90
.type _Z6searchPcS_ii,@function
_Z6searchPcS_ii: # @_Z6searchPcS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $264, %rsp # imm = 0x108
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl %ecx, -52(%rbp) # 4-byte Spill
movl %edx, -48(%rbp) # 4-byte Spill
movq %rsi, %r12
movq %rdi, %rbx
callq strlen
movq %rax, %r14
movq %r12, %rdi
callq strlen
movq %rax, %r15
movq %r14, -64(%rbp) # 8-byte Spill
movslq %r14d, %r14
movslq %r15d, %r13
leaq -120(%rbp), %rdi
movq %r13, %rsi
movl $1, %edx
callq hipMallocManaged
leaq -112(%rbp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq -104(%rbp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq -96(%rbp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
movq -120(%rbp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $4, %ecx
callq hipMemcpy
movq -96(%rbp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $4, %ecx
callq hipMemcpy
movq %r12, %rdi
callq strlen
movq -112(%rbp), %rcx
movl %eax, (%rcx)
movq %rbx, %rdi
callq strlen
movq %rsp, -144(%rbp) # 8-byte Spill
movq -104(%rbp), %rcx
movl %eax, (%rcx)
movl %r14d, %eax
movq %rsp, %r13
addq $15, %rax
andq $-16, %rax
subq %rax, %r13
movq %r13, %rsp
movq %r14, -80(%rbp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB3_2
# %bb.1: # %.lr.ph.preheader
movl -64(%rbp), %edx # 4-byte Reload
movq %r13, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB3_2: # %._crit_edge
leaq -88(%rbp), %rdi
movq -80(%rbp), %rsi # 8-byte Reload
callq hipMalloc
movl -48(%rbp), %r14d # 4-byte Reload
movslq %r14d, %rbx
leaq (,%rbx,4), %rsi
leaq -72(%rbp), %rdi
movl $1, %edx
callq hipMallocManaged
movl %ebx, %r12d
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%r12,%rdx), %rax
movq %rax, -160(%rbp) # 8-byte Spill
testl %ebx, %ebx
setg -42(%rbp) # 1-byte Folded Spill
movl -52(%rbp), %ebx # 4-byte Reload
imull %r14d, %ebx
testl %ebx, %ebx
setg %al
cmpl $0, -80(%rbp) # 4-byte Folded Reload
setg %cl
andb %al, %cl
movb %cl, -41(%rbp) # 1-byte Spill
movslq -64(%rbp), %r14 # 4-byte Folded Reload
leaq (,%r12,4), %rax
movq %rax, -152(%rbp) # 8-byte Spill
movq %rdx, %rax
incq %rax
movq %rax, -64(%rbp) # 8-byte Spill
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_3: # %_Z14bruteIncrementPciii.exit
# in Loop: Header=BB3_4 Depth=1
testl %eax, %eax
jne .LBB3_20
.LBB3_4: # =>This Loop Header: Depth=1
# Child Loop BB3_11 Depth 2
# Child Loop BB3_17 Depth 2
movq -88(%rbp), %rdi
movq %r13, %rsi
movq -80(%rbp), %rdx # 8-byte Reload
movl $4, %ecx
callq hipMemcpy
cmpl $0, -48(%rbp) # 4-byte Folded Reload
jle .LBB3_6
# %bb.5: # %.lr.ph54
# in Loop: Header=BB3_4 Depth=1
movq -72(%rbp), %rdi
xorl %esi, %esi
movq -152(%rbp), %rdx # 8-byte Reload
callq memset@PLT
.LBB3_6: # %._crit_edge55
# in Loop: Header=BB3_4 Depth=1
movq -64(%rbp), %rdi # 8-byte Reload
movl $1, %esi
movq -160(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_4 Depth=1
movq -96(%rbp), %rax
movq -104(%rbp), %rcx
movl (%rcx), %ecx
movq -112(%rbp), %rdx
movl (%rdx), %edx
movq %rax, -240(%rbp)
movq -120(%rbp), %rax
movq %rax, -232(%rbp)
movq -88(%rbp), %rax
movq %rax, -224(%rbp)
movl %ecx, -128(%rbp)
movl %edx, -124(%rbp)
movq -72(%rbp), %rax
movq %rax, -216(%rbp)
movl -52(%rbp), %eax # 4-byte Reload
movl %eax, -132(%rbp)
leaq -240(%rbp), %rax
movq %rax, -304(%rbp)
leaq -232(%rbp), %rax
movq %rax, -296(%rbp)
leaq -224(%rbp), %rax
movq %rax, -288(%rbp)
leaq -132(%rbp), %rax
movq %rax, -280(%rbp)
leaq -128(%rbp), %rax
movq %rax, -272(%rbp)
leaq -124(%rbp), %rax
movq %rax, -264(%rbp)
leaq -216(%rbp), %rax
movq %rax, -256(%rbp)
leaq -208(%rbp), %rdi
leaq -192(%rbp), %rsi
leaq -176(%rbp), %rdx
leaq -168(%rbp), %rcx
callq __hipPopCallConfiguration
movq -208(%rbp), %rsi
movl -200(%rbp), %edx
movq -192(%rbp), %rcx
movl -184(%rbp), %r8d
movl $_Z10searchPartPcS_S_iiiPi, %edi
leaq -304(%rbp), %r9
pushq -168(%rbp)
pushq -176(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB3_8: # in Loop: Header=BB3_4 Depth=1
callq hipDeviceSynchronize
movzbl -42(%rbp), %eax # 1-byte Folded Reload
cmpl $0, -48(%rbp) # 4-byte Folded Reload
jle .LBB3_14
# %bb.9: # %.lr.ph.i.preheader
# in Loop: Header=BB3_4 Depth=1
movq -72(%rbp), %rax
cmpl $0, (%rax)
jne .LBB3_21
# %bb.10: # %.lr.ph58.preheader
# in Loop: Header=BB3_4 Depth=1
movl $1, %edx
.p2align 4, 0x90
.LBB3_11: # %.lr.ph58
# Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
movq %rdx, %rcx
cmpq %rdx, %r12
je .LBB3_13
# %bb.12: # %.lr.ph.i
# in Loop: Header=BB3_11 Depth=2
leaq 1(%rcx), %rdx
cmpl $0, (%rax,%rcx,4)
je .LBB3_11
.LBB3_13: # %_Z3anyPii.exit.loopexit
# in Loop: Header=BB3_4 Depth=1
cmpq %r12, %rcx
setb %al
.LBB3_14: # %_Z3anyPii.exit
# in Loop: Header=BB3_4 Depth=1
testb %al, %al
jne .LBB3_21
# %bb.15: # in Loop: Header=BB3_4 Depth=1
movl %ebx, %eax
cmpb $0, -41(%rbp) # 1-byte Folded Reload
je .LBB3_3
# %bb.16: # %.lr.ph.i43.preheader
# in Loop: Header=BB3_4 Depth=1
movl $1, %esi
movl %ebx, %eax
.p2align 4, 0x90
.LBB3_17: # %.lr.ph.i43
# Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
movsbl -1(%r13,%rsi), %ecx
addl %eax, %ecx
movl %ecx, %eax
cltd
idivl %r15d
movb %dl, -1(%r13,%rsi)
testl %eax, %eax
jle .LBB3_3
# %bb.18: # %.lr.ph.i43
# in Loop: Header=BB3_17 Depth=2
leaq 1(%rsi), %rcx
cmpq %r14, %rsi
movq %rcx, %rsi
jl .LBB3_17
jmp .LBB3_3
.LBB3_21:
movl $1, %eax
jmp .LBB3_22
.LBB3_20:
movq -120(%rbp), %rdi
callq hipFree
movq -112(%rbp), %rdi
callq hipFree
movq -104(%rbp), %rdi
callq hipFree
movq -96(%rbp), %rdi
callq hipFree
movq -88(%rbp), %rdi
callq hipFree
movq -72(%rbp), %rdi
callq hipFree
xorl %eax, %eax
.LBB3_22: # %.loopexit
movq -144(%rbp), %rsp # 8-byte Reload
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end3:
.size _Z6searchPcS_ii, .Lfunc_end3-_Z6searchPcS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r15
movq 8(%rsi), %rbx
movq 16(%rsi), %r14
movq 24(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 32(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl $.L.str, %edi
movq %rbx, %rsi
movq %r14, %rdx
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movq %r14, %rsi
movl %r12d, %edx
movl %r15d, %ecx
callq _Z6searchPcS_ii
testl %eax, %eax
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10searchPartPcS_S_iiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10searchPartPcS_S_iiiPi,@object # @_Z10searchPartPcS_S_iiiPi
.section .rodata,"a",@progbits
.globl _Z10searchPartPcS_S_iiiPi
.p2align 3, 0x0
_Z10searchPartPcS_S_iiiPi:
.quad _Z25__device_stub__searchPartPcS_S_iiiPi
.size _Z10searchPartPcS_S_iiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Looking for %s in [%s]...\n"
.size .L.str, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10searchPartPcS_S_iiiPi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Notfound"
.size .Lstr, 9
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Found"
.size .Lstr.1, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__searchPartPcS_S_iiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10searchPartPcS_S_iiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ba0b7_00000000-6_Search.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14bruteIncrementPciii
.type _Z14bruteIncrementPciii, @function
_Z14bruteIncrementPciii:
.LFB2057:
.cfi_startproc
endbr64
movl %esi, %r8d
movl %edx, %r9d
testl %ecx, %ecx
jle .L4
testl %edx, %edx
jle .L4
movl $1, %esi
.L5:
movsbl -1(%rdi,%rsi), %eax
addl %ecx, %eax
cltd
idivl %r8d
movb %dl, -1(%rdi,%rsi)
movl %eax, %ecx
testl %eax, %eax
setg %dl
cmpl %esi, %r9d
setg %al
addq $1, %rsi
testb %al, %dl
jne .L5
.L4:
testl %ecx, %ecx
sete %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z14bruteIncrementPciii, .-_Z14bruteIncrementPciii
.globl _Z10cudaStrCmpPcS_iPi
.type _Z10cudaStrCmpPcS_iPi, @function
_Z10cudaStrCmpPcS_iPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10cudaStrCmpPcS_iPi, .-_Z10cudaStrCmpPcS_iPi
.globl _Z16k_bruteIncrementPciiiPi
.type _Z16k_bruteIncrementPciiiPi, @function
_Z16k_bruteIncrementPciiiPi:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z16k_bruteIncrementPciiiPi, .-_Z16k_bruteIncrementPciiiPi
.globl _Z13bruteToStringPciS_S_
.type _Z13bruteToStringPciS_S_, @function
_Z13bruteToStringPciS_S_:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z13bruteToStringPciS_S_, .-_Z13bruteToStringPciS_S_
.globl _Z3anyPii
.type _Z3anyPii, @function
_Z3anyPii:
.LFB2061:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
.L15:
movl (%rax), %edx
testl %edx, %edx
jne .L17
addq $4, %rax
cmpq %rcx, %rax
jne .L15
jmp .L13
.L16:
movl $0, %edx
jmp .L13
.L17:
movl $1, %edx
.L13:
movl %edx, %eax
ret
.cfi_endproc
.LFE2061:
.size _Z3anyPii, .-_Z3anyPii
.globl _Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi
.type _Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi, @function
_Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10searchPartPcS_S_iiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi, .-_Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi
.globl _Z10searchPartPcS_S_iiiPi
.type _Z10searchPartPcS_S_iiiPi, @function
_Z10searchPartPcS_S_iiiPi:
.LFB2089:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z10searchPartPcS_S_iiiPi, .-_Z10searchPartPcS_S_iiiPi
.globl _Z6searchPcS_ii
.type _Z6searchPcS_ii, @function
_Z6searchPcS_ii:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, %r14
movl %edx, %r13d
movl %ecx, -148(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq %rdi, -136(%rbp)
call strlen@PLT
movq %rax, %rbx
movl %eax, -140(%rbp)
movq %r14, %rdi
call strlen@PLT
movl %eax, -144(%rbp)
movslq %eax, %r12
leaq -128(%rbp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq -120(%rbp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq -112(%rbp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movslq %ebx, %r15
leaq -104(%rbp), %rdi
movl $1, %edx
movq %r15, %rsi
call cudaMallocManaged@PLT
movl $4, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq -128(%rbp), %rdi
call cudaMemcpy@PLT
movl $4, %ecx
movq %r15, %rdx
movq -136(%rbp), %r12
movq %r12, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
movq %r14, %rdi
call strlen@PLT
movq -120(%rbp), %rdx
movl %eax, (%rdx)
movq %r12, %rdi
call strlen@PLT
movq -112(%rbp), %rdx
movl %eax, (%rdx)
leaq 15(%r15), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L28:
cmpq %rdx, %rsp
je .L29
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L28
.L29:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L30
orq $0, -8(%rsp,%rax)
.L30:
movq %rsp, %r14
testl %ebx, %ebx
jle .L31
movq %r14, %rax
leal -1(%rbx), %edx
leaq 1(%r14,%rdx), %rdx
.L32:
movb $0, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L32
.L31:
leaq -96(%rbp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movslq %r13d, %rbx
salq $2, %rbx
leaq -88(%rbp), %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
movl -148(%rbp), %eax
imull %r13d, %eax
movl %eax, -136(%rbp)
jmp .L37
.L35:
call cudaDeviceSynchronize@PLT
movl %r13d, %esi
movq -88(%rbp), %rdi
call _Z3anyPii
testl %eax, %eax
jne .L39
movl -136(%rbp), %ecx
movl -140(%rbp), %edx
movl -144(%rbp), %esi
movq %r14, %rdi
call _Z14bruteIncrementPciii
movl %eax, %r12d
testl %eax, %eax
je .L44
.L37:
movl $4, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L33
movl $0, %eax
.L34:
movq -88(%rbp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq %rax, %rbx
jne .L34
.L33:
movl %r13d, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L35
movq -120(%rbp), %rax
movl (%rax), %r9d
movq -112(%rbp), %rax
movl (%rax), %r8d
subq $8, %rsp
pushq -88(%rbp)
movl -148(%rbp), %ecx
movq -96(%rbp), %rdx
movq -128(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z39__device_stub__Z10searchPartPcS_S_iiiPiPcS_S_iiiPi
addq $16, %rsp
jmp .L35
.L44:
movq -128(%rbp), %rdi
call cudaFree@PLT
movq -120(%rbp), %rdi
call cudaFree@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
jmp .L27
.L39:
movl $1, %r12d
.L27:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L45
movl %r12d, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L45:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z6searchPcS_ii, .-_Z6searchPcS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Looking for %s in [%s]...\n"
.LC1:
.string "Found\n"
.LC2:
.string "Notfound\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbx
movq 8(%rsi), %r12
movq 16(%rsi), %r13
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq %r13, %rcx
movq %r12, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movl %ebp, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z6searchPcS_ii
testl %eax, %eax
je .L47
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L48:
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10searchPartPcS_S_iiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10searchPartPcS_S_iiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Search.hip"
.globl _Z14bruteIncrementPciii # -- Begin function _Z14bruteIncrementPciii
.p2align 4, 0x90
.type _Z14bruteIncrementPciii,@function
_Z14bruteIncrementPciii: # @_Z14bruteIncrementPciii
.cfi_startproc
# %bb.0:
movl %ecx, %eax
testl %ecx, %ecx
jle .LBB0_5
# %bb.1:
testl %edx, %edx
jle .LBB0_5
# %bb.2: # %.lr.ph.preheader
movslq %edx, %r8
movl $1, %r9d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsbl -1(%rdi,%r9), %ecx
addl %eax, %ecx
movl %ecx, %eax
cltd
idivl %esi
movb %dl, -1(%rdi,%r9)
testl %eax, %eax
jle .LBB0_5
# %bb.4: # %.lr.ph
# in Loop: Header=BB0_3 Depth=1
leaq 1(%r9), %rcx
cmpq %r8, %r9
movq %rcx, %r9
jl .LBB0_3
.LBB0_5: # %._crit_edge
xorl %ecx, %ecx
testl %eax, %eax
sete %cl
movl %ecx, %eax
retq
.Lfunc_end0:
.size _Z14bruteIncrementPciii, .Lfunc_end0-_Z14bruteIncrementPciii
.cfi_endproc
# -- End function
.globl _Z3anyPii # -- Begin function _Z3anyPii
.p2align 4, 0x90
.type _Z3anyPii,@function
_Z3anyPii: # @_Z3anyPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
setg %al
jle .LBB1_6
# %bb.1: # %.lr.ph.preheader
cmpl $0, (%rdi)
je .LBB1_2
.LBB1_6: # %._crit_edge
movzbl %al, %eax
retq
.LBB1_2: # %.lr.ph16.preheader
movl %esi, %eax
movl $1, %edx
.p2align 4, 0x90
.LBB1_3: # %.lr.ph16
# =>This Inner Loop Header: Depth=1
movq %rdx, %rcx
cmpq %rdx, %rax
je .LBB1_5
# %bb.4: # %.lr.ph
# in Loop: Header=BB1_3 Depth=1
leaq 1(%rcx), %rdx
cmpl $0, (%rdi,%rcx,4)
je .LBB1_3
.LBB1_5: # %._crit_edge.loopexit
cmpq %rax, %rcx
setb %al
movzbl %al, %eax
retq
.Lfunc_end1:
.size _Z3anyPii, .Lfunc_end1-_Z3anyPii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__searchPartPcS_S_iiiPi # -- Begin function _Z25__device_stub__searchPartPcS_S_iiiPi
.p2align 4, 0x90
.type _Z25__device_stub__searchPartPcS_S_iiiPi,@function
_Z25__device_stub__searchPartPcS_S_iiiPi: # @_Z25__device_stub__searchPartPcS_S_iiiPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10searchPartPcS_S_iiiPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z25__device_stub__searchPartPcS_S_iiiPi, .Lfunc_end2-_Z25__device_stub__searchPartPcS_S_iiiPi
.cfi_endproc
# -- End function
.globl _Z6searchPcS_ii # -- Begin function _Z6searchPcS_ii
.p2align 4, 0x90
.type _Z6searchPcS_ii,@function
_Z6searchPcS_ii: # @_Z6searchPcS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $264, %rsp # imm = 0x108
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl %ecx, -52(%rbp) # 4-byte Spill
movl %edx, -48(%rbp) # 4-byte Spill
movq %rsi, %r12
movq %rdi, %rbx
callq strlen
movq %rax, %r14
movq %r12, %rdi
callq strlen
movq %rax, %r15
movq %r14, -64(%rbp) # 8-byte Spill
movslq %r14d, %r14
movslq %r15d, %r13
leaq -120(%rbp), %rdi
movq %r13, %rsi
movl $1, %edx
callq hipMallocManaged
leaq -112(%rbp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq -104(%rbp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq -96(%rbp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
movq -120(%rbp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $4, %ecx
callq hipMemcpy
movq -96(%rbp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $4, %ecx
callq hipMemcpy
movq %r12, %rdi
callq strlen
movq -112(%rbp), %rcx
movl %eax, (%rcx)
movq %rbx, %rdi
callq strlen
movq %rsp, -144(%rbp) # 8-byte Spill
movq -104(%rbp), %rcx
movl %eax, (%rcx)
movl %r14d, %eax
movq %rsp, %r13
addq $15, %rax
andq $-16, %rax
subq %rax, %r13
movq %r13, %rsp
movq %r14, -80(%rbp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB3_2
# %bb.1: # %.lr.ph.preheader
movl -64(%rbp), %edx # 4-byte Reload
movq %r13, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB3_2: # %._crit_edge
leaq -88(%rbp), %rdi
movq -80(%rbp), %rsi # 8-byte Reload
callq hipMalloc
movl -48(%rbp), %r14d # 4-byte Reload
movslq %r14d, %rbx
leaq (,%rbx,4), %rsi
leaq -72(%rbp), %rdi
movl $1, %edx
callq hipMallocManaged
movl %ebx, %r12d
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%r12,%rdx), %rax
movq %rax, -160(%rbp) # 8-byte Spill
testl %ebx, %ebx
setg -42(%rbp) # 1-byte Folded Spill
movl -52(%rbp), %ebx # 4-byte Reload
imull %r14d, %ebx
testl %ebx, %ebx
setg %al
cmpl $0, -80(%rbp) # 4-byte Folded Reload
setg %cl
andb %al, %cl
movb %cl, -41(%rbp) # 1-byte Spill
movslq -64(%rbp), %r14 # 4-byte Folded Reload
leaq (,%r12,4), %rax
movq %rax, -152(%rbp) # 8-byte Spill
movq %rdx, %rax
incq %rax
movq %rax, -64(%rbp) # 8-byte Spill
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_3: # %_Z14bruteIncrementPciii.exit
# in Loop: Header=BB3_4 Depth=1
testl %eax, %eax
jne .LBB3_20
.LBB3_4: # =>This Loop Header: Depth=1
# Child Loop BB3_11 Depth 2
# Child Loop BB3_17 Depth 2
movq -88(%rbp), %rdi
movq %r13, %rsi
movq -80(%rbp), %rdx # 8-byte Reload
movl $4, %ecx
callq hipMemcpy
cmpl $0, -48(%rbp) # 4-byte Folded Reload
jle .LBB3_6
# %bb.5: # %.lr.ph54
# in Loop: Header=BB3_4 Depth=1
movq -72(%rbp), %rdi
xorl %esi, %esi
movq -152(%rbp), %rdx # 8-byte Reload
callq memset@PLT
.LBB3_6: # %._crit_edge55
# in Loop: Header=BB3_4 Depth=1
movq -64(%rbp), %rdi # 8-byte Reload
movl $1, %esi
movq -160(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_4 Depth=1
movq -96(%rbp), %rax
movq -104(%rbp), %rcx
movl (%rcx), %ecx
movq -112(%rbp), %rdx
movl (%rdx), %edx
movq %rax, -240(%rbp)
movq -120(%rbp), %rax
movq %rax, -232(%rbp)
movq -88(%rbp), %rax
movq %rax, -224(%rbp)
movl %ecx, -128(%rbp)
movl %edx, -124(%rbp)
movq -72(%rbp), %rax
movq %rax, -216(%rbp)
movl -52(%rbp), %eax # 4-byte Reload
movl %eax, -132(%rbp)
leaq -240(%rbp), %rax
movq %rax, -304(%rbp)
leaq -232(%rbp), %rax
movq %rax, -296(%rbp)
leaq -224(%rbp), %rax
movq %rax, -288(%rbp)
leaq -132(%rbp), %rax
movq %rax, -280(%rbp)
leaq -128(%rbp), %rax
movq %rax, -272(%rbp)
leaq -124(%rbp), %rax
movq %rax, -264(%rbp)
leaq -216(%rbp), %rax
movq %rax, -256(%rbp)
leaq -208(%rbp), %rdi
leaq -192(%rbp), %rsi
leaq -176(%rbp), %rdx
leaq -168(%rbp), %rcx
callq __hipPopCallConfiguration
movq -208(%rbp), %rsi
movl -200(%rbp), %edx
movq -192(%rbp), %rcx
movl -184(%rbp), %r8d
movl $_Z10searchPartPcS_S_iiiPi, %edi
leaq -304(%rbp), %r9
pushq -168(%rbp)
pushq -176(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB3_8: # in Loop: Header=BB3_4 Depth=1
callq hipDeviceSynchronize
movzbl -42(%rbp), %eax # 1-byte Folded Reload
cmpl $0, -48(%rbp) # 4-byte Folded Reload
jle .LBB3_14
# %bb.9: # %.lr.ph.i.preheader
# in Loop: Header=BB3_4 Depth=1
movq -72(%rbp), %rax
cmpl $0, (%rax)
jne .LBB3_21
# %bb.10: # %.lr.ph58.preheader
# in Loop: Header=BB3_4 Depth=1
movl $1, %edx
.p2align 4, 0x90
.LBB3_11: # %.lr.ph58
# Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
movq %rdx, %rcx
cmpq %rdx, %r12
je .LBB3_13
# %bb.12: # %.lr.ph.i
# in Loop: Header=BB3_11 Depth=2
leaq 1(%rcx), %rdx
cmpl $0, (%rax,%rcx,4)
je .LBB3_11
.LBB3_13: # %_Z3anyPii.exit.loopexit
# in Loop: Header=BB3_4 Depth=1
cmpq %r12, %rcx
setb %al
.LBB3_14: # %_Z3anyPii.exit
# in Loop: Header=BB3_4 Depth=1
testb %al, %al
jne .LBB3_21
# %bb.15: # in Loop: Header=BB3_4 Depth=1
movl %ebx, %eax
cmpb $0, -41(%rbp) # 1-byte Folded Reload
je .LBB3_3
# %bb.16: # %.lr.ph.i43.preheader
# in Loop: Header=BB3_4 Depth=1
movl $1, %esi
movl %ebx, %eax
.p2align 4, 0x90
.LBB3_17: # %.lr.ph.i43
# Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
movsbl -1(%r13,%rsi), %ecx
addl %eax, %ecx
movl %ecx, %eax
cltd
idivl %r15d
movb %dl, -1(%r13,%rsi)
testl %eax, %eax
jle .LBB3_3
# %bb.18: # %.lr.ph.i43
# in Loop: Header=BB3_17 Depth=2
leaq 1(%rsi), %rcx
cmpq %r14, %rsi
movq %rcx, %rsi
jl .LBB3_17
jmp .LBB3_3
.LBB3_21:
movl $1, %eax
jmp .LBB3_22
.LBB3_20:
movq -120(%rbp), %rdi
callq hipFree
movq -112(%rbp), %rdi
callq hipFree
movq -104(%rbp), %rdi
callq hipFree
movq -96(%rbp), %rdi
callq hipFree
movq -88(%rbp), %rdi
callq hipFree
movq -72(%rbp), %rdi
callq hipFree
xorl %eax, %eax
.LBB3_22: # %.loopexit
movq -144(%rbp), %rsp # 8-byte Reload
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end3:
.size _Z6searchPcS_ii, .Lfunc_end3-_Z6searchPcS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r15
movq 8(%rsi), %rbx
movq 16(%rsi), %r14
movq 24(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 32(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl $.L.str, %edi
movq %rbx, %rsi
movq %r14, %rdx
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movq %r14, %rsi
movl %r12d, %edx
movl %r15d, %ecx
callq _Z6searchPcS_ii
testl %eax, %eax
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10searchPartPcS_S_iiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10searchPartPcS_S_iiiPi,@object # @_Z10searchPartPcS_S_iiiPi
.section .rodata,"a",@progbits
.globl _Z10searchPartPcS_S_iiiPi
.p2align 3, 0x0
_Z10searchPartPcS_S_iiiPi:
.quad _Z25__device_stub__searchPartPcS_S_iiiPi
.size _Z10searchPartPcS_S_iiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Looking for %s in [%s]...\n"
.size .L.str, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10searchPartPcS_S_iiiPi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Notfound"
.size .Lstr, 9
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Found"
.size .Lstr.1, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__searchPartPcS_S_iiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10searchPartPcS_S_iiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "gpuerrchk.cuh"
#include "real.h"
__global__ void ch9_aastrat1_kernel(char* buffer,unsigned int* histo, size_t inputsize){
int i = threadIdx.x + blockIdx.x*blockDim.x;
int section_size = (inputsize-1) / (blockDim.x*gridDim.x) + 1;
int start=i*section_size;
for (int k=0; k< section_size; ++k){
if (start+k < inputsize){
int alphabet_position=buffer[start+k]-'a';
if (alphabet_position >=0 && alphabet_position < 26)
atomicAdd(&histo[alphabet_position/4], 1);
}
}
}
void ch9_aastrat1(char* buffer, unsigned int* histo,size_t inputsize){
ch9_aastrat1_kernel<<<1, 512 >>>(buffer,histo,inputsize);
gpuErrchk(cudaPeekAtLastError());
} | code for sm_80
Function : _Z19ch9_aastrat1_kernelPcPjm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe40000000800 */
/*0050*/ IADD3 R0, P0, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fe20007f1e1ff */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0070*/ IADD3.X R3, R3, -0x1, RZ, P0, !PT ; /* 0xffffffff03037810 */
/* 0x000fc800007fe4ff */
/*0080*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05070 */
/*0090*/ @!P0 BRA 0xd0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, 0xc0 ; /* 0x000000c000027802 */
/* 0x000fe40000000f00 */
/*00b0*/ CALL.REL.NOINC 0xa60 ; /* 0x000009a000007944 */
/* 0x000fea0003c00000 */
/*00c0*/ BRA 0x200 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*00d0*/ I2F.U32.RP R4, UR4 ; /* 0x0000000400047d06 */
/* 0x000e220008209000 */
/*00e0*/ IMAD R5, RZ, RZ, -UR4 ; /* 0x80000004ff057e24 */
/* 0x000fe2000f8e02ff */
/*00f0*/ ISETP.NE.U32.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf45070 */
/*0100*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R5, R5, R3, RZ ; /* 0x0000000305057224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0160*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0180*/ IMAD R0, R5, UR4, R0 ; /* 0x0000000405007c24 */
/* 0x000fca000f8e0200 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*01a0*/ @P0 IADD3 R0, R0, -UR4, RZ ; /* 0x8000000400000c10 */
/* 0x000fe4000fffe0ff */
/*01b0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf26070 */
/*01d0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R3, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff03ac12 */
/* 0x000fca000f8e33ff */
/*01f0*/ IMAD.MOV.U32 R0, RZ, RZ, R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0003 */
/*0200*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0210*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x000fc60007ffe0ff */
/*0220*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0230*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f06270 */
/*0240*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fd800078e0202 */
/*0250*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0260*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*0270*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0280*/ IMAD R0, R5.reuse, R2, RZ ; /* 0x0000000205007224 */
/* 0x040fe200078e02ff */
/*0290*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*02a0*/ LOP3.LUT R4, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305047812 */
/* 0x000fd200078ec0ff */
/*02b0*/ @!P0 BRA 0x880 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.IADD R5, R5, 0x1, -R4 ; /* 0x0000000105057824 */
/* 0x000fe200078e0a04 */
/*02d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*02e0*/ IADD3 R7, R0, UR4, RZ ; /* 0x0000000400077c10 */
/* 0x001fe2000fffe0ff */
/*02f0*/ BSSY B0, 0x530 ; /* 0x0000023000007945 */
/* 0x000fe20003800000 */
/*0300*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe40007ffe0ff */
/*0310*/ IADD3 R3, R7.reuse, 0x2, RZ ; /* 0x0000000207037810 */
/* 0x040fe40007ffe0ff */
/*0320*/ ISETP.GE.U32.AND P3, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe40003f66070 */
/*0330*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe40003f26070 */
/*0340*/ SHF.R.S32.HI R3, RZ, 0x1f, R3 ; /* 0x0000001fff037819 */
/* 0x000fc40000011403 */
/*0350*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.GE.U32.AND.EX P1, PT, R3, c[0x0][0x174], PT, P1 ; /* 0x00005d0003007a0c */
/* 0x000fe40003f26110 */
/*0370*/ SHF.R.S32.HI R3, RZ, 0x1f, R7 ; /* 0x0000001fff037819 */
/* 0x000fe40000011407 */
/*0380*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f06070 */
/*0390*/ ISETP.GE.U32.AND.EX P3, PT, R3, c[0x0][0x174], PT, P3 ; /* 0x00005d0003007a0c */
/* 0x000fe40003f66130 */
/*03a0*/ IADD3 R6, R7, 0x3, RZ ; /* 0x0000000307067810 */
/* 0x000fc40007ffe0ff */
/*03b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R2 ; /* 0x0000001fff027819 */
/* 0x000fe40000011402 */
/*03c0*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f46070 */
/*03d0*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fe40003f06100 */
/*03e0*/ SHF.R.S32.HI R6, RZ, 0x1f, R6 ; /* 0x0000001fff067819 */
/* 0x000fe40000011406 */
/*03f0*/ IADD3 R2, P4, R7, c[0x0][0x160], RZ ; /* 0x0000580007027a10 */
/* 0x000fe40007f9e0ff */
/*0400*/ ISETP.GE.U32.AND.EX P2, PT, R6, c[0x0][0x174], PT, P2 ; /* 0x00005d0006007a0c */
/* 0x000fc40003f46120 */
/*0410*/ ISETP.NE.AND P5, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003fa5270 */
/*0420*/ IADD3.X R3, R3, c[0x0][0x164], RZ, P4, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200027fe4ff */
/*0430*/ @P3 BRA 0x520 ; /* 0x000000e000003947 */
/* 0x000fea0003800000 */
/*0440*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea4000c1e1100 */
/*0450*/ IADD3 R6, R7, -0x61, RZ ; /* 0xffffff9f07067810 */
/* 0x004fc80007ffe0ff */
/*0460*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*0470*/ ISETP.GT.U32.AND P3, PT, R6, 0x19, PT ; /* 0x000000190600780c */
/* 0x000fda0003f64070 */
/*0480*/ @P3 BRA 0x520 ; /* 0x0000009000003947 */
/* 0x000fea0003800000 */
/*0490*/ PRMT R6, R7, 0x8880, RZ ; /* 0x0000888007067816 */
/* 0x000fe200000000ff */
/*04a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fc600078e00ff */
/*04b0*/ IADD3 R6, R6, -0x61, RZ ; /* 0xffffff9f06067810 */
/* 0x000fc80007ffe0ff */
/*04c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fc80000011406 */
/*04d0*/ LEA.HI R7, R7, R6, RZ, 0x2 ; /* 0x0000000607077211 */
/* 0x000fe200078f10ff */
/*04e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc600078e00ff */
/*04f0*/ SHF.R.S32.HI R7, RZ, 0x2, R7 ; /* 0x00000002ff077819 */
/* 0x000fca0000011407 */
/*0500*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fca00078e0206 */
/*0510*/ RED.E.ADD.STRONG.GPU [R6.64], R9 ; /* 0x000000090600798e */
/* 0x0001e4000c10e186 */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ BSSY B0, 0x640 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0540*/ @P0 BRA 0x630 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*0550*/ LDG.E.U8 R7, [R2.64+0x1] ; /* 0x0000010602077981 */
/* 0x001ea4000c1e1100 */
/*0560*/ IADD3 R6, R7, -0x61, RZ ; /* 0xffffff9f07067810 */
/* 0x004fc80007ffe0ff */
/*0570*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*0580*/ ISETP.GT.U32.AND P0, PT, R6, 0x19, PT ; /* 0x000000190600780c */
/* 0x000fda0003f04070 */
/*0590*/ @P0 BRA 0x630 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*05a0*/ PRMT R6, R7, 0x8880, RZ ; /* 0x0000888007067816 */
/* 0x000fe200000000ff */
/*05b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fc600078e00ff */
/*05c0*/ IADD3 R6, R6, -0x61, RZ ; /* 0xffffff9f06067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fc80000011406 */
/*05e0*/ LEA.HI R7, R7, R6, RZ, 0x2 ; /* 0x0000000607077211 */
/* 0x000fe200078f10ff */
/*05f0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc600078e00ff */
/*0600*/ SHF.R.S32.HI R7, RZ, 0x2, R7 ; /* 0x00000002ff077819 */
/* 0x000fca0000011407 */
/*0610*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fca00078e0206 */
/*0620*/ RED.E.ADD.STRONG.GPU [R6.64], R9 ; /* 0x000000090600798e */
/* 0x0001e4000c10e186 */
/*0630*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0640*/ BSSY B0, 0x750 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0650*/ @P1 BRA 0x740 ; /* 0x000000e000001947 */
/* 0x000fea0003800000 */
/*0660*/ LDG.E.U8 R7, [R2.64+0x2] ; /* 0x0000020602077981 */
/* 0x001ea4000c1e1100 */
/*0670*/ IADD3 R6, R7, -0x61, RZ ; /* 0xffffff9f07067810 */
/* 0x004fc80007ffe0ff */
/*0680*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*0690*/ ISETP.GT.U32.AND P0, PT, R6, 0x19, PT ; /* 0x000000190600780c */
/* 0x000fda0003f04070 */
/*06a0*/ @P0 BRA 0x740 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*06b0*/ PRMT R6, R7, 0x8880, RZ ; /* 0x0000888007067816 */
/* 0x000fe200000000ff */
/*06c0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fc600078e00ff */
/*06d0*/ IADD3 R6, R6, -0x61, RZ ; /* 0xffffff9f06067810 */
/* 0x000fc80007ffe0ff */
/*06e0*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fc80000011406 */
/*06f0*/ LEA.HI R7, R7, R6, RZ, 0x2 ; /* 0x0000000607077211 */
/* 0x000fe200078f10ff */
/*0700*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc600078e00ff */
/*0710*/ SHF.R.S32.HI R7, RZ, 0x2, R7 ; /* 0x00000002ff077819 */
/* 0x000fca0000011407 */
/*0720*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fca00078e0206 */
/*0730*/ RED.E.ADD.STRONG.GPU [R6.64], R9 ; /* 0x000000090600798e */
/* 0x0001e4000c10e186 */
/*0740*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0750*/ BSSY B0, 0x860 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0760*/ @P2 BRA 0x850 ; /* 0x000000e000002947 */
/* 0x000fea0003800000 */
/*0770*/ LDG.E.U8 R2, [R2.64+0x3] ; /* 0x0000030602027981 */
/* 0x000ea4000c1e1100 */
/*0780*/ IADD3 R6, R2, -0x61, RZ ; /* 0xffffff9f02067810 */
/* 0x005fc80007ffe0ff */
/*0790*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*07a0*/ ISETP.GT.U32.AND P0, PT, R6, 0x19, PT ; /* 0x000000190600780c */
/* 0x000fda0003f04070 */
/*07b0*/ @P0 BRA 0x850 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*07c0*/ PRMT R2, R2, 0x8880, RZ ; /* 0x0000888002027816 */
/* 0x000fe200000000ff */
/*07d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fc600078e00ff */
/*07e0*/ IADD3 R2, R2, -0x61, RZ ; /* 0xffffff9f02027810 */
/* 0x000fc80007ffe0ff */
/*07f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*0800*/ LEA.HI R3, R3, R2, RZ, 0x2 ; /* 0x0000000203037211 */
/* 0x000fe200078f10ff */
/*0810*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc600078e00ff */
/*0820*/ SHF.R.S32.HI R3, RZ, 0x2, R3 ; /* 0x00000002ff037819 */
/* 0x000fca0000011403 */
/*0830*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0840*/ RED.E.ADD.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x0001e4000c10e186 */
/*0850*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0860*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0870*/ @P5 BRA 0x2e0 ; /* 0xfffffa6000005947 */
/* 0x000fea000383ffff */
/*0880*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0890*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08a0*/ IADD3 R2, R0, UR4, RZ ; /* 0x0000000400027c10 */
/* 0x001fe2000fffe0ff */
/*08b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*08c0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ BSSY B0, 0xa40 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*08e0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f06070 */
/*08f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*0900*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0910*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; /* 0x00005d0003007a0c */
/* 0x000fda0003f06100 */
/*0920*/ @P0 BRA 0xa30 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0930*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc80007f1e0ff */
/*0940*/ IADD3.X R3, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fca00007fe4ff */
/*0950*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1100 */
/*0960*/ IADD3 R5, R2, -0x61, RZ ; /* 0xffffff9f02057810 */
/* 0x004fc80007ffe0ff */
/*0970*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*0980*/ ISETP.GT.U32.AND P0, PT, R5, 0x19, PT ; /* 0x000000190500780c */
/* 0x000fda0003f04070 */
/*0990*/ @P0 BRA 0xa30 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*09a0*/ PRMT R2, R2, 0x8880, RZ ; /* 0x0000888002027816 */
/* 0x000fe200000000ff */
/*09b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*09c0*/ IADD3 R2, R2, -0x61, RZ ; /* 0xffffff9f02027810 */
/* 0x000fc80007ffe0ff */
/*09d0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*09e0*/ LEA.HI R3, R3, R2, RZ, 0x2 ; /* 0x0000000203037211 */
/* 0x000fe200078f10ff */
/*09f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc600078e00ff */
/*0a00*/ SHF.R.S32.HI R3, RZ, 0x2, R3 ; /* 0x00000002ff037819 */
/* 0x000fca0000011403 */
/*0a10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0a20*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e4000c10e186 */
/*0a30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a40*/ @P1 BRA 0x8a0 ; /* 0xfffffe5000001947 */
/* 0x000fea000383ffff */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*0a70*/ I2F.U64.RP R8, UR4 ; /* 0x0000000400087d12 */
/* 0x000e300008309000 */
/*0a80*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0a90*/ IADD3 R4, R8, 0x1ffffffe, RZ ; /* 0x1ffffffe08047810 */
/* 0x001fcc0007ffe0ff */
/*0aa0*/ F2I.U64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x000e24000020d800 */
/*0ab0*/ IMAD.WIDE.U32 R6, R4, UR4, RZ ; /* 0x0000000404067c25 */
/* 0x001fc8000f8e00ff */
/*0ac0*/ IMAD R7, R5, UR4, R7 ; /* 0x0000000405077c24 */
/* 0x000fe2000f8e0207 */
/*0ad0*/ IADD3 R9, P0, RZ, -R6, RZ ; /* 0x80000006ff097210 */
/* 0x000fca0007f1e0ff */
/*0ae0*/ IMAD.HI.U32 R6, R4, R9, RZ ; /* 0x0000000904067227 */
/* 0x000fc800078e00ff */
/*0af0*/ IMAD.X R11, RZ, RZ, ~R7, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe400000e0e07 */
/*0b00*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0004 */
/*0b10*/ IMAD R13, R5, R11.reuse, RZ ; /* 0x0000000b050d7224 */
/* 0x080fe400078e02ff */
/*0b20*/ IMAD.WIDE.U32 R6, P0, R4, R11, R6 ; /* 0x0000000b04067225 */
/* 0x000fc80007800006 */
/*0b30*/ IMAD.HI.U32 R11, R5, R11, RZ ; /* 0x0000000b050b7227 */
/* 0x000fc800078e00ff */
/*0b40*/ IMAD.HI.U32 R6, P1, R5, R9, R6 ; /* 0x0000000905067227 */
/* 0x000fca0007820006 */
/*0b50*/ IADD3 R7, P2, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x000fe20007f5e0ff */
/*0b60*/ IMAD.X R6, R11, 0x1, R5, P0 ; /* 0x000000010b067824 */
/* 0x000fc800000e0605 */
/*0b70*/ IMAD.WIDE.U32 R4, R7, UR4, RZ ; /* 0x0000000407047c25 */
/* 0x000fe2000f8e00ff */
/*0b80*/ IADD3.X R9, RZ, RZ, R6, P2, P1 ; /* 0x000000ffff097210 */
/* 0x000fc800017e2406 */
/*0b90*/ IADD3 R11, P0, RZ, -R4, RZ ; /* 0x80000004ff0b7210 */
/* 0x000fe20007f1e0ff */
/*0ba0*/ IMAD R4, R9, UR4, R5 ; /* 0x0000000409047c24 */
/* 0x000fe4000f8e0205 */
/*0bb0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0bc0*/ IMAD.HI.U32 R6, R7, R11, RZ ; /* 0x0000000b07067227 */
/* 0x000fc800078e00ff */
/*0bd0*/ IMAD.X R4, RZ, RZ, ~R4, P0 ; /* 0x000000ffff047224 */
/* 0x000fc800000e0e04 */
/*0be0*/ IMAD.WIDE.U32 R6, P0, R7, R4, R6 ; /* 0x0000000407067225 */
/* 0x000fc80007800006 */
/*0bf0*/ IMAD R8, R9.reuse, R4, RZ ; /* 0x0000000409087224 */
/* 0x040fe400078e02ff */
/*0c00*/ IMAD.HI.U32 R7, P1, R9, R11, R6 ; /* 0x0000000b09077227 */
/* 0x000fc80007820006 */
/*0c10*/ IMAD.HI.U32 R4, R9, R4, RZ ; /* 0x0000000409047227 */
/* 0x000fe200078e00ff */
/*0c20*/ IADD3 R7, P2, R8, R7, RZ ; /* 0x0000000708077210 */
/* 0x000fc60007f5e0ff */
/*0c30*/ IMAD.X R9, R4, 0x1, R9, P0 ; /* 0x0000000104097824 */
/* 0x000fe400000e0609 */
/*0c40*/ IMAD.HI.U32 R4, R7, R0, RZ ; /* 0x0000000007047227 */
/* 0x000fc600078e00ff */
/*0c50*/ IADD3.X R9, RZ, RZ, R9, P2, P1 ; /* 0x000000ffff097210 */
/* 0x000fc600017e2409 */
/*0c60*/ IMAD.WIDE.U32 R4, R7, R3, R4 ; /* 0x0000000307047225 */
/* 0x000fc800078e0004 */
/*0c70*/ IMAD R7, R9.reuse, R3, RZ ; /* 0x0000000309077224 */
/* 0x040fe400078e02ff */
/*0c80*/ IMAD.HI.U32 R4, P0, R9, R0, R4 ; /* 0x0000000009047227 */
/* 0x000fc80007800004 */
/*0c90*/ IMAD.HI.U32 R9, R9, R3, RZ ; /* 0x0000000309097227 */
/* 0x000fe200078e00ff */
/*0ca0*/ IADD3 R6, P1, R7, R4, RZ ; /* 0x0000000407067210 */
/* 0x000fc60007f3e0ff */
/*0cb0*/ IMAD.X R4, RZ, RZ, R9, P0 ; /* 0x000000ffff047224 */
/* 0x000fc800000e0609 */
/*0cc0*/ IMAD.X R7, RZ, RZ, R4, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0604 */
/*0cd0*/ IMAD.WIDE.U32 R4, R6, UR4, RZ ; /* 0x0000000406047c25 */
/* 0x000fc8000f8e00ff */
/*0ce0*/ IMAD R8, R7, UR4, R5 ; /* 0x0000000407087c24 */
/* 0x000fe2000f8e0205 */
/*0cf0*/ IADD3 R5, P0, -R4, R0, RZ ; /* 0x0000000004057210 */
/* 0x000fc80007f1e1ff */
/*0d00*/ IADD3 R0, P1, R5, -UR4, RZ ; /* 0x8000000405007c10 */
/* 0x000fe2000ff3e0ff */
/*0d10*/ IMAD.X R7, R3, 0x1, ~R8, P0 ; /* 0x0000000103077824 */
/* 0x000fe200000e0e08 */
/*0d20*/ ISETP.GE.U32.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe4000bf06070 */
/*0d30*/ IADD3 R3, R6, 0x1, RZ ; /* 0x0000000106037810 */
/* 0x000fe40007ffe0ff */
/*0d40*/ ISETP.GE.U32.AND.EX P0, PT, R7.reuse, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x040fe40003f06100 */
/*0d50*/ IADD3.X R4, R7, -0x1, RZ, P1, !PT ; /* 0xffffffff07047810 */
/* 0x000fe40000ffe4ff */
/*0d60*/ SEL R0, R0, R5, P0 ; /* 0x0000000500007207 */
/* 0x000fc40000000000 */
/*0d70*/ SEL R4, R4, R7, P0 ; /* 0x0000000704047207 */
/* 0x000fe40000000000 */
/*0d80*/ SEL R3, R3, R6, P0 ; /* 0x0000000603037207 */
/* 0x000fe40000000000 */
/*0d90*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe4000bf06070 */
/*0da0*/ IADD3 R0, R3, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x000fe40007ffe0ff */
/*0db0*/ ISETP.GE.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fe40003f06100 */
/*0dc0*/ ISETP.NE.U32.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc4000bf25070 */
/*0dd0*/ SEL R0, R0, R3, P0 ; /* 0x0000000300007207 */
/* 0x000fe20000000000 */
/*0de0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fe200078e00ff */
/*0df0*/ ISETP.NE.AND.EX P1, PT, RZ, RZ, PT, P1 ; /* 0x000000ffff00720c */
/* 0x000fc80003f25310 */
/*0e00*/ SEL R0, R0, 0xffffffff, P1 ; /* 0xffffffff00007807 */
/* 0x000fe20000800000 */
/*0e10*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff1e002007950 */
/* 0x000ff00003c3ffff */
/*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "gpuerrchk.cuh"
#include "real.h"
__global__ void ch9_aastrat1_kernel(char* buffer,unsigned int* histo, size_t inputsize){
int i = threadIdx.x + blockIdx.x*blockDim.x;
int section_size = (inputsize-1) / (blockDim.x*gridDim.x) + 1;
int start=i*section_size;
for (int k=0; k< section_size; ++k){
if (start+k < inputsize){
int alphabet_position=buffer[start+k]-'a';
if (alphabet_position >=0 && alphabet_position < 26)
atomicAdd(&histo[alphabet_position/4], 1);
}
}
}
void ch9_aastrat1(char* buffer, unsigned int* histo,size_t inputsize){
ch9_aastrat1_kernel<<<1, 512 >>>(buffer,histo,inputsize);
gpuErrchk(cudaPeekAtLastError());
} | .file "tmpxft_00179ef7_00000000-6_ch9_aastrat1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm
.type _Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm, @function
_Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19ch9_aastrat1_kernelPcPjm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm, .-_Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm
.globl _Z19ch9_aastrat1_kernelPcPjm
.type _Z19ch9_aastrat1_kernelPcPjm, @function
_Z19ch9_aastrat1_kernelPcPjm:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z19ch9_aastrat1_kernelPcPjm, .-_Z19ch9_aastrat1_kernelPcPjm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/paiforsyth/cuda_experiments/master/ch9_aastrat1/ch9_aastrat1.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU assert: %s %s %d\n"
.text
.globl _Z12ch9_aastrat1PcPjm
.type _Z12ch9_aastrat1PcPjm, @function
_Z12ch9_aastrat1PcPjm:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaPeekAtLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L16
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $20, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z12ch9_aastrat1PcPjm, .-_Z12ch9_aastrat1PcPjm
.section .rodata.str1.1
.LC2:
.string "_Z19ch9_aastrat1_kernelPcPjm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z19ch9_aastrat1_kernelPcPjm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "gpuerrchk.cuh"
#include "real.h"
__global__ void ch9_aastrat1_kernel(char* buffer,unsigned int* histo, size_t inputsize){
int i = threadIdx.x + blockIdx.x*blockDim.x;
int section_size = (inputsize-1) / (blockDim.x*gridDim.x) + 1;
int start=i*section_size;
for (int k=0; k< section_size; ++k){
if (start+k < inputsize){
int alphabet_position=buffer[start+k]-'a';
if (alphabet_position >=0 && alphabet_position < 26)
atomicAdd(&histo[alphabet_position/4], 1);
}
}
}
void ch9_aastrat1(char* buffer, unsigned int* histo,size_t inputsize){
ch9_aastrat1_kernel<<<1, 512 >>>(buffer,histo,inputsize);
gpuErrchk(cudaPeekAtLastError());
} | #include <hip/hip_runtime.h>
#include "real.h"
void ch9_aastrat1(char* buffer,unsigned int* histo,size_t inputsize); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "real.h"
void ch9_aastrat1(char* buffer,unsigned int* histo,size_t inputsize); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "real.h"
void ch9_aastrat1(char* buffer,unsigned int* histo,size_t inputsize); | .text
.file "ch9_aastrat1.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19ch9_aastrat1_kernelPcPjm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe40000000800 */
/*0050*/ IADD3 R0, P0, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fe20007f1e1ff */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0070*/ IADD3.X R3, R3, -0x1, RZ, P0, !PT ; /* 0xffffffff03037810 */
/* 0x000fc800007fe4ff */
/*0080*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05070 */
/*0090*/ @!P0 BRA 0xd0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, 0xc0 ; /* 0x000000c000027802 */
/* 0x000fe40000000f00 */
/*00b0*/ CALL.REL.NOINC 0xa60 ; /* 0x000009a000007944 */
/* 0x000fea0003c00000 */
/*00c0*/ BRA 0x200 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*00d0*/ I2F.U32.RP R4, UR4 ; /* 0x0000000400047d06 */
/* 0x000e220008209000 */
/*00e0*/ IMAD R5, RZ, RZ, -UR4 ; /* 0x80000004ff057e24 */
/* 0x000fe2000f8e02ff */
/*00f0*/ ISETP.NE.U32.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fcc000bf45070 */
/*0100*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R5, R5, R3, RZ ; /* 0x0000000305057224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0160*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0180*/ IMAD R0, R5, UR4, R0 ; /* 0x0000000405007c24 */
/* 0x000fca000f8e0200 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*01a0*/ @P0 IADD3 R0, R0, -UR4, RZ ; /* 0x8000000400000c10 */
/* 0x000fe4000fffe0ff */
/*01b0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf26070 */
/*01d0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R3, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff03ac12 */
/* 0x000fca000f8e33ff */
/*01f0*/ IMAD.MOV.U32 R0, RZ, RZ, R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0003 */
/*0200*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0210*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x000fc60007ffe0ff */
/*0220*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0230*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f06270 */
/*0240*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fd800078e0202 */
/*0250*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0260*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*0270*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0280*/ IMAD R0, R5.reuse, R2, RZ ; /* 0x0000000205007224 */
/* 0x040fe200078e02ff */
/*0290*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*02a0*/ LOP3.LUT R4, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305047812 */
/* 0x000fd200078ec0ff */
/*02b0*/ @!P0 BRA 0x880 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.IADD R5, R5, 0x1, -R4 ; /* 0x0000000105057824 */
/* 0x000fe200078e0a04 */
/*02d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*02e0*/ IADD3 R7, R0, UR4, RZ ; /* 0x0000000400077c10 */
/* 0x001fe2000fffe0ff */
/*02f0*/ BSSY B0, 0x530 ; /* 0x0000023000007945 */
/* 0x000fe20003800000 */
/*0300*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe40007ffe0ff */
/*0310*/ IADD3 R3, R7.reuse, 0x2, RZ ; /* 0x0000000207037810 */
/* 0x040fe40007ffe0ff */
/*0320*/ ISETP.GE.U32.AND P3, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe40003f66070 */
/*0330*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe40003f26070 */
/*0340*/ SHF.R.S32.HI R3, RZ, 0x1f, R3 ; /* 0x0000001fff037819 */
/* 0x000fc40000011403 */
/*0350*/ IADD3 R2, R7, 0x1, RZ ; /* 0x0000000107027810 */
/* 0x000fe40007ffe0ff */
/*0360*/ ISETP.GE.U32.AND.EX P1, PT, R3, c[0x0][0x174], PT, P1 ; /* 0x00005d0003007a0c */
/* 0x000fe40003f26110 */
/*0370*/ SHF.R.S32.HI R3, RZ, 0x1f, R7 ; /* 0x0000001fff037819 */
/* 0x000fe40000011407 */
/*0380*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f06070 */
/*0390*/ ISETP.GE.U32.AND.EX P3, PT, R3, c[0x0][0x174], PT, P3 ; /* 0x00005d0003007a0c */
/* 0x000fe40003f66130 */
/*03a0*/ IADD3 R6, R7, 0x3, RZ ; /* 0x0000000307067810 */
/* 0x000fc40007ffe0ff */
/*03b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R2 ; /* 0x0000001fff027819 */
/* 0x000fe40000011402 */
/*03c0*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f46070 */
/*03d0*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fe40003f06100 */
/*03e0*/ SHF.R.S32.HI R6, RZ, 0x1f, R6 ; /* 0x0000001fff067819 */
/* 0x000fe40000011406 */
/*03f0*/ IADD3 R2, P4, R7, c[0x0][0x160], RZ ; /* 0x0000580007027a10 */
/* 0x000fe40007f9e0ff */
/*0400*/ ISETP.GE.U32.AND.EX P2, PT, R6, c[0x0][0x174], PT, P2 ; /* 0x00005d0006007a0c */
/* 0x000fc40003f46120 */
/*0410*/ ISETP.NE.AND P5, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003fa5270 */
/*0420*/ IADD3.X R3, R3, c[0x0][0x164], RZ, P4, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200027fe4ff */
/*0430*/ @P3 BRA 0x520 ; /* 0x000000e000003947 */
/* 0x000fea0003800000 */
/*0440*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea4000c1e1100 */
/*0450*/ IADD3 R6, R7, -0x61, RZ ; /* 0xffffff9f07067810 */
/* 0x004fc80007ffe0ff */
/*0460*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*0470*/ ISETP.GT.U32.AND P3, PT, R6, 0x19, PT ; /* 0x000000190600780c */
/* 0x000fda0003f64070 */
/*0480*/ @P3 BRA 0x520 ; /* 0x0000009000003947 */
/* 0x000fea0003800000 */
/*0490*/ PRMT R6, R7, 0x8880, RZ ; /* 0x0000888007067816 */
/* 0x000fe200000000ff */
/*04a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fc600078e00ff */
/*04b0*/ IADD3 R6, R6, -0x61, RZ ; /* 0xffffff9f06067810 */
/* 0x000fc80007ffe0ff */
/*04c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fc80000011406 */
/*04d0*/ LEA.HI R7, R7, R6, RZ, 0x2 ; /* 0x0000000607077211 */
/* 0x000fe200078f10ff */
/*04e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc600078e00ff */
/*04f0*/ SHF.R.S32.HI R7, RZ, 0x2, R7 ; /* 0x00000002ff077819 */
/* 0x000fca0000011407 */
/*0500*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fca00078e0206 */
/*0510*/ RED.E.ADD.STRONG.GPU [R6.64], R9 ; /* 0x000000090600798e */
/* 0x0001e4000c10e186 */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ BSSY B0, 0x640 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0540*/ @P0 BRA 0x630 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*0550*/ LDG.E.U8 R7, [R2.64+0x1] ; /* 0x0000010602077981 */
/* 0x001ea4000c1e1100 */
/*0560*/ IADD3 R6, R7, -0x61, RZ ; /* 0xffffff9f07067810 */
/* 0x004fc80007ffe0ff */
/*0570*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*0580*/ ISETP.GT.U32.AND P0, PT, R6, 0x19, PT ; /* 0x000000190600780c */
/* 0x000fda0003f04070 */
/*0590*/ @P0 BRA 0x630 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*05a0*/ PRMT R6, R7, 0x8880, RZ ; /* 0x0000888007067816 */
/* 0x000fe200000000ff */
/*05b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fc600078e00ff */
/*05c0*/ IADD3 R6, R6, -0x61, RZ ; /* 0xffffff9f06067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fc80000011406 */
/*05e0*/ LEA.HI R7, R7, R6, RZ, 0x2 ; /* 0x0000000607077211 */
/* 0x000fe200078f10ff */
/*05f0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc600078e00ff */
/*0600*/ SHF.R.S32.HI R7, RZ, 0x2, R7 ; /* 0x00000002ff077819 */
/* 0x000fca0000011407 */
/*0610*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fca00078e0206 */
/*0620*/ RED.E.ADD.STRONG.GPU [R6.64], R9 ; /* 0x000000090600798e */
/* 0x0001e4000c10e186 */
/*0630*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0640*/ BSSY B0, 0x750 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0650*/ @P1 BRA 0x740 ; /* 0x000000e000001947 */
/* 0x000fea0003800000 */
/*0660*/ LDG.E.U8 R7, [R2.64+0x2] ; /* 0x0000020602077981 */
/* 0x001ea4000c1e1100 */
/*0670*/ IADD3 R6, R7, -0x61, RZ ; /* 0xffffff9f07067810 */
/* 0x004fc80007ffe0ff */
/*0680*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*0690*/ ISETP.GT.U32.AND P0, PT, R6, 0x19, PT ; /* 0x000000190600780c */
/* 0x000fda0003f04070 */
/*06a0*/ @P0 BRA 0x740 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*06b0*/ PRMT R6, R7, 0x8880, RZ ; /* 0x0000888007067816 */
/* 0x000fe200000000ff */
/*06c0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fc600078e00ff */
/*06d0*/ IADD3 R6, R6, -0x61, RZ ; /* 0xffffff9f06067810 */
/* 0x000fc80007ffe0ff */
/*06e0*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fc80000011406 */
/*06f0*/ LEA.HI R7, R7, R6, RZ, 0x2 ; /* 0x0000000607077211 */
/* 0x000fe200078f10ff */
/*0700*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc600078e00ff */
/*0710*/ SHF.R.S32.HI R7, RZ, 0x2, R7 ; /* 0x00000002ff077819 */
/* 0x000fca0000011407 */
/*0720*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fca00078e0206 */
/*0730*/ RED.E.ADD.STRONG.GPU [R6.64], R9 ; /* 0x000000090600798e */
/* 0x0001e4000c10e186 */
/*0740*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0750*/ BSSY B0, 0x860 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0760*/ @P2 BRA 0x850 ; /* 0x000000e000002947 */
/* 0x000fea0003800000 */
/*0770*/ LDG.E.U8 R2, [R2.64+0x3] ; /* 0x0000030602027981 */
/* 0x000ea4000c1e1100 */
/*0780*/ IADD3 R6, R2, -0x61, RZ ; /* 0xffffff9f02067810 */
/* 0x005fc80007ffe0ff */
/*0790*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*07a0*/ ISETP.GT.U32.AND P0, PT, R6, 0x19, PT ; /* 0x000000190600780c */
/* 0x000fda0003f04070 */
/*07b0*/ @P0 BRA 0x850 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*07c0*/ PRMT R2, R2, 0x8880, RZ ; /* 0x0000888002027816 */
/* 0x000fe200000000ff */
/*07d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fc600078e00ff */
/*07e0*/ IADD3 R2, R2, -0x61, RZ ; /* 0xffffff9f02027810 */
/* 0x000fc80007ffe0ff */
/*07f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*0800*/ LEA.HI R3, R3, R2, RZ, 0x2 ; /* 0x0000000203037211 */
/* 0x000fe200078f10ff */
/*0810*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc600078e00ff */
/*0820*/ SHF.R.S32.HI R3, RZ, 0x2, R3 ; /* 0x00000002ff037819 */
/* 0x000fca0000011403 */
/*0830*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0840*/ RED.E.ADD.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x0001e4000c10e186 */
/*0850*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0860*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0870*/ @P5 BRA 0x2e0 ; /* 0xfffffa6000005947 */
/* 0x000fea000383ffff */
/*0880*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0890*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08a0*/ IADD3 R2, R0, UR4, RZ ; /* 0x0000000400027c10 */
/* 0x001fe2000fffe0ff */
/*08b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*08c0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ BSSY B0, 0xa40 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*08e0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f06070 */
/*08f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*0900*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0910*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; /* 0x00005d0003007a0c */
/* 0x000fda0003f06100 */
/*0920*/ @P0 BRA 0xa30 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0930*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc80007f1e0ff */
/*0940*/ IADD3.X R3, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fca00007fe4ff */
/*0950*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1100 */
/*0960*/ IADD3 R5, R2, -0x61, RZ ; /* 0xffffff9f02057810 */
/* 0x004fc80007ffe0ff */
/*0970*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*0980*/ ISETP.GT.U32.AND P0, PT, R5, 0x19, PT ; /* 0x000000190500780c */
/* 0x000fda0003f04070 */
/*0990*/ @P0 BRA 0xa30 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*09a0*/ PRMT R2, R2, 0x8880, RZ ; /* 0x0000888002027816 */
/* 0x000fe200000000ff */
/*09b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*09c0*/ IADD3 R2, R2, -0x61, RZ ; /* 0xffffff9f02027810 */
/* 0x000fc80007ffe0ff */
/*09d0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*09e0*/ LEA.HI R3, R3, R2, RZ, 0x2 ; /* 0x0000000203037211 */
/* 0x000fe200078f10ff */
/*09f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc600078e00ff */
/*0a00*/ SHF.R.S32.HI R3, RZ, 0x2, R3 ; /* 0x00000002ff037819 */
/* 0x000fca0000011403 */
/*0a10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0a20*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0001e4000c10e186 */
/*0a30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a40*/ @P1 BRA 0x8a0 ; /* 0xfffffe5000001947 */
/* 0x000fea000383ffff */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*0a70*/ I2F.U64.RP R8, UR4 ; /* 0x0000000400087d12 */
/* 0x000e300008309000 */
/*0a80*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0a90*/ IADD3 R4, R8, 0x1ffffffe, RZ ; /* 0x1ffffffe08047810 */
/* 0x001fcc0007ffe0ff */
/*0aa0*/ F2I.U64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x000e24000020d800 */
/*0ab0*/ IMAD.WIDE.U32 R6, R4, UR4, RZ ; /* 0x0000000404067c25 */
/* 0x001fc8000f8e00ff */
/*0ac0*/ IMAD R7, R5, UR4, R7 ; /* 0x0000000405077c24 */
/* 0x000fe2000f8e0207 */
/*0ad0*/ IADD3 R9, P0, RZ, -R6, RZ ; /* 0x80000006ff097210 */
/* 0x000fca0007f1e0ff */
/*0ae0*/ IMAD.HI.U32 R6, R4, R9, RZ ; /* 0x0000000904067227 */
/* 0x000fc800078e00ff */
/*0af0*/ IMAD.X R11, RZ, RZ, ~R7, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe400000e0e07 */
/*0b00*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0004 */
/*0b10*/ IMAD R13, R5, R11.reuse, RZ ; /* 0x0000000b050d7224 */
/* 0x080fe400078e02ff */
/*0b20*/ IMAD.WIDE.U32 R6, P0, R4, R11, R6 ; /* 0x0000000b04067225 */
/* 0x000fc80007800006 */
/*0b30*/ IMAD.HI.U32 R11, R5, R11, RZ ; /* 0x0000000b050b7227 */
/* 0x000fc800078e00ff */
/*0b40*/ IMAD.HI.U32 R6, P1, R5, R9, R6 ; /* 0x0000000905067227 */
/* 0x000fca0007820006 */
/*0b50*/ IADD3 R7, P2, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x000fe20007f5e0ff */
/*0b60*/ IMAD.X R6, R11, 0x1, R5, P0 ; /* 0x000000010b067824 */
/* 0x000fc800000e0605 */
/*0b70*/ IMAD.WIDE.U32 R4, R7, UR4, RZ ; /* 0x0000000407047c25 */
/* 0x000fe2000f8e00ff */
/*0b80*/ IADD3.X R9, RZ, RZ, R6, P2, P1 ; /* 0x000000ffff097210 */
/* 0x000fc800017e2406 */
/*0b90*/ IADD3 R11, P0, RZ, -R4, RZ ; /* 0x80000004ff0b7210 */
/* 0x000fe20007f1e0ff */
/*0ba0*/ IMAD R4, R9, UR4, R5 ; /* 0x0000000409047c24 */
/* 0x000fe4000f8e0205 */
/*0bb0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0bc0*/ IMAD.HI.U32 R6, R7, R11, RZ ; /* 0x0000000b07067227 */
/* 0x000fc800078e00ff */
/*0bd0*/ IMAD.X R4, RZ, RZ, ~R4, P0 ; /* 0x000000ffff047224 */
/* 0x000fc800000e0e04 */
/*0be0*/ IMAD.WIDE.U32 R6, P0, R7, R4, R6 ; /* 0x0000000407067225 */
/* 0x000fc80007800006 */
/*0bf0*/ IMAD R8, R9.reuse, R4, RZ ; /* 0x0000000409087224 */
/* 0x040fe400078e02ff */
/*0c00*/ IMAD.HI.U32 R7, P1, R9, R11, R6 ; /* 0x0000000b09077227 */
/* 0x000fc80007820006 */
/*0c10*/ IMAD.HI.U32 R4, R9, R4, RZ ; /* 0x0000000409047227 */
/* 0x000fe200078e00ff */
/*0c20*/ IADD3 R7, P2, R8, R7, RZ ; /* 0x0000000708077210 */
/* 0x000fc60007f5e0ff */
/*0c30*/ IMAD.X R9, R4, 0x1, R9, P0 ; /* 0x0000000104097824 */
/* 0x000fe400000e0609 */
/*0c40*/ IMAD.HI.U32 R4, R7, R0, RZ ; /* 0x0000000007047227 */
/* 0x000fc600078e00ff */
/*0c50*/ IADD3.X R9, RZ, RZ, R9, P2, P1 ; /* 0x000000ffff097210 */
/* 0x000fc600017e2409 */
/*0c60*/ IMAD.WIDE.U32 R4, R7, R3, R4 ; /* 0x0000000307047225 */
/* 0x000fc800078e0004 */
/*0c70*/ IMAD R7, R9.reuse, R3, RZ ; /* 0x0000000309077224 */
/* 0x040fe400078e02ff */
/*0c80*/ IMAD.HI.U32 R4, P0, R9, R0, R4 ; /* 0x0000000009047227 */
/* 0x000fc80007800004 */
/*0c90*/ IMAD.HI.U32 R9, R9, R3, RZ ; /* 0x0000000309097227 */
/* 0x000fe200078e00ff */
/*0ca0*/ IADD3 R6, P1, R7, R4, RZ ; /* 0x0000000407067210 */
/* 0x000fc60007f3e0ff */
/*0cb0*/ IMAD.X R4, RZ, RZ, R9, P0 ; /* 0x000000ffff047224 */
/* 0x000fc800000e0609 */
/*0cc0*/ IMAD.X R7, RZ, RZ, R4, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0604 */
/*0cd0*/ IMAD.WIDE.U32 R4, R6, UR4, RZ ; /* 0x0000000406047c25 */
/* 0x000fc8000f8e00ff */
/*0ce0*/ IMAD R8, R7, UR4, R5 ; /* 0x0000000407087c24 */
/* 0x000fe2000f8e0205 */
/*0cf0*/ IADD3 R5, P0, -R4, R0, RZ ; /* 0x0000000004057210 */
/* 0x000fc80007f1e1ff */
/*0d00*/ IADD3 R0, P1, R5, -UR4, RZ ; /* 0x8000000405007c10 */
/* 0x000fe2000ff3e0ff */
/*0d10*/ IMAD.X R7, R3, 0x1, ~R8, P0 ; /* 0x0000000103077824 */
/* 0x000fe200000e0e08 */
/*0d20*/ ISETP.GE.U32.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe4000bf06070 */
/*0d30*/ IADD3 R3, R6, 0x1, RZ ; /* 0x0000000106037810 */
/* 0x000fe40007ffe0ff */
/*0d40*/ ISETP.GE.U32.AND.EX P0, PT, R7.reuse, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x040fe40003f06100 */
/*0d50*/ IADD3.X R4, R7, -0x1, RZ, P1, !PT ; /* 0xffffffff07047810 */
/* 0x000fe40000ffe4ff */
/*0d60*/ SEL R0, R0, R5, P0 ; /* 0x0000000500007207 */
/* 0x000fc40000000000 */
/*0d70*/ SEL R4, R4, R7, P0 ; /* 0x0000000704047207 */
/* 0x000fe40000000000 */
/*0d80*/ SEL R3, R3, R6, P0 ; /* 0x0000000603037207 */
/* 0x000fe40000000000 */
/*0d90*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe4000bf06070 */
/*0da0*/ IADD3 R0, R3, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x000fe40007ffe0ff */
/*0db0*/ ISETP.GE.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fe40003f06100 */
/*0dc0*/ ISETP.NE.U32.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc4000bf25070 */
/*0dd0*/ SEL R0, R0, R3, P0 ; /* 0x0000000300007207 */
/* 0x000fe20000000000 */
/*0de0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fe200078e00ff */
/*0df0*/ ISETP.NE.AND.EX P1, PT, RZ, RZ, PT, P1 ; /* 0x000000ffff00720c */
/* 0x000fc80003f25310 */
/*0e00*/ SEL R0, R0, 0xffffffff, P1 ; /* 0xffffffff00007807 */
/* 0x000fe20000800000 */
/*0e10*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff1e002007950 */
/* 0x000ff00003c3ffff */
/*0e20*/ BRA 0xe20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00179ef7_00000000-6_ch9_aastrat1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm
.type _Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm, @function
_Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19ch9_aastrat1_kernelPcPjm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm, .-_Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm
.globl _Z19ch9_aastrat1_kernelPcPjm
.type _Z19ch9_aastrat1_kernelPcPjm, @function
_Z19ch9_aastrat1_kernelPcPjm:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z19ch9_aastrat1_kernelPcPjm, .-_Z19ch9_aastrat1_kernelPcPjm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/paiforsyth/cuda_experiments/master/ch9_aastrat1/ch9_aastrat1.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU assert: %s %s %d\n"
.text
.globl _Z12ch9_aastrat1PcPjm
.type _Z12ch9_aastrat1PcPjm, @function
_Z12ch9_aastrat1PcPjm:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaPeekAtLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L16
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z42__device_stub__Z19ch9_aastrat1_kernelPcPjmPcPjm
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $20, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z12ch9_aastrat1PcPjm, .-_Z12ch9_aastrat1PcPjm
.section .rodata.str1.1
.LC2:
.string "_Z19ch9_aastrat1_kernelPcPjm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z19ch9_aastrat1_kernelPcPjm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ch9_aastrat1.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void histogram_kernel(unsigned int* input, unsigned int* bins, unsigned int num_elements, unsigned int num_bins){
extern __shared__ unsigned int bins_s[];
//Shared Memory
int thid = threadIdx.x;
while(thid < num_bins){
bins_s[thid] = 0u;
thid += blockDim.x;
}
__syncthreads();
//Histogram calculation
unsigned int element = blockIdx.x * blockDim.x + threadIdx.x;
while(element < num_elements){
atomicAdd(&(bins_s[input[element]]), 1);
element += blockDim.x * gridDim.x;
}
__syncthreads();
//Global Memory
thid = threadIdx.x;
while(thid < num_bins){
atomicAdd(&(bins[thid]), bins_s[thid]);
thid += blockDim.x;
}
} | code for sm_80
Function : _Z16histogram_kernelPjS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0xe0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x001fe20003f26070 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fce0003f06070 */
/*0070*/ @P1 BRA 0xd0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0000 */
/*0090*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0001e40000004800 */
/*00a0*/ IADD3 R2, R2, c[0x0][0x0], RZ ; /* 0x0000000002027a10 */
/* 0x001fc80007ffe0ff */
/*00b0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fda0003f26070 */
/*00c0*/ @!P1 BRA 0x90 ; /* 0xffffffc000009947 */
/* 0x000fea000383ffff */
/*00d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ @P0 BRA 0x1b0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0003 */
/*0120*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0130*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e0003 */
/*0140*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe200078e00ff */
/*0160*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe60003800000 */
/*0170*/ IMAD R4, R5, c[0x0][0xc], R4 ; /* 0x0000030005047a24 */
/* 0x000fca00078e0204 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe20003f06070 */
/*0190*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*01a0*/ @!P0 BRA 0x120 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*01b0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fc80000000f00 */
/*0200*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x0012a20000004800 */
/*0210*/ IMAD.WIDE R2, R0.reuse, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x041fe200078e0207 */
/*0220*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0230*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x002fc80007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06070 */
/*0250*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0041d8000c10e184 */
/*0260*/ @!P0 BRA 0x200 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void histogram_kernel(unsigned int* input, unsigned int* bins, unsigned int num_elements, unsigned int num_bins){
extern __shared__ unsigned int bins_s[];
//Shared Memory
int thid = threadIdx.x;
while(thid < num_bins){
bins_s[thid] = 0u;
thid += blockDim.x;
}
__syncthreads();
//Histogram calculation
unsigned int element = blockIdx.x * blockDim.x + threadIdx.x;
while(element < num_elements){
atomicAdd(&(bins_s[input[element]]), 1);
element += blockDim.x * gridDim.x;
}
__syncthreads();
//Global Memory
thid = threadIdx.x;
while(thid < num_bins){
atomicAdd(&(bins[thid]), bins_s[thid]);
thid += blockDim.x;
}
} | .file "tmpxft_00041d64_00000000-6_histogram_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z16histogram_kernelPjS_jjPjS_jj
.type _Z40__device_stub__Z16histogram_kernelPjS_jjPjS_jj, @function
_Z40__device_stub__Z16histogram_kernelPjS_jjPjS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16histogram_kernelPjS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z16histogram_kernelPjS_jjPjS_jj, .-_Z40__device_stub__Z16histogram_kernelPjS_jjPjS_jj
.globl _Z16histogram_kernelPjS_jj
.type _Z16histogram_kernelPjS_jj, @function
_Z16histogram_kernelPjS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16histogram_kernelPjS_jjPjS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16histogram_kernelPjS_jj, .-_Z16histogram_kernelPjS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16histogram_kernelPjS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16histogram_kernelPjS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void histogram_kernel(unsigned int* input, unsigned int* bins, unsigned int num_elements, unsigned int num_bins){
extern __shared__ unsigned int bins_s[];
//Shared Memory
int thid = threadIdx.x;
while(thid < num_bins){
bins_s[thid] = 0u;
thid += blockDim.x;
}
__syncthreads();
//Histogram calculation
unsigned int element = blockIdx.x * blockDim.x + threadIdx.x;
while(element < num_elements){
atomicAdd(&(bins_s[input[element]]), 1);
element += blockDim.x * gridDim.x;
}
__syncthreads();
//Global Memory
thid = threadIdx.x;
while(thid < num_bins){
atomicAdd(&(bins[thid]), bins_s[thid]);
thid += blockDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histogram_kernel(unsigned int* input, unsigned int* bins, unsigned int num_elements, unsigned int num_bins){
extern __shared__ unsigned int bins_s[];
//Shared Memory
int thid = threadIdx.x;
while(thid < num_bins){
bins_s[thid] = 0u;
thid += blockDim.x;
}
__syncthreads();
//Histogram calculation
unsigned int element = blockIdx.x * blockDim.x + threadIdx.x;
while(element < num_elements){
atomicAdd(&(bins_s[input[element]]), 1);
element += blockDim.x * gridDim.x;
}
__syncthreads();
//Global Memory
thid = threadIdx.x;
while(thid < num_bins){
atomicAdd(&(bins[thid]), bins_s[thid]);
thid += blockDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histogram_kernel(unsigned int* input, unsigned int* bins, unsigned int num_elements, unsigned int num_bins){
extern __shared__ unsigned int bins_s[];
//Shared Memory
int thid = threadIdx.x;
while(thid < num_bins){
bins_s[thid] = 0u;
thid += blockDim.x;
}
__syncthreads();
//Histogram calculation
unsigned int element = blockIdx.x * blockDim.x + threadIdx.x;
while(element < num_elements){
atomicAdd(&(bins_s[input[element]]), 1);
element += blockDim.x * gridDim.x;
}
__syncthreads();
//Global Memory
thid = threadIdx.x;
while(thid < num_bins){
atomicAdd(&(bins[thid]), bins_s[thid]);
thid += blockDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16histogram_kernelPjS_jj
.globl _Z16histogram_kernelPjS_jj
.p2align 8
.type _Z16histogram_kernelPjS_jj,@function
_Z16histogram_kernelPjS_jj:
s_load_b32 s4, s[0:1], 0x14
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_3
s_load_b32 s3, s[0:1], 0x24
v_lshl_add_u32 v1, v0, 2, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s6, s3, 2
.LBB0_2:
v_add_nc_u32_e32 v3, s3, v3
ds_store_b32 v1, v2
v_add_nc_u32_e32 v1, s6, v1
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_6
s_load_b32 s8, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 1
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s8, s5
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v1
global_load_b32 v4, v[4:5], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_lshl_add_u32 v4, v4, 2, 0
ds_add_u32 v4, v3
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x8
v_lshl_add_u32 v2, v0, 2, 0
s_mov_b32 s2, 0
s_lshl_b32 s3, s5, 2
.LBB0_8:
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s5, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v0
global_atomic_add_u32 v[3:4], v5, off
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_8
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16histogram_kernelPjS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16histogram_kernelPjS_jj, .Lfunc_end0-_Z16histogram_kernelPjS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym bins_s
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16histogram_kernelPjS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16histogram_kernelPjS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histogram_kernel(unsigned int* input, unsigned int* bins, unsigned int num_elements, unsigned int num_bins){
extern __shared__ unsigned int bins_s[];
//Shared Memory
int thid = threadIdx.x;
while(thid < num_bins){
bins_s[thid] = 0u;
thid += blockDim.x;
}
__syncthreads();
//Histogram calculation
unsigned int element = blockIdx.x * blockDim.x + threadIdx.x;
while(element < num_elements){
atomicAdd(&(bins_s[input[element]]), 1);
element += blockDim.x * gridDim.x;
}
__syncthreads();
//Global Memory
thid = threadIdx.x;
while(thid < num_bins){
atomicAdd(&(bins[thid]), bins_s[thid]);
thid += blockDim.x;
}
} | .text
.file "histogram_kernel.hip"
.globl _Z31__device_stub__histogram_kernelPjS_jj # -- Begin function _Z31__device_stub__histogram_kernelPjS_jj
.p2align 4, 0x90
.type _Z31__device_stub__histogram_kernelPjS_jj,@function
_Z31__device_stub__histogram_kernelPjS_jj: # @_Z31__device_stub__histogram_kernelPjS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16histogram_kernelPjS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__histogram_kernelPjS_jj, .Lfunc_end0-_Z31__device_stub__histogram_kernelPjS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16histogram_kernelPjS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16histogram_kernelPjS_jj,@object # @_Z16histogram_kernelPjS_jj
.section .rodata,"a",@progbits
.globl _Z16histogram_kernelPjS_jj
.p2align 3, 0x0
_Z16histogram_kernelPjS_jj:
.quad _Z31__device_stub__histogram_kernelPjS_jj
.size _Z16histogram_kernelPjS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16histogram_kernelPjS_jj"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__histogram_kernelPjS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16histogram_kernelPjS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16histogram_kernelPjS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0xe0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x001fe20003f26070 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fce0003f06070 */
/*0070*/ @P1 BRA 0xd0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0000 */
/*0090*/ STS [R2.X4], RZ ; /* 0x000000ff02007388 */
/* 0x0001e40000004800 */
/*00a0*/ IADD3 R2, R2, c[0x0][0x0], RZ ; /* 0x0000000002027a10 */
/* 0x001fc80007ffe0ff */
/*00b0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fda0003f26070 */
/*00c0*/ @!P1 BRA 0x90 ; /* 0xffffffc000009947 */
/* 0x000fea000383ffff */
/*00d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ @P0 BRA 0x1b0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0003 */
/*0120*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0130*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e0003 */
/*0140*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe200078e00ff */
/*0160*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe60003800000 */
/*0170*/ IMAD R4, R5, c[0x0][0xc], R4 ; /* 0x0000030005047a24 */
/* 0x000fca00078e0204 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe20003f06070 */
/*0190*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*01a0*/ @!P0 BRA 0x120 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*01b0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fc80000000f00 */
/*0200*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x0012a20000004800 */
/*0210*/ IMAD.WIDE R2, R0.reuse, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x041fe200078e0207 */
/*0220*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0230*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x002fc80007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06070 */
/*0250*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0041d8000c10e184 */
/*0260*/ @!P0 BRA 0x200 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16histogram_kernelPjS_jj
.globl _Z16histogram_kernelPjS_jj
.p2align 8
.type _Z16histogram_kernelPjS_jj,@function
_Z16histogram_kernelPjS_jj:
s_load_b32 s4, s[0:1], 0x14
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_3
s_load_b32 s3, s[0:1], 0x24
v_lshl_add_u32 v1, v0, 2, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s6, s3, 2
.LBB0_2:
v_add_nc_u32_e32 v3, s3, v3
ds_store_b32 v1, v2
v_add_nc_u32_e32 v1, s6, v1
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_6
s_load_b32 s8, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 1
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s8, s5
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v1
global_load_b32 v4, v[4:5], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_lshl_add_u32 v4, v4, 2, 0
ds_add_u32 v4, v3
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x8
v_lshl_add_u32 v2, v0, 2, 0
s_mov_b32 s2, 0
s_lshl_b32 s3, s5, 2
.LBB0_8:
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s5, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v0
global_atomic_add_u32 v[3:4], v5, off
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_8
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16histogram_kernelPjS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16histogram_kernelPjS_jj, .Lfunc_end0-_Z16histogram_kernelPjS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym bins_s
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16histogram_kernelPjS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16histogram_kernelPjS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00041d64_00000000-6_histogram_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z16histogram_kernelPjS_jjPjS_jj
.type _Z40__device_stub__Z16histogram_kernelPjS_jjPjS_jj, @function
_Z40__device_stub__Z16histogram_kernelPjS_jjPjS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16histogram_kernelPjS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z16histogram_kernelPjS_jjPjS_jj, .-_Z40__device_stub__Z16histogram_kernelPjS_jjPjS_jj
.globl _Z16histogram_kernelPjS_jj
.type _Z16histogram_kernelPjS_jj, @function
_Z16histogram_kernelPjS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16histogram_kernelPjS_jjPjS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16histogram_kernelPjS_jj, .-_Z16histogram_kernelPjS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16histogram_kernelPjS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16histogram_kernelPjS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "histogram_kernel.hip"
.globl _Z31__device_stub__histogram_kernelPjS_jj # -- Begin function _Z31__device_stub__histogram_kernelPjS_jj
.p2align 4, 0x90
.type _Z31__device_stub__histogram_kernelPjS_jj,@function
_Z31__device_stub__histogram_kernelPjS_jj: # @_Z31__device_stub__histogram_kernelPjS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16histogram_kernelPjS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__histogram_kernelPjS_jj, .Lfunc_end0-_Z31__device_stub__histogram_kernelPjS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16histogram_kernelPjS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16histogram_kernelPjS_jj,@object # @_Z16histogram_kernelPjS_jj
.section .rodata,"a",@progbits
.globl _Z16histogram_kernelPjS_jj
.p2align 3, 0x0
_Z16histogram_kernelPjS_jj:
.quad _Z31__device_stub__histogram_kernelPjS_jj
.size _Z16histogram_kernelPjS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16histogram_kernelPjS_jj"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__histogram_kernelPjS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16histogram_kernelPjS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
//#define NUMS 64
//#define num_size 8
//#define NUM 49
#define local_1(NUMS) \
__global__ void local_1_##NUMS(float *a) \
{\
float tmp[NUMS];\
int i;\
for(i=0;i<NUMS;i++)\
{\
tmp[i]=a[i];\
}\
for(i=0;i<NUMS;i++)\
{\
a[i]+=tmp[i];\
}\
}
//local_1(29) //sm_10
//local_1(30)
//local_1(73) //sm_35
//local_1(74)
#define local_2(num_size) \
__global__ void local_2_##num_size(float *a,float *b,float *c)\
{\
float tmp_a[num_size*num_size];\
float temp;\
int i,j,k;\
for (i=0;i<num_size*num_size;i++)\
{\
tmp_a[i]=a[i];\
}\
for (i=0;i<num_size;i++)\
{\
for (j=0;j<num_size;j++)\
{\
temp=0.0;\
for (k=0;k<num_size;k++)\
{\
temp+=tmp_a[i*num_size+k]*b[k*num_size+j];\
}\
c[i*num_size+j]=temp;\
}\
}\
}
//local_2(2) //sm_10
//local_2(3)
//local_2(4)
//local_2(5)
//local_2(6) //sm_35
//local_2(7)
//local_2(8)
//local_2(9)
#define local_3(NUM) \
__global__ void local_3_##NUM(float *a)\
{\
float tmp[NUM];\
float minf=0.0,temp;\
int mind;\
int i,j;\
for(i=0;i<NUM;i++)\
{\
tmp[i]=a[i];\
}\
for(i=0;i<NUM;i++)\
{\
minf=tmp[i];\
mind=i;\
for (j=i;j<NUM;j++)\
{\
if (minf>tmp[j])\
{\
minf=tmp[j];\
mind=i;\
} \
}\
if (mind!=i)\
{\
temp=tmp[i];\
tmp[i]=tmp[mind];\
tmp[mind]=temp;\
}\
}\
a[0]=tmp[NUM-1];\
}
//sm_10
local_3(2)
local_3(4)
local_3(8)
local_3(16)
local_3(32)
local_3(64)
local_3(128) | code for sm_80
Function : _Z11local_3_128Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0x1fc] ; /* 0x0001fc0402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10local_3_64Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0xfc] ; /* 0x0000fc0402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10local_3_32Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0x7c] ; /* 0x00007c0402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10local_3_16Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0x3c] ; /* 0x00003c0402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9local_3_8Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0x1c] ; /* 0x00001c0402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9local_3_4Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0xc] ; /* 0x00000c0402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9local_3_2Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
//#define NUMS 64
//#define num_size 8
//#define NUM 49
#define local_1(NUMS) \
__global__ void local_1_##NUMS(float *a) \
{\
float tmp[NUMS];\
int i;\
for(i=0;i<NUMS;i++)\
{\
tmp[i]=a[i];\
}\
for(i=0;i<NUMS;i++)\
{\
a[i]+=tmp[i];\
}\
}
//local_1(29) //sm_10
//local_1(30)
//local_1(73) //sm_35
//local_1(74)
#define local_2(num_size) \
__global__ void local_2_##num_size(float *a,float *b,float *c)\
{\
float tmp_a[num_size*num_size];\
float temp;\
int i,j,k;\
for (i=0;i<num_size*num_size;i++)\
{\
tmp_a[i]=a[i];\
}\
for (i=0;i<num_size;i++)\
{\
for (j=0;j<num_size;j++)\
{\
temp=0.0;\
for (k=0;k<num_size;k++)\
{\
temp+=tmp_a[i*num_size+k]*b[k*num_size+j];\
}\
c[i*num_size+j]=temp;\
}\
}\
}
//local_2(2) //sm_10
//local_2(3)
//local_2(4)
//local_2(5)
//local_2(6) //sm_35
//local_2(7)
//local_2(8)
//local_2(9)
#define local_3(NUM) \
__global__ void local_3_##NUM(float *a)\
{\
float tmp[NUM];\
float minf=0.0,temp;\
int mind;\
int i,j;\
for(i=0;i<NUM;i++)\
{\
tmp[i]=a[i];\
}\
for(i=0;i<NUM;i++)\
{\
minf=tmp[i];\
mind=i;\
for (j=i;j<NUM;j++)\
{\
if (minf>tmp[j])\
{\
minf=tmp[j];\
mind=i;\
} \
}\
if (mind!=i)\
{\
temp=tmp[i];\
tmp[i]=tmp[mind];\
tmp[mind]=temp;\
}\
}\
a[0]=tmp[NUM-1];\
}
//sm_10
local_3(2)
local_3(4)
local_3(8)
local_3(16)
local_3(32)
local_3(64)
local_3(128) | .file "tmpxft_000fdb10_00000000-6_local2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z9local_3_2PfPf
.type _Z28__device_stub__Z9local_3_2PfPf, @function
_Z28__device_stub__Z9local_3_2PfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9local_3_2Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z9local_3_2PfPf, .-_Z28__device_stub__Z9local_3_2PfPf
.globl _Z9local_3_2Pf
.type _Z9local_3_2Pf, @function
_Z9local_3_2Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9local_3_2PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9local_3_2Pf, .-_Z9local_3_2Pf
.globl _Z28__device_stub__Z9local_3_4PfPf
.type _Z28__device_stub__Z9local_3_4PfPf, @function
_Z28__device_stub__Z9local_3_4PfPf:
.LFB2053:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9local_3_4Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z28__device_stub__Z9local_3_4PfPf, .-_Z28__device_stub__Z9local_3_4PfPf
.globl _Z9local_3_4Pf
.type _Z9local_3_4Pf, @function
_Z9local_3_4Pf:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9local_3_4PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z9local_3_4Pf, .-_Z9local_3_4Pf
.globl _Z28__device_stub__Z9local_3_8PfPf
.type _Z28__device_stub__Z9local_3_8PfPf, @function
_Z28__device_stub__Z9local_3_8PfPf:
.LFB2055:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9local_3_8Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z28__device_stub__Z9local_3_8PfPf, .-_Z28__device_stub__Z9local_3_8PfPf
.globl _Z9local_3_8Pf
.type _Z9local_3_8Pf, @function
_Z9local_3_8Pf:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9local_3_8PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z9local_3_8Pf, .-_Z9local_3_8Pf
.globl _Z30__device_stub__Z10local_3_16PfPf
.type _Z30__device_stub__Z10local_3_16PfPf, @function
_Z30__device_stub__Z10local_3_16PfPf:
.LFB2057:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10local_3_16Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z30__device_stub__Z10local_3_16PfPf, .-_Z30__device_stub__Z10local_3_16PfPf
.globl _Z10local_3_16Pf
.type _Z10local_3_16Pf, @function
_Z10local_3_16Pf:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10local_3_16PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10local_3_16Pf, .-_Z10local_3_16Pf
.globl _Z30__device_stub__Z10local_3_32PfPf
.type _Z30__device_stub__Z10local_3_32PfPf, @function
_Z30__device_stub__Z10local_3_32PfPf:
.LFB2059:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10local_3_32Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z30__device_stub__Z10local_3_32PfPf, .-_Z30__device_stub__Z10local_3_32PfPf
.globl _Z10local_3_32Pf
.type _Z10local_3_32Pf, @function
_Z10local_3_32Pf:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10local_3_32PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z10local_3_32Pf, .-_Z10local_3_32Pf
.globl _Z30__device_stub__Z10local_3_64PfPf
.type _Z30__device_stub__Z10local_3_64PfPf, @function
_Z30__device_stub__Z10local_3_64PfPf:
.LFB2061:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10local_3_64Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z30__device_stub__Z10local_3_64PfPf, .-_Z30__device_stub__Z10local_3_64PfPf
.globl _Z10local_3_64Pf
.type _Z10local_3_64Pf, @function
_Z10local_3_64Pf:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10local_3_64PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z10local_3_64Pf, .-_Z10local_3_64Pf
.globl _Z31__device_stub__Z11local_3_128PfPf
.type _Z31__device_stub__Z11local_3_128PfPf, @function
_Z31__device_stub__Z11local_3_128PfPf:
.LFB2063:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11local_3_128Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z31__device_stub__Z11local_3_128PfPf, .-_Z31__device_stub__Z11local_3_128PfPf
.globl _Z11local_3_128Pf
.type _Z11local_3_128Pf, @function
_Z11local_3_128Pf:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11local_3_128PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z11local_3_128Pf, .-_Z11local_3_128Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11local_3_128Pf"
.LC1:
.string "_Z10local_3_64Pf"
.LC2:
.string "_Z10local_3_32Pf"
.LC3:
.string "_Z10local_3_16Pf"
.LC4:
.string "_Z9local_3_8Pf"
.LC5:
.string "_Z9local_3_4Pf"
.LC6:
.string "_Z9local_3_2Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2066:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11local_3_128Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10local_3_64Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10local_3_32Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10local_3_16Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9local_3_8Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9local_3_4Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9local_3_2Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
//#define NUMS 64
//#define num_size 8
//#define NUM 49
#define local_1(NUMS) \
__global__ void local_1_##NUMS(float *a) \
{\
float tmp[NUMS];\
int i;\
for(i=0;i<NUMS;i++)\
{\
tmp[i]=a[i];\
}\
for(i=0;i<NUMS;i++)\
{\
a[i]+=tmp[i];\
}\
}
//local_1(29) //sm_10
//local_1(30)
//local_1(73) //sm_35
//local_1(74)
#define local_2(num_size) \
__global__ void local_2_##num_size(float *a,float *b,float *c)\
{\
float tmp_a[num_size*num_size];\
float temp;\
int i,j,k;\
for (i=0;i<num_size*num_size;i++)\
{\
tmp_a[i]=a[i];\
}\
for (i=0;i<num_size;i++)\
{\
for (j=0;j<num_size;j++)\
{\
temp=0.0;\
for (k=0;k<num_size;k++)\
{\
temp+=tmp_a[i*num_size+k]*b[k*num_size+j];\
}\
c[i*num_size+j]=temp;\
}\
}\
}
//local_2(2) //sm_10
//local_2(3)
//local_2(4)
//local_2(5)
//local_2(6) //sm_35
//local_2(7)
//local_2(8)
//local_2(9)
#define local_3(NUM) \
__global__ void local_3_##NUM(float *a)\
{\
float tmp[NUM];\
float minf=0.0,temp;\
int mind;\
int i,j;\
for(i=0;i<NUM;i++)\
{\
tmp[i]=a[i];\
}\
for(i=0;i<NUM;i++)\
{\
minf=tmp[i];\
mind=i;\
for (j=i;j<NUM;j++)\
{\
if (minf>tmp[j])\
{\
minf=tmp[j];\
mind=i;\
} \
}\
if (mind!=i)\
{\
temp=tmp[i];\
tmp[i]=tmp[mind];\
tmp[mind]=temp;\
}\
}\
a[0]=tmp[NUM-1];\
}
//sm_10
local_3(2)
local_3(4)
local_3(8)
local_3(16)
local_3(32)
local_3(64)
local_3(128) | #include <hip/hip_runtime.h>
//#define NUMS 64
//#define num_size 8
//#define NUM 49
#define local_1(NUMS) \
__global__ void local_1_##NUMS(float *a) \
{\
float tmp[NUMS];\
int i;\
for(i=0;i<NUMS;i++)\
{\
tmp[i]=a[i];\
}\
for(i=0;i<NUMS;i++)\
{\
a[i]+=tmp[i];\
}\
}
//local_1(29) //sm_10
//local_1(30)
//local_1(73) //sm_35
//local_1(74)
#define local_2(num_size) \
__global__ void local_2_##num_size(float *a,float *b,float *c)\
{\
float tmp_a[num_size*num_size];\
float temp;\
int i,j,k;\
for (i=0;i<num_size*num_size;i++)\
{\
tmp_a[i]=a[i];\
}\
for (i=0;i<num_size;i++)\
{\
for (j=0;j<num_size;j++)\
{\
temp=0.0;\
for (k=0;k<num_size;k++)\
{\
temp+=tmp_a[i*num_size+k]*b[k*num_size+j];\
}\
c[i*num_size+j]=temp;\
}\
}\
}
//local_2(2) //sm_10
//local_2(3)
//local_2(4)
//local_2(5)
//local_2(6) //sm_35
//local_2(7)
//local_2(8)
//local_2(9)
#define local_3(NUM) \
__global__ void local_3_##NUM(float *a)\
{\
float tmp[NUM];\
float minf=0.0,temp;\
int mind;\
int i,j;\
for(i=0;i<NUM;i++)\
{\
tmp[i]=a[i];\
}\
for(i=0;i<NUM;i++)\
{\
minf=tmp[i];\
mind=i;\
for (j=i;j<NUM;j++)\
{\
if (minf>tmp[j])\
{\
minf=tmp[j];\
mind=i;\
} \
}\
if (mind!=i)\
{\
temp=tmp[i];\
tmp[i]=tmp[mind];\
tmp[mind]=temp;\
}\
}\
a[0]=tmp[NUM-1];\
}
//sm_10
local_3(2)
local_3(4)
local_3(8)
local_3(16)
local_3(32)
local_3(64)
local_3(128) |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#define NUMS 64
//#define num_size 8
//#define NUM 49
#define local_1(NUMS) \
__global__ void local_1_##NUMS(float *a) \
{\
float tmp[NUMS];\
int i;\
for(i=0;i<NUMS;i++)\
{\
tmp[i]=a[i];\
}\
for(i=0;i<NUMS;i++)\
{\
a[i]+=tmp[i];\
}\
}
//local_1(29) //sm_10
//local_1(30)
//local_1(73) //sm_35
//local_1(74)
#define local_2(num_size) \
__global__ void local_2_##num_size(float *a,float *b,float *c)\
{\
float tmp_a[num_size*num_size];\
float temp;\
int i,j,k;\
for (i=0;i<num_size*num_size;i++)\
{\
tmp_a[i]=a[i];\
}\
for (i=0;i<num_size;i++)\
{\
for (j=0;j<num_size;j++)\
{\
temp=0.0;\
for (k=0;k<num_size;k++)\
{\
temp+=tmp_a[i*num_size+k]*b[k*num_size+j];\
}\
c[i*num_size+j]=temp;\
}\
}\
}
//local_2(2) //sm_10
//local_2(3)
//local_2(4)
//local_2(5)
//local_2(6) //sm_35
//local_2(7)
//local_2(8)
//local_2(9)
#define local_3(NUM) \
__global__ void local_3_##NUM(float *a)\
{\
float tmp[NUM];\
float minf=0.0,temp;\
int mind;\
int i,j;\
for(i=0;i<NUM;i++)\
{\
tmp[i]=a[i];\
}\
for(i=0;i<NUM;i++)\
{\
minf=tmp[i];\
mind=i;\
for (j=i;j<NUM;j++)\
{\
if (minf>tmp[j])\
{\
minf=tmp[j];\
mind=i;\
} \
}\
if (mind!=i)\
{\
temp=tmp[i];\
tmp[i]=tmp[mind];\
tmp[mind]=temp;\
}\
}\
a[0]=tmp[NUM-1];\
}
//sm_10
local_3(2)
local_3(4)
local_3(8)
local_3(16)
local_3(32)
local_3(64)
local_3(128) | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9local_3_2Pf
.globl _Z9local_3_2Pf
.p2align 8
.type _Z9local_3_2Pf,@function
_Z9local_3_2Pf:
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[4:5], s[0:1]
.LBB0_1:
s_load_b32 s6, s[4:5], 0x0
s_cmp_eq_u32 s2, 1
s_cselect_b32 s7, -1, 0
s_cmp_eq_u32 s2, 0
s_cselect_b32 s8, -1, 0
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s2, 1
s_waitcnt lgkmcnt(0)
v_cndmask_b32_e64 v0, v0, s6, s7
v_cndmask_b32_e64 v1, v1, s6, s8
s_cbranch_scc1 .LBB0_1
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9local_3_2Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 9
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9local_3_2Pf, .Lfunc_end0-_Z9local_3_2Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9local_3_4Pf
.globl _Z9local_3_4Pf
.p2align 8
.type _Z9local_3_4Pf,@function
_Z9local_3_4Pf:
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[4:5], s[0:1]
.p2align 6
.LBB1_1:
s_load_b32 s6, s[4:5], 0x0
s_cmp_eq_u32 s2, 3
s_cselect_b32 s7, -1, 0
s_cmp_eq_u32 s2, 2
s_cselect_b32 s8, -1, 0
s_cmp_eq_u32 s2, 1
s_cselect_b32 s9, -1, 0
s_cmp_eq_u32 s2, 0
s_cselect_b32 s10, -1, 0
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s2, 4
s_waitcnt lgkmcnt(0)
v_cndmask_b32_e64 v1, v1, s6, s7
v_cndmask_b32_e64 v3, v3, s6, s8
v_cndmask_b32_e64 v2, v2, s6, s9
v_cndmask_b32_e64 v0, v0, s6, s10
s_cbranch_scc1 .LBB1_1
v_mov_b32_e32 v0, 0
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9local_3_4Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 11
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9local_3_4Pf, .Lfunc_end1-_Z9local_3_4Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9local_3_8Pf
.globl _Z9local_3_8Pf
.p2align 8
.type _Z9local_3_8Pf,@function
_Z9local_3_8Pf:
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[4:5], s[0:1]
.LBB2_1:
s_load_b32 s6, s[4:5], 0x0
s_mov_b32 m0, s2
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s2, 8
s_waitcnt lgkmcnt(0)
v_movreld_b32_e32 v0, s6
s_cbranch_scc1 .LBB2_1
v_mov_b32_e32 v0, 0
global_store_b32 v0, v7, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9local_3_8Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z9local_3_8Pf, .Lfunc_end2-_Z9local_3_8Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10local_3_16Pf
.globl _Z10local_3_16Pf
.p2align 8
.type _Z10local_3_16Pf,@function
_Z10local_3_16Pf:
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[4:5], s[0:1]
.LBB3_1:
s_load_b32 s6, s[4:5], 0x0
s_mov_b32 m0, s2
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s2, 16
s_waitcnt lgkmcnt(0)
v_movreld_b32_e32 v0, s6
s_cbranch_scc1 .LBB3_1
v_mov_b32_e32 v0, 0
global_store_b32 v0, v15, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10local_3_16Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z10local_3_16Pf, .Lfunc_end3-_Z10local_3_16Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10local_3_32Pf
.globl _Z10local_3_32Pf
.p2align 8
.type _Z10local_3_32Pf,@function
_Z10local_3_32Pf:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 16
s_mov_b64 s[2:3], 0
.LBB4_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
s_add_u32 s2, s2, 4
s_load_b32 s4, s[4:5], 0x0
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x80
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s4
scratch_store_b32 v0, v1, off
v_add_nc_u32_e32 v0, 4, v0
s_cbranch_scc1 .LBB4_1
scratch_load_b32 v0, off, off offset:140
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10local_3_32Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 144
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z10local_3_32Pf, .Lfunc_end4-_Z10local_3_32Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10local_3_64Pf
.globl _Z10local_3_64Pf
.p2align 8
.type _Z10local_3_64Pf,@function
_Z10local_3_64Pf:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 16
s_mov_b64 s[2:3], 0
.LBB5_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
s_add_u32 s2, s2, 4
s_load_b32 s4, s[4:5], 0x0
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x100
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s4
scratch_store_b32 v0, v1, off
v_add_nc_u32_e32 v0, 4, v0
s_cbranch_scc1 .LBB5_1
scratch_load_b32 v0, off, off offset:268
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10local_3_64Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 272
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z10local_3_64Pf, .Lfunc_end5-_Z10local_3_64Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11local_3_128Pf
.globl _Z11local_3_128Pf
.p2align 8
.type _Z11local_3_128Pf,@function
_Z11local_3_128Pf:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 16
s_mov_b64 s[2:3], 0
.LBB6_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
s_add_u32 s2, s2, 4
s_load_b32 s4, s[4:5], 0x0
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x200
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s4
scratch_store_b32 v0, v1, off
v_add_nc_u32_e32 v0, 4, v0
s_cbranch_scc1 .LBB6_1
scratch_load_b32 v0, off, off offset:524
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11local_3_128Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 528
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end6:
.size _Z11local_3_128Pf, .Lfunc_end6-_Z11local_3_128Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9local_3_2Pf
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z9local_3_2Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9local_3_4Pf
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: _Z9local_3_4Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9local_3_8Pf
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z9local_3_8Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10local_3_16Pf
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z10local_3_16Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10local_3_32Pf
.private_segment_fixed_size: 144
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z10local_3_32Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10local_3_64Pf
.private_segment_fixed_size: 272
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z10local_3_64Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11local_3_128Pf
.private_segment_fixed_size: 528
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11local_3_128Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#define NUMS 64
//#define num_size 8
//#define NUM 49
#define local_1(NUMS) \
__global__ void local_1_##NUMS(float *a) \
{\
float tmp[NUMS];\
int i;\
for(i=0;i<NUMS;i++)\
{\
tmp[i]=a[i];\
}\
for(i=0;i<NUMS;i++)\
{\
a[i]+=tmp[i];\
}\
}
//local_1(29) //sm_10
//local_1(30)
//local_1(73) //sm_35
//local_1(74)
#define local_2(num_size) \
__global__ void local_2_##num_size(float *a,float *b,float *c)\
{\
float tmp_a[num_size*num_size];\
float temp;\
int i,j,k;\
for (i=0;i<num_size*num_size;i++)\
{\
tmp_a[i]=a[i];\
}\
for (i=0;i<num_size;i++)\
{\
for (j=0;j<num_size;j++)\
{\
temp=0.0;\
for (k=0;k<num_size;k++)\
{\
temp+=tmp_a[i*num_size+k]*b[k*num_size+j];\
}\
c[i*num_size+j]=temp;\
}\
}\
}
//local_2(2) //sm_10
//local_2(3)
//local_2(4)
//local_2(5)
//local_2(6) //sm_35
//local_2(7)
//local_2(8)
//local_2(9)
#define local_3(NUM) \
__global__ void local_3_##NUM(float *a)\
{\
float tmp[NUM];\
float minf=0.0,temp;\
int mind;\
int i,j;\
for(i=0;i<NUM;i++)\
{\
tmp[i]=a[i];\
}\
for(i=0;i<NUM;i++)\
{\
minf=tmp[i];\
mind=i;\
for (j=i;j<NUM;j++)\
{\
if (minf>tmp[j])\
{\
minf=tmp[j];\
mind=i;\
} \
}\
if (mind!=i)\
{\
temp=tmp[i];\
tmp[i]=tmp[mind];\
tmp[mind]=temp;\
}\
}\
a[0]=tmp[NUM-1];\
}
//sm_10
local_3(2)
local_3(4)
local_3(8)
local_3(16)
local_3(32)
local_3(64)
local_3(128) | .text
.file "local2.hip"
.globl _Z24__device_stub__local_3_2Pf # -- Begin function _Z24__device_stub__local_3_2Pf
.p2align 4, 0x90
.type _Z24__device_stub__local_3_2Pf,@function
_Z24__device_stub__local_3_2Pf: # @_Z24__device_stub__local_3_2Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9local_3_2Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__local_3_2Pf, .Lfunc_end0-_Z24__device_stub__local_3_2Pf
.cfi_endproc
# -- End function
.globl _Z24__device_stub__local_3_4Pf # -- Begin function _Z24__device_stub__local_3_4Pf
.p2align 4, 0x90
.type _Z24__device_stub__local_3_4Pf,@function
_Z24__device_stub__local_3_4Pf: # @_Z24__device_stub__local_3_4Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9local_3_4Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z24__device_stub__local_3_4Pf, .Lfunc_end1-_Z24__device_stub__local_3_4Pf
.cfi_endproc
# -- End function
.globl _Z24__device_stub__local_3_8Pf # -- Begin function _Z24__device_stub__local_3_8Pf
.p2align 4, 0x90
.type _Z24__device_stub__local_3_8Pf,@function
_Z24__device_stub__local_3_8Pf: # @_Z24__device_stub__local_3_8Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9local_3_8Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z24__device_stub__local_3_8Pf, .Lfunc_end2-_Z24__device_stub__local_3_8Pf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__local_3_16Pf # -- Begin function _Z25__device_stub__local_3_16Pf
.p2align 4, 0x90
.type _Z25__device_stub__local_3_16Pf,@function
_Z25__device_stub__local_3_16Pf: # @_Z25__device_stub__local_3_16Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10local_3_16Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z25__device_stub__local_3_16Pf, .Lfunc_end3-_Z25__device_stub__local_3_16Pf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__local_3_32Pf # -- Begin function _Z25__device_stub__local_3_32Pf
.p2align 4, 0x90
.type _Z25__device_stub__local_3_32Pf,@function
_Z25__device_stub__local_3_32Pf: # @_Z25__device_stub__local_3_32Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10local_3_32Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size _Z25__device_stub__local_3_32Pf, .Lfunc_end4-_Z25__device_stub__local_3_32Pf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__local_3_64Pf # -- Begin function _Z25__device_stub__local_3_64Pf
.p2align 4, 0x90
.type _Z25__device_stub__local_3_64Pf,@function
_Z25__device_stub__local_3_64Pf: # @_Z25__device_stub__local_3_64Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10local_3_64Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end5:
.size _Z25__device_stub__local_3_64Pf, .Lfunc_end5-_Z25__device_stub__local_3_64Pf
.cfi_endproc
# -- End function
.globl _Z26__device_stub__local_3_128Pf # -- Begin function _Z26__device_stub__local_3_128Pf
.p2align 4, 0x90
.type _Z26__device_stub__local_3_128Pf,@function
_Z26__device_stub__local_3_128Pf: # @_Z26__device_stub__local_3_128Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11local_3_128Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end6:
.size _Z26__device_stub__local_3_128Pf, .Lfunc_end6-_Z26__device_stub__local_3_128Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9local_3_2Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9local_3_4Pf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9local_3_8Pf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10local_3_16Pf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10local_3_32Pf, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10local_3_64Pf, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11local_3_128Pf, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9local_3_2Pf,@object # @_Z9local_3_2Pf
.section .rodata,"a",@progbits
.globl _Z9local_3_2Pf
.p2align 3, 0x0
_Z9local_3_2Pf:
.quad _Z24__device_stub__local_3_2Pf
.size _Z9local_3_2Pf, 8
.type _Z9local_3_4Pf,@object # @_Z9local_3_4Pf
.globl _Z9local_3_4Pf
.p2align 3, 0x0
_Z9local_3_4Pf:
.quad _Z24__device_stub__local_3_4Pf
.size _Z9local_3_4Pf, 8
.type _Z9local_3_8Pf,@object # @_Z9local_3_8Pf
.globl _Z9local_3_8Pf
.p2align 3, 0x0
_Z9local_3_8Pf:
.quad _Z24__device_stub__local_3_8Pf
.size _Z9local_3_8Pf, 8
.type _Z10local_3_16Pf,@object # @_Z10local_3_16Pf
.globl _Z10local_3_16Pf
.p2align 3, 0x0
_Z10local_3_16Pf:
.quad _Z25__device_stub__local_3_16Pf
.size _Z10local_3_16Pf, 8
.type _Z10local_3_32Pf,@object # @_Z10local_3_32Pf
.globl _Z10local_3_32Pf
.p2align 3, 0x0
_Z10local_3_32Pf:
.quad _Z25__device_stub__local_3_32Pf
.size _Z10local_3_32Pf, 8
.type _Z10local_3_64Pf,@object # @_Z10local_3_64Pf
.globl _Z10local_3_64Pf
.p2align 3, 0x0
_Z10local_3_64Pf:
.quad _Z25__device_stub__local_3_64Pf
.size _Z10local_3_64Pf, 8
.type _Z11local_3_128Pf,@object # @_Z11local_3_128Pf
.globl _Z11local_3_128Pf
.p2align 3, 0x0
_Z11local_3_128Pf:
.quad _Z26__device_stub__local_3_128Pf
.size _Z11local_3_128Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9local_3_2Pf"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9local_3_4Pf"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9local_3_8Pf"
.size .L__unnamed_3, 15
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z10local_3_16Pf"
.size .L__unnamed_4, 17
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z10local_3_32Pf"
.size .L__unnamed_5, 17
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z10local_3_64Pf"
.size .L__unnamed_6, 17
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z11local_3_128Pf"
.size .L__unnamed_7, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__local_3_2Pf
.addrsig_sym _Z24__device_stub__local_3_4Pf
.addrsig_sym _Z24__device_stub__local_3_8Pf
.addrsig_sym _Z25__device_stub__local_3_16Pf
.addrsig_sym _Z25__device_stub__local_3_32Pf
.addrsig_sym _Z25__device_stub__local_3_64Pf
.addrsig_sym _Z26__device_stub__local_3_128Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9local_3_2Pf
.addrsig_sym _Z9local_3_4Pf
.addrsig_sym _Z9local_3_8Pf
.addrsig_sym _Z10local_3_16Pf
.addrsig_sym _Z10local_3_32Pf
.addrsig_sym _Z10local_3_64Pf
.addrsig_sym _Z11local_3_128Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11local_3_128Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0x1fc] ; /* 0x0001fc0402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10local_3_64Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0xfc] ; /* 0x0000fc0402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10local_3_32Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0x7c] ; /* 0x00007c0402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10local_3_16Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0x3c] ; /* 0x00003c0402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9local_3_8Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0x1c] ; /* 0x00001c0402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9local_3_4Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0xc] ; /* 0x00000c0402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9local_3_2Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9local_3_2Pf
.globl _Z9local_3_2Pf
.p2align 8
.type _Z9local_3_2Pf,@function
_Z9local_3_2Pf:
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[4:5], s[0:1]
.LBB0_1:
s_load_b32 s6, s[4:5], 0x0
s_cmp_eq_u32 s2, 1
s_cselect_b32 s7, -1, 0
s_cmp_eq_u32 s2, 0
s_cselect_b32 s8, -1, 0
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s2, 1
s_waitcnt lgkmcnt(0)
v_cndmask_b32_e64 v0, v0, s6, s7
v_cndmask_b32_e64 v1, v1, s6, s8
s_cbranch_scc1 .LBB0_1
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9local_3_2Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 9
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9local_3_2Pf, .Lfunc_end0-_Z9local_3_2Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9local_3_4Pf
.globl _Z9local_3_4Pf
.p2align 8
.type _Z9local_3_4Pf,@function
_Z9local_3_4Pf:
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[4:5], s[0:1]
.p2align 6
.LBB1_1:
s_load_b32 s6, s[4:5], 0x0
s_cmp_eq_u32 s2, 3
s_cselect_b32 s7, -1, 0
s_cmp_eq_u32 s2, 2
s_cselect_b32 s8, -1, 0
s_cmp_eq_u32 s2, 1
s_cselect_b32 s9, -1, 0
s_cmp_eq_u32 s2, 0
s_cselect_b32 s10, -1, 0
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s2, 4
s_waitcnt lgkmcnt(0)
v_cndmask_b32_e64 v1, v1, s6, s7
v_cndmask_b32_e64 v3, v3, s6, s8
v_cndmask_b32_e64 v2, v2, s6, s9
v_cndmask_b32_e64 v0, v0, s6, s10
s_cbranch_scc1 .LBB1_1
v_mov_b32_e32 v0, 0
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9local_3_4Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 11
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9local_3_4Pf, .Lfunc_end1-_Z9local_3_4Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9local_3_8Pf
.globl _Z9local_3_8Pf
.p2align 8
.type _Z9local_3_8Pf,@function
_Z9local_3_8Pf:
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[4:5], s[0:1]
.LBB2_1:
s_load_b32 s6, s[4:5], 0x0
s_mov_b32 m0, s2
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s2, 8
s_waitcnt lgkmcnt(0)
v_movreld_b32_e32 v0, s6
s_cbranch_scc1 .LBB2_1
v_mov_b32_e32 v0, 0
global_store_b32 v0, v7, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9local_3_8Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z9local_3_8Pf, .Lfunc_end2-_Z9local_3_8Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10local_3_16Pf
.globl _Z10local_3_16Pf
.p2align 8
.type _Z10local_3_16Pf,@function
_Z10local_3_16Pf:
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[4:5], s[0:1]
.LBB3_1:
s_load_b32 s6, s[4:5], 0x0
s_mov_b32 m0, s2
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s2, 16
s_waitcnt lgkmcnt(0)
v_movreld_b32_e32 v0, s6
s_cbranch_scc1 .LBB3_1
v_mov_b32_e32 v0, 0
global_store_b32 v0, v15, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10local_3_16Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z10local_3_16Pf, .Lfunc_end3-_Z10local_3_16Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10local_3_32Pf
.globl _Z10local_3_32Pf
.p2align 8
.type _Z10local_3_32Pf,@function
_Z10local_3_32Pf:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 16
s_mov_b64 s[2:3], 0
.LBB4_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
s_add_u32 s2, s2, 4
s_load_b32 s4, s[4:5], 0x0
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x80
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s4
scratch_store_b32 v0, v1, off
v_add_nc_u32_e32 v0, 4, v0
s_cbranch_scc1 .LBB4_1
scratch_load_b32 v0, off, off offset:140
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10local_3_32Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 144
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z10local_3_32Pf, .Lfunc_end4-_Z10local_3_32Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10local_3_64Pf
.globl _Z10local_3_64Pf
.p2align 8
.type _Z10local_3_64Pf,@function
_Z10local_3_64Pf:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 16
s_mov_b64 s[2:3], 0
.LBB5_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
s_add_u32 s2, s2, 4
s_load_b32 s4, s[4:5], 0x0
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x100
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s4
scratch_store_b32 v0, v1, off
v_add_nc_u32_e32 v0, 4, v0
s_cbranch_scc1 .LBB5_1
scratch_load_b32 v0, off, off offset:268
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10local_3_64Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 272
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z10local_3_64Pf, .Lfunc_end5-_Z10local_3_64Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11local_3_128Pf
.globl _Z11local_3_128Pf
.p2align 8
.type _Z11local_3_128Pf,@function
_Z11local_3_128Pf:
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 16
s_mov_b64 s[2:3], 0
.LBB6_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
s_add_u32 s2, s2, 4
s_load_b32 s4, s[4:5], 0x0
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x200
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s4
scratch_store_b32 v0, v1, off
v_add_nc_u32_e32 v0, 4, v0
s_cbranch_scc1 .LBB6_1
scratch_load_b32 v0, off, off offset:524
v_mov_b32_e32 v1, 0
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11local_3_128Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 528
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end6:
.size _Z11local_3_128Pf, .Lfunc_end6-_Z11local_3_128Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9local_3_2Pf
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z9local_3_2Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9local_3_4Pf
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: _Z9local_3_4Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9local_3_8Pf
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z9local_3_8Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10local_3_16Pf
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z10local_3_16Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10local_3_32Pf
.private_segment_fixed_size: 144
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z10local_3_32Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10local_3_64Pf
.private_segment_fixed_size: 272
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z10local_3_64Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11local_3_128Pf
.private_segment_fixed_size: 528
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11local_3_128Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fdb10_00000000-6_local2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z9local_3_2PfPf
.type _Z28__device_stub__Z9local_3_2PfPf, @function
_Z28__device_stub__Z9local_3_2PfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9local_3_2Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z9local_3_2PfPf, .-_Z28__device_stub__Z9local_3_2PfPf
.globl _Z9local_3_2Pf
.type _Z9local_3_2Pf, @function
_Z9local_3_2Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9local_3_2PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9local_3_2Pf, .-_Z9local_3_2Pf
.globl _Z28__device_stub__Z9local_3_4PfPf
.type _Z28__device_stub__Z9local_3_4PfPf, @function
_Z28__device_stub__Z9local_3_4PfPf:
.LFB2053:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9local_3_4Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z28__device_stub__Z9local_3_4PfPf, .-_Z28__device_stub__Z9local_3_4PfPf
.globl _Z9local_3_4Pf
.type _Z9local_3_4Pf, @function
_Z9local_3_4Pf:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9local_3_4PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z9local_3_4Pf, .-_Z9local_3_4Pf
.globl _Z28__device_stub__Z9local_3_8PfPf
.type _Z28__device_stub__Z9local_3_8PfPf, @function
_Z28__device_stub__Z9local_3_8PfPf:
.LFB2055:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9local_3_8Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z28__device_stub__Z9local_3_8PfPf, .-_Z28__device_stub__Z9local_3_8PfPf
.globl _Z9local_3_8Pf
.type _Z9local_3_8Pf, @function
_Z9local_3_8Pf:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9local_3_8PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z9local_3_8Pf, .-_Z9local_3_8Pf
.globl _Z30__device_stub__Z10local_3_16PfPf
.type _Z30__device_stub__Z10local_3_16PfPf, @function
_Z30__device_stub__Z10local_3_16PfPf:
.LFB2057:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10local_3_16Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z30__device_stub__Z10local_3_16PfPf, .-_Z30__device_stub__Z10local_3_16PfPf
.globl _Z10local_3_16Pf
.type _Z10local_3_16Pf, @function
_Z10local_3_16Pf:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10local_3_16PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10local_3_16Pf, .-_Z10local_3_16Pf
.globl _Z30__device_stub__Z10local_3_32PfPf
.type _Z30__device_stub__Z10local_3_32PfPf, @function
_Z30__device_stub__Z10local_3_32PfPf:
.LFB2059:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10local_3_32Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z30__device_stub__Z10local_3_32PfPf, .-_Z30__device_stub__Z10local_3_32PfPf
.globl _Z10local_3_32Pf
.type _Z10local_3_32Pf, @function
_Z10local_3_32Pf:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10local_3_32PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z10local_3_32Pf, .-_Z10local_3_32Pf
.globl _Z30__device_stub__Z10local_3_64PfPf
.type _Z30__device_stub__Z10local_3_64PfPf, @function
_Z30__device_stub__Z10local_3_64PfPf:
.LFB2061:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10local_3_64Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z30__device_stub__Z10local_3_64PfPf, .-_Z30__device_stub__Z10local_3_64PfPf
.globl _Z10local_3_64Pf
.type _Z10local_3_64Pf, @function
_Z10local_3_64Pf:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10local_3_64PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z10local_3_64Pf, .-_Z10local_3_64Pf
.globl _Z31__device_stub__Z11local_3_128PfPf
.type _Z31__device_stub__Z11local_3_128PfPf, @function
_Z31__device_stub__Z11local_3_128PfPf:
.LFB2063:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11local_3_128Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z31__device_stub__Z11local_3_128PfPf, .-_Z31__device_stub__Z11local_3_128PfPf
.globl _Z11local_3_128Pf
.type _Z11local_3_128Pf, @function
_Z11local_3_128Pf:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11local_3_128PfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z11local_3_128Pf, .-_Z11local_3_128Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11local_3_128Pf"
.LC1:
.string "_Z10local_3_64Pf"
.LC2:
.string "_Z10local_3_32Pf"
.LC3:
.string "_Z10local_3_16Pf"
.LC4:
.string "_Z9local_3_8Pf"
.LC5:
.string "_Z9local_3_4Pf"
.LC6:
.string "_Z9local_3_2Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2066:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11local_3_128Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10local_3_64Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10local_3_32Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10local_3_16Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9local_3_8Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9local_3_4Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9local_3_2Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "local2.hip"
.globl _Z24__device_stub__local_3_2Pf # -- Begin function _Z24__device_stub__local_3_2Pf
.p2align 4, 0x90
.type _Z24__device_stub__local_3_2Pf,@function
_Z24__device_stub__local_3_2Pf: # @_Z24__device_stub__local_3_2Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9local_3_2Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__local_3_2Pf, .Lfunc_end0-_Z24__device_stub__local_3_2Pf
.cfi_endproc
# -- End function
.globl _Z24__device_stub__local_3_4Pf # -- Begin function _Z24__device_stub__local_3_4Pf
.p2align 4, 0x90
.type _Z24__device_stub__local_3_4Pf,@function
_Z24__device_stub__local_3_4Pf: # @_Z24__device_stub__local_3_4Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9local_3_4Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z24__device_stub__local_3_4Pf, .Lfunc_end1-_Z24__device_stub__local_3_4Pf
.cfi_endproc
# -- End function
.globl _Z24__device_stub__local_3_8Pf # -- Begin function _Z24__device_stub__local_3_8Pf
.p2align 4, 0x90
.type _Z24__device_stub__local_3_8Pf,@function
_Z24__device_stub__local_3_8Pf: # @_Z24__device_stub__local_3_8Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9local_3_8Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z24__device_stub__local_3_8Pf, .Lfunc_end2-_Z24__device_stub__local_3_8Pf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__local_3_16Pf # -- Begin function _Z25__device_stub__local_3_16Pf
.p2align 4, 0x90
.type _Z25__device_stub__local_3_16Pf,@function
_Z25__device_stub__local_3_16Pf: # @_Z25__device_stub__local_3_16Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10local_3_16Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z25__device_stub__local_3_16Pf, .Lfunc_end3-_Z25__device_stub__local_3_16Pf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__local_3_32Pf # -- Begin function _Z25__device_stub__local_3_32Pf
.p2align 4, 0x90
.type _Z25__device_stub__local_3_32Pf,@function
_Z25__device_stub__local_3_32Pf: # @_Z25__device_stub__local_3_32Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10local_3_32Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size _Z25__device_stub__local_3_32Pf, .Lfunc_end4-_Z25__device_stub__local_3_32Pf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__local_3_64Pf # -- Begin function _Z25__device_stub__local_3_64Pf
.p2align 4, 0x90
.type _Z25__device_stub__local_3_64Pf,@function
_Z25__device_stub__local_3_64Pf: # @_Z25__device_stub__local_3_64Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10local_3_64Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end5:
.size _Z25__device_stub__local_3_64Pf, .Lfunc_end5-_Z25__device_stub__local_3_64Pf
.cfi_endproc
# -- End function
.globl _Z26__device_stub__local_3_128Pf # -- Begin function _Z26__device_stub__local_3_128Pf
.p2align 4, 0x90
.type _Z26__device_stub__local_3_128Pf,@function
_Z26__device_stub__local_3_128Pf: # @_Z26__device_stub__local_3_128Pf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11local_3_128Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end6:
.size _Z26__device_stub__local_3_128Pf, .Lfunc_end6-_Z26__device_stub__local_3_128Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9local_3_2Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9local_3_4Pf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9local_3_8Pf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10local_3_16Pf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10local_3_32Pf, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10local_3_64Pf, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11local_3_128Pf, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9local_3_2Pf,@object # @_Z9local_3_2Pf
.section .rodata,"a",@progbits
.globl _Z9local_3_2Pf
.p2align 3, 0x0
_Z9local_3_2Pf:
.quad _Z24__device_stub__local_3_2Pf
.size _Z9local_3_2Pf, 8
.type _Z9local_3_4Pf,@object # @_Z9local_3_4Pf
.globl _Z9local_3_4Pf
.p2align 3, 0x0
_Z9local_3_4Pf:
.quad _Z24__device_stub__local_3_4Pf
.size _Z9local_3_4Pf, 8
.type _Z9local_3_8Pf,@object # @_Z9local_3_8Pf
.globl _Z9local_3_8Pf
.p2align 3, 0x0
_Z9local_3_8Pf:
.quad _Z24__device_stub__local_3_8Pf
.size _Z9local_3_8Pf, 8
.type _Z10local_3_16Pf,@object # @_Z10local_3_16Pf
.globl _Z10local_3_16Pf
.p2align 3, 0x0
_Z10local_3_16Pf:
.quad _Z25__device_stub__local_3_16Pf
.size _Z10local_3_16Pf, 8
.type _Z10local_3_32Pf,@object # @_Z10local_3_32Pf
.globl _Z10local_3_32Pf
.p2align 3, 0x0
_Z10local_3_32Pf:
.quad _Z25__device_stub__local_3_32Pf
.size _Z10local_3_32Pf, 8
.type _Z10local_3_64Pf,@object # @_Z10local_3_64Pf
.globl _Z10local_3_64Pf
.p2align 3, 0x0
_Z10local_3_64Pf:
.quad _Z25__device_stub__local_3_64Pf
.size _Z10local_3_64Pf, 8
.type _Z11local_3_128Pf,@object # @_Z11local_3_128Pf
.globl _Z11local_3_128Pf
.p2align 3, 0x0
_Z11local_3_128Pf:
.quad _Z26__device_stub__local_3_128Pf
.size _Z11local_3_128Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9local_3_2Pf"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9local_3_4Pf"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9local_3_8Pf"
.size .L__unnamed_3, 15
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z10local_3_16Pf"
.size .L__unnamed_4, 17
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z10local_3_32Pf"
.size .L__unnamed_5, 17
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z10local_3_64Pf"
.size .L__unnamed_6, 17
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z11local_3_128Pf"
.size .L__unnamed_7, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__local_3_2Pf
.addrsig_sym _Z24__device_stub__local_3_4Pf
.addrsig_sym _Z24__device_stub__local_3_8Pf
.addrsig_sym _Z25__device_stub__local_3_16Pf
.addrsig_sym _Z25__device_stub__local_3_32Pf
.addrsig_sym _Z25__device_stub__local_3_64Pf
.addrsig_sym _Z26__device_stub__local_3_128Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9local_3_2Pf
.addrsig_sym _Z9local_3_4Pf
.addrsig_sym _Z9local_3_8Pf
.addrsig_sym _Z10local_3_16Pf
.addrsig_sym _Z10local_3_32Pf
.addrsig_sym _Z10local_3_64Pf
.addrsig_sym _Z11local_3_128Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cmath>
#include <cstring>
#define NSTREAM 4
#define BDIM 128
void initialData(float *ip, int size)
{
for (int i = 0; i < size; i++)
{
ip[i] = (float)(rand() & 0xFF) / 10.0f;
}
}
void sumArraysOnHost(float *A, float *B, float *C, const int N)
{
for (int idx = 0; idx < N; idx++)
C[idx] = A[idx] + B[idx];
}
__global__ void sumArrays(float *A, float *B, float *C, const int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N)
{
for (int i = 0; i < N; ++i)
{
C[idx] = A[idx] + B[idx];
}
}
}
void checkResult(float *hostRef, float *gpuRef, const int N)
{
double epsilon = 1.0E-8;
bool match = true;
for (int i = 0; i < N; i++)
{
if (abs(hostRef[i] - gpuRef[i]) > epsilon)
{
match = false;
printf("Arrays do not match!\n");
printf("host %5.2f gpu %5.2f at %d\n", hostRef[i], gpuRef[i], i);
break;
}
}
if (match)
printf("Arrays match.\n\n");
}
int main(int argc, char **argv)
{
printf("> %s Starting...\n", argv[0]);
int dev = 0;
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
printf("> Using Device %d: %s\n", dev, deviceProp.name);
cudaSetDevice(dev);
// check if device support hyper-q
if (deviceProp.major < 3 || (deviceProp.major == 3 && deviceProp.minor < 5))
{
if (deviceProp.concurrentKernels == 0)
{
printf("> GPU does not support concurrent kernel execution (SM 3.5 or higher required)\n");
printf("> CUDA kernel runs will be serialized\n");
}
else
{
printf("> GPU does not support HyperQ\n");
printf("> CUDA kernel runs will have limited concurrency\n");
}
}
printf("> Compute Capability %d.%d hardware with %d multi-processors\n", deviceProp.major, deviceProp.minor, deviceProp.multiProcessorCount);
// set up data size of vectors
int nElem = 1 << 16;
printf("> vector size = %d\n", nElem);
size_t nBytes = nElem * sizeof(float);
// malloc pinned host memory for async memcpy
float *h_A, *h_B, *hostRef, *gpuRef;
cudaHostAlloc((void**)&h_A, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&h_B, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&gpuRef, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&hostRef, nBytes, cudaHostAllocDefault);
// initialize data at host side
initialData(h_A, nElem);
initialData(h_B, nElem);
memset(hostRef, 0, nBytes);
memset(gpuRef, 0, nBytes);
// add vector at host side for result checks
sumArraysOnHost(h_A, h_B, hostRef, nElem);
// malloc device global memory
float *d_A, *d_B, *d_C;
cudaMalloc((float**)&d_A, nBytes);
cudaMalloc((float**)&d_B, nBytes);
cudaMalloc((float**)&d_C, nBytes);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// invoke kernel at host side
dim3 block(BDIM);
dim3 grid((nElem + block.x - 1) / block.x);
printf("> grid (%d, %d) block (%d, %d)\n", grid.x, grid.y, block.x,block.y);
// sequential operation
cudaEventRecord(start, 0);
cudaMemcpy(d_A, h_A, nBytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, nBytes, cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float memcpy_h2d_time;
cudaEventElapsedTime(&memcpy_h2d_time, start, stop);
cudaEventRecord(start, 0);
sumArrays <<<grid, block >>>(d_A, d_B, d_C, nElem);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float kernel_time;
cudaEventElapsedTime(&kernel_time, start, stop);
cudaEventRecord(start, 0);
cudaMemcpy(gpuRef, d_C, nBytes, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float memcpy_d2h_time;
cudaEventElapsedTime(&memcpy_d2h_time, start, stop);
float itotal = kernel_time + memcpy_h2d_time + memcpy_d2h_time;
printf("\n");
printf("Measured timings (throughput):\n");
printf(" Memcpy host to device\t: %f ms (%f GB/s)\n", memcpy_h2d_time, (nBytes * 1e-6) / memcpy_h2d_time);
printf(" Memcpy device to host\t: %f ms (%f GB/s)\n", memcpy_d2h_time, (nBytes * 1e-6) / memcpy_d2h_time);
printf(" Kernel\t\t\t: %f ms (%f GB/s)\n", kernel_time, (nBytes * 2e-6) / kernel_time);
printf(" Total\t\t\t: %f ms (%f GB/s)\n", itotal, (nBytes * 2e-6) / itotal);
// grid parallel operation
int iElem = nElem / NSTREAM;
size_t iBytes = iElem * sizeof(float);
grid.x = (iElem + block.x - 1) / block.x;
cudaStream_t stream[NSTREAM];
for (int i = 0; i < NSTREAM; ++i)
{
cudaStreamCreate(&stream[i]);
}
cudaEventRecord(start, 0);
// initiate all work on the device asynchronously in depth-first order
for (int i = 0; i < NSTREAM; ++i)
{
int ioffset = i * iElem;
cudaMemcpyAsync(&d_A[ioffset], &h_A[ioffset], iBytes, cudaMemcpyHostToDevice, stream[i]);
cudaMemcpyAsync(&d_B[ioffset], &h_B[ioffset], iBytes, cudaMemcpyHostToDevice, stream[i]);
sumArrays <<<grid, block, 0, stream[i] >>>(&d_A[ioffset], &d_B[ioffset], &d_C[ioffset], iElem);
cudaMemcpyAsync(&gpuRef[ioffset], &d_C[ioffset], iBytes, cudaMemcpyDeviceToHost, stream[i]);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float execution_time;
cudaEventElapsedTime(&execution_time, start, stop);
printf("\n");
printf("Actual results from overlapped data transfers:\n");
printf(" overlap with %d streams : %f ms (%f GB/s)\n", NSTREAM, execution_time, (nBytes * 2e-6) / execution_time);
printf(" speedup : %f \n", ((itotal - execution_time) * 100.0f) / itotal);
// check kernel error
cudaGetLastError();
// check device results
checkResult(hostRef, gpuRef, nElem);
// free device global memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// free host memory
cudaFreeHost(h_A);
cudaFreeHost(h_B);
cudaFreeHost(hostRef);
cudaFreeHost(gpuRef);
// destroy events
cudaEventDestroy(start);
cudaEventDestroy(stop);
// destroy streams
for (int i = 0; i < NSTREAM; ++i)
{
cudaStreamDestroy(stream[i]);
}
cudaDeviceReset();
system("Pause");
return(0);
} | code for sm_80
Function : _Z9sumArraysPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x178], !P0 ; /* 0x00005e0006007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fcc0003f06070 */
/*00d0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0100*/ @!P0 BRA 0x940 ; /* 0x0000083000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fc80007ffe1ff */
/*0120*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f04270 */
/*0130*/ @!P0 BRA 0x810 ; /* 0x000006d000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x5b0 ; /* 0x0000044000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001ea8000c1e1900 */
/*0190*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*01c0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0003e8000c101904 */
/*0200*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0005e8000c101904 */
/*0240*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0270*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0007e8000c101904 */
/*0280*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f24000c1e1900 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*02b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*02c0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x002f24000c1e1900 */
/*02e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*02f0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0003e8000c101904 */
/*0300*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x004f24000c1e1900 */
/*0320*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0330*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0005e8000c101904 */
/*0340*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0350*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x008f24000c1e1900 */
/*0360*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0370*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0007e8000c101904 */
/*0380*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f24000c1e1900 */
/*03a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*03b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x002f24000c1e1900 */
/*03e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*03f0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0003e8000c101904 */
/*0400*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x004f24000c1e1900 */
/*0420*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0430*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0005e8000c101904 */
/*0440*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x008f24000c1e1900 */
/*0460*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0470*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0007e8000c101904 */
/*0480*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f24000c1e1900 */
/*04a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*04b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*04c0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x002f24000c1e1900 */
/*04e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*04f0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0500*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x004f22000c1e1900 */
/*0520*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0530*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0540*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0550*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0560*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x008ea2000c1e1900 */
/*0570*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*0580*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fca0000000000 */
/*0590*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001ee000c101904 */
/*05a0*/ @P1 BRA 0x180 ; /* 0xfffffbd000001947 */
/* 0x000fea000383ffff */
/*05b0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*05c0*/ @!P1 BRA 0x7f0 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*05d0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001ea8000c1e1900 */
/*05e0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea4000c1e1900 */
/*05f0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*0600*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*0610*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0620*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea4000c1e1900 */
/*0630*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0640*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0003e8000c101904 */
/*0650*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0670*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0680*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0005e8000c101904 */
/*0690*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ee8000c1e1900 */
/*06a0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ee4000c1e1900 */
/*06b0*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*06c0*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0007e8000c101904 */
/*06d0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001f28000c1e1900 */
/*06e0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f24000c1e1900 */
/*06f0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*0700*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*0710*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0720*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x002f24000c1e1900 */
/*0730*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*0740*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0750*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0760*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x004f24000c1e1900 */
/*0770*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0780*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0790*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x008ea2000c1e1900 */
/*07b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*07c0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fca0000000000 */
/*07e0*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*07f0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0800*/ @!P0 BRA 0x940 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0810*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001ea8000c1e1900 */
/*0820*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea4000c1e1900 */
/*0830*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*0840*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*0850*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea4000c1e1900 */
/*0870*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0880*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0890*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*08a0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea2000c1e1900 */
/*08b0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*08d0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*08e0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*08f0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea2000c1e1900 */
/*0900*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0910*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fca0000000000 */
/*0920*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001ee000c101904 */
/*0930*/ @P0 BRA 0x810 ; /* 0xfffffed000000947 */
/* 0x001fea000383ffff */
/*0940*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0950*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0960*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea2000c1e1900 */
/*0980*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0990*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*09a0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*09b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*09c0*/ @P0 BRA 0x960 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*09d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09e0*/ BRA 0x9e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cmath>
#include <cstring>
#define NSTREAM 4
#define BDIM 128
void initialData(float *ip, int size)
{
for (int i = 0; i < size; i++)
{
ip[i] = (float)(rand() & 0xFF) / 10.0f;
}
}
void sumArraysOnHost(float *A, float *B, float *C, const int N)
{
for (int idx = 0; idx < N; idx++)
C[idx] = A[idx] + B[idx];
}
__global__ void sumArrays(float *A, float *B, float *C, const int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N)
{
for (int i = 0; i < N; ++i)
{
C[idx] = A[idx] + B[idx];
}
}
}
void checkResult(float *hostRef, float *gpuRef, const int N)
{
double epsilon = 1.0E-8;
bool match = true;
for (int i = 0; i < N; i++)
{
if (abs(hostRef[i] - gpuRef[i]) > epsilon)
{
match = false;
printf("Arrays do not match!\n");
printf("host %5.2f gpu %5.2f at %d\n", hostRef[i], gpuRef[i], i);
break;
}
}
if (match)
printf("Arrays match.\n\n");
}
int main(int argc, char **argv)
{
printf("> %s Starting...\n", argv[0]);
int dev = 0;
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
printf("> Using Device %d: %s\n", dev, deviceProp.name);
cudaSetDevice(dev);
// check if device support hyper-q
if (deviceProp.major < 3 || (deviceProp.major == 3 && deviceProp.minor < 5))
{
if (deviceProp.concurrentKernels == 0)
{
printf("> GPU does not support concurrent kernel execution (SM 3.5 or higher required)\n");
printf("> CUDA kernel runs will be serialized\n");
}
else
{
printf("> GPU does not support HyperQ\n");
printf("> CUDA kernel runs will have limited concurrency\n");
}
}
printf("> Compute Capability %d.%d hardware with %d multi-processors\n", deviceProp.major, deviceProp.minor, deviceProp.multiProcessorCount);
// set up data size of vectors
int nElem = 1 << 16;
printf("> vector size = %d\n", nElem);
size_t nBytes = nElem * sizeof(float);
// malloc pinned host memory for async memcpy
float *h_A, *h_B, *hostRef, *gpuRef;
cudaHostAlloc((void**)&h_A, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&h_B, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&gpuRef, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&hostRef, nBytes, cudaHostAllocDefault);
// initialize data at host side
initialData(h_A, nElem);
initialData(h_B, nElem);
memset(hostRef, 0, nBytes);
memset(gpuRef, 0, nBytes);
// add vector at host side for result checks
sumArraysOnHost(h_A, h_B, hostRef, nElem);
// malloc device global memory
float *d_A, *d_B, *d_C;
cudaMalloc((float**)&d_A, nBytes);
cudaMalloc((float**)&d_B, nBytes);
cudaMalloc((float**)&d_C, nBytes);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// invoke kernel at host side
dim3 block(BDIM);
dim3 grid((nElem + block.x - 1) / block.x);
printf("> grid (%d, %d) block (%d, %d)\n", grid.x, grid.y, block.x,block.y);
// sequential operation
cudaEventRecord(start, 0);
cudaMemcpy(d_A, h_A, nBytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, nBytes, cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float memcpy_h2d_time;
cudaEventElapsedTime(&memcpy_h2d_time, start, stop);
cudaEventRecord(start, 0);
sumArrays <<<grid, block >>>(d_A, d_B, d_C, nElem);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float kernel_time;
cudaEventElapsedTime(&kernel_time, start, stop);
cudaEventRecord(start, 0);
cudaMemcpy(gpuRef, d_C, nBytes, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float memcpy_d2h_time;
cudaEventElapsedTime(&memcpy_d2h_time, start, stop);
float itotal = kernel_time + memcpy_h2d_time + memcpy_d2h_time;
printf("\n");
printf("Measured timings (throughput):\n");
printf(" Memcpy host to device\t: %f ms (%f GB/s)\n", memcpy_h2d_time, (nBytes * 1e-6) / memcpy_h2d_time);
printf(" Memcpy device to host\t: %f ms (%f GB/s)\n", memcpy_d2h_time, (nBytes * 1e-6) / memcpy_d2h_time);
printf(" Kernel\t\t\t: %f ms (%f GB/s)\n", kernel_time, (nBytes * 2e-6) / kernel_time);
printf(" Total\t\t\t: %f ms (%f GB/s)\n", itotal, (nBytes * 2e-6) / itotal);
// grid parallel operation
int iElem = nElem / NSTREAM;
size_t iBytes = iElem * sizeof(float);
grid.x = (iElem + block.x - 1) / block.x;
cudaStream_t stream[NSTREAM];
for (int i = 0; i < NSTREAM; ++i)
{
cudaStreamCreate(&stream[i]);
}
cudaEventRecord(start, 0);
// initiate all work on the device asynchronously in depth-first order
for (int i = 0; i < NSTREAM; ++i)
{
int ioffset = i * iElem;
cudaMemcpyAsync(&d_A[ioffset], &h_A[ioffset], iBytes, cudaMemcpyHostToDevice, stream[i]);
cudaMemcpyAsync(&d_B[ioffset], &h_B[ioffset], iBytes, cudaMemcpyHostToDevice, stream[i]);
sumArrays <<<grid, block, 0, stream[i] >>>(&d_A[ioffset], &d_B[ioffset], &d_C[ioffset], iElem);
cudaMemcpyAsync(&gpuRef[ioffset], &d_C[ioffset], iBytes, cudaMemcpyDeviceToHost, stream[i]);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float execution_time;
cudaEventElapsedTime(&execution_time, start, stop);
printf("\n");
printf("Actual results from overlapped data transfers:\n");
printf(" overlap with %d streams : %f ms (%f GB/s)\n", NSTREAM, execution_time, (nBytes * 2e-6) / execution_time);
printf(" speedup : %f \n", ((itotal - execution_time) * 100.0f) / itotal);
// check kernel error
cudaGetLastError();
// check device results
checkResult(hostRef, gpuRef, nElem);
// free device global memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// free host memory
cudaFreeHost(h_A);
cudaFreeHost(h_B);
cudaFreeHost(hostRef);
cudaFreeHost(gpuRef);
// destroy events
cudaEventDestroy(start);
cudaEventDestroy(stop);
// destroy streams
for (int i = 0; i < NSTREAM; ++i)
{
cudaStreamDestroy(stream[i]);
}
cudaDeviceReset();
system("Pause");
return(0);
} | .file "tmpxft_00058680_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initialDataPfi
.type _Z11initialDataPfi, @function
_Z11initialDataPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11initialDataPfi, .-_Z11initialDataPfi
.globl _Z15sumArraysOnHostPfS_S_i
.type _Z15sumArraysOnHostPfS_S_i, @function
_Z15sumArraysOnHostPfS_S_i:
.LFB2058:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L13:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE2058:
.size _Z15sumArraysOnHostPfS_S_i, .-_Z15sumArraysOnHostPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Arrays do not match!\n"
.LC4:
.string "host %5.2f gpu %5.2f at %d\n"
.LC5:
.string "Arrays match.\n\n"
.text
.globl _Z11checkResultPfS_i
.type _Z11checkResultPfS_i, @function
_Z11checkResultPfS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %edx, %edx
jle .L16
movq %rdi, %rbp
movq %rsi, %rbx
movl $0, %r12d
movss .LC1(%rip), %xmm2
movsd .LC2(%rip), %xmm1
.L20:
movss 0(%rbp), %xmm0
subss (%rbx), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L25
addl $1, %r12d
addq $4, %rbp
addq $4, %rbx
cmpl %r12d, %edx
jne .L20
.L16:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L15:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movl %r12d, %edx
pxor %xmm1, %xmm1
cvtss2sd (%rbx), %xmm1
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
jmp .L15
.cfi_endproc
.LFE2059:
.size _Z11checkResultPfS_i, .-_Z11checkResultPfS_i
.globl _Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9sumArraysPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i
.globl _Z9sumArraysPfS_S_i
.type _Z9sumArraysPfS_S_i, @function
_Z9sumArraysPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9sumArraysPfS_S_i, .-_Z9sumArraysPfS_S_i
.section .rodata.str1.1
.LC6:
.string "> %s Starting...\n"
.LC7:
.string "> Using Device %d: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "> GPU does not support concurrent kernel execution (SM 3.5 or higher required)\n"
.align 8
.LC9:
.string "> CUDA kernel runs will be serialized\n"
.align 8
.LC10:
.string "> GPU does not support HyperQ\n"
.align 8
.LC11:
.string "> CUDA kernel runs will have limited concurrency\n"
.align 8
.LC12:
.string "> Compute Capability %d.%d hardware with %d multi-processors\n"
.section .rodata.str1.1
.LC13:
.string "> vector size = %d\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "> grid (%d, %d) block (%d, %d)\n"
.section .rodata.str1.1
.LC15:
.string "\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "Measured timings (throughput):\n"
.align 8
.LC18:
.string " Memcpy host to device\t: %f ms (%f GB/s)\n"
.align 8
.LC19:
.string " Memcpy device to host\t: %f ms (%f GB/s)\n"
.section .rodata.str1.1
.LC21:
.string " Kernel\t\t\t: %f ms (%f GB/s)\n"
.LC22:
.string " Total\t\t\t: %f ms (%f GB/s)\n"
.section .rodata.str1.8
.align 8
.LC23:
.string "Actual results from overlapped data transfers:\n"
.align 8
.LC24:
.string " overlap with %d streams : %f ms (%f GB/s)\n"
.align 8
.LC26:
.string " speedup : %f \n"
.section .rodata.str1.1
.LC27:
.string "Pause"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1200, %rsp
.cfi_def_cfa_offset 1248
movq %fs:40, %rax
movq %rax, 1192(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 160(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl $0, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl 520(%rsp), %eax
cmpl $2, %eax
jle .L35
cmpl $3, %eax
je .L46
.L36:
movl 548(%rsp), %r8d
movl 524(%rsp), %ecx
movl 520(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $65536, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
leaq 56(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
leaq 48(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
movl $65536, %esi
movq 32(%rsp), %rdi
call _Z11initialDataPfi
movl $65536, %esi
movq 40(%rsp), %rdi
call _Z11initialDataPfi
movl $262144, %edx
movl $0, %esi
movq 48(%rsp), %rdi
call memset@PLT
movl $262144, %edx
movl $0, %esi
movq 56(%rsp), %rdi
call memset@PLT
movl $65536, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z15sumArraysOnHostPfS_S_i
leaq 64(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, 112(%rsp)
movl $1, 124(%rsp)
movl $1, %r9d
movl $128, %r8d
movl $1, %ecx
movl $512, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $262144, %edx
movq 32(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $262144, %edx
movq 40(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movq 96(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 16(%rsp), %rdi
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl $512, 116(%rsp)
movl $1, 120(%rsp)
movl $128, 104(%rsp)
movl $1, 108(%rsp)
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L38:
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movq 96(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $262144, %edx
movq 80(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movq 96(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 24(%rsp), %rdi
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 20(%rsp), %xmm0
addss 16(%rsp), %xmm0
addss 24(%rsp), %xmm0
movss %xmm0, 12(%rsp)
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
movsd .LC17(%rip), %xmm1
divsd %xmm0, %xmm1
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 24(%rsp), %xmm0
movsd .LC17(%rip), %xmm1
divsd %xmm0, %xmm1
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
movsd .LC20(%rip), %xmm1
divsd %xmm0, %xmm1
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movsd .LC20(%rip), %xmm1
divsd %xmm0, %xmm1
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq 128(%rsp), %r13
movq %r13, %rdi
call cudaStreamCreate@PLT
leaq 136(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 144(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 152(%rsp), %rdi
call cudaStreamCreate@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq %r13, %r12
movq %r13, %rbp
movl $0, %ebx
jmp .L40
.L46:
cmpl $4, 524(%rsp)
jg .L36
.L35:
cmpl $0, 736(%rsp)
jne .L37
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L37:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L47:
movl $65536, %ecx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i
jmp .L38
.L39:
movq %rbx, %rsi
addq 80(%rsp), %rsi
movq %rbx, %rdi
addq 56(%rsp), %rdi
movq (%r14), %r8
movl $2, %ecx
movl $65536, %edx
call cudaMemcpyAsync@PLT
addq $8, %rbp
addq $65536, %rbx
cmpq $262144, %rbx
je .L48
.L40:
movq %rbp, %r14
movq %rbx, %rsi
addq 32(%rsp), %rsi
movq %rbx, %rdi
addq 64(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $65536, %edx
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq %rbx, %rdi
addq 72(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $65536, %edx
call cudaMemcpyAsync@PLT
movl $128, 116(%rsp)
movl 112(%rsp), %ecx
movq 0(%rbp), %r9
movl $0, %r8d
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L39
movq %rbx, %rdx
addq 80(%rsp), %rdx
movq %rbx, %rsi
addq 72(%rsp), %rsi
movq %rbx, %rdi
addq 64(%rsp), %rdi
movl $16384, %ecx
call _Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i
jmp .L39
.L48:
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movq 96(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
movsd .LC20(%rip), %xmm1
divsd %xmm0, %xmm1
movl $4, %edx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm2
movaps %xmm2, %xmm0
subss 28(%rsp), %xmm0
mulss .LC25(%rip), %xmm0
divss %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl $65536, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z11checkResultPfS_i
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq 56(%rsp), %rdi
call cudaFreeHost@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
movq 96(%rsp), %rdi
call cudaEventDestroy@PLT
addq $32, %r13
.L41:
movq (%r12), %rdi
call cudaStreamDestroy@PLT
addq $8, %r12
cmpq %r13, %r12
jne .L41
call cudaDeviceReset@PLT
leaq .LC27(%rip), %rdi
call system@PLT
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $1200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC28:
.string "_Z9sumArraysPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sumArraysPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1092616192
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -500134854
.long 1044740494
.align 8
.LC17:
.long -1598689907
.long 1070647031
.align 8
.LC20:
.long -1598689907
.long 1071695607
.section .rodata.cst4
.align 4
.LC25:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cmath>
#include <cstring>
#define NSTREAM 4
#define BDIM 128
void initialData(float *ip, int size)
{
for (int i = 0; i < size; i++)
{
ip[i] = (float)(rand() & 0xFF) / 10.0f;
}
}
void sumArraysOnHost(float *A, float *B, float *C, const int N)
{
for (int idx = 0; idx < N; idx++)
C[idx] = A[idx] + B[idx];
}
__global__ void sumArrays(float *A, float *B, float *C, const int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N)
{
for (int i = 0; i < N; ++i)
{
C[idx] = A[idx] + B[idx];
}
}
}
void checkResult(float *hostRef, float *gpuRef, const int N)
{
double epsilon = 1.0E-8;
bool match = true;
for (int i = 0; i < N; i++)
{
if (abs(hostRef[i] - gpuRef[i]) > epsilon)
{
match = false;
printf("Arrays do not match!\n");
printf("host %5.2f gpu %5.2f at %d\n", hostRef[i], gpuRef[i], i);
break;
}
}
if (match)
printf("Arrays match.\n\n");
}
int main(int argc, char **argv)
{
printf("> %s Starting...\n", argv[0]);
int dev = 0;
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
printf("> Using Device %d: %s\n", dev, deviceProp.name);
cudaSetDevice(dev);
// check if device support hyper-q
if (deviceProp.major < 3 || (deviceProp.major == 3 && deviceProp.minor < 5))
{
if (deviceProp.concurrentKernels == 0)
{
printf("> GPU does not support concurrent kernel execution (SM 3.5 or higher required)\n");
printf("> CUDA kernel runs will be serialized\n");
}
else
{
printf("> GPU does not support HyperQ\n");
printf("> CUDA kernel runs will have limited concurrency\n");
}
}
printf("> Compute Capability %d.%d hardware with %d multi-processors\n", deviceProp.major, deviceProp.minor, deviceProp.multiProcessorCount);
// set up data size of vectors
int nElem = 1 << 16;
printf("> vector size = %d\n", nElem);
size_t nBytes = nElem * sizeof(float);
// malloc pinned host memory for async memcpy
float *h_A, *h_B, *hostRef, *gpuRef;
cudaHostAlloc((void**)&h_A, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&h_B, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&gpuRef, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&hostRef, nBytes, cudaHostAllocDefault);
// initialize data at host side
initialData(h_A, nElem);
initialData(h_B, nElem);
memset(hostRef, 0, nBytes);
memset(gpuRef, 0, nBytes);
// add vector at host side for result checks
sumArraysOnHost(h_A, h_B, hostRef, nElem);
// malloc device global memory
float *d_A, *d_B, *d_C;
cudaMalloc((float**)&d_A, nBytes);
cudaMalloc((float**)&d_B, nBytes);
cudaMalloc((float**)&d_C, nBytes);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// invoke kernel at host side
dim3 block(BDIM);
dim3 grid((nElem + block.x - 1) / block.x);
printf("> grid (%d, %d) block (%d, %d)\n", grid.x, grid.y, block.x,block.y);
// sequential operation
cudaEventRecord(start, 0);
cudaMemcpy(d_A, h_A, nBytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, nBytes, cudaMemcpyHostToDevice);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float memcpy_h2d_time;
cudaEventElapsedTime(&memcpy_h2d_time, start, stop);
cudaEventRecord(start, 0);
sumArrays <<<grid, block >>>(d_A, d_B, d_C, nElem);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float kernel_time;
cudaEventElapsedTime(&kernel_time, start, stop);
cudaEventRecord(start, 0);
cudaMemcpy(gpuRef, d_C, nBytes, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float memcpy_d2h_time;
cudaEventElapsedTime(&memcpy_d2h_time, start, stop);
float itotal = kernel_time + memcpy_h2d_time + memcpy_d2h_time;
printf("\n");
printf("Measured timings (throughput):\n");
printf(" Memcpy host to device\t: %f ms (%f GB/s)\n", memcpy_h2d_time, (nBytes * 1e-6) / memcpy_h2d_time);
printf(" Memcpy device to host\t: %f ms (%f GB/s)\n", memcpy_d2h_time, (nBytes * 1e-6) / memcpy_d2h_time);
printf(" Kernel\t\t\t: %f ms (%f GB/s)\n", kernel_time, (nBytes * 2e-6) / kernel_time);
printf(" Total\t\t\t: %f ms (%f GB/s)\n", itotal, (nBytes * 2e-6) / itotal);
// grid parallel operation
int iElem = nElem / NSTREAM;
size_t iBytes = iElem * sizeof(float);
grid.x = (iElem + block.x - 1) / block.x;
cudaStream_t stream[NSTREAM];
for (int i = 0; i < NSTREAM; ++i)
{
cudaStreamCreate(&stream[i]);
}
cudaEventRecord(start, 0);
// initiate all work on the device asynchronously in depth-first order
for (int i = 0; i < NSTREAM; ++i)
{
int ioffset = i * iElem;
cudaMemcpyAsync(&d_A[ioffset], &h_A[ioffset], iBytes, cudaMemcpyHostToDevice, stream[i]);
cudaMemcpyAsync(&d_B[ioffset], &h_B[ioffset], iBytes, cudaMemcpyHostToDevice, stream[i]);
sumArrays <<<grid, block, 0, stream[i] >>>(&d_A[ioffset], &d_B[ioffset], &d_C[ioffset], iElem);
cudaMemcpyAsync(&gpuRef[ioffset], &d_C[ioffset], iBytes, cudaMemcpyDeviceToHost, stream[i]);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float execution_time;
cudaEventElapsedTime(&execution_time, start, stop);
printf("\n");
printf("Actual results from overlapped data transfers:\n");
printf(" overlap with %d streams : %f ms (%f GB/s)\n", NSTREAM, execution_time, (nBytes * 2e-6) / execution_time);
printf(" speedup : %f \n", ((itotal - execution_time) * 100.0f) / itotal);
// check kernel error
cudaGetLastError();
// check device results
checkResult(hostRef, gpuRef, nElem);
// free device global memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// free host memory
cudaFreeHost(h_A);
cudaFreeHost(h_B);
cudaFreeHost(hostRef);
cudaFreeHost(gpuRef);
// destroy events
cudaEventDestroy(start);
cudaEventDestroy(stop);
// destroy streams
for (int i = 0; i < NSTREAM; ++i)
{
cudaStreamDestroy(stream[i]);
}
cudaDeviceReset();
system("Pause");
return(0);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <cmath>
#include <cstring>
#define NSTREAM 4
#define BDIM 128
void initialData(float *ip, int size)
{
for (int i = 0; i < size; i++)
{
ip[i] = (float)(rand() & 0xFF) / 10.0f;
}
}
void sumArraysOnHost(float *A, float *B, float *C, const int N)
{
for (int idx = 0; idx < N; idx++)
C[idx] = A[idx] + B[idx];
}
__global__ void sumArrays(float *A, float *B, float *C, const int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N)
{
for (int i = 0; i < N; ++i)
{
C[idx] = A[idx] + B[idx];
}
}
}
void checkResult(float *hostRef, float *gpuRef, const int N)
{
double epsilon = 1.0E-8;
bool match = true;
for (int i = 0; i < N; i++)
{
if (abs(hostRef[i] - gpuRef[i]) > epsilon)
{
match = false;
printf("Arrays do not match!\n");
printf("host %5.2f gpu %5.2f at %d\n", hostRef[i], gpuRef[i], i);
break;
}
}
if (match)
printf("Arrays match.\n\n");
}
int main(int argc, char **argv)
{
printf("> %s Starting...\n", argv[0]);
int dev = 0;
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
printf("> Using Device %d: %s\n", dev, deviceProp.name);
hipSetDevice(dev);
// check if device support hyper-q
if (deviceProp.major < 3 || (deviceProp.major == 3 && deviceProp.minor < 5))
{
if (deviceProp.concurrentKernels == 0)
{
printf("> GPU does not support concurrent kernel execution (SM 3.5 or higher required)\n");
printf("> CUDA kernel runs will be serialized\n");
}
else
{
printf("> GPU does not support HyperQ\n");
printf("> CUDA kernel runs will have limited concurrency\n");
}
}
printf("> Compute Capability %d.%d hardware with %d multi-processors\n", deviceProp.major, deviceProp.minor, deviceProp.multiProcessorCount);
// set up data size of vectors
int nElem = 1 << 16;
printf("> vector size = %d\n", nElem);
size_t nBytes = nElem * sizeof(float);
// malloc pinned host memory for async memcpy
float *h_A, *h_B, *hostRef, *gpuRef;
hipHostAlloc((void**)&h_A, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&h_B, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&gpuRef, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&hostRef, nBytes, hipHostMallocDefault);
// initialize data at host side
initialData(h_A, nElem);
initialData(h_B, nElem);
memset(hostRef, 0, nBytes);
memset(gpuRef, 0, nBytes);
// add vector at host side for result checks
sumArraysOnHost(h_A, h_B, hostRef, nElem);
// malloc device global memory
float *d_A, *d_B, *d_C;
hipMalloc((float**)&d_A, nBytes);
hipMalloc((float**)&d_B, nBytes);
hipMalloc((float**)&d_C, nBytes);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// invoke kernel at host side
dim3 block(BDIM);
dim3 grid((nElem + block.x - 1) / block.x);
printf("> grid (%d, %d) block (%d, %d)\n", grid.x, grid.y, block.x,block.y);
// sequential operation
hipEventRecord(start, 0);
hipMemcpy(d_A, h_A, nBytes, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, nBytes, hipMemcpyHostToDevice);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float memcpy_h2d_time;
hipEventElapsedTime(&memcpy_h2d_time, start, stop);
hipEventRecord(start, 0);
sumArrays <<<grid, block >>>(d_A, d_B, d_C, nElem);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float kernel_time;
hipEventElapsedTime(&kernel_time, start, stop);
hipEventRecord(start, 0);
hipMemcpy(gpuRef, d_C, nBytes, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float memcpy_d2h_time;
hipEventElapsedTime(&memcpy_d2h_time, start, stop);
float itotal = kernel_time + memcpy_h2d_time + memcpy_d2h_time;
printf("\n");
printf("Measured timings (throughput):\n");
printf(" Memcpy host to device\t: %f ms (%f GB/s)\n", memcpy_h2d_time, (nBytes * 1e-6) / memcpy_h2d_time);
printf(" Memcpy device to host\t: %f ms (%f GB/s)\n", memcpy_d2h_time, (nBytes * 1e-6) / memcpy_d2h_time);
printf(" Kernel\t\t\t: %f ms (%f GB/s)\n", kernel_time, (nBytes * 2e-6) / kernel_time);
printf(" Total\t\t\t: %f ms (%f GB/s)\n", itotal, (nBytes * 2e-6) / itotal);
// grid parallel operation
int iElem = nElem / NSTREAM;
size_t iBytes = iElem * sizeof(float);
grid.x = (iElem + block.x - 1) / block.x;
hipStream_t stream[NSTREAM];
for (int i = 0; i < NSTREAM; ++i)
{
hipStreamCreate(&stream[i]);
}
hipEventRecord(start, 0);
// initiate all work on the device asynchronously in depth-first order
for (int i = 0; i < NSTREAM; ++i)
{
int ioffset = i * iElem;
hipMemcpyAsync(&d_A[ioffset], &h_A[ioffset], iBytes, hipMemcpyHostToDevice, stream[i]);
hipMemcpyAsync(&d_B[ioffset], &h_B[ioffset], iBytes, hipMemcpyHostToDevice, stream[i]);
sumArrays <<<grid, block, 0, stream[i] >>>(&d_A[ioffset], &d_B[ioffset], &d_C[ioffset], iElem);
hipMemcpyAsync(&gpuRef[ioffset], &d_C[ioffset], iBytes, hipMemcpyDeviceToHost, stream[i]);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float execution_time;
hipEventElapsedTime(&execution_time, start, stop);
printf("\n");
printf("Actual results from overlapped data transfers:\n");
printf(" overlap with %d streams : %f ms (%f GB/s)\n", NSTREAM, execution_time, (nBytes * 2e-6) / execution_time);
printf(" speedup : %f \n", ((itotal - execution_time) * 100.0f) / itotal);
// check kernel error
hipGetLastError();
// check device results
checkResult(hostRef, gpuRef, nElem);
// free device global memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// free host memory
hipHostFree(h_A);
hipHostFree(h_B);
hipHostFree(hostRef);
hipHostFree(gpuRef);
// destroy events
hipEventDestroy(start);
hipEventDestroy(stop);
// destroy streams
for (int i = 0; i < NSTREAM; ++i)
{
hipStreamDestroy(stream[i]);
}
hipDeviceReset();
system("Pause");
return(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <cmath>
#include <cstring>
#define NSTREAM 4
#define BDIM 128
void initialData(float *ip, int size)
{
for (int i = 0; i < size; i++)
{
ip[i] = (float)(rand() & 0xFF) / 10.0f;
}
}
void sumArraysOnHost(float *A, float *B, float *C, const int N)
{
for (int idx = 0; idx < N; idx++)
C[idx] = A[idx] + B[idx];
}
__global__ void sumArrays(float *A, float *B, float *C, const int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N)
{
for (int i = 0; i < N; ++i)
{
C[idx] = A[idx] + B[idx];
}
}
}
void checkResult(float *hostRef, float *gpuRef, const int N)
{
double epsilon = 1.0E-8;
bool match = true;
for (int i = 0; i < N; i++)
{
if (abs(hostRef[i] - gpuRef[i]) > epsilon)
{
match = false;
printf("Arrays do not match!\n");
printf("host %5.2f gpu %5.2f at %d\n", hostRef[i], gpuRef[i], i);
break;
}
}
if (match)
printf("Arrays match.\n\n");
}
int main(int argc, char **argv)
{
printf("> %s Starting...\n", argv[0]);
int dev = 0;
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
printf("> Using Device %d: %s\n", dev, deviceProp.name);
hipSetDevice(dev);
// check if device support hyper-q
if (deviceProp.major < 3 || (deviceProp.major == 3 && deviceProp.minor < 5))
{
if (deviceProp.concurrentKernels == 0)
{
printf("> GPU does not support concurrent kernel execution (SM 3.5 or higher required)\n");
printf("> CUDA kernel runs will be serialized\n");
}
else
{
printf("> GPU does not support HyperQ\n");
printf("> CUDA kernel runs will have limited concurrency\n");
}
}
printf("> Compute Capability %d.%d hardware with %d multi-processors\n", deviceProp.major, deviceProp.minor, deviceProp.multiProcessorCount);
// set up data size of vectors
int nElem = 1 << 16;
printf("> vector size = %d\n", nElem);
size_t nBytes = nElem * sizeof(float);
// malloc pinned host memory for async memcpy
float *h_A, *h_B, *hostRef, *gpuRef;
hipHostAlloc((void**)&h_A, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&h_B, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&gpuRef, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&hostRef, nBytes, hipHostMallocDefault);
// initialize data at host side
initialData(h_A, nElem);
initialData(h_B, nElem);
memset(hostRef, 0, nBytes);
memset(gpuRef, 0, nBytes);
// add vector at host side for result checks
sumArraysOnHost(h_A, h_B, hostRef, nElem);
// malloc device global memory
float *d_A, *d_B, *d_C;
hipMalloc((float**)&d_A, nBytes);
hipMalloc((float**)&d_B, nBytes);
hipMalloc((float**)&d_C, nBytes);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// invoke kernel at host side
dim3 block(BDIM);
dim3 grid((nElem + block.x - 1) / block.x);
printf("> grid (%d, %d) block (%d, %d)\n", grid.x, grid.y, block.x,block.y);
// sequential operation
hipEventRecord(start, 0);
hipMemcpy(d_A, h_A, nBytes, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, nBytes, hipMemcpyHostToDevice);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float memcpy_h2d_time;
hipEventElapsedTime(&memcpy_h2d_time, start, stop);
hipEventRecord(start, 0);
sumArrays <<<grid, block >>>(d_A, d_B, d_C, nElem);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float kernel_time;
hipEventElapsedTime(&kernel_time, start, stop);
hipEventRecord(start, 0);
hipMemcpy(gpuRef, d_C, nBytes, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float memcpy_d2h_time;
hipEventElapsedTime(&memcpy_d2h_time, start, stop);
float itotal = kernel_time + memcpy_h2d_time + memcpy_d2h_time;
printf("\n");
printf("Measured timings (throughput):\n");
printf(" Memcpy host to device\t: %f ms (%f GB/s)\n", memcpy_h2d_time, (nBytes * 1e-6) / memcpy_h2d_time);
printf(" Memcpy device to host\t: %f ms (%f GB/s)\n", memcpy_d2h_time, (nBytes * 1e-6) / memcpy_d2h_time);
printf(" Kernel\t\t\t: %f ms (%f GB/s)\n", kernel_time, (nBytes * 2e-6) / kernel_time);
printf(" Total\t\t\t: %f ms (%f GB/s)\n", itotal, (nBytes * 2e-6) / itotal);
// grid parallel operation
int iElem = nElem / NSTREAM;
size_t iBytes = iElem * sizeof(float);
grid.x = (iElem + block.x - 1) / block.x;
hipStream_t stream[NSTREAM];
for (int i = 0; i < NSTREAM; ++i)
{
hipStreamCreate(&stream[i]);
}
hipEventRecord(start, 0);
// initiate all work on the device asynchronously in depth-first order
for (int i = 0; i < NSTREAM; ++i)
{
int ioffset = i * iElem;
hipMemcpyAsync(&d_A[ioffset], &h_A[ioffset], iBytes, hipMemcpyHostToDevice, stream[i]);
hipMemcpyAsync(&d_B[ioffset], &h_B[ioffset], iBytes, hipMemcpyHostToDevice, stream[i]);
sumArrays <<<grid, block, 0, stream[i] >>>(&d_A[ioffset], &d_B[ioffset], &d_C[ioffset], iElem);
hipMemcpyAsync(&gpuRef[ioffset], &d_C[ioffset], iBytes, hipMemcpyDeviceToHost, stream[i]);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float execution_time;
hipEventElapsedTime(&execution_time, start, stop);
printf("\n");
printf("Actual results from overlapped data transfers:\n");
printf(" overlap with %d streams : %f ms (%f GB/s)\n", NSTREAM, execution_time, (nBytes * 2e-6) / execution_time);
printf(" speedup : %f \n", ((itotal - execution_time) * 100.0f) / itotal);
// check kernel error
hipGetLastError();
// check device results
checkResult(hostRef, gpuRef, nElem);
// free device global memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// free host memory
hipHostFree(h_A);
hipHostFree(h_B);
hipHostFree(hostRef);
hipHostFree(gpuRef);
// destroy events
hipEventDestroy(start);
hipEventDestroy(stop);
// destroy streams
for (int i = 0; i < NSTREAM; ++i)
{
hipStreamDestroy(stream[i]);
}
hipDeviceReset();
system("Pause");
return(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9sumArraysPfS_S_i
.globl _Z9sumArraysPfS_S_i
.p2align 8
.type _Z9sumArraysPfS_S_i,@function
_Z9sumArraysPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB0_2:
global_load_b32 v6, v[0:1], off
global_load_b32 v7, v[2:3], off
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v6, v7
global_store_b32 v[4:5], v6, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9sumArraysPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9sumArraysPfS_S_i, .Lfunc_end0-_Z9sumArraysPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9sumArraysPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9sumArraysPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <cmath>
#include <cstring>
#define NSTREAM 4
#define BDIM 128
void initialData(float *ip, int size)
{
for (int i = 0; i < size; i++)
{
ip[i] = (float)(rand() & 0xFF) / 10.0f;
}
}
void sumArraysOnHost(float *A, float *B, float *C, const int N)
{
for (int idx = 0; idx < N; idx++)
C[idx] = A[idx] + B[idx];
}
__global__ void sumArrays(float *A, float *B, float *C, const int N)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N)
{
for (int i = 0; i < N; ++i)
{
C[idx] = A[idx] + B[idx];
}
}
}
void checkResult(float *hostRef, float *gpuRef, const int N)
{
double epsilon = 1.0E-8;
bool match = true;
for (int i = 0; i < N; i++)
{
if (abs(hostRef[i] - gpuRef[i]) > epsilon)
{
match = false;
printf("Arrays do not match!\n");
printf("host %5.2f gpu %5.2f at %d\n", hostRef[i], gpuRef[i], i);
break;
}
}
if (match)
printf("Arrays match.\n\n");
}
int main(int argc, char **argv)
{
printf("> %s Starting...\n", argv[0]);
int dev = 0;
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
printf("> Using Device %d: %s\n", dev, deviceProp.name);
hipSetDevice(dev);
// check if device support hyper-q
if (deviceProp.major < 3 || (deviceProp.major == 3 && deviceProp.minor < 5))
{
if (deviceProp.concurrentKernels == 0)
{
printf("> GPU does not support concurrent kernel execution (SM 3.5 or higher required)\n");
printf("> CUDA kernel runs will be serialized\n");
}
else
{
printf("> GPU does not support HyperQ\n");
printf("> CUDA kernel runs will have limited concurrency\n");
}
}
printf("> Compute Capability %d.%d hardware with %d multi-processors\n", deviceProp.major, deviceProp.minor, deviceProp.multiProcessorCount);
// set up data size of vectors
int nElem = 1 << 16;
printf("> vector size = %d\n", nElem);
size_t nBytes = nElem * sizeof(float);
// malloc pinned host memory for async memcpy
float *h_A, *h_B, *hostRef, *gpuRef;
hipHostAlloc((void**)&h_A, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&h_B, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&gpuRef, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&hostRef, nBytes, hipHostMallocDefault);
// initialize data at host side
initialData(h_A, nElem);
initialData(h_B, nElem);
memset(hostRef, 0, nBytes);
memset(gpuRef, 0, nBytes);
// add vector at host side for result checks
sumArraysOnHost(h_A, h_B, hostRef, nElem);
// malloc device global memory
float *d_A, *d_B, *d_C;
hipMalloc((float**)&d_A, nBytes);
hipMalloc((float**)&d_B, nBytes);
hipMalloc((float**)&d_C, nBytes);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// invoke kernel at host side
dim3 block(BDIM);
dim3 grid((nElem + block.x - 1) / block.x);
printf("> grid (%d, %d) block (%d, %d)\n", grid.x, grid.y, block.x,block.y);
// sequential operation
hipEventRecord(start, 0);
hipMemcpy(d_A, h_A, nBytes, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, nBytes, hipMemcpyHostToDevice);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float memcpy_h2d_time;
hipEventElapsedTime(&memcpy_h2d_time, start, stop);
hipEventRecord(start, 0);
sumArrays <<<grid, block >>>(d_A, d_B, d_C, nElem);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float kernel_time;
hipEventElapsedTime(&kernel_time, start, stop);
hipEventRecord(start, 0);
hipMemcpy(gpuRef, d_C, nBytes, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float memcpy_d2h_time;
hipEventElapsedTime(&memcpy_d2h_time, start, stop);
float itotal = kernel_time + memcpy_h2d_time + memcpy_d2h_time;
printf("\n");
printf("Measured timings (throughput):\n");
printf(" Memcpy host to device\t: %f ms (%f GB/s)\n", memcpy_h2d_time, (nBytes * 1e-6) / memcpy_h2d_time);
printf(" Memcpy device to host\t: %f ms (%f GB/s)\n", memcpy_d2h_time, (nBytes * 1e-6) / memcpy_d2h_time);
printf(" Kernel\t\t\t: %f ms (%f GB/s)\n", kernel_time, (nBytes * 2e-6) / kernel_time);
printf(" Total\t\t\t: %f ms (%f GB/s)\n", itotal, (nBytes * 2e-6) / itotal);
// grid parallel operation
int iElem = nElem / NSTREAM;
size_t iBytes = iElem * sizeof(float);
grid.x = (iElem + block.x - 1) / block.x;
hipStream_t stream[NSTREAM];
for (int i = 0; i < NSTREAM; ++i)
{
hipStreamCreate(&stream[i]);
}
hipEventRecord(start, 0);
// initiate all work on the device asynchronously in depth-first order
for (int i = 0; i < NSTREAM; ++i)
{
int ioffset = i * iElem;
hipMemcpyAsync(&d_A[ioffset], &h_A[ioffset], iBytes, hipMemcpyHostToDevice, stream[i]);
hipMemcpyAsync(&d_B[ioffset], &h_B[ioffset], iBytes, hipMemcpyHostToDevice, stream[i]);
sumArrays <<<grid, block, 0, stream[i] >>>(&d_A[ioffset], &d_B[ioffset], &d_C[ioffset], iElem);
hipMemcpyAsync(&gpuRef[ioffset], &d_C[ioffset], iBytes, hipMemcpyDeviceToHost, stream[i]);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float execution_time;
hipEventElapsedTime(&execution_time, start, stop);
printf("\n");
printf("Actual results from overlapped data transfers:\n");
printf(" overlap with %d streams : %f ms (%f GB/s)\n", NSTREAM, execution_time, (nBytes * 2e-6) / execution_time);
printf(" speedup : %f \n", ((itotal - execution_time) * 100.0f) / itotal);
// check kernel error
hipGetLastError();
// check device results
checkResult(hostRef, gpuRef, nElem);
// free device global memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// free host memory
hipHostFree(h_A);
hipHostFree(h_B);
hipHostFree(hostRef);
hipHostFree(gpuRef);
// destroy events
hipEventDestroy(start);
hipEventDestroy(stop);
// destroy streams
for (int i = 0; i < NSTREAM; ++i)
{
hipStreamDestroy(stream[i]);
}
hipDeviceReset();
system("Pause");
return(0);
} | .text
.file "kernel.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11initialDataPfi
.LCPI0_0:
.long 0x41200000 # float 10
.text
.globl _Z11initialDataPfi
.p2align 4, 0x90
.type _Z11initialDataPfi,@function
_Z11initialDataPfi: # @_Z11initialDataPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11initialDataPfi, .Lfunc_end0-_Z11initialDataPfi
.cfi_endproc
# -- End function
.globl _Z15sumArraysOnHostPfS_S_i # -- Begin function _Z15sumArraysOnHostPfS_S_i
.p2align 4, 0x90
.type _Z15sumArraysOnHostPfS_S_i,@function
_Z15sumArraysOnHostPfS_S_i: # @_Z15sumArraysOnHostPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z15sumArraysOnHostPfS_S_i, .Lfunc_end1-_Z15sumArraysOnHostPfS_S_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__sumArraysPfS_S_i # -- Begin function _Z24__device_stub__sumArraysPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__sumArraysPfS_S_i,@function
_Z24__device_stub__sumArraysPfS_S_i: # @_Z24__device_stub__sumArraysPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9sumArraysPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z24__device_stub__sumArraysPfS_S_i, .Lfunc_end2-_Z24__device_stub__sumArraysPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11checkResultPfS_i
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.text
.globl _Z11checkResultPfS_i
.p2align 4, 0x90
.type _Z11checkResultPfS_i,@function
_Z11checkResultPfS_i: # @_Z11checkResultPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %edx, %edx
jle .LBB3_4
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ebx, %ebx
movaps .LCPI3_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%rsi,%rbx,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB3_5
# %bb.3: # in Loop: Header=BB3_2 Depth=1
incq %rbx
cmpq %rbx, %rax
jne .LBB3_2
.LBB3_4: # %.critedge
movl $.Lstr.1, %edi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB3_5:
.cfi_def_cfa_offset 32
movq %rdi, %r14
movl $.Lstr, %edi
movq %rsi, %r15
callq puts@PLT
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r15,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %ebx, %esi
movb $2, %al
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z11checkResultPfS_i, .Lfunc_end3-_Z11checkResultPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x41200000 # float 10
.LCPI4_3:
.long 0x42c80000 # float 100
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3fd0c6f7a0b5ed8d # double 0.26214399999999999
.LCPI4_2:
.quad 0x3fe0c6f7a0b5ed8d # double 0.52428799999999998
.LCPI4_5:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_4:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1720, %rsp # imm = 0x6B8
.cfi_def_cfa_offset 1776
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq (%rsi), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 248(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.4, %edi
xorl %esi, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
cmpl $3, 608(%rsp)
jl .LBB4_3
# %bb.1:
jne .LBB4_4
# %bb.2:
cmpl $4, 612(%rsp)
jg .LBB4_4
.LBB4_3: # %.sink.split
cmpl $0, 824(%rsp)
movl $.Lstr.4, %eax
movl $.Lstr.2, %edi
cmoveq %rax, %rdi
movl $.Lstr.5, %eax
movl $.Lstr.3, %ebx
cmoveq %rax, %rbx
callq puts@PLT
movq %rbx, %rdi
callq puts@PLT
.LBB4_4:
movl 608(%rsp), %esi
movl 612(%rsp), %edx
movl 636(%rsp), %ecx
xorl %ebx, %ebx
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $.L.str.10, %edi
movl $65536, %esi # imm = 0x10000
xorl %eax, %eax
callq printf
leaq 64(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
leaq 56(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
leaq 48(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
leaq 88(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
movq 64(%rsp), %r14
.p2align 4, 0x90
.LBB4_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%r14,%rbx,4)
incq %rbx
cmpq $65536, %rbx # imm = 0x10000
jne .LBB4_5
# %bb.6: # %_Z11initialDataPfi.exit
movq 56(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_7: # %.lr.ph.i88
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI4_0(%rip), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $65536, %r14 # imm = 0x10000
jne .LBB4_7
# %bb.8: # %_Z11initialDataPfi.exit92
movq 88(%rsp), %rbx
xorl %r14d, %r14d
movl $262144, %edx # imm = 0x40000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movq 48(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
xorl %esi, %esi
callq memset@PLT
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
.p2align 4, 0x90
.LBB4_9: # %.lr.ph.i93
# =>This Inner Loop Header: Depth=1
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rcx,%r14,4), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $65536, %r14 # imm = 0x10000
jne .LBB4_9
# %bb.10: # %_Z15sumArraysOnHostPfS_S_i.exit
movabsq $4294967424, %rbx # imm = 0x100000080
leaq 40(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $.L.str.11, %edi
movl $512, %esi # imm = 0x200
movl $1, %edx
movl $128, %ecx
movl $1, %r8d
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
movq 64(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 56(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 84(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 384(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl $65536, 96(%rsp) # imm = 0x10000
leaq 160(%rsp), %rax
movq %rax, 176(%rsp)
leaq 144(%rsp), %rax
movq %rax, 184(%rsp)
leaq 136(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rax
movq %rax, 200(%rsp)
leaq 208(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z9sumArraysPfS_S_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
movq 8(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
movq 24(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 76(%rsp), %rdi
callq hipEventElapsedTime
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 84(%rsp), %xmm0
addss 76(%rsp), %xmm0
movss %xmm0, 72(%rsp) # 4-byte Spill
movl $10, %edi
callq putchar@PLT
movl $.Lstr.6, %edi
callq puts@PLT
movss 84(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movl $.L.str.14, %edi
movb $2, %al
callq printf
movss 76(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movl $.L.str.15, %edi
movb $2, %al
callq printf
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI4_2(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movl $.L.str.16, %edi
movb $2, %al
callq printf
movss 72(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI4_2(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movl $.L.str.17, %edi
movb $2, %al
callq printf
.p2align 4, 0x90
.LBB4_13: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r14), %rdi
addq $208, %rdi
callq hipStreamCreate
addq $8, %r14
cmpq $32, %r14
jne .LBB4_13
# %bb.14:
movq 16(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
leaq 208(%rsp), %r15
leaq 104(%rsp), %r12
leaq 96(%rsp), %r13
leaq 176(%rsp), %rbp
jmp .LBB4_15
.p2align 4, 0x90
.LBB4_17: # in Loop: Header=BB4_15 Depth=1
movq 48(%rsp), %rdi
addq %r14, %rdi
movq 24(%rsp), %rsi
addq %r14, %rsi
movq (%r15), %r8
movl $65536, %edx # imm = 0x10000
movl $2, %ecx
callq hipMemcpyAsync
addq $65536, %r14 # imm = 0x10000
addq $8, %r15
cmpq $262144, %r14 # imm = 0x40000
je .LBB4_18
.LBB4_15: # =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rdi
addq %r14, %rdi
movq 64(%rsp), %rsi
addq %r14, %rsi
movq (%r15), %r8
movl $65536, %edx # imm = 0x10000
movl $1, %ecx
callq hipMemcpyAsync
movq 32(%rsp), %rdi
addq %r14, %rdi
movq 56(%rsp), %rsi
addq %r14, %rsi
movq (%r15), %r8
movl $65536, %edx # imm = 0x10000
movl $1, %ecx
callq hipMemcpyAsync
movq (%r15), %r9
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_17
# %bb.16: # in Loop: Header=BB4_15 Depth=1
movq 40(%rsp), %rax
addq %r14, %rax
movq 32(%rsp), %rcx
addq %r14, %rcx
movq 24(%rsp), %rdx
addq %r14, %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $16384, 156(%rsp) # imm = 0x4000
leaq 144(%rsp), %rax
movq %rax, 176(%rsp)
leaq 136(%rsp), %rax
movq %rax, 184(%rsp)
leaq 128(%rsp), %rax
movq %rax, 192(%rsp)
leaq 156(%rsp), %rax
movq %rax, 200(%rsp)
leaq 112(%rsp), %rdi
leaq 160(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
movl $_Z9sumArraysPfS_S_i, %edi
movq %rbp, %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_17
.LBB4_18:
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movl $10, %edi
callq putchar@PLT
movl $.Lstr.7, %edi
callq puts@PLT
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI4_2(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movl $.L.str.19, %edi
movl $4, %esi
movb $2, %al
callq printf
movss 72(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movaps %xmm1, %xmm0
subss 176(%rsp), %xmm0
mulss .LCPI4_3(%rip), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.20, %edi
movb $1, %al
callq printf
callq hipGetLastError
movq 88(%rsp), %r15
movq 48(%rsp), %r14
movaps .LCPI4_4(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI4_5(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB4_19: # %.lr.ph.i97
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%r14,%rbx,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB4_20
# %bb.21: # in Loop: Header=BB4_19 Depth=1
incq %rbx
cmpq $65536, %rbx # imm = 0x10000
jne .LBB4_19
# %bb.22: # %.critedge.i
movl $.Lstr.1, %edi
callq puts@PLT
jmp .LBB4_23
.LBB4_20:
movl $.Lstr, %edi
callq puts@PLT
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %ebx, %esi
movb $2, %al
callq printf
.LBB4_23: # %_Z11checkResultPfS_i.exit
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipHostFree
movq 56(%rsp), %rdi
callq hipHostFree
movq 88(%rsp), %rdi
callq hipHostFree
movq 48(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_24: # =>This Inner Loop Header: Depth=1
movq 208(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
incq %rbx
cmpq $4, %rbx
jne .LBB4_24
# %bb.25:
callq hipDeviceReset
movl $.L.str.21, %edi
callq system
xorl %eax, %eax
addq $1720, %rsp # imm = 0x6B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sumArraysPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9sumArraysPfS_S_i,@object # @_Z9sumArraysPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9sumArraysPfS_S_i
.p2align 3, 0x0
_Z9sumArraysPfS_S_i:
.quad _Z24__device_stub__sumArraysPfS_S_i
.size _Z9sumArraysPfS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "host %5.2f gpu %5.2f at %d\n"
.size .L.str.1, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "> %s Starting...\n"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "> Using Device %d: %s\n"
.size .L.str.4, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "> Compute Capability %d.%d hardware with %d multi-processors\n"
.size .L.str.9, 62
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "> vector size = %d\n"
.size .L.str.10, 20
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "> grid (%d, %d) block (%d, %d)\n"
.size .L.str.11, 32
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " Memcpy host to device\t: %f ms (%f GB/s)\n"
.size .L.str.14, 42
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " Memcpy device to host\t: %f ms (%f GB/s)\n"
.size .L.str.15, 42
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " Kernel\t\t\t: %f ms (%f GB/s)\n"
.size .L.str.16, 29
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " Total\t\t\t: %f ms (%f GB/s)\n"
.size .L.str.17, 28
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " overlap with %d streams : %f ms (%f GB/s)\n"
.size .L.str.19, 44
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " speedup : %f \n"
.size .L.str.20, 31
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Pause"
.size .L.str.21, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9sumArraysPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Arrays do not match!"
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Arrays match.\n"
.size .Lstr.1, 15
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "> GPU does not support HyperQ"
.size .Lstr.2, 30
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "> CUDA kernel runs will have limited concurrency"
.size .Lstr.3, 49
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "> GPU does not support concurrent kernel execution (SM 3.5 or higher required)"
.size .Lstr.4, 79
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "> CUDA kernel runs will be serialized"
.size .Lstr.5, 38
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Measured timings (throughput):"
.size .Lstr.6, 31
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Actual results from overlapped data transfers:"
.size .Lstr.7, 47
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sumArraysPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9sumArraysPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9sumArraysPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x178], !P0 ; /* 0x00005e0006007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fcc0003f06070 */
/*00d0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0100*/ @!P0 BRA 0x940 ; /* 0x0000083000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fc80007ffe1ff */
/*0120*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f04270 */
/*0130*/ @!P0 BRA 0x810 ; /* 0x000006d000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x5b0 ; /* 0x0000044000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001ea8000c1e1900 */
/*0190*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*01c0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0003e8000c101904 */
/*0200*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0005e8000c101904 */
/*0240*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0270*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0007e8000c101904 */
/*0280*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f24000c1e1900 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*02b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*02c0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x002f24000c1e1900 */
/*02e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*02f0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0003e8000c101904 */
/*0300*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x004f24000c1e1900 */
/*0320*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0330*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0005e8000c101904 */
/*0340*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0350*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x008f24000c1e1900 */
/*0360*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0370*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0007e8000c101904 */
/*0380*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f24000c1e1900 */
/*03a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*03b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x002f24000c1e1900 */
/*03e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*03f0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0003e8000c101904 */
/*0400*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x004f24000c1e1900 */
/*0420*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0430*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0005e8000c101904 */
/*0440*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x008f24000c1e1900 */
/*0460*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0470*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0007e8000c101904 */
/*0480*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f24000c1e1900 */
/*04a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*04b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*04c0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x002f24000c1e1900 */
/*04e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*04f0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0500*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x004f22000c1e1900 */
/*0520*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0530*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0540*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0550*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0560*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x008ea2000c1e1900 */
/*0570*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*0580*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fca0000000000 */
/*0590*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001ee000c101904 */
/*05a0*/ @P1 BRA 0x180 ; /* 0xfffffbd000001947 */
/* 0x000fea000383ffff */
/*05b0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*05c0*/ @!P1 BRA 0x7f0 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*05d0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001ea8000c1e1900 */
/*05e0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea4000c1e1900 */
/*05f0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*0600*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*0610*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0620*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea4000c1e1900 */
/*0630*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0640*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0003e8000c101904 */
/*0650*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0670*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0680*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0005e8000c101904 */
/*0690*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ee8000c1e1900 */
/*06a0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ee4000c1e1900 */
/*06b0*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*06c0*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0007e8000c101904 */
/*06d0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001f28000c1e1900 */
/*06e0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000f24000c1e1900 */
/*06f0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*0700*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*0710*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0720*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x002f24000c1e1900 */
/*0730*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*0740*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0750*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000f28000c1e1900 */
/*0760*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x004f24000c1e1900 */
/*0770*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0780*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*0790*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x008ea2000c1e1900 */
/*07b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*07c0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fca0000000000 */
/*07e0*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*07f0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0800*/ @!P0 BRA 0x940 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0810*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x001ea8000c1e1900 */
/*0820*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea4000c1e1900 */
/*0830*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*0840*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*0850*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea4000c1e1900 */
/*0870*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0880*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0890*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*08a0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea2000c1e1900 */
/*08b0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*08d0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*08e0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*08f0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea2000c1e1900 */
/*0900*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0910*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fca0000000000 */
/*0920*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001ee000c101904 */
/*0930*/ @P0 BRA 0x810 ; /* 0xfffffed000000947 */
/* 0x001fea000383ffff */
/*0940*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0950*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0960*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea2000c1e1900 */
/*0980*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0990*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*09a0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*09b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*09c0*/ @P0 BRA 0x960 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*09d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09e0*/ BRA 0x9e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9sumArraysPfS_S_i
.globl _Z9sumArraysPfS_S_i
.p2align 8
.type _Z9sumArraysPfS_S_i,@function
_Z9sumArraysPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB0_2:
global_load_b32 v6, v[0:1], off
global_load_b32 v7, v[2:3], off
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v6, v7
global_store_b32 v[4:5], v6, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9sumArraysPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9sumArraysPfS_S_i, .Lfunc_end0-_Z9sumArraysPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9sumArraysPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9sumArraysPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00058680_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initialDataPfi
.type _Z11initialDataPfi, @function
_Z11initialDataPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11initialDataPfi, .-_Z11initialDataPfi
.globl _Z15sumArraysOnHostPfS_S_i
.type _Z15sumArraysOnHostPfS_S_i, @function
_Z15sumArraysOnHostPfS_S_i:
.LFB2058:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L13:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE2058:
.size _Z15sumArraysOnHostPfS_S_i, .-_Z15sumArraysOnHostPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Arrays do not match!\n"
.LC4:
.string "host %5.2f gpu %5.2f at %d\n"
.LC5:
.string "Arrays match.\n\n"
.text
.globl _Z11checkResultPfS_i
.type _Z11checkResultPfS_i, @function
_Z11checkResultPfS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %edx, %edx
jle .L16
movq %rdi, %rbp
movq %rsi, %rbx
movl $0, %r12d
movss .LC1(%rip), %xmm2
movsd .LC2(%rip), %xmm1
.L20:
movss 0(%rbp), %xmm0
subss (%rbx), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L25
addl $1, %r12d
addq $4, %rbp
addq $4, %rbx
cmpl %r12d, %edx
jne .L20
.L16:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L15:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movl %r12d, %edx
pxor %xmm1, %xmm1
cvtss2sd (%rbx), %xmm1
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
jmp .L15
.cfi_endproc
.LFE2059:
.size _Z11checkResultPfS_i, .-_Z11checkResultPfS_i
.globl _Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9sumArraysPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i
.globl _Z9sumArraysPfS_S_i
.type _Z9sumArraysPfS_S_i, @function
_Z9sumArraysPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9sumArraysPfS_S_i, .-_Z9sumArraysPfS_S_i
.section .rodata.str1.1
.LC6:
.string "> %s Starting...\n"
.LC7:
.string "> Using Device %d: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "> GPU does not support concurrent kernel execution (SM 3.5 or higher required)\n"
.align 8
.LC9:
.string "> CUDA kernel runs will be serialized\n"
.align 8
.LC10:
.string "> GPU does not support HyperQ\n"
.align 8
.LC11:
.string "> CUDA kernel runs will have limited concurrency\n"
.align 8
.LC12:
.string "> Compute Capability %d.%d hardware with %d multi-processors\n"
.section .rodata.str1.1
.LC13:
.string "> vector size = %d\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "> grid (%d, %d) block (%d, %d)\n"
.section .rodata.str1.1
.LC15:
.string "\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "Measured timings (throughput):\n"
.align 8
.LC18:
.string " Memcpy host to device\t: %f ms (%f GB/s)\n"
.align 8
.LC19:
.string " Memcpy device to host\t: %f ms (%f GB/s)\n"
.section .rodata.str1.1
.LC21:
.string " Kernel\t\t\t: %f ms (%f GB/s)\n"
.LC22:
.string " Total\t\t\t: %f ms (%f GB/s)\n"
.section .rodata.str1.8
.align 8
.LC23:
.string "Actual results from overlapped data transfers:\n"
.align 8
.LC24:
.string " overlap with %d streams : %f ms (%f GB/s)\n"
.align 8
.LC26:
.string " speedup : %f \n"
.section .rodata.str1.1
.LC27:
.string "Pause"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1200, %rsp
.cfi_def_cfa_offset 1248
movq %fs:40, %rax
movq %rax, 1192(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 160(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl $0, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movl 520(%rsp), %eax
cmpl $2, %eax
jle .L35
cmpl $3, %eax
je .L46
.L36:
movl 548(%rsp), %r8d
movl 524(%rsp), %ecx
movl 520(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $65536, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
leaq 56(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
leaq 48(%rsp), %rdi
movl $0, %edx
movl $262144, %esi
call cudaHostAlloc@PLT
movl $65536, %esi
movq 32(%rsp), %rdi
call _Z11initialDataPfi
movl $65536, %esi
movq 40(%rsp), %rdi
call _Z11initialDataPfi
movl $262144, %edx
movl $0, %esi
movq 48(%rsp), %rdi
call memset@PLT
movl $262144, %edx
movl $0, %esi
movq 56(%rsp), %rdi
call memset@PLT
movl $65536, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z15sumArraysOnHostPfS_S_i
leaq 64(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, 112(%rsp)
movl $1, 124(%rsp)
movl $1, %r9d
movl $128, %r8d
movl $1, %ecx
movl $512, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $262144, %edx
movq 32(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $262144, %edx
movq 40(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movq 96(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 16(%rsp), %rdi
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl $512, 116(%rsp)
movl $1, 120(%rsp)
movl $128, 104(%rsp)
movl $1, 108(%rsp)
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L38:
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movq 96(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $262144, %edx
movq 80(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movq 96(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 24(%rsp), %rdi
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 20(%rsp), %xmm0
addss 16(%rsp), %xmm0
addss 24(%rsp), %xmm0
movss %xmm0, 12(%rsp)
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
movsd .LC17(%rip), %xmm1
divsd %xmm0, %xmm1
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 24(%rsp), %xmm0
movsd .LC17(%rip), %xmm1
divsd %xmm0, %xmm1
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
movsd .LC20(%rip), %xmm1
divsd %xmm0, %xmm1
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movsd .LC20(%rip), %xmm1
divsd %xmm0, %xmm1
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq 128(%rsp), %r13
movq %r13, %rdi
call cudaStreamCreate@PLT
leaq 136(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 144(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 152(%rsp), %rdi
call cudaStreamCreate@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq %r13, %r12
movq %r13, %rbp
movl $0, %ebx
jmp .L40
.L46:
cmpl $4, 524(%rsp)
jg .L36
.L35:
cmpl $0, 736(%rsp)
jne .L37
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L37:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L47:
movl $65536, %ecx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i
jmp .L38
.L39:
movq %rbx, %rsi
addq 80(%rsp), %rsi
movq %rbx, %rdi
addq 56(%rsp), %rdi
movq (%r14), %r8
movl $2, %ecx
movl $65536, %edx
call cudaMemcpyAsync@PLT
addq $8, %rbp
addq $65536, %rbx
cmpq $262144, %rbx
je .L48
.L40:
movq %rbp, %r14
movq %rbx, %rsi
addq 32(%rsp), %rsi
movq %rbx, %rdi
addq 64(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $65536, %edx
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq %rbx, %rdi
addq 72(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movl $65536, %edx
call cudaMemcpyAsync@PLT
movl $128, 116(%rsp)
movl 112(%rsp), %ecx
movq 0(%rbp), %r9
movl $0, %r8d
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L39
movq %rbx, %rdx
addq 80(%rsp), %rdx
movq %rbx, %rsi
addq 72(%rsp), %rsi
movq %rbx, %rdi
addq 64(%rsp), %rdi
movl $16384, %ecx
call _Z33__device_stub__Z9sumArraysPfS_S_iPfS_S_i
jmp .L39
.L48:
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movq 96(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
movsd .LC20(%rip), %xmm1
divsd %xmm0, %xmm1
movl $4, %edx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm2
movaps %xmm2, %xmm0
subss 28(%rsp), %xmm0
mulss .LC25(%rip), %xmm0
divss %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl $65536, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z11checkResultPfS_i
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq 56(%rsp), %rdi
call cudaFreeHost@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
movq 96(%rsp), %rdi
call cudaEventDestroy@PLT
addq $32, %r13
.L41:
movq (%r12), %rdi
call cudaStreamDestroy@PLT
addq $8, %r12
cmpq %r13, %r12
jne .L41
call cudaDeviceReset@PLT
leaq .LC27(%rip), %rdi
call system@PLT
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L49
movl $0, %eax
addq $1200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC28:
.string "_Z9sumArraysPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sumArraysPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1092616192
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -500134854
.long 1044740494
.align 8
.LC17:
.long -1598689907
.long 1070647031
.align 8
.LC20:
.long -1598689907
.long 1071695607
.section .rodata.cst4
.align 4
.LC25:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11initialDataPfi
.LCPI0_0:
.long 0x41200000 # float 10
.text
.globl _Z11initialDataPfi
.p2align 4, 0x90
.type _Z11initialDataPfi,@function
_Z11initialDataPfi: # @_Z11initialDataPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11initialDataPfi, .Lfunc_end0-_Z11initialDataPfi
.cfi_endproc
# -- End function
.globl _Z15sumArraysOnHostPfS_S_i # -- Begin function _Z15sumArraysOnHostPfS_S_i
.p2align 4, 0x90
.type _Z15sumArraysOnHostPfS_S_i,@function
_Z15sumArraysOnHostPfS_S_i: # @_Z15sumArraysOnHostPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z15sumArraysOnHostPfS_S_i, .Lfunc_end1-_Z15sumArraysOnHostPfS_S_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__sumArraysPfS_S_i # -- Begin function _Z24__device_stub__sumArraysPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__sumArraysPfS_S_i,@function
_Z24__device_stub__sumArraysPfS_S_i: # @_Z24__device_stub__sumArraysPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9sumArraysPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z24__device_stub__sumArraysPfS_S_i, .Lfunc_end2-_Z24__device_stub__sumArraysPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11checkResultPfS_i
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.text
.globl _Z11checkResultPfS_i
.p2align 4, 0x90
.type _Z11checkResultPfS_i,@function
_Z11checkResultPfS_i: # @_Z11checkResultPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %edx, %edx
jle .LBB3_4
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ebx, %ebx
movaps .LCPI3_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%rsi,%rbx,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB3_5
# %bb.3: # in Loop: Header=BB3_2 Depth=1
incq %rbx
cmpq %rbx, %rax
jne .LBB3_2
.LBB3_4: # %.critedge
movl $.Lstr.1, %edi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB3_5:
.cfi_def_cfa_offset 32
movq %rdi, %r14
movl $.Lstr, %edi
movq %rsi, %r15
callq puts@PLT
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r15,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %ebx, %esi
movb $2, %al
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z11checkResultPfS_i, .Lfunc_end3-_Z11checkResultPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x41200000 # float 10
.LCPI4_3:
.long 0x42c80000 # float 100
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3fd0c6f7a0b5ed8d # double 0.26214399999999999
.LCPI4_2:
.quad 0x3fe0c6f7a0b5ed8d # double 0.52428799999999998
.LCPI4_5:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_4:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1720, %rsp # imm = 0x6B8
.cfi_def_cfa_offset 1776
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq (%rsi), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
leaq 248(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.4, %edi
xorl %esi, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
cmpl $3, 608(%rsp)
jl .LBB4_3
# %bb.1:
jne .LBB4_4
# %bb.2:
cmpl $4, 612(%rsp)
jg .LBB4_4
.LBB4_3: # %.sink.split
cmpl $0, 824(%rsp)
movl $.Lstr.4, %eax
movl $.Lstr.2, %edi
cmoveq %rax, %rdi
movl $.Lstr.5, %eax
movl $.Lstr.3, %ebx
cmoveq %rax, %rbx
callq puts@PLT
movq %rbx, %rdi
callq puts@PLT
.LBB4_4:
movl 608(%rsp), %esi
movl 612(%rsp), %edx
movl 636(%rsp), %ecx
xorl %ebx, %ebx
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $.L.str.10, %edi
movl $65536, %esi # imm = 0x10000
xorl %eax, %eax
callq printf
leaq 64(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
leaq 56(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
leaq 48(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
leaq 88(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
xorl %edx, %edx
callq hipHostAlloc
movq 64(%rsp), %r14
.p2align 4, 0x90
.LBB4_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%r14,%rbx,4)
incq %rbx
cmpq $65536, %rbx # imm = 0x10000
jne .LBB4_5
# %bb.6: # %_Z11initialDataPfi.exit
movq 56(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_7: # %.lr.ph.i88
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI4_0(%rip), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $65536, %r14 # imm = 0x10000
jne .LBB4_7
# %bb.8: # %_Z11initialDataPfi.exit92
movq 88(%rsp), %rbx
xorl %r14d, %r14d
movl $262144, %edx # imm = 0x40000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movq 48(%rsp), %rdi
movl $262144, %edx # imm = 0x40000
xorl %esi, %esi
callq memset@PLT
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
.p2align 4, 0x90
.LBB4_9: # %.lr.ph.i93
# =>This Inner Loop Header: Depth=1
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rcx,%r14,4), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $65536, %r14 # imm = 0x10000
jne .LBB4_9
# %bb.10: # %_Z15sumArraysOnHostPfS_S_i.exit
movabsq $4294967424, %rbx # imm = 0x100000080
leaq 40(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $.L.str.11, %edi
movl $512, %esi # imm = 0x200
movl $1, %edx
movl $128, %ecx
movl $1, %r8d
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
movq 64(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 56(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 84(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 384(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl $65536, 96(%rsp) # imm = 0x10000
leaq 160(%rsp), %rax
movq %rax, 176(%rsp)
leaq 144(%rsp), %rax
movq %rax, 184(%rsp)
leaq 136(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rax
movq %rax, 200(%rsp)
leaq 208(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z9sumArraysPfS_S_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
movq 8(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
movq 24(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 76(%rsp), %rdi
callq hipEventElapsedTime
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 84(%rsp), %xmm0
addss 76(%rsp), %xmm0
movss %xmm0, 72(%rsp) # 4-byte Spill
movl $10, %edi
callq putchar@PLT
movl $.Lstr.6, %edi
callq puts@PLT
movss 84(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movl $.L.str.14, %edi
movb $2, %al
callq printf
movss 76(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movl $.L.str.15, %edi
movb $2, %al
callq printf
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI4_2(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movl $.L.str.16, %edi
movb $2, %al
callq printf
movss 72(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI4_2(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movl $.L.str.17, %edi
movb $2, %al
callq printf
.p2align 4, 0x90
.LBB4_13: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r14), %rdi
addq $208, %rdi
callq hipStreamCreate
addq $8, %r14
cmpq $32, %r14
jne .LBB4_13
# %bb.14:
movq 16(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
leaq 208(%rsp), %r15
leaq 104(%rsp), %r12
leaq 96(%rsp), %r13
leaq 176(%rsp), %rbp
jmp .LBB4_15
.p2align 4, 0x90
.LBB4_17: # in Loop: Header=BB4_15 Depth=1
movq 48(%rsp), %rdi
addq %r14, %rdi
movq 24(%rsp), %rsi
addq %r14, %rsi
movq (%r15), %r8
movl $65536, %edx # imm = 0x10000
movl $2, %ecx
callq hipMemcpyAsync
addq $65536, %r14 # imm = 0x10000
addq $8, %r15
cmpq $262144, %r14 # imm = 0x40000
je .LBB4_18
.LBB4_15: # =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rdi
addq %r14, %rdi
movq 64(%rsp), %rsi
addq %r14, %rsi
movq (%r15), %r8
movl $65536, %edx # imm = 0x10000
movl $1, %ecx
callq hipMemcpyAsync
movq 32(%rsp), %rdi
addq %r14, %rdi
movq 56(%rsp), %rsi
addq %r14, %rsi
movq (%r15), %r8
movl $65536, %edx # imm = 0x10000
movl $1, %ecx
callq hipMemcpyAsync
movq (%r15), %r9
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_17
# %bb.16: # in Loop: Header=BB4_15 Depth=1
movq 40(%rsp), %rax
addq %r14, %rax
movq 32(%rsp), %rcx
addq %r14, %rcx
movq 24(%rsp), %rdx
addq %r14, %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $16384, 156(%rsp) # imm = 0x4000
leaq 144(%rsp), %rax
movq %rax, 176(%rsp)
leaq 136(%rsp), %rax
movq %rax, 184(%rsp)
leaq 128(%rsp), %rax
movq %rax, 192(%rsp)
leaq 156(%rsp), %rax
movq %rax, 200(%rsp)
leaq 112(%rsp), %rdi
leaq 160(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
movl $_Z9sumArraysPfS_S_i, %edi
movq %rbp, %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_17
.LBB4_18:
movq 8(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movl $10, %edi
callq putchar@PLT
movl $.Lstr.7, %edi
callq puts@PLT
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI4_2(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movl $.L.str.19, %edi
movl $4, %esi
movb $2, %al
callq printf
movss 72(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movaps %xmm1, %xmm0
subss 176(%rsp), %xmm0
mulss .LCPI4_3(%rip), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.20, %edi
movb $1, %al
callq printf
callq hipGetLastError
movq 88(%rsp), %r15
movq 48(%rsp), %r14
movaps .LCPI4_4(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI4_5(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB4_19: # %.lr.ph.i97
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%r14,%rbx,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB4_20
# %bb.21: # in Loop: Header=BB4_19 Depth=1
incq %rbx
cmpq $65536, %rbx # imm = 0x10000
jne .LBB4_19
# %bb.22: # %.critedge.i
movl $.Lstr.1, %edi
callq puts@PLT
jmp .LBB4_23
.LBB4_20:
movl $.Lstr, %edi
callq puts@PLT
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %ebx, %esi
movb $2, %al
callq printf
.LBB4_23: # %_Z11checkResultPfS_i.exit
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipHostFree
movq 56(%rsp), %rdi
callq hipHostFree
movq 88(%rsp), %rdi
callq hipHostFree
movq 48(%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_24: # =>This Inner Loop Header: Depth=1
movq 208(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
incq %rbx
cmpq $4, %rbx
jne .LBB4_24
# %bb.25:
callq hipDeviceReset
movl $.L.str.21, %edi
callq system
xorl %eax, %eax
addq $1720, %rsp # imm = 0x6B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sumArraysPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9sumArraysPfS_S_i,@object # @_Z9sumArraysPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9sumArraysPfS_S_i
.p2align 3, 0x0
_Z9sumArraysPfS_S_i:
.quad _Z24__device_stub__sumArraysPfS_S_i
.size _Z9sumArraysPfS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "host %5.2f gpu %5.2f at %d\n"
.size .L.str.1, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "> %s Starting...\n"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "> Using Device %d: %s\n"
.size .L.str.4, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "> Compute Capability %d.%d hardware with %d multi-processors\n"
.size .L.str.9, 62
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "> vector size = %d\n"
.size .L.str.10, 20
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "> grid (%d, %d) block (%d, %d)\n"
.size .L.str.11, 32
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " Memcpy host to device\t: %f ms (%f GB/s)\n"
.size .L.str.14, 42
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " Memcpy device to host\t: %f ms (%f GB/s)\n"
.size .L.str.15, 42
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " Kernel\t\t\t: %f ms (%f GB/s)\n"
.size .L.str.16, 29
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " Total\t\t\t: %f ms (%f GB/s)\n"
.size .L.str.17, 28
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " overlap with %d streams : %f ms (%f GB/s)\n"
.size .L.str.19, 44
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " speedup : %f \n"
.size .L.str.20, 31
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Pause"
.size .L.str.21, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9sumArraysPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Arrays do not match!"
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Arrays match.\n"
.size .Lstr.1, 15
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "> GPU does not support HyperQ"
.size .Lstr.2, 30
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "> CUDA kernel runs will have limited concurrency"
.size .Lstr.3, 49
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "> GPU does not support concurrent kernel execution (SM 3.5 or higher required)"
.size .Lstr.4, 79
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "> CUDA kernel runs will be serialized"
.size .Lstr.5, 38
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Measured timings (throughput):"
.size .Lstr.6, 31
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Actual results from overlapped data transfers:"
.size .Lstr.7, 47
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sumArraysPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9sumArraysPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Segmented Scan CUDA sample
*
* Original:
* "Efficient Parallel Scan Algorithms for GPUs",
* Shubhabrata Sengupta,Mark Harris, Michael Garland.
* https://research.nvidia.com/sites/default/files/publications/nvr-2008-003.pdf
*
* via
* aokomoriuta san
* http://qiita.com/aokomoriuta/items/3c2a80181a01c7f22e7f
*
* Using a template kernel.cu in NVIDIA Cuda Toolkit 5.5
*/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
template<typename T>
class AddOp {
public:
static __device__ inline T apply(const T a, const T b) {
return a + b;
}
};
template<typename T>
class MaxOp {
public:
static __device__ inline T apply(const T a, const T b) {
return max(a,b);
}
};
cudaError_t segmentedScanTest(int *c, const int *a, const int *b, unsigned int size);
template<typename T, class OP>
__device__ void compute_segscan(volatile T *p, volatile int *hd,
const unsigned int tid, const unsigned int offset) {
const unsigned int lane = tid & 31;
if (lane >= offset) {
p[tid] = hd[tid] ? p[tid] : OP::apply(p[tid - offset],p[tid]);
hd[tid] = hd[tid - offset] | hd[tid];
}
}
/**
* Figure 6
*/
template<typename T, int Kind, class OP>
__device__ T segscan_warp(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int lane = tid & 31;
compute_segscan<T,OP>(p, hd, tid, 1);
compute_segscan<T,OP>(p, hd, tid, 2);
compute_segscan<T,OP>(p, hd, tid, 4);
compute_segscan<T,OP>(p, hd, tid, 8);
compute_segscan<T,OP>(p, hd, tid, 16);
if (Kind == 0)
return p[tid];
else
return (lane > 0) ? p[tid - 1] : 0;
}
template <typename T, class OP>
__global__ void segscan_warp_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
segscan_warp<int,0,OP>(dst, flag, threadIdx.x);
}
/**
* Figure 3
*/
template<typename T, int Kind, class OP>
__device__ T scan_warp(volatile T *p,
const unsigned int tid = threadIdx.x) {
const int lane = tid & 31;
if (lane >= 1)
p[tid] = OP::apply(p[tid - 1], p[tid]);
if (lane >= 2)
p[tid] = OP::apply(p[tid - 2], p[tid]);
if (lane >= 4)
p[tid] = OP::apply(p[tid - 4], p[tid]);
if (lane >= 8)
p[tid] = OP::apply(p[tid - 8], p[tid]);
if (lane >= 16)
p[tid] = OP::apply(p[tid - 16], p[tid]);
return p[tid];
}
/**
* Figure 7
*/
template<typename T, int Kind, class OP>
__device__ T segscan_warp2(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int lane = tid & 31;
if (hd[tid])
hd[tid] = lane;
int mindex = scan_warp<T,Kind, MaxOp<T> >(hd,tid);
if (lane >= mindex + 1)
p[tid] = OP::apply(p[tid - 1],p[tid]);
if (lane >= mindex + 2)
p[tid] = OP::apply(p[tid - 2], p[tid]);
if (lane >= mindex + 4)
p[tid] = OP::apply(p[tid - 4], p[tid]);
if (lane >= mindex + 8)
p[tid] = OP::apply(p[tid - 8], p[tid]);
if (lane >= mindex + 16)
p[tid] = OP::apply(p[tid - 16], p[tid]);
if (Kind == 0)
return p[tid];
else
return (lane > 0 && mindex != lane) ? p[tid - 1] : 0;
}
template <typename T, class OP>
__global__ void segscan_warp2_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
dst[tid] = segscan_warp2<int,0, OP>(dst, flag, tid);
}
/**
* Figure 10
*/
template<typename T, int Kind, class OP>
__device__ T segscan_block(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int warpid = tid >> 5;
const unsigned int warp_first = warpid << 5;
const unsigned int warp_last = warp_first + 31;
// step 1a
bool warp_is_open = (hd[warp_first] == 0);
__syncthreads();
// step 1b
T val = segscan_warp2<T,Kind, OP>(p, hd, tid);
// step 2a
T warp_total = p[warp_last];
// step 2b
int warp_flag = hd[warp_last] != 0 || !warp_is_open;
bool will_accumulate = warp_is_open && hd[tid] == 0;
__syncthreads();
// step 2c
if (tid == warp_last) {
p[warpid] = warp_total;
hd[warpid] = warp_flag;
}
__syncthreads();
// step 3
if (warpid == 0)
segscan_warp2<T,0, OP>(p, hd, tid);
__syncthreads();
// step 4
if (warpid != 0 && will_accumulate)
val = OP::apply( p[tid - 1] , val);
p[tid] = val;
__syncthreads();
return val;
}
template <typename T, class OP>
__global__ void segscan_block_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
dst[tid] = segscan_block<int,0, OP>(dst, flag, tid);
}
template <typename T, class OP, unsigned int SIZE>
__global__ void segscan_block_kernel_smem(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
__shared__ T smem[SIZE];
smem[tid] = src[tid];
dst[tid] = segscan_block<int,0, OP>(smem, flag, tid);
}
template<typename T>
void segmentedScanCpu( const T *src, T *dst, int *flag, const unsigned int size ) {
dst[0] = src[0];
for ( int i=1; i<size; i++ ) {
dst[i] = flag[i] ? src[i] : dst[i-1] + src[i];
}
}
int main() {
const int arraySize = 1024;
int src[arraySize];
int hd[arraySize]={0};
int dst[arraySize] = { 0 };
int dstCpu[arraySize] = { 0 };
for ( int i=0; i<arraySize; i++) {
src[i] = i;
hd[i] = (i % 4)==0 ? 1 : 0;
}
cudaError_t cudaStatus = segmentedScanTest(dst, src, hd, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
const char *fmt = "%4d";
for ( int i=0; i<32; i++ ) {
printf(fmt, src[i]);
}
puts("");
for ( int i=0; i<32; i++ ) {
printf(fmt, hd[i]);
}
puts("");
for ( int i=0; i<32; i++ ) {
printf(fmt, dst[i]);
}
puts("");
segmentedScanCpu(src, dstCpu, hd, arraySize);
for ( int i=0; i<arraySize; i++ ) {
if ( dstCpu[i] != dst[i] ) {
puts("compared... not ok");
break;
}
}
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t segmentedScanTest(int *c, const int *a, const int *b, unsigned int size) {
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr,
"cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = cudaMalloc((void**) &dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**) &dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**) &dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int),
cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int),
cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
// segscan_warp_kernel<int, AddOp<int> ><<<1, 32>>>(dev_a, dev_c, dev_b);
//scan_warp_max_kernel<<<1, 32>>>(dev_b, dev_c);
//segscan_warp2_kernel<<<1, 32>>>(dev_a, dev_c, dev_b);
segscan_block_kernel<int, AddOp<int> ><<<1, size>>>(dev_a, dev_c, dev_b);
//segscan_block_kernel_smem<int, 2048><<<1, size>>>(dev_a, dev_c, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, " launch failed: %s\n",
cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr,
"cudaDeviceSynchronize returned error code %d after launching addKernel!\n",
cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int),
cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error: cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | code for sm_80
Function : _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R32, SR_TID.X ; /* 0x0000000000207919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.WIDE.U32 R4, R32, 0x4, RZ ; /* 0x0000000420047825 */
/* 0x001fca00078e00ff */
/*0040*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0050*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fcc00007fe4ff */
/*0060*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0070*/ LOP3.LUT R26, R4.reuse, 0xffffff80, RZ, 0xc0, !PT ; /* 0xffffff80041a7812 */
/* 0x040fe400078ec0ff */
/*0080*/ IADD3 R24, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004187a10 */
/* 0x000fe40007f1e0ff */
/*0090*/ LOP3.LUT R0, R5.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305007812 */
/* 0x040fe400078ec0ff */
/*00a0*/ IADD3 R26, P1, R26, c[0x0][0x170], RZ ; /* 0x00005c001a1a7a10 */
/* 0x000fe40007f3e0ff */
/*00b0*/ IADD3.X R25, R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005197a10 */
/* 0x000fe400007fe4ff */
/*00c0*/ IADD3.X R27, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d00001b7a10 */
/* 0x000fc40000ffe4ff */
/*00d0*/ IADD3 R22, P2, R4, c[0x0][0x170], RZ ; /* 0x00005c0004167a10 */
/* 0x000fc80007f5e0ff */
/*00e0*/ IADD3.X R23, R5, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0005177a10 */
/* 0x000fe200017fe4ff */
/*00f0*/ STG.E [R24.64], R3 ; /* 0x0000000318007986 */
/* 0x0041e8000c101904 */
/*0100*/ LDG.E.STRONG.SYS R0, [R26.64] ; /* 0x000000041a007981 */
/* 0x0002a8000c1f5900 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ LDG.E.STRONG.SYS R2, [R22.64] ; /* 0x0000000416027981 */
/* 0x000ee2000c1f5900 */
/*0130*/ LOP3.LUT R31, R32.reuse, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f201f7812 */
/* 0x040fe200078ec0ff */
/*0140*/ IMAD.MOV.U32 R30, RZ, RZ, 0x4 ; /* 0x00000004ff1e7424 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R11, R32, -0x1, RZ ; /* 0xffffffff200b7810 */
/* 0x000fc40007ffe0ff */
/*0160*/ ISETP.NE.AND P0, PT, R31, RZ, PT ; /* 0x000000ff1f00720c */
/* 0x000fc60003f05270 */
/*0170*/ IMAD.WIDE.U32 R20, R11, R30, c[0x0][0x170] ; /* 0x00005c000b147625 */
/* 0x000fe200078e001e */
/*0180*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x008fda0003f25270 */
/*0190*/ @P1 STG.E.STRONG.SYS [R22.64], R31 ; /* 0x0000001f16001986 */
/* 0x000fe8000c115904 */
/*01a0*/ @P0 LDG.E.STRONG.SYS R2, [R20.64] ; /* 0x0000000414020981 */
/* 0x000ee8000c1f5900 */
/*01b0*/ @P0 LDG.E.STRONG.SYS R3, [R22.64] ; /* 0x0000000416030981 */
/* 0x001ee2000c1f5900 */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R31, 0x2, PT ; /* 0x000000021f00780c */
/* 0x000fe40003f26070 */
/*01d0*/ IADD3 R9, R32, -0x2, RZ ; /* 0xfffffffe20097810 */
/* 0x000fca0007ffe0ff */
/*01e0*/ IMAD.WIDE.U32 R18, R9, R30, c[0x0][0x170] ; /* 0x00005c0009127625 */
/* 0x000fe200078e001e */
/*01f0*/ @P0 IMNMX R3, R2, R3, !PT ; /* 0x0000000302030217 */
/* 0x008fca0007800200 */
/*0200*/ @P0 STG.E.STRONG.SYS [R22.64], R3 ; /* 0x0000000316000986 */
/* 0x0001e8000c115904 */
/*0210*/ @P1 LDG.E.STRONG.SYS R2, [R18.64] ; /* 0x0000000412021981 */
/* 0x000ee8000c1f5900 */
/*0220*/ @P1 LDG.E.STRONG.SYS R5, [R22.64] ; /* 0x0000000416051981 */
/* 0x000ee2000c1f5900 */
/*0230*/ ISETP.GE.U32.AND P2, PT, R31, 0x4, PT ; /* 0x000000041f00780c */
/* 0x000fe40003f46070 */
/*0240*/ IADD3 R7, R32, -0x4, RZ ; /* 0xfffffffc20077810 */
/* 0x000fca0007ffe0ff */
/*0250*/ IMAD.WIDE.U32 R16, R7, R30, c[0x0][0x170] ; /* 0x00005c0007107625 */
/* 0x000fe200078e001e */
/*0260*/ @P1 IMNMX R13, R2, R5, !PT ; /* 0x00000005020d1217 */
/* 0x008fca0007800200 */
/*0270*/ @P1 STG.E.STRONG.SYS [R22.64], R13 ; /* 0x0000000d16001986 */
/* 0x0007e8000c115904 */
/*0280*/ @P2 LDG.E.STRONG.SYS R2, [R16.64] ; /* 0x0000000410022981 */
/* 0x000f28000c1f5900 */
/*0290*/ @P2 LDG.E.STRONG.SYS R15, [R22.64] ; /* 0x00000004160f2981 */
/* 0x000f22000c1f5900 */
/*02a0*/ ISETP.GE.U32.AND P3, PT, R31, 0x8, PT ; /* 0x000000081f00780c */
/* 0x000fe40003f66070 */
/*02b0*/ IADD3 R5, R32, -0x8, RZ ; /* 0xfffffff820057810 */
/* 0x000fc40007ffe0ff */
/*02c0*/ @P2 IMNMX R29, R2, R15, !PT ; /* 0x0000000f021d2217 */
/* 0x010fc60007800200 */
/*02d0*/ IMAD.WIDE.U32 R14, R5, R30, c[0x0][0x170] ; /* 0x00005c00050e7625 */
/* 0x000fe400078e001e */
/*02e0*/ @P2 STG.E.STRONG.SYS [R22.64], R29 ; /* 0x0000001d16002986 */
/* 0x0009e8000c115904 */
/*02f0*/ @P3 LDG.E.STRONG.SYS R2, [R14.64] ; /* 0x000000040e023981 */
/* 0x000ea8000c1f5900 */
/*0300*/ @P3 LDG.E.STRONG.SYS R33, [R22.64] ; /* 0x0000000416213981 */
/* 0x000ea2000c1f5900 */
/*0310*/ ISETP.GE.U32.AND P4, PT, R31, 0x10, PT ; /* 0x000000101f00780c */
/* 0x000fc40003f86070 */
/*0320*/ IADD3 R3, R32, -0x10, RZ ; /* 0xfffffff020037810 */
/* 0x001fca0007ffe0ff */
/*0330*/ IMAD.WIDE.U32 R12, R3, R30, c[0x0][0x170] ; /* 0x00005c00030c7625 */
/* 0x008fe200078e001e */
/*0340*/ @P3 IMNMX R33, R2, R33, !PT ; /* 0x0000002102213217 */
/* 0x004fca0007800200 */
/*0350*/ @P3 STG.E.STRONG.SYS [R22.64], R33 ; /* 0x0000002116003986 */
/* 0x0001e8000c115904 */
/*0360*/ @P4 LDG.E.STRONG.SYS R2, [R12.64] ; /* 0x000000040c024981 */
/* 0x000ea8000c1f5900 */
/*0370*/ @P4 LDG.E.STRONG.SYS R35, [R22.64] ; /* 0x0000000416234981 */
/* 0x000ea4000c1f5900 */
/*0380*/ @P4 IMNMX R35, R2, R35, !PT ; /* 0x0000002302234217 */
/* 0x004fca0007800200 */
/*0390*/ @P4 STG.E.STRONG.SYS [R22.64], R35 ; /* 0x0000002316004986 */
/* 0x0005e8000c115904 */
/*03a0*/ LDG.E.STRONG.SYS R2, [R22.64] ; /* 0x0000000416027981 */
/* 0x000ee2000c1f5900 */
/*03b0*/ IMAD.WIDE.U32 R10, R11, R30, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fe200078e001e */
/*03c0*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x008fc80007ffe0ff */
/*03d0*/ ISETP.GE.U32.AND P5, PT, R31, R4, PT ; /* 0x000000041f00720c */
/* 0x000fda0003fa6070 */
/*03e0*/ @P5 LDG.E.STRONG.SYS R4, [R10.64] ; /* 0x000000040a045981 */
/* 0x000ee8000c1f5900 */
/*03f0*/ @P5 LDG.E.STRONG.SYS R29, [R24.64] ; /* 0x00000004181d5981 */
/* 0x010ee2000c1f5900 */
/*0400*/ IADD3 R6, R2, 0x2, RZ ; /* 0x0000000202067810 */
/* 0x000fe20007ffe0ff */
/*0410*/ IMAD.WIDE.U32 R8, R9, R30, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fc600078e001e */
/*0420*/ ISETP.GE.U32.AND P6, PT, R31, R6, PT ; /* 0x000000061f00720c */
/* 0x000fe20003fc6070 */
/*0430*/ @P5 IMAD.IADD R29, R4, 0x1, R29 ; /* 0x00000001041d5824 */
/* 0x008fca00078e021d */
/*0440*/ @P5 STG.E.STRONG.SYS [R24.64], R29 ; /* 0x0000001d18005986 */
/* 0x0007ee000c115904 */
/*0450*/ @P6 LDG.E.STRONG.SYS R4, [R8.64] ; /* 0x0000000408046981 */
/* 0x000f28000c1f5900 */
/*0460*/ @P6 LDG.E.STRONG.SYS R33, [R24.64] ; /* 0x0000000418216981 */
/* 0x001f22000c1f5900 */
/*0470*/ IADD3 R6, R2, 0x4, RZ ; /* 0x0000000402067810 */
/* 0x000fc80007ffe0ff */
/*0480*/ ISETP.GE.U32.AND P5, PT, R31, R6, PT ; /* 0x000000061f00720c */
/* 0x000fe20003fa6070 */
/*0490*/ IMAD.WIDE.U32 R6, R7, R30, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fc800078e001e */
/*04a0*/ @P6 IMAD.IADD R33, R4, 0x1, R33 ; /* 0x0000000104216824 */
/* 0x010fca00078e0221 */
/*04b0*/ @P6 STG.E.STRONG.SYS [R24.64], R33 ; /* 0x0000002118006986 */
/* 0x000fe8000c115904 */
/*04c0*/ @P5 LDG.E.STRONG.SYS R4, [R6.64] ; /* 0x0000000406045981 */
/* 0x000f28000c1f5900 */
/*04d0*/ @P5 LDG.E.STRONG.SYS R35, [R24.64] ; /* 0x0000000418235981 */
/* 0x004f22000c1f5900 */
/*04e0*/ IADD3 R28, R2, 0x8, RZ ; /* 0x00000008021c7810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.GE.U32.AND P6, PT, R31, R28, PT ; /* 0x0000001c1f00720c */
/* 0x000fe20003fc6070 */
/*0500*/ @P5 IMAD.IADD R35, R4, 0x1, R35 ; /* 0x0000000104235824 */
/* 0x010fe400078e0223 */
/*0510*/ IMAD.WIDE.U32 R4, R5, R30, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fc600078e001e */
/*0520*/ @P5 STG.E.STRONG.SYS [R24.64], R35 ; /* 0x0000002318005986 */
/* 0x0001ee000c115904 */
/*0530*/ @P6 LDG.E.STRONG.SYS R28, [R4.64] ; /* 0x00000004041c6981 */
/* 0x000ea8000c1f5900 */
/*0540*/ @P6 LDG.E.STRONG.SYS R29, [R24.64] ; /* 0x00000004181d6981 */
/* 0x008ea2000c1f5900 */
/*0550*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GE.U32.AND P5, PT, R31, R2, PT ; /* 0x000000021f00720c */
/* 0x000fe20003fa6070 */
/*0570*/ IMAD.WIDE.U32 R2, R3, R30, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e001e */
/*0580*/ @P6 IMAD.IADD R37, R28, 0x1, R29 ; /* 0x000000011c256824 */
/* 0x004fca00078e021d */
/*0590*/ @P6 STG.E.STRONG.SYS [R24.64], R37 ; /* 0x0000002518006986 */
/* 0x0005e8000c115904 */
/*05a0*/ @P5 LDG.E.STRONG.SYS R28, [R2.64] ; /* 0x00000004021c5981 */
/* 0x000ee8000c1f5900 */
/*05b0*/ @P5 LDG.E.STRONG.SYS R29, [R24.64] ; /* 0x00000004181d5981 */
/* 0x000ee2000c1f5900 */
/*05c0*/ LOP3.LUT R35, R32, 0x1f, RZ, 0xfc, !PT ; /* 0x0000001f20237812 */
/* 0x001fe200078efcff */
/*05d0*/ @P5 IMAD.IADD R34, R28, 0x1, R29 ; /* 0x000000011c225824 */
/* 0x008fc800078e021d */
/*05e0*/ IMAD.WIDE.U32 R28, R35.reuse, R30, c[0x0][0x168] ; /* 0x00005a00231c7625 */
/* 0x040fe200078e001e */
/*05f0*/ @P5 STG.E.STRONG.SYS [R24.64], R34 ; /* 0x0000002218005986 */
/* 0x0001e8000c115904 */
/*0600*/ LDG.E.STRONG.SYS R33, [R24.64] ; /* 0x0000000418217981 */
/* 0x000768000c1f5900 */
/*0610*/ LDG.E.STRONG.SYS R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000f28000c1f5900 */
/*0620*/ LDG.E.STRONG.SYS R27, [R26.64+0x7c] ; /* 0x00007c041a1b7981 */
/* 0x002ea2000c1f5900 */
/*0630*/ ISETP.NE.AND P5, PT, R35, R32, PT ; /* 0x000000202300720c */
/* 0x000fc40003fa5270 */
/*0640*/ LOP3.LUT P6, RZ, R27, R0, RZ, 0xfc, !PT ; /* 0x000000001bff7212 */
/* 0x004fd600078cfcff */
/*0650*/ @!P5 SEL R36, RZ, 0x1, !P6 ; /* 0x00000001ff24d807 */
/* 0x000fe40007000000 */
/*0660*/ ISETP.NE.AND P6, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003fc5270 */
/*0670*/ @!P6 LDG.E.STRONG.SYS R0, [R22.64] ; /* 0x000000041600e981 */
/* 0x000ea2000c1f5900 */
/*0680*/ SHF.R.U32.HI R37, RZ, 0x5, R32 ; /* 0x00000005ff257819 */
/* 0x000fe20000011620 */
/*0690*/ BSSY B0, 0xcc0 ; /* 0x0000062000007945 */
/* 0x000fe80003800000 */
/*06a0*/ @!P5 IMAD.WIDE.U32 R34, R37.reuse, R30.reuse, c[0x0][0x168] ; /* 0x00005a002522d625 */
/* 0x0c1fe200078e001e */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*06c0*/ @!P5 IMAD.WIDE.U32 R26, R37, R30, c[0x0][0x170] ; /* 0x00005c00251ad625 */
/* 0x000fc600078e001e */
/*06d0*/ @!P5 STG.E.STRONG.SYS [R34.64], R28 ; /* 0x0000001c2200d986 */
/* 0x0107e8000c115904 */
/*06e0*/ @!P5 STG.E.STRONG.SYS [R26.64], R36 ; /* 0x000000241a00d986 */
/* 0x0007e8000c115904 */
/*06f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0700*/ @!P6 ISETP.NE.AND P5, PT, R0, RZ, PT ; /* 0x000000ff0000e20c */
/* 0x004fe40003fa5270 */
/*0710*/ PRMT R0, RZ, 0x7610, R0 ; /* 0x00007610ff007816 */
/* 0x000fc40000000000 */
/*0720*/ @!P6 SEL R29, RZ, 0x1, P5 ; /* 0x00000001ff1de807 */
/* 0x000fe40002800000 */
/*0730*/ ISETP.NE.AND P5, PT, R37, RZ, PT ; /* 0x000000ff2500720c */
/* 0x000fe40003fa5270 */
/*0740*/ @!P6 PRMT R0, R29, 0x7610, R0 ; /* 0x000076101d00e816 */
/* 0x000fd60000000000 */
/*0750*/ @P5 BRA 0xcb0 ; /* 0x0000055000005947 */
/* 0x000fea0003800000 */
/*0760*/ LDG.E.STRONG.SYS R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x008ea2000c1f5900 */
/*0770*/ BSSY B1, 0x800 ; /* 0x0000008000017945 */
/* 0x000fe20003800000 */
/*0780*/ ISETP.NE.AND P5, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x004fda0003fa5270 */
/*0790*/ @P5 STG.E.STRONG.SYS [R22.64], R31 ; /* 0x0000001f16005986 */
/* 0x0001e2000c115904 */
/*07a0*/ @!P0 BRA 0x7f0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*07b0*/ LDG.E.STRONG.SYS R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1f5900 */
/*07c0*/ LDG.E.STRONG.SYS R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x000ea4000c1f5900 */
/*07d0*/ IMNMX R27, R20, R27, !PT ; /* 0x0000001b141b7217 */
/* 0x004fca0007800200 */
/*07e0*/ STG.E.STRONG.SYS [R22.64], R27 ; /* 0x0000001b16007986 */
/* 0x0003e4000c115904 */
/*07f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0800*/ BSSY B1, 0x870 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0810*/ @!P1 BRA 0x860 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0820*/ LDG.E.STRONG.SYS R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1f5900 */
/*0830*/ LDG.E.STRONG.SYS R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x000ea4000c1f5900 */
/*0840*/ IMNMX R21, R18, R21, !PT ; /* 0x0000001512157217 */
/* 0x004fca0007800200 */
/*0850*/ STG.E.STRONG.SYS [R22.64], R21 ; /* 0x0000001516007986 */
/* 0x0005e4000c115904 */
/*0860*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0870*/ BSSY B1, 0x8e0 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0880*/ @!P2 BRA 0x8d0 ; /* 0x000000400000a947 */
/* 0x000fea0003800000 */
/*0890*/ LDG.E.STRONG.SYS R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee8000c1f5900 */
/*08a0*/ LDG.E.STRONG.SYS R19, [R22.64] ; /* 0x0000000416137981 */
/* 0x000ee4000c1f5900 */
/*08b0*/ IMNMX R19, R16, R19, !PT ; /* 0x0000001310137217 */
/* 0x008fca0007800200 */
/*08c0*/ STG.E.STRONG.SYS [R22.64], R19 ; /* 0x0000001316007986 */
/* 0x0007e4000c115904 */
/*08d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08e0*/ BSSY B1, 0x950 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*08f0*/ @!P3 BRA 0x940 ; /* 0x000000400000b947 */
/* 0x000fea0003800000 */
/*0900*/ LDG.E.STRONG.SYS R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1f5900 */
/*0910*/ LDG.E.STRONG.SYS R17, [R22.64] ; /* 0x0000000416117981 */
/* 0x000f24000c1f5900 */
/*0920*/ IMNMX R17, R14, R17, !PT ; /* 0x000000110e117217 */
/* 0x010fca0007800200 */
/*0930*/ STG.E.STRONG.SYS [R22.64], R17 ; /* 0x0000001116007986 */
/* 0x0009e4000c115904 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ BSSY B1, 0x9c0 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0960*/ @!P4 BRA 0x9b0 ; /* 0x000000400000c947 */
/* 0x000fea0003800000 */
/*0970*/ LDG.E.STRONG.SYS R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x004ea8000c1f5900 */
/*0980*/ LDG.E.STRONG.SYS R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000ea4000c1f5900 */
/*0990*/ IMNMX R15, R12, R15, !PT ; /* 0x0000000f0c0f7217 */
/* 0x004fca0007800200 */
/*09a0*/ STG.E.STRONG.SYS [R22.64], R15 ; /* 0x0000000f16007986 */
/* 0x0005e4000c115904 */
/*09b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09c0*/ LDG.E.STRONG.SYS R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x01fea2000c1f5900 */
/*09d0*/ BSSY B1, 0xae0 ; /* 0x0000010000017945 */
/* 0x000fe20003800000 */
/*09e0*/ IADD3 R12, R22.reuse, 0x1, RZ ; /* 0x00000001160c7810 */
/* 0x044fe40007ffe0ff */
/*09f0*/ IADD3 R14, R22.reuse, 0x2, RZ ; /* 0x00000002160e7810 */
/* 0x040fe40007ffe0ff */
/*0a00*/ ISETP.GE.U32.AND P0, PT, R31, R12, PT ; /* 0x0000000c1f00720c */
/* 0x000fe40003f06070 */
/*0a10*/ IADD3 R16, R22.reuse, 0x4, RZ ; /* 0x0000000416107810 */
/* 0x040fe40007ffe0ff */
/*0a20*/ IADD3 R12, R22, 0x8, RZ ; /* 0x00000008160c7810 */
/* 0x000fc40007ffe0ff */
/*0a30*/ IADD3 R18, R22, 0x10, RZ ; /* 0x0000001016127810 */
/* 0x000fe40007ffe0ff */
/*0a40*/ ISETP.GE.U32.AND P1, PT, R31.reuse, R14, PT ; /* 0x0000000e1f00720c */
/* 0x040fe40003f26070 */
/*0a50*/ ISETP.GE.U32.AND P2, PT, R31.reuse, R16, PT ; /* 0x000000101f00720c */
/* 0x040fe40003f46070 */
/*0a60*/ ISETP.GE.U32.AND P3, PT, R31.reuse, R12, PT ; /* 0x0000000c1f00720c */
/* 0x040fe40003f66070 */
/*0a70*/ ISETP.GE.U32.AND P4, PT, R31, R18, PT ; /* 0x000000121f00720c */
/* 0x000fe20003f86070 */
/*0a80*/ @!P0 BRA 0xad0 ; /* 0x0000004000008947 */
/* 0x000fee0003800000 */
/*0a90*/ LDG.E.STRONG.SYS R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1f5900 */
/*0aa0*/ LDG.E.STRONG.SYS R13, [R24.64] ; /* 0x00000004180d7981 */
/* 0x000ea4000c1f5900 */
/*0ab0*/ IMAD.IADD R13, R12, 0x1, R13 ; /* 0x000000010c0d7824 */
/* 0x004fca00078e020d */
/*0ac0*/ STG.E.STRONG.SYS [R24.64], R13 ; /* 0x0000000d18007986 */
/* 0x0001e4000c115904 */
/*0ad0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ae0*/ BSSY B1, 0xb50 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0af0*/ @!P1 BRA 0xb40 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0b00*/ LDG.E.STRONG.SYS R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1f5900 */
/*0b10*/ LDG.E.STRONG.SYS R13, [R24.64] ; /* 0x00000004180d7981 */
/* 0x001ea4000c1f5900 */
/*0b20*/ IMAD.IADD R13, R8, 0x1, R13 ; /* 0x00000001080d7824 */
/* 0x004fca00078e020d */
/*0b30*/ STG.E.STRONG.SYS [R24.64], R13 ; /* 0x0000000d18007986 */
/* 0x0001e4000c115904 */
/*0b40*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b50*/ BSSY B1, 0xbc0 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0b60*/ @!P2 BRA 0xbb0 ; /* 0x000000400000a947 */
/* 0x000fea0003800000 */
/*0b70*/ LDG.E.STRONG.SYS R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1f5900 */
/*0b80*/ LDG.E.STRONG.SYS R9, [R24.64] ; /* 0x0000000418097981 */
/* 0x000ea4000c1f5900 */
/*0b90*/ IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106097824 */
/* 0x004fca00078e0209 */
/*0ba0*/ STG.E.STRONG.SYS [R24.64], R9 ; /* 0x0000000918007986 */
/* 0x0003e4000c115904 */
/*0bb0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0bc0*/ BSSY B1, 0xc30 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0bd0*/ @!P3 BRA 0xc20 ; /* 0x000000400000b947 */
/* 0x000fea0003800000 */
/*0be0*/ LDG.E.STRONG.SYS R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1f5900 */
/*0bf0*/ LDG.E.STRONG.SYS R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x000ea4000c1f5900 */
/*0c00*/ IMAD.IADD R7, R4, 0x1, R7 ; /* 0x0000000104077824 */
/* 0x004fca00078e0207 */
/*0c10*/ STG.E.STRONG.SYS [R24.64], R7 ; /* 0x0000000718007986 */
/* 0x0005e4000c115904 */
/*0c20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c30*/ BSSY B1, 0xca0 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0c40*/ @!P4 BRA 0xc90 ; /* 0x000000400000c947 */
/* 0x000fea0003800000 */
/*0c50*/ LDG.E.STRONG.SYS R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee8000c1f5900 */
/*0c60*/ LDG.E.STRONG.SYS R5, [R24.64] ; /* 0x0000000418057981 */
/* 0x000ee4000c1f5900 */
/*0c70*/ IMAD.IADD R5, R2, 0x1, R5 ; /* 0x0000000102057824 */
/* 0x008fca00078e0205 */
/*0c80*/ STG.E.STRONG.SYS [R24.64], R5 ; /* 0x0000000518007986 */
/* 0x0007e4000c115904 */
/*0c90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ca0*/ LDG.E.STRONG.SYS R2, [R24.64] ; /* 0x0000000418027981 */
/* 0x000964000c1f5900 */
/*0cb0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x008fea0003800000 */
/*0cc0*/ PRMT R0, R0, 0x9910, RZ ; /* 0x0000991000007816 */
/* 0x000fe200000000ff */
/*0cd0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0ce0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*0cf0*/ BSSY B0, 0xd50 ; /* 0x0000005000007945 */
/* 0x000fe20003800000 */
/*0d00*/ ISETP.EQ.OR P0, PT, R37, RZ, !P0 ; /* 0x000000ff2500720c */
/* 0x000fda0004702670 */
/*0d10*/ @P0 BRA 0xd40 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0d20*/ LDG.E.STRONG.SYS R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee4000c1f5900 */
/*0d30*/ IMAD.IADD R33, R33, 0x1, R10 ; /* 0x0000000121217824 */
/* 0x028fe400078e020a */
/*0d40*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d50*/ STG.E.STRONG.SYS [R24.64], R33 ; /* 0x0000002118007986 */
/* 0x020fe8000c115904 */
/*0d60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0d70*/ STG.E [R24.64], R33 ; /* 0x0000002118007986 */
/* 0x000fe2000c101904 */
/*0d80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d90*/ BRA 0xd90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Segmented Scan CUDA sample
*
* Original:
* "Efficient Parallel Scan Algorithms for GPUs",
* Shubhabrata Sengupta,Mark Harris, Michael Garland.
* https://research.nvidia.com/sites/default/files/publications/nvr-2008-003.pdf
*
* via
* aokomoriuta san
* http://qiita.com/aokomoriuta/items/3c2a80181a01c7f22e7f
*
* Using a template kernel.cu in NVIDIA Cuda Toolkit 5.5
*/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
template<typename T>
class AddOp {
public:
static __device__ inline T apply(const T a, const T b) {
return a + b;
}
};
template<typename T>
class MaxOp {
public:
static __device__ inline T apply(const T a, const T b) {
return max(a,b);
}
};
cudaError_t segmentedScanTest(int *c, const int *a, const int *b, unsigned int size);
template<typename T, class OP>
__device__ void compute_segscan(volatile T *p, volatile int *hd,
const unsigned int tid, const unsigned int offset) {
const unsigned int lane = tid & 31;
if (lane >= offset) {
p[tid] = hd[tid] ? p[tid] : OP::apply(p[tid - offset],p[tid]);
hd[tid] = hd[tid - offset] | hd[tid];
}
}
/**
* Figure 6
*/
template<typename T, int Kind, class OP>
__device__ T segscan_warp(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int lane = tid & 31;
compute_segscan<T,OP>(p, hd, tid, 1);
compute_segscan<T,OP>(p, hd, tid, 2);
compute_segscan<T,OP>(p, hd, tid, 4);
compute_segscan<T,OP>(p, hd, tid, 8);
compute_segscan<T,OP>(p, hd, tid, 16);
if (Kind == 0)
return p[tid];
else
return (lane > 0) ? p[tid - 1] : 0;
}
template <typename T, class OP>
__global__ void segscan_warp_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
segscan_warp<int,0,OP>(dst, flag, threadIdx.x);
}
/**
* Figure 3
*/
template<typename T, int Kind, class OP>
__device__ T scan_warp(volatile T *p,
const unsigned int tid = threadIdx.x) {
const int lane = tid & 31;
if (lane >= 1)
p[tid] = OP::apply(p[tid - 1], p[tid]);
if (lane >= 2)
p[tid] = OP::apply(p[tid - 2], p[tid]);
if (lane >= 4)
p[tid] = OP::apply(p[tid - 4], p[tid]);
if (lane >= 8)
p[tid] = OP::apply(p[tid - 8], p[tid]);
if (lane >= 16)
p[tid] = OP::apply(p[tid - 16], p[tid]);
return p[tid];
}
/**
* Figure 7
*/
template<typename T, int Kind, class OP>
__device__ T segscan_warp2(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int lane = tid & 31;
if (hd[tid])
hd[tid] = lane;
int mindex = scan_warp<T,Kind, MaxOp<T> >(hd,tid);
if (lane >= mindex + 1)
p[tid] = OP::apply(p[tid - 1],p[tid]);
if (lane >= mindex + 2)
p[tid] = OP::apply(p[tid - 2], p[tid]);
if (lane >= mindex + 4)
p[tid] = OP::apply(p[tid - 4], p[tid]);
if (lane >= mindex + 8)
p[tid] = OP::apply(p[tid - 8], p[tid]);
if (lane >= mindex + 16)
p[tid] = OP::apply(p[tid - 16], p[tid]);
if (Kind == 0)
return p[tid];
else
return (lane > 0 && mindex != lane) ? p[tid - 1] : 0;
}
template <typename T, class OP>
__global__ void segscan_warp2_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
dst[tid] = segscan_warp2<int,0, OP>(dst, flag, tid);
}
/**
* Figure 10
*/
template<typename T, int Kind, class OP>
__device__ T segscan_block(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int warpid = tid >> 5;
const unsigned int warp_first = warpid << 5;
const unsigned int warp_last = warp_first + 31;
// step 1a
bool warp_is_open = (hd[warp_first] == 0);
__syncthreads();
// step 1b
T val = segscan_warp2<T,Kind, OP>(p, hd, tid);
// step 2a
T warp_total = p[warp_last];
// step 2b
int warp_flag = hd[warp_last] != 0 || !warp_is_open;
bool will_accumulate = warp_is_open && hd[tid] == 0;
__syncthreads();
// step 2c
if (tid == warp_last) {
p[warpid] = warp_total;
hd[warpid] = warp_flag;
}
__syncthreads();
// step 3
if (warpid == 0)
segscan_warp2<T,0, OP>(p, hd, tid);
__syncthreads();
// step 4
if (warpid != 0 && will_accumulate)
val = OP::apply( p[tid - 1] , val);
p[tid] = val;
__syncthreads();
return val;
}
template <typename T, class OP>
__global__ void segscan_block_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
dst[tid] = segscan_block<int,0, OP>(dst, flag, tid);
}
template <typename T, class OP, unsigned int SIZE>
__global__ void segscan_block_kernel_smem(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
__shared__ T smem[SIZE];
smem[tid] = src[tid];
dst[tid] = segscan_block<int,0, OP>(smem, flag, tid);
}
template<typename T>
void segmentedScanCpu( const T *src, T *dst, int *flag, const unsigned int size ) {
dst[0] = src[0];
for ( int i=1; i<size; i++ ) {
dst[i] = flag[i] ? src[i] : dst[i-1] + src[i];
}
}
int main() {
const int arraySize = 1024;
int src[arraySize];
int hd[arraySize]={0};
int dst[arraySize] = { 0 };
int dstCpu[arraySize] = { 0 };
for ( int i=0; i<arraySize; i++) {
src[i] = i;
hd[i] = (i % 4)==0 ? 1 : 0;
}
cudaError_t cudaStatus = segmentedScanTest(dst, src, hd, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
const char *fmt = "%4d";
for ( int i=0; i<32; i++ ) {
printf(fmt, src[i]);
}
puts("");
for ( int i=0; i<32; i++ ) {
printf(fmt, hd[i]);
}
puts("");
for ( int i=0; i<32; i++ ) {
printf(fmt, dst[i]);
}
puts("");
segmentedScanCpu(src, dstCpu, hd, arraySize);
for ( int i=0; i<arraySize; i++ ) {
if ( dstCpu[i] != dst[i] ) {
puts("compared... not ok");
break;
}
}
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t segmentedScanTest(int *c, const int *a, const int *b, unsigned int size) {
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr,
"cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = cudaMalloc((void**) &dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**) &dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**) &dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int),
cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int),
cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
// segscan_warp_kernel<int, AddOp<int> ><<<1, 32>>>(dev_a, dev_c, dev_b);
//scan_warp_max_kernel<<<1, 32>>>(dev_b, dev_c);
//segscan_warp2_kernel<<<1, 32>>>(dev_a, dev_c, dev_b);
segscan_block_kernel<int, AddOp<int> ><<<1, size>>>(dev_a, dev_c, dev_b);
//segscan_block_kernel_smem<int, 2048><<<1, size>>>(dev_a, dev_c, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, " launch failed: %s\n",
cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr,
"cudaDeviceSynchronize returned error code %d after launching addKernel!\n",
cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int),
cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error: cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | .file "tmpxft_0007df36_00000000-6_segscan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL61__device_stub__Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_PiPKiPiS1_, @function
_ZL61__device_stub__Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_PiPKiPiS1_:
.LFB2099:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2099:
.size _ZL61__device_stub__Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_PiPKiPiS1_, .-_ZL61__device_stub__Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_PiPKiPiS1_
.section .text._Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,"axG",@progbits,_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,comdat
.weak _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.type _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, @function
_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi:
.LFB2149:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL61__device_stub__Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_PiPKiPiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2149:
.size _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, .-_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string " launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z17segmentedScanTestPiPKiS1_j
.type _Z17segmentedScanTestPiPKiS1_j, @function
_Z17segmentedScanTestPiPKiS1_j:
.LFB2074:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L24
movl %ebp, %r15d
salq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L25
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L29
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L19:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L32
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L13
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L24:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L26:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L27:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L28:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L29:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L30:
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _ZL61__device_stub__Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_PiPKiPiS1_
jmp .L19
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L32:
movl %eax, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2074:
.size _Z17segmentedScanTestPiPKiS1_j, .-_Z17segmentedScanTestPiPKiS1_j
.section .rodata.str1.1
.LC5:
.string "addWithCuda failed!"
.LC6:
.string "%4d"
.LC7:
.string ""
.LC8:
.string "compared... not ok"
.LC9:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB2073:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -16384(%rsp), %r11
.cfi_def_cfa 11, 16424
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $24, %rsp
.cfi_def_cfa_offset 16448
movq %fs:40, %rax
movq %rax, 16392(%rsp)
xorl %eax, %eax
leaq 4096(%rsp), %rdi
movl $512, %ecx
rep stosq
leaq 8192(%rsp), %rdi
movl $512, %ecx
rep stosq
leaq 12288(%rsp), %rdi
movl $512, %ecx
rep stosq
.L35:
movl %eax, (%rsp,%rax,4)
testb $3, %al
sete %dl
movzbl %dl, %edx
movl %edx, 4096(%rsp,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L35
leaq 4096(%rsp), %rdx
movq %rsp, %rsi
leaq 8192(%rsp), %rdi
movl $1024, %ecx
call _Z17segmentedScanTestPiPKiS1_j
movq %rsp, %rbx
leaq 128(%rsp), %r12
leaq .LC6(%rip), %rbp
testl %eax, %eax
jne .L57
.L38:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L38
leaq .LC7(%rip), %rdi
call puts@PLT
leaq 4096(%rsp), %r13
leaq 4224(%rsp), %r12
movq %r13, %rbx
leaq .LC6(%rip), %rbp
.L39:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L39
leaq .LC7(%rip), %rdi
call puts@PLT
leaq 8192(%rsp), %rbx
leaq 8320(%rsp), %r12
leaq .LC6(%rip), %rbp
.L40:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L40
leaq .LC7(%rip), %rdi
call puts@PLT
movl (%rsp), %eax
movl %eax, 12288(%rsp)
leaq 4100(%rsp), %rax
leaq 4(%rsp), %rcx
leaq 12292(%rsp), %rdx
addq $4096, %r13
jmp .L43
.L57:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L34
.L41:
movl (%rcx), %esi
addl -4(%rdx), %esi
.L42:
movl %esi, (%rdx)
addq $4, %rax
addq $4, %rcx
addq $4, %rdx
cmpq %r13, %rax
je .L58
.L43:
cmpl $0, (%rax)
je .L41
movl (%rcx), %esi
jmp .L42
.L58:
movl $0, %eax
leaq 8192(%rsp), %rdx
.L46:
movl (%rdx,%rax), %ecx
cmpl %ecx, 12288(%rsp,%rax)
jne .L59
addq $4, %rax
cmpq $4096, %rax
jne .L46
jmp .L45
.L59:
leaq .LC8(%rip), %rdi
call puts@PLT
.L45:
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L60
.L34:
movq 16392(%rsp), %rdx
subq %fs:40, %rdx
jne .L61
addq $16408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L34
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC10:
.string "_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2102:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2102:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Segmented Scan CUDA sample
*
* Original:
* "Efficient Parallel Scan Algorithms for GPUs",
* Shubhabrata Sengupta,Mark Harris, Michael Garland.
* https://research.nvidia.com/sites/default/files/publications/nvr-2008-003.pdf
*
* via
* aokomoriuta san
* http://qiita.com/aokomoriuta/items/3c2a80181a01c7f22e7f
*
* Using a template kernel.cu in NVIDIA Cuda Toolkit 5.5
*/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
template<typename T>
class AddOp {
public:
static __device__ inline T apply(const T a, const T b) {
return a + b;
}
};
template<typename T>
class MaxOp {
public:
static __device__ inline T apply(const T a, const T b) {
return max(a,b);
}
};
cudaError_t segmentedScanTest(int *c, const int *a, const int *b, unsigned int size);
template<typename T, class OP>
__device__ void compute_segscan(volatile T *p, volatile int *hd,
const unsigned int tid, const unsigned int offset) {
const unsigned int lane = tid & 31;
if (lane >= offset) {
p[tid] = hd[tid] ? p[tid] : OP::apply(p[tid - offset],p[tid]);
hd[tid] = hd[tid - offset] | hd[tid];
}
}
/**
* Figure 6
*/
template<typename T, int Kind, class OP>
__device__ T segscan_warp(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int lane = tid & 31;
compute_segscan<T,OP>(p, hd, tid, 1);
compute_segscan<T,OP>(p, hd, tid, 2);
compute_segscan<T,OP>(p, hd, tid, 4);
compute_segscan<T,OP>(p, hd, tid, 8);
compute_segscan<T,OP>(p, hd, tid, 16);
if (Kind == 0)
return p[tid];
else
return (lane > 0) ? p[tid - 1] : 0;
}
template <typename T, class OP>
__global__ void segscan_warp_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
segscan_warp<int,0,OP>(dst, flag, threadIdx.x);
}
/**
* Figure 3
*/
template<typename T, int Kind, class OP>
__device__ T scan_warp(volatile T *p,
const unsigned int tid = threadIdx.x) {
const int lane = tid & 31;
if (lane >= 1)
p[tid] = OP::apply(p[tid - 1], p[tid]);
if (lane >= 2)
p[tid] = OP::apply(p[tid - 2], p[tid]);
if (lane >= 4)
p[tid] = OP::apply(p[tid - 4], p[tid]);
if (lane >= 8)
p[tid] = OP::apply(p[tid - 8], p[tid]);
if (lane >= 16)
p[tid] = OP::apply(p[tid - 16], p[tid]);
return p[tid];
}
/**
* Figure 7
*/
template<typename T, int Kind, class OP>
__device__ T segscan_warp2(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int lane = tid & 31;
if (hd[tid])
hd[tid] = lane;
int mindex = scan_warp<T,Kind, MaxOp<T> >(hd,tid);
if (lane >= mindex + 1)
p[tid] = OP::apply(p[tid - 1],p[tid]);
if (lane >= mindex + 2)
p[tid] = OP::apply(p[tid - 2], p[tid]);
if (lane >= mindex + 4)
p[tid] = OP::apply(p[tid - 4], p[tid]);
if (lane >= mindex + 8)
p[tid] = OP::apply(p[tid - 8], p[tid]);
if (lane >= mindex + 16)
p[tid] = OP::apply(p[tid - 16], p[tid]);
if (Kind == 0)
return p[tid];
else
return (lane > 0 && mindex != lane) ? p[tid - 1] : 0;
}
template <typename T, class OP>
__global__ void segscan_warp2_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
dst[tid] = segscan_warp2<int,0, OP>(dst, flag, tid);
}
/**
* Figure 10
*/
template<typename T, int Kind, class OP>
__device__ T segscan_block(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int warpid = tid >> 5;
const unsigned int warp_first = warpid << 5;
const unsigned int warp_last = warp_first + 31;
// step 1a
bool warp_is_open = (hd[warp_first] == 0);
__syncthreads();
// step 1b
T val = segscan_warp2<T,Kind, OP>(p, hd, tid);
// step 2a
T warp_total = p[warp_last];
// step 2b
int warp_flag = hd[warp_last] != 0 || !warp_is_open;
bool will_accumulate = warp_is_open && hd[tid] == 0;
__syncthreads();
// step 2c
if (tid == warp_last) {
p[warpid] = warp_total;
hd[warpid] = warp_flag;
}
__syncthreads();
// step 3
if (warpid == 0)
segscan_warp2<T,0, OP>(p, hd, tid);
__syncthreads();
// step 4
if (warpid != 0 && will_accumulate)
val = OP::apply( p[tid - 1] , val);
p[tid] = val;
__syncthreads();
return val;
}
template <typename T, class OP>
__global__ void segscan_block_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
dst[tid] = segscan_block<int,0, OP>(dst, flag, tid);
}
template <typename T, class OP, unsigned int SIZE>
__global__ void segscan_block_kernel_smem(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
__shared__ T smem[SIZE];
smem[tid] = src[tid];
dst[tid] = segscan_block<int,0, OP>(smem, flag, tid);
}
template<typename T>
void segmentedScanCpu( const T *src, T *dst, int *flag, const unsigned int size ) {
dst[0] = src[0];
for ( int i=1; i<size; i++ ) {
dst[i] = flag[i] ? src[i] : dst[i-1] + src[i];
}
}
int main() {
const int arraySize = 1024;
int src[arraySize];
int hd[arraySize]={0};
int dst[arraySize] = { 0 };
int dstCpu[arraySize] = { 0 };
for ( int i=0; i<arraySize; i++) {
src[i] = i;
hd[i] = (i % 4)==0 ? 1 : 0;
}
cudaError_t cudaStatus = segmentedScanTest(dst, src, hd, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
const char *fmt = "%4d";
for ( int i=0; i<32; i++ ) {
printf(fmt, src[i]);
}
puts("");
for ( int i=0; i<32; i++ ) {
printf(fmt, hd[i]);
}
puts("");
for ( int i=0; i<32; i++ ) {
printf(fmt, dst[i]);
}
puts("");
segmentedScanCpu(src, dstCpu, hd, arraySize);
for ( int i=0; i<arraySize; i++ ) {
if ( dstCpu[i] != dst[i] ) {
puts("compared... not ok");
break;
}
}
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t segmentedScanTest(int *c, const int *a, const int *b, unsigned int size) {
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr,
"cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = cudaMalloc((void**) &dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**) &dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**) &dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int),
cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int),
cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
// segscan_warp_kernel<int, AddOp<int> ><<<1, 32>>>(dev_a, dev_c, dev_b);
//scan_warp_max_kernel<<<1, 32>>>(dev_b, dev_c);
//segscan_warp2_kernel<<<1, 32>>>(dev_a, dev_c, dev_b);
segscan_block_kernel<int, AddOp<int> ><<<1, size>>>(dev_a, dev_c, dev_b);
//segscan_block_kernel_smem<int, 2048><<<1, size>>>(dev_a, dev_c, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, " launch failed: %s\n",
cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr,
"cudaDeviceSynchronize returned error code %d after launching addKernel!\n",
cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int),
cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error: cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | /**
* Segmented Scan CUDA sample
*
* Original:
* "Efficient Parallel Scan Algorithms for GPUs",
* Shubhabrata Sengupta,Mark Harris, Michael Garland.
* https://research.nvidia.com/sites/default/files/publications/nvr-2008-003.pdf
*
* via
* aokomoriuta san
* http://qiita.com/aokomoriuta/items/3c2a80181a01c7f22e7f
*
* Using a template kernel.cu in NVIDIA Cuda Toolkit 5.5
*/
#include "hip/hip_runtime.h"
#include <stdio.h>
template<typename T>
class AddOp {
public:
static __device__ inline T apply(const T a, const T b) {
return a + b;
}
};
template<typename T>
class MaxOp {
public:
static __device__ inline T apply(const T a, const T b) {
return max(a,b);
}
};
hipError_t segmentedScanTest(int *c, const int *a, const int *b, unsigned int size);
template<typename T, class OP>
__device__ void compute_segscan(volatile T *p, volatile int *hd,
const unsigned int tid, const unsigned int offset) {
const unsigned int lane = tid & 31;
if (lane >= offset) {
p[tid] = hd[tid] ? p[tid] : OP::apply(p[tid - offset],p[tid]);
hd[tid] = hd[tid - offset] | hd[tid];
}
}
/**
* Figure 6
*/
template<typename T, int Kind, class OP>
__device__ T segscan_warp(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int lane = tid & 31;
compute_segscan<T,OP>(p, hd, tid, 1);
compute_segscan<T,OP>(p, hd, tid, 2);
compute_segscan<T,OP>(p, hd, tid, 4);
compute_segscan<T,OP>(p, hd, tid, 8);
compute_segscan<T,OP>(p, hd, tid, 16);
if (Kind == 0)
return p[tid];
else
return (lane > 0) ? p[tid - 1] : 0;
}
template <typename T, class OP>
__global__ void segscan_warp_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
segscan_warp<int,0,OP>(dst, flag, threadIdx.x);
}
/**
* Figure 3
*/
template<typename T, int Kind, class OP>
__device__ T scan_warp(volatile T *p,
const unsigned int tid = threadIdx.x) {
const int lane = tid & 31;
if (lane >= 1)
p[tid] = OP::apply(p[tid - 1], p[tid]);
if (lane >= 2)
p[tid] = OP::apply(p[tid - 2], p[tid]);
if (lane >= 4)
p[tid] = OP::apply(p[tid - 4], p[tid]);
if (lane >= 8)
p[tid] = OP::apply(p[tid - 8], p[tid]);
if (lane >= 16)
p[tid] = OP::apply(p[tid - 16], p[tid]);
return p[tid];
}
/**
* Figure 7
*/
template<typename T, int Kind, class OP>
__device__ T segscan_warp2(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int lane = tid & 31;
if (hd[tid])
hd[tid] = lane;
int mindex = scan_warp<T,Kind, MaxOp<T> >(hd,tid);
if (lane >= mindex + 1)
p[tid] = OP::apply(p[tid - 1],p[tid]);
if (lane >= mindex + 2)
p[tid] = OP::apply(p[tid - 2], p[tid]);
if (lane >= mindex + 4)
p[tid] = OP::apply(p[tid - 4], p[tid]);
if (lane >= mindex + 8)
p[tid] = OP::apply(p[tid - 8], p[tid]);
if (lane >= mindex + 16)
p[tid] = OP::apply(p[tid - 16], p[tid]);
if (Kind == 0)
return p[tid];
else
return (lane > 0 && mindex != lane) ? p[tid - 1] : 0;
}
template <typename T, class OP>
__global__ void segscan_warp2_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
dst[tid] = segscan_warp2<int,0, OP>(dst, flag, tid);
}
/**
* Figure 10
*/
template<typename T, int Kind, class OP>
__device__ T segscan_block(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int warpid = tid >> 5;
const unsigned int warp_first = warpid << 5;
const unsigned int warp_last = warp_first + 31;
// step 1a
bool warp_is_open = (hd[warp_first] == 0);
__syncthreads();
// step 1b
T val = segscan_warp2<T,Kind, OP>(p, hd, tid);
// step 2a
T warp_total = p[warp_last];
// step 2b
int warp_flag = hd[warp_last] != 0 || !warp_is_open;
bool will_accumulate = warp_is_open && hd[tid] == 0;
__syncthreads();
// step 2c
if (tid == warp_last) {
p[warpid] = warp_total;
hd[warpid] = warp_flag;
}
__syncthreads();
// step 3
if (warpid == 0)
segscan_warp2<T,0, OP>(p, hd, tid);
__syncthreads();
// step 4
if (warpid != 0 && will_accumulate)
val = OP::apply( p[tid - 1] , val);
p[tid] = val;
__syncthreads();
return val;
}
template <typename T, class OP>
__global__ void segscan_block_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
dst[tid] = segscan_block<int,0, OP>(dst, flag, tid);
}
template <typename T, class OP, unsigned int SIZE>
__global__ void segscan_block_kernel_smem(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
__shared__ T smem[SIZE];
smem[tid] = src[tid];
dst[tid] = segscan_block<int,0, OP>(smem, flag, tid);
}
template<typename T>
void segmentedScanCpu( const T *src, T *dst, int *flag, const unsigned int size ) {
dst[0] = src[0];
for ( int i=1; i<size; i++ ) {
dst[i] = flag[i] ? src[i] : dst[i-1] + src[i];
}
}
int main() {
const int arraySize = 1024;
int src[arraySize];
int hd[arraySize]={0};
int dst[arraySize] = { 0 };
int dstCpu[arraySize] = { 0 };
for ( int i=0; i<arraySize; i++) {
src[i] = i;
hd[i] = (i % 4)==0 ? 1 : 0;
}
hipError_t cudaStatus = segmentedScanTest(dst, src, hd, arraySize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
const char *fmt = "%4d";
for ( int i=0; i<32; i++ ) {
printf(fmt, src[i]);
}
puts("");
for ( int i=0; i<32; i++ ) {
printf(fmt, hd[i]);
}
puts("");
for ( int i=0; i<32; i++ ) {
printf(fmt, dst[i]);
}
puts("");
segmentedScanCpu(src, dstCpu, hd, arraySize);
for ( int i=0; i<arraySize; i++ ) {
if ( dstCpu[i] != dst[i] ) {
puts("compared... not ok");
break;
}
}
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t segmentedScanTest(int *c, const int *a, const int *b, unsigned int size) {
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr,
"hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = hipMalloc((void**) &dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**) &dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**) &dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int),
hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int),
hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
// segscan_warp_kernel<int, AddOp<int> ><<<1, 32>>>(dev_a, dev_c, dev_b);
//scan_warp_max_kernel<<<1, 32>>>(dev_b, dev_c);
//segscan_warp2_kernel<<<1, 32>>>(dev_a, dev_c, dev_b);
segscan_block_kernel<int, AddOp<int> ><<<1, size>>>(dev_a, dev_c, dev_b);
//segscan_block_kernel_smem<int, 2048><<<1, size>>>(dev_a, dev_c, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, " launch failed: %s\n",
hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr,
"hipDeviceSynchronize returned error code %d after launching addKernel!\n",
cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int),
hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error: hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Segmented Scan CUDA sample
*
* Original:
* "Efficient Parallel Scan Algorithms for GPUs",
* Shubhabrata Sengupta,Mark Harris, Michael Garland.
* https://research.nvidia.com/sites/default/files/publications/nvr-2008-003.pdf
*
* via
* aokomoriuta san
* http://qiita.com/aokomoriuta/items/3c2a80181a01c7f22e7f
*
* Using a template kernel.cu in NVIDIA Cuda Toolkit 5.5
*/
#include "hip/hip_runtime.h"
#include <stdio.h>
template<typename T>
class AddOp {
public:
static __device__ inline T apply(const T a, const T b) {
return a + b;
}
};
template<typename T>
class MaxOp {
public:
static __device__ inline T apply(const T a, const T b) {
return max(a,b);
}
};
hipError_t segmentedScanTest(int *c, const int *a, const int *b, unsigned int size);
template<typename T, class OP>
__device__ void compute_segscan(volatile T *p, volatile int *hd,
const unsigned int tid, const unsigned int offset) {
const unsigned int lane = tid & 31;
if (lane >= offset) {
p[tid] = hd[tid] ? p[tid] : OP::apply(p[tid - offset],p[tid]);
hd[tid] = hd[tid - offset] | hd[tid];
}
}
/**
* Figure 6
*/
template<typename T, int Kind, class OP>
__device__ T segscan_warp(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int lane = tid & 31;
compute_segscan<T,OP>(p, hd, tid, 1);
compute_segscan<T,OP>(p, hd, tid, 2);
compute_segscan<T,OP>(p, hd, tid, 4);
compute_segscan<T,OP>(p, hd, tid, 8);
compute_segscan<T,OP>(p, hd, tid, 16);
if (Kind == 0)
return p[tid];
else
return (lane > 0) ? p[tid - 1] : 0;
}
template <typename T, class OP>
__global__ void segscan_warp_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
segscan_warp<int,0,OP>(dst, flag, threadIdx.x);
}
/**
* Figure 3
*/
template<typename T, int Kind, class OP>
__device__ T scan_warp(volatile T *p,
const unsigned int tid = threadIdx.x) {
const int lane = tid & 31;
if (lane >= 1)
p[tid] = OP::apply(p[tid - 1], p[tid]);
if (lane >= 2)
p[tid] = OP::apply(p[tid - 2], p[tid]);
if (lane >= 4)
p[tid] = OP::apply(p[tid - 4], p[tid]);
if (lane >= 8)
p[tid] = OP::apply(p[tid - 8], p[tid]);
if (lane >= 16)
p[tid] = OP::apply(p[tid - 16], p[tid]);
return p[tid];
}
/**
* Figure 7
*/
template<typename T, int Kind, class OP>
__device__ T segscan_warp2(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int lane = tid & 31;
if (hd[tid])
hd[tid] = lane;
int mindex = scan_warp<T,Kind, MaxOp<T> >(hd,tid);
if (lane >= mindex + 1)
p[tid] = OP::apply(p[tid - 1],p[tid]);
if (lane >= mindex + 2)
p[tid] = OP::apply(p[tid - 2], p[tid]);
if (lane >= mindex + 4)
p[tid] = OP::apply(p[tid - 4], p[tid]);
if (lane >= mindex + 8)
p[tid] = OP::apply(p[tid - 8], p[tid]);
if (lane >= mindex + 16)
p[tid] = OP::apply(p[tid - 16], p[tid]);
if (Kind == 0)
return p[tid];
else
return (lane > 0 && mindex != lane) ? p[tid - 1] : 0;
}
template <typename T, class OP>
__global__ void segscan_warp2_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
dst[tid] = segscan_warp2<int,0, OP>(dst, flag, tid);
}
/**
* Figure 10
*/
template<typename T, int Kind, class OP>
__device__ T segscan_block(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int warpid = tid >> 5;
const unsigned int warp_first = warpid << 5;
const unsigned int warp_last = warp_first + 31;
// step 1a
bool warp_is_open = (hd[warp_first] == 0);
__syncthreads();
// step 1b
T val = segscan_warp2<T,Kind, OP>(p, hd, tid);
// step 2a
T warp_total = p[warp_last];
// step 2b
int warp_flag = hd[warp_last] != 0 || !warp_is_open;
bool will_accumulate = warp_is_open && hd[tid] == 0;
__syncthreads();
// step 2c
if (tid == warp_last) {
p[warpid] = warp_total;
hd[warpid] = warp_flag;
}
__syncthreads();
// step 3
if (warpid == 0)
segscan_warp2<T,0, OP>(p, hd, tid);
__syncthreads();
// step 4
if (warpid != 0 && will_accumulate)
val = OP::apply( p[tid - 1] , val);
p[tid] = val;
__syncthreads();
return val;
}
template <typename T, class OP>
__global__ void segscan_block_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
dst[tid] = segscan_block<int,0, OP>(dst, flag, tid);
}
template <typename T, class OP, unsigned int SIZE>
__global__ void segscan_block_kernel_smem(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
__shared__ T smem[SIZE];
smem[tid] = src[tid];
dst[tid] = segscan_block<int,0, OP>(smem, flag, tid);
}
template<typename T>
void segmentedScanCpu( const T *src, T *dst, int *flag, const unsigned int size ) {
dst[0] = src[0];
for ( int i=1; i<size; i++ ) {
dst[i] = flag[i] ? src[i] : dst[i-1] + src[i];
}
}
int main() {
const int arraySize = 1024;
int src[arraySize];
int hd[arraySize]={0};
int dst[arraySize] = { 0 };
int dstCpu[arraySize] = { 0 };
for ( int i=0; i<arraySize; i++) {
src[i] = i;
hd[i] = (i % 4)==0 ? 1 : 0;
}
hipError_t cudaStatus = segmentedScanTest(dst, src, hd, arraySize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
const char *fmt = "%4d";
for ( int i=0; i<32; i++ ) {
printf(fmt, src[i]);
}
puts("");
for ( int i=0; i<32; i++ ) {
printf(fmt, hd[i]);
}
puts("");
for ( int i=0; i<32; i++ ) {
printf(fmt, dst[i]);
}
puts("");
segmentedScanCpu(src, dstCpu, hd, arraySize);
for ( int i=0; i<arraySize; i++ ) {
if ( dstCpu[i] != dst[i] ) {
puts("compared... not ok");
break;
}
}
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t segmentedScanTest(int *c, const int *a, const int *b, unsigned int size) {
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr,
"hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = hipMalloc((void**) &dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**) &dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**) &dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int),
hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int),
hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
// segscan_warp_kernel<int, AddOp<int> ><<<1, 32>>>(dev_a, dev_c, dev_b);
//scan_warp_max_kernel<<<1, 32>>>(dev_b, dev_c);
//segscan_warp2_kernel<<<1, 32>>>(dev_a, dev_c, dev_b);
segscan_block_kernel<int, AddOp<int> ><<<1, size>>>(dev_a, dev_c, dev_b);
//segscan_block_kernel_smem<int, 2048><<<1, size>>>(dev_a, dev_c, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, " launch failed: %s\n",
hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr,
"hipDeviceSynchronize returned error code %d after launching addKernel!\n",
cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int),
hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error: hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,"axG",@progbits,_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,comdat
.protected _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.globl _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.p2align 8
.type _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,@function
_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
v_and_b32_e32 v3, 0x3e0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
v_add_co_u32 v5, s0, s8, v3
v_add_co_ci_u32_e64 v6, null, s9, 0, s0
v_add_co_u32 v3, s0, s8, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s9, 0, s0
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
global_store_b32 v1, v2, s[6:7]
flat_load_b32 v7, v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
flat_load_b32 v2, v[3:4] glc dlc
s_waitcnt vmcnt(0)
v_and_b32_e32 v5, 31, v0
s_waitcnt lgkmcnt(0)
v_cmpx_ne_u32_e32 0, v2
s_cbranch_execz .LBB0_2
flat_store_b32 v[3:4], v5 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_ne_u32_e32 vcc_lo, 0, v5
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, s0, s8, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, s9, v9, s0
flat_load_b32 v2, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v2, v2, v6
flat_store_b32 v[3:4], v2 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_lt_u32_e64 s0, 1, v5
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_6
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, -2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, s1, s8, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s1, s9, v9, s1
flat_load_b32 v2, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v2, v2, v6
flat_store_b32 v[3:4], v2 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_lt_u32_e64 s1, 3, v5
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, -4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, s2, s8, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s2, s9, v9, s2
flat_load_b32 v2, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v2, v2, v6
flat_store_b32 v[3:4], v2 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_lt_u32_e64 s2, 7, v5
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, -8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, s3, s8, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s3, s9, v9, s3
flat_load_b32 v2, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v2, v2, v6
flat_store_b32 v[3:4], v2 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s4
v_add_co_u32 v1, s3, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s7, 0, s3
v_cmp_lt_u32_e64 s3, 15, v5
s_and_saveexec_b32 s5, s3
s_cbranch_execz .LBB0_12
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, -16, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, s4, s8, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s4, s9, v9, s4
flat_load_b32 v6, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v8, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v6, v6, v8
flat_store_b32 v[3:4], v6 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s5
flat_load_b32 v6, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v8, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e64 s4, v5, v8
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_14
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, s4, s6, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s4, s7, v9, s4
flat_load_b32 v8, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v8, v9, v8
flat_store_b32 v[1:2], v8 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v8, 2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e64 s4, v5, v8
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, -2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, s4, s6, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s4, s7, v9, s4
flat_load_b32 v8, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v8, v9, v8
flat_store_b32 v[1:2], v8 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v8, 4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e64 s4, v5, v8
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_18
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, -4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, s4, s6, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s4, s7, v9, s4
flat_load_b32 v8, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v8, v9, v8
flat_store_b32 v[1:2], v8 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v8, 8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e64 s4, v5, v8
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_20
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, -8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, s4, s6, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s4, s7, v9, s4
flat_load_b32 v8, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v8, v9, v8
flat_store_b32 v[1:2], v8 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v6, 16, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e64 s4, v5, v6
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_22
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, -16, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, s4, s6, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s4, s7, v9, s4
flat_load_b32 v6, v[8:9] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v8, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v6, v8, v6
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s5
v_or_b32_e32 v9, 31, v0
v_cmp_eq_u32_e64 s5, 0, v7
s_mov_b32 s10, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 2, v9
v_add_co_u32 v10, s4, s6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, null, s7, 0, s4
v_add_co_u32 v12, s4, s8, v6
v_add_co_ci_u32_e64 v13, null, s9, 0, s4
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v8, v[10:11] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v10, v[12:13] glc dlc
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e64 s4, 0, v7
s_and_saveexec_b32 s11, s5
s_cbranch_execz .LBB0_24
flat_load_b32 v7, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u32_e64 s5, 0, v7
s_delay_alu instid0(VALU_DEP_1)
s_or_not1_b32 s10, s5, exec_lo
.LBB0_24:
s_or_b32 exec_lo, exec_lo, s11
v_cmp_eq_u32_e64 s5, v9, v0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s11, s5
s_cbranch_execz .LBB0_26
v_lshrrev_b32_e32 v7, 3, v0
v_cmp_ne_u32_e64 s5, 0, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v7, 0x7c, v7
s_or_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v13, 0, 1, s4
v_add_co_u32 v9, s4, s6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v10, null, s7, 0, s4
v_add_co_u32 v11, s4, s8, v7
v_add_co_ci_u32_e64 v12, null, s9, 0, s4
flat_store_b32 v[9:10], v8 dlc
s_waitcnt_vscnt null, 0x0
flat_store_b32 v[11:12], v13 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s11
v_cmp_gt_u32_e64 s4, 32, v0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_50
flat_load_b32 v7, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u32_e64 s4, 0, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s11, s4
s_cbranch_execz .LBB0_29
flat_store_b32 v[3:4], v5 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s11
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_31
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
flat_load_b32 v7, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v8, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v7, v7, v8
flat_store_b32 v[3:4], v7 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_31:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB0_33
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, -2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
flat_load_b32 v7, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v8, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v7, v7, v8
flat_store_b32 v[3:4], v7 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_33:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_35
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, -4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
flat_load_b32 v7, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v8, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v7, v7, v8
flat_store_b32 v[3:4], v7 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_37
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, -8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
flat_load_b32 v7, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v8, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v7, v7, v8
flat_store_b32 v[3:4], v7 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_37:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB0_39
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, -16, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
flat_load_b32 v7, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v8, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_max_i32_e32 v7, v7, v8
flat_store_b32 v[3:4], v7 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_39:
s_or_b32 exec_lo, exec_lo, s0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, 1, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_u32_e64 v5, v4
s_cbranch_execz .LBB0_41
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
flat_load_b32 v4, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v7, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v4, v7, v4
flat_store_b32 v[1:2], v4 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_41:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v4, 2, v3
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_u32_e64 v5, v4
s_cbranch_execz .LBB0_43
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, -2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
flat_load_b32 v4, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v7, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v4, v7, v4
flat_store_b32 v[1:2], v4 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_43:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v4, 4, v3
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_u32_e64 v5, v4
s_cbranch_execz .LBB0_45
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, -4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
flat_load_b32 v4, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v7, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v4, v7, v4
flat_store_b32 v[1:2], v4 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_45:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v4, 8, v3
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_u32_e64 v5, v4
s_cbranch_execz .LBB0_47
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, -8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
flat_load_b32 v4, v[7:8] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v7, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v4, v7, v4
flat_store_b32 v[1:2], v4 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_47:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v3, 16, v3
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_u32_e64 v5, v3
s_cbranch_execz .LBB0_49
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, -16, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_49:
s_or_b32 exec_lo, exec_lo, s0
flat_load_b32 v3, v[1:2] glc dlc
s_waitcnt vmcnt(0)
s_or_b32 s10, s10, exec_lo
.LBB0_50:
s_or_b32 exec_lo, exec_lo, s5
s_xor_b32 s1, s10, -1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_52
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
flat_load_b32 v0, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v6, v0, v6
.LBB0_52:
s_or_b32 exec_lo, exec_lo, s0
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_store_b32 v[1:2], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,"axG",@progbits,_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,comdat
.Lfunc_end0:
.size _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, .Lfunc_end0-_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Segmented Scan CUDA sample
*
* Original:
* "Efficient Parallel Scan Algorithms for GPUs",
* Shubhabrata Sengupta,Mark Harris, Michael Garland.
* https://research.nvidia.com/sites/default/files/publications/nvr-2008-003.pdf
*
* via
* aokomoriuta san
* http://qiita.com/aokomoriuta/items/3c2a80181a01c7f22e7f
*
* Using a template kernel.cu in NVIDIA Cuda Toolkit 5.5
*/
#include "hip/hip_runtime.h"
#include <stdio.h>
template<typename T>
class AddOp {
public:
static __device__ inline T apply(const T a, const T b) {
return a + b;
}
};
template<typename T>
class MaxOp {
public:
static __device__ inline T apply(const T a, const T b) {
return max(a,b);
}
};
hipError_t segmentedScanTest(int *c, const int *a, const int *b, unsigned int size);
template<typename T, class OP>
__device__ void compute_segscan(volatile T *p, volatile int *hd,
const unsigned int tid, const unsigned int offset) {
const unsigned int lane = tid & 31;
if (lane >= offset) {
p[tid] = hd[tid] ? p[tid] : OP::apply(p[tid - offset],p[tid]);
hd[tid] = hd[tid - offset] | hd[tid];
}
}
/**
* Figure 6
*/
template<typename T, int Kind, class OP>
__device__ T segscan_warp(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int lane = tid & 31;
compute_segscan<T,OP>(p, hd, tid, 1);
compute_segscan<T,OP>(p, hd, tid, 2);
compute_segscan<T,OP>(p, hd, tid, 4);
compute_segscan<T,OP>(p, hd, tid, 8);
compute_segscan<T,OP>(p, hd, tid, 16);
if (Kind == 0)
return p[tid];
else
return (lane > 0) ? p[tid - 1] : 0;
}
template <typename T, class OP>
__global__ void segscan_warp_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
segscan_warp<int,0,OP>(dst, flag, threadIdx.x);
}
/**
* Figure 3
*/
template<typename T, int Kind, class OP>
__device__ T scan_warp(volatile T *p,
const unsigned int tid = threadIdx.x) {
const int lane = tid & 31;
if (lane >= 1)
p[tid] = OP::apply(p[tid - 1], p[tid]);
if (lane >= 2)
p[tid] = OP::apply(p[tid - 2], p[tid]);
if (lane >= 4)
p[tid] = OP::apply(p[tid - 4], p[tid]);
if (lane >= 8)
p[tid] = OP::apply(p[tid - 8], p[tid]);
if (lane >= 16)
p[tid] = OP::apply(p[tid - 16], p[tid]);
return p[tid];
}
/**
* Figure 7
*/
template<typename T, int Kind, class OP>
__device__ T segscan_warp2(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int lane = tid & 31;
if (hd[tid])
hd[tid] = lane;
int mindex = scan_warp<T,Kind, MaxOp<T> >(hd,tid);
if (lane >= mindex + 1)
p[tid] = OP::apply(p[tid - 1],p[tid]);
if (lane >= mindex + 2)
p[tid] = OP::apply(p[tid - 2], p[tid]);
if (lane >= mindex + 4)
p[tid] = OP::apply(p[tid - 4], p[tid]);
if (lane >= mindex + 8)
p[tid] = OP::apply(p[tid - 8], p[tid]);
if (lane >= mindex + 16)
p[tid] = OP::apply(p[tid - 16], p[tid]);
if (Kind == 0)
return p[tid];
else
return (lane > 0 && mindex != lane) ? p[tid - 1] : 0;
}
template <typename T, class OP>
__global__ void segscan_warp2_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
dst[tid] = segscan_warp2<int,0, OP>(dst, flag, tid);
}
/**
* Figure 10
*/
template<typename T, int Kind, class OP>
__device__ T segscan_block(volatile T *p, volatile int *hd,
const unsigned int tid = threadIdx.x) {
const unsigned int warpid = tid >> 5;
const unsigned int warp_first = warpid << 5;
const unsigned int warp_last = warp_first + 31;
// step 1a
bool warp_is_open = (hd[warp_first] == 0);
__syncthreads();
// step 1b
T val = segscan_warp2<T,Kind, OP>(p, hd, tid);
// step 2a
T warp_total = p[warp_last];
// step 2b
int warp_flag = hd[warp_last] != 0 || !warp_is_open;
bool will_accumulate = warp_is_open && hd[tid] == 0;
__syncthreads();
// step 2c
if (tid == warp_last) {
p[warpid] = warp_total;
hd[warpid] = warp_flag;
}
__syncthreads();
// step 3
if (warpid == 0)
segscan_warp2<T,0, OP>(p, hd, tid);
__syncthreads();
// step 4
if (warpid != 0 && will_accumulate)
val = OP::apply( p[tid - 1] , val);
p[tid] = val;
__syncthreads();
return val;
}
template <typename T, class OP>
__global__ void segscan_block_kernel(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
dst[tid] = src[tid];
dst[tid] = segscan_block<int,0, OP>(dst, flag, tid);
}
template <typename T, class OP, unsigned int SIZE>
__global__ void segscan_block_kernel_smem(const T *src, T *dst, int *flag) {
const unsigned int tid = threadIdx.x;
__shared__ T smem[SIZE];
smem[tid] = src[tid];
dst[tid] = segscan_block<int,0, OP>(smem, flag, tid);
}
template<typename T>
void segmentedScanCpu( const T *src, T *dst, int *flag, const unsigned int size ) {
dst[0] = src[0];
for ( int i=1; i<size; i++ ) {
dst[i] = flag[i] ? src[i] : dst[i-1] + src[i];
}
}
int main() {
const int arraySize = 1024;
int src[arraySize];
int hd[arraySize]={0};
int dst[arraySize] = { 0 };
int dstCpu[arraySize] = { 0 };
for ( int i=0; i<arraySize; i++) {
src[i] = i;
hd[i] = (i % 4)==0 ? 1 : 0;
}
hipError_t cudaStatus = segmentedScanTest(dst, src, hd, arraySize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
const char *fmt = "%4d";
for ( int i=0; i<32; i++ ) {
printf(fmt, src[i]);
}
puts("");
for ( int i=0; i<32; i++ ) {
printf(fmt, hd[i]);
}
puts("");
for ( int i=0; i<32; i++ ) {
printf(fmt, dst[i]);
}
puts("");
segmentedScanCpu(src, dstCpu, hd, arraySize);
for ( int i=0; i<arraySize; i++ ) {
if ( dstCpu[i] != dst[i] ) {
puts("compared... not ok");
break;
}
}
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t segmentedScanTest(int *c, const int *a, const int *b, unsigned int size) {
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr,
"hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = hipMalloc((void**) &dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**) &dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**) &dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int),
hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int),
hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
// segscan_warp_kernel<int, AddOp<int> ><<<1, 32>>>(dev_a, dev_c, dev_b);
//scan_warp_max_kernel<<<1, 32>>>(dev_b, dev_c);
//segscan_warp2_kernel<<<1, 32>>>(dev_a, dev_c, dev_b);
segscan_block_kernel<int, AddOp<int> ><<<1, size>>>(dev_a, dev_c, dev_b);
//segscan_block_kernel_smem<int, 2048><<<1, size>>>(dev_a, dev_c, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, " launch failed: %s\n",
hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr,
"hipDeviceSynchronize returned error code %d after launching addKernel!\n",
cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int),
hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error: hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} | .text
.file "segscan.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16384, %rsp # imm = 0x4000
.cfi_def_cfa_offset 16400
.cfi_offset %rbx, -16
leaq 8192(%rsp), %rdi
xorl %ebx, %ebx
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
leaq 12288(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
leaq 4096(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rsp,%rbx,4)
xorl %eax, %eax
testb $3, %bl
sete %al
movl %eax, 8192(%rsp,%rbx,4)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB0_1
# %bb.2:
leaq 12288(%rsp), %rdi
movq %rsp, %rsi
leaq 8192(%rsp), %rdx
movl $1024, %ecx # imm = 0x400
callq _Z17segmentedScanTestPiPKiS1_j
testl %eax, %eax
jne .LBB0_22
# %bb.3: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_4: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB0_4
# %bb.5:
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_6: # =>This Inner Loop Header: Depth=1
movl 8192(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB0_6
# %bb.7:
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_8: # =>This Inner Loop Header: Depth=1
movl 12288(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB0_8
# %bb.9:
movl $10, %edi
callq putchar@PLT
movl (%rsp), %eax
movl %eax, 4096(%rsp)
movl $1, %eax
jmp .LBB0_10
.p2align 4, 0x90
.LBB0_12: # in Loop: Header=BB0_10 Depth=1
movl (%rsp,%rax,4), %ecx
addl 4092(%rsp,%rax,4), %ecx
.LBB0_13: # in Loop: Header=BB0_10 Depth=1
movl %ecx, 4096(%rsp,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
je .LBB0_14
.LBB0_10: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
cmpl $0, 8192(%rsp,%rax,4)
je .LBB0_12
# %bb.11: # in Loop: Header=BB0_10 Depth=1
movl (%rsp,%rax,4), %ecx
jmp .LBB0_13
.LBB0_14: # %_Z16segmentedScanCpuIiEvPKT_PS0_Pij.exit.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_16: # %_Z16segmentedScanCpuIiEvPKT_PS0_Pij.exit.preheader
# =>This Inner Loop Header: Depth=1
movl 4096(%rsp,%rax,4), %ecx
cmpl 12288(%rsp,%rax,4), %ecx
jne .LBB0_17
# %bb.15: # %_Z16segmentedScanCpuIiEvPKT_PS0_Pij.exit
# in Loop: Header=BB0_16 Depth=1
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB0_16
jmp .LBB0_18
.LBB0_17:
movl $.L.str.3, %edi
callq puts
.LBB0_18: # %.loopexit
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB0_19
.LBB0_21:
addq $16384, %rsp # imm = 0x4000
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_22:
.cfi_def_cfa_offset 16400
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $19, %esi
jmp .LBB0_20
.LBB0_19:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $22, %esi
.LBB0_20:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB0_21
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z17segmentedScanTestPiPKiS1_j # -- Begin function _Z17segmentedScanTestPiPKiS1_j
.p2align 4, 0x90
.type _Z17segmentedScanTestPiPKiS1_j,@function
_Z17segmentedScanTestPiPKiS1_j: # @_Z17segmentedScanTestPiPKiS1_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_18
# %bb.1:
movl %ebp, %r15d
leaq (,%r15,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_12
# %bb.2:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_12
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_12
# %bb.4:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.5:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.6:
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r15
orq $1, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_19
# %bb.9:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_20
# %bb.10:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB1_17
# %bb.11:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB1_16
.LBB1_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
jmp .LBB1_14
.LBB1_13:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
.LBB1_14:
movl $17, %esi
.LBB1_15:
movl $1, %edx
.LBB1_16:
callq fwrite@PLT
.LBB1_17:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 176
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $63, %esi
jmp .LBB1_15
.LBB1_19:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_17
.LBB1_20:
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_17
.Lfunc_end1:
.size _Z17segmentedScanTestPiPKiS1_j, .Lfunc_end1-_Z17segmentedScanTestPiPKiS1_j
.cfi_endproc
# -- End function
.section .text._Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,"axG",@progbits,_Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,comdat
.weak _Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi # -- Begin function _Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.p2align 4, 0x90
.type _Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,@function
_Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi: # @_Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, .Lfunc_end2-_Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "addWithCuda failed!"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%4d"
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "compared... not ok"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipDeviceReset failed!"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.5, 64
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMalloc failed!"
.size .L.str.6, 18
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy failed!"
.size .L.str.7, 18
.type _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,@object # @_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.section .rodata._Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,"aG",@progbits,_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,comdat
.weak _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.p2align 3, 0x0
_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi:
.quad _Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.size _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz " launch failed: %s\n"
.size .L.str.8, 20
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.9, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007df36_00000000-6_segscan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL61__device_stub__Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_PiPKiPiS1_, @function
_ZL61__device_stub__Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_PiPKiPiS1_:
.LFB2099:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2099:
.size _ZL61__device_stub__Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_PiPKiPiS1_, .-_ZL61__device_stub__Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_PiPKiPiS1_
.section .text._Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,"axG",@progbits,_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,comdat
.weak _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.type _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, @function
_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi:
.LFB2149:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL61__device_stub__Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_PiPKiPiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2149:
.size _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, .-_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string " launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z17segmentedScanTestPiPKiS1_j
.type _Z17segmentedScanTestPiPKiS1_j, @function
_Z17segmentedScanTestPiPKiS1_j:
.LFB2074:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L24
movl %ebp, %r15d
salq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L25
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L29
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L19:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L32
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L13
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L24:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L26:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L27:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L28:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L29:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L30:
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _ZL61__device_stub__Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_PiPKiPiS1_
jmp .L19
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L32:
movl %eax, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2074:
.size _Z17segmentedScanTestPiPKiS1_j, .-_Z17segmentedScanTestPiPKiS1_j
.section .rodata.str1.1
.LC5:
.string "addWithCuda failed!"
.LC6:
.string "%4d"
.LC7:
.string ""
.LC8:
.string "compared... not ok"
.LC9:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB2073:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -16384(%rsp), %r11
.cfi_def_cfa 11, 16424
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $24, %rsp
.cfi_def_cfa_offset 16448
movq %fs:40, %rax
movq %rax, 16392(%rsp)
xorl %eax, %eax
leaq 4096(%rsp), %rdi
movl $512, %ecx
rep stosq
leaq 8192(%rsp), %rdi
movl $512, %ecx
rep stosq
leaq 12288(%rsp), %rdi
movl $512, %ecx
rep stosq
.L35:
movl %eax, (%rsp,%rax,4)
testb $3, %al
sete %dl
movzbl %dl, %edx
movl %edx, 4096(%rsp,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L35
leaq 4096(%rsp), %rdx
movq %rsp, %rsi
leaq 8192(%rsp), %rdi
movl $1024, %ecx
call _Z17segmentedScanTestPiPKiS1_j
movq %rsp, %rbx
leaq 128(%rsp), %r12
leaq .LC6(%rip), %rbp
testl %eax, %eax
jne .L57
.L38:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L38
leaq .LC7(%rip), %rdi
call puts@PLT
leaq 4096(%rsp), %r13
leaq 4224(%rsp), %r12
movq %r13, %rbx
leaq .LC6(%rip), %rbp
.L39:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L39
leaq .LC7(%rip), %rdi
call puts@PLT
leaq 8192(%rsp), %rbx
leaq 8320(%rsp), %r12
leaq .LC6(%rip), %rbp
.L40:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L40
leaq .LC7(%rip), %rdi
call puts@PLT
movl (%rsp), %eax
movl %eax, 12288(%rsp)
leaq 4100(%rsp), %rax
leaq 4(%rsp), %rcx
leaq 12292(%rsp), %rdx
addq $4096, %r13
jmp .L43
.L57:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L34
.L41:
movl (%rcx), %esi
addl -4(%rdx), %esi
.L42:
movl %esi, (%rdx)
addq $4, %rax
addq $4, %rcx
addq $4, %rdx
cmpq %r13, %rax
je .L58
.L43:
cmpl $0, (%rax)
je .L41
movl (%rcx), %esi
jmp .L42
.L58:
movl $0, %eax
leaq 8192(%rsp), %rdx
.L46:
movl (%rdx,%rax), %ecx
cmpl %ecx, 12288(%rsp,%rax)
jne .L59
addq $4, %rax
cmpq $4096, %rax
jne .L46
jmp .L45
.L59:
leaq .LC8(%rip), %rdi
call puts@PLT
.L45:
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L60
.L34:
movq 16392(%rsp), %rdx
subq %fs:40, %rdx
jne .L61
addq $16408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L34
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC10:
.string "_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2102:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2102:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "segscan.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16384, %rsp # imm = 0x4000
.cfi_def_cfa_offset 16400
.cfi_offset %rbx, -16
leaq 8192(%rsp), %rdi
xorl %ebx, %ebx
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
leaq 12288(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
leaq 4096(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %ebx, (%rsp,%rbx,4)
xorl %eax, %eax
testb $3, %bl
sete %al
movl %eax, 8192(%rsp,%rbx,4)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB0_1
# %bb.2:
leaq 12288(%rsp), %rdi
movq %rsp, %rsi
leaq 8192(%rsp), %rdx
movl $1024, %ecx # imm = 0x400
callq _Z17segmentedScanTestPiPKiS1_j
testl %eax, %eax
jne .LBB0_22
# %bb.3: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_4: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB0_4
# %bb.5:
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_6: # =>This Inner Loop Header: Depth=1
movl 8192(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB0_6
# %bb.7:
movl $10, %edi
callq putchar@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_8: # =>This Inner Loop Header: Depth=1
movl 12288(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB0_8
# %bb.9:
movl $10, %edi
callq putchar@PLT
movl (%rsp), %eax
movl %eax, 4096(%rsp)
movl $1, %eax
jmp .LBB0_10
.p2align 4, 0x90
.LBB0_12: # in Loop: Header=BB0_10 Depth=1
movl (%rsp,%rax,4), %ecx
addl 4092(%rsp,%rax,4), %ecx
.LBB0_13: # in Loop: Header=BB0_10 Depth=1
movl %ecx, 4096(%rsp,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
je .LBB0_14
.LBB0_10: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
cmpl $0, 8192(%rsp,%rax,4)
je .LBB0_12
# %bb.11: # in Loop: Header=BB0_10 Depth=1
movl (%rsp,%rax,4), %ecx
jmp .LBB0_13
.LBB0_14: # %_Z16segmentedScanCpuIiEvPKT_PS0_Pij.exit.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_16: # %_Z16segmentedScanCpuIiEvPKT_PS0_Pij.exit.preheader
# =>This Inner Loop Header: Depth=1
movl 4096(%rsp,%rax,4), %ecx
cmpl 12288(%rsp,%rax,4), %ecx
jne .LBB0_17
# %bb.15: # %_Z16segmentedScanCpuIiEvPKT_PS0_Pij.exit
# in Loop: Header=BB0_16 Depth=1
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB0_16
jmp .LBB0_18
.LBB0_17:
movl $.L.str.3, %edi
callq puts
.LBB0_18: # %.loopexit
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB0_19
.LBB0_21:
addq $16384, %rsp # imm = 0x4000
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_22:
.cfi_def_cfa_offset 16400
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $19, %esi
jmp .LBB0_20
.LBB0_19:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $22, %esi
.LBB0_20:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB0_21
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z17segmentedScanTestPiPKiS1_j # -- Begin function _Z17segmentedScanTestPiPKiS1_j
.p2align 4, 0x90
.type _Z17segmentedScanTestPiPKiS1_j,@function
_Z17segmentedScanTestPiPKiS1_j: # @_Z17segmentedScanTestPiPKiS1_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_18
# %bb.1:
movl %ebp, %r15d
leaq (,%r15,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_12
# %bb.2:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_12
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_12
# %bb.4:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.5:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.6:
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r15
orq $1, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_19
# %bb.9:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_20
# %bb.10:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB1_17
# %bb.11:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB1_16
.LBB1_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
jmp .LBB1_14
.LBB1_13:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
.LBB1_14:
movl $17, %esi
.LBB1_15:
movl $1, %edx
.LBB1_16:
callq fwrite@PLT
.LBB1_17:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_18:
.cfi_def_cfa_offset 176
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $63, %esi
jmp .LBB1_15
.LBB1_19:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_17
.LBB1_20:
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_17
.Lfunc_end1:
.size _Z17segmentedScanTestPiPKiS1_j, .Lfunc_end1-_Z17segmentedScanTestPiPKiS1_j
.cfi_endproc
# -- End function
.section .text._Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,"axG",@progbits,_Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,comdat
.weak _Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi # -- Begin function _Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.p2align 4, 0x90
.type _Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,@function
_Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi: # @_Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, .Lfunc_end2-_Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "addWithCuda failed!"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%4d"
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "compared... not ok"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipDeviceReset failed!"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.5, 64
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMalloc failed!"
.size .L.str.6, 18
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy failed!"
.size .L.str.7, 18
.type _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,@object # @_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.section .rodata._Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,"aG",@progbits,_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi,comdat
.weak _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.p2align 3, 0x0
_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi:
.quad _Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.size _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz " launch failed: %s\n"
.size .L.str.8, 20
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.9, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20segscan_block_kernelIi5AddOpIiEEvPKT_PS2_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <cuda_runtime.h>
//TODO: BIG INT is needed
__global__ void decyrption(int *M, int *C, int *d, int *N){
int i = threadIdx.x;
M[i] = pow(M[i], d[i]);
M[i] = M[i] % N[i];
}
int main(){
int C[4] = {541, 795, 1479, 2753};
int M[4];
int d[4] = {1019, 1019, 1019, 1019};
int N[4] = {3337, 3337, 3337, 3337};
int *C_GPU, *M_GPU, *d_GPU, *N_GPU;
int size = 4 * sizeof(int);
cudaMalloc((void **)&C_GPU, size);
cudaMalloc((void **)&M_GPU, size);
cudaMalloc((void **)&d_GPU, size);
cudaMalloc((void **)&N_GPU, size);
cudaMemcpy(C_GPU, C, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_GPU, d, size, cudaMemcpyHostToDevice);
cudaMemcpy(N_GPU, N, size, cudaMemcpyHostToDevice);
decyrption<<<1, 4>>>(M_GPU, C_GPU, d_GPU, N_GPU);
cudaMemcpy(M, M_GPU, size, cudaMemcpyDeviceToHost);
cudaFree(M_GPU);
cudaFree(C_GPU);
cudaFree(d_GPU);
cudaFree(N_GPU);
int i;
for (i = 0; i < 4; i++){
printf("The result is %d, %d\n", M[i], C[i]);
}
} | code for sm_80
Function : _Z10decyrptionPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R10, R2, R5, c[0x0][0x170] ; /* 0x00005c00020a7625 */
/* 0x001fca00078e0205 */
/*0050*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R26, [R4.64] ; /* 0x00000004041a7981 */
/* 0x000ee2000c1e1900 */
/*0080*/ BSSY B0, 0x140 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0090*/ I2F.F64 R6, R3 ; /* 0x0000000300067312 */
/* 0x004e240000201c00 */
/*00a0*/ LOP3.LUT R0, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007007812 */
/* 0x001fc800078ec0ff */
/*00b0*/ LEA.HI R9, R0, 0xfffffc0c, RZ, 0xc ; /* 0xfffffc0c00097811 */
/* 0x000fe400078f60ff */
/*00c0*/ MOV R0, 0x130 ; /* 0x0000013000007802 */
/* 0x000fe40000000f00 */
/*00d0*/ SHF.L.U32 R27, R6.reuse, R9.reuse, RZ ; /* 0x00000009061b7219 */
/* 0x0c0fe400000006ff */
/*00e0*/ SHF.L.U64.HI R28, R6, R9, R7 ; /* 0x00000009061c7219 */
/* 0x000fe40000010207 */
/*00f0*/ I2F.F64 R8, R26 ; /* 0x0000001a00087312 */
/* 0x0080620000201c00 */
/*0100*/ ISETP.NE.U32.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fc80003f05070 */
/*0110*/ ISETP.NE.AND.EX P0, PT, R28, -0x80000000, PT, P0 ; /* 0x800000001c00780c */
/* 0x000fd00003f05300 */
/*0120*/ CALL.REL.NOINC 0x700 ; /* 0x000005d000007944 */
/* 0x003fea0003c00000 */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.OR P0, PT, R9, -0x1, P0 ; /* 0xffffffff0900780c */
/* 0x000fe20000704670 */
/*0150*/ IMAD.MOV.U32 R11, RZ, RZ, R15 ; /* 0x000000ffff0b7224 */
/* 0x002fe200078e000f */
/*0160*/ ISETP.NE.AND P1, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f25270 */
/*0170*/ BSSY B0, 0x2e0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0180*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fd200078e000e */
/*0190*/ @!P0 LOP3.LUT R13, R11, 0x80000000, RZ, 0x3c, !PT ; /* 0x800000000b0d8812 */
/* 0x001fca00078e3cff */
/*01a0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b8224 */
/* 0x000fe200078e000d */
/*01b0*/ @!P1 BRA 0x260 ; /* 0x000000a000009947 */
/* 0x000fea0003800000 */
/*01c0*/ FRND.F64.TRUNC R12, R6 ; /* 0x00000006000c7313 */
/* 0x000e22000030d800 */
/*01d0*/ ISETP.NE.U32.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fc80003f05070 */
/*01e0*/ ISETP.NE.AND.EX P0, PT, R28, -0x80000000, PT, P0 ; /* 0x800000001c00780c */
/* 0x000fc80003f05300 */
/*01f0*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe2000070e170 */
/*0200*/ DSETP.NEU.AND P1, PT, R12, R6, PT ; /* 0x000000060c00722a */
/* 0x001e0c0003f2d000 */
/*0210*/ ISETP.GT.OR P1, PT, R9, -0x1, !P1 ; /* 0xffffffff0900780c */
/* 0x001fda0004f24670 */
/*0220*/ @P1 BRA 0x2d0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0240*/ IMAD.MOV.U32 R11, RZ, RZ, -0x80000 ; /* 0xfff80000ff0b7424 */
/* 0x000fe200078e00ff */
/*0250*/ BRA 0x2d0 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*0260*/ DSETP.NEU.AND P0, PT, |R6|, 0.5, PT ; /* 0x3fe000000600742a */
/* 0x000e220003f0d200 */
/*0270*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f26270 */
/*0280*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0290*/ ISETP.EQ.U32.AND P2, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fc80003f42070 */
/*02a0*/ ISETP.EQ.AND.EX P0, PT, R28, -0x80000000, P0, P2 ; /* 0x800000001c00780c */
/* 0x001fc80000702320 */
/*02b0*/ SEL R11, R9, RZ, P0 ; /* 0x000000ff090b7207 */
/* 0x000fc80000000000 */
/*02c0*/ @!P1 LOP3.LUT R11, R11, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000b0b9812 */
/* 0x000fe400078efcff */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ DADD R12, R8, R6 ; /* 0x00000000080c7229 */
/* 0x000e220000000006 */
/*02f0*/ BSSY B0, 0x4f0 ; /* 0x000001f000007945 */
/* 0x000ff20003800000 */
/*0300*/ LOP3.LUT R12, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d0c7812 */
/* 0x001fc800078ec0ff */
/*0310*/ ISETP.NE.AND P1, PT, R12, 0x7ff00000, PT ; /* 0x7ff000000c00780c */
/* 0x000fda0003f25270 */
/*0320*/ @P1 BRA 0x4e0 ; /* 0x000001b000001947 */
/* 0x000fea0003800000 */
/*0330*/ DSETP.GTU.AND P1, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e0c0003f2c200 */
/*0340*/ DSETP.GTU.OR P1, PT, |R8|, +INF , P1 ; /* 0x7ff000000800742a */
/* 0x001e1c0000f2c600 */
/*0350*/ @P1 BRA 0x4d0 ; /* 0x0000017000001947 */
/* 0x001fea0003800000 */
/*0360*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*0370*/ LOP3.LUT R0, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07007812 */
/* 0x000fc800078ec0ff */
/*0380*/ ISETP.EQ.AND P1, PT, R0, 0x7ff00000, !P1 ; /* 0x7ff000000000780c */
/* 0x000fda0004f22270 */
/*0390*/ @!P1 BRA 0x420 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f26270 */
/*03b0*/ DSETP.GT.AND P0, PT, |R8|, 1, PT ; /* 0x3ff000000800742a */
/* 0x000e220003f04200 */
/*03c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e00ff */
/*03d0*/ SEL R0, RZ, 0x7ff00000, !P0 ; /* 0x7ff00000ff007807 */
/* 0x001fe40004000000 */
/*03e0*/ ISETP.NE.AND P0, PT, R26, -0x1, PT ; /* 0xffffffff1a00780c */
/* 0x000fc80003f05270 */
/*03f0*/ @!P1 LOP3.LUT R0, R0, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000000009812 */
/* 0x000fc800078e3cff */
/*0400*/ SEL R11, R0, 0x3ff00000, P0 ; /* 0x3ff00000000b7807 */
/* 0x000fe20000000000 */
/*0410*/ BRA 0x4e0 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0420*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0430*/ LOP3.LUT R12, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff090c7812 */
/* 0x000fc800078ec0ff */
/*0440*/ ISETP.NE.OR P1, PT, R12, 0x7ff00000, P1 ; /* 0x7ff000000c00780c */
/* 0x000fda0000f25670 */
/*0450*/ @P1 BRA 0x4e0 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0460*/ ISETP.LT.AND P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20000701270 */
/*0470*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0480*/ ISETP.GT.AND P1, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x000fe40003f24270 */
/*0490*/ ISETP.NE.AND P0, PT, R0, 0x3fe00000, P0 ; /* 0x3fe000000000780c */
/* 0x000fe40000705270 */
/*04a0*/ SEL R11, RZ, 0x7ff00000, !P1 ; /* 0x7ff00000ff0b7807 */
/* 0x000fd60004800000 */
/*04b0*/ @P0 IADD3 R11, R11, -0x80000000, RZ ; /* 0x800000000b0b0810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ BRA 0x4e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*04d0*/ DADD R10, R8, R6 ; /* 0x00000000080a7229 */
/* 0x00004c0000000006 */
/*04e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04f0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*0500*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0510*/ ISETP.EQ.OR P0, PT, R26, 0x1, !P0 ; /* 0x000000011a00780c */
/* 0x000fe20004702670 */
/*0520*/ IMAD.WIDE R2, R2, R3, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fc600078e0203 */
/*0530*/ FSEL R7, R11, 1.875, !P0 ; /* 0x3ff000000b077808 */
/* 0x003fe40004000000 */
/*0540*/ FSEL R6, R10, RZ, !P0 ; /* 0x000000ff0a067208 */
/* 0x000fc80004000000 */
/*0550*/ F2I.F64.TRUNC R7, R6 ; /* 0x0000000600077311 */
/* 0x000e24000030d100 */
/*0560*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe8000c101904 */
/*0570*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IABS R6, R7 ; /* 0x0000000700067213 */
/* 0x000fe40000000000 */
/*0590*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f46270 */
/*05a0*/ IABS R10, R2 ; /* 0x00000002000a7213 */
/* 0x004fc40000000000 */
/*05b0*/ IABS R3, R2 ; /* 0x0000000200037213 */
/* 0x000fe40000000000 */
/*05c0*/ I2F.RP R0, R10 ; /* 0x0000000a00007306 */
/* 0x000e300000209400 */
/*05d0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*05e0*/ IADD3 R8, R0, 0xffffffe, RZ ; /* 0x0ffffffe00087810 */
/* 0x001fe20007ffe0ff */
/*05f0*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fca00078e0a03 */
/*0600*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0610*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0620*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a09 */
/*0630*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*0640*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fcc00078e0008 */
/*0650*/ IMAD.HI.U32 R9, R9, R6, RZ ; /* 0x0000000609097227 */
/* 0x000fc800078e00ff */
/*0660*/ IMAD R9, R9, R0, R6 ; /* 0x0000000009097224 */
/* 0x000fca00078e0206 */
/*0670*/ ISETP.GT.U32.AND P0, PT, R10, R9, PT ; /* 0x000000090a00720c */
/* 0x000fda0003f04070 */
/*0680*/ @!P0 IMAD.IADD R9, R9, 0x1, -R10 ; /* 0x0000000109098824 */
/* 0x000fe200078e0a0a */
/*0690*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc80003f05270 */
/*06a0*/ ISETP.GT.U32.AND P1, PT, R10, R9, PT ; /* 0x000000090a00720c */
/* 0x000fda0003f24070 */
/*06b0*/ @!P1 IMAD.IADD R9, R9, 0x1, -R10 ; /* 0x0000000109099824 */
/* 0x000fc800078e0a0a */
/*06c0*/ @!P2 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09a224 */
/* 0x000fe200078e0a09 */
/*06d0*/ @!P0 LOP3.LUT R9, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff098212 */
/* 0x000fca00078e33ff */
/*06e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*06f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0700*/ DADD R10, -RZ, |R8| ; /* 0x00000000ff0a7229 */
/* 0x000e220000000508 */
/*0710*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd200078e00ff */
/*0720*/ SHF.R.U32.HI R29, RZ, 0x14, R11 ; /* 0x00000014ff1d7819 */
/* 0x001fc8000001160b */
/*0730*/ ISETP.NE.AND P1, PT, R29, RZ, PT ; /* 0x000000ff1d00720c */
/* 0x000fda0003f25270 */
/*0740*/ @!P1 DMUL R20, R10, 1.80143985094819840000e+16 ; /* 0x435000000a149828 */
/* 0x000e140000000000 */
/*0750*/ @!P1 IMAD.MOV.U32 R11, RZ, RZ, R21 ; /* 0x000000ffff0b9224 */
/* 0x001fe200078e0015 */
/*0760*/ @!P1 LEA.HI R29, R21, 0xffffffca, RZ, 0xc ; /* 0xffffffca151d9811 */
/* 0x000fe200078f60ff */
/*0770*/ @!P1 IMAD.MOV.U32 R10, RZ, RZ, R20 ; /* 0x000000ffff0a9224 */
/* 0x000fc600078e0014 */
/*0780*/ LOP3.LUT R11, R11, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fe200078ec0ff */
/*0790*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fc600078e000a */
/*07a0*/ LOP3.LUT R17, R11, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000b117812 */
/* 0x000fc800078efcff */
/*07b0*/ ISETP.GE.U32.AND P2, PT, R17, 0x3ff6a09f, PT ; /* 0x3ff6a09f1100780c */
/* 0x000fda0003f46070 */
/*07c0*/ @P2 IADD3 R11, R17, -0x100000, RZ ; /* 0xfff00000110b2810 */
/* 0x000fca0007ffe0ff */
/*07d0*/ @P2 IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff112224 */
/* 0x000fcc00078e000b */
/*07e0*/ DADD R18, R16, 1 ; /* 0x3ff0000010127429 */
/* 0x000e080000000000 */
/*07f0*/ DADD R16, R16, -1 ; /* 0xbff0000010107429 */
/* 0x000fe40000000000 */
/*0800*/ MUFU.RCP64H R15, R19 ; /* 0x00000013000f7308 */
/* 0x001e240000001800 */
/*0810*/ DFMA R10, -R18, R14, 1 ; /* 0x3ff00000120a742b */
/* 0x001e0c000000010e */
/*0820*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0830*/ DFMA R14, R14, R10, R14 ; /* 0x0000000a0e0e722b */
/* 0x001e0c000000000e */
/*0840*/ DMUL R10, R14, R16 ; /* 0x000000100e0a7228 */
/* 0x001e0c0000000000 */
/*0850*/ DFMA R10, R14, R16, R10 ; /* 0x000000100e0a722b */
/* 0x001e0c000000000a */
/*0860*/ DADD R12, R16, -R10 ; /* 0x00000000100c7229 */
/* 0x001e08000000080a */
/*0870*/ DMUL R22, R10, R10 ; /* 0x0000000a0a167228 */
/* 0x000fc80000000000 */
/*0880*/ DADD R12, R12, R12 ; /* 0x000000000c0c7229 */
/* 0x001e0c000000000c */
/*0890*/ DFMA R12, R16, -R10, R12 ; /* 0x8000000a100c722b */
/* 0x001064000000000c */
/*08a0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff107424 */
/* 0x001fe400078e00ff */
/*08b0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff117424 */
/* 0x000fe400078e00ff */
/*08c0*/ DMUL R12, R14, R12 ; /* 0x0000000c0e0c7228 */
/* 0x002fc80000000000 */
/*08d0*/ DFMA R16, R22, R16, c[0x2][0x0] ; /* 0x008000001610762b */
/* 0x000e0c0000000010 */
/*08e0*/ DFMA R18, R22, R16, c[0x2][0x8] ; /* 0x008002001612762b */
/* 0x001e220000000010 */
/*08f0*/ IADD3 R21, R13, 0x100000, RZ ; /* 0x001000000d157810 */
/* 0x000fe20007ffe0ff */
/*0900*/ IMAD.MOV.U32 R20, RZ, RZ, R12 ; /* 0x000000ffff147224 */
/* 0x000fc800078e000c */
/*0910*/ DFMA R18, R22, R18, c[0x2][0x10] ; /* 0x008004001612762b */
/* 0x001e0c0000000012 */
/*0920*/ DFMA R18, R22, R18, c[0x2][0x18] ; /* 0x008006001612762b */
/* 0x001e0c0000000012 */
/*0930*/ DFMA R18, R22, R18, c[0x2][0x20] ; /* 0x008008001612762b */
/* 0x001e0c0000000012 */
/*0940*/ DFMA R18, R22, R18, c[0x2][0x28] ; /* 0x00800a001612762b */
/* 0x001e0c0000000012 */
/*0950*/ DFMA R14, R22, R18, c[0x2][0x30] ; /* 0x00800c00160e762b */
/* 0x001e0c0000000012 */
/*0960*/ DADD R16, -R14, c[0x2][0x30] ; /* 0x00800c000e107629 */
/* 0x001e0c0000000100 */
/*0970*/ DFMA R16, R22, R18, R16 ; /* 0x000000121610722b */
/* 0x001e080000000010 */
/*0980*/ DMUL R18, R10, R10 ; /* 0x0000000a0a127228 */
/* 0x000e480000000000 */
/*0990*/ DADD R16, RZ, R16 ; /* 0x00000000ff107229 */
/* 0x001fc80000000010 */
/*09a0*/ DFMA R22, R10, R10, -R18 ; /* 0x0000000a0a16722b */
/* 0x002e0c0000000812 */
/*09b0*/ DFMA R20, R10, R20, R22 ; /* 0x000000140a14722b */
/* 0x001fc80000000016 */
/*09c0*/ DMUL R22, R10, R18 ; /* 0x000000120a167228 */
/* 0x000e0c0000000000 */
/*09d0*/ DFMA R24, R10, R18, -R22 ; /* 0x000000120a18722b */
/* 0x001e0c0000000816 */
/*09e0*/ DFMA R24, R12, R18, R24 ; /* 0x000000120c18722b */
/* 0x001e0c0000000018 */
/*09f0*/ DFMA R20, R10, R20, R24 ; /* 0x000000140a14722b */
/* 0x001fc80000000018 */
/*0a00*/ DADD R24, R16, c[0x2][0x38] ; /* 0x00800e0010187629 */
/* 0x000e0c0000000000 */
/*0a10*/ DADD R16, R14, R24 ; /* 0x000000000e107229 */
/* 0x001e0c0000000018 */
/*0a20*/ DADD R14, R14, -R16 ; /* 0x000000000e0e7229 */
/* 0x001e080000000810 */
/*0a30*/ DMUL R18, R16, R22 ; /* 0x0000001610127228 */
/* 0x000e480000000000 */
/*0a40*/ DADD R24, R24, R14 ; /* 0x0000000018187229 */
/* 0x001fc8000000000e */
/*0a50*/ DFMA R14, R16, R22, -R18 ; /* 0x00000016100e722b */
/* 0x002e0c0000000812 */
/*0a60*/ DFMA R14, R16, R20, R14 ; /* 0x00000014100e722b */
/* 0x001e0c000000000e */
/*0a70*/ DFMA R24, R24, R22, R14 ; /* 0x000000161818722b */
/* 0x001e0c000000000e */
/*0a80*/ DADD R16, R18, R24 ; /* 0x0000000012107229 */
/* 0x001e0c0000000018 */
/*0a90*/ DADD R14, R10, R16 ; /* 0x000000000a0e7229 */
/* 0x001e080000000010 */
/*0aa0*/ DADD R18, R18, -R16 ; /* 0x0000000012127229 */
/* 0x000e480000000810 */
/*0ab0*/ DADD R10, R10, -R14 ; /* 0x000000000a0a7229 */
/* 0x001e08000000080e */
/*0ac0*/ DADD R18, R24, R18 ; /* 0x0000000018127229 */
/* 0x002fc80000000012 */
/*0ad0*/ DADD R10, R16, R10 ; /* 0x00000000100a7229 */
/* 0x001064000000000a */
/*0ae0*/ IADD3 R16, R29.reuse, -0x3ff, RZ ; /* 0xfffffc011d107810 */
/* 0x041fe40007ffe0ff */
/*0af0*/ @P2 IADD3 R16, R29, -0x3fe, RZ ; /* 0xfffffc021d102810 */
/* 0x000fe40007ffe0ff */
/*0b00*/ DADD R18, R18, R10 ; /* 0x0000000012127229 */
/* 0x002064000000000a */
/*0b10*/ LOP3.LUT R10, R16, 0x80000000, RZ, 0x3c, !PT ; /* 0x80000000100a7812 */
/* 0x001fe200078e3cff */
/*0b20*/ IMAD.MOV.U32 R11, RZ, RZ, 0x43300000 ; /* 0x43300000ff0b7424 */
/* 0x000fc600078e00ff */
/*0b30*/ DADD R18, R12, R18 ; /* 0x000000000c127229 */
/* 0x002e080000000012 */
/*0b40*/ DADD R12, R10, c[0x2][0x40] ; /* 0x008010000a0c7629 */
/* 0x000fc80000000000 */
/*0b50*/ DADD R16, R14, R18 ; /* 0x000000000e107229 */
/* 0x001e0c0000000012 */
/*0b60*/ DFMA R10, R12, c[0x2][0x48], R16 ; /* 0x008012000c0a7a2b */
/* 0x001e080000000010 */
/*0b70*/ DADD R20, R14, -R16 ; /* 0x000000000e147229 */
/* 0x000e480000000810 */
/*0b80*/ DFMA R14, -R12, c[0x2][0x48], R10 ; /* 0x008012000c0e7a2b */
/* 0x001e08000000010a */
/*0b90*/ DADD R20, R18, R20 ; /* 0x0000000012147229 */
/* 0x0023e40000000014 */
/*0ba0*/ IMAD.SHL.U32 R18, R7, 0x2, RZ ; /* 0x0000000207127824 */
/* 0x002fe400078e00ff */
/*0bb0*/ DADD R14, -R16, R14 ; /* 0x00000000100e7229 */
/* 0x001e22000000010e */
/*0bc0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff137424 */
/* 0x000fe400078e00ff */
/*0bd0*/ ISETP.GT.U32.AND P1, PT, R18, -0x2000001, PT ; /* 0xfdffffff1200780c */
/* 0x000fe20003f24070 */
/*0be0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x652b82fe ; /* 0x652b82feff127424 */
/* 0x000fe400078e00ff */
/*0bf0*/ DADD R14, R20, -R14 ; /* 0x00000000140e7229 */
/* 0x001e0c000000080e */
/*0c00*/ DFMA R16, R12, c[0x2][0x50], R14 ; /* 0x008014000c107a2b */
/* 0x001064000000000e */
/*0c10*/ LOP3.LUT R13, R7, 0xff0fffff, RZ, 0xc0, !PT ; /* 0xff0fffff070d7812 */
/* 0x001fe200078ec0ff */
/*0c20*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e0006 */
/*0c30*/ DADD R14, R10, R16 ; /* 0x000000000a0e7229 */
/* 0x002e220000000010 */
/*0c40*/ SEL R13, R13, R7, P1 ; /* 0x000000070d0d7207 */
/* 0x000fca0000800000 */
/*0c50*/ DADD R10, R10, -R14 ; /* 0x000000000a0a7229 */
/* 0x001e08000000080e */
/*0c60*/ DMUL R20, R14, R12 ; /* 0x0000000c0e147228 */
/* 0x000e480000000000 */
/*0c70*/ DADD R10, R16, R10 ; /* 0x00000000100a7229 */
/* 0x001fc8000000000a */
/*0c80*/ DFMA R14, R14, R12, -R20 ; /* 0x0000000c0e0e722b */
/* 0x002e0c0000000814 */
/*0c90*/ DFMA R10, R10, R12, R14 ; /* 0x0000000c0a0a722b */
/* 0x001e0c000000000e */
/*0ca0*/ DADD R12, R20, R10 ; /* 0x00000000140c7229 */
/* 0x001e0c000000000a */
/*0cb0*/ DFMA R18, R12, R18, 6.75539944105574400000e+15 ; /* 0x433800000c12742b */
/* 0x001e080000000012 */
/*0cc0*/ FSETP.GEU.AND P1, PT, |R13|, 4.1917929649353027344, PT ; /* 0x4086232b0d00780b */
/* 0x000fe40003f2e200 */
/*0cd0*/ DADD R14, R18, -6.75539944105574400000e+15 ; /* 0xc3380000120e7429 */
/* 0x001e0c0000000000 */
/*0ce0*/ DFMA R16, R14, c[0x2][0x58], R12 ; /* 0x008016000e107a2b */
/* 0x001e0c000000000c */
/*0cf0*/ DFMA R16, R14, c[0x2][0x60], R16 ; /* 0x008018000e107a2b */
/* 0x0010640000000010 */
/*0d00*/ IMAD.MOV.U32 R14, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff0e7424 */
/* 0x001fe400078e00ff */
/*0d10*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff0f7424 */
/* 0x000fcc00078e00ff */
/*0d20*/ DFMA R14, R16, R14, c[0x2][0x68] ; /* 0x00801a00100e762b */
/* 0x002e0c000000000e */
/*0d30*/ DFMA R14, R16, R14, c[0x2][0x70] ; /* 0x00801c00100e762b */
/* 0x001e0c000000000e */
/*0d40*/ DFMA R14, R16, R14, c[0x2][0x78] ; /* 0x00801e00100e762b */
/* 0x001e0c000000000e */
/*0d50*/ DFMA R14, R16, R14, c[0x2][0x80] ; /* 0x00802000100e762b */
/* 0x001e0c000000000e */
/*0d60*/ DFMA R14, R16, R14, c[0x2][0x88] ; /* 0x00802200100e762b */
/* 0x001e0c000000000e */
/*0d70*/ DFMA R14, R16, R14, c[0x2][0x90] ; /* 0x00802400100e762b */
/* 0x001e0c000000000e */
/*0d80*/ DFMA R14, R16, R14, c[0x2][0x98] ; /* 0x00802600100e762b */
/* 0x001e0c000000000e */
/*0d90*/ DFMA R14, R16, R14, c[0x2][0xa0] ; /* 0x00802800100e762b */
/* 0x001e0c000000000e */
/*0da0*/ DFMA R14, R16, R14, c[0x2][0xa8] ; /* 0x00802a00100e762b */
/* 0x001e0c000000000e */
/*0db0*/ DFMA R14, R16, R14, 1 ; /* 0x3ff00000100e742b */
/* 0x001e0c000000000e */
/*0dc0*/ DFMA R16, R16, R14, 1 ; /* 0x3ff000001010742b */
/* 0x001e14000000000e */
/*0dd0*/ IMAD R15, R18, 0x100000, R17 ; /* 0x00100000120f7824 */
/* 0x001fe400078e0211 */
/*0de0*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0010 */
/*0df0*/ @!P1 BRA 0xec0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0e00*/ FSETP.GEU.AND P2, PT, |R13|, 4.2275390625, PT ; /* 0x408748000d00780b */
/* 0x000fe20003f4e200 */
/*0e10*/ DADD R14, R12, +INF ; /* 0x7ff000000c0e7429 */
/* 0x000fc80000000000 */
/*0e20*/ DSETP.GEU.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00722a */
/* 0x000e0c0003f2e000 */
/*0e30*/ FSEL R14, R14, RZ, P1 ; /* 0x000000ff0e0e7208 */
/* 0x001fe40000800000 */
/*0e40*/ @!P2 LEA.HI R19, R18, R18, RZ, 0x1 ; /* 0x000000121213a211 */
/* 0x000fe400078f08ff */
/*0e50*/ FSEL R15, R15, RZ, P1 ; /* 0x000000ff0f0f7208 */
/* 0x000fe40000800000 */
/*0e60*/ @!P2 SHF.R.S32.HI R19, RZ, 0x1, R19 ; /* 0x00000001ff13a819 */
/* 0x000fca0000011413 */
/*0e70*/ @!P2 IMAD.IADD R18, R18, 0x1, -R19 ; /* 0x000000011212a824 */
/* 0x000fe400078e0a13 */
/*0e80*/ @!P2 IMAD R17, R19, 0x100000, R17 ; /* 0x001000001311a824 */
/* 0x000fc600078e0211 */
/*0e90*/ @!P2 LEA R19, R18, 0x3ff00000, 0x14 ; /* 0x3ff000001213a811 */
/* 0x000fe200078ea0ff */
/*0ea0*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12a224 */
/* 0x000fcc00078e00ff */
/*0eb0*/ @!P2 DMUL R14, R16, R18 ; /* 0x00000012100ea228 */
/* 0x0000540000000000 */
/*0ec0*/ LOP3.LUT R16, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0f107812 */
/* 0x003fe200078ec0ff */
/*0ed0*/ DADD R12, R20, -R12 ; /* 0x00000000140c7229 */
/* 0x000e06000000080c */
/*0ee0*/ ISETP.NE.AND P1, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fc60003f25270 */
/*0ef0*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x001062000000000c */
/*0f00*/ ISETP.EQ.AND P1, PT, R14, RZ, !P1 ; /* 0x000000ff0e00720c */
/* 0x000fe20004f22270 */
/*0f10*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0000 */
/*0f20*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fd400078e00ff */
/*0f30*/ @!P1 DFMA R14, R12, R14, R14 ; /* 0x0000000e0c0e922b */
/* 0x002062000000000e */
/*0f40*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff0b00a007950 */
/* 0x000ff40003c3ffff */
/*0f50*/ BRA 0xf50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <cuda_runtime.h>
//TODO: BIG INT is needed
__global__ void decyrption(int *M, int *C, int *d, int *N){
int i = threadIdx.x;
M[i] = pow(M[i], d[i]);
M[i] = M[i] % N[i];
}
int main(){
int C[4] = {541, 795, 1479, 2753};
int M[4];
int d[4] = {1019, 1019, 1019, 1019};
int N[4] = {3337, 3337, 3337, 3337};
int *C_GPU, *M_GPU, *d_GPU, *N_GPU;
int size = 4 * sizeof(int);
cudaMalloc((void **)&C_GPU, size);
cudaMalloc((void **)&M_GPU, size);
cudaMalloc((void **)&d_GPU, size);
cudaMalloc((void **)&N_GPU, size);
cudaMemcpy(C_GPU, C, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_GPU, d, size, cudaMemcpyHostToDevice);
cudaMemcpy(N_GPU, N, size, cudaMemcpyHostToDevice);
decyrption<<<1, 4>>>(M_GPU, C_GPU, d_GPU, N_GPU);
cudaMemcpy(M, M_GPU, size, cudaMemcpyDeviceToHost);
cudaFree(M_GPU);
cudaFree(C_GPU);
cudaFree(d_GPU);
cudaFree(N_GPU);
int i;
for (i = 0; i < 4; i++){
printf("The result is %d, %d\n", M[i], C[i]);
}
} | .file "tmpxft_001b3906_00000000-6_decryption.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_
.type _Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_, @function
_Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10decyrptionPiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_, .-_Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_
.globl _Z10decyrptionPiS_S_S_
.type _Z10decyrptionPiS_S_S_, @function
_Z10decyrptionPiS_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10decyrptionPiS_S_S_, .-_Z10decyrptionPiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "The result is %d, %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $541, 64(%rsp)
movl $795, 68(%rsp)
movl $1479, 72(%rsp)
movl $2753, 76(%rsp)
movl $1019, 96(%rsp)
movl $1019, 100(%rsp)
movl $1019, 104(%rsp)
movl $1019, 108(%rsp)
movl $3337, 112(%rsp)
movl $3337, 116(%rsp)
movl $3337, 120(%rsp)
movl $3337, 124(%rsp)
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L13:
movl 64(%rsp,%rbx), %ecx
movl 80(%rsp,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $16, %rbx
jne .L13
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10decyrptionPiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10decyrptionPiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <cuda_runtime.h>
//TODO: BIG INT is needed
__global__ void decyrption(int *M, int *C, int *d, int *N){
int i = threadIdx.x;
M[i] = pow(M[i], d[i]);
M[i] = M[i] % N[i];
}
int main(){
int C[4] = {541, 795, 1479, 2753};
int M[4];
int d[4] = {1019, 1019, 1019, 1019};
int N[4] = {3337, 3337, 3337, 3337};
int *C_GPU, *M_GPU, *d_GPU, *N_GPU;
int size = 4 * sizeof(int);
cudaMalloc((void **)&C_GPU, size);
cudaMalloc((void **)&M_GPU, size);
cudaMalloc((void **)&d_GPU, size);
cudaMalloc((void **)&N_GPU, size);
cudaMemcpy(C_GPU, C, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_GPU, d, size, cudaMemcpyHostToDevice);
cudaMemcpy(N_GPU, N, size, cudaMemcpyHostToDevice);
decyrption<<<1, 4>>>(M_GPU, C_GPU, d_GPU, N_GPU);
cudaMemcpy(M, M_GPU, size, cudaMemcpyDeviceToHost);
cudaFree(M_GPU);
cudaFree(C_GPU);
cudaFree(d_GPU);
cudaFree(N_GPU);
int i;
for (i = 0; i < 4; i++){
printf("The result is %d, %d\n", M[i], C[i]);
}
} | #include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
//TODO: BIG INT is needed
__global__ void decyrption(int *M, int *C, int *d, int *N){
int i = threadIdx.x;
M[i] = pow(M[i], d[i]);
M[i] = M[i] % N[i];
}
int main(){
int C[4] = {541, 795, 1479, 2753};
int M[4];
int d[4] = {1019, 1019, 1019, 1019};
int N[4] = {3337, 3337, 3337, 3337};
int *C_GPU, *M_GPU, *d_GPU, *N_GPU;
int size = 4 * sizeof(int);
hipMalloc((void **)&C_GPU, size);
hipMalloc((void **)&M_GPU, size);
hipMalloc((void **)&d_GPU, size);
hipMalloc((void **)&N_GPU, size);
hipMemcpy(C_GPU, C, size, hipMemcpyHostToDevice);
hipMemcpy(d_GPU, d, size, hipMemcpyHostToDevice);
hipMemcpy(N_GPU, N, size, hipMemcpyHostToDevice);
decyrption<<<1, 4>>>(M_GPU, C_GPU, d_GPU, N_GPU);
hipMemcpy(M, M_GPU, size, hipMemcpyDeviceToHost);
hipFree(M_GPU);
hipFree(C_GPU);
hipFree(d_GPU);
hipFree(N_GPU);
int i;
for (i = 0; i < 4; i++){
printf("The result is %d, %d\n", M[i], C[i]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
//TODO: BIG INT is needed
__global__ void decyrption(int *M, int *C, int *d, int *N){
int i = threadIdx.x;
M[i] = pow(M[i], d[i]);
M[i] = M[i] % N[i];
}
int main(){
int C[4] = {541, 795, 1479, 2753};
int M[4];
int d[4] = {1019, 1019, 1019, 1019};
int N[4] = {3337, 3337, 3337, 3337};
int *C_GPU, *M_GPU, *d_GPU, *N_GPU;
int size = 4 * sizeof(int);
hipMalloc((void **)&C_GPU, size);
hipMalloc((void **)&M_GPU, size);
hipMalloc((void **)&d_GPU, size);
hipMalloc((void **)&N_GPU, size);
hipMemcpy(C_GPU, C, size, hipMemcpyHostToDevice);
hipMemcpy(d_GPU, d, size, hipMemcpyHostToDevice);
hipMemcpy(N_GPU, N, size, hipMemcpyHostToDevice);
decyrption<<<1, 4>>>(M_GPU, C_GPU, d_GPU, N_GPU);
hipMemcpy(M, M_GPU, size, hipMemcpyDeviceToHost);
hipFree(M_GPU);
hipFree(C_GPU);
hipFree(d_GPU);
hipFree(N_GPU);
int i;
for (i = 0; i < 4; i++){
printf("The result is %d, %d\n", M[i], C[i]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10decyrptionPiS_S_S_
.globl _Z10decyrptionPiS_S_S_
.p2align 8
.type _Z10decyrptionPiS_S_S_,@function
_Z10decyrptionPiS_S_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_mov_b32 s1, 0x3fe55555
s_mov_b32 s0, 0x55555555
s_mov_b32 s9, 0x3fbdee67
s_mov_b32 s8, 0x4222de17
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v3, v0, s[2:3]
s_mov_b32 s5, 0x3fba6564
s_mov_b32 s4, 0x968915a9
s_waitcnt vmcnt(1)
v_cvt_f64_i32_e32 v[1:2], v1
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 1, v3
v_cvt_f64_i32_e32 v[3:4], v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v2, 0x3ff00000, v2, vcc_lo
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_neq_f64_e32 vcc_lo, 0, v[1:2]
v_cndmask_b32_e32 v4, 0x3ff00000, v4, vcc_lo
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e64 v[5:6], |v[3:4]|
v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[5:6]
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[5:6], v[5:6], v7
v_add_f64 v[7:8], v[5:6], 1.0
v_add_f64 v[13:14], v[5:6], -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[9:10], v[7:8]
v_add_f64 v[15:16], v[7:8], -1.0
v_add_f64 v[5:6], v[5:6], -v[15:16]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
v_mul_f64 v[11:12], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[7:8], v[11:12]
v_fma_f64 v[7:8], v[11:12], v[7:8], -v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[11:12], v[5:6], v[7:8]
v_add_f64 v[7:8], v[17:18], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[15:16], v[13:14], -v[7:8]
v_add_f64 v[17:18], v[7:8], -v[17:18]
v_add_f64 v[13:14], v[13:14], -v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[17:18], -v[5:6]
v_add_f64 v[7:8], v[13:14], -v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_add_f64 v[5:6], v[15:16], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[5:6], v[9:10], v[5:6]
v_add_f64 v[7:8], v[11:12], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[7:8], -v[11:12]
v_mul_f64 v[11:12], v[7:8], v[7:8]
v_add_f64 v[5:6], v[5:6], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[9:10], v[7:8], v[7:8], -v[11:12]
v_add_f64 v[13:14], v[5:6], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[7:8], v[13:14], v[9:10]
v_add_f64 v[13:14], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], s[8:9], s[4:5]
s_mov_b32 s5, 0x3fbe25e4
s_mov_b32 s4, 0x3abe935a
v_add_f64 v[11:12], v[13:14], -v[11:12]
v_mul_f64 v[21:22], v[7:8], v[13:14]
s_mov_b32 s9, 0x3ff71547
s_mov_b32 s8, 0x652b82fe
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
s_mov_b32 s5, 0x3fc110ef
s_mov_b32 s4, 0x47e6c9c2
v_add_f64 v[9:10], v[9:10], -v[11:12]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
s_mov_b32 s5, 0x3fc3b13b
s_mov_b32 s4, 0xcfa74449
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
s_mov_b32 s5, 0x3fc745d1
s_mov_b32 s4, 0x71bf3c30
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
s_mov_b32 s5, 0x3fcc71c7
s_mov_b32 s4, 0x1c7792ce
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
s_mov_b32 s5, 0x3fd24924
s_mov_b32 s4, 0x924920da
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
s_mov_b32 s5, 0x3fd99999
s_mov_b32 s4, 0x9999999c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[4:5]
s_mov_b32 s5, 0x3c7abc9e
s_mov_b32 s4, 0x3b39803f
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[13:14], v[15:16]
v_fma_f64 v[11:12], v[13:14], v[15:16], -v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[9:10], v[15:16], v[11:12]
v_add_f64 v[15:16], v[17:18], v[11:12]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[19:20], v[15:16], s[0:1]
v_add_f64 v[17:18], v[15:16], -v[17:18]
s_mov_b32 s1, 0xbfe55555
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_f64 v[23:24], v[19:20], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], -v[17:18]
v_fma_f64 v[17:18], v[13:14], v[7:8], -v[21:22]
s_mov_b32 s1, 0x3c8543b0
s_mov_b32 s0, 0xd5df274d
v_add_f64 v[15:16], v[15:16], -v[23:24]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], s[0:1]
v_fma_f64 v[13:14], v[13:14], v[5:6], v[17:18]
s_mov_b32 s1, 0x3fe62e42
s_mov_b32 s0, 0xfefa39ef
v_ldexp_f64 v[5:6], v[5:6], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], v[15:16]
v_fma_f64 v[9:10], v[9:10], v[7:8], v[13:14]
v_ldexp_f64 v[7:8], v[7:8], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[13:14], v[19:20], v[11:12]
v_add_f64 v[15:16], v[21:22], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[17:18], v[19:20], -v[13:14]
v_mul_f64 v[19:20], v[15:16], v[13:14]
v_add_f64 v[21:22], v[15:16], -v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], v[17:18]
v_fma_f64 v[17:18], v[15:16], v[13:14], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[9:10], -v[21:22]
v_fma_f64 v[11:12], v[15:16], v[11:12], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[9:10], v[9:10], v[13:14], v[11:12]
v_frexp_exp_i32_f64_e32 v13, v[3:4]
v_add_f64 v[11:12], v[19:20], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
v_cvt_f64_i32_e32 v[13:14], v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[15:16], v[7:8], v[11:12]
v_add_f64 v[17:18], v[11:12], -v[19:20]
v_mul_f64 v[19:20], v[13:14], s[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[15:16], -v[7:8]
v_add_f64 v[9:10], v[9:10], -v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[17:18], v[13:14], s[0:1], -v[19:20]
s_mov_b32 s1, 0xbfe62e42
v_add_f64 v[7:8], v[11:12], -v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[5:6], v[5:6], v[9:10]
v_fma_f64 v[9:10], v[13:14], s[4:5], v[17:18]
s_mov_b32 s5, 0xbc7abc9e
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_add_f64 v[7:8], v[19:20], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[15:16], v[5:6]
v_add_f64 v[19:20], v[7:8], -v[19:20]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[13:14], v[7:8], v[11:12]
v_add_f64 v[15:16], v[11:12], -v[15:16]
v_add_f64 v[9:10], v[9:10], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[17:18], v[13:14], -v[7:8]
v_add_f64 v[5:6], v[5:6], -v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[21:22], v[13:14], -v[17:18]
v_add_f64 v[11:12], v[11:12], -v[17:18]
v_add_f64 v[15:16], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], -v[21:22]
v_add_f64 v[7:8], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[15:16], -v[9:10]
v_add_f64 v[7:8], v[15:16], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[15:16], v[15:16], -v[11:12]
v_add_f64 v[5:6], v[5:6], -v[11:12]
v_add_f64 v[17:18], v[13:14], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[9:10], -v[15:16]
v_add_f64 v[11:12], v[17:18], -v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[9:10]
v_add_f64 v[7:8], v[7:8], -v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_add_f64 v[7:8], v[17:18], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[7:8], -v[17:18]
v_mul_f64 v[11:12], v[1:2], v[7:8]
v_add_f64 v[5:6], v[5:6], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[7:8], v[1:2], v[7:8], -v[11:12]
v_cmp_class_f64_e64 vcc_lo, v[11:12], 0x204
v_fma_f64 v[5:6], v[1:2], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[11:12], v[5:6]
v_dual_cndmask_b32 v10, v8, v12 :: v_dual_cndmask_b32 v9, v7, v11
v_add_f64 v[7:8], v[7:8], -v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[9:10]|
v_add_f64 v[5:6], v[5:6], -v[7:8]
v_mul_f64 v[7:8], v[1:2], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_mul_f64 v[13:14], v[9:10], s[8:9]
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[13:14], v[13:14]
v_fma_f64 v[15:16], v[13:14], s[0:1], v[9:10]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
v_cvt_i32_f64_e32 v19, v[13:14]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[15:16], v[13:14], s[4:5], v[15:16]
s_mov_b32 s5, 0x3e5ade15
s_mov_b32 s4, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], s[4:5], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
v_cmp_nlt_f64_e64 s0, 0x40900000, v[9:10]
v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[17:18], v[15:16], v[17:18], 1.0
s_and_b32 vcc_lo, s1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[15:16], v[17:18], 1.0
v_ldexp_f64 v[11:12], v[13:14], v19
v_trunc_f64_e32 v[13:14], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v12, 0x7ff00000, v12, s0
v_cndmask_b32_e32 v9, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v10, 0, v12, s1
v_trunc_f64_e32 v[11:12], v[7:8]
v_cmp_eq_f64_e64 s1, v[13:14], v[1:2]
v_fma_f64 v[5:6], v[9:10], v[5:6], v[9:10]
v_cmp_class_f64_e64 s0, v[9:10], 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_neq_f64_e32 vcc_lo, v[11:12], v[7:8]
v_cndmask_b32_e64 v5, v5, v9, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v6, v6, v10, s0
v_cmp_gt_f64_e64 s0, 0, v[3:4]
v_cndmask_b32_e64 v7, 0, v5, s1
s_and_b32 vcc_lo, s1, vcc_lo
v_cndmask_b32_e32 v8, 0x3ff00000, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v6, 0x7fffffff, v6, v8
v_cndmask_b32_e64 v8, 0x7ff80000, v6, s1
v_cmp_gt_f64_e64 s1, 0, v[1:2]
v_cndmask_b32_e64 v1, v5, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v2, v6, v8, s0
v_cmp_eq_f64_e64 s0, 0, v[3:4]
v_cndmask_b32_e32 v3, 0, v4, vcc_lo
s_xor_b32 s1, s1, s0
v_cndmask_b32_e64 v1, v1, 0, s0
v_cndmask_b32_e64 v4, 0x7ff00000, 0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v3, 0x7fffffff, v4, v3
v_cndmask_b32_e64 v2, v2, v3, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v1, v[1:2]
global_store_b32 v0, v1, s[2:3]
global_load_b32 v2, v0, s[6:7]
v_ashrrev_i32_e32 v5, 31, v1
v_add_nc_u32_e32 v1, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v5
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v3
v_cvt_f32_u32_e32 v3, v2
v_sub_nc_u32_e32 v4, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, v3
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_mul_hi_u32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, v2
v_sub_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v1, v2
v_cmp_ge_u32_e32 vcc_lo, v1, v2
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v1, v2
v_cmp_ge_u32_e32 vcc_lo, v1, v2
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v5
v_sub_nc_u32_e32 v1, v1, v5
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10decyrptionPiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10decyrptionPiS_S_S_, .Lfunc_end0-_Z10decyrptionPiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10decyrptionPiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z10decyrptionPiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
//TODO: BIG INT is needed
__global__ void decyrption(int *M, int *C, int *d, int *N){
int i = threadIdx.x;
M[i] = pow(M[i], d[i]);
M[i] = M[i] % N[i];
}
int main(){
int C[4] = {541, 795, 1479, 2753};
int M[4];
int d[4] = {1019, 1019, 1019, 1019};
int N[4] = {3337, 3337, 3337, 3337};
int *C_GPU, *M_GPU, *d_GPU, *N_GPU;
int size = 4 * sizeof(int);
hipMalloc((void **)&C_GPU, size);
hipMalloc((void **)&M_GPU, size);
hipMalloc((void **)&d_GPU, size);
hipMalloc((void **)&N_GPU, size);
hipMemcpy(C_GPU, C, size, hipMemcpyHostToDevice);
hipMemcpy(d_GPU, d, size, hipMemcpyHostToDevice);
hipMemcpy(N_GPU, N, size, hipMemcpyHostToDevice);
decyrption<<<1, 4>>>(M_GPU, C_GPU, d_GPU, N_GPU);
hipMemcpy(M, M_GPU, size, hipMemcpyDeviceToHost);
hipFree(M_GPU);
hipFree(C_GPU);
hipFree(d_GPU);
hipFree(N_GPU);
int i;
for (i = 0; i < 4; i++){
printf("The result is %d, %d\n", M[i], C[i]);
}
} | .text
.file "decryption.hip"
.globl _Z25__device_stub__decyrptionPiS_S_S_ # -- Begin function _Z25__device_stub__decyrptionPiS_S_S_
.p2align 4, 0x90
.type _Z25__device_stub__decyrptionPiS_S_S_,@function
_Z25__device_stub__decyrptionPiS_S_S_: # @_Z25__device_stub__decyrptionPiS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10decyrptionPiS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__decyrptionPiS_S_S_, .Lfunc_end0-_Z25__device_stub__decyrptionPiS_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 541 # 0x21d
.long 795 # 0x31b
.long 1479 # 0x5c7
.long 2753 # 0xac1
.LCPI1_1:
.long 1019 # 0x3fb
.long 1019 # 0x3fb
.long 1019 # 0x3fb
.long 1019 # 0x3fb
.LCPI1_2:
.long 3337 # 0xd09
.long 3337 # 0xd09
.long 3337 # 0xd09
.long 3337 # 0xd09
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $192, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [541,795,1479,2753]
movaps %xmm0, 144(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [1019,1019,1019,1019]
movaps %xmm0, 176(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [3337,3337,3337,3337]
movaps %xmm0, 160(%rsp)
leaq 24(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 160(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10decyrptionPiS_S_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $16, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl 144(%rsp,%rbx,4), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4, %rbx
jne .LBB1_3
# %bb.4:
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10decyrptionPiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10decyrptionPiS_S_S_,@object # @_Z10decyrptionPiS_S_S_
.section .rodata,"a",@progbits
.globl _Z10decyrptionPiS_S_S_
.p2align 3, 0x0
_Z10decyrptionPiS_S_S_:
.quad _Z25__device_stub__decyrptionPiS_S_S_
.size _Z10decyrptionPiS_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The result is %d, %d\n"
.size .L.str, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10decyrptionPiS_S_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__decyrptionPiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10decyrptionPiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b3906_00000000-6_decryption.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_
.type _Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_, @function
_Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10decyrptionPiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_, .-_Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_
.globl _Z10decyrptionPiS_S_S_
.type _Z10decyrptionPiS_S_S_, @function
_Z10decyrptionPiS_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10decyrptionPiS_S_S_, .-_Z10decyrptionPiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "The result is %d, %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $541, 64(%rsp)
movl $795, 68(%rsp)
movl $1479, 72(%rsp)
movl $2753, 76(%rsp)
movl $1019, 96(%rsp)
movl $1019, 100(%rsp)
movl $1019, 104(%rsp)
movl $1019, 108(%rsp)
movl $3337, 112(%rsp)
movl $3337, 116(%rsp)
movl $3337, 120(%rsp)
movl $3337, 124(%rsp)
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L13:
movl 64(%rsp,%rbx), %ecx
movl 80(%rsp,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $16, %rbx
jne .L13
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z10decyrptionPiS_S_S_PiS_S_S_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10decyrptionPiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10decyrptionPiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "decryption.hip"
.globl _Z25__device_stub__decyrptionPiS_S_S_ # -- Begin function _Z25__device_stub__decyrptionPiS_S_S_
.p2align 4, 0x90
.type _Z25__device_stub__decyrptionPiS_S_S_,@function
_Z25__device_stub__decyrptionPiS_S_S_: # @_Z25__device_stub__decyrptionPiS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10decyrptionPiS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__decyrptionPiS_S_S_, .Lfunc_end0-_Z25__device_stub__decyrptionPiS_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 541 # 0x21d
.long 795 # 0x31b
.long 1479 # 0x5c7
.long 2753 # 0xac1
.LCPI1_1:
.long 1019 # 0x3fb
.long 1019 # 0x3fb
.long 1019 # 0x3fb
.long 1019 # 0x3fb
.LCPI1_2:
.long 3337 # 0xd09
.long 3337 # 0xd09
.long 3337 # 0xd09
.long 3337 # 0xd09
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $192, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [541,795,1479,2753]
movaps %xmm0, 144(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [1019,1019,1019,1019]
movaps %xmm0, 176(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [3337,3337,3337,3337]
movaps %xmm0, 160(%rsp)
leaq 24(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 160(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10decyrptionPiS_S_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $16, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl 144(%rsp,%rbx,4), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4, %rbx
jne .LBB1_3
# %bb.4:
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10decyrptionPiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10decyrptionPiS_S_S_,@object # @_Z10decyrptionPiS_S_S_
.section .rodata,"a",@progbits
.globl _Z10decyrptionPiS_S_S_
.p2align 3, 0x0
_Z10decyrptionPiS_S_S_:
.quad _Z25__device_stub__decyrptionPiS_S_S_
.size _Z10decyrptionPiS_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The result is %d, %d\n"
.size .L.str, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10decyrptionPiS_S_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__decyrptionPiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10decyrptionPiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<math.h>
#include<cuda.h>
#define N 256
__global__ void matrix_vector_multi_gpu_1_256(float *A_d,float *B_d,float *C_d){
int i;
A_d[threadIdx.x]=0.0;
for(i=0;i<N;i++){
A_d[threadIdx.x]=A_d[threadIdx.x]+B_d[threadIdx.x*N+i]*C_d[i];
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
float *A_d,*B_d,*C_d;
dim3 blocks(1,1,1);
dim3 threads(256,1,1);
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
cudaMalloc((void**)&A_d,N*sizeof(float));
cudaMalloc((void**)&B_d,N*N*sizeof(float));
cudaMalloc((void**)&C_d,N*sizeof(float));
cudaMemcpy(A_d,A,N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B,N*N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(C_d,C,N*sizeof(float),cudaMemcpyHostToDevice);
matrix_vector_multi_gpu_1_256<<<blocks,threads>>>(A_d,B_d,C_d);
cudaMemcpy(A,A_d,N*sizeof(float),cudaMemcpyDeviceToHost);
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
return 0;
} | code for sm_80
Function : _Z29matrix_vector_multi_gpu_1_256PfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0050*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe40000000f00 */
/*0060*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*0070*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fc60000000f00 */
/*0080*/ IMAD.WIDE.U32 R2, R4.reuse, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x041fe200078e0005 */
/*0090*/ SHF.L.U32 R4, R4, 0x8, RZ ; /* 0x0000000804047819 */
/* 0x000fc800000006ff */
/*00a0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*00b0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0005 */
/*00c0*/ IADD3 R8, P0, R4, 0x20, RZ ; /* 0x0000002004087810 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R5, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff057210 */
/* 0x001fe400007fe4ff */
/*00e0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fe40000000f00 */
/*00f0*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R10, [R4.64+-0x20] ; /* 0xffffe004040a7981 */
/* 0x000ea4000c1e1900 */
/*0110*/ FFMA R9, R8, R10, R9 ; /* 0x0000000a08097223 */
/* 0x006fca0000000009 */
/*0120*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0130*/ LDG.E R8, [R6.64+0x4] ; /* 0x0000040406087981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R10, [R4.64+-0x1c] ; /* 0xffffe404040a7981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FFMA R11, R8, R10, R9 ; /* 0x0000000a080b7223 */
/* 0x004fca0000000009 */
/*0160*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0170*/ LDG.E R8, [R6.64+0x8] ; /* 0x0000080406087981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R10, [R4.64+-0x18] ; /* 0xffffe804040a7981 */
/* 0x000ea4000c1e1900 */
/*0190*/ FFMA R13, R8, R10, R11 ; /* 0x0000000a080d7223 */
/* 0x004fca000000000b */
/*01a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*01b0*/ LDG.E R8, [R6.64+0xc] ; /* 0x00000c0406087981 */
/* 0x000e28000c1e1900 */
/*01c0*/ LDG.E R10, [R4.64+-0x14] ; /* 0xffffec04040a7981 */
/* 0x000e24000c1e1900 */
/*01d0*/ FFMA R9, R8, R10, R13 ; /* 0x0000000a08097223 */
/* 0x001fca000000000d */
/*01e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R8, [R6.64+0x10] ; /* 0x0000100406087981 */
/* 0x000e68000c1e1900 */
/*0200*/ LDG.E R10, [R4.64+-0x10] ; /* 0xfffff004040a7981 */
/* 0x000e64000c1e1900 */
/*0210*/ FFMA R11, R8, R10, R9 ; /* 0x0000000a080b7223 */
/* 0x002fca0000000009 */
/*0220*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0230*/ LDG.E R8, [R6.64+0x14] ; /* 0x0000140406087981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R10, [R4.64+-0xc] ; /* 0xfffff404040a7981 */
/* 0x000ea4000c1e1900 */
/*0250*/ FFMA R13, R8, R10, R11 ; /* 0x0000000a080d7223 */
/* 0x004fca000000000b */
/*0260*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0270*/ LDG.E R8, [R6.64+0x18] ; /* 0x0000180406087981 */
/* 0x000e28000c1e1900 */
/*0280*/ LDG.E R10, [R4.64+-0x8] ; /* 0xfffff804040a7981 */
/* 0x000e24000c1e1900 */
/*0290*/ FFMA R9, R8, R10, R13 ; /* 0x0000000a08097223 */
/* 0x001fca000000000d */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R8, [R6.64+0x1c] ; /* 0x00001c0406087981 */
/* 0x000e68000c1e1900 */
/*02c0*/ LDG.E R10, [R4.64+-0x4] ; /* 0xfffffc04040a7981 */
/* 0x000e64000c1e1900 */
/*02d0*/ FFMA R11, R8, R10, R9 ; /* 0x0000000a080b7223 */
/* 0x002fca0000000009 */
/*02e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*02f0*/ LDG.E R8, [R6.64+0x20] ; /* 0x0000200406087981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0310*/ FFMA R13, R8, R10, R11 ; /* 0x0000000a080d7223 */
/* 0x004fca000000000b */
/*0320*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R8, [R6.64+0x24] ; /* 0x0000240406087981 */
/* 0x000e28000c1e1900 */
/*0340*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000e24000c1e1900 */
/*0350*/ FFMA R9, R8, R10, R13 ; /* 0x0000000a08097223 */
/* 0x001fca000000000d */
/*0360*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0370*/ LDG.E R8, [R6.64+0x28] ; /* 0x0000280406087981 */
/* 0x000e68000c1e1900 */
/*0380*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000e64000c1e1900 */
/*0390*/ FFMA R11, R8, R10, R9 ; /* 0x0000000a080b7223 */
/* 0x002fca0000000009 */
/*03a0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*03b0*/ LDG.E R8, [R6.64+0x2c] ; /* 0x00002c0406087981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ FFMA R13, R8, R10, R11 ; /* 0x0000000a080d7223 */
/* 0x004fca000000000b */
/*03e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*03f0*/ LDG.E R8, [R6.64+0x30] ; /* 0x0000300406087981 */
/* 0x000e28000c1e1900 */
/*0400*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000e24000c1e1900 */
/*0410*/ FFMA R9, R8, R10, R13 ; /* 0x0000000a08097223 */
/* 0x001fca000000000d */
/*0420*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0430*/ LDG.E R8, [R6.64+0x34] ; /* 0x0000340406087981 */
/* 0x000e68000c1e1900 */
/*0440*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000e64000c1e1900 */
/*0450*/ FFMA R11, R8, R10, R9 ; /* 0x0000000a080b7223 */
/* 0x002fca0000000009 */
/*0460*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0470*/ LDG.E R8, [R6.64+0x38] ; /* 0x0000380406087981 */
/* 0x000ea8000c1e1900 */
/*0480*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */
/* 0x000ea2000c1e1900 */
/*0490*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ FFMA R13, R8, R10, R11 ; /* 0x0000000a080d7223 */
/* 0x004fca000000000b */
/*04b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*04c0*/ LDG.E R8, [R6.64+0x3c] ; /* 0x00003c0406087981 */
/* 0x000428000c1e1900 */
/*04d0*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000e22000c1e1900 */
/*04e0*/ ISETP.NE.AND P0, PT, R0, 0x100, PT ; /* 0x000001000000780c */
/* 0x000fe40003f05270 */
/*04f0*/ IADD3 R6, P2, R6, 0x40, RZ ; /* 0x0000004006067810 */
/* 0x004fc80007f5e0ff */
/*0500*/ IADD3.X R7, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff077210 */
/* 0x000fe200017fe4ff */
/*0510*/ FFMA R9, R8, R10, R13 ; /* 0x0000000a08097223 */
/* 0x001fe2000000000d */
/*0520*/ IADD3 R8, P1, R4, 0x40, RZ ; /* 0x0000004004087810 */
/* 0x000fc80007f3e0ff */
/*0530*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e2000c101904 */
/*0540*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0550*/ @P0 BRA 0xe0 ; /* 0xfffffb8000000947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<math.h>
#include<cuda.h>
#define N 256
__global__ void matrix_vector_multi_gpu_1_256(float *A_d,float *B_d,float *C_d){
int i;
A_d[threadIdx.x]=0.0;
for(i=0;i<N;i++){
A_d[threadIdx.x]=A_d[threadIdx.x]+B_d[threadIdx.x*N+i]*C_d[i];
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
float *A_d,*B_d,*C_d;
dim3 blocks(1,1,1);
dim3 threads(256,1,1);
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
cudaMalloc((void**)&A_d,N*sizeof(float));
cudaMalloc((void**)&B_d,N*N*sizeof(float));
cudaMalloc((void**)&C_d,N*sizeof(float));
cudaMemcpy(A_d,A,N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B,N*N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(C_d,C,N*sizeof(float),cudaMemcpyHostToDevice);
matrix_vector_multi_gpu_1_256<<<blocks,threads>>>(A_d,B_d,C_d);
cudaMemcpy(A,A_d,N*sizeof(float),cudaMemcpyDeviceToHost);
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
return 0;
} | .file "tmpxft_0012f8a0_00000000-6_Matrix-cuda-256.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_
.type _Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_, @function
_Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29matrix_vector_multi_gpu_1_256PfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_, .-_Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_
.globl _Z29matrix_vector_multi_gpu_1_256PfS_S_
.type _Z29matrix_vector_multi_gpu_1_256PfS_S_, @function
_Z29matrix_vector_multi_gpu_1_256PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z29matrix_vector_multi_gpu_1_256PfS_S_, .-_Z29matrix_vector_multi_gpu_1_256PfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "A[ %d ]=%f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -262144(%rsp), %r11
.cfi_def_cfa 11, 262168
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2120, %rsp
.cfi_def_cfa_offset 264288
movq %fs:40, %rax
movq %rax, 264248(%rsp)
xorl %eax, %eax
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
leaq 3120(%rsp), %rdx
movl $0, %ecx
movss .LC0(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss %xmm1, %xmm0
leaq -1024(%rdx), %rax
.L13:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
addl $1, %ecx
addq $1024, %rdx
cmpl $256, %ecx
jne .L12
leaq 1072(%rsp), %rax
leaq 2096(%rsp), %rdx
movss .LC1(%rip), %xmm0
.L15:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L15
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 2096(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 1072(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L16:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $1024, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L17:
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $256, %rbx
jne .L17
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 264248(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $264264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z29matrix_vector_multi_gpu_1_256PfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z29matrix_vector_multi_gpu_1_256PfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 998244352
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<math.h>
#include<cuda.h>
#define N 256
__global__ void matrix_vector_multi_gpu_1_256(float *A_d,float *B_d,float *C_d){
int i;
A_d[threadIdx.x]=0.0;
for(i=0;i<N;i++){
A_d[threadIdx.x]=A_d[threadIdx.x]+B_d[threadIdx.x*N+i]*C_d[i];
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
float *A_d,*B_d,*C_d;
dim3 blocks(1,1,1);
dim3 threads(256,1,1);
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
cudaMalloc((void**)&A_d,N*sizeof(float));
cudaMalloc((void**)&B_d,N*N*sizeof(float));
cudaMalloc((void**)&C_d,N*sizeof(float));
cudaMemcpy(A_d,A,N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B,N*N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(C_d,C,N*sizeof(float),cudaMemcpyHostToDevice);
matrix_vector_multi_gpu_1_256<<<blocks,threads>>>(A_d,B_d,C_d);
cudaMemcpy(A,A_d,N*sizeof(float),cudaMemcpyDeviceToHost);
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
return 0;
} | #include<stdio.h>
#include<math.h>
#include<hip/hip_runtime.h>
#define N 256
__global__ void matrix_vector_multi_gpu_1_256(float *A_d,float *B_d,float *C_d){
int i;
A_d[threadIdx.x]=0.0;
for(i=0;i<N;i++){
A_d[threadIdx.x]=A_d[threadIdx.x]+B_d[threadIdx.x*N+i]*C_d[i];
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
float *A_d,*B_d,*C_d;
dim3 blocks(1,1,1);
dim3 threads(256,1,1);
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
hipMalloc((void**)&A_d,N*sizeof(float));
hipMalloc((void**)&B_d,N*N*sizeof(float));
hipMalloc((void**)&C_d,N*sizeof(float));
hipMemcpy(A_d,A,N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(B_d,B,N*N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(C_d,C,N*sizeof(float),hipMemcpyHostToDevice);
matrix_vector_multi_gpu_1_256<<<blocks,threads>>>(A_d,B_d,C_d);
hipMemcpy(A,A_d,N*sizeof(float),hipMemcpyDeviceToHost);
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<math.h>
#include<hip/hip_runtime.h>
#define N 256
__global__ void matrix_vector_multi_gpu_1_256(float *A_d,float *B_d,float *C_d){
int i;
A_d[threadIdx.x]=0.0;
for(i=0;i<N;i++){
A_d[threadIdx.x]=A_d[threadIdx.x]+B_d[threadIdx.x*N+i]*C_d[i];
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
float *A_d,*B_d,*C_d;
dim3 blocks(1,1,1);
dim3 threads(256,1,1);
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
hipMalloc((void**)&A_d,N*sizeof(float));
hipMalloc((void**)&B_d,N*N*sizeof(float));
hipMalloc((void**)&C_d,N*sizeof(float));
hipMemcpy(A_d,A,N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(B_d,B,N*N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(C_d,C,N*sizeof(float),hipMemcpyHostToDevice);
matrix_vector_multi_gpu_1_256<<<blocks,threads>>>(A_d,B_d,C_d);
hipMemcpy(A,A_d,N*sizeof(float),hipMemcpyDeviceToHost);
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29matrix_vector_multi_gpu_1_256PfS_S_
.globl _Z29matrix_vector_multi_gpu_1_256PfS_S_
.p2align 8
.type _Z29matrix_vector_multi_gpu_1_256PfS_S_,@function
_Z29matrix_vector_multi_gpu_1_256PfS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v6, 2, v0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 10, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s2, s4, v6
v_add_co_ci_u32_e64 v1, null, s5, 0, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, s6, v3
v_add_co_ci_u32_e64 v4, null, s7, 0, s2
s_mov_b64 s[2:3], 0
global_store_b32 v6, v2, s[4:5]
.LBB0_1:
v_add_co_u32 v6, vcc_lo, v3, s2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v4, vcc_lo
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
global_load_b32 v8, v2, s[4:5]
global_load_b32 v6, v[6:7], off
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x400
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v6, v8
global_store_b32 v[0:1], v5, off
s_cbranch_scc1 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29matrix_vector_multi_gpu_1_256PfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29matrix_vector_multi_gpu_1_256PfS_S_, .Lfunc_end0-_Z29matrix_vector_multi_gpu_1_256PfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29matrix_vector_multi_gpu_1_256PfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z29matrix_vector_multi_gpu_1_256PfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<math.h>
#include<hip/hip_runtime.h>
#define N 256
__global__ void matrix_vector_multi_gpu_1_256(float *A_d,float *B_d,float *C_d){
int i;
A_d[threadIdx.x]=0.0;
for(i=0;i<N;i++){
A_d[threadIdx.x]=A_d[threadIdx.x]+B_d[threadIdx.x*N+i]*C_d[i];
}
}
int main(){
int i,j;
float A[N],B[N*N],C[N];
float *A_d,*B_d,*C_d;
dim3 blocks(1,1,1);
dim3 threads(256,1,1);
for(j=0;j<N;j++){
for(i=0;i<N;i++){
B[j*N+i]=((float)j)/256.0;
}
}
for(j=0;j<N;j++){
C[j]=1.0F;
}
hipMalloc((void**)&A_d,N*sizeof(float));
hipMalloc((void**)&B_d,N*N*sizeof(float));
hipMalloc((void**)&C_d,N*sizeof(float));
hipMemcpy(A_d,A,N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(B_d,B,N*N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(C_d,C,N*sizeof(float),hipMemcpyHostToDevice);
matrix_vector_multi_gpu_1_256<<<blocks,threads>>>(A_d,B_d,C_d);
hipMemcpy(A,A_d,N*sizeof(float),hipMemcpyDeviceToHost);
for(j=0;j<N;j++){
printf("A[ %d ]=%f \n",j,A[j]);
}
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
return 0;
} | .text
.file "Matrix-cuda-256.hip"
.globl _Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_ # -- Begin function _Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_
.p2align 4, 0x90
.type _Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_,@function
_Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_: # @_Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29matrix_vector_multi_gpu_1_256PfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_, .Lfunc_end0-_Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $264320, %rsp # imm = 0x40880
.cfi_def_cfa_offset 264336
.cfi_offset %rbx, -16
leaq 2176(%rsp), %rax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm1, (%rax,%rdx,4)
incq %rdx
cmpq $256, %rdx # imm = 0x100
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $1024, %rax # imm = 0x400
cmpq $256, %rcx # imm = 0x100
jne .LBB1_1
# %bb.4: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, 1152(%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_5
# %bb.6:
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq (%rsp), %rdi
leaq 128(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 2176(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 1152(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z29matrix_vector_multi_gpu_1_256PfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movss 128(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_9
# %bb.10:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $264320, %rsp # imm = 0x40880
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29matrix_vector_multi_gpu_1_256PfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29matrix_vector_multi_gpu_1_256PfS_S_,@object # @_Z29matrix_vector_multi_gpu_1_256PfS_S_
.section .rodata,"a",@progbits
.globl _Z29matrix_vector_multi_gpu_1_256PfS_S_
.p2align 3, 0x0
_Z29matrix_vector_multi_gpu_1_256PfS_S_:
.quad _Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_
.size _Z29matrix_vector_multi_gpu_1_256PfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A[ %d ]=%f \n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z29matrix_vector_multi_gpu_1_256PfS_S_"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29matrix_vector_multi_gpu_1_256PfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z29matrix_vector_multi_gpu_1_256PfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0050*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe40000000f00 */
/*0060*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*0070*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fc60000000f00 */
/*0080*/ IMAD.WIDE.U32 R2, R4.reuse, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x041fe200078e0005 */
/*0090*/ SHF.L.U32 R4, R4, 0x8, RZ ; /* 0x0000000804047819 */
/* 0x000fc800000006ff */
/*00a0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*00b0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0005 */
/*00c0*/ IADD3 R8, P0, R4, 0x20, RZ ; /* 0x0000002004087810 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R5, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff057210 */
/* 0x001fe400007fe4ff */
/*00e0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fe40000000f00 */
/*00f0*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R10, [R4.64+-0x20] ; /* 0xffffe004040a7981 */
/* 0x000ea4000c1e1900 */
/*0110*/ FFMA R9, R8, R10, R9 ; /* 0x0000000a08097223 */
/* 0x006fca0000000009 */
/*0120*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0130*/ LDG.E R8, [R6.64+0x4] ; /* 0x0000040406087981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R10, [R4.64+-0x1c] ; /* 0xffffe404040a7981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FFMA R11, R8, R10, R9 ; /* 0x0000000a080b7223 */
/* 0x004fca0000000009 */
/*0160*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0170*/ LDG.E R8, [R6.64+0x8] ; /* 0x0000080406087981 */
/* 0x000ea8000c1e1900 */
/*0180*/ LDG.E R10, [R4.64+-0x18] ; /* 0xffffe804040a7981 */
/* 0x000ea4000c1e1900 */
/*0190*/ FFMA R13, R8, R10, R11 ; /* 0x0000000a080d7223 */
/* 0x004fca000000000b */
/*01a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*01b0*/ LDG.E R8, [R6.64+0xc] ; /* 0x00000c0406087981 */
/* 0x000e28000c1e1900 */
/*01c0*/ LDG.E R10, [R4.64+-0x14] ; /* 0xffffec04040a7981 */
/* 0x000e24000c1e1900 */
/*01d0*/ FFMA R9, R8, R10, R13 ; /* 0x0000000a08097223 */
/* 0x001fca000000000d */
/*01e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R8, [R6.64+0x10] ; /* 0x0000100406087981 */
/* 0x000e68000c1e1900 */
/*0200*/ LDG.E R10, [R4.64+-0x10] ; /* 0xfffff004040a7981 */
/* 0x000e64000c1e1900 */
/*0210*/ FFMA R11, R8, R10, R9 ; /* 0x0000000a080b7223 */
/* 0x002fca0000000009 */
/*0220*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0230*/ LDG.E R8, [R6.64+0x14] ; /* 0x0000140406087981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R10, [R4.64+-0xc] ; /* 0xfffff404040a7981 */
/* 0x000ea4000c1e1900 */
/*0250*/ FFMA R13, R8, R10, R11 ; /* 0x0000000a080d7223 */
/* 0x004fca000000000b */
/*0260*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0270*/ LDG.E R8, [R6.64+0x18] ; /* 0x0000180406087981 */
/* 0x000e28000c1e1900 */
/*0280*/ LDG.E R10, [R4.64+-0x8] ; /* 0xfffff804040a7981 */
/* 0x000e24000c1e1900 */
/*0290*/ FFMA R9, R8, R10, R13 ; /* 0x0000000a08097223 */
/* 0x001fca000000000d */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R8, [R6.64+0x1c] ; /* 0x00001c0406087981 */
/* 0x000e68000c1e1900 */
/*02c0*/ LDG.E R10, [R4.64+-0x4] ; /* 0xfffffc04040a7981 */
/* 0x000e64000c1e1900 */
/*02d0*/ FFMA R11, R8, R10, R9 ; /* 0x0000000a080b7223 */
/* 0x002fca0000000009 */
/*02e0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*02f0*/ LDG.E R8, [R6.64+0x20] ; /* 0x0000200406087981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea4000c1e1900 */
/*0310*/ FFMA R13, R8, R10, R11 ; /* 0x0000000a080d7223 */
/* 0x004fca000000000b */
/*0320*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R8, [R6.64+0x24] ; /* 0x0000240406087981 */
/* 0x000e28000c1e1900 */
/*0340*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000e24000c1e1900 */
/*0350*/ FFMA R9, R8, R10, R13 ; /* 0x0000000a08097223 */
/* 0x001fca000000000d */
/*0360*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0370*/ LDG.E R8, [R6.64+0x28] ; /* 0x0000280406087981 */
/* 0x000e68000c1e1900 */
/*0380*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000e64000c1e1900 */
/*0390*/ FFMA R11, R8, R10, R9 ; /* 0x0000000a080b7223 */
/* 0x002fca0000000009 */
/*03a0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*03b0*/ LDG.E R8, [R6.64+0x2c] ; /* 0x00002c0406087981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ FFMA R13, R8, R10, R11 ; /* 0x0000000a080d7223 */
/* 0x004fca000000000b */
/*03e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*03f0*/ LDG.E R8, [R6.64+0x30] ; /* 0x0000300406087981 */
/* 0x000e28000c1e1900 */
/*0400*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000e24000c1e1900 */
/*0410*/ FFMA R9, R8, R10, R13 ; /* 0x0000000a08097223 */
/* 0x001fca000000000d */
/*0420*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0430*/ LDG.E R8, [R6.64+0x34] ; /* 0x0000340406087981 */
/* 0x000e68000c1e1900 */
/*0440*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000e64000c1e1900 */
/*0450*/ FFMA R11, R8, R10, R9 ; /* 0x0000000a080b7223 */
/* 0x002fca0000000009 */
/*0460*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0470*/ LDG.E R8, [R6.64+0x38] ; /* 0x0000380406087981 */
/* 0x000ea8000c1e1900 */
/*0480*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */
/* 0x000ea2000c1e1900 */
/*0490*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ FFMA R13, R8, R10, R11 ; /* 0x0000000a080d7223 */
/* 0x004fca000000000b */
/*04b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*04c0*/ LDG.E R8, [R6.64+0x3c] ; /* 0x00003c0406087981 */
/* 0x000428000c1e1900 */
/*04d0*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000e22000c1e1900 */
/*04e0*/ ISETP.NE.AND P0, PT, R0, 0x100, PT ; /* 0x000001000000780c */
/* 0x000fe40003f05270 */
/*04f0*/ IADD3 R6, P2, R6, 0x40, RZ ; /* 0x0000004006067810 */
/* 0x004fc80007f5e0ff */
/*0500*/ IADD3.X R7, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff077210 */
/* 0x000fe200017fe4ff */
/*0510*/ FFMA R9, R8, R10, R13 ; /* 0x0000000a08097223 */
/* 0x001fe2000000000d */
/*0520*/ IADD3 R8, P1, R4, 0x40, RZ ; /* 0x0000004004087810 */
/* 0x000fc80007f3e0ff */
/*0530*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e2000c101904 */
/*0540*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0550*/ @P0 BRA 0xe0 ; /* 0xfffffb8000000947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29matrix_vector_multi_gpu_1_256PfS_S_
.globl _Z29matrix_vector_multi_gpu_1_256PfS_S_
.p2align 8
.type _Z29matrix_vector_multi_gpu_1_256PfS_S_,@function
_Z29matrix_vector_multi_gpu_1_256PfS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v6, 2, v0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 10, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s2, s4, v6
v_add_co_ci_u32_e64 v1, null, s5, 0, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, s6, v3
v_add_co_ci_u32_e64 v4, null, s7, 0, s2
s_mov_b64 s[2:3], 0
global_store_b32 v6, v2, s[4:5]
.LBB0_1:
v_add_co_u32 v6, vcc_lo, v3, s2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v4, vcc_lo
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
global_load_b32 v8, v2, s[4:5]
global_load_b32 v6, v[6:7], off
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s2, 0x400
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v6, v8
global_store_b32 v[0:1], v5, off
s_cbranch_scc1 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29matrix_vector_multi_gpu_1_256PfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29matrix_vector_multi_gpu_1_256PfS_S_, .Lfunc_end0-_Z29matrix_vector_multi_gpu_1_256PfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29matrix_vector_multi_gpu_1_256PfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z29matrix_vector_multi_gpu_1_256PfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012f8a0_00000000-6_Matrix-cuda-256.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_
.type _Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_, @function
_Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29matrix_vector_multi_gpu_1_256PfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_, .-_Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_
.globl _Z29matrix_vector_multi_gpu_1_256PfS_S_
.type _Z29matrix_vector_multi_gpu_1_256PfS_S_, @function
_Z29matrix_vector_multi_gpu_1_256PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z29matrix_vector_multi_gpu_1_256PfS_S_, .-_Z29matrix_vector_multi_gpu_1_256PfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "A[ %d ]=%f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -262144(%rsp), %r11
.cfi_def_cfa 11, 262168
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2120, %rsp
.cfi_def_cfa_offset 264288
movq %fs:40, %rax
movq %rax, 264248(%rsp)
xorl %eax, %eax
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
leaq 3120(%rsp), %rdx
movl $0, %ecx
movss .LC0(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss %xmm1, %xmm0
leaq -1024(%rdx), %rax
.L13:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
addl $1, %ecx
addq $1024, %rdx
cmpl $256, %ecx
jne .L12
leaq 1072(%rsp), %rax
leaq 2096(%rsp), %rdx
movss .LC1(%rip), %xmm0
.L15:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L15
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 2096(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 1072(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl 32(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L16:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $1024, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L17:
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $256, %rbx
jne .L17
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 264248(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $264264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z53__device_stub__Z29matrix_vector_multi_gpu_1_256PfS_S_PfS_S_
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z29matrix_vector_multi_gpu_1_256PfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z29matrix_vector_multi_gpu_1_256PfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 998244352
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Matrix-cuda-256.hip"
.globl _Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_ # -- Begin function _Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_
.p2align 4, 0x90
.type _Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_,@function
_Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_: # @_Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29matrix_vector_multi_gpu_1_256PfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_, .Lfunc_end0-_Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $264320, %rsp # imm = 0x40880
.cfi_def_cfa_offset 264336
.cfi_offset %rbx, -16
leaq 2176(%rsp), %rax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm1, (%rax,%rdx,4)
incq %rdx
cmpq $256, %rdx # imm = 0x100
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $1024, %rax # imm = 0x400
cmpq $256, %rcx # imm = 0x100
jne .LBB1_1
# %bb.4: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, 1152(%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_5
# %bb.6:
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq (%rsp), %rdi
leaq 128(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 2176(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 1152(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z29matrix_vector_multi_gpu_1_256PfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq (%rsp), %rsi
leaq 128(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movss 128(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_9
# %bb.10:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $264320, %rsp # imm = 0x40880
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29matrix_vector_multi_gpu_1_256PfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29matrix_vector_multi_gpu_1_256PfS_S_,@object # @_Z29matrix_vector_multi_gpu_1_256PfS_S_
.section .rodata,"a",@progbits
.globl _Z29matrix_vector_multi_gpu_1_256PfS_S_
.p2align 3, 0x0
_Z29matrix_vector_multi_gpu_1_256PfS_S_:
.quad _Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_
.size _Z29matrix_vector_multi_gpu_1_256PfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A[ %d ]=%f \n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z29matrix_vector_multi_gpu_1_256PfS_S_"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__matrix_vector_multi_gpu_1_256PfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29matrix_vector_multi_gpu_1_256PfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define NBR 68
__global__ void histo_kernel(unsigned char *buffer,long size, unsigned int *histo){
__shared__ unsigned int temp[68];
int dt = 32;
temp[threadIdx.x]=0;
int i = threadIdx.x + blockIdx.x *blockDim.x;
int offset = blockDim.x *gridDim.x;
while(i<size){
if (buffer[i] >= 32 && buffer[i] < 97)
// histo[buffer[i]-dt]++;
atomicAdd(&temp[buffer[i]-dt],1);
if (buffer[i] >=97 && buffer[i] <= 122)
atomicAdd(&temp[buffer[i] -dt -32],1);
// histo[buffer[i] - dt - 32]++;
if (buffer[i] > 122 && buffer[i] <= 127 )
// histo[buffer[i] - dt - 32 - 26]++;
atomicAdd(&temp[buffer[i]-dt -32-26],1);
i+=offset;
}
__syncthreads();
atomicAdd( &(histo[threadIdx.x]), temp[threadIdx.x] );
}
int main(int argc, char *argv[]){
// unsigned char *buffer = (unsigned char *) big_random_block(SIZE);
if(argc <= 2){
fprintf(stderr, "Arguments non valide");
return 1;
}
/*For file input file and output file*/
FILE *f_input;
FILE *f_output;
/*Will content the number of char in the input file*/
long lSize;
/*will content the file in char format*/
char *buffer;
/*Open the */
f_input = fopen ( argv[1] ,"r" );
f_output = fopen( argv[2],"w");
if( !f_input ) perror(argv[1]),exit(1);
fseek( f_input , 0L , SEEK_END);
lSize = ftell( f_input );
rewind( f_input );
//buffer = calloc( 1, lSize+1 );
buffer =(char*) malloc(lSize);
if( !buffer ) fclose(f_input),fputs("memory alloc fails",stderr),exit(1);
if( 1!=fread( buffer , lSize, 1 , f_input) )
fclose(f_input),free(buffer),fputs("entire read fails",stderr),exit(1);
/*Create event for co;pute running time*/
cudaEvent_t start, stop;
cudaEventCreate( &start );
cudaEventCreate( &stop );
/*Launch event to specify the start of running*/
cudaEventRecord( start, 0);
/*allocate device memory*/
unsigned char *dev_buffer;
unsigned int *dev_histo;
/*Give space in Global memory of GPU to store different variable*/
cudaMalloc( (void**)&dev_buffer, lSize);
/*Copy from CPU Global memory to GPU Global memory*/
cudaMemcpy( dev_buffer, buffer, lSize, cudaMemcpyHostToDevice );
/*Create space for histo variable and initialize at 0 each slopt*/
cudaMalloc( (void**)&dev_histo, NBR * sizeof( long));
cudaMemset( dev_histo, 0, NBR * sizeof( int ));
/*Define of the configuration for kernel running*/
cudaDeviceProp proprieties;
cudaGetDeviceProperties( &proprieties, 0 );
int multiproc = proprieties.multiProcessorCount;
dim3 blocks(multiproc*2,1,1);
dim3 threads(NBR, 1, 1);
histo_kernel<<<blocks,threads>>>( dev_buffer, lSize, dev_histo );
/*Define histo vqriqble and copy on GPU global memory*/
unsigned int histo[NBR];
cudaMemcpy( histo, dev_histo,NBR * sizeof( int ),cudaMemcpyDeviceToHost);
int dt =32;
for(int i =0;i< NBR;i++){
if((i>=0 && i<= 31 && (i+dt != 42) && (i+dt != 36)) || (i>58 && i<=64) )
fprintf(f_output, "%c:%d\n",i+dt,histo[i]);
if(i>31 && i<= 58 )
fprintf(f_output, "%c:%d\n",i+dt+32,histo[i]);
// if(i> 58 && i <=64)
// fprintf(f_output, "%c:%d\n",i+dt,histo[i]);
if(i>64)
fprintf(f_output, "%c:%d\n",i+dt+26,histo[i]);
}
/*Get event at the end of loop*/
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
float elapsedTime;
cudaEventElapsedTime( &elapsedTime, start, stop );
printf( "Time of running : %3.1f ms\n", elapsedTime );
/*Destroy event for running time*/
cudaEventDestroy( start );
cudaEventDestroy( stop );
/*Free memory and close the files**/
cudaFree( dev_histo );
cudaFree( dev_buffer );
fclose(f_input);
fclose(f_output);
free( buffer );
return 0;
} | code for sm_80
Function : _Z12histo_kernelPhlPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ STS [R7.X4], RZ ; /* 0x000000ff07007388 */
/* 0x0011e20000004800 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0207 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0070*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0080*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06300 */
/*0090*/ @P0 BRA 0x2c0 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff037224 */
/* 0x001fe400078e0002 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0000 */
/*00c0*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R3, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fca00007fe4ff */
/*00e0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0100*/ BSSY B0, 0x1d0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0110*/ IADD3 R4, R2.reuse, -0x20, RZ ; /* 0xffffffe002047810 */
/* 0x044fe40007ffe0ff */
/*0120*/ PRMT R6, R2, 0x8880, RZ ; /* 0x0000888002067816 */
/* 0x000fe400000000ff */
/*0130*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*0140*/ IADD3 R5, R2, -0x61, RZ ; /* 0xffffff9f02057810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GT.U32.AND P2, PT, R4, 0x40, PT ; /* 0x000000400400780c */
/* 0x000fc40003f44070 */
/*0160*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0170*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f06270 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R5, 0x19, PT ; /* 0x000000190500780c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.LT.U32.OR P0, PT, R2, 0x7b, !P0 ; /* 0x0000007b0200780c */
/* 0x000fca0004701470 */
/*01a0*/ @P2 BRA 0x1c0 ; /* 0x0000001000002947 */
/* 0x000fec0003800000 */
/*01b0*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ+-0x80] ; /* 0xffff800002ff7f8c */
/* 0x0001e4000d00403f */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ BSSY B0, 0x210 ; /* 0x0000003000007945 */
/* 0x000fe20003800000 */
/*01e0*/ @P1 BRA 0x200 ; /* 0x0000001000001947 */
/* 0x000fea0003800000 */
/*01f0*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ+-0x100] ; /* 0xffff000002ff7f8c */
/* 0x0003e4000d00403f */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ BSSY B0, 0x250 ; /* 0x0000003000007945 */
/* 0x000fe20003800000 */
/*0220*/ @P0 BRA 0x240 ; /* 0x0000001000000947 */
/* 0x000fea0003800000 */
/*0230*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ+-0x168] ; /* 0xfffe980002ff7f8c */
/* 0x0005e4000d00403f */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD R2, R3, c[0x0][0xc], R0 ; /* 0x0000030003027a24 */
/* 0x007fc800078e0200 */
/*0270*/ IMAD.MOV.U32 R0, RZ, RZ, R2.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0002 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*0290*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*02a0*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06300 */
/*02b0*/ @!P0 BRA 0xc0 ; /* 0xfffffe0000008947 */
/* 0x000fea000383ffff */
/*02c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x001fe20003800000 */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02e0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fe200078e0002 */
/*0300*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e280000004800 */
/*0310*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define NBR 68
__global__ void histo_kernel(unsigned char *buffer,long size, unsigned int *histo){
__shared__ unsigned int temp[68];
int dt = 32;
temp[threadIdx.x]=0;
int i = threadIdx.x + blockIdx.x *blockDim.x;
int offset = blockDim.x *gridDim.x;
while(i<size){
if (buffer[i] >= 32 && buffer[i] < 97)
// histo[buffer[i]-dt]++;
atomicAdd(&temp[buffer[i]-dt],1);
if (buffer[i] >=97 && buffer[i] <= 122)
atomicAdd(&temp[buffer[i] -dt -32],1);
// histo[buffer[i] - dt - 32]++;
if (buffer[i] > 122 && buffer[i] <= 127 )
// histo[buffer[i] - dt - 32 - 26]++;
atomicAdd(&temp[buffer[i]-dt -32-26],1);
i+=offset;
}
__syncthreads();
atomicAdd( &(histo[threadIdx.x]), temp[threadIdx.x] );
}
int main(int argc, char *argv[]){
// unsigned char *buffer = (unsigned char *) big_random_block(SIZE);
if(argc <= 2){
fprintf(stderr, "Arguments non valide");
return 1;
}
/*For file input file and output file*/
FILE *f_input;
FILE *f_output;
/*Will content the number of char in the input file*/
long lSize;
/*will content the file in char format*/
char *buffer;
/*Open the */
f_input = fopen ( argv[1] ,"r" );
f_output = fopen( argv[2],"w");
if( !f_input ) perror(argv[1]),exit(1);
fseek( f_input , 0L , SEEK_END);
lSize = ftell( f_input );
rewind( f_input );
//buffer = calloc( 1, lSize+1 );
buffer =(char*) malloc(lSize);
if( !buffer ) fclose(f_input),fputs("memory alloc fails",stderr),exit(1);
if( 1!=fread( buffer , lSize, 1 , f_input) )
fclose(f_input),free(buffer),fputs("entire read fails",stderr),exit(1);
/*Create event for co;pute running time*/
cudaEvent_t start, stop;
cudaEventCreate( &start );
cudaEventCreate( &stop );
/*Launch event to specify the start of running*/
cudaEventRecord( start, 0);
/*allocate device memory*/
unsigned char *dev_buffer;
unsigned int *dev_histo;
/*Give space in Global memory of GPU to store different variable*/
cudaMalloc( (void**)&dev_buffer, lSize);
/*Copy from CPU Global memory to GPU Global memory*/
cudaMemcpy( dev_buffer, buffer, lSize, cudaMemcpyHostToDevice );
/*Create space for histo variable and initialize at 0 each slopt*/
cudaMalloc( (void**)&dev_histo, NBR * sizeof( long));
cudaMemset( dev_histo, 0, NBR * sizeof( int ));
/*Define of the configuration for kernel running*/
cudaDeviceProp proprieties;
cudaGetDeviceProperties( &proprieties, 0 );
int multiproc = proprieties.multiProcessorCount;
dim3 blocks(multiproc*2,1,1);
dim3 threads(NBR, 1, 1);
histo_kernel<<<blocks,threads>>>( dev_buffer, lSize, dev_histo );
/*Define histo vqriqble and copy on GPU global memory*/
unsigned int histo[NBR];
cudaMemcpy( histo, dev_histo,NBR * sizeof( int ),cudaMemcpyDeviceToHost);
int dt =32;
for(int i =0;i< NBR;i++){
if((i>=0 && i<= 31 && (i+dt != 42) && (i+dt != 36)) || (i>58 && i<=64) )
fprintf(f_output, "%c:%d\n",i+dt,histo[i]);
if(i>31 && i<= 58 )
fprintf(f_output, "%c:%d\n",i+dt+32,histo[i]);
// if(i> 58 && i <=64)
// fprintf(f_output, "%c:%d\n",i+dt,histo[i]);
if(i>64)
fprintf(f_output, "%c:%d\n",i+dt+26,histo[i]);
}
/*Get event at the end of loop*/
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
float elapsedTime;
cudaEventElapsedTime( &elapsedTime, start, stop );
printf( "Time of running : %3.1f ms\n", elapsedTime );
/*Destroy event for running time*/
cudaEventDestroy( start );
cudaEventDestroy( stop );
/*Free memory and close the files**/
cudaFree( dev_histo );
cudaFree( dev_buffer );
fclose(f_input);
fclose(f_output);
free( buffer );
return 0;
} | .file "tmpxft_0004e97e_00000000-6_gpusharedmem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12histo_kernelPhlPjPhlPj
.type _Z35__device_stub__Z12histo_kernelPhlPjPhlPj, @function
_Z35__device_stub__Z12histo_kernelPhlPjPhlPj:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12histo_kernelPhlPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z12histo_kernelPhlPjPhlPj, .-_Z35__device_stub__Z12histo_kernelPhlPjPhlPj
.globl _Z12histo_kernelPhlPj
.type _Z12histo_kernelPhlPj, @function
_Z12histo_kernelPhlPj:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12histo_kernelPhlPjPhlPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12histo_kernelPhlPj, .-_Z12histo_kernelPhlPj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Arguments non valide"
.LC1:
.string "r"
.LC2:
.string "w"
.LC3:
.string "memory alloc fails"
.LC4:
.string "entire read fails"
.LC5:
.string "%c:%d\n"
.LC6:
.string "Time of running : %3.1f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1384, %rsp
.cfi_def_cfa_offset 1440
movq %fs:40, %rax
movq %rax, 1368(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jle .L30
movq %rsi, %rbx
movq 8(%rsi), %rdi
leaq .LC1(%rip), %rsi
call fopen@PLT
movq %rax, %r14
movq 16(%rbx), %rdi
leaq .LC2(%rip), %rsi
call fopen@PLT
movq %rax, %r12
testq %r14, %r14
je .L31
movl $2, %edx
movl $0, %esi
movq %r14, %rdi
call fseek@PLT
movq %r14, %rdi
call ftell@PLT
movq %rax, %rbx
movq %r14, %rdi
call rewind@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
testq %rax, %rax
je .L32
movq %r14, %r8
movl $1, %ecx
movq %rbx, %rdx
movq %rbx, %rsi
movq %rax, %rdi
call __fread_chk@PLT
cmpq $1, %rax
jne .L33
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $544, %esi
call cudaMalloc@PLT
movl $272, %edx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
leaq 336(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 724(%rsp), %eax
addl %eax, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $68, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L17:
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $272, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC5(%rip), %r13
jmp .L26
.L30:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L11
.L31:
movq 8(%rbx), %rdi
call perror@PLT
movl $1, %edi
call exit@PLT
.L32:
movq %r14, %rdi
call fclose@PLT
movq stderr(%rip), %rcx
movl $18, %edx
movl $1, %esi
leaq .LC3(%rip), %rdi
call fwrite@PLT
movl $1, %edi
call exit@PLT
.L33:
movq %r14, %rdi
call fclose@PLT
movq %r15, %rdi
call free@PLT
movq stderr(%rip), %rcx
movl $17, %edx
movl $1, %esi
leaq .LC4(%rip), %rdi
call fwrite@PLT
movl $1, %edi
call exit@PLT
.L34:
movq 32(%rsp), %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z12histo_kernelPhlPjPhlPj
jmp .L17
.L18:
leal -59(%rbx), %eax
cmpl $5, %eax
jbe .L19
leal -32(%rbx), %eax
cmpl $26, %eax
jbe .L35
.L23:
cmpl $64, %ebx
jg .L36
.L24:
addq $1, %rbx
.L26:
movl %ebx, %ebp
cmpl $31, %ebx
ja .L18
cmpl $4, %ebx
je .L23
cmpl $10, %ebx
je .L23
.L19:
leal 32(%rbp), %ecx
movl 64(%rsp,%rbx,4), %r8d
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L23
.L35:
leal 64(%rbx), %ecx
movl 64(%rsp,%rbx,4), %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L24
.L36:
leal 58(%rbp), %ecx
movl 64(%rsp,%rbx,4), %r8d
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq $68, %rbx
jne .L26
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call fclose@PLT
movq %r12, %rdi
call fclose@PLT
movq %r15, %rdi
call free@PLT
movl $0, %eax
.L11:
movq 1368(%rsp), %rdx
subq %fs:40, %rdx
jne .L37
addq $1384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12histo_kernelPhlPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12histo_kernelPhlPj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define NBR 68
__global__ void histo_kernel(unsigned char *buffer,long size, unsigned int *histo){
__shared__ unsigned int temp[68];
int dt = 32;
temp[threadIdx.x]=0;
int i = threadIdx.x + blockIdx.x *blockDim.x;
int offset = blockDim.x *gridDim.x;
while(i<size){
if (buffer[i] >= 32 && buffer[i] < 97)
// histo[buffer[i]-dt]++;
atomicAdd(&temp[buffer[i]-dt],1);
if (buffer[i] >=97 && buffer[i] <= 122)
atomicAdd(&temp[buffer[i] -dt -32],1);
// histo[buffer[i] - dt - 32]++;
if (buffer[i] > 122 && buffer[i] <= 127 )
// histo[buffer[i] - dt - 32 - 26]++;
atomicAdd(&temp[buffer[i]-dt -32-26],1);
i+=offset;
}
__syncthreads();
atomicAdd( &(histo[threadIdx.x]), temp[threadIdx.x] );
}
int main(int argc, char *argv[]){
// unsigned char *buffer = (unsigned char *) big_random_block(SIZE);
if(argc <= 2){
fprintf(stderr, "Arguments non valide");
return 1;
}
/*For file input file and output file*/
FILE *f_input;
FILE *f_output;
/*Will content the number of char in the input file*/
long lSize;
/*will content the file in char format*/
char *buffer;
/*Open the */
f_input = fopen ( argv[1] ,"r" );
f_output = fopen( argv[2],"w");
if( !f_input ) perror(argv[1]),exit(1);
fseek( f_input , 0L , SEEK_END);
lSize = ftell( f_input );
rewind( f_input );
//buffer = calloc( 1, lSize+1 );
buffer =(char*) malloc(lSize);
if( !buffer ) fclose(f_input),fputs("memory alloc fails",stderr),exit(1);
if( 1!=fread( buffer , lSize, 1 , f_input) )
fclose(f_input),free(buffer),fputs("entire read fails",stderr),exit(1);
/*Create event for co;pute running time*/
cudaEvent_t start, stop;
cudaEventCreate( &start );
cudaEventCreate( &stop );
/*Launch event to specify the start of running*/
cudaEventRecord( start, 0);
/*allocate device memory*/
unsigned char *dev_buffer;
unsigned int *dev_histo;
/*Give space in Global memory of GPU to store different variable*/
cudaMalloc( (void**)&dev_buffer, lSize);
/*Copy from CPU Global memory to GPU Global memory*/
cudaMemcpy( dev_buffer, buffer, lSize, cudaMemcpyHostToDevice );
/*Create space for histo variable and initialize at 0 each slopt*/
cudaMalloc( (void**)&dev_histo, NBR * sizeof( long));
cudaMemset( dev_histo, 0, NBR * sizeof( int ));
/*Define of the configuration for kernel running*/
cudaDeviceProp proprieties;
cudaGetDeviceProperties( &proprieties, 0 );
int multiproc = proprieties.multiProcessorCount;
dim3 blocks(multiproc*2,1,1);
dim3 threads(NBR, 1, 1);
histo_kernel<<<blocks,threads>>>( dev_buffer, lSize, dev_histo );
/*Define histo vqriqble and copy on GPU global memory*/
unsigned int histo[NBR];
cudaMemcpy( histo, dev_histo,NBR * sizeof( int ),cudaMemcpyDeviceToHost);
int dt =32;
for(int i =0;i< NBR;i++){
if((i>=0 && i<= 31 && (i+dt != 42) && (i+dt != 36)) || (i>58 && i<=64) )
fprintf(f_output, "%c:%d\n",i+dt,histo[i]);
if(i>31 && i<= 58 )
fprintf(f_output, "%c:%d\n",i+dt+32,histo[i]);
// if(i> 58 && i <=64)
// fprintf(f_output, "%c:%d\n",i+dt,histo[i]);
if(i>64)
fprintf(f_output, "%c:%d\n",i+dt+26,histo[i]);
}
/*Get event at the end of loop*/
cudaEventRecord( stop, 0 );
cudaEventSynchronize( stop );
float elapsedTime;
cudaEventElapsedTime( &elapsedTime, start, stop );
printf( "Time of running : %3.1f ms\n", elapsedTime );
/*Destroy event for running time*/
cudaEventDestroy( start );
cudaEventDestroy( stop );
/*Free memory and close the files**/
cudaFree( dev_histo );
cudaFree( dev_buffer );
fclose(f_input);
fclose(f_output);
free( buffer );
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define NBR 68
__global__ void histo_kernel(unsigned char *buffer,long size, unsigned int *histo){
__shared__ unsigned int temp[68];
int dt = 32;
temp[threadIdx.x]=0;
int i = threadIdx.x + blockIdx.x *blockDim.x;
int offset = blockDim.x *gridDim.x;
while(i<size){
if (buffer[i] >= 32 && buffer[i] < 97)
// histo[buffer[i]-dt]++;
atomicAdd(&temp[buffer[i]-dt],1);
if (buffer[i] >=97 && buffer[i] <= 122)
atomicAdd(&temp[buffer[i] -dt -32],1);
// histo[buffer[i] - dt - 32]++;
if (buffer[i] > 122 && buffer[i] <= 127 )
// histo[buffer[i] - dt - 32 - 26]++;
atomicAdd(&temp[buffer[i]-dt -32-26],1);
i+=offset;
}
__syncthreads();
atomicAdd( &(histo[threadIdx.x]), temp[threadIdx.x] );
}
int main(int argc, char *argv[]){
// unsigned char *buffer = (unsigned char *) big_random_block(SIZE);
if(argc <= 2){
fprintf(stderr, "Arguments non valide");
return 1;
}
/*For file input file and output file*/
FILE *f_input;
FILE *f_output;
/*Will content the number of char in the input file*/
long lSize;
/*will content the file in char format*/
char *buffer;
/*Open the */
f_input = fopen ( argv[1] ,"r" );
f_output = fopen( argv[2],"w");
if( !f_input ) perror(argv[1]),exit(1);
fseek( f_input , 0L , SEEK_END);
lSize = ftell( f_input );
rewind( f_input );
//buffer = calloc( 1, lSize+1 );
buffer =(char*) malloc(lSize);
if( !buffer ) fclose(f_input),fputs("memory alloc fails",stderr),exit(1);
if( 1!=fread( buffer , lSize, 1 , f_input) )
fclose(f_input),free(buffer),fputs("entire read fails",stderr),exit(1);
/*Create event for co;pute running time*/
hipEvent_t start, stop;
hipEventCreate( &start );
hipEventCreate( &stop );
/*Launch event to specify the start of running*/
hipEventRecord( start, 0);
/*allocate device memory*/
unsigned char *dev_buffer;
unsigned int *dev_histo;
/*Give space in Global memory of GPU to store different variable*/
hipMalloc( (void**)&dev_buffer, lSize);
/*Copy from CPU Global memory to GPU Global memory*/
hipMemcpy( dev_buffer, buffer, lSize, hipMemcpyHostToDevice );
/*Create space for histo variable and initialize at 0 each slopt*/
hipMalloc( (void**)&dev_histo, NBR * sizeof( long));
hipMemset( dev_histo, 0, NBR * sizeof( int ));
/*Define of the configuration for kernel running*/
hipDeviceProp_t proprieties;
hipGetDeviceProperties( &proprieties, 0 );
int multiproc = proprieties.multiProcessorCount;
dim3 blocks(multiproc*2,1,1);
dim3 threads(NBR, 1, 1);
histo_kernel<<<blocks,threads>>>( dev_buffer, lSize, dev_histo );
/*Define histo vqriqble and copy on GPU global memory*/
unsigned int histo[NBR];
hipMemcpy( histo, dev_histo,NBR * sizeof( int ),hipMemcpyDeviceToHost);
int dt =32;
for(int i =0;i< NBR;i++){
if((i>=0 && i<= 31 && (i+dt != 42) && (i+dt != 36)) || (i>58 && i<=64) )
fprintf(f_output, "%c:%d\n",i+dt,histo[i]);
if(i>31 && i<= 58 )
fprintf(f_output, "%c:%d\n",i+dt+32,histo[i]);
// if(i> 58 && i <=64)
// fprintf(f_output, "%c:%d\n",i+dt,histo[i]);
if(i>64)
fprintf(f_output, "%c:%d\n",i+dt+26,histo[i]);
}
/*Get event at the end of loop*/
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
float elapsedTime;
hipEventElapsedTime( &elapsedTime, start, stop );
printf( "Time of running : %3.1f ms\n", elapsedTime );
/*Destroy event for running time*/
hipEventDestroy( start );
hipEventDestroy( stop );
/*Free memory and close the files**/
hipFree( dev_histo );
hipFree( dev_buffer );
fclose(f_input);
fclose(f_output);
free( buffer );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define NBR 68
__global__ void histo_kernel(unsigned char *buffer,long size, unsigned int *histo){
__shared__ unsigned int temp[68];
int dt = 32;
temp[threadIdx.x]=0;
int i = threadIdx.x + blockIdx.x *blockDim.x;
int offset = blockDim.x *gridDim.x;
while(i<size){
if (buffer[i] >= 32 && buffer[i] < 97)
// histo[buffer[i]-dt]++;
atomicAdd(&temp[buffer[i]-dt],1);
if (buffer[i] >=97 && buffer[i] <= 122)
atomicAdd(&temp[buffer[i] -dt -32],1);
// histo[buffer[i] - dt - 32]++;
if (buffer[i] > 122 && buffer[i] <= 127 )
// histo[buffer[i] - dt - 32 - 26]++;
atomicAdd(&temp[buffer[i]-dt -32-26],1);
i+=offset;
}
__syncthreads();
atomicAdd( &(histo[threadIdx.x]), temp[threadIdx.x] );
}
int main(int argc, char *argv[]){
// unsigned char *buffer = (unsigned char *) big_random_block(SIZE);
if(argc <= 2){
fprintf(stderr, "Arguments non valide");
return 1;
}
/*For file input file and output file*/
FILE *f_input;
FILE *f_output;
/*Will content the number of char in the input file*/
long lSize;
/*will content the file in char format*/
char *buffer;
/*Open the */
f_input = fopen ( argv[1] ,"r" );
f_output = fopen( argv[2],"w");
if( !f_input ) perror(argv[1]),exit(1);
fseek( f_input , 0L , SEEK_END);
lSize = ftell( f_input );
rewind( f_input );
//buffer = calloc( 1, lSize+1 );
buffer =(char*) malloc(lSize);
if( !buffer ) fclose(f_input),fputs("memory alloc fails",stderr),exit(1);
if( 1!=fread( buffer , lSize, 1 , f_input) )
fclose(f_input),free(buffer),fputs("entire read fails",stderr),exit(1);
/*Create event for co;pute running time*/
hipEvent_t start, stop;
hipEventCreate( &start );
hipEventCreate( &stop );
/*Launch event to specify the start of running*/
hipEventRecord( start, 0);
/*allocate device memory*/
unsigned char *dev_buffer;
unsigned int *dev_histo;
/*Give space in Global memory of GPU to store different variable*/
hipMalloc( (void**)&dev_buffer, lSize);
/*Copy from CPU Global memory to GPU Global memory*/
hipMemcpy( dev_buffer, buffer, lSize, hipMemcpyHostToDevice );
/*Create space for histo variable and initialize at 0 each slopt*/
hipMalloc( (void**)&dev_histo, NBR * sizeof( long));
hipMemset( dev_histo, 0, NBR * sizeof( int ));
/*Define of the configuration for kernel running*/
hipDeviceProp_t proprieties;
hipGetDeviceProperties( &proprieties, 0 );
int multiproc = proprieties.multiProcessorCount;
dim3 blocks(multiproc*2,1,1);
dim3 threads(NBR, 1, 1);
histo_kernel<<<blocks,threads>>>( dev_buffer, lSize, dev_histo );
/*Define histo vqriqble and copy on GPU global memory*/
unsigned int histo[NBR];
hipMemcpy( histo, dev_histo,NBR * sizeof( int ),hipMemcpyDeviceToHost);
int dt =32;
for(int i =0;i< NBR;i++){
if((i>=0 && i<= 31 && (i+dt != 42) && (i+dt != 36)) || (i>58 && i<=64) )
fprintf(f_output, "%c:%d\n",i+dt,histo[i]);
if(i>31 && i<= 58 )
fprintf(f_output, "%c:%d\n",i+dt+32,histo[i]);
// if(i> 58 && i <=64)
// fprintf(f_output, "%c:%d\n",i+dt,histo[i]);
if(i>64)
fprintf(f_output, "%c:%d\n",i+dt+26,histo[i]);
}
/*Get event at the end of loop*/
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
float elapsedTime;
hipEventElapsedTime( &elapsedTime, start, stop );
printf( "Time of running : %3.1f ms\n", elapsedTime );
/*Destroy event for running time*/
hipEventDestroy( start );
hipEventDestroy( stop );
/*Free memory and close the files**/
hipFree( dev_histo );
hipFree( dev_buffer );
fclose(f_input);
fclose(f_output);
free( buffer );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12histo_kernelPhlPj
.globl _Z12histo_kernelPhlPj
.p2align 8
.type _Z12histo_kernelPhlPj,@function
_Z12histo_kernelPhlPj:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 2, v0
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_9
s_load_b32 s8, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v4, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s8, s7
s_mov_b32 s8, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v1, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_le_i64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_9
.LBB0_3:
v_add_co_u32 v5, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
s_mov_b32 s9, exec_lo
global_load_i8 v2, v[5:6], off
s_waitcnt vmcnt(0)
v_sub_nc_u16 v5, v2, 32
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, 0xff, v5
v_cmpx_gt_u16_e32 0x41, v5
s_cbranch_execz .LBB0_5
v_and_b32_e32 v5, 0xff, v2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, v5, 2, 0xffffff80
ds_add_u32 v5, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u16 v5, v2, 0xff9f
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, 0xff, v5
v_cmpx_gt_u16_e32 26, v5
s_cbranch_execz .LBB0_7
v_and_b32_e32 v5, 63, v2
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v5, 2, v5
ds_add_u32 v5, v4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s9, exec_lo
v_cmpx_lt_i16_e32 0x7a, v2
s_cbranch_execz .LBB0_2
v_and_b32_e32 v2, 0xff, v2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0xfffffe98
ds_add_u32 v2, v4
s_branch .LBB0_2
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v3
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12histo_kernelPhlPj
.amdhsa_group_segment_fixed_size 272
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12histo_kernelPhlPj, .Lfunc_end0-_Z12histo_kernelPhlPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 272
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12histo_kernelPhlPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12histo_kernelPhlPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define NBR 68
__global__ void histo_kernel(unsigned char *buffer,long size, unsigned int *histo){
__shared__ unsigned int temp[68];
int dt = 32;
temp[threadIdx.x]=0;
int i = threadIdx.x + blockIdx.x *blockDim.x;
int offset = blockDim.x *gridDim.x;
while(i<size){
if (buffer[i] >= 32 && buffer[i] < 97)
// histo[buffer[i]-dt]++;
atomicAdd(&temp[buffer[i]-dt],1);
if (buffer[i] >=97 && buffer[i] <= 122)
atomicAdd(&temp[buffer[i] -dt -32],1);
// histo[buffer[i] - dt - 32]++;
if (buffer[i] > 122 && buffer[i] <= 127 )
// histo[buffer[i] - dt - 32 - 26]++;
atomicAdd(&temp[buffer[i]-dt -32-26],1);
i+=offset;
}
__syncthreads();
atomicAdd( &(histo[threadIdx.x]), temp[threadIdx.x] );
}
int main(int argc, char *argv[]){
// unsigned char *buffer = (unsigned char *) big_random_block(SIZE);
if(argc <= 2){
fprintf(stderr, "Arguments non valide");
return 1;
}
/*For file input file and output file*/
FILE *f_input;
FILE *f_output;
/*Will content the number of char in the input file*/
long lSize;
/*will content the file in char format*/
char *buffer;
/*Open the */
f_input = fopen ( argv[1] ,"r" );
f_output = fopen( argv[2],"w");
if( !f_input ) perror(argv[1]),exit(1);
fseek( f_input , 0L , SEEK_END);
lSize = ftell( f_input );
rewind( f_input );
//buffer = calloc( 1, lSize+1 );
buffer =(char*) malloc(lSize);
if( !buffer ) fclose(f_input),fputs("memory alloc fails",stderr),exit(1);
if( 1!=fread( buffer , lSize, 1 , f_input) )
fclose(f_input),free(buffer),fputs("entire read fails",stderr),exit(1);
/*Create event for co;pute running time*/
hipEvent_t start, stop;
hipEventCreate( &start );
hipEventCreate( &stop );
/*Launch event to specify the start of running*/
hipEventRecord( start, 0);
/*allocate device memory*/
unsigned char *dev_buffer;
unsigned int *dev_histo;
/*Give space in Global memory of GPU to store different variable*/
hipMalloc( (void**)&dev_buffer, lSize);
/*Copy from CPU Global memory to GPU Global memory*/
hipMemcpy( dev_buffer, buffer, lSize, hipMemcpyHostToDevice );
/*Create space for histo variable and initialize at 0 each slopt*/
hipMalloc( (void**)&dev_histo, NBR * sizeof( long));
hipMemset( dev_histo, 0, NBR * sizeof( int ));
/*Define of the configuration for kernel running*/
hipDeviceProp_t proprieties;
hipGetDeviceProperties( &proprieties, 0 );
int multiproc = proprieties.multiProcessorCount;
dim3 blocks(multiproc*2,1,1);
dim3 threads(NBR, 1, 1);
histo_kernel<<<blocks,threads>>>( dev_buffer, lSize, dev_histo );
/*Define histo vqriqble and copy on GPU global memory*/
unsigned int histo[NBR];
hipMemcpy( histo, dev_histo,NBR * sizeof( int ),hipMemcpyDeviceToHost);
int dt =32;
for(int i =0;i< NBR;i++){
if((i>=0 && i<= 31 && (i+dt != 42) && (i+dt != 36)) || (i>58 && i<=64) )
fprintf(f_output, "%c:%d\n",i+dt,histo[i]);
if(i>31 && i<= 58 )
fprintf(f_output, "%c:%d\n",i+dt+32,histo[i]);
// if(i> 58 && i <=64)
// fprintf(f_output, "%c:%d\n",i+dt,histo[i]);
if(i>64)
fprintf(f_output, "%c:%d\n",i+dt+26,histo[i]);
}
/*Get event at the end of loop*/
hipEventRecord( stop, 0 );
hipEventSynchronize( stop );
float elapsedTime;
hipEventElapsedTime( &elapsedTime, start, stop );
printf( "Time of running : %3.1f ms\n", elapsedTime );
/*Destroy event for running time*/
hipEventDestroy( start );
hipEventDestroy( stop );
/*Free memory and close the files**/
hipFree( dev_histo );
hipFree( dev_buffer );
fclose(f_input);
fclose(f_output);
free( buffer );
return 0;
} | .text
.file "gpusharedmem.hip"
.globl _Z27__device_stub__histo_kernelPhlPj # -- Begin function _Z27__device_stub__histo_kernelPhlPj
.p2align 4, 0x90
.type _Z27__device_stub__histo_kernelPhlPj,@function
_Z27__device_stub__histo_kernelPhlPj: # @_Z27__device_stub__histo_kernelPhlPj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12histo_kernelPhlPj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__histo_kernelPhlPj, .Lfunc_end0-_Z27__device_stub__histo_kernelPhlPj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1864, %rsp # imm = 0x748
.cfi_def_cfa_offset 1904
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $2, %edi
jle .LBB1_1
# %bb.2:
movq %rsi, %r15
movq 8(%rsi), %rdi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movq 16(%r15), %rdi
movl $.L.str.2, %esi
callq fopen
testq %rbx, %rbx
je .LBB1_23
# %bb.3:
movq %rax, %r14
movq %rbx, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %rbx, %rdi
callq ftell
movq %rax, %r12
movq %rbx, %rdi
callq rewind
movq %r12, %rdi
callq malloc
testq %rax, %rax
je .LBB1_4
# %bb.6:
movq %rax, %r15
movl $1, %edx
movq %rax, %rdi
movq %r12, %rsi
movq %rbx, %rcx
callq fread
cmpq $1, %rax
jne .LBB1_7
# %bb.8:
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $544, %esi # imm = 0x220
callq hipMalloc
movq 8(%rsp), %rdi
movl $272, %edx # imm = 0x110
xorl %esi, %esi
callq hipMemset
leaq 392(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 780(%rsp), %edi
addl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $68, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movq %r12, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12histo_kernelPhlPj, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $272, %edx # imm = 0x110
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_11 Depth=1
incq %r12
cmpq $68, %r12
je .LBB1_21
.LBB1_11: # =>This Inner Loop Header: Depth=1
cmpq $31, %r12
ja .LBB1_14
# %bb.12: # in Loop: Header=BB1_11 Depth=1
leal 32(%r12), %eax
cmpl $42, %eax
je .LBB1_14
# %bb.13: # in Loop: Header=BB1_11 Depth=1
cmpl $36, %eax
jne .LBB1_15
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_11 Depth=1
leal -59(%r12), %eax
cmpl $5, %eax
ja .LBB1_16
.LBB1_15: # in Loop: Header=BB1_11 Depth=1
movl 112(%rsp,%r12,4), %ecx
leal 32(%r12), %edx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
.LBB1_16: # in Loop: Header=BB1_11 Depth=1
leal -32(%r12), %eax
cmpl $26, %eax
ja .LBB1_18
# %bb.17: # in Loop: Header=BB1_11 Depth=1
movl 112(%rsp,%r12,4), %ecx
movl %r12d, %edx
orl $64, %edx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
.LBB1_18: # in Loop: Header=BB1_11 Depth=1
cmpq $65, %r12
jb .LBB1_20
# %bb.19: # in Loop: Header=BB1_11 Depth=1
movl 112(%rsp,%r12,4), %ecx
leal 58(%r12), %edx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
jmp .LBB1_20
.LBB1_21:
movq 16(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq fclose
movq %r14, %rdi
callq fclose
movq %r15, %rdi
callq free
.LBB1_22:
movl %r12d, %eax
addq $1864, %rsp # imm = 0x748
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 1904
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $20, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %r12d
jmp .LBB1_22
.LBB1_23:
movq 8(%r15), %rdi
callq perror
movl $1, %edi
callq exit
.LBB1_4:
movq %rbx, %rdi
callq fclose
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $18, %esi
jmp .LBB1_5
.LBB1_7:
movq %rbx, %rdi
callq fclose
movq %r15, %rdi
callq free
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $17, %esi
.LBB1_5:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12histo_kernelPhlPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12histo_kernelPhlPj,@object # @_Z12histo_kernelPhlPj
.section .rodata,"a",@progbits
.globl _Z12histo_kernelPhlPj
.p2align 3, 0x0
_Z12histo_kernelPhlPj:
.quad _Z27__device_stub__histo_kernelPhlPj
.size _Z12histo_kernelPhlPj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Arguments non valide"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "w"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "memory alloc fails"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "entire read fails"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%c:%d\n"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time of running : %3.1f ms\n"
.size .L.str.6, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12histo_kernelPhlPj"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__histo_kernelPhlPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12histo_kernelPhlPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12histo_kernelPhlPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ STS [R7.X4], RZ ; /* 0x000000ff07007388 */
/* 0x0011e20000004800 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0207 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0070*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0080*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06300 */
/*0090*/ @P0 BRA 0x2c0 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff037224 */
/* 0x001fe400078e0002 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0000 */
/*00c0*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R3, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fca00007fe4ff */
/*00e0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0100*/ BSSY B0, 0x1d0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0110*/ IADD3 R4, R2.reuse, -0x20, RZ ; /* 0xffffffe002047810 */
/* 0x044fe40007ffe0ff */
/*0120*/ PRMT R6, R2, 0x8880, RZ ; /* 0x0000888002067816 */
/* 0x000fe400000000ff */
/*0130*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*0140*/ IADD3 R5, R2, -0x61, RZ ; /* 0xffffff9f02057810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GT.U32.AND P2, PT, R4, 0x40, PT ; /* 0x000000400400780c */
/* 0x000fc40003f44070 */
/*0160*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0170*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f06270 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R5, 0x19, PT ; /* 0x000000190500780c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.LT.U32.OR P0, PT, R2, 0x7b, !P0 ; /* 0x0000007b0200780c */
/* 0x000fca0004701470 */
/*01a0*/ @P2 BRA 0x1c0 ; /* 0x0000001000002947 */
/* 0x000fec0003800000 */
/*01b0*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ+-0x80] ; /* 0xffff800002ff7f8c */
/* 0x0001e4000d00403f */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ BSSY B0, 0x210 ; /* 0x0000003000007945 */
/* 0x000fe20003800000 */
/*01e0*/ @P1 BRA 0x200 ; /* 0x0000001000001947 */
/* 0x000fea0003800000 */
/*01f0*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ+-0x100] ; /* 0xffff000002ff7f8c */
/* 0x0003e4000d00403f */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ BSSY B0, 0x250 ; /* 0x0000003000007945 */
/* 0x000fe20003800000 */
/*0220*/ @P0 BRA 0x240 ; /* 0x0000001000000947 */
/* 0x000fea0003800000 */
/*0230*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ+-0x168] ; /* 0xfffe980002ff7f8c */
/* 0x0005e4000d00403f */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD R2, R3, c[0x0][0xc], R0 ; /* 0x0000030003027a24 */
/* 0x007fc800078e0200 */
/*0270*/ IMAD.MOV.U32 R0, RZ, RZ, R2.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0002 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe40003f06070 */
/*0290*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*02a0*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06300 */
/*02b0*/ @!P0 BRA 0xc0 ; /* 0xfffffe0000008947 */
/* 0x000fea000383ffff */
/*02c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x001fe20003800000 */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02e0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fe200078e0002 */
/*0300*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e280000004800 */
/*0310*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12histo_kernelPhlPj
.globl _Z12histo_kernelPhlPj
.p2align 8
.type _Z12histo_kernelPhlPj,@function
_Z12histo_kernelPhlPj:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 2, v0
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_9
s_load_b32 s8, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v4, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s8, s7
s_mov_b32 s8, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v1, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_le_i64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_9
.LBB0_3:
v_add_co_u32 v5, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
s_mov_b32 s9, exec_lo
global_load_i8 v2, v[5:6], off
s_waitcnt vmcnt(0)
v_sub_nc_u16 v5, v2, 32
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, 0xff, v5
v_cmpx_gt_u16_e32 0x41, v5
s_cbranch_execz .LBB0_5
v_and_b32_e32 v5, 0xff, v2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, v5, 2, 0xffffff80
ds_add_u32 v5, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u16 v5, v2, 0xff9f
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, 0xff, v5
v_cmpx_gt_u16_e32 26, v5
s_cbranch_execz .LBB0_7
v_and_b32_e32 v5, 63, v2
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v5, 2, v5
ds_add_u32 v5, v4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s9, exec_lo
v_cmpx_lt_i16_e32 0x7a, v2
s_cbranch_execz .LBB0_2
v_and_b32_e32 v2, 0xff, v2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0xfffffe98
ds_add_u32 v2, v4
s_branch .LBB0_2
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v3
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12histo_kernelPhlPj
.amdhsa_group_segment_fixed_size 272
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12histo_kernelPhlPj, .Lfunc_end0-_Z12histo_kernelPhlPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 272
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12histo_kernelPhlPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12histo_kernelPhlPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004e97e_00000000-6_gpusharedmem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12histo_kernelPhlPjPhlPj
.type _Z35__device_stub__Z12histo_kernelPhlPjPhlPj, @function
_Z35__device_stub__Z12histo_kernelPhlPjPhlPj:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12histo_kernelPhlPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z12histo_kernelPhlPjPhlPj, .-_Z35__device_stub__Z12histo_kernelPhlPjPhlPj
.globl _Z12histo_kernelPhlPj
.type _Z12histo_kernelPhlPj, @function
_Z12histo_kernelPhlPj:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12histo_kernelPhlPjPhlPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12histo_kernelPhlPj, .-_Z12histo_kernelPhlPj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Arguments non valide"
.LC1:
.string "r"
.LC2:
.string "w"
.LC3:
.string "memory alloc fails"
.LC4:
.string "entire read fails"
.LC5:
.string "%c:%d\n"
.LC6:
.string "Time of running : %3.1f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1384, %rsp
.cfi_def_cfa_offset 1440
movq %fs:40, %rax
movq %rax, 1368(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jle .L30
movq %rsi, %rbx
movq 8(%rsi), %rdi
leaq .LC1(%rip), %rsi
call fopen@PLT
movq %rax, %r14
movq 16(%rbx), %rdi
leaq .LC2(%rip), %rsi
call fopen@PLT
movq %rax, %r12
testq %r14, %r14
je .L31
movl $2, %edx
movl $0, %esi
movq %r14, %rdi
call fseek@PLT
movq %r14, %rdi
call ftell@PLT
movq %rax, %rbx
movq %r14, %rdi
call rewind@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
testq %rax, %rax
je .L32
movq %r14, %r8
movl $1, %ecx
movq %rbx, %rdx
movq %rbx, %rsi
movq %rax, %rdi
call __fread_chk@PLT
cmpq $1, %rax
jne .L33
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movl $544, %esi
call cudaMalloc@PLT
movl $272, %edx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
leaq 336(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 724(%rsp), %eax
addl %eax, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $68, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L17:
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $272, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC5(%rip), %r13
jmp .L26
.L30:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L11
.L31:
movq 8(%rbx), %rdi
call perror@PLT
movl $1, %edi
call exit@PLT
.L32:
movq %r14, %rdi
call fclose@PLT
movq stderr(%rip), %rcx
movl $18, %edx
movl $1, %esi
leaq .LC3(%rip), %rdi
call fwrite@PLT
movl $1, %edi
call exit@PLT
.L33:
movq %r14, %rdi
call fclose@PLT
movq %r15, %rdi
call free@PLT
movq stderr(%rip), %rcx
movl $17, %edx
movl $1, %esi
leaq .LC4(%rip), %rdi
call fwrite@PLT
movl $1, %edi
call exit@PLT
.L34:
movq 32(%rsp), %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z12histo_kernelPhlPjPhlPj
jmp .L17
.L18:
leal -59(%rbx), %eax
cmpl $5, %eax
jbe .L19
leal -32(%rbx), %eax
cmpl $26, %eax
jbe .L35
.L23:
cmpl $64, %ebx
jg .L36
.L24:
addq $1, %rbx
.L26:
movl %ebx, %ebp
cmpl $31, %ebx
ja .L18
cmpl $4, %ebx
je .L23
cmpl $10, %ebx
je .L23
.L19:
leal 32(%rbp), %ecx
movl 64(%rsp,%rbx,4), %r8d
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L23
.L35:
leal 64(%rbx), %ecx
movl 64(%rsp,%rbx,4), %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L24
.L36:
leal 58(%rbp), %ecx
movl 64(%rsp,%rbx,4), %r8d
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq $68, %rbx
jne .L26
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call fclose@PLT
movq %r12, %rdi
call fclose@PLT
movq %r15, %rdi
call free@PLT
movl $0, %eax
.L11:
movq 1368(%rsp), %rdx
subq %fs:40, %rdx
jne .L37
addq $1384, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12histo_kernelPhlPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12histo_kernelPhlPj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpusharedmem.hip"
.globl _Z27__device_stub__histo_kernelPhlPj # -- Begin function _Z27__device_stub__histo_kernelPhlPj
.p2align 4, 0x90
.type _Z27__device_stub__histo_kernelPhlPj,@function
_Z27__device_stub__histo_kernelPhlPj: # @_Z27__device_stub__histo_kernelPhlPj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12histo_kernelPhlPj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__histo_kernelPhlPj, .Lfunc_end0-_Z27__device_stub__histo_kernelPhlPj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1864, %rsp # imm = 0x748
.cfi_def_cfa_offset 1904
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $2, %edi
jle .LBB1_1
# %bb.2:
movq %rsi, %r15
movq 8(%rsi), %rdi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movq 16(%r15), %rdi
movl $.L.str.2, %esi
callq fopen
testq %rbx, %rbx
je .LBB1_23
# %bb.3:
movq %rax, %r14
movq %rbx, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %rbx, %rdi
callq ftell
movq %rax, %r12
movq %rbx, %rdi
callq rewind
movq %r12, %rdi
callq malloc
testq %rax, %rax
je .LBB1_4
# %bb.6:
movq %rax, %r15
movl $1, %edx
movq %rax, %rdi
movq %r12, %rsi
movq %rbx, %rcx
callq fread
cmpq $1, %rax
jne .LBB1_7
# %bb.8:
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $544, %esi # imm = 0x220
callq hipMalloc
movq 8(%rsp), %rdi
movl $272, %edx # imm = 0x110
xorl %esi, %esi
callq hipMemset
leaq 392(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 780(%rsp), %edi
addl %edi, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $68, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movq %r12, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12histo_kernelPhlPj, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $272, %edx # imm = 0x110
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_11 Depth=1
incq %r12
cmpq $68, %r12
je .LBB1_21
.LBB1_11: # =>This Inner Loop Header: Depth=1
cmpq $31, %r12
ja .LBB1_14
# %bb.12: # in Loop: Header=BB1_11 Depth=1
leal 32(%r12), %eax
cmpl $42, %eax
je .LBB1_14
# %bb.13: # in Loop: Header=BB1_11 Depth=1
cmpl $36, %eax
jne .LBB1_15
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_11 Depth=1
leal -59(%r12), %eax
cmpl $5, %eax
ja .LBB1_16
.LBB1_15: # in Loop: Header=BB1_11 Depth=1
movl 112(%rsp,%r12,4), %ecx
leal 32(%r12), %edx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
.LBB1_16: # in Loop: Header=BB1_11 Depth=1
leal -32(%r12), %eax
cmpl $26, %eax
ja .LBB1_18
# %bb.17: # in Loop: Header=BB1_11 Depth=1
movl 112(%rsp,%r12,4), %ecx
movl %r12d, %edx
orl $64, %edx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
.LBB1_18: # in Loop: Header=BB1_11 Depth=1
cmpq $65, %r12
jb .LBB1_20
# %bb.19: # in Loop: Header=BB1_11 Depth=1
movl 112(%rsp,%r12,4), %ecx
leal 58(%r12), %edx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
jmp .LBB1_20
.LBB1_21:
movq 16(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq fclose
movq %r14, %rdi
callq fclose
movq %r15, %rdi
callq free
.LBB1_22:
movl %r12d, %eax
addq $1864, %rsp # imm = 0x748
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 1904
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $20, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %r12d
jmp .LBB1_22
.LBB1_23:
movq 8(%r15), %rdi
callq perror
movl $1, %edi
callq exit
.LBB1_4:
movq %rbx, %rdi
callq fclose
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $18, %esi
jmp .LBB1_5
.LBB1_7:
movq %rbx, %rdi
callq fclose
movq %r15, %rdi
callq free
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $17, %esi
.LBB1_5:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12histo_kernelPhlPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12histo_kernelPhlPj,@object # @_Z12histo_kernelPhlPj
.section .rodata,"a",@progbits
.globl _Z12histo_kernelPhlPj
.p2align 3, 0x0
_Z12histo_kernelPhlPj:
.quad _Z27__device_stub__histo_kernelPhlPj
.size _Z12histo_kernelPhlPj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Arguments non valide"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "w"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "memory alloc fails"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "entire read fails"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%c:%d\n"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time of running : %3.1f ms\n"
.size .L.str.6, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12histo_kernelPhlPj"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__histo_kernelPhlPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12histo_kernelPhlPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
// CUDA check error
#define cuda_check_error(msg) \
{ \
cudaError_t err = cudaGetLastError(); \
if( cudaSuccess != err) { \
fprintf(stderr, "[GPUJPEG] [Error] %s (line %i): %s: %s.\n", \
__FILE__, __LINE__, msg, cudaGetErrorString( err) ); \
exit(-1); \
} \
} \
__global__
void get_value(int* index, int* value)
{
int x[3];
for ( int i = 0; i < 3; i++ )
x[i] = 55;
*value = x[*index];
}
int main()
{
int* d_index;
int* d_value;
cudaMalloc((void**)&d_index, sizeof(int));
cudaMalloc((void**)&d_value, sizeof(int));
cuda_check_error("Alloc failed");
int index = 0;
int value = 0;
cudaMemcpy(d_index, &index, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_value, &value, sizeof(int), cudaMemcpyHostToDevice);
cuda_check_error("Init failed");
get_value<<<1, 1>>>(d_index, d_value);
cudaThreadSynchronize();
cuda_check_error("Kernel failed");
cudaMemcpy(&index, d_index, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(&value, d_value, sizeof(int), cudaMemcpyDeviceToHost);
cuda_check_error("Copy failed");
printf("index = %d\n", index);
printf("value = %d\n", value);
return 0;
} | code for sm_80
Function : _Z9get_valuePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.SHL.U32 R0, R2, 0x4, RZ ; /* 0x0000000402007824 */
/* 0x004fca00078e00ff */
/*0080*/ ISETP.EQ.AND P0, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe40003f02270 */
/*0090*/ ISETP.EQ.AND P1, PT, R0.reuse, 0x4, PT ; /* 0x000000040000780c */
/* 0x040fe40003f22270 */
/*00a0*/ ISETP.EQ.AND P2, PT, R0, 0x8, PT ; /* 0x000000080000780c */
/* 0x000fd20003f42270 */
/*00b0*/ @P0 MOV R0, 0x37 ; /* 0x0000003700000802 */
/* 0x000fe40000000f00 */
/*00c0*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, 0x37 ; /* 0x00000037ff001424 */
/* 0x000fe400078e00ff */
/*00d0*/ @P2 MOV R0, 0x37 ; /* 0x0000003700002802 */
/* 0x000fca0000000f00 */
/*00e0*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
// CUDA check error
#define cuda_check_error(msg) \
{ \
cudaError_t err = cudaGetLastError(); \
if( cudaSuccess != err) { \
fprintf(stderr, "[GPUJPEG] [Error] %s (line %i): %s: %s.\n", \
__FILE__, __LINE__, msg, cudaGetErrorString( err) ); \
exit(-1); \
} \
} \
__global__
void get_value(int* index, int* value)
{
int x[3];
for ( int i = 0; i < 3; i++ )
x[i] = 55;
*value = x[*index];
}
int main()
{
int* d_index;
int* d_value;
cudaMalloc((void**)&d_index, sizeof(int));
cudaMalloc((void**)&d_value, sizeof(int));
cuda_check_error("Alloc failed");
int index = 0;
int value = 0;
cudaMemcpy(d_index, &index, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_value, &value, sizeof(int), cudaMemcpyHostToDevice);
cuda_check_error("Init failed");
get_value<<<1, 1>>>(d_index, d_value);
cudaThreadSynchronize();
cuda_check_error("Kernel failed");
cudaMemcpy(&index, d_index, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(&value, d_value, sizeof(int), cudaMemcpyDeviceToHost);
cuda_check_error("Copy failed");
printf("index = %d\n", index);
printf("value = %d\n", value);
return 0;
} | .file "tmpxft_001a3f53_00000000-6_memcheck.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9get_valuePiS_PiS_
.type _Z30__device_stub__Z9get_valuePiS_PiS_, @function
_Z30__device_stub__Z9get_valuePiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9get_valuePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9get_valuePiS_PiS_, .-_Z30__device_stub__Z9get_valuePiS_PiS_
.globl _Z9get_valuePiS_
.type _Z9get_valuePiS_, @function
_Z9get_valuePiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9get_valuePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9get_valuePiS_, .-_Z9get_valuePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Alloc failed"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/CESNET/GPUJPEG/master/test/memcheck/memcheck.cu"
.align 8
.LC2:
.string "[GPUJPEG] [Error] %s (line %i): %s: %s.\n"
.section .rodata.str1.1
.LC3:
.string "Init failed"
.LC4:
.string "Kernel failed"
.LC5:
.string "Copy failed"
.LC6:
.string "index = %d\n"
.LC7:
.string "value = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L19
movl $0, 8(%rsp)
movl $0, 12(%rsp)
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
leaq 8(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
movl 8(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 88
pushq %rax
.cfi_def_cfa_offset 96
leaq .LC0(%rip), %r9
movl $31, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L20:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 88
pushq %rax
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
movl $37, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L21:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9get_valuePiS_PiS_
jmp .L14
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 88
pushq %rax
.cfi_def_cfa_offset 96
leaq .LC4(%rip), %r9
movl $41, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L23:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 88
pushq %rax
.cfi_def_cfa_offset 96
leaq .LC5(%rip), %r9
movl $45, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9get_valuePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9get_valuePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
// CUDA check error
#define cuda_check_error(msg) \
{ \
cudaError_t err = cudaGetLastError(); \
if( cudaSuccess != err) { \
fprintf(stderr, "[GPUJPEG] [Error] %s (line %i): %s: %s.\n", \
__FILE__, __LINE__, msg, cudaGetErrorString( err) ); \
exit(-1); \
} \
} \
__global__
void get_value(int* index, int* value)
{
int x[3];
for ( int i = 0; i < 3; i++ )
x[i] = 55;
*value = x[*index];
}
int main()
{
int* d_index;
int* d_value;
cudaMalloc((void**)&d_index, sizeof(int));
cudaMalloc((void**)&d_value, sizeof(int));
cuda_check_error("Alloc failed");
int index = 0;
int value = 0;
cudaMemcpy(d_index, &index, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_value, &value, sizeof(int), cudaMemcpyHostToDevice);
cuda_check_error("Init failed");
get_value<<<1, 1>>>(d_index, d_value);
cudaThreadSynchronize();
cuda_check_error("Kernel failed");
cudaMemcpy(&index, d_index, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(&value, d_value, sizeof(int), cudaMemcpyDeviceToHost);
cuda_check_error("Copy failed");
printf("index = %d\n", index);
printf("value = %d\n", value);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
// CUDA check error
#define cuda_check_error(msg) \
{ \
hipError_t err = hipGetLastError(); \
if( hipSuccess != err) { \
fprintf(stderr, "[GPUJPEG] [Error] %s (line %i): %s: %s.\n", \
__FILE__, __LINE__, msg, hipGetErrorString( err) ); \
exit(-1); \
} \
} \
__global__
void get_value(int* index, int* value)
{
int x[3];
for ( int i = 0; i < 3; i++ )
x[i] = 55;
*value = x[*index];
}
int main()
{
int* d_index;
int* d_value;
hipMalloc((void**)&d_index, sizeof(int));
hipMalloc((void**)&d_value, sizeof(int));
cuda_check_error("Alloc failed");
int index = 0;
int value = 0;
hipMemcpy(d_index, &index, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_value, &value, sizeof(int), hipMemcpyHostToDevice);
cuda_check_error("Init failed");
get_value<<<1, 1>>>(d_index, d_value);
hipDeviceSynchronize();
cuda_check_error("Kernel failed");
hipMemcpy(&index, d_index, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(&value, d_value, sizeof(int), hipMemcpyDeviceToHost);
cuda_check_error("Copy failed");
printf("index = %d\n", index);
printf("value = %d\n", value);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
// CUDA check error
#define cuda_check_error(msg) \
{ \
hipError_t err = hipGetLastError(); \
if( hipSuccess != err) { \
fprintf(stderr, "[GPUJPEG] [Error] %s (line %i): %s: %s.\n", \
__FILE__, __LINE__, msg, hipGetErrorString( err) ); \
exit(-1); \
} \
} \
__global__
void get_value(int* index, int* value)
{
int x[3];
for ( int i = 0; i < 3; i++ )
x[i] = 55;
*value = x[*index];
}
int main()
{
int* d_index;
int* d_value;
hipMalloc((void**)&d_index, sizeof(int));
hipMalloc((void**)&d_value, sizeof(int));
cuda_check_error("Alloc failed");
int index = 0;
int value = 0;
hipMemcpy(d_index, &index, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_value, &value, sizeof(int), hipMemcpyHostToDevice);
cuda_check_error("Init failed");
get_value<<<1, 1>>>(d_index, d_value);
hipDeviceSynchronize();
cuda_check_error("Kernel failed");
hipMemcpy(&index, d_index, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(&value, d_value, sizeof(int), hipMemcpyDeviceToHost);
cuda_check_error("Copy failed");
printf("index = %d\n", index);
printf("value = %d\n", value);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9get_valuePiS_
.globl _Z9get_valuePiS_
.p2align 8
.type _Z9get_valuePiS_,@function
_Z9get_valuePiS_:
s_mov_b64 s[2:3], 0
.LBB0_1:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 2
s_cselect_b32 s5, s5, 55
s_cmp_lg_u32 s2, 1
s_cselect_b32 s6, s6, 55
s_cmp_lg_u32 s2, 0
s_cselect_b32 s4, s4, 55
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 3
s_cbranch_scc0 .LBB0_1
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s0, 1
s_cselect_b32 s1, s6, s4
s_cmp_eq_u32 s0, 2
s_cselect_b32 s0, s5, s1
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9get_valuePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9get_valuePiS_, .Lfunc_end0-_Z9get_valuePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9get_valuePiS_
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z9get_valuePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
// CUDA check error
#define cuda_check_error(msg) \
{ \
hipError_t err = hipGetLastError(); \
if( hipSuccess != err) { \
fprintf(stderr, "[GPUJPEG] [Error] %s (line %i): %s: %s.\n", \
__FILE__, __LINE__, msg, hipGetErrorString( err) ); \
exit(-1); \
} \
} \
__global__
void get_value(int* index, int* value)
{
int x[3];
for ( int i = 0; i < 3; i++ )
x[i] = 55;
*value = x[*index];
}
int main()
{
int* d_index;
int* d_value;
hipMalloc((void**)&d_index, sizeof(int));
hipMalloc((void**)&d_value, sizeof(int));
cuda_check_error("Alloc failed");
int index = 0;
int value = 0;
hipMemcpy(d_index, &index, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_value, &value, sizeof(int), hipMemcpyHostToDevice);
cuda_check_error("Init failed");
get_value<<<1, 1>>>(d_index, d_value);
hipDeviceSynchronize();
cuda_check_error("Kernel failed");
hipMemcpy(&index, d_index, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(&value, d_value, sizeof(int), hipMemcpyDeviceToHost);
cuda_check_error("Copy failed");
printf("index = %d\n", index);
printf("value = %d\n", value);
return 0;
} | .text
.file "memcheck.hip"
.globl _Z24__device_stub__get_valuePiS_ # -- Begin function _Z24__device_stub__get_valuePiS_
.p2align 4, 0x90
.type _Z24__device_stub__get_valuePiS_,@function
_Z24__device_stub__get_valuePiS_: # @_Z24__device_stub__get_valuePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9get_valuePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__get_valuePiS_, .Lfunc_end0-_Z24__device_stub__get_valuePiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_1
# %bb.3:
movl $0, 12(%rsp)
movl $0, 8(%rsp)
movq 24(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_4
# %bb.5:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9get_valuePiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_8
# %bb.9:
movq 24(%rsp), %rsi
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_10
# %bb.11:
movl 12(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 8(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movl $31, %ecx
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movl $37, %ecx
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.4, %r8d
movq %rbx, %rdi
movl $41, %ecx
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.5, %r8d
movq %rbx, %rdi
movl $45, %ecx
.LBB1_2:
movq %rax, %r9
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9get_valuePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9get_valuePiS_,@object # @_Z9get_valuePiS_
.section .rodata,"a",@progbits
.globl _Z9get_valuePiS_
.p2align 3, 0x0
_Z9get_valuePiS_:
.quad _Z24__device_stub__get_valuePiS_
.size _Z9get_valuePiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[GPUJPEG] [Error] %s (line %i): %s: %s.\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/CESNET/GPUJPEG/master/test/memcheck/memcheck.hip"
.size .L.str.1, 106
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Alloc failed"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Init failed"
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Kernel failed"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Copy failed"
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "index = %d\n"
.size .L.str.6, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "value = %d\n"
.size .L.str.7, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9get_valuePiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__get_valuePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9get_valuePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9get_valuePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.SHL.U32 R0, R2, 0x4, RZ ; /* 0x0000000402007824 */
/* 0x004fca00078e00ff */
/*0080*/ ISETP.EQ.AND P0, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe40003f02270 */
/*0090*/ ISETP.EQ.AND P1, PT, R0.reuse, 0x4, PT ; /* 0x000000040000780c */
/* 0x040fe40003f22270 */
/*00a0*/ ISETP.EQ.AND P2, PT, R0, 0x8, PT ; /* 0x000000080000780c */
/* 0x000fd20003f42270 */
/*00b0*/ @P0 MOV R0, 0x37 ; /* 0x0000003700000802 */
/* 0x000fe40000000f00 */
/*00c0*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, 0x37 ; /* 0x00000037ff001424 */
/* 0x000fe400078e00ff */
/*00d0*/ @P2 MOV R0, 0x37 ; /* 0x0000003700002802 */
/* 0x000fca0000000f00 */
/*00e0*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9get_valuePiS_
.globl _Z9get_valuePiS_
.p2align 8
.type _Z9get_valuePiS_,@function
_Z9get_valuePiS_:
s_mov_b64 s[2:3], 0
.LBB0_1:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 2
s_cselect_b32 s5, s5, 55
s_cmp_lg_u32 s2, 1
s_cselect_b32 s6, s6, 55
s_cmp_lg_u32 s2, 0
s_cselect_b32 s4, s4, 55
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 3
s_cbranch_scc0 .LBB0_1
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s0, 1
s_cselect_b32 s1, s6, s4
s_cmp_eq_u32 s0, 2
s_cselect_b32 s0, s5, s1
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9get_valuePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9get_valuePiS_, .Lfunc_end0-_Z9get_valuePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9get_valuePiS_
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z9get_valuePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a3f53_00000000-6_memcheck.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9get_valuePiS_PiS_
.type _Z30__device_stub__Z9get_valuePiS_PiS_, @function
_Z30__device_stub__Z9get_valuePiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9get_valuePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9get_valuePiS_PiS_, .-_Z30__device_stub__Z9get_valuePiS_PiS_
.globl _Z9get_valuePiS_
.type _Z9get_valuePiS_, @function
_Z9get_valuePiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9get_valuePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9get_valuePiS_, .-_Z9get_valuePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Alloc failed"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/CESNET/GPUJPEG/master/test/memcheck/memcheck.cu"
.align 8
.LC2:
.string "[GPUJPEG] [Error] %s (line %i): %s: %s.\n"
.section .rodata.str1.1
.LC3:
.string "Init failed"
.LC4:
.string "Kernel failed"
.LC5:
.string "Copy failed"
.LC6:
.string "index = %d\n"
.LC7:
.string "value = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L19
movl $0, 8(%rsp)
movl $0, 12(%rsp)
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L22
leaq 8(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
movl 8(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 88
pushq %rax
.cfi_def_cfa_offset 96
leaq .LC0(%rip), %r9
movl $31, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L20:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 88
pushq %rax
.cfi_def_cfa_offset 96
leaq .LC3(%rip), %r9
movl $37, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L21:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9get_valuePiS_PiS_
jmp .L14
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 88
pushq %rax
.cfi_def_cfa_offset 96
leaq .LC4(%rip), %r9
movl $41, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L23:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 88
pushq %rax
.cfi_def_cfa_offset 96
leaq .LC5(%rip), %r9
movl $45, %r8d
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9get_valuePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9get_valuePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "memcheck.hip"
.globl _Z24__device_stub__get_valuePiS_ # -- Begin function _Z24__device_stub__get_valuePiS_
.p2align 4, 0x90
.type _Z24__device_stub__get_valuePiS_,@function
_Z24__device_stub__get_valuePiS_: # @_Z24__device_stub__get_valuePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9get_valuePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__get_valuePiS_, .Lfunc_end0-_Z24__device_stub__get_valuePiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_1
# %bb.3:
movl $0, 12(%rsp)
movl $0, 8(%rsp)
movq 24(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_4
# %bb.5:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9get_valuePiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB1_8
# %bb.9:
movq 24(%rsp), %rsi
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_10
# %bb.11:
movl 12(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 8(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.2, %r8d
movq %rbx, %rdi
movl $31, %ecx
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.3, %r8d
movq %rbx, %rdi
movl $37, %ecx
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.4, %r8d
movq %rbx, %rdi
movl $41, %ecx
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.5, %r8d
movq %rbx, %rdi
movl $45, %ecx
.LBB1_2:
movq %rax, %r9
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9get_valuePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9get_valuePiS_,@object # @_Z9get_valuePiS_
.section .rodata,"a",@progbits
.globl _Z9get_valuePiS_
.p2align 3, 0x0
_Z9get_valuePiS_:
.quad _Z24__device_stub__get_valuePiS_
.size _Z9get_valuePiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[GPUJPEG] [Error] %s (line %i): %s: %s.\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/CESNET/GPUJPEG/master/test/memcheck/memcheck.hip"
.size .L.str.1, 106
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Alloc failed"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Init failed"
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Kernel failed"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Copy failed"
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "index = %d\n"
.size .L.str.6, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "value = %d\n"
.size .L.str.7, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9get_valuePiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__get_valuePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9get_valuePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/device_reference.h>
#include <thrust/tuple.h>
#include <thrust/transform.h>
#include <thrust/sequence.h>
#define SPHERES 20
#define rnd( x ) (x * rand() / RAND_MAX)
#define INF 2e10f
#define DIM 2048
struct Sphere {
float r,b,g;
float radius;
float x,y,z;
__host__ __device__ float hit( float ox, float oy, float *n ) {
float dx = ox - x;
float dy = oy - y;
if (dx*dx + dy*dy < radius*radius) {
float dz = sqrtf( radius*radius - dx*dx - dy*dy );
*n = dz / sqrtf( radius * radius );
return dz + z;
}
return -INF;
}
};
struct CalculateBitmap
{
Sphere* s;
CalculateBitmap(Sphere* sp) : s(sp) {}
__host__ __device__ thrust::tuple<unsigned char,unsigned char,unsigned char, unsigned char> operator()(const int& idx)const {
int x = idx / DIM;
int y = idx % DIM;
//int offset = idx;
float ox = (x - DIM/2);
float oy = (y - DIM/2);
//printf("x:%d, y:%d, ox:%f, oy:%f\n",x,y,ox,oy);
float r=0, g=0, b=0;
float maxz = -INF;
for(int i=0; i<SPHERES; i++) {
float n;
float t = s[i].hit( ox, oy, &n );
if (t > maxz) {
float fscale = n;
r = s[i].r * fscale;
g = s[i].g * fscale;
b = s[i].b * fscale;
maxz = t;
}
}
/*
ptr[offset*4 + 0] = (int)(r * 255);
ptr[offset*4 + 1] = (int)(g * 255);
ptr[offset*4 + 2] = (int)(b * 255);
ptr[offset*4 + 3] = 255;
*/
thrust::tuple<unsigned char, unsigned char, unsigned char, unsigned char> result((int)(r*255),(int)(g*255),(int)(b*255),255);
return result;
}
};
void ppm_write(unsigned char* bitmap, int xdim,int ydim, FILE* fp)
{
int i,x,y;
fprintf(fp,"P3\n");
fprintf(fp,"%d %d\n",xdim, ydim);
fprintf(fp,"255\n");
for (y=0;y<ydim;y++) {
for (x=0;x<xdim;x++) {
i=x+y*xdim;
fprintf(fp,"%d %d %d ",bitmap[4*i],bitmap[4*i+1],bitmap[4*i+2]);
}
fprintf(fp,"\n");
}
}
int main(int argc, char* argv[])
{
srand(time(NULL));
if (argc!=2) {
printf("> a.out [filename.ppm]\n");
printf("for example, '> a.out result.ppm' means executing THRUST\n");
exit(0);
}
FILE* fp = fopen(argv[1],"w");
Sphere* temp_s = (Sphere*)malloc( sizeof(Sphere) * SPHERES );
Sphere* dev_temp_s;
cudaMalloc( (void**)&dev_temp_s, SPHERES*sizeof(Sphere));
for (int i=0; i<SPHERES; i++) {
temp_s[i].r = rnd( 1.0f );
temp_s[i].g = rnd( 1.0f );
temp_s[i].b = rnd( 1.0f );
temp_s[i].x = rnd( 2000.0f ) - 1000;
temp_s[i].y = rnd( 2000.0f ) - 1000;
temp_s[i].z = rnd( 2000.0f ) - 1000;
temp_s[i].radius = rnd( 200.0f ) + 40;
}
cudaMemcpy(dev_temp_s, temp_s, SPHERES*sizeof(Sphere),cudaMemcpyHostToDevice);
thrust::device_vector<thrust::tuple<unsigned char, unsigned char, unsigned char, unsigned char> > dev_bitm(DIM*DIM);
thrust::device_vector<int> idx(DIM*DIM);
thrust::sequence(idx.begin(),idx.end());
unsigned char* bitmap = (unsigned char*) malloc(sizeof(unsigned char)*DIM*DIM*4);
unsigned char* dev_bitmap;
cudaMalloc((void**)&dev_bitmap,sizeof(unsigned char)*DIM*DIM*4);
clock_t start = clock();
thrust::transform(idx.begin(),idx.end(),dev_bitm.begin(),CalculateBitmap(dev_temp_s));
clock_t end = clock();
//printf("end of parallel\n");
thrust::host_vector<thrust::tuple<unsigned char,unsigned char,unsigned char, unsigned char> > bitm = dev_bitm;
for(int i=0;i<DIM;i++){
for(int j=0;j<DIM;j++){
for(int k=0;k<4;k++){
bitmap[(i*DIM+j)*4 + 0] = thrust::get<0>(bitm[i+j*DIM]);
bitmap[(i*DIM+j)*4 + 1] = thrust::get<1>(bitm[i+j*DIM]);
bitmap[(i*DIM+j)*4 + 2] = thrust::get<2>(bitm[i+j*DIM]);
bitmap[(i*DIM+j)*4 + 4] = thrust::get<3>(bitm[i+j*DIM]);
}
}
}
//clock_t end = clock();
//printf("end of copy\n");
ppm_write(bitmap,DIM,DIM,fp);
fclose(fp);
//free(bitmap);
//free(temp_s);
printf("THRUST ray tracing: %1.6f sec\n",(end-start) / (float)CLOCKS_PER_SEC);
printf("[%s] was generated.\n",argv[1]);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/device_reference.h>
#include <thrust/tuple.h>
#include <thrust/transform.h>
#include <thrust/sequence.h>
#define SPHERES 20
#define rnd( x ) (x * rand() / RAND_MAX)
#define INF 2e10f
#define DIM 2048
struct Sphere {
float r,b,g;
float radius;
float x,y,z;
__host__ __device__ float hit( float ox, float oy, float *n ) {
float dx = ox - x;
float dy = oy - y;
if (dx*dx + dy*dy < radius*radius) {
float dz = sqrtf( radius*radius - dx*dx - dy*dy );
*n = dz / sqrtf( radius * radius );
return dz + z;
}
return -INF;
}
};
struct CalculateBitmap
{
Sphere* s;
CalculateBitmap(Sphere* sp) : s(sp) {}
__host__ __device__ thrust::tuple<unsigned char,unsigned char,unsigned char, unsigned char> operator()(const int& idx)const {
int x = idx / DIM;
int y = idx % DIM;
//int offset = idx;
float ox = (x - DIM/2);
float oy = (y - DIM/2);
//printf("x:%d, y:%d, ox:%f, oy:%f\n",x,y,ox,oy);
float r=0, g=0, b=0;
float maxz = -INF;
for(int i=0; i<SPHERES; i++) {
float n;
float t = s[i].hit( ox, oy, &n );
if (t > maxz) {
float fscale = n;
r = s[i].r * fscale;
g = s[i].g * fscale;
b = s[i].b * fscale;
maxz = t;
}
}
/*
ptr[offset*4 + 0] = (int)(r * 255);
ptr[offset*4 + 1] = (int)(g * 255);
ptr[offset*4 + 2] = (int)(b * 255);
ptr[offset*4 + 3] = 255;
*/
thrust::tuple<unsigned char, unsigned char, unsigned char, unsigned char> result((int)(r*255),(int)(g*255),(int)(b*255),255);
return result;
}
};
void ppm_write(unsigned char* bitmap, int xdim,int ydim, FILE* fp)
{
int i,x,y;
fprintf(fp,"P3\n");
fprintf(fp,"%d %d\n",xdim, ydim);
fprintf(fp,"255\n");
for (y=0;y<ydim;y++) {
for (x=0;x<xdim;x++) {
i=x+y*xdim;
fprintf(fp,"%d %d %d ",bitmap[4*i],bitmap[4*i+1],bitmap[4*i+2]);
}
fprintf(fp,"\n");
}
}
int main(int argc, char* argv[])
{
srand(time(NULL));
if (argc!=2) {
printf("> a.out [filename.ppm]\n");
printf("for example, '> a.out result.ppm' means executing THRUST\n");
exit(0);
}
FILE* fp = fopen(argv[1],"w");
Sphere* temp_s = (Sphere*)malloc( sizeof(Sphere) * SPHERES );
Sphere* dev_temp_s;
hipMalloc( (void**)&dev_temp_s, SPHERES*sizeof(Sphere));
for (int i=0; i<SPHERES; i++) {
temp_s[i].r = rnd( 1.0f );
temp_s[i].g = rnd( 1.0f );
temp_s[i].b = rnd( 1.0f );
temp_s[i].x = rnd( 2000.0f ) - 1000;
temp_s[i].y = rnd( 2000.0f ) - 1000;
temp_s[i].z = rnd( 2000.0f ) - 1000;
temp_s[i].radius = rnd( 200.0f ) + 40;
}
hipMemcpy(dev_temp_s, temp_s, SPHERES*sizeof(Sphere),hipMemcpyHostToDevice);
thrust::device_vector<thrust::tuple<unsigned char, unsigned char, unsigned char, unsigned char> > dev_bitm(DIM*DIM);
thrust::device_vector<int> idx(DIM*DIM);
thrust::sequence(idx.begin(),idx.end());
unsigned char* bitmap = (unsigned char*) malloc(sizeof(unsigned char)*DIM*DIM*4);
unsigned char* dev_bitmap;
hipMalloc((void**)&dev_bitmap,sizeof(unsigned char)*DIM*DIM*4);
clock_t start = clock();
thrust::transform(idx.begin(),idx.end(),dev_bitm.begin(),CalculateBitmap(dev_temp_s));
clock_t end = clock();
//printf("end of parallel\n");
thrust::host_vector<thrust::tuple<unsigned char,unsigned char,unsigned char, unsigned char> > bitm = dev_bitm;
for(int i=0;i<DIM;i++){
for(int j=0;j<DIM;j++){
for(int k=0;k<4;k++){
bitmap[(i*DIM+j)*4 + 0] = thrust::get<0>(bitm[i+j*DIM]);
bitmap[(i*DIM+j)*4 + 1] = thrust::get<1>(bitm[i+j*DIM]);
bitmap[(i*DIM+j)*4 + 2] = thrust::get<2>(bitm[i+j*DIM]);
bitmap[(i*DIM+j)*4 + 4] = thrust::get<3>(bitm[i+j*DIM]);
}
}
}
//clock_t end = clock();
//printf("end of copy\n");
ppm_write(bitmap,DIM,DIM,fp);
fclose(fp);
//free(bitmap);
//free(temp_s);
printf("THRUST ray tracing: %1.6f sec\n",(end-start) / (float)CLOCKS_PER_SEC);
printf("[%s] was generated.\n",argv[1]);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void solve(){
__shared__ int going;
int id = threadIdx.x;
going = -1;
while (going < 0){
if (id==7){
going = id;
return;
}
}
}
int main(){
solve<<<1, 32>>>();
return 0;
} | code for sm_80
Function : _Z5solvev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, 0xffffffff ; /* 0xffffffff00027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x7 ; /* 0x00000007ff037424 */
/* 0x000fc800078e00ff */
/*0040*/ STS [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0003e80000000800 */
/*0050*/ STS [RZ], R3 ; /* 0x00000003ff007388 */
/* 0x0003e20000000800 */
/*0060*/ ISETP.NE.AND P0, PT, R0, 0x7, PT ; /* 0x000000070000780c */
/* 0x001fda0003f05270 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x002fea0003800000 */
/*0080*/ BRA 0x80 ; /* 0xfffffff000007947 */
/* 0x000fea000383ffff */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void solve(){
__shared__ int going;
int id = threadIdx.x;
going = -1;
while (going < 0){
if (id==7){
going = id;
return;
}
}
}
int main(){
solve<<<1, 32>>>();
return 0;
} | .file "tmpxft_00045ebc_00000000-6_end.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5solvevv
.type _Z23__device_stub__Z5solvevv, @function
_Z23__device_stub__Z5solvevv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5solvev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5solvevv, .-_Z23__device_stub__Z5solvevv
.globl _Z5solvev
.type _Z5solvev, @function
_Z5solvev:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5solvevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5solvev, .-_Z5solvev
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5solvevv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5solvev"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5solvev(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void solve(){
__shared__ int going;
int id = threadIdx.x;
going = -1;
while (going < 0){
if (id==7){
going = id;
return;
}
}
}
int main(){
solve<<<1, 32>>>();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void solve(){
__shared__ int going;
int id = threadIdx.x;
going = -1;
while (going < 0){
if (id==7){
going = id;
return;
}
}
}
int main(){
solve<<<1, 32>>>();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void solve(){
__shared__ int going;
int id = threadIdx.x;
going = -1;
while (going < 0){
if (id==7){
going = id;
return;
}
}
}
int main(){
solve<<<1, 32>>>();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5solvev
.globl _Z5solvev
.p2align 8
.type _Z5solvev,@function
_Z5solvev:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5solvev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5solvev, .Lfunc_end0-_Z5solvev
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5solvev
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z5solvev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void solve(){
__shared__ int going;
int id = threadIdx.x;
going = -1;
while (going < 0){
if (id==7){
going = id;
return;
}
}
}
int main(){
solve<<<1, 32>>>();
return 0;
} | .text
.file "end.hip"
.globl _Z20__device_stub__solvev # -- Begin function _Z20__device_stub__solvev
.p2align 4, 0x90
.type _Z20__device_stub__solvev,@function
_Z20__device_stub__solvev: # @_Z20__device_stub__solvev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5solvev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__solvev, .Lfunc_end0-_Z20__device_stub__solvev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5solvev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5solvev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5solvev,@object # @_Z5solvev
.section .rodata,"a",@progbits
.globl _Z5solvev
.p2align 3, 0x0
_Z5solvev:
.quad _Z20__device_stub__solvev
.size _Z5solvev, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5solvev"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__solvev
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5solvev
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5solvev
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, 0xffffffff ; /* 0xffffffff00027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x7 ; /* 0x00000007ff037424 */
/* 0x000fc800078e00ff */
/*0040*/ STS [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0003e80000000800 */
/*0050*/ STS [RZ], R3 ; /* 0x00000003ff007388 */
/* 0x0003e20000000800 */
/*0060*/ ISETP.NE.AND P0, PT, R0, 0x7, PT ; /* 0x000000070000780c */
/* 0x001fda0003f05270 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x002fea0003800000 */
/*0080*/ BRA 0x80 ; /* 0xfffffff000007947 */
/* 0x000fea000383ffff */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5solvev
.globl _Z5solvev
.p2align 8
.type _Z5solvev,@function
_Z5solvev:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5solvev
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5solvev, .Lfunc_end0-_Z5solvev
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5solvev
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z5solvev.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00045ebc_00000000-6_end.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5solvevv
.type _Z23__device_stub__Z5solvevv, @function
_Z23__device_stub__Z5solvevv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5solvev(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5solvevv, .-_Z23__device_stub__Z5solvevv
.globl _Z5solvev
.type _Z5solvev, @function
_Z5solvev:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5solvevv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5solvev, .-_Z5solvev
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5solvevv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5solvev"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5solvev(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "end.hip"
.globl _Z20__device_stub__solvev # -- Begin function _Z20__device_stub__solvev
.p2align 4, 0x90
.type _Z20__device_stub__solvev,@function
_Z20__device_stub__solvev: # @_Z20__device_stub__solvev
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5solvev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__solvev, .Lfunc_end0-_Z20__device_stub__solvev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5solvev, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5solvev, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5solvev,@object # @_Z5solvev
.section .rodata,"a",@progbits
.globl _Z5solvev
.p2align 3, 0x0
_Z5solvev:
.quad _Z20__device_stub__solvev
.size _Z5solvev, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5solvev"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__solvev
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5solvev
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | # include<stdio.h>
__global__ void mykernel()
{
printf("hello world for GPU\n");
}
int main()
{
mykernel<<<1, 10>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | # include<stdio.h>
__global__ void mykernel()
{
printf("hello world for GPU\n");
}
int main()
{
mykernel<<<1, 10>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00080031_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | # include<stdio.h>
__global__ void mykernel()
{
printf("hello world for GPU\n");
}
int main()
{
mykernel<<<1, 10>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
# include<stdio.h>
__global__ void mykernel()
{
printf("hello world for GPU\n");
}
int main()
{
mykernel<<<1, 10>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
# include<stdio.h>
__global__ void mykernel()
{
printf("hello world for GPU\n");
}
int main()
{
mykernel<<<1, 10>>>();
hipDeviceSynchronize();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelv
.globl _Z8mykernelv
.p2align 8
.type _Z8mykernelv,@function
_Z8mykernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 21
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "hello world for GPU\n"
.size .str, 21
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z8mykernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
# include<stdio.h>
__global__ void mykernel()
{
printf("hello world for GPU\n");
}
int main()
{
mykernel<<<1, 10>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "hello.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelv
.globl _Z8mykernelv
.p2align 8
.type _Z8mykernelv,@function
_Z8mykernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 21
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "hello world for GPU\n"
.size .str, 21
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z8mykernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00080031_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Block size X: 32 */
__global__ void fct_ale_b3_vertical(const int maxLevels, const int * __restrict__ nLevels, double * __restrict__ fct_adf_v, const double * __restrict__ fct_plus, const double * __restrict__ fct_minus)
{
const int node = (blockIdx.x * maxLevels);
const int flux_index = (blockIdx.x * (maxLevels + 1));
const int maxNodeLevel = nLevels[blockIdx.x] - 1;
/* Intermediate levels */
for ( int level = threadIdx.x + 1; level < maxNodeLevel; level += 32 )
{
double flux = 0.0;
double ae_plus = 0.0;
double ae_minus = 0.0;
flux = fct_adf_v[flux_index + level];
ae_plus = 1.0;
ae_minus = 1.0;
ae_plus = fmin(ae_plus, fct_minus[node + (level) - 1]);
ae_minus = fmin(ae_minus, fct_minus[node + (level)]);
ae_plus = fmin(ae_plus, fct_plus[node + (level)]);
ae_minus = fmin(ae_minus, fct_plus[node + (level) - 1]);
if ( signbit(flux) == 0 )
{
flux *= ae_plus;
}
else
{
flux *= ae_minus;
}
fct_adf_v[flux_index + level] = flux;
}
/* Top level */
if ( threadIdx.x == 0 )
{
double flux = fct_adf_v[flux_index];
double ae = 1.0;
if ( signbit(flux) == 0 )
{
ae = fmin(ae, fct_plus[node]);
}
else
{
ae = fmin(ae, fct_minus[node]);
}
fct_adf_v[flux_index] = ae * flux;
}
} | code for sm_80
Function : _Z19fct_ale_b3_verticaliPKiPdPKdS3_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R6, R4, R7, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x001fcc00078e0007 */
/*0050*/ LDG.E.CONSTANT R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e9900 */
/*0060*/ IMAD R3, R4, c[0x0][0x160], RZ ; /* 0x0000580004037a24 */
/* 0x000fe200078e02ff */
/*0070*/ BSSY B0, 0x1080 ; /* 0x0000100000007945 */
/* 0x000fe40003800000 */
/*0080*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0090*/ IMAD.IADD R5, R3, 0x1, R4 ; /* 0x0000000103057824 */
/* 0x000fe200078e0204 */
/*00a0*/ IADD3 R26, R0, 0x1, RZ ; /* 0x00000001001a7810 */
/* 0x001fe40007ffe0ff */
/*00b0*/ IADD3 R2, R7, -0x1, RZ ; /* 0xffffffff07027810 */
/* 0x004fc80007ffe0ff */
/*00c0*/ ISETP.GE.AND P0, PT, R26, R2, PT ; /* 0x000000021a00720c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 BRA 0x1070 ; /* 0x00000f9000000947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R7, -R0, -0x3, R7 ; /* 0xfffffffd00077810 */
/* 0x000fe20007ffe107 */
/*00f0*/ BSSY B1, 0x540 ; /* 0x0000044000017945 */
/* 0x000fe60003800000 */
/*0100*/ LEA.HI R4, R7.reuse, 0x1, RZ, 0x1b ; /* 0x0000000107047811 */
/* 0x040fe400078fd8ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R7, 0x60, PT ; /* 0x000000600700780c */
/* 0x000fe40003f06070 */
/*0120*/ LOP3.LUT P1, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000782c0ff */
/*0130*/ @!P1 BRA 0x530 ; /* 0x000003f000009947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.IADD R8, R3, 0x1, R0 ; /* 0x0000000103087824 */
/* 0x000fe200078e0200 */
/*0150*/ IADD3 R16, R0, 0x1, R5 ; /* 0x0000000100107810 */
/* 0x000fe20007ffe005 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc600078e00ff */
/*0170*/ IADD3 R6, R8.reuse, 0x1, RZ ; /* 0x0000000108067810 */
/* 0x040fe20007ffe0ff */
/*0180*/ IMAD.WIDE R8, R8, R7, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x000fc800078e0207 */
/*0190*/ IMAD.WIDE R16, R16, R7, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fc800078e0207 */
/*01a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*01b0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*01c0*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0007 */
/*01d0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*01e0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0009 */
/*01f0*/ LDG.E.64.CONSTANT R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e9b00 */
/*0200*/ LDG.E.64.CONSTANT R18, [R6.64+0x8] ; /* 0x0000080406127981 */
/* 0x000ee2000c1e9b00 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000c */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000d */
/*0230*/ LDG.E.64.CONSTANT R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x001f28000c1e9b00 */
/*0240*/ LDG.E.64.CONSTANT R12, [R8.64+-0x8] ; /* 0xfffff804080c7981 */
/* 0x000f62000c1e9b00 */
/*0250*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0010 */
/*0260*/ IMAD.MOV.U32 R15, RZ, RZ, R17 ; /* 0x000000ffff0f7224 */
/* 0x000fca00078e0011 */
/*0270*/ LDG.E.64 R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000f22000c1e1b00 */
/*0280*/ IMAD.MOV.U32 R24, RZ, RZ, 0x80000 ; /* 0x00080000ff187424 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R26, R26, 0x20, RZ ; /* 0x000000201a1a7810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ DSETP.MIN.AND P2, P3, R20, 1, PT ; /* 0x3ff000001400742a */
/* 0x0040620003b40000 */
/*02c0*/ IMAD.MOV.U32 R22, RZ, RZ, R21 ; /* 0x000000ffff167224 */
/* 0x000fc600078e0015 */
/*02d0*/ DSETP.MIN.AND P1, P4, R18, 1, PT ; /* 0x3ff000001200742a */
/* 0x008ea20003c20000 */
/*02e0*/ IMAD.MOV.U32 R21, RZ, RZ, R19 ; /* 0x000000ffff157224 */
/* 0x001fe200078e0013 */
/*02f0*/ FSEL R23, R22, 1.875, P2 ; /* 0x3ff0000016177808 */
/* 0x002fe20001000000 */
/*0300*/ IMAD.MOV.U32 R22, RZ, RZ, 0x80000 ; /* 0x00080000ff167424 */
/* 0x000fe200078e00ff */
/*0310*/ SEL R20, R20, RZ, P2 ; /* 0x000000ff14147207 */
/* 0x000fe40001000000 */
/*0320*/ FSEL R25, R21, 1.875, P1 ; /* 0x3ff0000015197808 */
/* 0x004fe40000800000 */
/*0330*/ SEL R18, R18, RZ, P1 ; /* 0x000000ff12127207 */
/* 0x000fe40000800000 */
/*0340*/ @P3 LOP3.LUT R23, R24, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000018173812 */
/* 0x000fc800078efcff */
/*0350*/ @P4 LOP3.LUT R25, R22, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000016194812 */
/* 0x000fe200078efcff */
/*0360*/ IMAD.MOV.U32 R21, RZ, RZ, R23 ; /* 0x000000ffff157224 */
/* 0x000fc800078e0017 */
/*0370*/ IMAD.MOV.U32 R19, RZ, RZ, R25 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0019 */
/*0380*/ DSETP.MIN.AND P2, P3, R20, R10, PT ; /* 0x0000000a1400722a */
/* 0x0100620003b40000 */
/*0390*/ IMAD.MOV.U32 R25, RZ, RZ, R11 ; /* 0x000000ffff197224 */
/* 0x000fe400078e000b */
/*03a0*/ IMAD.MOV.U32 R22, RZ, RZ, R21 ; /* 0x000000ffff167224 */
/* 0x000fe200078e0015 */
/*03b0*/ DSETP.MIN.AND P1, P4, R18, R12, PT ; /* 0x0000000c1200722a */
/* 0x020ea20003c20000 */
/*03c0*/ IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b7224 */
/* 0x001fe200078e0013 */
/*03d0*/ SEL R10, R20, R10, P2 ; /* 0x0000000a140a7207 */
/* 0x002fe20001000000 */
/*03e0*/ IMAD.MOV.U32 R20, RZ, RZ, R13 ; /* 0x000000ffff147224 */
/* 0x000fe200078e000d */
/*03f0*/ FSEL R23, R22, R25, P2 ; /* 0x0000001916177208 */
/* 0x000fc40001000000 */
/*0400*/ SEL R12, R18, R12, P1 ; /* 0x0000000c120c7207 */
/* 0x004fe40000800000 */
/*0410*/ FSEL R21, R11, R20, P1 ; /* 0x000000140b157208 */
/* 0x000fe40000800000 */
/*0420*/ @P3 LOP3.LUT R23, R25, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000019173812 */
/* 0x000fe400078efcff */
/*0430*/ ISETP.GT.AND P1, PT, R17, -0x1, PT ; /* 0xffffffff1100780c */
/* 0x000fe40003f24270 */
/*0440*/ @P4 LOP3.LUT R21, R20, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000014154812 */
/* 0x000fe200078efcff */
/*0450*/ IMAD.MOV.U32 R11, RZ, RZ, R23 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0017 */
/*0460*/ FSEL R10, R10, R12, P1 ; /* 0x0000000c0a0a7208 */
/* 0x000fc40000800000 */
/*0470*/ IADD3 R12, P2, R8, 0x100, RZ ; /* 0x00000100080c7810 */
/* 0x000fe20007f5e0ff */
/*0480*/ IMAD.MOV.U32 R13, RZ, RZ, R21 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0015 */
/*0490*/ IADD3 R8, P3, R6, 0x100, RZ ; /* 0x0000010006087810 */
/* 0x000fc80007f7e0ff */
/*04a0*/ FSEL R11, R11, R13, P1 ; /* 0x0000000d0b0b7208 */
/* 0x000fe20000800000 */
/*04b0*/ IMAD.X R13, RZ, RZ, R9, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e0609 */
/*04c0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25270 */
/*04d0*/ IMAD.X R9, RZ, RZ, R7, P3 ; /* 0x000000ffff097224 */
/* 0x000fc600018e0607 */
/*04e0*/ DMUL R10, R16, R10 ; /* 0x0000000a100a7228 */
/* 0x0000640000000000 */
/*04f0*/ IADD3 R16, P4, R14, 0x100, RZ ; /* 0x000001000e107810 */
/* 0x001fca0007f9e0ff */
/*0500*/ STG.E.64 [R14.64], R10 ; /* 0x0000000a0e007986 */
/* 0x0021e2000c101b04 */
/*0510*/ IMAD.X R17, RZ, RZ, R15, P4 ; /* 0x000000ffff117224 */
/* 0x000fe200020e060f */
/*0520*/ @P1 BRA 0x1d0 ; /* 0xfffffca000001947 */
/* 0x000fea000383ffff */
/*0530*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0540*/ @!P0 BRA 0x1070 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*0550*/ IMAD.IADD R14, R5, 0x1, R26.reuse ; /* 0x00000001050e7824 */
/* 0x101fe400078e021a */
/*0560*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD.IADD R6, R3, 0x1, R26 ; /* 0x0000000103067824 */
/* 0x000fe400078e021a */
/*0580*/ IMAD.WIDE R14, R14, R15, c[0x0][0x170] ; /* 0x00005c000e0e7625 */
/* 0x000fc600078e020f */
/*0590*/ IADD3 R22, R6, -0x1, RZ ; /* 0xffffffff06167810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ IMAD.MOV.U32 R25, RZ, RZ, R15 ; /* 0x000000ffff197224 */
/* 0x000fe400078e000f */
/*05b0*/ IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff187624 */
/* 0x000fe400078e00ff */
/*05c0*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff177624 */
/* 0x000fe400078e00ff */
/*05d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe400078e00ff */
/*05e0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff077624 */
/* 0x000fe400078e00ff */
/*05f0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0004 */
/*0600*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0007 */
/*0610*/ IMAD.WIDE R28, R22, 0x8, R8 ; /* 0x00000008161c7825 */
/* 0x000fca00078e0208 */
/*0620*/ LDG.E.64.CONSTANT R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x000ea2000c1e9b00 */
/*0630*/ IMAD.MOV.U32 R8, RZ, RZ, R24 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0018 */
/*0640*/ IMAD.MOV.U32 R9, RZ, RZ, R23 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0017 */
/*0650*/ LDG.E.64.CONSTANT R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x000ee6000c1e9b00 */
/*0660*/ IMAD.WIDE R8, R6, 0x8, R8 ; /* 0x0000000806087825 */
/* 0x000fca00078e0208 */
/*0670*/ LDG.E.64.CONSTANT R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x000f28000c1e9b00 */
/*0680*/ LDG.E.64.CONSTANT R12, [R8.64+-0x8] ; /* 0xfffff804080c7981 */
/* 0x000f62000c1e9b00 */
/*0690*/ DSETP.MIN.AND P0, P1, R18, 1, PT ; /* 0x3ff000001200742a */
/* 0x0040620003900000 */
/*06a0*/ IMAD.MOV.U32 R15, RZ, RZ, R18 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0012 */
/*06b0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x80000 ; /* 0x00080000ff127424 */
/* 0x001fc600078e00ff */
/*06c0*/ FSEL R19, R19, 1.875, P0 ; /* 0x3ff0000013137808 */
/* 0x002fd00000000000 */
/*06d0*/ @P1 LOP3.LUT R19, R18, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000012131812 */
/* 0x000fe400078efcff */
/*06e0*/ SEL R18, R15, RZ, P0 ; /* 0x000000ff0f127207 */
/* 0x000fe20000000000 */
/*06f0*/ DSETP.MIN.AND P0, P1, R10, 1, PT ; /* 0x3ff000000a00742a */
/* 0x0080620003900000 */
/*0700*/ IMAD.MOV.U32 R20, RZ, RZ, R10 ; /* 0x000000ffff147224 */
/* 0x000fe400078e000a */
/*0710*/ IMAD.MOV.U32 R10, RZ, RZ, 0x80000 ; /* 0x00080000ff0a7424 */
/* 0x001fc600078e00ff */
/*0720*/ FSEL R21, R11, 1.875, P0 ; /* 0x3ff000000b157808 */
/* 0x002fe20000000000 */
/*0730*/ IMAD.MOV.U32 R11, RZ, RZ, R25 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0019 */
/*0740*/ DSETP.MIN.AND P2, P3, R18, R16, PT ; /* 0x000000101200722a */
/* 0x0100620003b40000 */
/*0750*/ IMAD.MOV.U32 R31, RZ, RZ, R16 ; /* 0x000000ffff1f7224 */
/* 0x000fca00078e0010 */
/*0760*/ @P1 LOP3.LUT R21, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a151812 */
/* 0x000fe200078efcff */
/*0770*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*0780*/ IMAD.MOV.U32 R15, RZ, RZ, R17 ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e0011 */
/*0790*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x001ea2000c1e1b00 */
/*07a0*/ SEL R20, R20, RZ, P0 ; /* 0x000000ff14147207 */
/* 0x000fe20000000000 */
/*07b0*/ IMAD.MOV.U32 R30, RZ, RZ, R18 ; /* 0x000000ffff1e7224 */
/* 0x000fe400078e0012 */
/*07c0*/ IMAD.MOV.U32 R25, RZ, RZ, R13 ; /* 0x000000ffff197224 */
/* 0x020fe400078e000d */
/*07d0*/ IMAD.MOV.U32 R18, RZ, RZ, R20 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0014 */
/*07e0*/ DSETP.MIN.AND P0, P1, R20, R12, PT ; /* 0x0000000c1400722a */
/* 0x0000e40003900000 */
/*07f0*/ IMAD.MOV.U32 R20, RZ, RZ, R12 ; /* 0x000000ffff147224 */
/* 0x001fe400078e000c */
/*0800*/ LDG.E.64.CONSTANT R12, [R28.64+0x100] ; /* 0x000100041c0c7981 */
/* 0x000f22000c1e9b00 */
/*0810*/ FSEL R19, R19, R15, P2 ; /* 0x0000000f13137208 */
/* 0x002fc40001000000 */
/*0820*/ @P3 LOP3.LUT R19, R15, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000f133812 */
/* 0x000fe400078efcff */
/*0830*/ LDG.E.64.CONSTANT R14, [R8.64+0x100] ; /* 0x00010004080e7981 */
/* 0x000f62000c1e9b00 */
/*0840*/ SEL R30, R30, R31, P2 ; /* 0x0000001f1e1e7207 */
/* 0x000fe40001000000 */
/*0850*/ SEL R20, R18, R20, P0 ; /* 0x0000001412147207 */
/* 0x008fe20000000000 */
/*0860*/ IMAD.MOV.U32 R31, RZ, RZ, R19 ; /* 0x000000ffff1f7224 */
/* 0x000fe200078e0013 */
/*0870*/ FSEL R21, R21, R25, P0 ; /* 0x0000001915157208 */
/* 0x000fe40000000000 */
/*0880*/ @P1 LOP3.LUT R21, R25, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000019151812 */
/* 0x000fe400078efcff */
/*0890*/ ISETP.GT.AND P0, PT, R17, -0x1, PT ; /* 0xffffffff1100780c */
/* 0x004fc80003f04270 */
/*08a0*/ FSEL R18, R30, R20, P0 ; /* 0x000000141e127208 */
/* 0x000fe40000000000 */
/*08b0*/ FSEL R19, R31, R21, P0 ; /* 0x000000151f137208 */
/* 0x000fe40000000000 */
/*08c0*/ LDG.E.64.CONSTANT R30, [R28.64+0x108] ; /* 0x000108041c1e7981 */
/* 0x000ea2000c1e9b00 */
/*08d0*/ DSETP.MIN.AND P0, P1, R12, 1, PT ; /* 0x3ff000000c00742a */
/* 0x010e080003900000 */
/*08e0*/ DMUL R18, R16, R18 ; /* 0x0000001210127228 */
/* 0x0002e40000000000 */
/*08f0*/ IMAD.MOV.U32 R16, RZ, RZ, R13 ; /* 0x000000ffff107224 */
/* 0x002fe400078e000d */
/*0900*/ IMAD.MOV.U32 R20, RZ, RZ, 0x80000 ; /* 0x00080000ff147424 */
/* 0x000fc600078e00ff */
/*0910*/ FSEL R17, R16, 1.875, P0 ; /* 0x3ff0000010117808 */
/* 0x001fe20000000000 */
/*0920*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000c */
/*0930*/ LDG.E.64.CONSTANT R12, [R8.64+0xf8] ; /* 0x0000f804080c7981 */
/* 0x000f22000c1e9b00 */
/*0940*/ @P1 LOP3.LUT R17, R20, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000014111812 */
/* 0x000fe400078efcff */
/*0950*/ SEL R16, R16, RZ, P0 ; /* 0x000000ff10107207 */
/* 0x000fe20000000000 */
/*0960*/ STG.E.64 [R10.64], R18 ; /* 0x000000120a007986 */
/* 0x0081e8000c101b04 */
/*0970*/ IMAD.MOV.U32 R20, RZ, RZ, R16 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0010 */
/*0980*/ DSETP.MIN.AND P0, P1, R16, R14, PT ; /* 0x0000000e1000722a */
/* 0x0202e20003900000 */
/*0990*/ IMAD.MOV.U32 R18, RZ, RZ, R17 ; /* 0x000000ffff127224 */
/* 0x001fc400078e0011 */
/*09a0*/ IMAD.MOV.U32 R17, RZ, RZ, R14 ; /* 0x000000ffff117224 */
/* 0x002fca00078e000e */
/*09b0*/ SEL R14, R20, R17, P0 ; /* 0x00000011140e7207 */
/* 0x008fe40000000000 */
/*09c0*/ LDG.E.64 R16, [R10.64+0x100] ; /* 0x000100040a107981 */
/* 0x000ee2000c1e1b00 */
/*09d0*/ IMAD.MOV.U32 R19, RZ, RZ, R15 ; /* 0x000000ffff137224 */
/* 0x000fca00078e000f */
/*09e0*/ FSEL R15, R18, R19, P0 ; /* 0x00000013120f7208 */
/* 0x000fe40000000000 */
/*09f0*/ @P1 LOP3.LUT R15, R19, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000130f1812 */
/* 0x000fe400078efcff */
/*0a00*/ LDG.E.64.CONSTANT R18, [R28.64+0x200] ; /* 0x000200041c127981 */
/* 0x000f62000c1e9b00 */
/*0a10*/ IMAD.MOV.U32 R25, RZ, RZ, 0x80000 ; /* 0x00080000ff197424 */
/* 0x000fe200078e00ff */
/*0a20*/ DSETP.MIN.AND P0, P1, R30, 1, PT ; /* 0x3ff000001e00742a */
/* 0x004e220003900000 */
/*0a30*/ IMAD.MOV.U32 R20, RZ, RZ, R30 ; /* 0x000000ffff147224 */
/* 0x000fca00078e001e */
/*0a40*/ FSEL R21, R31, 1.875, P0 ; /* 0x3ff000001f157808 */
/* 0x001fe40000000000 */
/*0a50*/ SEL R20, R20, RZ, P0 ; /* 0x000000ff14147207 */
/* 0x000fcc0000000000 */
/*0a60*/ @P1 LOP3.LUT R21, R25, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000019151812 */
/* 0x000fcc00078efcff */
/*0a70*/ DSETP.MIN.AND P0, P1, R20, R12, PT ; /* 0x0000000c1400722a */
/* 0x0100620003900000 */
/*0a80*/ IMAD.MOV.U32 R25, RZ, RZ, R20 ; /* 0x000000ffff197224 */
/* 0x000fe400078e0014 */
/*0a90*/ IMAD.MOV.U32 R27, RZ, RZ, R21 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e0015 */
/*0aa0*/ IMAD.MOV.U32 R20, RZ, RZ, R12 ; /* 0x000000ffff147224 */
/* 0x001fc600078e000c */
/*0ab0*/ FSEL R21, R27, R13, P0 ; /* 0x0000000d1b157208 */
/* 0x002fe40000000000 */
/*0ac0*/ SEL R20, R25, R20, P0 ; /* 0x0000001419147207 */
/* 0x000fc80000000000 */
/*0ad0*/ @P1 LOP3.LUT R21, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d151812 */
/* 0x000fe400078efcff */
/*0ae0*/ LDG.E.64.CONSTANT R12, [R8.64+0x200] ; /* 0x00020004080c7981 */
/* 0x000ea2000c1e9b00 */
/*0af0*/ ISETP.GT.AND P0, PT, R17, -0x1, PT ; /* 0xffffffff1100780c */
/* 0x008fc80003f04270 */
/*0b00*/ FSEL R14, R14, R20, P0 ; /* 0x000000140e0e7208 */
/* 0x000fe40000000000 */
/*0b10*/ FSEL R15, R15, R21, P0 ; /* 0x000000150f0f7208 */
/* 0x000fe40000000000 */
/*0b20*/ LDG.E.64.CONSTANT R20, [R28.64+0x208] ; /* 0x000208041c147981 */
/* 0x000ee8000c1e9b00 */
/*0b30*/ DMUL R32, R16, R14 ; /* 0x0000000e10207228 */
/* 0x0001e40000000000 */
/*0b40*/ LDG.E.64.CONSTANT R16, [R8.64+0x1f8] ; /* 0x0001f80408107981 */
/* 0x001f24000c1e9b00 */
/*0b50*/ DSETP.MIN.AND P0, P1, R18, 1, PT ; /* 0x3ff000001200742a */
/* 0x020e220003900000 */
/*0b60*/ IMAD.MOV.U32 R14, RZ, RZ, 0x80000 ; /* 0x00080000ff0e7424 */
/* 0x000fca00078e00ff */
/*0b70*/ FSEL R31, R19, 1.875, P0 ; /* 0x3ff00000131f7808 */
/* 0x001fd00000000000 */
/*0b80*/ @P1 LOP3.LUT R31, R14, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000e1f1812 */
/* 0x000fe400078efcff */
/*0b90*/ LDG.E.64 R14, [R10.64+0x200] ; /* 0x000200040a0e7981 */
/* 0x000f62000c1e1b00 */
/*0ba0*/ IMAD.MOV.U32 R30, RZ, RZ, R18 ; /* 0x000000ffff1e7224 */
/* 0x000fca00078e0012 */
/*0bb0*/ SEL R30, R30, RZ, P0 ; /* 0x000000ff1e1e7207 */
/* 0x000fe20000000000 */
/*0bc0*/ IMAD.MOV.U32 R19, RZ, RZ, R31 ; /* 0x000000ffff137224 */
/* 0x000fc800078e001f */
/*0bd0*/ IMAD.MOV.U32 R18, RZ, RZ, R30 ; /* 0x000000ffff127224 */
/* 0x000fe200078e001e */
/*0be0*/ DSETP.MIN.AND P2, P3, R30, R12, PT ; /* 0x0000000c1e00722a */
/* 0x0041e20003b40000 */
/*0bf0*/ IMAD.MOV.U32 R25, RZ, RZ, R12 ; /* 0x000000ffff197224 */
/* 0x000fe200078e000c */
/*0c00*/ LDG.E.64.CONSTANT R30, [R28.64+0x308] ; /* 0x000308041c1e7981 */
/* 0x001ea4000c1e9b00 */
/*0c10*/ DSETP.MIN.AND P0, P1, R20, 1, PT ; /* 0x3ff000001400742a */
/* 0x0080620003900000 */
/*0c20*/ IMAD.MOV.U32 R12, RZ, RZ, R20 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0014 */
/*0c30*/ IMAD.MOV.U32 R20, RZ, RZ, 0x80000 ; /* 0x00080000ff147424 */
/* 0x001fc600078e00ff */
/*0c40*/ FSEL R21, R21, 1.875, P0 ; /* 0x3ff0000015157808 */
/* 0x002fe40000000000 */
/*0c50*/ FSEL R19, R19, R13, P2 ; /* 0x0000000d13137208 */
/* 0x000fe40001000000 */
/*0c60*/ @P3 LOP3.LUT R19, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d133812 */
/* 0x000fc800078efcff */
/*0c70*/ @P1 LOP3.LUT R21, R20, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000014151812 */
/* 0x000fe400078efcff */
/*0c80*/ SEL R12, R12, RZ, P0 ; /* 0x000000ff0c0c7207 */
/* 0x000fc60000000000 */
/*0c90*/ IMAD.MOV.U32 R13, RZ, RZ, R21 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0015 */
/*0ca0*/ IMAD.MOV.U32 R21, RZ, RZ, R12 ; /* 0x000000ffff157224 */
/* 0x000fc800078e000c */
/*0cb0*/ DSETP.MIN.AND P0, P1, R12, R16, PT ; /* 0x000000100c00722a */
/* 0x0100640003900000 */
/*0cc0*/ IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c7224 */
/* 0x001fe400078e0010 */
/*0cd0*/ IMAD.MOV.U32 R20, RZ, RZ, R13 ; /* 0x000000ffff147224 */
/* 0x000fc600078e000d */
/*0ce0*/ SEL R16, R21, R12, P0 ; /* 0x0000000c15107207 */
/* 0x002fe40000000000 */
/*0cf0*/ LDG.E.64.CONSTANT R12, [R28.64+0x300] ; /* 0x000300041c0c7981 */
/* 0x000ee2000c1e9b00 */
/*0d00*/ FSEL R21, R20, R17, P0 ; /* 0x0000001114157208 */
/* 0x000fc80000000000 */
/*0d10*/ @P1 LOP3.LUT R21, R17, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000011151812 */
/* 0x000fe400078efcff */
/*0d20*/ SEL R18, R18, R25, P2 ; /* 0x0000001912127207 */
/* 0x000fe40001000000 */
/*0d30*/ ISETP.GT.AND P0, PT, R15, -0x1, PT ; /* 0xffffffff0f00780c */
/* 0x020fe20003f04270 */
/*0d40*/ IMAD.MOV.U32 R17, RZ, RZ, R21 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0015 */
/*0d50*/ LDG.E.64.CONSTANT R20, [R8.64+0x2f8] ; /* 0x0002f80408147981 */
/* 0x000122000c1e9b00 */
/*0d60*/ FSEL R16, R18, R16, P0 ; /* 0x0000001012107208 */
/* 0x000fe40000000000 */
/*0d70*/ FSEL R17, R19, R17, P0 ; /* 0x0000001113117208 */
/* 0x000fc40000000000 */
/*0d80*/ LDG.E.64.CONSTANT R18, [R8.64+0x300] ; /* 0x0003000408127981 */
/* 0x000168000c1e9b00 */
/*0d90*/ DMUL R16, R14, R16 ; /* 0x000000100e107228 */
/* 0x0002240000000000 */
/*0da0*/ LDG.E.64 R14, [R10.64+0x300] ; /* 0x000300040a0e7981 */
/* 0x002f62000c1e1b00 */
/*0db0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x80000 ; /* 0x00080000ff087424 */
/* 0x001fc600078e00ff */
/*0dc0*/ STG.E.64 [R10.64+0x100], R32 ; /* 0x000100200a007986 */
/* 0x0001e2000c101b04 */
/*0dd0*/ IADD3 R26, R26, 0x80, RZ ; /* 0x000000801a1a7810 */
/* 0x000fc60007ffe0ff */
/*0de0*/ STG.E.64 [R10.64+0x200], R16 ; /* 0x000200100a007986 */
/* 0x0001e2000c101b04 */
/*0df0*/ DSETP.MIN.AND P2, P3, R30, 1, PT ; /* 0x3ff000001e00742a */
/* 0x004e4c0003b40000 */
/*0e00*/ FSEL R9, R31, 1.875, P2 ; /* 0x3ff000001f097808 */
/* 0x002fd00001000000 */
/*0e10*/ @P3 LOP3.LUT R9, R8, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000008093812 */
/* 0x000fe200078efcff */
/*0e20*/ DSETP.MIN.AND P0, P1, R12, 1, PT ; /* 0x3ff000000c00742a */
/* 0x0082a20003900000 */
/*0e30*/ IMAD.MOV.U32 R25, RZ, RZ, R12 ; /* 0x000000ffff197224 */
/* 0x000fe400078e000c */
/*0e40*/ IMAD.MOV.U32 R27, RZ, RZ, R13 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e000d */
/*0e50*/ IMAD.MOV.U32 R12, RZ, RZ, 0x80000 ; /* 0x00080000ff0c7424 */
/* 0x002fe400078e00ff */
/*0e60*/ IMAD.MOV.U32 R13, RZ, RZ, R30 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e001e */
/*0e70*/ FSEL R27, R27, 1.875, P0 ; /* 0x3ff000001b1b7808 */
/* 0x004fcc0000000000 */
/*0e80*/ @P1 LOP3.LUT R27, R12, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000c1b1812 */
/* 0x000fe400078efcff */
/*0e90*/ SEL R8, R13, RZ, P2 ; /* 0x000000ff0d087207 */
/* 0x000fe40001000000 */
/*0ea0*/ SEL R12, R25, RZ, P0 ; /* 0x000000ff190c7207 */
/* 0x000fe20000000000 */
/*0eb0*/ IMAD.MOV.U32 R13, RZ, RZ, R27 ; /* 0x000000ffff0d7224 */
/* 0x000fc600078e001b */
/*0ec0*/ DSETP.MIN.AND P2, P3, R8, R20, PT ; /* 0x000000140800722a */
/* 0x010fc80003b40000 */
/*0ed0*/ DSETP.MIN.AND P0, P1, R12, R18, PT ; /* 0x000000120c00722a */
/* 0x0202a20003900000 */
/*0ee0*/ IMAD.MOV.U32 R25, RZ, RZ, R12 ; /* 0x000000ffff197224 */
/* 0x000fe400078e000c */
/*0ef0*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x002fe400078e0008 */
/*0f00*/ IMAD.MOV.U32 R8, RZ, RZ, R18 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0012 */
/*0f10*/ IMAD.MOV.U32 R18, RZ, RZ, R21 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0015 */
/*0f20*/ FSEL R13, R13, R19, P0 ; /* 0x000000130d0d7208 */
/* 0x004fcc0000000000 */
/*0f30*/ @P1 LOP3.LUT R13, R19, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000130d1812 */
/* 0x000fe400078efcff */
/*0f40*/ FSEL R19, R9, R18, P2 ; /* 0x0000001209137208 */
/* 0x000fe40001000000 */
/*0f50*/ @P3 LOP3.LUT R19, R18, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000012133812 */
/* 0x000fe200078efcff */
/*0f60*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*0f70*/ SEL R8, R25, R8, P0 ; /* 0x0000000819087207 */
/* 0x000fe40000000000 */
/*0f80*/ SEL R12, R12, R20, P2 ; /* 0x000000140c0c7207 */
/* 0x000fe20001000000 */
/*0f90*/ IMAD.MOV.U32 R13, RZ, RZ, R19 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0013 */
/*0fa0*/ ISETP.GT.AND P0, PT, R15, -0x1, PT ; /* 0xffffffff0f00780c */
/* 0x000fc80003f04270 */
/*0fb0*/ FSEL R8, R8, R12, P0 ; /* 0x0000000c08087208 */
/* 0x000fe40000000000 */
/*0fc0*/ FSEL R9, R9, R13, P0 ; /* 0x0000000d09097208 */
/* 0x000fcc0000000000 */
/*0fd0*/ DMUL R8, R14, R8 ; /* 0x000000080e087228 */
/* 0x000e620000000000 */
/*0fe0*/ ISETP.GE.AND P0, PT, R26, R2, PT ; /* 0x000000021a00720c */
/* 0x000fcc0003f06270 */
/*0ff0*/ STG.E.64 [R10.64+0x300], R8 ; /* 0x000300080a007986 */
/* 0x0021e2000c101b04 */
/*1000*/ IADD3 R4, P1, R4, 0x400, RZ ; /* 0x0000040004047810 */
/* 0x000fe40007f3e0ff */
/*1010*/ IADD3 R24, P2, R24, 0x400, RZ ; /* 0x0000040018187810 */
/* 0x000fe40007f5e0ff */
/*1020*/ IADD3 R14, P3, R10, 0x400, RZ ; /* 0x000004000a0e7810 */
/* 0x000fe20007f7e0ff */
/*1030*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0607 */
/*1040*/ IMAD.X R23, RZ, RZ, R23, P2 ; /* 0x000000ffff177224 */
/* 0x000fe400010e0617 */
/*1050*/ IMAD.X R25, RZ, RZ, R11, P3 ; /* 0x000000ffff197224 */
/* 0x000fe200018e060b */
/*1060*/ @!P0 BRA 0x5f0 ; /* 0xfffff58000008947 */
/* 0x000fea000383ffff */
/*1070*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*1080*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*1090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*10a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fc800078e00ff */
/*10b0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fca00078e0204 */
/*10c0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1b00 */
/*10d0*/ SHF.R.S32.HI R0, RZ, 0x1f, R3 ; /* 0x0000001fff007819 */
/* 0x000fe40000011403 */
/*10e0*/ ISETP.GT.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x004fda0003f04270 */
/*10f0*/ @!P0 LEA R8, P1, R3.reuse, c[0x0][0x180], 0x3 ; /* 0x0000600003088a11 */
/* 0x041fe400078218ff */
/*1100*/ @P0 LEA R2, P2, R3.reuse, c[0x0][0x178], 0x3 ; /* 0x00005e0003020a11 */
/* 0x040fe400078418ff */
/*1110*/ @!P0 LEA.HI.X R9, R3.reuse, c[0x0][0x184], R0.reuse, 0x3, P1 ; /* 0x0000610003098a11 */
/* 0x140fe400008f1c00 */
/*1120*/ @P0 LEA.HI.X R3, R3, c[0x0][0x17c], R0, 0x3, P2 ; /* 0x00005f0003030a11 */
/* 0x000fc800010f1c00 */
/*1130*/ @!P0 LDG.E.64.CONSTANT R8, [R8.64] ; /* 0x0000000408088981 */
/* 0x000ea8000c1e9b00 */
/*1140*/ @P0 LDG.E.64.CONSTANT R2, [R2.64] ; /* 0x0000000402020981 */
/* 0x000ee2000c1e9b00 */
/*1150*/ IMAD.MOV.U32 R11, RZ, RZ, 0x80000 ; /* 0x00080000ff0b7424 */
/* 0x000fca00078e00ff */
/*1160*/ LOP3.LUT R11, R11, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000b0b7812 */
/* 0x000fe200078efcff */
/*1170*/ @!P0 DSETP.MIN.AND P1, P2, R8, 1, PT ; /* 0x3ff000000800842a */
/* 0x004e220003a20000 */
/*1180*/ @!P0 IMAD.MOV.U32 R0, RZ, RZ, R9 ; /* 0x000000ffff008224 */
/* 0x000fc600078e0009 */
/*1190*/ @P0 DSETP.MIN.AND P3, P4, R2, 1, PT ; /* 0x3ff000000200042a */
/* 0x008e620003c60000 */
/*11a0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a0224 */
/* 0x000fe200078e0003 */
/*11b0*/ @!P0 FSEL R0, R0, 1.875, P1 ; /* 0x3ff0000000008808 */
/* 0x001fe20000800000 */
/*11c0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff090224 */
/* 0x000fe200078e0002 */
/*11d0*/ @!P0 SEL R2, R8, RZ, P1 ; /* 0x000000ff08028207 */
/* 0x000fe40000800000 */
/*11e0*/ @P0 FSEL R10, R10, 1.875, P3 ; /* 0x3ff000000a0a0808 */
/* 0x002fe40001800000 */
/*11f0*/ @P0 SEL R9, R9, RZ, P3 ; /* 0x000000ff09090207 */
/* 0x000fe40001800000 */
/*1200*/ @P0 SEL R10, R11, R10, P4 ; /* 0x0000000a0b0a0207 */
/* 0x000fc40002000000 */
/*1210*/ @!P0 SEL R3, R11, R0, P2 ; /* 0x000000000b038207 */
/* 0x000fe20001000000 */
/*1220*/ @P0 IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff020224 */
/* 0x000fe400078e0009 */
/*1230*/ @P0 IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff030224 */
/* 0x000fcc00078e000a */
/*1240*/ DMUL R2, R6, R2 ; /* 0x0000000206027228 */
/* 0x000e0e0000000000 */
/*1250*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*1260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1270*/ BRA 0x1270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Block size X: 32 */
__global__ void fct_ale_b3_vertical(const int maxLevels, const int * __restrict__ nLevels, double * __restrict__ fct_adf_v, const double * __restrict__ fct_plus, const double * __restrict__ fct_minus)
{
const int node = (blockIdx.x * maxLevels);
const int flux_index = (blockIdx.x * (maxLevels + 1));
const int maxNodeLevel = nLevels[blockIdx.x] - 1;
/* Intermediate levels */
for ( int level = threadIdx.x + 1; level < maxNodeLevel; level += 32 )
{
double flux = 0.0;
double ae_plus = 0.0;
double ae_minus = 0.0;
flux = fct_adf_v[flux_index + level];
ae_plus = 1.0;
ae_minus = 1.0;
ae_plus = fmin(ae_plus, fct_minus[node + (level) - 1]);
ae_minus = fmin(ae_minus, fct_minus[node + (level)]);
ae_plus = fmin(ae_plus, fct_plus[node + (level)]);
ae_minus = fmin(ae_minus, fct_plus[node + (level) - 1]);
if ( signbit(flux) == 0 )
{
flux *= ae_plus;
}
else
{
flux *= ae_minus;
}
fct_adf_v[flux_index + level] = flux;
}
/* Top level */
if ( threadIdx.x == 0 )
{
double flux = fct_adf_v[flux_index];
double ae = 1.0;
if ( signbit(flux) == 0 )
{
ae = fmin(ae, fct_plus[node]);
}
else
{
ae = fmin(ae, fct_minus[node]);
}
fct_adf_v[flux_index] = ae * flux;
}
} | .file "tmpxft_0003cfba_00000000-6_fct_ale_b3_vertical.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z19fct_ale_b3_verticaliPKiPdPKdS3_iPKiPdPKdS3_
.type _Z49__device_stub__Z19fct_ale_b3_verticaliPKiPdPKdS3_iPKiPdPKdS3_, @function
_Z49__device_stub__Z19fct_ale_b3_verticaliPKiPdPKdS3_iPKiPdPKdS3_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movq %rcx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
movq %r8, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19fct_ale_b3_verticaliPKiPdPKdS3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z19fct_ale_b3_verticaliPKiPdPKdS3_iPKiPdPKdS3_, .-_Z49__device_stub__Z19fct_ale_b3_verticaliPKiPdPKdS3_iPKiPdPKdS3_
.globl _Z19fct_ale_b3_verticaliPKiPdPKdS3_
.type _Z19fct_ale_b3_verticaliPKiPdPKdS3_, @function
_Z19fct_ale_b3_verticaliPKiPdPKdS3_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z19fct_ale_b3_verticaliPKiPdPKdS3_iPKiPdPKdS3_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19fct_ale_b3_verticaliPKiPdPKdS3_, .-_Z19fct_ale_b3_verticaliPKiPdPKdS3_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19fct_ale_b3_verticaliPKiPdPKdS3_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19fct_ale_b3_verticaliPKiPdPKdS3_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Block size X: 32 */
__global__ void fct_ale_b3_vertical(const int maxLevels, const int * __restrict__ nLevels, double * __restrict__ fct_adf_v, const double * __restrict__ fct_plus, const double * __restrict__ fct_minus)
{
const int node = (blockIdx.x * maxLevels);
const int flux_index = (blockIdx.x * (maxLevels + 1));
const int maxNodeLevel = nLevels[blockIdx.x] - 1;
/* Intermediate levels */
for ( int level = threadIdx.x + 1; level < maxNodeLevel; level += 32 )
{
double flux = 0.0;
double ae_plus = 0.0;
double ae_minus = 0.0;
flux = fct_adf_v[flux_index + level];
ae_plus = 1.0;
ae_minus = 1.0;
ae_plus = fmin(ae_plus, fct_minus[node + (level) - 1]);
ae_minus = fmin(ae_minus, fct_minus[node + (level)]);
ae_plus = fmin(ae_plus, fct_plus[node + (level)]);
ae_minus = fmin(ae_minus, fct_plus[node + (level) - 1]);
if ( signbit(flux) == 0 )
{
flux *= ae_plus;
}
else
{
flux *= ae_minus;
}
fct_adf_v[flux_index + level] = flux;
}
/* Top level */
if ( threadIdx.x == 0 )
{
double flux = fct_adf_v[flux_index];
double ae = 1.0;
if ( signbit(flux) == 0 )
{
ae = fmin(ae, fct_plus[node]);
}
else
{
ae = fmin(ae, fct_minus[node]);
}
fct_adf_v[flux_index] = ae * flux;
}
} | #include <hip/hip_runtime.h>
/* Block size X: 32 */
__global__ void fct_ale_b3_vertical(const int maxLevels, const int * __restrict__ nLevels, double * __restrict__ fct_adf_v, const double * __restrict__ fct_plus, const double * __restrict__ fct_minus)
{
const int node = (blockIdx.x * maxLevels);
const int flux_index = (blockIdx.x * (maxLevels + 1));
const int maxNodeLevel = nLevels[blockIdx.x] - 1;
/* Intermediate levels */
for ( int level = threadIdx.x + 1; level < maxNodeLevel; level += 32 )
{
double flux = 0.0;
double ae_plus = 0.0;
double ae_minus = 0.0;
flux = fct_adf_v[flux_index + level];
ae_plus = 1.0;
ae_minus = 1.0;
ae_plus = fmin(ae_plus, fct_minus[node + (level) - 1]);
ae_minus = fmin(ae_minus, fct_minus[node + (level)]);
ae_plus = fmin(ae_plus, fct_plus[node + (level)]);
ae_minus = fmin(ae_minus, fct_plus[node + (level) - 1]);
if ( signbit(flux) == 0 )
{
flux *= ae_plus;
}
else
{
flux *= ae_minus;
}
fct_adf_v[flux_index + level] = flux;
}
/* Top level */
if ( threadIdx.x == 0 )
{
double flux = fct_adf_v[flux_index];
double ae = 1.0;
if ( signbit(flux) == 0 )
{
ae = fmin(ae, fct_plus[node]);
}
else
{
ae = fmin(ae, fct_minus[node]);
}
fct_adf_v[flux_index] = ae * flux;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/* Block size X: 32 */
__global__ void fct_ale_b3_vertical(const int maxLevels, const int * __restrict__ nLevels, double * __restrict__ fct_adf_v, const double * __restrict__ fct_plus, const double * __restrict__ fct_minus)
{
const int node = (blockIdx.x * maxLevels);
const int flux_index = (blockIdx.x * (maxLevels + 1));
const int maxNodeLevel = nLevels[blockIdx.x] - 1;
/* Intermediate levels */
for ( int level = threadIdx.x + 1; level < maxNodeLevel; level += 32 )
{
double flux = 0.0;
double ae_plus = 0.0;
double ae_minus = 0.0;
flux = fct_adf_v[flux_index + level];
ae_plus = 1.0;
ae_minus = 1.0;
ae_plus = fmin(ae_plus, fct_minus[node + (level) - 1]);
ae_minus = fmin(ae_minus, fct_minus[node + (level)]);
ae_plus = fmin(ae_plus, fct_plus[node + (level)]);
ae_minus = fmin(ae_minus, fct_plus[node + (level) - 1]);
if ( signbit(flux) == 0 )
{
flux *= ae_plus;
}
else
{
flux *= ae_minus;
}
fct_adf_v[flux_index + level] = flux;
}
/* Top level */
if ( threadIdx.x == 0 )
{
double flux = fct_adf_v[flux_index];
double ae = 1.0;
if ( signbit(flux) == 0 )
{
ae = fmin(ae, fct_plus[node]);
}
else
{
ae = fmin(ae, fct_minus[node]);
}
fct_adf_v[flux_index] = ae * flux;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19fct_ale_b3_verticaliPKiPdPKdS3_
.globl _Z19fct_ale_b3_verticaliPKiPdPKdS3_
.p2align 8
.type _Z19fct_ale_b3_verticaliPKiPdPKdS3_,@function
_Z19fct_ale_b3_verticaliPKiPdPKdS3_:
s_clause 0x1
s_load_b32 s12, s[0:1], 0x0
s_load_b256 s[0:7], s[0:1], 0x8
s_mov_b32 s10, s15
s_mov_b32 s11, 0
v_add_nc_u32_e32 v7, 1, v0
s_lshl_b64 s[8:9], s[10:11], 2
s_waitcnt lgkmcnt(0)
s_add_i32 s13, s12, 1
s_add_u32 s0, s0, s8
s_addc_u32 s1, s1, s9
s_mul_i32 s8, s15, s12
s_load_b32 s1, s[0:1], 0x0
s_mul_i32 s10, s13, s15
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_add_i32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s1, v7
s_cbranch_execz .LBB0_3
v_add3_u32 v3, v0, s10, 1
v_add_nc_u32_e32 v1, s8, v0
s_mov_b64 s[12:13], s[4:5]
s_mov_b64 s[14:15], s[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v5, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 3, v[3:4]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_lshlrev_b64 v[3:4], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v9, vcc_lo
.LBB0_2:
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s14, v1
v_add_co_ci_u32_e32 v9, vcc_lo, s15, v2, vcc_lo
v_add_co_u32 v10, vcc_lo, s14, v3
v_add_co_ci_u32_e32 v11, vcc_lo, s15, v4, vcc_lo
v_add_co_u32 v12, vcc_lo, s12, v3
s_clause 0x1
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[10:11], v[10:11], off
v_add_co_ci_u32_e32 v13, vcc_lo, s13, v4, vcc_lo
v_add_co_u32 v14, vcc_lo, s12, v1
v_add_co_ci_u32_e32 v15, vcc_lo, s13, v2, vcc_lo
s_clause 0x1
global_load_b64 v[12:13], v[12:13], off
global_load_b64 v[14:15], v[14:15], off
global_load_b64 v[16:17], v[5:6], off
v_add_nc_u32_e32 v7, 32, v7
s_add_u32 s14, s14, 0x100
s_addc_u32 s15, s15, 0
s_add_u32 s12, s12, 0x100
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(4)
v_max_f64 v[8:9], v[8:9], v[8:9]
s_waitcnt vmcnt(3)
v_max_f64 v[10:11], v[10:11], v[10:11]
s_waitcnt vmcnt(2)
v_max_f64 v[12:13], v[12:13], v[12:13]
s_waitcnt vmcnt(1)
v_max_f64 v[14:15], v[14:15], v[14:15]
s_waitcnt vmcnt(0)
v_cmp_gt_i64_e32 vcc_lo, 0, v[16:17]
v_min_f64 v[8:9], v[8:9], 1.0
v_min_f64 v[10:11], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_f64 v[8:9], v[8:9], v[12:13]
v_min_f64 v[10:11], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v9, v9, v11 :: v_dual_cndmask_b32 v8, v8, v10
v_cmp_le_i32_e32 vcc_lo, s1, v7
v_mul_f64 v[8:9], v[16:17], v[8:9]
s_or_b32 s11, vcc_lo, s11
global_store_b64 v[5:6], v[8:9], off
v_add_co_u32 v5, s0, v5, 0x100
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
s_ashr_i32 s11, s10, 31
v_mov_b32_e32 v4, 0
s_lshl_b64 s[0:1], s[10:11], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_ashr_i32 s9, s8, 31
global_load_b64 v[0:1], v4, s[0:1]
s_waitcnt vmcnt(0)
v_cmp_gt_i64_e32 vcc_lo, 0, v[0:1]
s_and_b32 s2, vcc_lo, exec_lo
s_cselect_b32 s5, s7, s5
s_cselect_b32 s4, s6, s4
s_lshl_b64 s[2:3], s[8:9], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_max_f64 v[2:3], s[2:3], s[2:3]
v_min_f64 v[2:3], v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19fct_ale_b3_verticaliPKiPdPKdS3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19fct_ale_b3_verticaliPKiPdPKdS3_, .Lfunc_end0-_Z19fct_ale_b3_verticaliPKiPdPKdS3_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19fct_ale_b3_verticaliPKiPdPKdS3_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19fct_ale_b3_verticaliPKiPdPKdS3_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/* Block size X: 32 */
__global__ void fct_ale_b3_vertical(const int maxLevels, const int * __restrict__ nLevels, double * __restrict__ fct_adf_v, const double * __restrict__ fct_plus, const double * __restrict__ fct_minus)
{
const int node = (blockIdx.x * maxLevels);
const int flux_index = (blockIdx.x * (maxLevels + 1));
const int maxNodeLevel = nLevels[blockIdx.x] - 1;
/* Intermediate levels */
for ( int level = threadIdx.x + 1; level < maxNodeLevel; level += 32 )
{
double flux = 0.0;
double ae_plus = 0.0;
double ae_minus = 0.0;
flux = fct_adf_v[flux_index + level];
ae_plus = 1.0;
ae_minus = 1.0;
ae_plus = fmin(ae_plus, fct_minus[node + (level) - 1]);
ae_minus = fmin(ae_minus, fct_minus[node + (level)]);
ae_plus = fmin(ae_plus, fct_plus[node + (level)]);
ae_minus = fmin(ae_minus, fct_plus[node + (level) - 1]);
if ( signbit(flux) == 0 )
{
flux *= ae_plus;
}
else
{
flux *= ae_minus;
}
fct_adf_v[flux_index + level] = flux;
}
/* Top level */
if ( threadIdx.x == 0 )
{
double flux = fct_adf_v[flux_index];
double ae = 1.0;
if ( signbit(flux) == 0 )
{
ae = fmin(ae, fct_plus[node]);
}
else
{
ae = fmin(ae, fct_minus[node]);
}
fct_adf_v[flux_index] = ae * flux;
}
} | .text
.file "fct_ale_b3_vertical.hip"
.globl _Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_ # -- Begin function _Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_
.p2align 4, 0x90
.type _Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_,@function
_Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_: # @_Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19fct_ale_b3_verticaliPKiPdPKdS3_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_, .Lfunc_end0-_Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19fct_ale_b3_verticaliPKiPdPKdS3_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19fct_ale_b3_verticaliPKiPdPKdS3_,@object # @_Z19fct_ale_b3_verticaliPKiPdPKdS3_
.section .rodata,"a",@progbits
.globl _Z19fct_ale_b3_verticaliPKiPdPKdS3_
.p2align 3, 0x0
_Z19fct_ale_b3_verticaliPKiPdPKdS3_:
.quad _Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_
.size _Z19fct_ale_b3_verticaliPKiPdPKdS3_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19fct_ale_b3_verticaliPKiPdPKdS3_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19fct_ale_b3_verticaliPKiPdPKdS3_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003cfba_00000000-6_fct_ale_b3_vertical.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z19fct_ale_b3_verticaliPKiPdPKdS3_iPKiPdPKdS3_
.type _Z49__device_stub__Z19fct_ale_b3_verticaliPKiPdPKdS3_iPKiPdPKdS3_, @function
_Z49__device_stub__Z19fct_ale_b3_verticaliPKiPdPKdS3_iPKiPdPKdS3_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movq %rcx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
movq %r8, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19fct_ale_b3_verticaliPKiPdPKdS3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z19fct_ale_b3_verticaliPKiPdPKdS3_iPKiPdPKdS3_, .-_Z49__device_stub__Z19fct_ale_b3_verticaliPKiPdPKdS3_iPKiPdPKdS3_
.globl _Z19fct_ale_b3_verticaliPKiPdPKdS3_
.type _Z19fct_ale_b3_verticaliPKiPdPKdS3_, @function
_Z19fct_ale_b3_verticaliPKiPdPKdS3_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z19fct_ale_b3_verticaliPKiPdPKdS3_iPKiPdPKdS3_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19fct_ale_b3_verticaliPKiPdPKdS3_, .-_Z19fct_ale_b3_verticaliPKiPdPKdS3_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19fct_ale_b3_verticaliPKiPdPKdS3_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19fct_ale_b3_verticaliPKiPdPKdS3_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fct_ale_b3_vertical.hip"
.globl _Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_ # -- Begin function _Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_
.p2align 4, 0x90
.type _Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_,@function
_Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_: # @_Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19fct_ale_b3_verticaliPKiPdPKdS3_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_, .Lfunc_end0-_Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19fct_ale_b3_verticaliPKiPdPKdS3_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19fct_ale_b3_verticaliPKiPdPKdS3_,@object # @_Z19fct_ale_b3_verticaliPKiPdPKdS3_
.section .rodata,"a",@progbits
.globl _Z19fct_ale_b3_verticaliPKiPdPKdS3_
.p2align 3, 0x0
_Z19fct_ale_b3_verticaliPKiPdPKdS3_:
.quad _Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_
.size _Z19fct_ale_b3_verticaliPKiPdPKdS3_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19fct_ale_b3_verticaliPKiPdPKdS3_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__fct_ale_b3_verticaliPKiPdPKdS3_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19fct_ale_b3_verticaliPKiPdPKdS3_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define N 100
#define D 48
#define Q 100
#define BL 32//threadsPerBlock -> como son 2 dimensiones el maximo de threadsPerBlock debe ser calculado con BL * BL, por eso no puede ser muy grande, creo xD -->
//deje paginas abiertas: https://devtalk.nvidia.com/default/topic/523694/question-about-grid-block-thread-sizes/
//http://stackoverflow.com/questions/9985912/how-do-i-choose-grid-and-block-dimensions-for-cuda-kernels
double getRand(){
int r = rand();
return 100.0 * r / INT_MAX;
}
int main(){
srand(time(NULL));
printf("%d %d\n" , N , D );
for(int i = 0 ; i < N ; i++){
for(int j = 0 ; j < D ; j++)
printf("%.3lf ", getRand() );
printf("\n");
}
printf("%d\n",Q);
for(int i = 0 ; i < Q ; i++){
for(int j = 0 ; j < D ; j++)
printf("%.3lf ", getRand() );
printf(" 5\n");
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define N 100
#define D 48
#define Q 100
#define BL 32//threadsPerBlock -> como son 2 dimensiones el maximo de threadsPerBlock debe ser calculado con BL * BL, por eso no puede ser muy grande, creo xD -->
//deje paginas abiertas: https://devtalk.nvidia.com/default/topic/523694/question-about-grid-block-thread-sizes/
//http://stackoverflow.com/questions/9985912/how-do-i-choose-grid-and-block-dimensions-for-cuda-kernels
double getRand(){
int r = rand();
return 100.0 * r / INT_MAX;
}
int main(){
srand(time(NULL));
printf("%d %d\n" , N , D );
for(int i = 0 ; i < N ; i++){
for(int j = 0 ; j < D ; j++)
printf("%.3lf ", getRand() );
printf("\n");
}
printf("%d\n",Q);
for(int i = 0 ; i < Q ; i++){
for(int j = 0 ; j < D ; j++)
printf("%.3lf ", getRand() );
printf(" 5\n");
}
return 0;
} | .file "tmpxft_0003d39f_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10863:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10863:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7getRandv
.type _Z7getRandv, @function
_Z7getRandv:
.LFB10859:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC0(%rip), %xmm0
divsd .LC1(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10859:
.size _Z7getRandv, .-_Z7getRandv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d %d\n"
.LC3:
.string "%.3lf "
.LC4:
.string "\n"
.LC5:
.string "%d\n"
.LC6:
.string " 5\n"
.text
.globl main
.type main, @function
main:
.LFB10860:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $48, %ecx
movl $100, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %r12d
leaq .LC3(%rip), %rbp
leaq .LC4(%rip), %r13
jmp .L6
.L15:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subl $1, %r12d
je .L8
.L6:
movl $48, %ebx
.L7:
call _Z7getRandv
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
subl $1, %ebx
jne .L7
jmp .L15
.L8:
movl $100, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %r12d
leaq .LC3(%rip), %rbp
leaq .LC6(%rip), %r13
jmp .L9
.L16:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subl $1, %r12d
je .L11
.L9:
movl $48, %ebx
.L10:
call _Z7getRandv
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
subl $1, %ebx
jne .L10
jmp .L16
.L11:
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10860:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10886:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1079574528
.align 8
.LC1:
.long -4194304
.long 1105199103
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define N 100
#define D 48
#define Q 100
#define BL 32//threadsPerBlock -> como son 2 dimensiones el maximo de threadsPerBlock debe ser calculado con BL * BL, por eso no puede ser muy grande, creo xD -->
//deje paginas abiertas: https://devtalk.nvidia.com/default/topic/523694/question-about-grid-block-thread-sizes/
//http://stackoverflow.com/questions/9985912/how-do-i-choose-grid-and-block-dimensions-for-cuda-kernels
double getRand(){
int r = rand();
return 100.0 * r / INT_MAX;
}
int main(){
srand(time(NULL));
printf("%d %d\n" , N , D );
for(int i = 0 ; i < N ; i++){
for(int j = 0 ; j < D ; j++)
printf("%.3lf ", getRand() );
printf("\n");
}
printf("%d\n",Q);
for(int i = 0 ; i < Q ; i++){
for(int j = 0 ; j < D ; j++)
printf("%.3lf ", getRand() );
printf(" 5\n");
}
return 0;
} | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define N 100
#define D 48
#define Q 100
#define BL 32//threadsPerBlock -> como son 2 dimensiones el maximo de threadsPerBlock debe ser calculado con BL * BL, por eso no puede ser muy grande, creo xD -->
//deje paginas abiertas: https://devtalk.nvidia.com/default/topic/523694/question-about-grid-block-thread-sizes/
//http://stackoverflow.com/questions/9985912/how-do-i-choose-grid-and-block-dimensions-for-cuda-kernels
double getRand(){
int r = rand();
return 100.0 * r / INT_MAX;
}
int main(){
srand(time(NULL));
printf("%d %d\n" , N , D );
for(int i = 0 ; i < N ; i++){
for(int j = 0 ; j < D ; j++)
printf("%.3lf ", getRand() );
printf("\n");
}
printf("%d\n",Q);
for(int i = 0 ; i < Q ; i++){
for(int j = 0 ; j < D ; j++)
printf("%.3lf ", getRand() );
printf(" 5\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define N 100
#define D 48
#define Q 100
#define BL 32//threadsPerBlock -> como son 2 dimensiones el maximo de threadsPerBlock debe ser calculado con BL * BL, por eso no puede ser muy grande, creo xD -->
//deje paginas abiertas: https://devtalk.nvidia.com/default/topic/523694/question-about-grid-block-thread-sizes/
//http://stackoverflow.com/questions/9985912/how-do-i-choose-grid-and-block-dimensions-for-cuda-kernels
double getRand(){
int r = rand();
return 100.0 * r / INT_MAX;
}
int main(){
srand(time(NULL));
printf("%d %d\n" , N , D );
for(int i = 0 ; i < N ; i++){
for(int j = 0 ; j < D ; j++)
printf("%.3lf ", getRand() );
printf("\n");
}
printf("%d\n",Q);
for(int i = 0 ; i < Q ; i++){
for(int j = 0 ; j < D ; j++)
printf("%.3lf ", getRand() );
printf(" 5\n");
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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