system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define N 100
#define D 48
#define Q 100
#define BL 32//threadsPerBlock -> como son 2 dimensiones el maximo de threadsPerBlock debe ser calculado con BL * BL, por eso no puede ser muy grande, creo xD -->
//deje paginas abiertas: https://devtalk.nvidia.com/default/topic/523694/question-about-grid-block-thread-sizes/
//http://stackoverflow.com/questions/9985912/how-do-i-choose-grid-and-block-dimensions-for-cuda-kernels
double getRand(){
int r = rand();
return 100.0 * r / INT_MAX;
}
int main(){
srand(time(NULL));
printf("%d %d\n" , N , D );
for(int i = 0 ; i < N ; i++){
for(int j = 0 ; j < D ; j++)
printf("%.3lf ", getRand() );
printf("\n");
}
printf("%d\n",Q);
for(int i = 0 ; i < Q ; i++){
for(int j = 0 ; j < D ; j++)
printf("%.3lf ", getRand() );
printf(" 5\n");
}
return 0;
} | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7getRandv
.LCPI0_0:
.quad 0x4059000000000000 # double 100
.LCPI0_1:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl _Z7getRandv
.p2align 4, 0x90
.type _Z7getRandv,@function
_Z7getRandv: # @_Z7getRandv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq rand
cvtsi2sd %eax, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
divsd .LCPI0_1(%rip), %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7getRandv, .Lfunc_end0-_Z7getRandv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4059000000000000 # double 100
.LCPI1_1:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $.L.str, %edi
movl $100, %esi
movl $48, %edx
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_1: # %.preheader11
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl $48, %ebp
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
decl %ebp
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebx
cmpl $100, %ebx
jne .LBB1_1
# %bb.4:
xorl %ebx, %ebx
movl $.L.str.3, %edi
movl $100, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
movl $48, %ebp
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
decl %ebp
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $.Lstr, %edi
callq puts@PLT
incl %ebx
cmpl $100, %ebx
jne .LBB1_5
# %bb.8:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d\n"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%.3lf "
.size .L.str.1, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " 5"
.size .Lstr, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003d39f_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10863:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10863:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7getRandv
.type _Z7getRandv, @function
_Z7getRandv:
.LFB10859:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC0(%rip), %xmm0
divsd .LC1(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10859:
.size _Z7getRandv, .-_Z7getRandv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d %d\n"
.LC3:
.string "%.3lf "
.LC4:
.string "\n"
.LC5:
.string "%d\n"
.LC6:
.string " 5\n"
.text
.globl main
.type main, @function
main:
.LFB10860:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $48, %ecx
movl $100, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %r12d
leaq .LC3(%rip), %rbp
leaq .LC4(%rip), %r13
jmp .L6
.L15:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subl $1, %r12d
je .L8
.L6:
movl $48, %ebx
.L7:
call _Z7getRandv
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
subl $1, %ebx
jne .L7
jmp .L15
.L8:
movl $100, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %r12d
leaq .LC3(%rip), %rbp
leaq .LC6(%rip), %r13
jmp .L9
.L16:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subl $1, %r12d
je .L11
.L9:
movl $48, %ebx
.L10:
call _Z7getRandv
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
subl $1, %ebx
jne .L10
jmp .L16
.L11:
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10860:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10886:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1079574528
.align 8
.LC1:
.long -4194304
.long 1105199103
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7getRandv
.LCPI0_0:
.quad 0x4059000000000000 # double 100
.LCPI0_1:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl _Z7getRandv
.p2align 4, 0x90
.type _Z7getRandv,@function
_Z7getRandv: # @_Z7getRandv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq rand
cvtsi2sd %eax, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
divsd .LCPI0_1(%rip), %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7getRandv, .Lfunc_end0-_Z7getRandv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4059000000000000 # double 100
.LCPI1_1:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $.L.str, %edi
movl $100, %esi
movl $48, %edx
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_1: # %.preheader11
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl $48, %ebp
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
decl %ebp
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebx
cmpl $100, %ebx
jne .LBB1_1
# %bb.4:
xorl %ebx, %ebx
movl $.L.str.3, %edi
movl $100, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
movl $48, %ebp
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
decl %ebp
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $.Lstr, %edi
callq puts@PLT
incl %ebx
cmpl $100, %ebx
jne .LBB1_5
# %bb.8:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d\n"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%.3lf "
.size .L.str.1, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " 5"
.size .Lstr, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sumaVector(float *v1, float *v2, float *res){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < TAM_V)
res[index] = v1[index] + v2[index];
} | code for sm_80
Function : _Z10sumaVectorPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x3ff, PT ; /* 0x000003ff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sumaVector(float *v1, float *v2, float *res){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < TAM_V)
res[index] = v1[index] + v2[index];
} | .file "tmpxft_000b7261_00000000-6_sumaVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10sumaVectorPfS_S_PfS_S_
.type _Z34__device_stub__Z10sumaVectorPfS_S_PfS_S_, @function
_Z34__device_stub__Z10sumaVectorPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10sumaVectorPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z10sumaVectorPfS_S_PfS_S_, .-_Z34__device_stub__Z10sumaVectorPfS_S_PfS_S_
.globl _Z10sumaVectorPfS_S_
.type _Z10sumaVectorPfS_S_, @function
_Z10sumaVectorPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10sumaVectorPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10sumaVectorPfS_S_, .-_Z10sumaVectorPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10sumaVectorPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sumaVectorPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sumaVector(float *v1, float *v2, float *res){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < TAM_V)
res[index] = v1[index] + v2[index];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumaVector(float *v1, float *v2, float *res){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < TAM_V)
res[index] = v1[index] + v2[index];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumaVector(float *v1, float *v2, float *res){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < TAM_V)
res[index] = v1[index] + v2[index];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10sumaVectorPfS_S_
.globl _Z10sumaVectorPfS_S_
.p2align 8
.type _Z10sumaVectorPfS_S_,@function
_Z10sumaVectorPfS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10sumaVectorPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10sumaVectorPfS_S_, .Lfunc_end0-_Z10sumaVectorPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10sumaVectorPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10sumaVectorPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumaVector(float *v1, float *v2, float *res){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < TAM_V)
res[index] = v1[index] + v2[index];
} | .text
.file "sumaVector.hip"
.globl _Z25__device_stub__sumaVectorPfS_S_ # -- Begin function _Z25__device_stub__sumaVectorPfS_S_
.p2align 4, 0x90
.type _Z25__device_stub__sumaVectorPfS_S_,@function
_Z25__device_stub__sumaVectorPfS_S_: # @_Z25__device_stub__sumaVectorPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10sumaVectorPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__sumaVectorPfS_S_, .Lfunc_end0-_Z25__device_stub__sumaVectorPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10sumaVectorPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10sumaVectorPfS_S_,@object # @_Z10sumaVectorPfS_S_
.section .rodata,"a",@progbits
.globl _Z10sumaVectorPfS_S_
.p2align 3, 0x0
_Z10sumaVectorPfS_S_:
.quad _Z25__device_stub__sumaVectorPfS_S_
.size _Z10sumaVectorPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10sumaVectorPfS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__sumaVectorPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10sumaVectorPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10sumaVectorPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x3ff, PT ; /* 0x000003ff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10sumaVectorPfS_S_
.globl _Z10sumaVectorPfS_S_
.p2align 8
.type _Z10sumaVectorPfS_S_,@function
_Z10sumaVectorPfS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10sumaVectorPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10sumaVectorPfS_S_, .Lfunc_end0-_Z10sumaVectorPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10sumaVectorPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10sumaVectorPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b7261_00000000-6_sumaVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10sumaVectorPfS_S_PfS_S_
.type _Z34__device_stub__Z10sumaVectorPfS_S_PfS_S_, @function
_Z34__device_stub__Z10sumaVectorPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10sumaVectorPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z10sumaVectorPfS_S_PfS_S_, .-_Z34__device_stub__Z10sumaVectorPfS_S_PfS_S_
.globl _Z10sumaVectorPfS_S_
.type _Z10sumaVectorPfS_S_, @function
_Z10sumaVectorPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10sumaVectorPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10sumaVectorPfS_S_, .-_Z10sumaVectorPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10sumaVectorPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10sumaVectorPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumaVector.hip"
.globl _Z25__device_stub__sumaVectorPfS_S_ # -- Begin function _Z25__device_stub__sumaVectorPfS_S_
.p2align 4, 0x90
.type _Z25__device_stub__sumaVectorPfS_S_,@function
_Z25__device_stub__sumaVectorPfS_S_: # @_Z25__device_stub__sumaVectorPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10sumaVectorPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__sumaVectorPfS_S_, .Lfunc_end0-_Z25__device_stub__sumaVectorPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10sumaVectorPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10sumaVectorPfS_S_,@object # @_Z10sumaVectorPfS_S_
.section .rodata,"a",@progbits
.globl _Z10sumaVectorPfS_S_
.p2align 3, 0x0
_Z10sumaVectorPfS_S_:
.quad _Z25__device_stub__sumaVectorPfS_S_
.size _Z10sumaVectorPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10sumaVectorPfS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__sumaVectorPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10sumaVectorPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda_runtime.h>
#include <cuda.h>
#define BDIM 32
CUdevice device;
CUcontext context;
CUmodule module;
CUfunction function;
#define module_file "kernel.cubin"
#define kernel_name "arr_kernel"
void initCUDA()
{
int deviceCount = 0;
CUresult err = cuInit(0);
if (err == CUDA_SUCCESS)
cuDeviceGetCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "Error: no devices supporting CUDA\n");
exit(-1);
}
// get first CUDA device
cuDeviceGet(&device, 0);
char name[100];
cuDeviceGetName(name, 100, device);
printf("> Using device 0: %s\n", name);
err = cuCtxCreate(&context, 0, device);
if (err != CUDA_SUCCESS) {
fprintf(stderr, "* Error initializing the CUDA context.\n");
cuCtxDestroy(context);
exit(-1);
}
err = cuModuleLoad(&module, module_file);
if (err != CUDA_SUCCESS) {
fprintf(stderr, "* Error loading the module %s\n", module_file);
const char * str;
cuGetErrorString(err, &str);
fprintf(stderr, "%s\n", str);
cuCtxDestroy(context);
exit(-1);
}
err = cuModuleGetFunction(&function, module, kernel_name);
if (err != CUDA_SUCCESS) {
fprintf(stderr, "* Error getting kernel function %s\n", kernel_name);
const char * str;
cuGetErrorString(err, &str);
fprintf(stderr, "%s\n", str);
cuCtxDestroy(context);
exit(-1);
}
}
int main() {
int size = BDIM * 16 * sizeof(int);
int *in = (int *)malloc(size);
int *out = (int *)malloc(size);
int *in_dev, *out_dev;
initCUDA();
cudaMalloc(&in_dev, size);
cudaMalloc(&out_dev, size);
for (int i = 0; i < BDIM; ++i)
in[i] = i;
cudaMemcpy(in_dev, in, size, cudaMemcpyHostToDevice);
void * args[2] = {&in_dev, &out_dev};
cuLaunchKernel(function,
1, 1, 1,
BDIM, 1, 1,
0, 0, args, 0);
// Test
cudaMemcpy(out, out_dev, size, cudaMemcpyDeviceToHost);
printf("%d\n",out[0]);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda_runtime.h>
#include <cuda.h>
#define BDIM 32
CUdevice device;
CUcontext context;
CUmodule module;
CUfunction function;
#define module_file "kernel.cubin"
#define kernel_name "arr_kernel"
void initCUDA()
{
int deviceCount = 0;
CUresult err = cuInit(0);
if (err == CUDA_SUCCESS)
cuDeviceGetCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "Error: no devices supporting CUDA\n");
exit(-1);
}
// get first CUDA device
cuDeviceGet(&device, 0);
char name[100];
cuDeviceGetName(name, 100, device);
printf("> Using device 0: %s\n", name);
err = cuCtxCreate(&context, 0, device);
if (err != CUDA_SUCCESS) {
fprintf(stderr, "* Error initializing the CUDA context.\n");
cuCtxDestroy(context);
exit(-1);
}
err = cuModuleLoad(&module, module_file);
if (err != CUDA_SUCCESS) {
fprintf(stderr, "* Error loading the module %s\n", module_file);
const char * str;
cuGetErrorString(err, &str);
fprintf(stderr, "%s\n", str);
cuCtxDestroy(context);
exit(-1);
}
err = cuModuleGetFunction(&function, module, kernel_name);
if (err != CUDA_SUCCESS) {
fprintf(stderr, "* Error getting kernel function %s\n", kernel_name);
const char * str;
cuGetErrorString(err, &str);
fprintf(stderr, "%s\n", str);
cuCtxDestroy(context);
exit(-1);
}
}
int main() {
int size = BDIM * 16 * sizeof(int);
int *in = (int *)malloc(size);
int *out = (int *)malloc(size);
int *in_dev, *out_dev;
initCUDA();
cudaMalloc(&in_dev, size);
cudaMalloc(&out_dev, size);
for (int i = 0; i < BDIM; ++i)
in[i] = i;
cudaMemcpy(in_dev, in, size, cudaMemcpyHostToDevice);
void * args[2] = {&in_dev, &out_dev};
cuLaunchKernel(function,
1, 1, 1,
BDIM, 1, 1,
0, 0, args, 0);
// Test
cudaMemcpy(out, out_dev, size, cudaMemcpyDeviceToHost);
printf("%d\n",out[0]);
return 0;
} | .file "tmpxft_0004da3d_00000000-6_stall.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: no devices supporting CUDA\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "> Using device 0: %s\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "* Error initializing the CUDA context.\n"
.section .rodata.str1.1
.LC3:
.string "kernel.cubin"
.section .rodata.str1.8
.align 8
.LC4:
.string "* Error loading the module %s\n"
.section .rodata.str1.1
.LC5:
.string "%s\n"
.LC6:
.string "arr_kernel"
.section .rodata.str1.8
.align 8
.LC7:
.string "* Error getting kernel function %s\n"
.text
.globl _Z8initCUDAv
.type _Z8initCUDAv, @function
_Z8initCUDAv:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
addq $-128, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
movl $0, %edi
call cuInit@PLT
testl %eax, %eax
je .L11
.L4:
cmpl $0, 4(%rsp)
je .L12
movl $0, %esi
leaq device(%rip), %rdi
call cuDeviceGet@PLT
leaq 16(%rsp), %rbx
movl device(%rip), %edx
movl $100, %esi
movq %rbx, %rdi
call cuDeviceGetName@PLT
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl device(%rip), %edx
movl $0, %esi
leaq context(%rip), %rdi
call cuCtxCreate_v2@PLT
testl %eax, %eax
jne .L13
leaq .LC3(%rip), %rsi
leaq module(%rip), %rdi
call cuModuleLoad@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L14
leaq .LC6(%rip), %rdx
movq module(%rip), %rsi
leaq function(%rip), %rdi
call cuModuleGetFunction@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L15
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
leaq 4(%rsp), %rdi
call cuDeviceGetCount@PLT
jmp .L4
.L12:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L13:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq context(%rip), %rdi
call cuCtxDestroy_v2@PLT
movl $-1, %edi
call exit@PLT
.L14:
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 8(%rsp), %rsi
movl %ebx, %edi
call cuGetErrorString@PLT
movq 8(%rsp), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq context(%rip), %rdi
call cuCtxDestroy_v2@PLT
movl $-1, %edi
call exit@PLT
.L15:
leaq .LC6(%rip), %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 8(%rsp), %rsi
movl %ebx, %edi
call cuGetErrorString@PLT
movq 8(%rsp), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq context(%rip), %rdi
call cuCtxDestroy_v2@PLT
movl $-1, %edi
call exit@PLT
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z8initCUDAv, .-_Z8initCUDAv
.section .rodata.str1.1
.LC8:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $2048, %edi
call malloc@PLT
movq %rax, %rbx
movl $2048, %edi
call malloc@PLT
movq %rax, %rbp
call _Z8initCUDAv
movq %rsp, %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $0, %eax
.L18:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $32, %rax
jne .L18
movl $1, %ecx
movl $2048, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq %rsp, %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $0
.cfi_def_cfa_offset 96
leaq 32(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 104
pushq $0
.cfi_def_cfa_offset 112
pushq $0
.cfi_def_cfa_offset 120
pushq $1
.cfi_def_cfa_offset 128
movl $1, %r9d
movl $32, %r8d
movl $1, %ecx
movl $1, %edx
movl $1, %esi
movq function(%rip), %rdi
call cuLaunchKernel@PLT
addq $48, %rsp
.cfi_def_cfa_offset 80
movl $2, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl 0(%rbp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl function
.bss
.align 8
.type function, @object
.size function, 8
function:
.zero 8
.globl module
.align 8
.type module, @object
.size module, 8
module:
.zero 8
.globl context
.align 8
.type context, @object
.size context, 8
context:
.zero 8
.globl device
.align 4
.type device, @object
.size device, 4
device:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda_runtime.h>
#include <cuda.h>
#define BDIM 32
CUdevice device;
CUcontext context;
CUmodule module;
CUfunction function;
#define module_file "kernel.cubin"
#define kernel_name "arr_kernel"
void initCUDA()
{
int deviceCount = 0;
CUresult err = cuInit(0);
if (err == CUDA_SUCCESS)
cuDeviceGetCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "Error: no devices supporting CUDA\n");
exit(-1);
}
// get first CUDA device
cuDeviceGet(&device, 0);
char name[100];
cuDeviceGetName(name, 100, device);
printf("> Using device 0: %s\n", name);
err = cuCtxCreate(&context, 0, device);
if (err != CUDA_SUCCESS) {
fprintf(stderr, "* Error initializing the CUDA context.\n");
cuCtxDestroy(context);
exit(-1);
}
err = cuModuleLoad(&module, module_file);
if (err != CUDA_SUCCESS) {
fprintf(stderr, "* Error loading the module %s\n", module_file);
const char * str;
cuGetErrorString(err, &str);
fprintf(stderr, "%s\n", str);
cuCtxDestroy(context);
exit(-1);
}
err = cuModuleGetFunction(&function, module, kernel_name);
if (err != CUDA_SUCCESS) {
fprintf(stderr, "* Error getting kernel function %s\n", kernel_name);
const char * str;
cuGetErrorString(err, &str);
fprintf(stderr, "%s\n", str);
cuCtxDestroy(context);
exit(-1);
}
}
int main() {
int size = BDIM * 16 * sizeof(int);
int *in = (int *)malloc(size);
int *out = (int *)malloc(size);
int *in_dev, *out_dev;
initCUDA();
cudaMalloc(&in_dev, size);
cudaMalloc(&out_dev, size);
for (int i = 0; i < BDIM; ++i)
in[i] = i;
cudaMemcpy(in_dev, in, size, cudaMemcpyHostToDevice);
void * args[2] = {&in_dev, &out_dev};
cuLaunchKernel(function,
1, 1, 1,
BDIM, 1, 1,
0, 0, args, 0);
// Test
cudaMemcpy(out, out_dev, size, cudaMemcpyDeviceToHost);
printf("%d\n",out[0]);
return 0;
} | #include <iostream>
#include <hip/hip_runtime.h>
#define BDIM 32
hipDevice_t device;
hipCtx_t context;
hipModule_t module;
hipFunction_t function;
#define module_file "kernel.cubin"
#define kernel_name "arr_kernel"
void initCUDA()
{
int deviceCount = 0;
hipError_t err = hipInit(0);
if (err == hipSuccess)
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "Error: no devices supporting CUDA\n");
exit(-1);
}
// get first CUDA device
hipDeviceGet(&device, 0);
char name[100];
hipDeviceGetName(name, 100, device);
printf("> Using device 0: %s\n", name);
err = hipCtxCreate(&context, 0, device);
if (err != hipSuccess) {
fprintf(stderr, "* Error initializing the CUDA context.\n");
hipCtxDestroy(context);
exit(-1);
}
err = hipModuleLoad(&module, module_file);
if (err != hipSuccess) {
fprintf(stderr, "* Error loading the module %s\n", module_file);
const char * str;
hipDrvGetErrorString(err, &str);
fprintf(stderr, "%s\n", str);
hipCtxDestroy(context);
exit(-1);
}
err = hipModuleGetFunction(&function, module, kernel_name);
if (err != hipSuccess) {
fprintf(stderr, "* Error getting kernel function %s\n", kernel_name);
const char * str;
hipDrvGetErrorString(err, &str);
fprintf(stderr, "%s\n", str);
hipCtxDestroy(context);
exit(-1);
}
}
int main() {
int size = BDIM * 16 * sizeof(int);
int *in = (int *)malloc(size);
int *out = (int *)malloc(size);
int *in_dev, *out_dev;
initCUDA();
hipMalloc(&in_dev, size);
hipMalloc(&out_dev, size);
for (int i = 0; i < BDIM; ++i)
in[i] = i;
hipMemcpy(in_dev, in, size, hipMemcpyHostToDevice);
void * args[2] = {&in_dev, &out_dev};
hipModuleLaunchKernel(function,
1, 1, 1,
BDIM, 1, 1,
0, 0, args, 0);
// Test
hipMemcpy(out, out_dev, size, hipMemcpyDeviceToHost);
printf("%d\n",out[0]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#define BDIM 32
hipDevice_t device;
hipCtx_t context;
hipModule_t module;
hipFunction_t function;
#define module_file "kernel.cubin"
#define kernel_name "arr_kernel"
void initCUDA()
{
int deviceCount = 0;
hipError_t err = hipInit(0);
if (err == hipSuccess)
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "Error: no devices supporting CUDA\n");
exit(-1);
}
// get first CUDA device
hipDeviceGet(&device, 0);
char name[100];
hipDeviceGetName(name, 100, device);
printf("> Using device 0: %s\n", name);
err = hipCtxCreate(&context, 0, device);
if (err != hipSuccess) {
fprintf(stderr, "* Error initializing the CUDA context.\n");
hipCtxDestroy(context);
exit(-1);
}
err = hipModuleLoad(&module, module_file);
if (err != hipSuccess) {
fprintf(stderr, "* Error loading the module %s\n", module_file);
const char * str;
hipDrvGetErrorString(err, &str);
fprintf(stderr, "%s\n", str);
hipCtxDestroy(context);
exit(-1);
}
err = hipModuleGetFunction(&function, module, kernel_name);
if (err != hipSuccess) {
fprintf(stderr, "* Error getting kernel function %s\n", kernel_name);
const char * str;
hipDrvGetErrorString(err, &str);
fprintf(stderr, "%s\n", str);
hipCtxDestroy(context);
exit(-1);
}
}
int main() {
int size = BDIM * 16 * sizeof(int);
int *in = (int *)malloc(size);
int *out = (int *)malloc(size);
int *in_dev, *out_dev;
initCUDA();
hipMalloc(&in_dev, size);
hipMalloc(&out_dev, size);
for (int i = 0; i < BDIM; ++i)
in[i] = i;
hipMemcpy(in_dev, in, size, hipMemcpyHostToDevice);
void * args[2] = {&in_dev, &out_dev};
hipModuleLaunchKernel(function,
1, 1, 1,
BDIM, 1, 1,
0, 0, args, 0);
// Test
hipMemcpy(out, out_dev, size, hipMemcpyDeviceToHost);
printf("%d\n",out[0]);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#define BDIM 32
hipDevice_t device;
hipCtx_t context;
hipModule_t module;
hipFunction_t function;
#define module_file "kernel.cubin"
#define kernel_name "arr_kernel"
void initCUDA()
{
int deviceCount = 0;
hipError_t err = hipInit(0);
if (err == hipSuccess)
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "Error: no devices supporting CUDA\n");
exit(-1);
}
// get first CUDA device
hipDeviceGet(&device, 0);
char name[100];
hipDeviceGetName(name, 100, device);
printf("> Using device 0: %s\n", name);
err = hipCtxCreate(&context, 0, device);
if (err != hipSuccess) {
fprintf(stderr, "* Error initializing the CUDA context.\n");
hipCtxDestroy(context);
exit(-1);
}
err = hipModuleLoad(&module, module_file);
if (err != hipSuccess) {
fprintf(stderr, "* Error loading the module %s\n", module_file);
const char * str;
hipDrvGetErrorString(err, &str);
fprintf(stderr, "%s\n", str);
hipCtxDestroy(context);
exit(-1);
}
err = hipModuleGetFunction(&function, module, kernel_name);
if (err != hipSuccess) {
fprintf(stderr, "* Error getting kernel function %s\n", kernel_name);
const char * str;
hipDrvGetErrorString(err, &str);
fprintf(stderr, "%s\n", str);
hipCtxDestroy(context);
exit(-1);
}
}
int main() {
int size = BDIM * 16 * sizeof(int);
int *in = (int *)malloc(size);
int *out = (int *)malloc(size);
int *in_dev, *out_dev;
initCUDA();
hipMalloc(&in_dev, size);
hipMalloc(&out_dev, size);
for (int i = 0; i < BDIM; ++i)
in[i] = i;
hipMemcpy(in_dev, in, size, hipMemcpyHostToDevice);
void * args[2] = {&in_dev, &out_dev};
hipModuleLaunchKernel(function,
1, 1, 1,
BDIM, 1, 1,
0, 0, args, 0);
// Test
hipMemcpy(out, out_dev, size, hipMemcpyDeviceToHost);
printf("%d\n",out[0]);
return 0;
} | .text
.file "stall.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8initCUDAv # -- Begin function _Z8initCUDAv
.p2align 4, 0x90
.type _Z8initCUDAv,@function
_Z8initCUDAv: # @_Z8initCUDAv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movl $0, 4(%rsp)
xorl %edi, %edi
callq hipInit
testl %eax, %eax
jne .LBB0_2
# %bb.1:
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
.LBB0_2:
cmpl $0, 4(%rsp)
je .LBB0_12
# %bb.3:
movl $device, %edi
xorl %esi, %esi
callq hipDeviceGet
movl device(%rip), %edx
leaq 16(%rsp), %rbx
movq %rbx, %rdi
movl $100, %esi
callq hipDeviceGetName
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl device(%rip), %edx
movl $context, %edi
xorl %esi, %esi
callq hipCtxCreate
testl %eax, %eax
jne .LBB0_4
# %bb.6:
movl $module, %edi
movl $.L.str.3, %esi
callq hipModuleLoad
testl %eax, %eax
jne .LBB0_7
# %bb.9:
movq module(%rip), %rsi
movl $function, %edi
movl $.L.str.6, %edx
callq hipModuleGetFunction
testl %eax, %eax
jne .LBB0_10
# %bb.11:
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $34, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.LBB0_4:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $39, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB0_5
.LBB0_7:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.3, %edx
jmp .LBB0_8
.LBB0_10:
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
movl $.L.str.6, %edx
.LBB0_8:
movl %eax, %ebx
xorl %eax, %eax
callq fprintf
leaq 8(%rsp), %rsi
movl %ebx, %edi
callq hipDrvGetErrorString
movq stderr(%rip), %rdi
movq 8(%rsp), %rdx
movl $.L.str.5, %esi
xorl %eax, %eax
callq fprintf
.LBB0_5:
movq context(%rip), %rdi
callq hipCtxDestroy
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z8initCUDAv, .Lfunc_end0-_Z8initCUDAv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
callq _Z8initCUDAv
leaq 8(%rsp), %r15
movl $2048, %esi # imm = 0x800
movq %r15, %rdi
callq hipMalloc
movq %rsp, %r12
movl $2048, %esi # imm = 0x800
movq %r12, %rdi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r15, 16(%rsp)
movq %r12, 24(%rsp)
movq function(%rip), %rdi
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 24(%rsp), %rax
movl $1, %esi
movl $1, %edx
movl $1, %ecx
movl $32, %r8d
movl $1, %r9d
pushq $0
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq hipModuleLaunchKernel
addq $48, %rsp
.cfi_adjust_cfa_offset -48
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type device,@object # @device
.bss
.globl device
.p2align 2, 0x0
device:
.long 0 # 0x0
.size device, 4
.type context,@object # @context
.globl context
.p2align 3, 0x0
context:
.quad 0
.size context, 8
.type module,@object # @module
.globl module
.p2align 3, 0x0
module:
.quad 0
.size module, 8
.type function,@object # @function
.globl function
.p2align 3, 0x0
function:
.quad 0
.size function, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: no devices supporting CUDA\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "> Using device 0: %s\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "* Error initializing the CUDA context.\n"
.size .L.str.2, 40
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "kernel.cubin"
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "* Error loading the module %s\n"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s\n"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "arr_kernel"
.size .L.str.6, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "* Error getting kernel function %s\n"
.size .L.str.7, 36
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d\n"
.size .L.str.8, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym device
.addrsig_sym context
.addrsig_sym module
.addrsig_sym function
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004da3d_00000000-6_stall.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: no devices supporting CUDA\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "> Using device 0: %s\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "* Error initializing the CUDA context.\n"
.section .rodata.str1.1
.LC3:
.string "kernel.cubin"
.section .rodata.str1.8
.align 8
.LC4:
.string "* Error loading the module %s\n"
.section .rodata.str1.1
.LC5:
.string "%s\n"
.LC6:
.string "arr_kernel"
.section .rodata.str1.8
.align 8
.LC7:
.string "* Error getting kernel function %s\n"
.text
.globl _Z8initCUDAv
.type _Z8initCUDAv, @function
_Z8initCUDAv:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
addq $-128, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
movl $0, %edi
call cuInit@PLT
testl %eax, %eax
je .L11
.L4:
cmpl $0, 4(%rsp)
je .L12
movl $0, %esi
leaq device(%rip), %rdi
call cuDeviceGet@PLT
leaq 16(%rsp), %rbx
movl device(%rip), %edx
movl $100, %esi
movq %rbx, %rdi
call cuDeviceGetName@PLT
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl device(%rip), %edx
movl $0, %esi
leaq context(%rip), %rdi
call cuCtxCreate_v2@PLT
testl %eax, %eax
jne .L13
leaq .LC3(%rip), %rsi
leaq module(%rip), %rdi
call cuModuleLoad@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L14
leaq .LC6(%rip), %rdx
movq module(%rip), %rsi
leaq function(%rip), %rdi
call cuModuleGetFunction@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L15
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
leaq 4(%rsp), %rdi
call cuDeviceGetCount@PLT
jmp .L4
.L12:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L13:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq context(%rip), %rdi
call cuCtxDestroy_v2@PLT
movl $-1, %edi
call exit@PLT
.L14:
leaq .LC3(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 8(%rsp), %rsi
movl %ebx, %edi
call cuGetErrorString@PLT
movq 8(%rsp), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq context(%rip), %rdi
call cuCtxDestroy_v2@PLT
movl $-1, %edi
call exit@PLT
.L15:
leaq .LC6(%rip), %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 8(%rsp), %rsi
movl %ebx, %edi
call cuGetErrorString@PLT
movq 8(%rsp), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq context(%rip), %rdi
call cuCtxDestroy_v2@PLT
movl $-1, %edi
call exit@PLT
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z8initCUDAv, .-_Z8initCUDAv
.section .rodata.str1.1
.LC8:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $2048, %edi
call malloc@PLT
movq %rax, %rbx
movl $2048, %edi
call malloc@PLT
movq %rax, %rbp
call _Z8initCUDAv
movq %rsp, %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $0, %eax
.L18:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $32, %rax
jne .L18
movl $1, %ecx
movl $2048, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq %rsp, %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
subq $8, %rsp
.cfi_def_cfa_offset 88
pushq $0
.cfi_def_cfa_offset 96
leaq 32(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 104
pushq $0
.cfi_def_cfa_offset 112
pushq $0
.cfi_def_cfa_offset 120
pushq $1
.cfi_def_cfa_offset 128
movl $1, %r9d
movl $32, %r8d
movl $1, %ecx
movl $1, %edx
movl $1, %esi
movq function(%rip), %rdi
call cuLaunchKernel@PLT
addq $48, %rsp
.cfi_def_cfa_offset 80
movl $2, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl 0(%rbp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl function
.bss
.align 8
.type function, @object
.size function, 8
function:
.zero 8
.globl module
.align 8
.type module, @object
.size module, 8
module:
.zero 8
.globl context
.align 8
.type context, @object
.size context, 8
context:
.zero 8
.globl device
.align 4
.type device, @object
.size device, 4
device:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stall.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8initCUDAv # -- Begin function _Z8initCUDAv
.p2align 4, 0x90
.type _Z8initCUDAv,@function
_Z8initCUDAv: # @_Z8initCUDAv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movl $0, 4(%rsp)
xorl %edi, %edi
callq hipInit
testl %eax, %eax
jne .LBB0_2
# %bb.1:
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
.LBB0_2:
cmpl $0, 4(%rsp)
je .LBB0_12
# %bb.3:
movl $device, %edi
xorl %esi, %esi
callq hipDeviceGet
movl device(%rip), %edx
leaq 16(%rsp), %rbx
movq %rbx, %rdi
movl $100, %esi
callq hipDeviceGetName
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl device(%rip), %edx
movl $context, %edi
xorl %esi, %esi
callq hipCtxCreate
testl %eax, %eax
jne .LBB0_4
# %bb.6:
movl $module, %edi
movl $.L.str.3, %esi
callq hipModuleLoad
testl %eax, %eax
jne .LBB0_7
# %bb.9:
movq module(%rip), %rsi
movl $function, %edi
movl $.L.str.6, %edx
callq hipModuleGetFunction
testl %eax, %eax
jne .LBB0_10
# %bb.11:
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $34, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.LBB0_4:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $39, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB0_5
.LBB0_7:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.3, %edx
jmp .LBB0_8
.LBB0_10:
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
movl $.L.str.6, %edx
.LBB0_8:
movl %eax, %ebx
xorl %eax, %eax
callq fprintf
leaq 8(%rsp), %rsi
movl %ebx, %edi
callq hipDrvGetErrorString
movq stderr(%rip), %rdi
movq 8(%rsp), %rdx
movl $.L.str.5, %esi
xorl %eax, %eax
callq fprintf
.LBB0_5:
movq context(%rip), %rdi
callq hipCtxDestroy
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z8initCUDAv, .Lfunc_end0-_Z8initCUDAv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
callq _Z8initCUDAv
leaq 8(%rsp), %r15
movl $2048, %esi # imm = 0x800
movq %r15, %rdi
callq hipMalloc
movq %rsp, %r12
movl $2048, %esi # imm = 0x800
movq %r12, %rdi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r15, 16(%rsp)
movq %r12, 24(%rsp)
movq function(%rip), %rdi
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 24(%rsp), %rax
movl $1, %esi
movl $1, %edx
movl $1, %ecx
movl $32, %r8d
movl $1, %r9d
pushq $0
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq hipModuleLaunchKernel
addq $48, %rsp
.cfi_adjust_cfa_offset -48
movq (%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type device,@object # @device
.bss
.globl device
.p2align 2, 0x0
device:
.long 0 # 0x0
.size device, 4
.type context,@object # @context
.globl context
.p2align 3, 0x0
context:
.quad 0
.size context, 8
.type module,@object # @module
.globl module
.p2align 3, 0x0
module:
.quad 0
.size module, 8
.type function,@object # @function
.globl function
.p2align 3, 0x0
function:
.quad 0
.size function, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: no devices supporting CUDA\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "> Using device 0: %s\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "* Error initializing the CUDA context.\n"
.size .L.str.2, 40
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "kernel.cubin"
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "* Error loading the module %s\n"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s\n"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "arr_kernel"
.size .L.str.6, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "* Error getting kernel function %s\n"
.size .L.str.7, 36
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d\n"
.size .L.str.8, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym device
.addrsig_sym context
.addrsig_sym module
.addrsig_sym function
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <iostream>
using std::cout;
using std::endl;
#include<fstream>
using std::ofstream;
#include <algorithm>
using std::fill;
/***** ERROR CHECKING MACRO *****/
cudaError_t _TempErrorCode;
#define CHECK_CUDA_ERROR() _TempErrorCode = cudaGetLastError(); if(_TempErrorCode) fprintf(stderr,"!!CUDA ERROR in %s at line %d : %s\n",__FILE__,__LINE__,cudaGetErrorString(_TempErrorCode));
/***** CUSTOM COMMAND LINE ARGUMENT PARSING *****/
//list of global variables (with default values)
int NumberOfArgs = 1; //how many constants are listed below
// you can add your own global variables to be parsed here
// (I start with underline to distiguish that it is a global variable):
int _ArraySize = 1024;
float _IncrementValue = 1.0f;
char _OutputFile[] = "output.txt";
//this will display the global variable values before program starts running
void displayGlobals(void){
cout<<"Setting ArraysSize to " << _ArraySize << endl;
cout<<"Setting IncrementValue to " << _IncrementValue << endl;
}
//this parses the command line arguments
void parseArguments(int arg_count, char* args[]){
//the first argument is always the program
cout << "Running (" << args[0] << ")" << endl;
if(arg_count > NumberOfArgs){
// add your string to whatever parsing here
_ArraySize = atoi(args[1]);
_IncrementValue = atof(args[2]);
//for strings just copy the pointer? (address):
//OutputFile = args[3];
displayGlobals();
}else{
//output usage
cout << "Usage: "<< args[0] << " <ArraySize> <IncrementValue> " << endl;// <OutputFile>" << endl;
//show default values
displayGlobals();
}
}
/***** A DEVICE FUNCTION *****/
__device__ float AddNum(float a, float b){
return a + b;
}
/***** CUDA KERNEL ******/
/** this function increments the inArray by increment for all indicies less than MaxIndex **/
__global__ void incrementKernel(float* outArray,float* inArray, int MaxIndex, float increment){
//the objects (gridDim,blockIdx,blockDim,threadIdx) are already defined:
int threadIndex = blockIdx.x*blockDim.x + threadIdx.x;
if(threadIndex < MaxIndex){ //keep it safe
outArray[threadIndex] = AddNum(inArray[threadIndex], increment);
}
}
/***** MAIN *****/
int main(int argc, char* argv[]){
parseArguments(argc, argv); //this will set the global variables
//Device array pointers
float* inArray_dev; //set to zero to avoid compile warnings
float* outArray_dev;
//Host array pointers
float* inArray_host;
float* outArray_host;
//initialize arrays on host (using c++)
inArray_host = new float[_ArraySize]; //equiv. to (float*)malloc(sizeof(float)*ARRAY_SIZE);
outArray_host = new float[_ArraySize];
//fill
fill(inArray_host, inArray_host+_ArraySize, 1.0f); //fill with ones
fill(outArray_host, outArray_host+_ArraySize, 0.0f); //fill with zeros
//initialize arrays on device (GPU)
cudaMalloc((void**)&inArray_dev, sizeof(float)*_ArraySize);
CHECK_CUDA_ERROR();
cudaMalloc((void**)&outArray_dev, sizeof(float)*_ArraySize);
CHECK_CUDA_ERROR();
//fill
cudaMemset(inArray_dev, sizeof(float)*_ArraySize, 0); //set input array to zero (must be a byte value)
CHECK_CUDA_ERROR();
cudaMemset(outArray_dev, sizeof(float)*_ArraySize, 0); //set output array to zero (must be a byte value)
CHECK_CUDA_ERROR();
//copy input array to device
//cudaMemcpy(DestinationPointer, SourcePointer, NumberOfBytes, cudaMemcpy[Host|Device]To[Host|Device]);
cudaMemcpy(inArray_dev, inArray_host, sizeof(float)*_ArraySize, cudaMemcpyHostToDevice);
//__LAUNCH KERNEL__
//in general this geometry can be 3D, but for now we are just indexing a linear array
int threadsPerBlock = 512; //this is typically the max for most GPUs except Fermi
int blockCount;
//special case for small array size:
if(_ArraySize <= threadsPerBlock){
blockCount = 1;
}else{
blockCount = _ArraySize/threadsPerBlock + 1; //max block size
}
incrementKernel <<< blockCount,threadsPerBlock >>> (outArray_dev, inArray_dev, _ArraySize, _IncrementValue);
cudaThreadSynchronize();
CHECK_CUDA_ERROR();
// copy back results
cudaMemcpy(outArray_host, outArray_dev, sizeof(float)*_ArraySize, cudaMemcpyDeviceToHost);
CHECK_CUDA_ERROR();
ofstream outFileStream;
outFileStream.open(_OutputFile);
//print output
for(int i = 0; i<_ArraySize; i++){
outFileStream << outArray_host[i] << endl;
}
cout << "Data saved in file " << _OutputFile << endl;
//cleanup
outFileStream.close();
delete inArray_host; //like free()
delete outArray_host;
cudaFree(inArray_dev);
cudaFree(outArray_dev);
} | code for sm_80
Function : _Z15incrementKernelPfS_if
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FADD R7, R2, c[0x0][0x174] ; /* 0x00005d0002077621 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <iostream>
using std::cout;
using std::endl;
#include<fstream>
using std::ofstream;
#include <algorithm>
using std::fill;
/***** ERROR CHECKING MACRO *****/
cudaError_t _TempErrorCode;
#define CHECK_CUDA_ERROR() _TempErrorCode = cudaGetLastError(); if(_TempErrorCode) fprintf(stderr,"!!CUDA ERROR in %s at line %d : %s\n",__FILE__,__LINE__,cudaGetErrorString(_TempErrorCode));
/***** CUSTOM COMMAND LINE ARGUMENT PARSING *****/
//list of global variables (with default values)
int NumberOfArgs = 1; //how many constants are listed below
// you can add your own global variables to be parsed here
// (I start with underline to distiguish that it is a global variable):
int _ArraySize = 1024;
float _IncrementValue = 1.0f;
char _OutputFile[] = "output.txt";
//this will display the global variable values before program starts running
void displayGlobals(void){
cout<<"Setting ArraysSize to " << _ArraySize << endl;
cout<<"Setting IncrementValue to " << _IncrementValue << endl;
}
//this parses the command line arguments
void parseArguments(int arg_count, char* args[]){
//the first argument is always the program
cout << "Running (" << args[0] << ")" << endl;
if(arg_count > NumberOfArgs){
// add your string to whatever parsing here
_ArraySize = atoi(args[1]);
_IncrementValue = atof(args[2]);
//for strings just copy the pointer? (address):
//OutputFile = args[3];
displayGlobals();
}else{
//output usage
cout << "Usage: "<< args[0] << " <ArraySize> <IncrementValue> " << endl;// <OutputFile>" << endl;
//show default values
displayGlobals();
}
}
/***** A DEVICE FUNCTION *****/
__device__ float AddNum(float a, float b){
return a + b;
}
/***** CUDA KERNEL ******/
/** this function increments the inArray by increment for all indicies less than MaxIndex **/
__global__ void incrementKernel(float* outArray,float* inArray, int MaxIndex, float increment){
//the objects (gridDim,blockIdx,blockDim,threadIdx) are already defined:
int threadIndex = blockIdx.x*blockDim.x + threadIdx.x;
if(threadIndex < MaxIndex){ //keep it safe
outArray[threadIndex] = AddNum(inArray[threadIndex], increment);
}
}
/***** MAIN *****/
int main(int argc, char* argv[]){
parseArguments(argc, argv); //this will set the global variables
//Device array pointers
float* inArray_dev; //set to zero to avoid compile warnings
float* outArray_dev;
//Host array pointers
float* inArray_host;
float* outArray_host;
//initialize arrays on host (using c++)
inArray_host = new float[_ArraySize]; //equiv. to (float*)malloc(sizeof(float)*ARRAY_SIZE);
outArray_host = new float[_ArraySize];
//fill
fill(inArray_host, inArray_host+_ArraySize, 1.0f); //fill with ones
fill(outArray_host, outArray_host+_ArraySize, 0.0f); //fill with zeros
//initialize arrays on device (GPU)
cudaMalloc((void**)&inArray_dev, sizeof(float)*_ArraySize);
CHECK_CUDA_ERROR();
cudaMalloc((void**)&outArray_dev, sizeof(float)*_ArraySize);
CHECK_CUDA_ERROR();
//fill
cudaMemset(inArray_dev, sizeof(float)*_ArraySize, 0); //set input array to zero (must be a byte value)
CHECK_CUDA_ERROR();
cudaMemset(outArray_dev, sizeof(float)*_ArraySize, 0); //set output array to zero (must be a byte value)
CHECK_CUDA_ERROR();
//copy input array to device
//cudaMemcpy(DestinationPointer, SourcePointer, NumberOfBytes, cudaMemcpy[Host|Device]To[Host|Device]);
cudaMemcpy(inArray_dev, inArray_host, sizeof(float)*_ArraySize, cudaMemcpyHostToDevice);
//__LAUNCH KERNEL__
//in general this geometry can be 3D, but for now we are just indexing a linear array
int threadsPerBlock = 512; //this is typically the max for most GPUs except Fermi
int blockCount;
//special case for small array size:
if(_ArraySize <= threadsPerBlock){
blockCount = 1;
}else{
blockCount = _ArraySize/threadsPerBlock + 1; //max block size
}
incrementKernel <<< blockCount,threadsPerBlock >>> (outArray_dev, inArray_dev, _ArraySize, _IncrementValue);
cudaThreadSynchronize();
CHECK_CUDA_ERROR();
// copy back results
cudaMemcpy(outArray_host, outArray_dev, sizeof(float)*_ArraySize, cudaMemcpyDeviceToHost);
CHECK_CUDA_ERROR();
ofstream outFileStream;
outFileStream.open(_OutputFile);
//print output
for(int i = 0; i<_ArraySize; i++){
outFileStream << outArray_host[i] << endl;
}
cout << "Data saved in file " << _OutputFile << endl;
//cleanup
outFileStream.close();
delete inArray_host; //like free()
delete outArray_host;
cudaFree(inArray_dev);
cudaFree(outArray_dev);
} | .file "tmpxft_000cf54d_00000000-6_cudaExample.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Setting ArraysSize to "
.LC1:
.string "Setting IncrementValue to "
.text
.globl _Z14displayGlobalsv
.type _Z14displayGlobalsv, @function
_Z14displayGlobalsv:
.LFB4054:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $22, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl _ArraySize(%rip), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L11
cmpb $0, 56(%rbp)
je .L5
movzbl 67(%rbp), %esi
.L6:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $26, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd _IncrementValue(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L12
cmpb $0, 56(%rbp)
je .L8
movzbl 67(%rbp), %esi
.L9:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L5:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L6
.L12:
call _ZSt16__throw_bad_castv@PLT
.L8:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L9
.cfi_endproc
.LFE4054:
.size _Z14displayGlobalsv, .-_Z14displayGlobalsv
.section .rodata.str1.1
.LC2:
.string "Running ("
.LC3:
.string ")"
.LC4:
.string "Usage: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string " <ArraySize> <IncrementValue> "
.text
.globl _Z14parseArgumentsiPPc
.type _Z14parseArgumentsiPPc, @function
_Z14parseArgumentsiPPc:
.LFB4055:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %r12d
movq %rsi, %rbx
movl $9, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rbp
testq %rbp, %rbp
je .L27
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L15:
movl $1, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .L28
cmpb $0, 56(%rbp)
je .L17
movzbl 67(%rbp), %esi
.L18:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
cmpl %r12d, NumberOfArgs(%rip)
jge .L19
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, _ArraySize(%rip)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, _IncrementValue(%rip)
call _Z14displayGlobalsv
.L13:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L15
.L28:
call _ZSt16__throw_bad_castv@PLT
.L17:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L18
.L19:
movl $7, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rbx
testq %rbx, %rbx
je .L29
movq %rbx, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L22:
movl $30, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L30
cmpb $0, 56(%rbx)
je .L24
movzbl 67(%rbx), %esi
.L25:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call _Z14displayGlobalsv
jmp .L13
.L29:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L22
.L30:
call _ZSt16__throw_bad_castv@PLT
.L24:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L25
.cfi_endproc
.LFE4055:
.size _Z14parseArgumentsiPPc, .-_Z14parseArgumentsiPPc
.globl _Z6AddNumff
.type _Z6AddNumff, @function
_Z6AddNumff:
.LFB4056:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4056:
.size _Z6AddNumff, .-_Z6AddNumff
.globl _Z39__device_stub__Z15incrementKernelPfS_ifPfS_if
.type _Z39__device_stub__Z15incrementKernelPfS_ifPfS_if, @function
_Z39__device_stub__Z15incrementKernelPfS_ifPfS_if:
.LFB4082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15incrementKernelPfS_if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4082:
.size _Z39__device_stub__Z15incrementKernelPfS_ifPfS_if, .-_Z39__device_stub__Z15incrementKernelPfS_ifPfS_if
.globl _Z15incrementKernelPfS_if
.type _Z15incrementKernelPfS_if, @function
_Z15incrementKernelPfS_if:
.LFB4083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15incrementKernelPfS_ifPfS_if
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4083:
.size _Z15incrementKernelPfS_if, .-_Z15incrementKernelPfS_if
.section .rodata.str1.1
.LC6:
.string "_Z15incrementKernelPfS_if"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z15incrementKernelPfS_if(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8
.align 8
.LC9:
.string "/home/ubuntu/Datasets/stackv2/train-structured/rudm818/ucsd-comp-phys/master/142-242/cudaExample/cudaExample.cu"
.align 8
.LC10:
.string "!!CUDA ERROR in %s at line %d : %s\n"
.section .rodata.str1.1
.LC11:
.string "Data saved in file "
.text
.globl main
.type main, @function
main:
.LFB4057:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4057
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $584, %rsp
.cfi_def_cfa_offset 640
movq %fs:40, %rax
movq %rax, 568(%rsp)
xorl %eax, %eax
.LEHB0:
call _Z14parseArgumentsiPPc
movslq _ArraySize(%rip), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L44
salq $2, %rdi
call _Znam@PLT
movq %rax, %r15
movslq _ArraySize(%rip), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L80
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
movslq _ArraySize(%rip), %rsi
salq $2, %rsi
leaq (%r15,%rsi), %rdx
movq %r15, %rax
movss .LC7(%rip), %xmm0
cmpq %r15, %rdx
je .L49
.L48:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L48
.L49:
leaq 0(%r13,%rsi), %rdx
cmpq %r13, %rdx
je .L51
movq %r13, %rax
.L52:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L52
.L51:
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .L81
.L53:
movslq _ArraySize(%rip), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .L82
.L54:
movl _ArraySize(%rip), %eax
leal 0(,%rax,4), %esi
movl $0, %edx
movq 8(%rsp), %rdi
call cudaMemset@PLT
call cudaGetLastError@PLT
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .L83
.L55:
movl _ArraySize(%rip), %eax
leal 0(,%rax,4), %esi
movl $0, %edx
movq 16(%rsp), %rdi
call cudaMemset@PLT
call cudaGetLastError@PLT
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .L84
.L56:
movslq _ArraySize(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl _ArraySize(%rip), %eax
movl $1, %edx
cmpl $512, %eax
jle .L57
movl $512, %ecx
cltd
idivl %ecx
leal 1(%rax), %edx
.L57:
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %edx, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L58:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .L86
.L59:
movslq _ArraySize(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .L87
.L60:
leaq 48(%rsp), %rbx
movq %rbx, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $16, %edx
leaq _OutputFile(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE1:
jmp .L88
.L44:
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L47
call __stack_chk_fail@PLT
.L47:
.LEHB2:
call __cxa_throw_bad_array_new_length@PLT
.L80:
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L50
call __stack_chk_fail@PLT
.L50:
call __cxa_throw_bad_array_new_length@PLT
.L81:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $103, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L53
.L82:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $105, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L54
.L83:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $109, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L55
.L84:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $111, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L56
.L85:
movss _IncrementValue(%rip), %xmm0
movl _ArraySize(%rip), %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z39__device_stub__Z15incrementKernelPfS_ifPfS_if
jmp .L58
.L86:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $131, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L59
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $135, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.LEHE2:
jmp .L60
.L88:
cmpl $0, _ArraySize(%rip)
jle .L61
movl $0, %r12d
movq %rbx, %r14
jmp .L66
.L92:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L89
cmpb $0, 56(%rbp)
je .L64
movzbl 67(%rbp), %esi
.L65:
movsbl %sil, %esi
movq %rbx, %rdi
.LEHB3:
call _ZNSo3putEc@PLT
jmp .L90
.L89:
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L91
call _ZSt16__throw_bad_castv@PLT
.L72:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L68
call __stack_chk_fail@PLT
.L91:
call __stack_chk_fail@PLT
.L64:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L65
.L90:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %r12
cmpl %r12d, _ArraySize(%rip)
jle .L61
.L66:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%r12,4), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L92
.L61:
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq _OutputFile(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 48(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movl $4, %esi
movq %r15, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r13, %rdi
call _ZdlPvm@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 48(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L93
movl $0, %eax
addq $584, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L93:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4057:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4057-.LLSDACSB4057
.LLSDACSB4057:
.uleb128 .LEHB0-.LFB4057
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4057
.uleb128 .LEHE1-.LEHB1
.uleb128 .L72-.LFB4057
.uleb128 0
.uleb128 .LEHB2-.LFB4057
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4057
.uleb128 .LEHE3-.LEHB3
.uleb128 .L72-.LFB4057
.uleb128 0
.uleb128 .LEHB4-.LFB4057
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4057:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl _OutputFile
.data
.align 8
.type _OutputFile, @object
.size _OutputFile, 11
_OutputFile:
.string "output.txt"
.globl _IncrementValue
.align 4
.type _IncrementValue, @object
.size _IncrementValue, 4
_IncrementValue:
.long 1065353216
.globl _ArraySize
.align 4
.type _ArraySize, @object
.size _ArraySize, 4
_ArraySize:
.long 1024
.globl NumberOfArgs
.align 4
.type NumberOfArgs, @object
.size NumberOfArgs, 4
NumberOfArgs:
.long 1
.globl _TempErrorCode
.bss
.align 4
.type _TempErrorCode, @object
.size _TempErrorCode, 4
_TempErrorCode:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1065353216
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <iostream>
using std::cout;
using std::endl;
#include<fstream>
using std::ofstream;
#include <algorithm>
using std::fill;
/***** ERROR CHECKING MACRO *****/
cudaError_t _TempErrorCode;
#define CHECK_CUDA_ERROR() _TempErrorCode = cudaGetLastError(); if(_TempErrorCode) fprintf(stderr,"!!CUDA ERROR in %s at line %d : %s\n",__FILE__,__LINE__,cudaGetErrorString(_TempErrorCode));
/***** CUSTOM COMMAND LINE ARGUMENT PARSING *****/
//list of global variables (with default values)
int NumberOfArgs = 1; //how many constants are listed below
// you can add your own global variables to be parsed here
// (I start with underline to distiguish that it is a global variable):
int _ArraySize = 1024;
float _IncrementValue = 1.0f;
char _OutputFile[] = "output.txt";
//this will display the global variable values before program starts running
void displayGlobals(void){
cout<<"Setting ArraysSize to " << _ArraySize << endl;
cout<<"Setting IncrementValue to " << _IncrementValue << endl;
}
//this parses the command line arguments
void parseArguments(int arg_count, char* args[]){
//the first argument is always the program
cout << "Running (" << args[0] << ")" << endl;
if(arg_count > NumberOfArgs){
// add your string to whatever parsing here
_ArraySize = atoi(args[1]);
_IncrementValue = atof(args[2]);
//for strings just copy the pointer? (address):
//OutputFile = args[3];
displayGlobals();
}else{
//output usage
cout << "Usage: "<< args[0] << " <ArraySize> <IncrementValue> " << endl;// <OutputFile>" << endl;
//show default values
displayGlobals();
}
}
/***** A DEVICE FUNCTION *****/
__device__ float AddNum(float a, float b){
return a + b;
}
/***** CUDA KERNEL ******/
/** this function increments the inArray by increment for all indicies less than MaxIndex **/
__global__ void incrementKernel(float* outArray,float* inArray, int MaxIndex, float increment){
//the objects (gridDim,blockIdx,blockDim,threadIdx) are already defined:
int threadIndex = blockIdx.x*blockDim.x + threadIdx.x;
if(threadIndex < MaxIndex){ //keep it safe
outArray[threadIndex] = AddNum(inArray[threadIndex], increment);
}
}
/***** MAIN *****/
int main(int argc, char* argv[]){
parseArguments(argc, argv); //this will set the global variables
//Device array pointers
float* inArray_dev; //set to zero to avoid compile warnings
float* outArray_dev;
//Host array pointers
float* inArray_host;
float* outArray_host;
//initialize arrays on host (using c++)
inArray_host = new float[_ArraySize]; //equiv. to (float*)malloc(sizeof(float)*ARRAY_SIZE);
outArray_host = new float[_ArraySize];
//fill
fill(inArray_host, inArray_host+_ArraySize, 1.0f); //fill with ones
fill(outArray_host, outArray_host+_ArraySize, 0.0f); //fill with zeros
//initialize arrays on device (GPU)
cudaMalloc((void**)&inArray_dev, sizeof(float)*_ArraySize);
CHECK_CUDA_ERROR();
cudaMalloc((void**)&outArray_dev, sizeof(float)*_ArraySize);
CHECK_CUDA_ERROR();
//fill
cudaMemset(inArray_dev, sizeof(float)*_ArraySize, 0); //set input array to zero (must be a byte value)
CHECK_CUDA_ERROR();
cudaMemset(outArray_dev, sizeof(float)*_ArraySize, 0); //set output array to zero (must be a byte value)
CHECK_CUDA_ERROR();
//copy input array to device
//cudaMemcpy(DestinationPointer, SourcePointer, NumberOfBytes, cudaMemcpy[Host|Device]To[Host|Device]);
cudaMemcpy(inArray_dev, inArray_host, sizeof(float)*_ArraySize, cudaMemcpyHostToDevice);
//__LAUNCH KERNEL__
//in general this geometry can be 3D, but for now we are just indexing a linear array
int threadsPerBlock = 512; //this is typically the max for most GPUs except Fermi
int blockCount;
//special case for small array size:
if(_ArraySize <= threadsPerBlock){
blockCount = 1;
}else{
blockCount = _ArraySize/threadsPerBlock + 1; //max block size
}
incrementKernel <<< blockCount,threadsPerBlock >>> (outArray_dev, inArray_dev, _ArraySize, _IncrementValue);
cudaThreadSynchronize();
CHECK_CUDA_ERROR();
// copy back results
cudaMemcpy(outArray_host, outArray_dev, sizeof(float)*_ArraySize, cudaMemcpyDeviceToHost);
CHECK_CUDA_ERROR();
ofstream outFileStream;
outFileStream.open(_OutputFile);
//print output
for(int i = 0; i<_ArraySize; i++){
outFileStream << outArray_host[i] << endl;
}
cout << "Data saved in file " << _OutputFile << endl;
//cleanup
outFileStream.close();
delete inArray_host; //like free()
delete outArray_host;
cudaFree(inArray_dev);
cudaFree(outArray_dev);
} | #include <hip/hip_runtime.h>
#include <iostream>
using std::cout;
using std::endl;
#include<fstream>
using std::ofstream;
#include <algorithm>
using std::fill;
/***** ERROR CHECKING MACRO *****/
hipError_t _TempErrorCode;
#define CHECK_CUDA_ERROR() _TempErrorCode = hipGetLastError(); if(_TempErrorCode) fprintf(stderr,"!!CUDA ERROR in %s at line %d : %s\n",__FILE__,__LINE__,hipGetErrorString(_TempErrorCode));
/***** CUSTOM COMMAND LINE ARGUMENT PARSING *****/
//list of global variables (with default values)
int NumberOfArgs = 1; //how many constants are listed below
// you can add your own global variables to be parsed here
// (I start with underline to distiguish that it is a global variable):
int _ArraySize = 1024;
float _IncrementValue = 1.0f;
char _OutputFile[] = "output.txt";
//this will display the global variable values before program starts running
void displayGlobals(void){
cout<<"Setting ArraysSize to " << _ArraySize << endl;
cout<<"Setting IncrementValue to " << _IncrementValue << endl;
}
//this parses the command line arguments
void parseArguments(int arg_count, char* args[]){
//the first argument is always the program
cout << "Running (" << args[0] << ")" << endl;
if(arg_count > NumberOfArgs){
// add your string to whatever parsing here
_ArraySize = atoi(args[1]);
_IncrementValue = atof(args[2]);
//for strings just copy the pointer? (address):
//OutputFile = args[3];
displayGlobals();
}else{
//output usage
cout << "Usage: "<< args[0] << " <ArraySize> <IncrementValue> " << endl;// <OutputFile>" << endl;
//show default values
displayGlobals();
}
}
/***** A DEVICE FUNCTION *****/
__device__ float AddNum(float a, float b){
return a + b;
}
/***** CUDA KERNEL ******/
/** this function increments the inArray by increment for all indicies less than MaxIndex **/
__global__ void incrementKernel(float* outArray,float* inArray, int MaxIndex, float increment){
//the objects (gridDim,blockIdx,blockDim,threadIdx) are already defined:
int threadIndex = blockIdx.x*blockDim.x + threadIdx.x;
if(threadIndex < MaxIndex){ //keep it safe
outArray[threadIndex] = AddNum(inArray[threadIndex], increment);
}
}
/***** MAIN *****/
int main(int argc, char* argv[]){
parseArguments(argc, argv); //this will set the global variables
//Device array pointers
float* inArray_dev; //set to zero to avoid compile warnings
float* outArray_dev;
//Host array pointers
float* inArray_host;
float* outArray_host;
//initialize arrays on host (using c++)
inArray_host = new float[_ArraySize]; //equiv. to (float*)malloc(sizeof(float)*ARRAY_SIZE);
outArray_host = new float[_ArraySize];
//fill
fill(inArray_host, inArray_host+_ArraySize, 1.0f); //fill with ones
fill(outArray_host, outArray_host+_ArraySize, 0.0f); //fill with zeros
//initialize arrays on device (GPU)
hipMalloc((void**)&inArray_dev, sizeof(float)*_ArraySize);
CHECK_CUDA_ERROR();
hipMalloc((void**)&outArray_dev, sizeof(float)*_ArraySize);
CHECK_CUDA_ERROR();
//fill
hipMemset(inArray_dev, sizeof(float)*_ArraySize, 0); //set input array to zero (must be a byte value)
CHECK_CUDA_ERROR();
hipMemset(outArray_dev, sizeof(float)*_ArraySize, 0); //set output array to zero (must be a byte value)
CHECK_CUDA_ERROR();
//copy input array to device
//cudaMemcpy(DestinationPointer, SourcePointer, NumberOfBytes, cudaMemcpy[Host|Device]To[Host|Device]);
hipMemcpy(inArray_dev, inArray_host, sizeof(float)*_ArraySize, hipMemcpyHostToDevice);
//__LAUNCH KERNEL__
//in general this geometry can be 3D, but for now we are just indexing a linear array
int threadsPerBlock = 512; //this is typically the max for most GPUs except Fermi
int blockCount;
//special case for small array size:
if(_ArraySize <= threadsPerBlock){
blockCount = 1;
}else{
blockCount = _ArraySize/threadsPerBlock + 1; //max block size
}
incrementKernel <<< blockCount,threadsPerBlock >>> (outArray_dev, inArray_dev, _ArraySize, _IncrementValue);
hipDeviceSynchronize();
CHECK_CUDA_ERROR();
// copy back results
hipMemcpy(outArray_host, outArray_dev, sizeof(float)*_ArraySize, hipMemcpyDeviceToHost);
CHECK_CUDA_ERROR();
ofstream outFileStream;
outFileStream.open(_OutputFile);
//print output
for(int i = 0; i<_ArraySize; i++){
outFileStream << outArray_host[i] << endl;
}
cout << "Data saved in file " << _OutputFile << endl;
//cleanup
outFileStream.close();
delete inArray_host; //like free()
delete outArray_host;
hipFree(inArray_dev);
hipFree(outArray_dev);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using std::cout;
using std::endl;
#include<fstream>
using std::ofstream;
#include <algorithm>
using std::fill;
/***** ERROR CHECKING MACRO *****/
hipError_t _TempErrorCode;
#define CHECK_CUDA_ERROR() _TempErrorCode = hipGetLastError(); if(_TempErrorCode) fprintf(stderr,"!!CUDA ERROR in %s at line %d : %s\n",__FILE__,__LINE__,hipGetErrorString(_TempErrorCode));
/***** CUSTOM COMMAND LINE ARGUMENT PARSING *****/
//list of global variables (with default values)
int NumberOfArgs = 1; //how many constants are listed below
// you can add your own global variables to be parsed here
// (I start with underline to distiguish that it is a global variable):
int _ArraySize = 1024;
float _IncrementValue = 1.0f;
char _OutputFile[] = "output.txt";
//this will display the global variable values before program starts running
void displayGlobals(void){
cout<<"Setting ArraysSize to " << _ArraySize << endl;
cout<<"Setting IncrementValue to " << _IncrementValue << endl;
}
//this parses the command line arguments
void parseArguments(int arg_count, char* args[]){
//the first argument is always the program
cout << "Running (" << args[0] << ")" << endl;
if(arg_count > NumberOfArgs){
// add your string to whatever parsing here
_ArraySize = atoi(args[1]);
_IncrementValue = atof(args[2]);
//for strings just copy the pointer? (address):
//OutputFile = args[3];
displayGlobals();
}else{
//output usage
cout << "Usage: "<< args[0] << " <ArraySize> <IncrementValue> " << endl;// <OutputFile>" << endl;
//show default values
displayGlobals();
}
}
/***** A DEVICE FUNCTION *****/
__device__ float AddNum(float a, float b){
return a + b;
}
/***** CUDA KERNEL ******/
/** this function increments the inArray by increment for all indicies less than MaxIndex **/
__global__ void incrementKernel(float* outArray,float* inArray, int MaxIndex, float increment){
//the objects (gridDim,blockIdx,blockDim,threadIdx) are already defined:
int threadIndex = blockIdx.x*blockDim.x + threadIdx.x;
if(threadIndex < MaxIndex){ //keep it safe
outArray[threadIndex] = AddNum(inArray[threadIndex], increment);
}
}
/***** MAIN *****/
int main(int argc, char* argv[]){
parseArguments(argc, argv); //this will set the global variables
//Device array pointers
float* inArray_dev; //set to zero to avoid compile warnings
float* outArray_dev;
//Host array pointers
float* inArray_host;
float* outArray_host;
//initialize arrays on host (using c++)
inArray_host = new float[_ArraySize]; //equiv. to (float*)malloc(sizeof(float)*ARRAY_SIZE);
outArray_host = new float[_ArraySize];
//fill
fill(inArray_host, inArray_host+_ArraySize, 1.0f); //fill with ones
fill(outArray_host, outArray_host+_ArraySize, 0.0f); //fill with zeros
//initialize arrays on device (GPU)
hipMalloc((void**)&inArray_dev, sizeof(float)*_ArraySize);
CHECK_CUDA_ERROR();
hipMalloc((void**)&outArray_dev, sizeof(float)*_ArraySize);
CHECK_CUDA_ERROR();
//fill
hipMemset(inArray_dev, sizeof(float)*_ArraySize, 0); //set input array to zero (must be a byte value)
CHECK_CUDA_ERROR();
hipMemset(outArray_dev, sizeof(float)*_ArraySize, 0); //set output array to zero (must be a byte value)
CHECK_CUDA_ERROR();
//copy input array to device
//cudaMemcpy(DestinationPointer, SourcePointer, NumberOfBytes, cudaMemcpy[Host|Device]To[Host|Device]);
hipMemcpy(inArray_dev, inArray_host, sizeof(float)*_ArraySize, hipMemcpyHostToDevice);
//__LAUNCH KERNEL__
//in general this geometry can be 3D, but for now we are just indexing a linear array
int threadsPerBlock = 512; //this is typically the max for most GPUs except Fermi
int blockCount;
//special case for small array size:
if(_ArraySize <= threadsPerBlock){
blockCount = 1;
}else{
blockCount = _ArraySize/threadsPerBlock + 1; //max block size
}
incrementKernel <<< blockCount,threadsPerBlock >>> (outArray_dev, inArray_dev, _ArraySize, _IncrementValue);
hipDeviceSynchronize();
CHECK_CUDA_ERROR();
// copy back results
hipMemcpy(outArray_host, outArray_dev, sizeof(float)*_ArraySize, hipMemcpyDeviceToHost);
CHECK_CUDA_ERROR();
ofstream outFileStream;
outFileStream.open(_OutputFile);
//print output
for(int i = 0; i<_ArraySize; i++){
outFileStream << outArray_host[i] << endl;
}
cout << "Data saved in file " << _OutputFile << endl;
//cleanup
outFileStream.close();
delete inArray_host; //like free()
delete outArray_host;
hipFree(inArray_dev);
hipFree(outArray_dev);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15incrementKernelPfS_if
.globl _Z15incrementKernelPfS_if
.p2align 8
.type _Z15incrementKernelPfS_if,@function
_Z15incrementKernelPfS_if:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15incrementKernelPfS_if
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15incrementKernelPfS_if, .Lfunc_end0-_Z15incrementKernelPfS_if
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15incrementKernelPfS_if
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15incrementKernelPfS_if.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using std::cout;
using std::endl;
#include<fstream>
using std::ofstream;
#include <algorithm>
using std::fill;
/***** ERROR CHECKING MACRO *****/
hipError_t _TempErrorCode;
#define CHECK_CUDA_ERROR() _TempErrorCode = hipGetLastError(); if(_TempErrorCode) fprintf(stderr,"!!CUDA ERROR in %s at line %d : %s\n",__FILE__,__LINE__,hipGetErrorString(_TempErrorCode));
/***** CUSTOM COMMAND LINE ARGUMENT PARSING *****/
//list of global variables (with default values)
int NumberOfArgs = 1; //how many constants are listed below
// you can add your own global variables to be parsed here
// (I start with underline to distiguish that it is a global variable):
int _ArraySize = 1024;
float _IncrementValue = 1.0f;
char _OutputFile[] = "output.txt";
//this will display the global variable values before program starts running
void displayGlobals(void){
cout<<"Setting ArraysSize to " << _ArraySize << endl;
cout<<"Setting IncrementValue to " << _IncrementValue << endl;
}
//this parses the command line arguments
void parseArguments(int arg_count, char* args[]){
//the first argument is always the program
cout << "Running (" << args[0] << ")" << endl;
if(arg_count > NumberOfArgs){
// add your string to whatever parsing here
_ArraySize = atoi(args[1]);
_IncrementValue = atof(args[2]);
//for strings just copy the pointer? (address):
//OutputFile = args[3];
displayGlobals();
}else{
//output usage
cout << "Usage: "<< args[0] << " <ArraySize> <IncrementValue> " << endl;// <OutputFile>" << endl;
//show default values
displayGlobals();
}
}
/***** A DEVICE FUNCTION *****/
__device__ float AddNum(float a, float b){
return a + b;
}
/***** CUDA KERNEL ******/
/** this function increments the inArray by increment for all indicies less than MaxIndex **/
__global__ void incrementKernel(float* outArray,float* inArray, int MaxIndex, float increment){
//the objects (gridDim,blockIdx,blockDim,threadIdx) are already defined:
int threadIndex = blockIdx.x*blockDim.x + threadIdx.x;
if(threadIndex < MaxIndex){ //keep it safe
outArray[threadIndex] = AddNum(inArray[threadIndex], increment);
}
}
/***** MAIN *****/
int main(int argc, char* argv[]){
parseArguments(argc, argv); //this will set the global variables
//Device array pointers
float* inArray_dev; //set to zero to avoid compile warnings
float* outArray_dev;
//Host array pointers
float* inArray_host;
float* outArray_host;
//initialize arrays on host (using c++)
inArray_host = new float[_ArraySize]; //equiv. to (float*)malloc(sizeof(float)*ARRAY_SIZE);
outArray_host = new float[_ArraySize];
//fill
fill(inArray_host, inArray_host+_ArraySize, 1.0f); //fill with ones
fill(outArray_host, outArray_host+_ArraySize, 0.0f); //fill with zeros
//initialize arrays on device (GPU)
hipMalloc((void**)&inArray_dev, sizeof(float)*_ArraySize);
CHECK_CUDA_ERROR();
hipMalloc((void**)&outArray_dev, sizeof(float)*_ArraySize);
CHECK_CUDA_ERROR();
//fill
hipMemset(inArray_dev, sizeof(float)*_ArraySize, 0); //set input array to zero (must be a byte value)
CHECK_CUDA_ERROR();
hipMemset(outArray_dev, sizeof(float)*_ArraySize, 0); //set output array to zero (must be a byte value)
CHECK_CUDA_ERROR();
//copy input array to device
//cudaMemcpy(DestinationPointer, SourcePointer, NumberOfBytes, cudaMemcpy[Host|Device]To[Host|Device]);
hipMemcpy(inArray_dev, inArray_host, sizeof(float)*_ArraySize, hipMemcpyHostToDevice);
//__LAUNCH KERNEL__
//in general this geometry can be 3D, but for now we are just indexing a linear array
int threadsPerBlock = 512; //this is typically the max for most GPUs except Fermi
int blockCount;
//special case for small array size:
if(_ArraySize <= threadsPerBlock){
blockCount = 1;
}else{
blockCount = _ArraySize/threadsPerBlock + 1; //max block size
}
incrementKernel <<< blockCount,threadsPerBlock >>> (outArray_dev, inArray_dev, _ArraySize, _IncrementValue);
hipDeviceSynchronize();
CHECK_CUDA_ERROR();
// copy back results
hipMemcpy(outArray_host, outArray_dev, sizeof(float)*_ArraySize, hipMemcpyDeviceToHost);
CHECK_CUDA_ERROR();
ofstream outFileStream;
outFileStream.open(_OutputFile);
//print output
for(int i = 0; i<_ArraySize; i++){
outFileStream << outArray_host[i] << endl;
}
cout << "Data saved in file " << _OutputFile << endl;
//cleanup
outFileStream.close();
delete inArray_host; //like free()
delete outArray_host;
hipFree(inArray_dev);
hipFree(outArray_dev);
} | .text
.file "cudaExample.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z14displayGlobalsv # -- Begin function _Z14displayGlobalsv
.p2align 4, 0x90
.type _Z14displayGlobalsv,@function
_Z14displayGlobalsv: # @_Z14displayGlobalsv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl _ArraySize(%rip), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_9
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss _IncrementValue(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i2
cmpb $0, 56(%rbx)
je .LBB0_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB0_8
.LBB0_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit5
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB0_9:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z14displayGlobalsv, .Lfunc_end0-_Z14displayGlobalsv
.cfi_endproc
# -- End function
.globl _Z14parseArgumentsiPPc # -- Begin function _Z14parseArgumentsiPPc
.p2align 4, 0x90
.type _Z14parseArgumentsiPPc,@function
_Z14parseArgumentsiPPc: # @_Z14parseArgumentsiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %r14
testq %r14, %r14
je .LBB1_1
# %bb.2:
movq %r14, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_3
.LBB1_1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_18
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_6
# %bb.5:
movzbl 67(%r14), %eax
jmp .LBB1_7
.LBB1_6:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl %ebp, NumberOfArgs(%rip)
jge .LBB1_9
# %bb.8:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, _ArraySize(%rip)
movq 16(%rbx), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, _IncrementValue(%rip)
jmp .LBB1_17
.LBB1_9:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rbx
testq %rbx, %rbx
je .LBB1_10
# %bb.11:
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_12
.LBB1_10:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit5
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_18
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %eax
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_17:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _Z14displayGlobalsv # TAILCALL
.LBB1_18:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z14parseArgumentsiPPc, .Lfunc_end1-_Z14parseArgumentsiPPc
.cfi_endproc
# -- End function
.globl _Z30__device_stub__incrementKernelPfS_if # -- Begin function _Z30__device_stub__incrementKernelPfS_if
.p2align 4, 0x90
.type _Z30__device_stub__incrementKernelPfS_if,@function
_Z30__device_stub__incrementKernelPfS_if: # @_Z30__device_stub__incrementKernelPfS_if
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15incrementKernelPfS_if, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z30__device_stub__incrementKernelPfS_if, .Lfunc_end2-_Z30__device_stub__incrementKernelPfS_if
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $616, %rsp # imm = 0x268
.cfi_def_cfa_offset 672
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
callq _Z14parseArgumentsiPPc
movslq _ArraySize(%rip), %r12
leaq (,%r12,4), %r15
testq %r12, %r12
movq $-1, %r14
cmovnsq %r15, %r14
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Znam
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Znam
movq %rax, %r14
testq %r12, %r12
je .LBB3_4
# %bb.1: # %.lr.ph.i.i.i.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax) # imm = 0x3F800000
addq $4, %rax
cmpq %rax, %r15
jne .LBB3_2
# %bb.3: # %.lr.ph.i.i.i40.preheader
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
.LBB3_4: # %_ZSt4fillIPffEvT_S1_RKT0_.exit43
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
.cfi_escape 0x2e, 0x00
callq hipGetLastError
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .LBB3_5
.LBB3_6:
movslq _ArraySize(%rip), %rsi
shlq $2, %rsi
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipMalloc
.cfi_escape 0x2e, 0x00
callq hipGetLastError
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .LBB3_7
.LBB3_8:
movq 16(%rsp), %rdi
movl _ArraySize(%rip), %esi
shll $2, %esi
.cfi_escape 0x2e, 0x00
xorl %edx, %edx
callq hipMemset
.cfi_escape 0x2e, 0x00
callq hipGetLastError
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .LBB3_9
.LBB3_10:
movq 8(%rsp), %rdi
movl _ArraySize(%rip), %esi
shll $2, %esi
.cfi_escape 0x2e, 0x00
xorl %edx, %edx
callq hipMemset
.cfi_escape 0x2e, 0x00
callq hipGetLastError
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .LBB3_11
.LBB3_12:
movq 16(%rsp), %rdi
movslq _ArraySize(%rip), %rdx
shlq $2, %rdx
.cfi_escape 0x2e, 0x00
movl $1, %ebp
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl _ArraySize(%rip), %eax
movl %eax, %edi
shrl $9, %edi
incl %edi
cmpl $513, %eax # imm = 0x201
cmovll %ebp, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_14
# %bb.13:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movl _ArraySize(%rip), %edx
movss _IncrementValue(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
movss %xmm0, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z15incrementKernelPfS_if, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_14:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.cfi_escape 0x2e, 0x00
callq hipGetLastError
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .LBB3_15
.LBB3_16:
movq 8(%rsp), %rsi
movslq _ArraySize(%rip), %rdx
shlq $2, %rdx
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
callq hipGetLastError
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .LBB3_17
.LBB3_18:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %r12
movq %r12, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
leaq 104(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_OutputFile, %esi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.19: # %.noexc
movq 96(%rsp), %rcx
addq -24(%rcx), %r12
xorl %esi, %esi
testq %rax, %rax
jne .LBB3_21
# %bb.20:
movl 32(%r12), %esi
orl $4, %esi
.LBB3_21: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.22: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
cmpl $0, _ArraySize(%rip)
jle .LBB3_35
# %bb.23: # %.lr.ph.preheader
xorl %r15d, %r15d
leaq 96(%rsp), %r12
.p2align 4, 0x90
.LBB3_24: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp4:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp5:
# %bb.25: # %_ZNSolsEf.exit
# in Loop: Header=BB3_24 Depth=1
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB3_26
# %bb.28: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB3_24 Depth=1
cmpb $0, 56(%rbp)
je .LBB3_30
# %bb.29: # in Loop: Header=BB3_24 Depth=1
movzbl 67(%rbp), %eax
jmp .LBB3_32
.p2align 4, 0x90
.LBB3_30: # in Loop: Header=BB3_24 Depth=1
.Ltmp6:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp7:
# %bb.31: # %.noexc58
# in Loop: Header=BB3_24 Depth=1
movq (%rbp), %rax
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp9:
.LBB3_32: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB3_24 Depth=1
.Ltmp10:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
.Ltmp11:
# %bb.33: # %.noexc60
# in Loop: Header=BB3_24 Depth=1
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp13:
# %bb.34: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB3_24 Depth=1
incq %r15
movslq _ArraySize(%rip), %rax
cmpq %rax, %r15
jl .LBB3_24
.LBB3_35: # %._crit_edge
.Ltmp15:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp16:
# %bb.36: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.cfi_escape 0x2e, 0x00
movl $_OutputFile, %edi
callq strlen
.Ltmp17:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $_OutputFile, %esi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp18:
# %bb.37: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit50
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_38
# %bb.42: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i63
cmpb $0, 56(%r12)
je .LBB3_44
# %bb.43:
movzbl 67(%r12), %eax
jmp .LBB3_46
.LBB3_44:
.Ltmp19:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp20:
# %bb.45: # %.noexc68
movq (%r12), %rax
.Ltmp21:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp22:
.LBB3_46: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i65
.Ltmp23:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp24:
# %bb.47: # %.noexc70
.Ltmp25:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp26:
# %bb.48: # %_ZNSolsEPFRSoS_E.exit52
.Ltmp27:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp28:
# %bb.49: # %.noexc54
testq %rax, %rax
jne .LBB3_51
# %bb.50:
movq 96(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $96, %rdi
movl 128(%rsp,%rax), %esi
orl $4, %esi
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp30:
.LBB3_51: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
movq 16(%rsp), %rdi
.Ltmp31:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp32:
# %bb.52:
movq 8(%rsp), %rdi
.Ltmp33:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp34:
# %bb.53:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $616, %rsp # imm = 0x268
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_5:
.cfi_def_cfa_offset 672
movq stderr(%rip), %r15
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movq %r15, %rdi
movl $103, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB3_6
.LBB3_7:
movq stderr(%rip), %r15
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movq %r15, %rdi
movl $105, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB3_8
.LBB3_9:
movq stderr(%rip), %r15
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movq %r15, %rdi
movl $109, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB3_10
.LBB3_11:
movq stderr(%rip), %r15
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movq %r15, %rdi
movl $111, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB3_12
.LBB3_15:
movq stderr(%rip), %r15
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movq %r15, %rdi
movl $131, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB3_16
.LBB3_17:
movq stderr(%rip), %r15
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movq %r15, %rdi
movl $135, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB3_18
.LBB3_26:
.Ltmp38:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp39:
# %bb.27: # %.noexc57
.LBB3_38:
.Ltmp35:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp36:
# %bb.41: # %.noexc67
.LBB3_54:
.Ltmp37:
jmp .LBB3_55
.LBB3_40: # %.loopexit.split-lp
.Ltmp40:
jmp .LBB3_55
.LBB3_39: # %.loopexit
.Ltmp14:
.LBB3_55:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp13-.Ltmp4 # Call between .Ltmp4 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp34-.Ltmp15 # Call between .Ltmp15 and .Ltmp34
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp38-.Ltmp34 # Call between .Ltmp34 and .Ltmp38
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp36-.Ltmp35 # Call between .Ltmp35 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end3-.Ltmp36 # Call between .Ltmp36 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15incrementKernelPfS_if, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _TempErrorCode,@object # @_TempErrorCode
.bss
.globl _TempErrorCode
.p2align 2, 0x0
_TempErrorCode:
.long 0 # 0x0
.size _TempErrorCode, 4
.type NumberOfArgs,@object # @NumberOfArgs
.data
.globl NumberOfArgs
.p2align 2, 0x0
NumberOfArgs:
.long 1 # 0x1
.size NumberOfArgs, 4
.type _ArraySize,@object # @_ArraySize
.globl _ArraySize
.p2align 2, 0x0
_ArraySize:
.long 1024 # 0x400
.size _ArraySize, 4
.type _IncrementValue,@object # @_IncrementValue
.globl _IncrementValue
.p2align 2, 0x0
_IncrementValue:
.long 0x3f800000 # float 1
.size _IncrementValue, 4
.type _OutputFile,@object # @_OutputFile
.globl _OutputFile
_OutputFile:
.asciz "output.txt"
.size _OutputFile, 11
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Setting ArraysSize to "
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Setting IncrementValue to "
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Running ("
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Usage: "
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " <ArraySize> <IncrementValue> "
.size .L.str.5, 31
.type _Z15incrementKernelPfS_if,@object # @_Z15incrementKernelPfS_if
.section .rodata,"a",@progbits
.globl _Z15incrementKernelPfS_if
.p2align 3, 0x0
_Z15incrementKernelPfS_if:
.quad _Z30__device_stub__incrementKernelPfS_if
.size _Z15incrementKernelPfS_if, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "!!CUDA ERROR in %s at line %d : %s\n"
.size .L.str.6, 36
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/rudm818/ucsd-comp-phys/master/142-242/cudaExample/cudaExample.hip"
.size .L.str.7, 123
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Data saved in file "
.size .L.str.8, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15incrementKernelPfS_if"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__incrementKernelPfS_if
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _OutputFile
.addrsig_sym _ZSt4cout
.addrsig_sym _Z15incrementKernelPfS_if
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15incrementKernelPfS_if
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FADD R7, R2, c[0x0][0x174] ; /* 0x00005d0002077621 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15incrementKernelPfS_if
.globl _Z15incrementKernelPfS_if
.p2align 8
.type _Z15incrementKernelPfS_if,@function
_Z15incrementKernelPfS_if:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15incrementKernelPfS_if
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15incrementKernelPfS_if, .Lfunc_end0-_Z15incrementKernelPfS_if
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15incrementKernelPfS_if
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15incrementKernelPfS_if.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cf54d_00000000-6_cudaExample.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Setting ArraysSize to "
.LC1:
.string "Setting IncrementValue to "
.text
.globl _Z14displayGlobalsv
.type _Z14displayGlobalsv, @function
_Z14displayGlobalsv:
.LFB4054:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $22, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl _ArraySize(%rip), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L11
cmpb $0, 56(%rbp)
je .L5
movzbl 67(%rbp), %esi
.L6:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $26, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd _IncrementValue(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L12
cmpb $0, 56(%rbp)
je .L8
movzbl 67(%rbp), %esi
.L9:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L5:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L6
.L12:
call _ZSt16__throw_bad_castv@PLT
.L8:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L9
.cfi_endproc
.LFE4054:
.size _Z14displayGlobalsv, .-_Z14displayGlobalsv
.section .rodata.str1.1
.LC2:
.string "Running ("
.LC3:
.string ")"
.LC4:
.string "Usage: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string " <ArraySize> <IncrementValue> "
.text
.globl _Z14parseArgumentsiPPc
.type _Z14parseArgumentsiPPc, @function
_Z14parseArgumentsiPPc:
.LFB4055:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %r12d
movq %rsi, %rbx
movl $9, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rbp
testq %rbp, %rbp
je .L27
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L15:
movl $1, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .L28
cmpb $0, 56(%rbp)
je .L17
movzbl 67(%rbp), %esi
.L18:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
cmpl %r12d, NumberOfArgs(%rip)
jge .L19
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, _ArraySize(%rip)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, _IncrementValue(%rip)
call _Z14displayGlobalsv
.L13:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L15
.L28:
call _ZSt16__throw_bad_castv@PLT
.L17:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L18
.L19:
movl $7, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rbx
testq %rbx, %rbx
je .L29
movq %rbx, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L22:
movl $30, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L30
cmpb $0, 56(%rbx)
je .L24
movzbl 67(%rbx), %esi
.L25:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call _Z14displayGlobalsv
jmp .L13
.L29:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L22
.L30:
call _ZSt16__throw_bad_castv@PLT
.L24:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L25
.cfi_endproc
.LFE4055:
.size _Z14parseArgumentsiPPc, .-_Z14parseArgumentsiPPc
.globl _Z6AddNumff
.type _Z6AddNumff, @function
_Z6AddNumff:
.LFB4056:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4056:
.size _Z6AddNumff, .-_Z6AddNumff
.globl _Z39__device_stub__Z15incrementKernelPfS_ifPfS_if
.type _Z39__device_stub__Z15incrementKernelPfS_ifPfS_if, @function
_Z39__device_stub__Z15incrementKernelPfS_ifPfS_if:
.LFB4082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15incrementKernelPfS_if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4082:
.size _Z39__device_stub__Z15incrementKernelPfS_ifPfS_if, .-_Z39__device_stub__Z15incrementKernelPfS_ifPfS_if
.globl _Z15incrementKernelPfS_if
.type _Z15incrementKernelPfS_if, @function
_Z15incrementKernelPfS_if:
.LFB4083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15incrementKernelPfS_ifPfS_if
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4083:
.size _Z15incrementKernelPfS_if, .-_Z15incrementKernelPfS_if
.section .rodata.str1.1
.LC6:
.string "_Z15incrementKernelPfS_if"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z15incrementKernelPfS_if(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8
.align 8
.LC9:
.string "/home/ubuntu/Datasets/stackv2/train-structured/rudm818/ucsd-comp-phys/master/142-242/cudaExample/cudaExample.cu"
.align 8
.LC10:
.string "!!CUDA ERROR in %s at line %d : %s\n"
.section .rodata.str1.1
.LC11:
.string "Data saved in file "
.text
.globl main
.type main, @function
main:
.LFB4057:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4057
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $584, %rsp
.cfi_def_cfa_offset 640
movq %fs:40, %rax
movq %rax, 568(%rsp)
xorl %eax, %eax
.LEHB0:
call _Z14parseArgumentsiPPc
movslq _ArraySize(%rip), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L44
salq $2, %rdi
call _Znam@PLT
movq %rax, %r15
movslq _ArraySize(%rip), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L80
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
movslq _ArraySize(%rip), %rsi
salq $2, %rsi
leaq (%r15,%rsi), %rdx
movq %r15, %rax
movss .LC7(%rip), %xmm0
cmpq %r15, %rdx
je .L49
.L48:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L48
.L49:
leaq 0(%r13,%rsi), %rdx
cmpq %r13, %rdx
je .L51
movq %r13, %rax
.L52:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L52
.L51:
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .L81
.L53:
movslq _ArraySize(%rip), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .L82
.L54:
movl _ArraySize(%rip), %eax
leal 0(,%rax,4), %esi
movl $0, %edx
movq 8(%rsp), %rdi
call cudaMemset@PLT
call cudaGetLastError@PLT
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .L83
.L55:
movl _ArraySize(%rip), %eax
leal 0(,%rax,4), %esi
movl $0, %edx
movq 16(%rsp), %rdi
call cudaMemset@PLT
call cudaGetLastError@PLT
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .L84
.L56:
movslq _ArraySize(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl _ArraySize(%rip), %eax
movl $1, %edx
cmpl $512, %eax
jle .L57
movl $512, %ecx
cltd
idivl %ecx
leal 1(%rax), %edx
.L57:
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %edx, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L58:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .L86
.L59:
movslq _ArraySize(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .L87
.L60:
leaq 48(%rsp), %rbx
movq %rbx, %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $16, %edx
leaq _OutputFile(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
.LEHE1:
jmp .L88
.L44:
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L47
call __stack_chk_fail@PLT
.L47:
.LEHB2:
call __cxa_throw_bad_array_new_length@PLT
.L80:
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L50
call __stack_chk_fail@PLT
.L50:
call __cxa_throw_bad_array_new_length@PLT
.L81:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $103, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L53
.L82:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $105, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L54
.L83:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $109, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L55
.L84:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $111, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L56
.L85:
movss _IncrementValue(%rip), %xmm0
movl _ArraySize(%rip), %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z39__device_stub__Z15incrementKernelPfS_ifPfS_if
jmp .L58
.L86:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $131, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L59
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $135, %r8d
leaq .LC9(%rip), %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.LEHE2:
jmp .L60
.L88:
cmpl $0, _ArraySize(%rip)
jle .L61
movl $0, %r12d
movq %rbx, %r14
jmp .L66
.L92:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L89
cmpb $0, 56(%rbp)
je .L64
movzbl 67(%rbp), %esi
.L65:
movsbl %sil, %esi
movq %rbx, %rdi
.LEHB3:
call _ZNSo3putEc@PLT
jmp .L90
.L89:
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L91
call _ZSt16__throw_bad_castv@PLT
.L72:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L68
call __stack_chk_fail@PLT
.L91:
call __stack_chk_fail@PLT
.L64:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L65
.L90:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %r12
cmpl %r12d, _ArraySize(%rip)
jle .L61
.L66:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%r12,4), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L92
.L61:
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq _OutputFile(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 48(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movl $4, %esi
movq %r15, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r13, %rdi
call _ZdlPvm@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 48(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L93
movl $0, %eax
addq $584, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L93:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4057:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4057-.LLSDACSB4057
.LLSDACSB4057:
.uleb128 .LEHB0-.LFB4057
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4057
.uleb128 .LEHE1-.LEHB1
.uleb128 .L72-.LFB4057
.uleb128 0
.uleb128 .LEHB2-.LFB4057
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4057
.uleb128 .LEHE3-.LEHB3
.uleb128 .L72-.LFB4057
.uleb128 0
.uleb128 .LEHB4-.LFB4057
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4057:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl _OutputFile
.data
.align 8
.type _OutputFile, @object
.size _OutputFile, 11
_OutputFile:
.string "output.txt"
.globl _IncrementValue
.align 4
.type _IncrementValue, @object
.size _IncrementValue, 4
_IncrementValue:
.long 1065353216
.globl _ArraySize
.align 4
.type _ArraySize, @object
.size _ArraySize, 4
_ArraySize:
.long 1024
.globl NumberOfArgs
.align 4
.type NumberOfArgs, @object
.size NumberOfArgs, 4
NumberOfArgs:
.long 1
.globl _TempErrorCode
.bss
.align 4
.type _TempErrorCode, @object
.size _TempErrorCode, 4
_TempErrorCode:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1065353216
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaExample.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z14displayGlobalsv # -- Begin function _Z14displayGlobalsv
.p2align 4, 0x90
.type _Z14displayGlobalsv,@function
_Z14displayGlobalsv: # @_Z14displayGlobalsv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl _ArraySize(%rip), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_9
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss _IncrementValue(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i2
cmpb $0, 56(%rbx)
je .LBB0_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB0_8
.LBB0_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit5
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB0_9:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z14displayGlobalsv, .Lfunc_end0-_Z14displayGlobalsv
.cfi_endproc
# -- End function
.globl _Z14parseArgumentsiPPc # -- Begin function _Z14parseArgumentsiPPc
.p2align 4, 0x90
.type _Z14parseArgumentsiPPc,@function
_Z14parseArgumentsiPPc: # @_Z14parseArgumentsiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %r14
testq %r14, %r14
je .LBB1_1
# %bb.2:
movq %r14, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_3
.LBB1_1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_18
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_6
# %bb.5:
movzbl 67(%r14), %eax
jmp .LBB1_7
.LBB1_6:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl %ebp, NumberOfArgs(%rip)
jge .LBB1_9
# %bb.8:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, _ArraySize(%rip)
movq 16(%rbx), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, _IncrementValue(%rip)
jmp .LBB1_17
.LBB1_9:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rbx
testq %rbx, %rbx
je .LBB1_10
# %bb.11:
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_12
.LBB1_10:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit5
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_18
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %eax
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_17:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _Z14displayGlobalsv # TAILCALL
.LBB1_18:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z14parseArgumentsiPPc, .Lfunc_end1-_Z14parseArgumentsiPPc
.cfi_endproc
# -- End function
.globl _Z30__device_stub__incrementKernelPfS_if # -- Begin function _Z30__device_stub__incrementKernelPfS_if
.p2align 4, 0x90
.type _Z30__device_stub__incrementKernelPfS_if,@function
_Z30__device_stub__incrementKernelPfS_if: # @_Z30__device_stub__incrementKernelPfS_if
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15incrementKernelPfS_if, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z30__device_stub__incrementKernelPfS_if, .Lfunc_end2-_Z30__device_stub__incrementKernelPfS_if
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $616, %rsp # imm = 0x268
.cfi_def_cfa_offset 672
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
callq _Z14parseArgumentsiPPc
movslq _ArraySize(%rip), %r12
leaq (,%r12,4), %r15
testq %r12, %r12
movq $-1, %r14
cmovnsq %r15, %r14
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Znam
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Znam
movq %rax, %r14
testq %r12, %r12
je .LBB3_4
# %bb.1: # %.lr.ph.i.i.i.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax) # imm = 0x3F800000
addq $4, %rax
cmpq %rax, %r15
jne .LBB3_2
# %bb.3: # %.lr.ph.i.i.i40.preheader
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
.LBB3_4: # %_ZSt4fillIPffEvT_S1_RKT0_.exit43
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
.cfi_escape 0x2e, 0x00
callq hipGetLastError
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .LBB3_5
.LBB3_6:
movslq _ArraySize(%rip), %rsi
shlq $2, %rsi
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipMalloc
.cfi_escape 0x2e, 0x00
callq hipGetLastError
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .LBB3_7
.LBB3_8:
movq 16(%rsp), %rdi
movl _ArraySize(%rip), %esi
shll $2, %esi
.cfi_escape 0x2e, 0x00
xorl %edx, %edx
callq hipMemset
.cfi_escape 0x2e, 0x00
callq hipGetLastError
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .LBB3_9
.LBB3_10:
movq 8(%rsp), %rdi
movl _ArraySize(%rip), %esi
shll $2, %esi
.cfi_escape 0x2e, 0x00
xorl %edx, %edx
callq hipMemset
.cfi_escape 0x2e, 0x00
callq hipGetLastError
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .LBB3_11
.LBB3_12:
movq 16(%rsp), %rdi
movslq _ArraySize(%rip), %rdx
shlq $2, %rdx
.cfi_escape 0x2e, 0x00
movl $1, %ebp
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl _ArraySize(%rip), %eax
movl %eax, %edi
shrl $9, %edi
incl %edi
cmpl $513, %eax # imm = 0x201
cmovll %ebp, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_14
# %bb.13:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movl _ArraySize(%rip), %edx
movss _IncrementValue(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
movss %xmm0, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z15incrementKernelPfS_if, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_14:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.cfi_escape 0x2e, 0x00
callq hipGetLastError
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .LBB3_15
.LBB3_16:
movq 8(%rsp), %rsi
movslq _ArraySize(%rip), %rdx
shlq $2, %rdx
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
callq hipGetLastError
movl %eax, _TempErrorCode(%rip)
testl %eax, %eax
jne .LBB3_17
.LBB3_18:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %r12
movq %r12, %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev
leaq 104(%rsp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_OutputFile, %esi
movl $16, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.19: # %.noexc
movq 96(%rsp), %rcx
addq -24(%rcx), %r12
xorl %esi, %esi
testq %rax, %rax
jne .LBB3_21
# %bb.20:
movl 32(%r12), %esi
orl $4, %esi
.LBB3_21: # %.invoke
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.22: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
cmpl $0, _ArraySize(%rip)
jle .LBB3_35
# %bb.23: # %.lr.ph.preheader
xorl %r15d, %r15d
leaq 96(%rsp), %r12
.p2align 4, 0x90
.LBB3_24: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp4:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp5:
# %bb.25: # %_ZNSolsEf.exit
# in Loop: Header=BB3_24 Depth=1
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB3_26
# %bb.28: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB3_24 Depth=1
cmpb $0, 56(%rbp)
je .LBB3_30
# %bb.29: # in Loop: Header=BB3_24 Depth=1
movzbl 67(%rbp), %eax
jmp .LBB3_32
.p2align 4, 0x90
.LBB3_30: # in Loop: Header=BB3_24 Depth=1
.Ltmp6:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp7:
# %bb.31: # %.noexc58
# in Loop: Header=BB3_24 Depth=1
movq (%rbp), %rax
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp9:
.LBB3_32: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB3_24 Depth=1
.Ltmp10:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
.Ltmp11:
# %bb.33: # %.noexc60
# in Loop: Header=BB3_24 Depth=1
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp13:
# %bb.34: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB3_24 Depth=1
incq %r15
movslq _ArraySize(%rip), %rax
cmpq %rax, %r15
jl .LBB3_24
.LBB3_35: # %._crit_edge
.Ltmp15:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp16:
# %bb.36: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.cfi_escape 0x2e, 0x00
movl $_OutputFile, %edi
callq strlen
.Ltmp17:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $_OutputFile, %esi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp18:
# %bb.37: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit50
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_38
# %bb.42: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i63
cmpb $0, 56(%r12)
je .LBB3_44
# %bb.43:
movzbl 67(%r12), %eax
jmp .LBB3_46
.LBB3_44:
.Ltmp19:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp20:
# %bb.45: # %.noexc68
movq (%r12), %rax
.Ltmp21:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp22:
.LBB3_46: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i65
.Ltmp23:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp24:
# %bb.47: # %.noexc70
.Ltmp25:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp26:
# %bb.48: # %_ZNSolsEPFRSoS_E.exit52
.Ltmp27:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp28:
# %bb.49: # %.noexc54
testq %rax, %rax
jne .LBB3_51
# %bb.50:
movq 96(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $96, %rdi
movl 128(%rsp,%rax), %esi
orl $4, %esi
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp30:
.LBB3_51: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
movq 16(%rsp), %rdi
.Ltmp31:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp32:
# %bb.52:
movq 8(%rsp), %rdi
.Ltmp33:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp34:
# %bb.53:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $616, %rsp # imm = 0x268
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_5:
.cfi_def_cfa_offset 672
movq stderr(%rip), %r15
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movq %r15, %rdi
movl $103, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB3_6
.LBB3_7:
movq stderr(%rip), %r15
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movq %r15, %rdi
movl $105, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB3_8
.LBB3_9:
movq stderr(%rip), %r15
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movq %r15, %rdi
movl $109, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB3_10
.LBB3_11:
movq stderr(%rip), %r15
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movq %r15, %rdi
movl $111, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB3_12
.LBB3_15:
movq stderr(%rip), %r15
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movq %r15, %rdi
movl $131, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB3_16
.LBB3_17:
movq stderr(%rip), %r15
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movq %r15, %rdi
movl $135, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB3_18
.LBB3_26:
.Ltmp38:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp39:
# %bb.27: # %.noexc57
.LBB3_38:
.Ltmp35:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp36:
# %bb.41: # %.noexc67
.LBB3_54:
.Ltmp37:
jmp .LBB3_55
.LBB3_40: # %.loopexit.split-lp
.Ltmp40:
jmp .LBB3_55
.LBB3_39: # %.loopexit
.Ltmp14:
.LBB3_55:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp13-.Ltmp4 # Call between .Ltmp4 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp34-.Ltmp15 # Call between .Ltmp15 and .Ltmp34
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp38-.Ltmp34 # Call between .Ltmp34 and .Ltmp38
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp36-.Ltmp35 # Call between .Ltmp35 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end3-.Ltmp36 # Call between .Ltmp36 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15incrementKernelPfS_if, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _TempErrorCode,@object # @_TempErrorCode
.bss
.globl _TempErrorCode
.p2align 2, 0x0
_TempErrorCode:
.long 0 # 0x0
.size _TempErrorCode, 4
.type NumberOfArgs,@object # @NumberOfArgs
.data
.globl NumberOfArgs
.p2align 2, 0x0
NumberOfArgs:
.long 1 # 0x1
.size NumberOfArgs, 4
.type _ArraySize,@object # @_ArraySize
.globl _ArraySize
.p2align 2, 0x0
_ArraySize:
.long 1024 # 0x400
.size _ArraySize, 4
.type _IncrementValue,@object # @_IncrementValue
.globl _IncrementValue
.p2align 2, 0x0
_IncrementValue:
.long 0x3f800000 # float 1
.size _IncrementValue, 4
.type _OutputFile,@object # @_OutputFile
.globl _OutputFile
_OutputFile:
.asciz "output.txt"
.size _OutputFile, 11
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Setting ArraysSize to "
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Setting IncrementValue to "
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Running ("
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Usage: "
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " <ArraySize> <IncrementValue> "
.size .L.str.5, 31
.type _Z15incrementKernelPfS_if,@object # @_Z15incrementKernelPfS_if
.section .rodata,"a",@progbits
.globl _Z15incrementKernelPfS_if
.p2align 3, 0x0
_Z15incrementKernelPfS_if:
.quad _Z30__device_stub__incrementKernelPfS_if
.size _Z15incrementKernelPfS_if, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "!!CUDA ERROR in %s at line %d : %s\n"
.size .L.str.6, 36
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/rudm818/ucsd-comp-phys/master/142-242/cudaExample/cudaExample.hip"
.size .L.str.7, 123
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Data saved in file "
.size .L.str.8, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15incrementKernelPfS_if"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__incrementKernelPfS_if
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _OutputFile
.addrsig_sym _ZSt4cout
.addrsig_sym _Z15incrementKernelPfS_if
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void add2( double * v1, const double * v2 )
{
int idx = threadIdx.x;
v1[idx] += v2[idx];
} | code for sm_80
Function : _Z4add2PdPKd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fc800078e0205 */
/*0050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0060*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*0080*/ DADD R6, R2, R6 ; /* 0x0000000002067229 */
/* 0x004e0e0000000006 */
/*0090*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void add2( double * v1, const double * v2 )
{
int idx = threadIdx.x;
v1[idx] += v2[idx];
} | .file "tmpxft_0014f272_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4add2PdPKdPdPKd
.type _Z26__device_stub__Z4add2PdPKdPdPKd, @function
_Z26__device_stub__Z4add2PdPKdPdPKd:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4add2PdPKd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z4add2PdPKdPdPKd, .-_Z26__device_stub__Z4add2PdPKdPdPKd
.globl _Z4add2PdPKd
.type _Z4add2PdPKd, @function
_Z4add2PdPKd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4add2PdPKdPdPKd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4add2PdPKd, .-_Z4add2PdPKd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4add2PdPKd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4add2PdPKd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void add2( double * v1, const double * v2 )
{
int idx = threadIdx.x;
v1[idx] += v2[idx];
} | #include <hip/hip_runtime.h>
__global__ void add2( double * v1, const double * v2 )
{
int idx = threadIdx.x;
v1[idx] += v2[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void add2( double * v1, const double * v2 )
{
int idx = threadIdx.x;
v1[idx] += v2[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4add2PdPKd
.globl _Z4add2PdPKd
.p2align 8
.type _Z4add2PdPKd,@function
_Z4add2PdPKd:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[0:1], v4, s[2:3]
global_load_b64 v[2:3], v4, s[0:1]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4add2PdPKd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4add2PdPKd, .Lfunc_end0-_Z4add2PdPKd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4add2PdPKd
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z4add2PdPKd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void add2( double * v1, const double * v2 )
{
int idx = threadIdx.x;
v1[idx] += v2[idx];
} | .text
.file "test.hip"
.globl _Z19__device_stub__add2PdPKd # -- Begin function _Z19__device_stub__add2PdPKd
.p2align 4, 0x90
.type _Z19__device_stub__add2PdPKd,@function
_Z19__device_stub__add2PdPKd: # @_Z19__device_stub__add2PdPKd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4add2PdPKd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__add2PdPKd, .Lfunc_end0-_Z19__device_stub__add2PdPKd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4add2PdPKd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4add2PdPKd,@object # @_Z4add2PdPKd
.section .rodata,"a",@progbits
.globl _Z4add2PdPKd
.p2align 3, 0x0
_Z4add2PdPKd:
.quad _Z19__device_stub__add2PdPKd
.size _Z4add2PdPKd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4add2PdPKd"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__add2PdPKd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4add2PdPKd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4add2PdPKd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fc800078e0205 */
/*0050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0060*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*0080*/ DADD R6, R2, R6 ; /* 0x0000000002067229 */
/* 0x004e0e0000000006 */
/*0090*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4add2PdPKd
.globl _Z4add2PdPKd
.p2align 8
.type _Z4add2PdPKd,@function
_Z4add2PdPKd:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[0:1], v4, s[2:3]
global_load_b64 v[2:3], v4, s[0:1]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4add2PdPKd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4add2PdPKd, .Lfunc_end0-_Z4add2PdPKd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4add2PdPKd
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z4add2PdPKd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014f272_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4add2PdPKdPdPKd
.type _Z26__device_stub__Z4add2PdPKdPdPKd, @function
_Z26__device_stub__Z4add2PdPKdPdPKd:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4add2PdPKd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z4add2PdPKdPdPKd, .-_Z26__device_stub__Z4add2PdPKdPdPKd
.globl _Z4add2PdPKd
.type _Z4add2PdPKd, @function
_Z4add2PdPKd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4add2PdPKdPdPKd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4add2PdPKd, .-_Z4add2PdPKd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4add2PdPKd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4add2PdPKd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z19__device_stub__add2PdPKd # -- Begin function _Z19__device_stub__add2PdPKd
.p2align 4, 0x90
.type _Z19__device_stub__add2PdPKd,@function
_Z19__device_stub__add2PdPKd: # @_Z19__device_stub__add2PdPKd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4add2PdPKd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__add2PdPKd, .Lfunc_end0-_Z19__device_stub__add2PdPKd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4add2PdPKd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4add2PdPKd,@object # @_Z4add2PdPKd
.section .rodata,"a",@progbits
.globl _Z4add2PdPKd
.p2align 3, 0x0
_Z4add2PdPKd:
.quad _Z19__device_stub__add2PdPKd
.size _Z4add2PdPKd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4add2PdPKd"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__add2PdPKd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4add2PdPKd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ __forceinline__ size_t gpu_scalar_index(unsigned int x, unsigned int y)
{
return NX*y+x;
}
__device__ __forceinline__ size_t gpu_s_scalar_index(unsigned int x, unsigned int y)
{
return (2*RAD + nThreads)*y + x;
}
__global__ void gpu_poisson(double *c, double *fi,double *R){
unsigned int y = blockIdx.y;
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int s_y = threadIdx.y + RAD;
unsigned int s_x = threadIdx.x + RAD;
unsigned int xp1 = (x + blockDim.x) % NX;
unsigned int yp1 = (y + blockDim.y) % NY;
unsigned int xm1 = (NX + x - 1) % NX;
unsigned int ym1 = (NY + y - 1) % NY;
__shared__ double s_in[(2*RAD + nThreads)*3];
// load to shared memory (regular cells)
s_in[gpu_s_scalar_index(s_x,s_y)] = fi[gpu_scalar_index(x, y)];
// load halo cells
if (threadIdx.x < RAD) {
s_in[gpu_s_scalar_index(s_x - RAD, s_y)] = fi[gpu_scalar_index(xm1, y)];
s_in[gpu_s_scalar_index(s_x + blockDim.x, s_y)] = fi[gpu_scalar_index(xp1, y)];
}
if (threadIdx.y < RAD) {
s_in[gpu_s_scalar_index(s_x, s_y - RAD)] = fi[gpu_scalar_index(x, ym1)];
s_in[gpu_s_scalar_index(s_x, s_y + blockDim.y)] = fi[gpu_scalar_index(x, yp1)];
}
// Boundary conditions
if (y == 0) {
fi[gpu_scalar_index(x, y)] = voltage;
return;
}
if (y == NY - 1) {
fi[gpu_scalar_index(x, y)] = 0.0;
return;
}
__syncthreads();
double charge = c[gpu_scalar_index(x, y)];
//double phi = fi[gpu_scalar_index(x, y)];
//double phiL = fi[gpu_scalar_index(xm1, y)];
//double phiR = fi[gpu_scalar_index(xp1, y)];
//double phiU = fi[gpu_scalar_index(x, yp1)];
//double phiD = fi[gpu_scalar_index(x, ym1)];
double phi = s_in[gpu_s_scalar_index(s_x, s_y)];
double phiL = s_in[gpu_s_scalar_index(s_x-1, s_y)];
double phiR = s_in[gpu_s_scalar_index(s_x+1, s_y)];
double phiU = s_in[gpu_s_scalar_index(s_x, s_y+1)];
double phiD = s_in[gpu_s_scalar_index(s_x, s_y-1)];
double source = (charge / eps) * dx *dx; // Right hand side of the equation
double phi_old = phi;
phi = 0.25 * (phiL + phiR + phiU + phiD + source);
// Record the error
R[gpu_scalar_index(x, y)] = fabs(phi - phi_old);
//__syncthreads();
fi[gpu_scalar_index(x, y)] = phi;
//if (x == 5 && y == 5) printf("%g\n", phi);
} | code for sm_80
Function : _Z11gpu_poissonPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000ea20000002600 */
/*0050*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x001fe20003f05270 */
/*0060*/ IMAD R5, R5, c[0x0][0x0], R4 ; /* 0x0000000005057a24 */
/* 0x002fc800078e0204 */
/*0070*/ IMAD R18, R0, 0x7a, R5 ; /* 0x0000007a00127824 */
/* 0x004fd000078e0205 */
/*0080*/ @!P0 IADD3 R8, R5.reuse, 0x79, RZ ; /* 0x0000007905088810 */
/* 0x040fe40007ffe0ff */
/*0090*/ @!P0 IADD3 R9, R5, c[0x0][0x0], RZ ; /* 0x0000000005098a10 */
/* 0x000fc60007ffe0ff */
/*00a0*/ @!P0 IMAD.WIDE.U32 R2, R8, 0x4325c53f, RZ ; /* 0x4325c53f08028825 */
/* 0x000fc800078e00ff */
/*00b0*/ @!P0 IMAD.WIDE.U32 R6, R9, 0x4325c53f, RZ ; /* 0x4325c53f09068825 */
/* 0x000fe200078e00ff */
/*00c0*/ @!P0 SHF.R.U32.HI R3, RZ, 0x5, R3 ; /* 0x00000005ff038819 */
/* 0x000fc80000011603 */
/*00d0*/ @!P0 SHF.R.U32.HI R6, RZ, 0x5, R7 ; /* 0x00000005ff068819 */
/* 0x000fe20000011607 */
/*00e0*/ @!P0 IMAD R3, R3, -0x7a, R8 ; /* 0xffffff8603038824 */
/* 0x000fc800078e0208 */
/*00f0*/ @!P0 IMAD R9, R6, -0x7a, R9 ; /* 0xffffff8606098824 */
/* 0x000fe400078e0209 */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; /* 0x00000008ff067424 */
/* 0x000fe400078e00ff */
/*0110*/ @!P0 IMAD R11, R0.reuse, 0x7a, R3 ; /* 0x0000007a000b8824 */
/* 0x040fe400078e0203 */
/*0120*/ @!P0 IMAD R9, R0, 0x7a, R9 ; /* 0x0000007a00098824 */
/* 0x000fe400078e0209 */
/*0130*/ IMAD.WIDE.U32 R2, R18, R6, c[0x0][0x168] ; /* 0x00005a0012027625 */
/* 0x000fc800078e0006 */
/*0140*/ @!P0 IMAD.WIDE.U32 R10, R11, R6, c[0x0][0x168] ; /* 0x00005a000b0a8625 */
/* 0x000fc800078e0006 */
/*0150*/ @!P0 IMAD.WIDE.U32 R12, R9, R6, c[0x0][0x168] ; /* 0x00005a00090c8625 */
/* 0x000fe400078e0006 */
/*0160*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1b00 */
/*0170*/ @!P0 LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a8981 */
/* 0x000ee8000c1e1b00 */
/*0180*/ @!P0 LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c8981 */
/* 0x000f22000c1e1b00 */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, 0x3f ; /* 0x0000003fff0e7424 */
/* 0x000fe200078e00ff */
/*01a0*/ BSSY B0, 0x3f0 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*01b0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*01c0*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e240000002200 */
/*01d0*/ IMAD R15, R7, R14, 0x3f ; /* 0x0000003f070f7424 */
/* 0x001fc400078e020e */
/*01e0*/ @!P0 IMAD R17, R7, 0x1f8, RZ ; /* 0x000001f807118824 */
/* 0x000fe400078e02ff */
/*01f0*/ IMAD.IADD R16, R15, 0x1, R4 ; /* 0x000000010f107824 */
/* 0x000fc800078e0204 */
/*0200*/ IMAD.SHL.U32 R15, R16, 0x8, RZ ; /* 0x00000008100f7824 */
/* 0x000fc800078e00ff */
/*0210*/ @!P0 IMAD R15, R6, c[0x0][0x0], R15 ; /* 0x00000000060f8a24 */
/* 0x000fe200078e020f */
/*0220*/ STS.64 [R16.X8+0x8], R8 ; /* 0x0000080810007388 */
/* 0x0041e80000008a00 */
/*0230*/ @!P0 STS.64 [R17+0x1f8], R10 ; /* 0x0001f80a11008388 */
/* 0x0081e80000000a00 */
/*0240*/ @!P0 STS.64 [R15+0x8], R12 ; /* 0x0000080c0f008388 */
/* 0x0101e20000000a00 */
/*0250*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0260*/ @P0 BRA 0x3e0 ; /* 0x0000017000000947 */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R13, R0.reuse, 0x64, RZ ; /* 0x00000064000d7810 */
/* 0x041fe40007ffe0ff */
/*0280*/ IADD3 R15, R0, c[0x0][0x4], RZ ; /* 0x00000100000f7a10 */
/* 0x000fc60007ffe0ff */
/*0290*/ IMAD.WIDE.U32 R10, R13, 0x446f8657, RZ ; /* 0x446f86570d0a7825 */
/* 0x000fc800078e00ff */
/*02a0*/ IMAD.WIDE.U32 R8, R15, 0x446f8657, RZ ; /* 0x446f86570f087825 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD.IADD R10, R13, 0x1, -R11 ; /* 0x000000010d0a7824 */
/* 0x000fe400078e0a0b */
/*02c0*/ IMAD.IADD R8, R15, 0x1, -R9 ; /* 0x000000010f087824 */
/* 0x000fc600078e0a09 */
/*02d0*/ LEA.HI R10, R10, R11, RZ, 0x1f ; /* 0x0000000b0a0a7211 */
/* 0x000fe400078ff8ff */
/*02e0*/ LEA.HI R8, R8, R9, RZ, 0x1f ; /* 0x0000000908087211 */
/* 0x000fe400078ff8ff */
/*02f0*/ SHF.R.U32.HI R10, RZ, 0x6, R10 ; /* 0x00000006ff0a7819 */
/* 0x000fe4000001160a */
/*0300*/ SHF.R.U32.HI R8, RZ, 0x6, R8 ; /* 0x00000006ff087819 */
/* 0x000fc60000011608 */
/*0310*/ IMAD R10, R10, -0x65, R13 ; /* 0xffffff9b0a0a7824 */
/* 0x000fe400078e020d */
/*0320*/ IMAD R8, R8, -0x65, R15 ; /* 0xffffff9b08087824 */
/* 0x000fe400078e020f */
/*0330*/ IMAD R9, R10, 0x7a, R5.reuse ; /* 0x0000007a0a097824 */
/* 0x100fe400078e0205 */
/*0340*/ IMAD R11, R8, 0x7a, R5 ; /* 0x0000007a080b7824 */
/* 0x000fe400078e0205 */
/*0350*/ IMAD.WIDE.U32 R8, R9, R6, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fc800078e0006 */
/*0360*/ IMAD.WIDE.U32 R10, R11, R6, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fe400078e0006 */
/*0370*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*0380*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1b00 */
/*0390*/ IADD3.X R12, R7, c[0x0][0x4], RZ, PT, !PT ; /* 0x00000100070c7a10 */
/* 0x000fe20003ffe4ff */
/*03a0*/ IMAD.SHL.U32 R7, R4, 0x8, RZ ; /* 0x0000000804077824 */
/* 0x000fc800078e00ff */
/*03b0*/ IMAD R7, R12, 0x1f8, R7 ; /* 0x000001f80c077824 */
/* 0x000fe200078e0207 */
/*03c0*/ STS.64 [R4.X8+0x8], R8 ; /* 0x0000080804007388 */
/* 0x0041e80000008a00 */
/*03d0*/ STS.64 [R7+0x8], R10 ; /* 0x0000080a07007388 */
/* 0x0081e40000000a00 */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*03f0*/ @!P1 BRA 0x710 ; /* 0x0000031000009947 */
/* 0x000fea0003800000 */
/*0400*/ ISETP.NE.AND P0, PT, R0, 0x64, PT ; /* 0x000000640000780c */
/* 0x000fda0003f05270 */
/*0410*/ @!P0 IADD3 R7, R5, 0x2fa8, RZ ; /* 0x00002fa805078810 */
/* 0x000fca0007ffe0ff */
/*0420*/ @!P0 IMAD.WIDE.U32 R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007068625 */
/* 0x000fca00078e0006 */
/*0430*/ @!P0 STG.E.64 [R6.64], RZ ; /* 0x000000ff06008986 */
/* 0x0001e2000c101b04 */
/*0440*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0450*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0460*/ SHF.L.U32 R17, R18, 0x3, RZ ; /* 0x0000000312117819 */
/* 0x000fe400000006ff */
/*0470*/ SHF.R.U32.HI R18, RZ, 0x1d, R18 ; /* 0x0000001dff127819 */
/* 0x000fe40000011612 */
/*0480*/ IADD3 R6, P0, R17, c[0x0][0x160], RZ ; /* 0x0000580011067a10 */
/* 0x001fc80007f1e0ff */
/*0490*/ IADD3.X R7, R18, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590012077a10 */
/* 0x000fcc00007fe4ff */
/*04a0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*04b0*/ MUFU.RCP64H R5, c[0x3][0x14] ; /* 0x00c0050000057b08 */
/* 0x000e220000001800 */
/*04c0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x3][0x10] ; /* 0x00c00400ff0a7624 */
/* 0x000fe200078e00ff */
/*04d0*/ BSSY B0, 0x5f0 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*04e0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x3][0x14] ; /* 0x00c00500ff0b7624 */
/* 0x000fe400078e00ff */
/*04f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fcc00078e00ff */
/*0500*/ DFMA R8, R4, -R10, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c000000080a */
/*0510*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0520*/ DFMA R8, R4, R8, R4 ; /* 0x000000080408722b */
/* 0x001e0c0000000004 */
/*0530*/ DFMA R4, R8, -R10, 1 ; /* 0x3ff000000804742b */
/* 0x001e0c000000080a */
/*0540*/ DFMA R4, R8, R4, R8 ; /* 0x000000040804722b */
/* 0x001e8c0000000008 */
/*0550*/ DMUL R8, R6, R4 ; /* 0x0000000406087228 */
/* 0x004e220000000000 */
/*0560*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*0570*/ DFMA R10, R8, -c[0x3][0x10], R6 ; /* 0x80c00400080a7a2b */
/* 0x001e0c0000000006 */
/*0580*/ DFMA R8, R4, R10, R8 ; /* 0x0000000a0408722b */
/* 0x001e140000000008 */
/*0590*/ FFMA R0, RZ, c[0x3][0x14], R9 ; /* 0x00c00500ff007a23 */
/* 0x001fca0000000009 */
/*05a0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*05b0*/ @P0 BRA P1, 0x5e0 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*05c0*/ MOV R0, 0x5e0 ; /* 0x000005e000007802 */
/* 0x000fe40000000f00 */
/*05d0*/ CALL.REL.NOINC 0x760 ; /* 0x0000018000007944 */
/* 0x000fea0003c00000 */
/*05e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05f0*/ LDS.64 R6, [R16.X8+0x10] ; /* 0x0000100010067984 */
/* 0x000fe20000008a00 */
/*0600*/ DMUL R8, R8, c[0x3][0x0] ; /* 0x00c0000008087a28 */
/* 0x000fc60000000000 */
/*0610*/ LDS.64 R10, [R16.X8] ; /* 0x00000000100a7984 */
/* 0x000e280000008a00 */
/*0620*/ LDS.64 R12, [R16.X8+0x200] ; /* 0x00020000100c7984 */
/* 0x000ea80000008a00 */
/*0630*/ LDS.64 R14, [R16.X8+-0x1f0] ; /* 0xfffe1000100e7984 */
/* 0x002e680000008a00 */
/*0640*/ LDS.64 R4, [R16.X8+0x8] ; /* 0x0000080010047984 */
/* 0x000ee20000008a00 */
/*0650*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x001e8c000000000a */
/*0660*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x004e4c000000000c */
/*0670*/ DADD R6, R6, R14 ; /* 0x0000000006067229 */
/* 0x002e0c000000000e */
/*0680*/ DFMA R6, R8, c[0x3][0x0], R6 ; /* 0x00c0000008067a2b */
/* 0x0010640000000006 */
/*0690*/ IADD3 R8, P0, R17, c[0x0][0x170], RZ ; /* 0x00005c0011087a10 */
/* 0x001fc80007f1e0ff */
/*06a0*/ DMUL R6, R6, 0.25 ; /* 0x3fd0000006067828 */
/* 0x002ee20000000000 */
/*06b0*/ IADD3.X R9, R18, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0012097a10 */
/* 0x000fca00007fe4ff */
/*06c0*/ DADD R4, R6, -R4 ; /* 0x0000000006047229 */
/* 0x008e0c0000000804 */
/*06d0*/ DADD R4, -RZ, |R4| ; /* 0x00000000ff047229 */
/* 0x001e0e0000000504 */
/*06e0*/ STG.E.64 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x001fe8000c101b04 */
/*06f0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101b04 */
/*0700*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0710*/ IMAD.WIDE.U32 R6, R5, R6, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fc800078e0006 */
/*0720*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x3][0x8] ; /* 0x00c00200ff027624 */
/* 0x000fe400078e00ff */
/*0730*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x3][0xc] ; /* 0x00c00300ff037624 */
/* 0x000fca00078e00ff */
/*0740*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x000fe2000c101b04 */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x3][0x14] ; /* 0x00c00500ff137624 */
/* 0x000fe200078e00ff */
/*0770*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0780*/ IMAD.MOV.U32 R23, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff177424 */
/* 0x000fe200078e00ff */
/*0790*/ LOP3.LUT R21, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007157812 */
/* 0x000fe200078ec0ff */
/*07a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*07b0*/ FSETP.GEU.AND P0, PT, |R19|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x040fe20003f0e200 */
/*07c0*/ BSSY B1, 0xd10 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*07d0*/ LOP3.LUT R4, R19.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff13047812 */
/* 0x040fe200078ec0ff */
/*07e0*/ IMAD.MOV.U32 R22, RZ, RZ, R21 ; /* 0x000000ffff167224 */
/* 0x000fe200078e0015 */
/*07f0*/ LOP3.LUT R20, R19, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000013147812 */
/* 0x000fc400078ec0ff */
/*0800*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0810*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x3][0x10] ; /* 0x00c00400ff047624 */
/* 0x000fe200078e00ff */
/*0820*/ ISETP.GE.U32.AND P1, PT, R21, R20.reuse, PT ; /* 0x000000141500720c */
/* 0x080fe40003f26070 */
/*0830*/ MOV R25, R20 ; /* 0x0000001400197202 */
/* 0x000fe40000000f00 */
/*0840*/ SEL R23, R23, 0x63400000, !P1 ; /* 0x6340000017177807 */
/* 0x000fe20004800000 */
/*0850*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, c[0x3][0x10] ; /* 0x00c00400ff088624 */
/* 0x000fe200078e00ff */
/*0860*/ @!P0 MOV R9, c[0x3][0x14] ; /* 0x00c0050000098a02 */
/* 0x000fe40000000f00 */
/*0870*/ @!P2 LOP3.LUT R14, R23, 0x80000000, R7, 0xf8, !PT ; /* 0x80000000170ea812 */
/* 0x000fc800078ef807 */
/*0880*/ @!P0 DMUL R4, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008048828 */
/* 0x0000620000000000 */
/*0890*/ @!P2 LOP3.LUT R15, R14, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000e0fa812 */
/* 0x000fe200078efcff */
/*08a0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0006 */
/*08b0*/ LOP3.LUT R9, R23, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff17097812 */
/* 0x000fe200078ef807 */
/*08c0*/ @!P2 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0ea224 */
/* 0x000fe400078e00ff */
/*08d0*/ MUFU.RCP64H R11, R5 ; /* 0x00000005000b7308 */
/* 0x002e280000001800 */
/*08e0*/ @!P2 DFMA R8, R8, 2, -R14 ; /* 0x400000000808a82b */
/* 0x000e62000000080e */
/*08f0*/ @!P0 LOP3.LUT R25, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005198812 */
/* 0x000fc800078ec0ff */
/*0900*/ IADD3 R24, R25, -0x1, RZ ; /* 0xffffffff19187810 */
/* 0x000fca0007ffe0ff */
/*0910*/ @!P2 LOP3.LUT R22, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000916a812 */
/* 0x002fe200078ec0ff */
/*0920*/ DFMA R12, R10, -R4, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e060000000804 */
/*0930*/ IADD3 R14, R22, -0x1, RZ ; /* 0xffffffff160e7810 */
/* 0x000fc60007ffe0ff */
/*0940*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e22000000000c */
/*0950*/ ISETP.GT.U32.AND P0, PT, R14, 0x7feffffe, PT ; /* 0x7feffffe0e00780c */
/* 0x000fc80003f04070 */
/*0960*/ ISETP.GT.U32.OR P0, PT, R24, 0x7feffffe, P0 ; /* 0x7feffffe1800780c */
/* 0x000fe20000704470 */
/*0970*/ DFMA R10, R10, R12, R10 ; /* 0x0000000c0a0a722b */
/* 0x001e0c000000000a */
/*0980*/ DFMA R12, R10, -R4, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c0000000804 */
/*0990*/ DFMA R10, R10, R12, R10 ; /* 0x0000000c0a0a722b */
/* 0x001e0c000000000a */
/*09a0*/ DMUL R12, R10, R8 ; /* 0x000000080a0c7228 */
/* 0x001e0c0000000000 */
/*09b0*/ DFMA R14, R12, -R4, R8 ; /* 0x800000040c0e722b */
/* 0x001e0c0000000008 */
/*09c0*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x001062000000000c */
/*09d0*/ @P0 BRA 0xb80 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*09e0*/ IMAD.IADD R20, R21, 0x1, -R20 ; /* 0x0000000115147824 */
/* 0x000fe400078e0a14 */
/*09f0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0a00*/ IMNMX R20, R20, -0x46a00000, !PT ; /* 0xb960000014147817 */
/* 0x000fc80007800200 */
/*0a10*/ IMNMX R20, R20, 0x46a00000, PT ; /* 0x46a0000014147817 */
/* 0x000fca0003800200 */
/*0a20*/ IMAD.IADD R20, R20, 0x1, -R23 ; /* 0x0000000114147824 */
/* 0x000fca00078e0a17 */
/*0a30*/ IADD3 R7, R20, 0x7fe00000, RZ ; /* 0x7fe0000014077810 */
/* 0x000fcc0007ffe0ff */
/*0a40*/ DMUL R10, R14, R6 ; /* 0x000000060e0a7228 */
/* 0x003e140000000000 */
/*0a50*/ FSETP.GTU.AND P0, PT, |R11|, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x001fda0003f0c200 */
/*0a60*/ @P0 BRA 0xd00 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*0a70*/ DFMA R4, R14, -R4, R8 ; /* 0x800000040e04722b */
/* 0x000e220000000008 */
/*0a80*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0a90*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0aa0*/ LOP3.LUT R4, R5, c[0x3][0x14], RZ, 0x3c, !PT ; /* 0x00c0050005047a12 */
/* 0x000fc800078e3cff */
/*0ab0*/ LOP3.LUT R9, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004097812 */
/* 0x000fc800078ec0ff */
/*0ac0*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fc600078efcff */
/*0ad0*/ @!P0 BRA 0xd00 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ IMAD.MOV R5, RZ, RZ, -R20 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a14 */
/*0af0*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e220000008000 */
/*0b00*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0b10*/ DFMA R4, R10, -R4, R14 ; /* 0x800000040a04722b */
/* 0x000e46000000000e */
/*0b20*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*0b30*/ IADD3 R4, -R20, -0x43300000, RZ ; /* 0xbcd0000014047810 */
/* 0x002fc80007ffe1ff */
/*0b40*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0b50*/ FSEL R10, R6, R10, !P0 ; /* 0x0000000a060a7208 */
/* 0x000fe40004000000 */
/*0b60*/ FSEL R11, R9, R11, !P0 ; /* 0x0000000b090b7208 */
/* 0x000fe20004000000 */
/*0b70*/ BRA 0xd00 ; /* 0x0000018000007947 */
/* 0x000fea0003800000 */
/*0b80*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0b90*/ @P0 BRA 0xce0 ; /* 0x0000014000000947 */
/* 0x004fea0003800000 */
/*0ba0*/ MOV R4, c[0x3][0x10] ; /* 0x00c0040000047a02 */
/* 0x000fe20000000f00 */
/*0bb0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x3][0x14] ; /* 0x00c00500ff057624 */
/* 0x000fcc00078e00ff */
/*0bc0*/ DSETP.NAN.AND P0, PT, R4, c[0x3][0x10], PT ; /* 0x00c004000400762a */
/* 0x000e9c0003f08000 */
/*0bd0*/ @P0 BRA 0xcb0 ; /* 0x000000d000000947 */
/* 0x004fea0003800000 */
/*0be0*/ ISETP.NE.AND P0, PT, R22, R25, PT ; /* 0x000000191600720c */
/* 0x000fe20003f05270 */
/*0bf0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x001fe400078e00ff */
/*0c00*/ IMAD.MOV.U32 R11, RZ, RZ, -0x80000 ; /* 0xfff80000ff0b7424 */
/* 0x000fd400078e00ff */
/*0c10*/ @!P0 BRA 0xd00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0c20*/ ISETP.NE.AND P0, PT, R22, 0x7ff00000, PT ; /* 0x7ff000001600780c */
/* 0x000fe40003f05270 */
/*0c30*/ LOP3.LUT R6, R7, c[0x3][0x14], RZ, 0x3c, !PT ; /* 0x00c0050007067a12 */
/* 0x000fe400078e3cff */
/*0c40*/ ISETP.EQ.OR P0, PT, R25, RZ, !P0 ; /* 0x000000ff1900720c */
/* 0x000fe40004702670 */
/*0c50*/ LOP3.LUT R11, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000060b7812 */
/* 0x000fd600078ec0ff */
/*0c60*/ @P0 LOP3.LUT R4, R11, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000b040812 */
/* 0x000fe200078efcff */
/*0c70*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe400078e00ff */
/*0c80*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0c90*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, R4 ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e0004 */
/*0ca0*/ BRA 0xd00 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0cb0*/ LOP3.LUT R11, R19, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000130b7812 */
/* 0x001fe400078efcff */
/*0cc0*/ MOV R10, c[0x3][0x10] ; /* 0x00c00400000a7a02 */
/* 0x000fe20000000f00 */
/*0cd0*/ BRA 0xd00 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0ce0*/ LOP3.LUT R11, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070b7812 */
/* 0x001fe200078efcff */
/*0cf0*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fc400078e0006 */
/*0d00*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d10*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0d20*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc400078e00ff */
/*0d30*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000a */
/*0d40*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000b */
/*0d50*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff2a004007950 */
/* 0x000fec0003c3ffff */
/*0d60*/ BRA 0xd60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ __forceinline__ size_t gpu_scalar_index(unsigned int x, unsigned int y)
{
return NX*y+x;
}
__device__ __forceinline__ size_t gpu_s_scalar_index(unsigned int x, unsigned int y)
{
return (2*RAD + nThreads)*y + x;
}
__global__ void gpu_poisson(double *c, double *fi,double *R){
unsigned int y = blockIdx.y;
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int s_y = threadIdx.y + RAD;
unsigned int s_x = threadIdx.x + RAD;
unsigned int xp1 = (x + blockDim.x) % NX;
unsigned int yp1 = (y + blockDim.y) % NY;
unsigned int xm1 = (NX + x - 1) % NX;
unsigned int ym1 = (NY + y - 1) % NY;
__shared__ double s_in[(2*RAD + nThreads)*3];
// load to shared memory (regular cells)
s_in[gpu_s_scalar_index(s_x,s_y)] = fi[gpu_scalar_index(x, y)];
// load halo cells
if (threadIdx.x < RAD) {
s_in[gpu_s_scalar_index(s_x - RAD, s_y)] = fi[gpu_scalar_index(xm1, y)];
s_in[gpu_s_scalar_index(s_x + blockDim.x, s_y)] = fi[gpu_scalar_index(xp1, y)];
}
if (threadIdx.y < RAD) {
s_in[gpu_s_scalar_index(s_x, s_y - RAD)] = fi[gpu_scalar_index(x, ym1)];
s_in[gpu_s_scalar_index(s_x, s_y + blockDim.y)] = fi[gpu_scalar_index(x, yp1)];
}
// Boundary conditions
if (y == 0) {
fi[gpu_scalar_index(x, y)] = voltage;
return;
}
if (y == NY - 1) {
fi[gpu_scalar_index(x, y)] = 0.0;
return;
}
__syncthreads();
double charge = c[gpu_scalar_index(x, y)];
//double phi = fi[gpu_scalar_index(x, y)];
//double phiL = fi[gpu_scalar_index(xm1, y)];
//double phiR = fi[gpu_scalar_index(xp1, y)];
//double phiU = fi[gpu_scalar_index(x, yp1)];
//double phiD = fi[gpu_scalar_index(x, ym1)];
double phi = s_in[gpu_s_scalar_index(s_x, s_y)];
double phiL = s_in[gpu_s_scalar_index(s_x-1, s_y)];
double phiR = s_in[gpu_s_scalar_index(s_x+1, s_y)];
double phiU = s_in[gpu_s_scalar_index(s_x, s_y+1)];
double phiD = s_in[gpu_s_scalar_index(s_x, s_y-1)];
double source = (charge / eps) * dx *dx; // Right hand side of the equation
double phi_old = phi;
phi = 0.25 * (phiL + phiR + phiU + phiD + source);
// Record the error
R[gpu_scalar_index(x, y)] = fabs(phi - phi_old);
//__syncthreads();
fi[gpu_scalar_index(x, y)] = phi;
//if (x == 5 && y == 5) printf("%g\n", phi);
} | .file "tmpxft_001b27b3_00000000-6_gpu_poisson.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11gpu_poissonPdS_S_PdS_S_
.type _Z35__device_stub__Z11gpu_poissonPdS_S_PdS_S_, @function
_Z35__device_stub__Z11gpu_poissonPdS_S_PdS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11gpu_poissonPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z35__device_stub__Z11gpu_poissonPdS_S_PdS_S_, .-_Z35__device_stub__Z11gpu_poissonPdS_S_PdS_S_
.globl _Z11gpu_poissonPdS_S_
.type _Z11gpu_poissonPdS_S_, @function
_Z11gpu_poissonPdS_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11gpu_poissonPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11gpu_poissonPdS_S_, .-_Z11gpu_poissonPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11gpu_poissonPdS_S_"
.LC1:
.string "dx"
.LC2:
.string "voltage"
.LC3:
.string "eps"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gpu_poissonPdS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2dx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7voltage(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3eps(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3eps
.comm _ZL3eps,8,8
.local _ZL7voltage
.comm _ZL7voltage,8,8
.local _ZL2dx
.comm _ZL2dx,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ __forceinline__ size_t gpu_scalar_index(unsigned int x, unsigned int y)
{
return NX*y+x;
}
__device__ __forceinline__ size_t gpu_s_scalar_index(unsigned int x, unsigned int y)
{
return (2*RAD + nThreads)*y + x;
}
__global__ void gpu_poisson(double *c, double *fi,double *R){
unsigned int y = blockIdx.y;
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int s_y = threadIdx.y + RAD;
unsigned int s_x = threadIdx.x + RAD;
unsigned int xp1 = (x + blockDim.x) % NX;
unsigned int yp1 = (y + blockDim.y) % NY;
unsigned int xm1 = (NX + x - 1) % NX;
unsigned int ym1 = (NY + y - 1) % NY;
__shared__ double s_in[(2*RAD + nThreads)*3];
// load to shared memory (regular cells)
s_in[gpu_s_scalar_index(s_x,s_y)] = fi[gpu_scalar_index(x, y)];
// load halo cells
if (threadIdx.x < RAD) {
s_in[gpu_s_scalar_index(s_x - RAD, s_y)] = fi[gpu_scalar_index(xm1, y)];
s_in[gpu_s_scalar_index(s_x + blockDim.x, s_y)] = fi[gpu_scalar_index(xp1, y)];
}
if (threadIdx.y < RAD) {
s_in[gpu_s_scalar_index(s_x, s_y - RAD)] = fi[gpu_scalar_index(x, ym1)];
s_in[gpu_s_scalar_index(s_x, s_y + blockDim.y)] = fi[gpu_scalar_index(x, yp1)];
}
// Boundary conditions
if (y == 0) {
fi[gpu_scalar_index(x, y)] = voltage;
return;
}
if (y == NY - 1) {
fi[gpu_scalar_index(x, y)] = 0.0;
return;
}
__syncthreads();
double charge = c[gpu_scalar_index(x, y)];
//double phi = fi[gpu_scalar_index(x, y)];
//double phiL = fi[gpu_scalar_index(xm1, y)];
//double phiR = fi[gpu_scalar_index(xp1, y)];
//double phiU = fi[gpu_scalar_index(x, yp1)];
//double phiD = fi[gpu_scalar_index(x, ym1)];
double phi = s_in[gpu_s_scalar_index(s_x, s_y)];
double phiL = s_in[gpu_s_scalar_index(s_x-1, s_y)];
double phiR = s_in[gpu_s_scalar_index(s_x+1, s_y)];
double phiU = s_in[gpu_s_scalar_index(s_x, s_y+1)];
double phiD = s_in[gpu_s_scalar_index(s_x, s_y-1)];
double source = (charge / eps) * dx *dx; // Right hand side of the equation
double phi_old = phi;
phi = 0.25 * (phiL + phiR + phiU + phiD + source);
// Record the error
R[gpu_scalar_index(x, y)] = fabs(phi - phi_old);
//__syncthreads();
fi[gpu_scalar_index(x, y)] = phi;
//if (x == 5 && y == 5) printf("%g\n", phi);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ size_t gpu_scalar_index(unsigned int x, unsigned int y)
{
return NX*y+x;
}
__device__ __forceinline__ size_t gpu_s_scalar_index(unsigned int x, unsigned int y)
{
return (2*RAD + nThreads)*y + x;
}
__global__ void gpu_poisson(double *c, double *fi,double *R){
unsigned int y = blockIdx.y;
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int s_y = threadIdx.y + RAD;
unsigned int s_x = threadIdx.x + RAD;
unsigned int xp1 = (x + blockDim.x) % NX;
unsigned int yp1 = (y + blockDim.y) % NY;
unsigned int xm1 = (NX + x - 1) % NX;
unsigned int ym1 = (NY + y - 1) % NY;
__shared__ double s_in[(2*RAD + nThreads)*3];
// load to shared memory (regular cells)
s_in[gpu_s_scalar_index(s_x,s_y)] = fi[gpu_scalar_index(x, y)];
// load halo cells
if (threadIdx.x < RAD) {
s_in[gpu_s_scalar_index(s_x - RAD, s_y)] = fi[gpu_scalar_index(xm1, y)];
s_in[gpu_s_scalar_index(s_x + blockDim.x, s_y)] = fi[gpu_scalar_index(xp1, y)];
}
if (threadIdx.y < RAD) {
s_in[gpu_s_scalar_index(s_x, s_y - RAD)] = fi[gpu_scalar_index(x, ym1)];
s_in[gpu_s_scalar_index(s_x, s_y + blockDim.y)] = fi[gpu_scalar_index(x, yp1)];
}
// Boundary conditions
if (y == 0) {
fi[gpu_scalar_index(x, y)] = voltage;
return;
}
if (y == NY - 1) {
fi[gpu_scalar_index(x, y)] = 0.0;
return;
}
__syncthreads();
double charge = c[gpu_scalar_index(x, y)];
//double phi = fi[gpu_scalar_index(x, y)];
//double phiL = fi[gpu_scalar_index(xm1, y)];
//double phiR = fi[gpu_scalar_index(xp1, y)];
//double phiU = fi[gpu_scalar_index(x, yp1)];
//double phiD = fi[gpu_scalar_index(x, ym1)];
double phi = s_in[gpu_s_scalar_index(s_x, s_y)];
double phiL = s_in[gpu_s_scalar_index(s_x-1, s_y)];
double phiR = s_in[gpu_s_scalar_index(s_x+1, s_y)];
double phiU = s_in[gpu_s_scalar_index(s_x, s_y+1)];
double phiD = s_in[gpu_s_scalar_index(s_x, s_y-1)];
double source = (charge / eps) * dx *dx; // Right hand side of the equation
double phi_old = phi;
phi = 0.25 * (phiL + phiR + phiU + phiD + source);
// Record the error
R[gpu_scalar_index(x, y)] = fabs(phi - phi_old);
//__syncthreads();
fi[gpu_scalar_index(x, y)] = phi;
//if (x == 5 && y == 5) printf("%g\n", phi);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ size_t gpu_scalar_index(unsigned int x, unsigned int y)
{
return NX*y+x;
}
__device__ __forceinline__ size_t gpu_s_scalar_index(unsigned int x, unsigned int y)
{
return (2*RAD + nThreads)*y + x;
}
__global__ void gpu_poisson(double *c, double *fi,double *R){
unsigned int y = blockIdx.y;
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int s_y = threadIdx.y + RAD;
unsigned int s_x = threadIdx.x + RAD;
unsigned int xp1 = (x + blockDim.x) % NX;
unsigned int yp1 = (y + blockDim.y) % NY;
unsigned int xm1 = (NX + x - 1) % NX;
unsigned int ym1 = (NY + y - 1) % NY;
__shared__ double s_in[(2*RAD + nThreads)*3];
// load to shared memory (regular cells)
s_in[gpu_s_scalar_index(s_x,s_y)] = fi[gpu_scalar_index(x, y)];
// load halo cells
if (threadIdx.x < RAD) {
s_in[gpu_s_scalar_index(s_x - RAD, s_y)] = fi[gpu_scalar_index(xm1, y)];
s_in[gpu_s_scalar_index(s_x + blockDim.x, s_y)] = fi[gpu_scalar_index(xp1, y)];
}
if (threadIdx.y < RAD) {
s_in[gpu_s_scalar_index(s_x, s_y - RAD)] = fi[gpu_scalar_index(x, ym1)];
s_in[gpu_s_scalar_index(s_x, s_y + blockDim.y)] = fi[gpu_scalar_index(x, yp1)];
}
// Boundary conditions
if (y == 0) {
fi[gpu_scalar_index(x, y)] = voltage;
return;
}
if (y == NY - 1) {
fi[gpu_scalar_index(x, y)] = 0.0;
return;
}
__syncthreads();
double charge = c[gpu_scalar_index(x, y)];
//double phi = fi[gpu_scalar_index(x, y)];
//double phiL = fi[gpu_scalar_index(xm1, y)];
//double phiR = fi[gpu_scalar_index(xp1, y)];
//double phiU = fi[gpu_scalar_index(x, yp1)];
//double phiD = fi[gpu_scalar_index(x, ym1)];
double phi = s_in[gpu_s_scalar_index(s_x, s_y)];
double phiL = s_in[gpu_s_scalar_index(s_x-1, s_y)];
double phiR = s_in[gpu_s_scalar_index(s_x+1, s_y)];
double phiU = s_in[gpu_s_scalar_index(s_x, s_y+1)];
double phiD = s_in[gpu_s_scalar_index(s_x, s_y-1)];
double source = (charge / eps) * dx *dx; // Right hand side of the equation
double phi_old = phi;
phi = 0.25 * (phiL + phiR + phiU + phiD + source);
// Record the error
R[gpu_scalar_index(x, y)] = fabs(phi - phi_old);
//__syncthreads();
fi[gpu_scalar_index(x, y)] = phi;
//if (x == 5 && y == 5) printf("%g\n", phi);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11gpu_poissonPdS_S_
.globl _Z11gpu_poissonPdS_S_
.p2align 8
.type _Z11gpu_poissonPdS_S_,@function
_Z11gpu_poissonPdS_S_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v6, 0x3ff, v0
s_mul_i32 s8, s15, 0x7a
v_bfe_u32 v7, v0, 10, 10
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, 1, v6
s_mov_b32 s9, exec_lo
v_add_nc_u32_e32 v10, 1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v9, 63, v10
v_add_lshl_u32 v0, v9, v8, 3
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s14, s7
v_add_nc_u32_e32 v1, s4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s8, v1
v_lshlrev_b64 v[2:3], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b64 v[11:12], v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b64 v0, v[11:12]
v_cmpx_eq_u32_e32 0, v6
s_cbranch_execz .LBB0_2
s_add_i32 s10, s4, 0x79
s_add_i32 s12, s4, s7
s_mul_hi_u32 s11, s10, 0x4325c53f
s_mul_hi_u32 s4, s12, 0x4325c53f
s_lshr_b32 s11, s11, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mulk_i32 s11, 0x7a
s_sub_i32 s10, s10, s11
s_lshr_b32 s11, s4, 5
s_add_i32 s4, s10, s8
s_mul_i32 s13, s11, 0x7a
s_lshl_b64 s[10:11], s[4:5], 3
s_sub_i32 s4, s12, s13
s_add_u32 s10, s2, s10
s_addc_u32 s11, s3, s11
s_add_i32 s4, s4, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 3
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
s_clause 0x1
s_load_b64 s[10:11], s[10:11], 0x0
s_load_b64 s[4:5], s[4:5], 0x0
v_add_nc_u32_e32 v13, v9, v8
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v12, s11 :: v_dual_lshlrev_b32 v15, 3, v9
v_mov_b32_e32 v11, s10
s_delay_alu instid0(VALU_DEP_3)
v_add_lshl_u32 v16, v13, s7, 3
v_dual_mov_b32 v14, s5 :: v_dual_mov_b32 v13, s4
ds_store_b64 v15, v[11:12]
ds_store_b64 v16, v[13:14]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v7
s_cbranch_execz .LBB0_4
s_lshr_b32 s5, s6, 16
s_add_i32 s6, s15, 0x64
s_and_b32 s5, 0xffff, s5
s_mul_hi_u32 s7, s6, 0x446f8657
s_add_i32 s8, s15, s5
s_sub_i32 s9, s6, s7
s_mul_hi_u32 s10, s8, 0x446f8657
s_lshr_b32 s9, s9, 1
s_sub_i32 s11, s8, s10
s_add_i32 s9, s9, s7
s_lshr_b32 s7, s11, 1
s_lshr_b32 s9, s9, 6
s_add_i32 s7, s7, s10
s_mulk_i32 s9, 0x65
s_lshr_b32 s7, s7, 6
s_sub_i32 s6, s6, s9
s_mulk_i32 s7, 0x65
v_mad_u64_u32 v[11:12], null, s6, 0x7a, v[1:2]
s_sub_i32 s6, s8, s7
v_dual_mov_b32 v12, 0 :: v_dual_lshlrev_b32 v15, 3, v8
v_mad_u64_u32 v[13:14], null, s6, 0x7a, v[1:2]
v_add_nc_u32_e32 v10, s5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mov_b32_e32 v14, v12
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_mul_u32_u24_e32 v10, 63, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s2, v13
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_b64 v[11:12], v[11:12], off
global_load_b64 v[13:14], v[13:14], off
v_add_lshl_u32 v10, v10, v8, 3
s_waitcnt vmcnt(1)
ds_store_b64 v15, v[11:12]
s_waitcnt vmcnt(0)
ds_store_b64 v10, v[13:14]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_mov_b32 s6, -1
s_mov_b32 s4, 0
s_cmpk_lt_i32 s15, 0x64
s_mov_b32 s5, 0
s_cbranch_scc0 .LBB0_9
s_and_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_12
.LBB0_6:
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccz .LBB0_13
.LBB0_7:
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_14
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_9:
s_cmpk_eq_i32 s15, 0x64
s_mov_b32 s5, -1
s_cbranch_scc0 .LBB0_11
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v10, 0x2fa8, v1
v_mov_b32_e32 v12, 0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_mov_b32_e32 v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v10, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
global_store_b64 v[10:11], v[12:13], off
.LBB0_11:
s_branch .LBB0_6
.LBB0_12:
s_cmp_lg_u32 s15, 0
s_mov_b32 s4, -1
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_7
.LBB0_13:
s_load_b64 s[4:5], s[0:1], 0x0
v_lshlrev_b64 v[13:14], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_add_lshl_u32 v6, v9, v6, 3
s_load_b64 s[0:1], s[0:1], 0x10
v_add_co_u32 v4, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v14, vcc_lo
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, eps@rel32@lo+4
s_addc_u32 s5, s5, eps@rel32@hi+12
s_load_b64 s[4:5], s[4:5], 0x0
global_load_b64 v[15:16], v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[15:16]
v_div_scale_f64 v[19:20], vcc_lo, v[15:16], s[4:5], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[4:5], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[17:18], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[4:5], v[10:11], 1.0
v_fma_f64 v[17:18], v[10:11], v[17:18], v[10:11]
ds_load_2addr_b64 v[9:12], v6 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f64 v[9:10], v[9:10], v[11:12]
v_mul_f64 v[21:22], v[19:20], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[21:22], v[19:20]
v_div_fmas_f64 v[11:12], v[4:5], v[17:18], v[21:22]
v_mul_u32_u24_e32 v4, 63, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v4, v4, v8, 3
ds_load_2addr_b64 v[4:7], v4 offset1:126
s_waitcnt lgkmcnt(0)
v_add_f64 v[6:7], v[9:10], v[6:7]
v_div_fixup_f64 v[8:9], v[11:12], s[4:5], v[15:16]
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, dx@rel32@lo+4
s_addc_u32 s5, s5, dx@rel32@hi+12
s_load_b64 s[4:5], s[4:5], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[6:7], v[4:5]
s_waitcnt lgkmcnt(0)
v_mul_f64 v[6:7], v[8:9], s[4:5]
v_add_co_u32 v8, vcc_lo, s0, v13
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], s[4:5], v[6:7], v[4:5]
ds_load_b64 v[6:7], v0
s_waitcnt lgkmcnt(0)
v_fma_f64 v[6:7], v[4:5], 0x3fd00000, -v[6:7]
v_ldexp_f64 v[4:5], v[4:5], -2
v_and_b32_e32 v7, 0x7fffffff, v7
global_store_b64 v[8:9], v[6:7], off
global_store_b64 v[2:3], v[4:5], off
s_cbranch_execnz .LBB0_8
.LBB0_14:
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, voltage@rel32@lo+4
s_addc_u32 s1, s1, voltage@rel32@hi+12
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11gpu_poissonPdS_S_
.amdhsa_group_segment_fixed_size 1512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11gpu_poissonPdS_S_, .Lfunc_end0-_Z11gpu_poissonPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected dx
.type dx,@object
.data
.globl dx
.p2align 3, 0x0
dx:
.quad 0x3f847ae147ae147b
.size dx, 8
.protected voltage
.type voltage,@object
.globl voltage
.p2align 3, 0x0
voltage:
.quad 0x40c3880000000000
.size voltage, 8
.protected eps
.type eps,@object
.globl eps
.p2align 3, 0x0
eps:
.quad 0x3f1a36e2eb1c432d
.size eps, 8
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym dx
.addrsig_sym voltage
.addrsig_sym eps
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1512
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11gpu_poissonPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11gpu_poissonPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ size_t gpu_scalar_index(unsigned int x, unsigned int y)
{
return NX*y+x;
}
__device__ __forceinline__ size_t gpu_s_scalar_index(unsigned int x, unsigned int y)
{
return (2*RAD + nThreads)*y + x;
}
__global__ void gpu_poisson(double *c, double *fi,double *R){
unsigned int y = blockIdx.y;
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int s_y = threadIdx.y + RAD;
unsigned int s_x = threadIdx.x + RAD;
unsigned int xp1 = (x + blockDim.x) % NX;
unsigned int yp1 = (y + blockDim.y) % NY;
unsigned int xm1 = (NX + x - 1) % NX;
unsigned int ym1 = (NY + y - 1) % NY;
__shared__ double s_in[(2*RAD + nThreads)*3];
// load to shared memory (regular cells)
s_in[gpu_s_scalar_index(s_x,s_y)] = fi[gpu_scalar_index(x, y)];
// load halo cells
if (threadIdx.x < RAD) {
s_in[gpu_s_scalar_index(s_x - RAD, s_y)] = fi[gpu_scalar_index(xm1, y)];
s_in[gpu_s_scalar_index(s_x + blockDim.x, s_y)] = fi[gpu_scalar_index(xp1, y)];
}
if (threadIdx.y < RAD) {
s_in[gpu_s_scalar_index(s_x, s_y - RAD)] = fi[gpu_scalar_index(x, ym1)];
s_in[gpu_s_scalar_index(s_x, s_y + blockDim.y)] = fi[gpu_scalar_index(x, yp1)];
}
// Boundary conditions
if (y == 0) {
fi[gpu_scalar_index(x, y)] = voltage;
return;
}
if (y == NY - 1) {
fi[gpu_scalar_index(x, y)] = 0.0;
return;
}
__syncthreads();
double charge = c[gpu_scalar_index(x, y)];
//double phi = fi[gpu_scalar_index(x, y)];
//double phiL = fi[gpu_scalar_index(xm1, y)];
//double phiR = fi[gpu_scalar_index(xp1, y)];
//double phiU = fi[gpu_scalar_index(x, yp1)];
//double phiD = fi[gpu_scalar_index(x, ym1)];
double phi = s_in[gpu_s_scalar_index(s_x, s_y)];
double phiL = s_in[gpu_s_scalar_index(s_x-1, s_y)];
double phiR = s_in[gpu_s_scalar_index(s_x+1, s_y)];
double phiU = s_in[gpu_s_scalar_index(s_x, s_y+1)];
double phiD = s_in[gpu_s_scalar_index(s_x, s_y-1)];
double source = (charge / eps) * dx *dx; // Right hand side of the equation
double phi_old = phi;
phi = 0.25 * (phiL + phiR + phiU + phiD + source);
// Record the error
R[gpu_scalar_index(x, y)] = fabs(phi - phi_old);
//__syncthreads();
fi[gpu_scalar_index(x, y)] = phi;
//if (x == 5 && y == 5) printf("%g\n", phi);
} | .text
.file "gpu_poisson.hip"
.globl _Z26__device_stub__gpu_poissonPdS_S_ # -- Begin function _Z26__device_stub__gpu_poissonPdS_S_
.p2align 4, 0x90
.type _Z26__device_stub__gpu_poissonPdS_S_,@function
_Z26__device_stub__gpu_poissonPdS_S_: # @_Z26__device_stub__gpu_poissonPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11gpu_poissonPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__gpu_poissonPdS_S_, .Lfunc_end0-_Z26__device_stub__gpu_poissonPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gpu_poissonPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $dx, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $voltage, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $eps, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type dx,@object # @dx
.local dx
.comm dx,8,8
.type voltage,@object # @voltage
.local voltage
.comm voltage,8,8
.type eps,@object # @eps
.local eps
.comm eps,8,8
.type _Z11gpu_poissonPdS_S_,@object # @_Z11gpu_poissonPdS_S_
.section .rodata,"a",@progbits
.globl _Z11gpu_poissonPdS_S_
.p2align 3, 0x0
_Z11gpu_poissonPdS_S_:
.quad _Z26__device_stub__gpu_poissonPdS_S_
.size _Z11gpu_poissonPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11gpu_poissonPdS_S_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "dx"
.size .L__unnamed_2, 3
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "voltage"
.size .L__unnamed_3, 8
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "eps"
.size .L__unnamed_4, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__gpu_poissonPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dx
.addrsig_sym voltage
.addrsig_sym eps
.addrsig_sym _Z11gpu_poissonPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11gpu_poissonPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000ea20000002600 */
/*0050*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x001fe20003f05270 */
/*0060*/ IMAD R5, R5, c[0x0][0x0], R4 ; /* 0x0000000005057a24 */
/* 0x002fc800078e0204 */
/*0070*/ IMAD R18, R0, 0x7a, R5 ; /* 0x0000007a00127824 */
/* 0x004fd000078e0205 */
/*0080*/ @!P0 IADD3 R8, R5.reuse, 0x79, RZ ; /* 0x0000007905088810 */
/* 0x040fe40007ffe0ff */
/*0090*/ @!P0 IADD3 R9, R5, c[0x0][0x0], RZ ; /* 0x0000000005098a10 */
/* 0x000fc60007ffe0ff */
/*00a0*/ @!P0 IMAD.WIDE.U32 R2, R8, 0x4325c53f, RZ ; /* 0x4325c53f08028825 */
/* 0x000fc800078e00ff */
/*00b0*/ @!P0 IMAD.WIDE.U32 R6, R9, 0x4325c53f, RZ ; /* 0x4325c53f09068825 */
/* 0x000fe200078e00ff */
/*00c0*/ @!P0 SHF.R.U32.HI R3, RZ, 0x5, R3 ; /* 0x00000005ff038819 */
/* 0x000fc80000011603 */
/*00d0*/ @!P0 SHF.R.U32.HI R6, RZ, 0x5, R7 ; /* 0x00000005ff068819 */
/* 0x000fe20000011607 */
/*00e0*/ @!P0 IMAD R3, R3, -0x7a, R8 ; /* 0xffffff8603038824 */
/* 0x000fc800078e0208 */
/*00f0*/ @!P0 IMAD R9, R6, -0x7a, R9 ; /* 0xffffff8606098824 */
/* 0x000fe400078e0209 */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; /* 0x00000008ff067424 */
/* 0x000fe400078e00ff */
/*0110*/ @!P0 IMAD R11, R0.reuse, 0x7a, R3 ; /* 0x0000007a000b8824 */
/* 0x040fe400078e0203 */
/*0120*/ @!P0 IMAD R9, R0, 0x7a, R9 ; /* 0x0000007a00098824 */
/* 0x000fe400078e0209 */
/*0130*/ IMAD.WIDE.U32 R2, R18, R6, c[0x0][0x168] ; /* 0x00005a0012027625 */
/* 0x000fc800078e0006 */
/*0140*/ @!P0 IMAD.WIDE.U32 R10, R11, R6, c[0x0][0x168] ; /* 0x00005a000b0a8625 */
/* 0x000fc800078e0006 */
/*0150*/ @!P0 IMAD.WIDE.U32 R12, R9, R6, c[0x0][0x168] ; /* 0x00005a00090c8625 */
/* 0x000fe400078e0006 */
/*0160*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1b00 */
/*0170*/ @!P0 LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a8981 */
/* 0x000ee8000c1e1b00 */
/*0180*/ @!P0 LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c8981 */
/* 0x000f22000c1e1b00 */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, 0x3f ; /* 0x0000003fff0e7424 */
/* 0x000fe200078e00ff */
/*01a0*/ BSSY B0, 0x3f0 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*01b0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*01c0*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e240000002200 */
/*01d0*/ IMAD R15, R7, R14, 0x3f ; /* 0x0000003f070f7424 */
/* 0x001fc400078e020e */
/*01e0*/ @!P0 IMAD R17, R7, 0x1f8, RZ ; /* 0x000001f807118824 */
/* 0x000fe400078e02ff */
/*01f0*/ IMAD.IADD R16, R15, 0x1, R4 ; /* 0x000000010f107824 */
/* 0x000fc800078e0204 */
/*0200*/ IMAD.SHL.U32 R15, R16, 0x8, RZ ; /* 0x00000008100f7824 */
/* 0x000fc800078e00ff */
/*0210*/ @!P0 IMAD R15, R6, c[0x0][0x0], R15 ; /* 0x00000000060f8a24 */
/* 0x000fe200078e020f */
/*0220*/ STS.64 [R16.X8+0x8], R8 ; /* 0x0000080810007388 */
/* 0x0041e80000008a00 */
/*0230*/ @!P0 STS.64 [R17+0x1f8], R10 ; /* 0x0001f80a11008388 */
/* 0x0081e80000000a00 */
/*0240*/ @!P0 STS.64 [R15+0x8], R12 ; /* 0x0000080c0f008388 */
/* 0x0101e20000000a00 */
/*0250*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0260*/ @P0 BRA 0x3e0 ; /* 0x0000017000000947 */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R13, R0.reuse, 0x64, RZ ; /* 0x00000064000d7810 */
/* 0x041fe40007ffe0ff */
/*0280*/ IADD3 R15, R0, c[0x0][0x4], RZ ; /* 0x00000100000f7a10 */
/* 0x000fc60007ffe0ff */
/*0290*/ IMAD.WIDE.U32 R10, R13, 0x446f8657, RZ ; /* 0x446f86570d0a7825 */
/* 0x000fc800078e00ff */
/*02a0*/ IMAD.WIDE.U32 R8, R15, 0x446f8657, RZ ; /* 0x446f86570f087825 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD.IADD R10, R13, 0x1, -R11 ; /* 0x000000010d0a7824 */
/* 0x000fe400078e0a0b */
/*02c0*/ IMAD.IADD R8, R15, 0x1, -R9 ; /* 0x000000010f087824 */
/* 0x000fc600078e0a09 */
/*02d0*/ LEA.HI R10, R10, R11, RZ, 0x1f ; /* 0x0000000b0a0a7211 */
/* 0x000fe400078ff8ff */
/*02e0*/ LEA.HI R8, R8, R9, RZ, 0x1f ; /* 0x0000000908087211 */
/* 0x000fe400078ff8ff */
/*02f0*/ SHF.R.U32.HI R10, RZ, 0x6, R10 ; /* 0x00000006ff0a7819 */
/* 0x000fe4000001160a */
/*0300*/ SHF.R.U32.HI R8, RZ, 0x6, R8 ; /* 0x00000006ff087819 */
/* 0x000fc60000011608 */
/*0310*/ IMAD R10, R10, -0x65, R13 ; /* 0xffffff9b0a0a7824 */
/* 0x000fe400078e020d */
/*0320*/ IMAD R8, R8, -0x65, R15 ; /* 0xffffff9b08087824 */
/* 0x000fe400078e020f */
/*0330*/ IMAD R9, R10, 0x7a, R5.reuse ; /* 0x0000007a0a097824 */
/* 0x100fe400078e0205 */
/*0340*/ IMAD R11, R8, 0x7a, R5 ; /* 0x0000007a080b7824 */
/* 0x000fe400078e0205 */
/*0350*/ IMAD.WIDE.U32 R8, R9, R6, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fc800078e0006 */
/*0360*/ IMAD.WIDE.U32 R10, R11, R6, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fe400078e0006 */
/*0370*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*0380*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1b00 */
/*0390*/ IADD3.X R12, R7, c[0x0][0x4], RZ, PT, !PT ; /* 0x00000100070c7a10 */
/* 0x000fe20003ffe4ff */
/*03a0*/ IMAD.SHL.U32 R7, R4, 0x8, RZ ; /* 0x0000000804077824 */
/* 0x000fc800078e00ff */
/*03b0*/ IMAD R7, R12, 0x1f8, R7 ; /* 0x000001f80c077824 */
/* 0x000fe200078e0207 */
/*03c0*/ STS.64 [R4.X8+0x8], R8 ; /* 0x0000080804007388 */
/* 0x0041e80000008a00 */
/*03d0*/ STS.64 [R7+0x8], R10 ; /* 0x0000080a07007388 */
/* 0x0081e40000000a00 */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*03f0*/ @!P1 BRA 0x710 ; /* 0x0000031000009947 */
/* 0x000fea0003800000 */
/*0400*/ ISETP.NE.AND P0, PT, R0, 0x64, PT ; /* 0x000000640000780c */
/* 0x000fda0003f05270 */
/*0410*/ @!P0 IADD3 R7, R5, 0x2fa8, RZ ; /* 0x00002fa805078810 */
/* 0x000fca0007ffe0ff */
/*0420*/ @!P0 IMAD.WIDE.U32 R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007068625 */
/* 0x000fca00078e0006 */
/*0430*/ @!P0 STG.E.64 [R6.64], RZ ; /* 0x000000ff06008986 */
/* 0x0001e2000c101b04 */
/*0440*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0450*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0460*/ SHF.L.U32 R17, R18, 0x3, RZ ; /* 0x0000000312117819 */
/* 0x000fe400000006ff */
/*0470*/ SHF.R.U32.HI R18, RZ, 0x1d, R18 ; /* 0x0000001dff127819 */
/* 0x000fe40000011612 */
/*0480*/ IADD3 R6, P0, R17, c[0x0][0x160], RZ ; /* 0x0000580011067a10 */
/* 0x001fc80007f1e0ff */
/*0490*/ IADD3.X R7, R18, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590012077a10 */
/* 0x000fcc00007fe4ff */
/*04a0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*04b0*/ MUFU.RCP64H R5, c[0x3][0x14] ; /* 0x00c0050000057b08 */
/* 0x000e220000001800 */
/*04c0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x3][0x10] ; /* 0x00c00400ff0a7624 */
/* 0x000fe200078e00ff */
/*04d0*/ BSSY B0, 0x5f0 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*04e0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x3][0x14] ; /* 0x00c00500ff0b7624 */
/* 0x000fe400078e00ff */
/*04f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fcc00078e00ff */
/*0500*/ DFMA R8, R4, -R10, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c000000080a */
/*0510*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0520*/ DFMA R8, R4, R8, R4 ; /* 0x000000080408722b */
/* 0x001e0c0000000004 */
/*0530*/ DFMA R4, R8, -R10, 1 ; /* 0x3ff000000804742b */
/* 0x001e0c000000080a */
/*0540*/ DFMA R4, R8, R4, R8 ; /* 0x000000040804722b */
/* 0x001e8c0000000008 */
/*0550*/ DMUL R8, R6, R4 ; /* 0x0000000406087228 */
/* 0x004e220000000000 */
/*0560*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*0570*/ DFMA R10, R8, -c[0x3][0x10], R6 ; /* 0x80c00400080a7a2b */
/* 0x001e0c0000000006 */
/*0580*/ DFMA R8, R4, R10, R8 ; /* 0x0000000a0408722b */
/* 0x001e140000000008 */
/*0590*/ FFMA R0, RZ, c[0x3][0x14], R9 ; /* 0x00c00500ff007a23 */
/* 0x001fca0000000009 */
/*05a0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*05b0*/ @P0 BRA P1, 0x5e0 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*05c0*/ MOV R0, 0x5e0 ; /* 0x000005e000007802 */
/* 0x000fe40000000f00 */
/*05d0*/ CALL.REL.NOINC 0x760 ; /* 0x0000018000007944 */
/* 0x000fea0003c00000 */
/*05e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05f0*/ LDS.64 R6, [R16.X8+0x10] ; /* 0x0000100010067984 */
/* 0x000fe20000008a00 */
/*0600*/ DMUL R8, R8, c[0x3][0x0] ; /* 0x00c0000008087a28 */
/* 0x000fc60000000000 */
/*0610*/ LDS.64 R10, [R16.X8] ; /* 0x00000000100a7984 */
/* 0x000e280000008a00 */
/*0620*/ LDS.64 R12, [R16.X8+0x200] ; /* 0x00020000100c7984 */
/* 0x000ea80000008a00 */
/*0630*/ LDS.64 R14, [R16.X8+-0x1f0] ; /* 0xfffe1000100e7984 */
/* 0x002e680000008a00 */
/*0640*/ LDS.64 R4, [R16.X8+0x8] ; /* 0x0000080010047984 */
/* 0x000ee20000008a00 */
/*0650*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x001e8c000000000a */
/*0660*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x004e4c000000000c */
/*0670*/ DADD R6, R6, R14 ; /* 0x0000000006067229 */
/* 0x002e0c000000000e */
/*0680*/ DFMA R6, R8, c[0x3][0x0], R6 ; /* 0x00c0000008067a2b */
/* 0x0010640000000006 */
/*0690*/ IADD3 R8, P0, R17, c[0x0][0x170], RZ ; /* 0x00005c0011087a10 */
/* 0x001fc80007f1e0ff */
/*06a0*/ DMUL R6, R6, 0.25 ; /* 0x3fd0000006067828 */
/* 0x002ee20000000000 */
/*06b0*/ IADD3.X R9, R18, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0012097a10 */
/* 0x000fca00007fe4ff */
/*06c0*/ DADD R4, R6, -R4 ; /* 0x0000000006047229 */
/* 0x008e0c0000000804 */
/*06d0*/ DADD R4, -RZ, |R4| ; /* 0x00000000ff047229 */
/* 0x001e0e0000000504 */
/*06e0*/ STG.E.64 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x001fe8000c101b04 */
/*06f0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101b04 */
/*0700*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0710*/ IMAD.WIDE.U32 R6, R5, R6, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fc800078e0006 */
/*0720*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x3][0x8] ; /* 0x00c00200ff027624 */
/* 0x000fe400078e00ff */
/*0730*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x3][0xc] ; /* 0x00c00300ff037624 */
/* 0x000fca00078e00ff */
/*0740*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x000fe2000c101b04 */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x3][0x14] ; /* 0x00c00500ff137624 */
/* 0x000fe200078e00ff */
/*0770*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0780*/ IMAD.MOV.U32 R23, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff177424 */
/* 0x000fe200078e00ff */
/*0790*/ LOP3.LUT R21, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007157812 */
/* 0x000fe200078ec0ff */
/*07a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*07b0*/ FSETP.GEU.AND P0, PT, |R19|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x040fe20003f0e200 */
/*07c0*/ BSSY B1, 0xd10 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*07d0*/ LOP3.LUT R4, R19.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff13047812 */
/* 0x040fe200078ec0ff */
/*07e0*/ IMAD.MOV.U32 R22, RZ, RZ, R21 ; /* 0x000000ffff167224 */
/* 0x000fe200078e0015 */
/*07f0*/ LOP3.LUT R20, R19, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000013147812 */
/* 0x000fc400078ec0ff */
/*0800*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0810*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x3][0x10] ; /* 0x00c00400ff047624 */
/* 0x000fe200078e00ff */
/*0820*/ ISETP.GE.U32.AND P1, PT, R21, R20.reuse, PT ; /* 0x000000141500720c */
/* 0x080fe40003f26070 */
/*0830*/ MOV R25, R20 ; /* 0x0000001400197202 */
/* 0x000fe40000000f00 */
/*0840*/ SEL R23, R23, 0x63400000, !P1 ; /* 0x6340000017177807 */
/* 0x000fe20004800000 */
/*0850*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, c[0x3][0x10] ; /* 0x00c00400ff088624 */
/* 0x000fe200078e00ff */
/*0860*/ @!P0 MOV R9, c[0x3][0x14] ; /* 0x00c0050000098a02 */
/* 0x000fe40000000f00 */
/*0870*/ @!P2 LOP3.LUT R14, R23, 0x80000000, R7, 0xf8, !PT ; /* 0x80000000170ea812 */
/* 0x000fc800078ef807 */
/*0880*/ @!P0 DMUL R4, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008048828 */
/* 0x0000620000000000 */
/*0890*/ @!P2 LOP3.LUT R15, R14, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000e0fa812 */
/* 0x000fe200078efcff */
/*08a0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0006 */
/*08b0*/ LOP3.LUT R9, R23, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff17097812 */
/* 0x000fe200078ef807 */
/*08c0*/ @!P2 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0ea224 */
/* 0x000fe400078e00ff */
/*08d0*/ MUFU.RCP64H R11, R5 ; /* 0x00000005000b7308 */
/* 0x002e280000001800 */
/*08e0*/ @!P2 DFMA R8, R8, 2, -R14 ; /* 0x400000000808a82b */
/* 0x000e62000000080e */
/*08f0*/ @!P0 LOP3.LUT R25, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005198812 */
/* 0x000fc800078ec0ff */
/*0900*/ IADD3 R24, R25, -0x1, RZ ; /* 0xffffffff19187810 */
/* 0x000fca0007ffe0ff */
/*0910*/ @!P2 LOP3.LUT R22, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000916a812 */
/* 0x002fe200078ec0ff */
/*0920*/ DFMA R12, R10, -R4, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e060000000804 */
/*0930*/ IADD3 R14, R22, -0x1, RZ ; /* 0xffffffff160e7810 */
/* 0x000fc60007ffe0ff */
/*0940*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e22000000000c */
/*0950*/ ISETP.GT.U32.AND P0, PT, R14, 0x7feffffe, PT ; /* 0x7feffffe0e00780c */
/* 0x000fc80003f04070 */
/*0960*/ ISETP.GT.U32.OR P0, PT, R24, 0x7feffffe, P0 ; /* 0x7feffffe1800780c */
/* 0x000fe20000704470 */
/*0970*/ DFMA R10, R10, R12, R10 ; /* 0x0000000c0a0a722b */
/* 0x001e0c000000000a */
/*0980*/ DFMA R12, R10, -R4, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c0000000804 */
/*0990*/ DFMA R10, R10, R12, R10 ; /* 0x0000000c0a0a722b */
/* 0x001e0c000000000a */
/*09a0*/ DMUL R12, R10, R8 ; /* 0x000000080a0c7228 */
/* 0x001e0c0000000000 */
/*09b0*/ DFMA R14, R12, -R4, R8 ; /* 0x800000040c0e722b */
/* 0x001e0c0000000008 */
/*09c0*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x001062000000000c */
/*09d0*/ @P0 BRA 0xb80 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*09e0*/ IMAD.IADD R20, R21, 0x1, -R20 ; /* 0x0000000115147824 */
/* 0x000fe400078e0a14 */
/*09f0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0a00*/ IMNMX R20, R20, -0x46a00000, !PT ; /* 0xb960000014147817 */
/* 0x000fc80007800200 */
/*0a10*/ IMNMX R20, R20, 0x46a00000, PT ; /* 0x46a0000014147817 */
/* 0x000fca0003800200 */
/*0a20*/ IMAD.IADD R20, R20, 0x1, -R23 ; /* 0x0000000114147824 */
/* 0x000fca00078e0a17 */
/*0a30*/ IADD3 R7, R20, 0x7fe00000, RZ ; /* 0x7fe0000014077810 */
/* 0x000fcc0007ffe0ff */
/*0a40*/ DMUL R10, R14, R6 ; /* 0x000000060e0a7228 */
/* 0x003e140000000000 */
/*0a50*/ FSETP.GTU.AND P0, PT, |R11|, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x001fda0003f0c200 */
/*0a60*/ @P0 BRA 0xd00 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*0a70*/ DFMA R4, R14, -R4, R8 ; /* 0x800000040e04722b */
/* 0x000e220000000008 */
/*0a80*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0a90*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0aa0*/ LOP3.LUT R4, R5, c[0x3][0x14], RZ, 0x3c, !PT ; /* 0x00c0050005047a12 */
/* 0x000fc800078e3cff */
/*0ab0*/ LOP3.LUT R9, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004097812 */
/* 0x000fc800078ec0ff */
/*0ac0*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fc600078efcff */
/*0ad0*/ @!P0 BRA 0xd00 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ IMAD.MOV R5, RZ, RZ, -R20 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a14 */
/*0af0*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e220000008000 */
/*0b00*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0b10*/ DFMA R4, R10, -R4, R14 ; /* 0x800000040a04722b */
/* 0x000e46000000000e */
/*0b20*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*0b30*/ IADD3 R4, -R20, -0x43300000, RZ ; /* 0xbcd0000014047810 */
/* 0x002fc80007ffe1ff */
/*0b40*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0b50*/ FSEL R10, R6, R10, !P0 ; /* 0x0000000a060a7208 */
/* 0x000fe40004000000 */
/*0b60*/ FSEL R11, R9, R11, !P0 ; /* 0x0000000b090b7208 */
/* 0x000fe20004000000 */
/*0b70*/ BRA 0xd00 ; /* 0x0000018000007947 */
/* 0x000fea0003800000 */
/*0b80*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0b90*/ @P0 BRA 0xce0 ; /* 0x0000014000000947 */
/* 0x004fea0003800000 */
/*0ba0*/ MOV R4, c[0x3][0x10] ; /* 0x00c0040000047a02 */
/* 0x000fe20000000f00 */
/*0bb0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x3][0x14] ; /* 0x00c00500ff057624 */
/* 0x000fcc00078e00ff */
/*0bc0*/ DSETP.NAN.AND P0, PT, R4, c[0x3][0x10], PT ; /* 0x00c004000400762a */
/* 0x000e9c0003f08000 */
/*0bd0*/ @P0 BRA 0xcb0 ; /* 0x000000d000000947 */
/* 0x004fea0003800000 */
/*0be0*/ ISETP.NE.AND P0, PT, R22, R25, PT ; /* 0x000000191600720c */
/* 0x000fe20003f05270 */
/*0bf0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x001fe400078e00ff */
/*0c00*/ IMAD.MOV.U32 R11, RZ, RZ, -0x80000 ; /* 0xfff80000ff0b7424 */
/* 0x000fd400078e00ff */
/*0c10*/ @!P0 BRA 0xd00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0c20*/ ISETP.NE.AND P0, PT, R22, 0x7ff00000, PT ; /* 0x7ff000001600780c */
/* 0x000fe40003f05270 */
/*0c30*/ LOP3.LUT R6, R7, c[0x3][0x14], RZ, 0x3c, !PT ; /* 0x00c0050007067a12 */
/* 0x000fe400078e3cff */
/*0c40*/ ISETP.EQ.OR P0, PT, R25, RZ, !P0 ; /* 0x000000ff1900720c */
/* 0x000fe40004702670 */
/*0c50*/ LOP3.LUT R11, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000060b7812 */
/* 0x000fd600078ec0ff */
/*0c60*/ @P0 LOP3.LUT R4, R11, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000b040812 */
/* 0x000fe200078efcff */
/*0c70*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe400078e00ff */
/*0c80*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0c90*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, R4 ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e0004 */
/*0ca0*/ BRA 0xd00 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0cb0*/ LOP3.LUT R11, R19, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000130b7812 */
/* 0x001fe400078efcff */
/*0cc0*/ MOV R10, c[0x3][0x10] ; /* 0x00c00400000a7a02 */
/* 0x000fe20000000f00 */
/*0cd0*/ BRA 0xd00 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0ce0*/ LOP3.LUT R11, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070b7812 */
/* 0x001fe200078efcff */
/*0cf0*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fc400078e0006 */
/*0d00*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d10*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0d20*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc400078e00ff */
/*0d30*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000a */
/*0d40*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000b */
/*0d50*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff2a004007950 */
/* 0x000fec0003c3ffff */
/*0d60*/ BRA 0xd60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11gpu_poissonPdS_S_
.globl _Z11gpu_poissonPdS_S_
.p2align 8
.type _Z11gpu_poissonPdS_S_,@function
_Z11gpu_poissonPdS_S_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v6, 0x3ff, v0
s_mul_i32 s8, s15, 0x7a
v_bfe_u32 v7, v0, 10, 10
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, 1, v6
s_mov_b32 s9, exec_lo
v_add_nc_u32_e32 v10, 1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v9, 63, v10
v_add_lshl_u32 v0, v9, v8, 3
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s14, s7
v_add_nc_u32_e32 v1, s4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s8, v1
v_lshlrev_b64 v[2:3], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b64 v[11:12], v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b64 v0, v[11:12]
v_cmpx_eq_u32_e32 0, v6
s_cbranch_execz .LBB0_2
s_add_i32 s10, s4, 0x79
s_add_i32 s12, s4, s7
s_mul_hi_u32 s11, s10, 0x4325c53f
s_mul_hi_u32 s4, s12, 0x4325c53f
s_lshr_b32 s11, s11, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mulk_i32 s11, 0x7a
s_sub_i32 s10, s10, s11
s_lshr_b32 s11, s4, 5
s_add_i32 s4, s10, s8
s_mul_i32 s13, s11, 0x7a
s_lshl_b64 s[10:11], s[4:5], 3
s_sub_i32 s4, s12, s13
s_add_u32 s10, s2, s10
s_addc_u32 s11, s3, s11
s_add_i32 s4, s4, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 3
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
s_clause 0x1
s_load_b64 s[10:11], s[10:11], 0x0
s_load_b64 s[4:5], s[4:5], 0x0
v_add_nc_u32_e32 v13, v9, v8
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v12, s11 :: v_dual_lshlrev_b32 v15, 3, v9
v_mov_b32_e32 v11, s10
s_delay_alu instid0(VALU_DEP_3)
v_add_lshl_u32 v16, v13, s7, 3
v_dual_mov_b32 v14, s5 :: v_dual_mov_b32 v13, s4
ds_store_b64 v15, v[11:12]
ds_store_b64 v16, v[13:14]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v7
s_cbranch_execz .LBB0_4
s_lshr_b32 s5, s6, 16
s_add_i32 s6, s15, 0x64
s_and_b32 s5, 0xffff, s5
s_mul_hi_u32 s7, s6, 0x446f8657
s_add_i32 s8, s15, s5
s_sub_i32 s9, s6, s7
s_mul_hi_u32 s10, s8, 0x446f8657
s_lshr_b32 s9, s9, 1
s_sub_i32 s11, s8, s10
s_add_i32 s9, s9, s7
s_lshr_b32 s7, s11, 1
s_lshr_b32 s9, s9, 6
s_add_i32 s7, s7, s10
s_mulk_i32 s9, 0x65
s_lshr_b32 s7, s7, 6
s_sub_i32 s6, s6, s9
s_mulk_i32 s7, 0x65
v_mad_u64_u32 v[11:12], null, s6, 0x7a, v[1:2]
s_sub_i32 s6, s8, s7
v_dual_mov_b32 v12, 0 :: v_dual_lshlrev_b32 v15, 3, v8
v_mad_u64_u32 v[13:14], null, s6, 0x7a, v[1:2]
v_add_nc_u32_e32 v10, s5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mov_b32_e32 v14, v12
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_mul_u32_u24_e32 v10, 63, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_add_co_u32 v11, vcc_lo, s2, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s2, v13
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_b64 v[11:12], v[11:12], off
global_load_b64 v[13:14], v[13:14], off
v_add_lshl_u32 v10, v10, v8, 3
s_waitcnt vmcnt(1)
ds_store_b64 v15, v[11:12]
s_waitcnt vmcnt(0)
ds_store_b64 v10, v[13:14]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_mov_b32 s6, -1
s_mov_b32 s4, 0
s_cmpk_lt_i32 s15, 0x64
s_mov_b32 s5, 0
s_cbranch_scc0 .LBB0_9
s_and_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_12
.LBB0_6:
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccz .LBB0_13
.LBB0_7:
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_14
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_9:
s_cmpk_eq_i32 s15, 0x64
s_mov_b32 s5, -1
s_cbranch_scc0 .LBB0_11
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v10, 0x2fa8, v1
v_mov_b32_e32 v12, 0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_mov_b32_e32 v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v10, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
global_store_b64 v[10:11], v[12:13], off
.LBB0_11:
s_branch .LBB0_6
.LBB0_12:
s_cmp_lg_u32 s15, 0
s_mov_b32 s4, -1
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_7
.LBB0_13:
s_load_b64 s[4:5], s[0:1], 0x0
v_lshlrev_b64 v[13:14], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_add_lshl_u32 v6, v9, v6, 3
s_load_b64 s[0:1], s[0:1], 0x10
v_add_co_u32 v4, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v14, vcc_lo
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, eps@rel32@lo+4
s_addc_u32 s5, s5, eps@rel32@hi+12
s_load_b64 s[4:5], s[4:5], 0x0
global_load_b64 v[15:16], v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[15:16]
v_div_scale_f64 v[19:20], vcc_lo, v[15:16], s[4:5], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[4:5], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[17:18], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[4:5], v[10:11], 1.0
v_fma_f64 v[17:18], v[10:11], v[17:18], v[10:11]
ds_load_2addr_b64 v[9:12], v6 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f64 v[9:10], v[9:10], v[11:12]
v_mul_f64 v[21:22], v[19:20], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[21:22], v[19:20]
v_div_fmas_f64 v[11:12], v[4:5], v[17:18], v[21:22]
v_mul_u32_u24_e32 v4, 63, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v4, v4, v8, 3
ds_load_2addr_b64 v[4:7], v4 offset1:126
s_waitcnt lgkmcnt(0)
v_add_f64 v[6:7], v[9:10], v[6:7]
v_div_fixup_f64 v[8:9], v[11:12], s[4:5], v[15:16]
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, dx@rel32@lo+4
s_addc_u32 s5, s5, dx@rel32@hi+12
s_load_b64 s[4:5], s[4:5], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[6:7], v[4:5]
s_waitcnt lgkmcnt(0)
v_mul_f64 v[6:7], v[8:9], s[4:5]
v_add_co_u32 v8, vcc_lo, s0, v13
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], s[4:5], v[6:7], v[4:5]
ds_load_b64 v[6:7], v0
s_waitcnt lgkmcnt(0)
v_fma_f64 v[6:7], v[4:5], 0x3fd00000, -v[6:7]
v_ldexp_f64 v[4:5], v[4:5], -2
v_and_b32_e32 v7, 0x7fffffff, v7
global_store_b64 v[8:9], v[6:7], off
global_store_b64 v[2:3], v[4:5], off
s_cbranch_execnz .LBB0_8
.LBB0_14:
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, voltage@rel32@lo+4
s_addc_u32 s1, s1, voltage@rel32@hi+12
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11gpu_poissonPdS_S_
.amdhsa_group_segment_fixed_size 1512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11gpu_poissonPdS_S_, .Lfunc_end0-_Z11gpu_poissonPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected dx
.type dx,@object
.data
.globl dx
.p2align 3, 0x0
dx:
.quad 0x3f847ae147ae147b
.size dx, 8
.protected voltage
.type voltage,@object
.globl voltage
.p2align 3, 0x0
voltage:
.quad 0x40c3880000000000
.size voltage, 8
.protected eps
.type eps,@object
.globl eps
.p2align 3, 0x0
eps:
.quad 0x3f1a36e2eb1c432d
.size eps, 8
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym dx
.addrsig_sym voltage
.addrsig_sym eps
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1512
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11gpu_poissonPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11gpu_poissonPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b27b3_00000000-6_gpu_poisson.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11gpu_poissonPdS_S_PdS_S_
.type _Z35__device_stub__Z11gpu_poissonPdS_S_PdS_S_, @function
_Z35__device_stub__Z11gpu_poissonPdS_S_PdS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11gpu_poissonPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z35__device_stub__Z11gpu_poissonPdS_S_PdS_S_, .-_Z35__device_stub__Z11gpu_poissonPdS_S_PdS_S_
.globl _Z11gpu_poissonPdS_S_
.type _Z11gpu_poissonPdS_S_, @function
_Z11gpu_poissonPdS_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11gpu_poissonPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11gpu_poissonPdS_S_, .-_Z11gpu_poissonPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11gpu_poissonPdS_S_"
.LC1:
.string "dx"
.LC2:
.string "voltage"
.LC3:
.string "eps"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gpu_poissonPdS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2dx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7voltage(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3eps(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3eps
.comm _ZL3eps,8,8
.local _ZL7voltage
.comm _ZL7voltage,8,8
.local _ZL2dx
.comm _ZL2dx,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_poisson.hip"
.globl _Z26__device_stub__gpu_poissonPdS_S_ # -- Begin function _Z26__device_stub__gpu_poissonPdS_S_
.p2align 4, 0x90
.type _Z26__device_stub__gpu_poissonPdS_S_,@function
_Z26__device_stub__gpu_poissonPdS_S_: # @_Z26__device_stub__gpu_poissonPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11gpu_poissonPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__gpu_poissonPdS_S_, .Lfunc_end0-_Z26__device_stub__gpu_poissonPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gpu_poissonPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $dx, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $voltage, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $eps, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type dx,@object # @dx
.local dx
.comm dx,8,8
.type voltage,@object # @voltage
.local voltage
.comm voltage,8,8
.type eps,@object # @eps
.local eps
.comm eps,8,8
.type _Z11gpu_poissonPdS_S_,@object # @_Z11gpu_poissonPdS_S_
.section .rodata,"a",@progbits
.globl _Z11gpu_poissonPdS_S_
.p2align 3, 0x0
_Z11gpu_poissonPdS_S_:
.quad _Z26__device_stub__gpu_poissonPdS_S_
.size _Z11gpu_poissonPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11gpu_poissonPdS_S_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "dx"
.size .L__unnamed_2, 3
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "voltage"
.size .L__unnamed_3, 8
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "eps"
.size .L__unnamed_4, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__gpu_poissonPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dx
.addrsig_sym voltage
.addrsig_sym eps
.addrsig_sym _Z11gpu_poissonPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ int d(void) { return 8; }
__global__ void g(void) {} | code for sm_80
Function : _Z1gv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ int d(void) { return 8; }
__global__ void g(void) {} | .file "tmpxft_000628f0_00000000-6_g.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1dv
.type _Z1dv, @function
_Z1dv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z1dv, .-_Z1dv
.globl _Z19__device_stub__Z1gvv
.type _Z19__device_stub__Z1gvv, @function
_Z19__device_stub__Z1gvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z1gv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z19__device_stub__Z1gvv, .-_Z19__device_stub__Z1gvv
.globl _Z1gv
.type _Z1gv, @function
_Z1gv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19__device_stub__Z1gvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z1gv, .-_Z1gv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1gv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1gv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ int d(void) { return 8; }
__global__ void g(void) {} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int d(void) { return 8; }
__global__ void g(void) {} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int d(void) { return 8; }
__global__ void g(void) {} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1gv
.globl _Z1gv
.p2align 8
.type _Z1gv,@function
_Z1gv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1gv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1gv, .Lfunc_end0-_Z1gv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1gv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z1gv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int d(void) { return 8; }
__global__ void g(void) {} | .text
.file "g.hip"
.globl _Z16__device_stub__gv # -- Begin function _Z16__device_stub__gv
.p2align 4, 0x90
.type _Z16__device_stub__gv,@function
_Z16__device_stub__gv: # @_Z16__device_stub__gv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1gv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z16__device_stub__gv, .Lfunc_end0-_Z16__device_stub__gv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1gv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1gv,@object # @_Z1gv
.section .rodata,"a",@progbits
.globl _Z1gv
.p2align 3, 0x0
_Z1gv:
.quad _Z16__device_stub__gv
.size _Z1gv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1gv"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__gv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1gv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z1gv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1gv
.globl _Z1gv
.p2align 8
.type _Z1gv,@function
_Z1gv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1gv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1gv, .Lfunc_end0-_Z1gv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1gv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z1gv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000628f0_00000000-6_g.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1dv
.type _Z1dv, @function
_Z1dv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z1dv, .-_Z1dv
.globl _Z19__device_stub__Z1gvv
.type _Z19__device_stub__Z1gvv, @function
_Z19__device_stub__Z1gvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z1gv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z19__device_stub__Z1gvv, .-_Z19__device_stub__Z1gvv
.globl _Z1gv
.type _Z1gv, @function
_Z1gv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z19__device_stub__Z1gvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z1gv, .-_Z1gv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1gv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1gv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "g.hip"
.globl _Z16__device_stub__gv # -- Begin function _Z16__device_stub__gv
.p2align 4, 0x90
.type _Z16__device_stub__gv,@function
_Z16__device_stub__gv: # @_Z16__device_stub__gv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z1gv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z16__device_stub__gv, .Lfunc_end0-_Z16__device_stub__gv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1gv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1gv,@object # @_Z1gv
.section .rodata,"a",@progbits
.globl _Z1gv
.p2align 3, 0x0
_Z1gv:
.quad _Z16__device_stub__gv
.size _Z1gv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1gv"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__gv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1gv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void zupdate2_dummy(float *z1, float *z2, float *f, float tau, int nx, int ny)
{
int px = blockIdx.x * blockDim.x + threadIdx.x;
int py = blockIdx.y * blockDim.y + threadIdx.y;
int idx = px + py*nx;
float a, b, t;
if (px<nx && py<ny)
{
// compute the gradient
a = 0;
b = 0;
float fc = f[idx];
// float fr=f[idx+1];
// float fu=f[idx+nx];
// if (!(px==(nx-1))) a = fr - fc;
// if (!(py==(ny-1))) b = fu - fc;
a = fc;
b = fc;
// update z
t = 1 / (1 + tau*sqrtf(a*a + b*b));
z1[idx] = (z1[idx] + tau*a)*t;
z2[idx] = (z2[idx] + tau*b)*t;
}
} | code for sm_80
Function : _Z14zupdate2_dummyPfS_S_fii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x17c], P0 ; /* 0x00005f0002007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003027a24 */
/* 0x000fe200078e0202 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R2, R5, c[0x0][0x170] ; /* 0x00005c0002047625 */
/* 0x000fca00078e0205 */
/*00e0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ BSSY B0, 0x1e0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0100*/ FMUL R3, R0, R0 ; /* 0x0000000000037220 */
/* 0x004fc80000400000 */
/*0110*/ FFMA R3, R0, R0, R3 ; /* 0x0000000000037223 */
/* 0x000fc80000000003 */
/*0120*/ MUFU.RSQ R6, R3 ; /* 0x0000000300067308 */
/* 0x0000620000001400 */
/*0130*/ IADD3 R7, R3, -0xd000000, RZ ; /* 0xf300000003077810 */
/* 0x000fc80007ffe0ff */
/*0140*/ ISETP.GT.U32.AND P0, PT, R7, 0x727fffff, PT ; /* 0x727fffff0700780c */
/* 0x000fda0003f04070 */
/*0150*/ @!P0 BRA 0x190 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R9, 0x180 ; /* 0x0000018000097802 */
/* 0x003fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x6f0 ; /* 0x0000057000007944 */
/* 0x000fea0003c00000 */
/*0180*/ BRA 0x1d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0190*/ FMUL.FTZ R4, R3, R6 ; /* 0x0000000603047220 */
/* 0x003fe40000410000 */
/*01a0*/ FMUL.FTZ R6, R6, 0.5 ; /* 0x3f00000006067820 */
/* 0x000fe40000410000 */
/*01b0*/ FFMA R3, -R4, R4, R3 ; /* 0x0000000404037223 */
/* 0x000fc80000000103 */
/*01c0*/ FFMA R3, R3, R6, R4 ; /* 0x0000000603037223 */
/* 0x000fe40000000004 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*01f0*/ BSSY B0, 0x2d0 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0200*/ FFMA R5, R3, R4, 1 ; /* 0x3f80000003057423 */
/* 0x000fca0000000004 */
/*0210*/ IADD3 R3, R5, 0x1800000, RZ ; /* 0x0180000005037810 */
/* 0x000fc80007ffe0ff */
/*0220*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000003037812 */
/* 0x000fc800078ec0ff */
/*0230*/ ISETP.GT.U32.AND P0, PT, R3, 0x1ffffff, PT ; /* 0x01ffffff0300780c */
/* 0x000fda0003f04070 */
/*0240*/ @P0 BRA 0x280 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0250*/ MOV R4, 0x270 ; /* 0x0000027000047802 */
/* 0x000fe40000000f00 */
/*0260*/ CALL.REL.NOINC 0x390 ; /* 0x0000012000007944 */
/* 0x000fea0003c00000 */
/*0270*/ BRA 0x2c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0280*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e240000001000 */
/*0290*/ FFMA R3, R5, R6, -1 ; /* 0xbf80000005037423 */
/* 0x001fc80000000006 */
/*02a0*/ FADD.FTZ R3, -R3, -RZ ; /* 0x800000ff03037221 */
/* 0x000fc80000010100 */
/*02b0*/ FFMA R6, R6, R3, R6 ; /* 0x0000000306067223 */
/* 0x000fe40000000006 */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fd400000001ff */
/*02e0*/ IMAD.WIDE R4, R2, R9, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fca00078e0209 */
/*02f0*/ LDG.E R3, [R4.64] ; /* 0x0000000404037981 */
/* 0x001ea4000c1e1900 */
/*0300*/ FFMA R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a23 */
/* 0x004fc80000000003 */
/*0310*/ FMUL R7, R3, R6 ; /* 0x0000000603077220 */
/* 0x000fe40000400000 */
/*0320*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc600078e0209 */
/*0330*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe8000c101904 */
/*0340*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea4000c1e1900 */
/*0350*/ FFMA R9, R0, c[0x0][0x178], R9 ; /* 0x00005e0000097a23 */
/* 0x004fc80000000009 */
/*0360*/ FMUL R9, R9, R6 ; /* 0x0000000609097220 */
/* 0x000fca0000400000 */
/*0370*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ IMAD.SHL.U32 R3, R5, 0x2, RZ ; /* 0x0000000205037824 */
/* 0x000fe200078e00ff */
/*03a0*/ BSSY B1, 0x6c0 ; /* 0x0000031000017945 */
/* 0x000fe80003800000 */
/*03b0*/ SHF.R.U32.HI R10, RZ, 0x18, R3 ; /* 0x00000018ff0a7819 */
/* 0x000fe40000011603 */
/*03c0*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x000fe40000000f00 */
/*03d0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05070 */
/*03e0*/ @P0 BRA 0x490 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*03f0*/ IMAD.SHL.U32 R5, R3, 0x2, RZ ; /* 0x0000000203057824 */
/* 0x000fca00078e00ff */
/*0400*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0410*/ @P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003060823 */
/* 0x000fe200000000ff */
/*0420*/ @!P0 MUFU.RCP R5, R3 ; /* 0x0000000300058308 */
/* 0x000ff00000001000 */
/*0430*/ @P0 MUFU.RCP R7, R6 ; /* 0x0000000600070308 */
/* 0x000e240000001000 */
/*0440*/ @P0 FFMA R8, R6, R7, -1 ; /* 0xbf80000006080423 */
/* 0x001fc80000000007 */
/*0450*/ @P0 FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08080221 */
/* 0x000fc80000010100 */
/*0460*/ @P0 FFMA R8, R7, R8, R7 ; /* 0x0000000807080223 */
/* 0x000fc80000000007 */
/*0470*/ @P0 FFMA R5, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008050823 */
/* 0x000fe200000000ff */
/*0480*/ BRA 0x6b0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0490*/ IADD3 R12, R10, -0xfd, RZ ; /* 0xffffff030a0c7810 */
/* 0x000fc80007ffe0ff */
/*04a0*/ ISETP.GT.U32.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f04070 */
/*04b0*/ @P0 BRA 0x6a0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*04c0*/ LOP3.LUT R5, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03057812 */
/* 0x000fe200078ec0ff */
/*04d0*/ HFMA2.MMA R9, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff097435 */
/* 0x000fc600000001ff */
/*04e0*/ LOP3.LUT R5, R5, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000005057812 */
/* 0x000fc800078efcff */
/*04f0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e260000001000 */
/*0500*/ SHF.L.U32 R9, R9, R12, RZ ; /* 0x0000000c09097219 */
/* 0x000fe200000006ff */
/*0510*/ FFMA R7, R5, R6, -1 ; /* 0xbf80000005077423 */
/* 0x001fc80000000006 */
/*0520*/ FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07077221 */
/* 0x000fc80000010100 */
/*0530*/ FFMA.RM R8, R6.reuse, R7.reuse, R6.reuse ; /* 0x0000000706087223 */
/* 0x1c0fe40000004006 */
/*0540*/ FFMA.RP R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc60000008006 */
/*0550*/ LOP3.LUT R6, R8.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08067812 */
/* 0x040fe400078ec0ff */
/*0560*/ FSETP.NEU.FTZ.AND P0, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x000fe40003f1d000 */
/*0570*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0580*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */
/* 0x000fe40004000000 */
/*0590*/ LOP3.LUT R9, R9, R6, RZ, 0xc0, !PT ; /* 0x0000000609097212 */
/* 0x000fc600078ec0ff */
/*05a0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a07 */
/*05b0*/ SHF.R.U32.HI R9, RZ, R12, R9 ; /* 0x0000000cff097219 */
/* 0x000fc80000011609 */
/*05c0*/ LOP3.LUT P1, RZ, R7, R12, R6, 0xf8, !PT ; /* 0x0000000c07ff7212 */
/* 0x000fe4000782f806 */
/*05d0*/ LOP3.LUT P0, RZ, R9.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109ff7812 */
/* 0x040fe4000780c0ff */
/*05e0*/ LOP3.LUT P2, RZ, R9, 0x2, RZ, 0xc0, !PT ; /* 0x0000000209ff7812 */
/* 0x000fc8000784c0ff */
/*05f0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0600*/ LOP3.LUT P1, RZ, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03ff7812 */
/* 0x000fe4000782c0ff */
/*0610*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0620*/ IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05057210 */
/* 0x000fc80007ffe1ff */
/*0630*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f06270 */
/*0640*/ IADD3 R5, R10, -0xfc, RZ ; /* 0xffffff040a057810 */
/* 0x000fc80007ffe0ff */
/*0650*/ SHF.R.U32.HI R6, RZ, R5, R6 ; /* 0x00000005ff067219 */
/* 0x000fce0000011606 */
/*0660*/ @!P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106068810 */
/* 0x000fca0007ffe0ff */
/*0670*/ @!P1 IMAD.SHL.U32 R6, R6, 0x2, RZ ; /* 0x0000000206069824 */
/* 0x000fca00078e00ff */
/*0680*/ LOP3.LUT R5, R6, 0x80000000, R3, 0xf8, !PT ; /* 0x8000000006057812 */
/* 0x000fe200078ef803 */
/*0690*/ BRA 0x6b0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*06a0*/ MUFU.RCP R5, R3 ; /* 0x0000000300057308 */
/* 0x0000640000001000 */
/*06b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06c0*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x002fe20000000f00 */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*06e0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff91004007950 */
/* 0x000fea0003c3ffff */
/*06f0*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0700*/ @!P0 MOV R4, R3 ; /* 0x0000000300048202 */
/* 0x000fe20000000f00 */
/*0710*/ @!P0 BRA 0x820 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0720*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fda0003f1e000 */
/*0730*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff048424 */
/* 0x000fe200078e00ff */
/*0740*/ @!P0 BRA 0x820 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0750*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*0760*/ @P0 FADD.FTZ R4, R3, 1 ; /* 0x3f80000003040421 */
/* 0x000fe20000010000 */
/*0770*/ @P0 BRA 0x820 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0780*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1d200 */
/*0790*/ @P0 FFMA R5, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003050823 */
/* 0x000fc800000000ff */
/*07a0*/ @P0 MUFU.RSQ R4, R5 ; /* 0x0000000500040308 */
/* 0x000e240000001400 */
/*07b0*/ @P0 FMUL.FTZ R6, R5, R4 ; /* 0x0000000405060220 */
/* 0x001fe40000410000 */
/*07c0*/ @P0 FMUL.FTZ R8, R4, 0.5 ; /* 0x3f00000004080820 */
/* 0x000fe20000410000 */
/*07d0*/ @!P0 MOV R4, R3 ; /* 0x0000000300048202 */
/* 0x000fe20000000f00 */
/*07e0*/ @P0 FADD.FTZ R7, -R6, -RZ ; /* 0x800000ff06070221 */
/* 0x000fc80000010100 */
/*07f0*/ @P0 FFMA R7, R6, R7, R5 ; /* 0x0000000706070223 */
/* 0x000fc80000000005 */
/*0800*/ @P0 FFMA R7, R7, R8, R6 ; /* 0x0000000807070223 */
/* 0x000fc80000000006 */
/*0810*/ @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007040820 */
/* 0x000fc80000410000 */
/*0820*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0004 */
/*0830*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*0840*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0850*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff7a004007950 */
/* 0x000fea0003c3ffff */
/*0860*/ BRA 0x860; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void zupdate2_dummy(float *z1, float *z2, float *f, float tau, int nx, int ny)
{
int px = blockIdx.x * blockDim.x + threadIdx.x;
int py = blockIdx.y * blockDim.y + threadIdx.y;
int idx = px + py*nx;
float a, b, t;
if (px<nx && py<ny)
{
// compute the gradient
a = 0;
b = 0;
float fc = f[idx];
// float fr=f[idx+1];
// float fu=f[idx+nx];
// if (!(px==(nx-1))) a = fr - fc;
// if (!(py==(ny-1))) b = fu - fc;
a = fc;
b = fc;
// update z
t = 1 / (1 + tau*sqrtf(a*a + b*b));
z1[idx] = (z1[idx] + tau*a)*t;
z2[idx] = (z2[idx] + tau*b)*t;
}
} | .file "tmpxft_001327ba_00000000-6_zupdate2_dummy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14zupdate2_dummyPfS_S_fiiPfS_S_fii
.type _Z41__device_stub__Z14zupdate2_dummyPfS_S_fiiPfS_S_fii, @function
_Z41__device_stub__Z14zupdate2_dummyPfS_S_fiiPfS_S_fii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14zupdate2_dummyPfS_S_fii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14zupdate2_dummyPfS_S_fiiPfS_S_fii, .-_Z41__device_stub__Z14zupdate2_dummyPfS_S_fiiPfS_S_fii
.globl _Z14zupdate2_dummyPfS_S_fii
.type _Z14zupdate2_dummyPfS_S_fii, @function
_Z14zupdate2_dummyPfS_S_fii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14zupdate2_dummyPfS_S_fiiPfS_S_fii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14zupdate2_dummyPfS_S_fii, .-_Z14zupdate2_dummyPfS_S_fii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14zupdate2_dummyPfS_S_fii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14zupdate2_dummyPfS_S_fii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void zupdate2_dummy(float *z1, float *z2, float *f, float tau, int nx, int ny)
{
int px = blockIdx.x * blockDim.x + threadIdx.x;
int py = blockIdx.y * blockDim.y + threadIdx.y;
int idx = px + py*nx;
float a, b, t;
if (px<nx && py<ny)
{
// compute the gradient
a = 0;
b = 0;
float fc = f[idx];
// float fr=f[idx+1];
// float fu=f[idx+nx];
// if (!(px==(nx-1))) a = fr - fc;
// if (!(py==(ny-1))) b = fu - fc;
a = fc;
b = fc;
// update z
t = 1 / (1 + tau*sqrtf(a*a + b*b));
z1[idx] = (z1[idx] + tau*a)*t;
z2[idx] = (z2[idx] + tau*b)*t;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void zupdate2_dummy(float *z1, float *z2, float *f, float tau, int nx, int ny)
{
int px = blockIdx.x * blockDim.x + threadIdx.x;
int py = blockIdx.y * blockDim.y + threadIdx.y;
int idx = px + py*nx;
float a, b, t;
if (px<nx && py<ny)
{
// compute the gradient
a = 0;
b = 0;
float fc = f[idx];
// float fr=f[idx+1];
// float fu=f[idx+nx];
// if (!(px==(nx-1))) a = fr - fc;
// if (!(py==(ny-1))) b = fu - fc;
a = fc;
b = fc;
// update z
t = 1 / (1 + tau*sqrtf(a*a + b*b));
z1[idx] = (z1[idx] + tau*a)*t;
z2[idx] = (z2[idx] + tau*b)*t;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void zupdate2_dummy(float *z1, float *z2, float *f, float tau, int nx, int ny)
{
int px = blockIdx.x * blockDim.x + threadIdx.x;
int py = blockIdx.y * blockDim.y + threadIdx.y;
int idx = px + py*nx;
float a, b, t;
if (px<nx && py<ny)
{
// compute the gradient
a = 0;
b = 0;
float fc = f[idx];
// float fr=f[idx+1];
// float fu=f[idx+nx];
// if (!(px==(nx-1))) a = fr - fc;
// if (!(py==(ny-1))) b = fu - fc;
a = fc;
b = fc;
// update z
t = 1 / (1 + tau*sqrtf(a*a + b*b));
z1[idx] = (z1[idx] + tau*a)*t;
z2[idx] = (z2[idx] + tau*b)*t;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14zupdate2_dummyPfS_S_fii
.globl _Z14zupdate2_dummyPfS_S_fii
.p2align 8
.type _Z14zupdate2_dummyPfS_S_fii,@function
_Z14zupdate2_dummyPfS_S_fii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v6, v4, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v6, v6, v6 :: v_dual_fmac_f32 v5, s1, v4
v_mul_f32_e32 v7, 0x4f800000, v6
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_sqrt_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, -1, v7
v_add_nc_u32_e32 v9, 1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, -v8, v7, v6
v_fma_f32 v11, -v9, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_f32_e64 s2, 0, v10
v_cmp_lt_f32_e64 s0, 0, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, v7, v8, s2
v_cndmask_b32_e64 v7, v7, v9, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, 0x37800000, v7
v_cndmask_b32_e32 v7, v7, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v6, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
v_fma_f32 v6, v6, s1, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v7, null, v6, v6, 1.0
v_div_scale_f32 v10, vcc_lo, 1.0, v6, 1.0
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v7, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v8
v_mul_f32_e32 v9, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v7, v9, v10
v_fmac_f32_e32 v9, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v7, v9, v10
v_div_fmas_f32 v7, v7, v8, v9
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v6, v7, v6, 1.0
v_mul_f32_e32 v5, v5, v6
global_store_b32 v[2:3], v5, off
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, s1, v4
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v6
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14zupdate2_dummyPfS_S_fii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14zupdate2_dummyPfS_S_fii, .Lfunc_end0-_Z14zupdate2_dummyPfS_S_fii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14zupdate2_dummyPfS_S_fii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14zupdate2_dummyPfS_S_fii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void zupdate2_dummy(float *z1, float *z2, float *f, float tau, int nx, int ny)
{
int px = blockIdx.x * blockDim.x + threadIdx.x;
int py = blockIdx.y * blockDim.y + threadIdx.y;
int idx = px + py*nx;
float a, b, t;
if (px<nx && py<ny)
{
// compute the gradient
a = 0;
b = 0;
float fc = f[idx];
// float fr=f[idx+1];
// float fu=f[idx+nx];
// if (!(px==(nx-1))) a = fr - fc;
// if (!(py==(ny-1))) b = fu - fc;
a = fc;
b = fc;
// update z
t = 1 / (1 + tau*sqrtf(a*a + b*b));
z1[idx] = (z1[idx] + tau*a)*t;
z2[idx] = (z2[idx] + tau*b)*t;
}
} | .text
.file "zupdate2_dummy.hip"
.globl _Z29__device_stub__zupdate2_dummyPfS_S_fii # -- Begin function _Z29__device_stub__zupdate2_dummyPfS_S_fii
.p2align 4, 0x90
.type _Z29__device_stub__zupdate2_dummyPfS_S_fii,@function
_Z29__device_stub__zupdate2_dummyPfS_S_fii: # @_Z29__device_stub__zupdate2_dummyPfS_S_fii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14zupdate2_dummyPfS_S_fii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__zupdate2_dummyPfS_S_fii, .Lfunc_end0-_Z29__device_stub__zupdate2_dummyPfS_S_fii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14zupdate2_dummyPfS_S_fii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14zupdate2_dummyPfS_S_fii,@object # @_Z14zupdate2_dummyPfS_S_fii
.section .rodata,"a",@progbits
.globl _Z14zupdate2_dummyPfS_S_fii
.p2align 3, 0x0
_Z14zupdate2_dummyPfS_S_fii:
.quad _Z29__device_stub__zupdate2_dummyPfS_S_fii
.size _Z14zupdate2_dummyPfS_S_fii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14zupdate2_dummyPfS_S_fii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__zupdate2_dummyPfS_S_fii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14zupdate2_dummyPfS_S_fii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14zupdate2_dummyPfS_S_fii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x17c], P0 ; /* 0x00005f0002007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003027a24 */
/* 0x000fe200078e0202 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R2, R5, c[0x0][0x170] ; /* 0x00005c0002047625 */
/* 0x000fca00078e0205 */
/*00e0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ BSSY B0, 0x1e0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0100*/ FMUL R3, R0, R0 ; /* 0x0000000000037220 */
/* 0x004fc80000400000 */
/*0110*/ FFMA R3, R0, R0, R3 ; /* 0x0000000000037223 */
/* 0x000fc80000000003 */
/*0120*/ MUFU.RSQ R6, R3 ; /* 0x0000000300067308 */
/* 0x0000620000001400 */
/*0130*/ IADD3 R7, R3, -0xd000000, RZ ; /* 0xf300000003077810 */
/* 0x000fc80007ffe0ff */
/*0140*/ ISETP.GT.U32.AND P0, PT, R7, 0x727fffff, PT ; /* 0x727fffff0700780c */
/* 0x000fda0003f04070 */
/*0150*/ @!P0 BRA 0x190 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R9, 0x180 ; /* 0x0000018000097802 */
/* 0x003fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x6f0 ; /* 0x0000057000007944 */
/* 0x000fea0003c00000 */
/*0180*/ BRA 0x1d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0190*/ FMUL.FTZ R4, R3, R6 ; /* 0x0000000603047220 */
/* 0x003fe40000410000 */
/*01a0*/ FMUL.FTZ R6, R6, 0.5 ; /* 0x3f00000006067820 */
/* 0x000fe40000410000 */
/*01b0*/ FFMA R3, -R4, R4, R3 ; /* 0x0000000404037223 */
/* 0x000fc80000000103 */
/*01c0*/ FFMA R3, R3, R6, R4 ; /* 0x0000000603037223 */
/* 0x000fe40000000004 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*01f0*/ BSSY B0, 0x2d0 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0200*/ FFMA R5, R3, R4, 1 ; /* 0x3f80000003057423 */
/* 0x000fca0000000004 */
/*0210*/ IADD3 R3, R5, 0x1800000, RZ ; /* 0x0180000005037810 */
/* 0x000fc80007ffe0ff */
/*0220*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000003037812 */
/* 0x000fc800078ec0ff */
/*0230*/ ISETP.GT.U32.AND P0, PT, R3, 0x1ffffff, PT ; /* 0x01ffffff0300780c */
/* 0x000fda0003f04070 */
/*0240*/ @P0 BRA 0x280 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0250*/ MOV R4, 0x270 ; /* 0x0000027000047802 */
/* 0x000fe40000000f00 */
/*0260*/ CALL.REL.NOINC 0x390 ; /* 0x0000012000007944 */
/* 0x000fea0003c00000 */
/*0270*/ BRA 0x2c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0280*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e240000001000 */
/*0290*/ FFMA R3, R5, R6, -1 ; /* 0xbf80000005037423 */
/* 0x001fc80000000006 */
/*02a0*/ FADD.FTZ R3, -R3, -RZ ; /* 0x800000ff03037221 */
/* 0x000fc80000010100 */
/*02b0*/ FFMA R6, R6, R3, R6 ; /* 0x0000000306067223 */
/* 0x000fe40000000006 */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fd400000001ff */
/*02e0*/ IMAD.WIDE R4, R2, R9, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fca00078e0209 */
/*02f0*/ LDG.E R3, [R4.64] ; /* 0x0000000404037981 */
/* 0x001ea4000c1e1900 */
/*0300*/ FFMA R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a23 */
/* 0x004fc80000000003 */
/*0310*/ FMUL R7, R3, R6 ; /* 0x0000000603077220 */
/* 0x000fe40000400000 */
/*0320*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc600078e0209 */
/*0330*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe8000c101904 */
/*0340*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea4000c1e1900 */
/*0350*/ FFMA R9, R0, c[0x0][0x178], R9 ; /* 0x00005e0000097a23 */
/* 0x004fc80000000009 */
/*0360*/ FMUL R9, R9, R6 ; /* 0x0000000609097220 */
/* 0x000fca0000400000 */
/*0370*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ IMAD.SHL.U32 R3, R5, 0x2, RZ ; /* 0x0000000205037824 */
/* 0x000fe200078e00ff */
/*03a0*/ BSSY B1, 0x6c0 ; /* 0x0000031000017945 */
/* 0x000fe80003800000 */
/*03b0*/ SHF.R.U32.HI R10, RZ, 0x18, R3 ; /* 0x00000018ff0a7819 */
/* 0x000fe40000011603 */
/*03c0*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x000fe40000000f00 */
/*03d0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05070 */
/*03e0*/ @P0 BRA 0x490 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*03f0*/ IMAD.SHL.U32 R5, R3, 0x2, RZ ; /* 0x0000000203057824 */
/* 0x000fca00078e00ff */
/*0400*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0410*/ @P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003060823 */
/* 0x000fe200000000ff */
/*0420*/ @!P0 MUFU.RCP R5, R3 ; /* 0x0000000300058308 */
/* 0x000ff00000001000 */
/*0430*/ @P0 MUFU.RCP R7, R6 ; /* 0x0000000600070308 */
/* 0x000e240000001000 */
/*0440*/ @P0 FFMA R8, R6, R7, -1 ; /* 0xbf80000006080423 */
/* 0x001fc80000000007 */
/*0450*/ @P0 FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08080221 */
/* 0x000fc80000010100 */
/*0460*/ @P0 FFMA R8, R7, R8, R7 ; /* 0x0000000807080223 */
/* 0x000fc80000000007 */
/*0470*/ @P0 FFMA R5, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008050823 */
/* 0x000fe200000000ff */
/*0480*/ BRA 0x6b0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0490*/ IADD3 R12, R10, -0xfd, RZ ; /* 0xffffff030a0c7810 */
/* 0x000fc80007ffe0ff */
/*04a0*/ ISETP.GT.U32.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f04070 */
/*04b0*/ @P0 BRA 0x6a0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*04c0*/ LOP3.LUT R5, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03057812 */
/* 0x000fe200078ec0ff */
/*04d0*/ HFMA2.MMA R9, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff097435 */
/* 0x000fc600000001ff */
/*04e0*/ LOP3.LUT R5, R5, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000005057812 */
/* 0x000fc800078efcff */
/*04f0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e260000001000 */
/*0500*/ SHF.L.U32 R9, R9, R12, RZ ; /* 0x0000000c09097219 */
/* 0x000fe200000006ff */
/*0510*/ FFMA R7, R5, R6, -1 ; /* 0xbf80000005077423 */
/* 0x001fc80000000006 */
/*0520*/ FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07077221 */
/* 0x000fc80000010100 */
/*0530*/ FFMA.RM R8, R6.reuse, R7.reuse, R6.reuse ; /* 0x0000000706087223 */
/* 0x1c0fe40000004006 */
/*0540*/ FFMA.RP R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc60000008006 */
/*0550*/ LOP3.LUT R6, R8.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08067812 */
/* 0x040fe400078ec0ff */
/*0560*/ FSETP.NEU.FTZ.AND P0, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x000fe40003f1d000 */
/*0570*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0580*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */
/* 0x000fe40004000000 */
/*0590*/ LOP3.LUT R9, R9, R6, RZ, 0xc0, !PT ; /* 0x0000000609097212 */
/* 0x000fc600078ec0ff */
/*05a0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a07 */
/*05b0*/ SHF.R.U32.HI R9, RZ, R12, R9 ; /* 0x0000000cff097219 */
/* 0x000fc80000011609 */
/*05c0*/ LOP3.LUT P1, RZ, R7, R12, R6, 0xf8, !PT ; /* 0x0000000c07ff7212 */
/* 0x000fe4000782f806 */
/*05d0*/ LOP3.LUT P0, RZ, R9.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109ff7812 */
/* 0x040fe4000780c0ff */
/*05e0*/ LOP3.LUT P2, RZ, R9, 0x2, RZ, 0xc0, !PT ; /* 0x0000000209ff7812 */
/* 0x000fc8000784c0ff */
/*05f0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0600*/ LOP3.LUT P1, RZ, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03ff7812 */
/* 0x000fe4000782c0ff */
/*0610*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0620*/ IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05057210 */
/* 0x000fc80007ffe1ff */
/*0630*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f06270 */
/*0640*/ IADD3 R5, R10, -0xfc, RZ ; /* 0xffffff040a057810 */
/* 0x000fc80007ffe0ff */
/*0650*/ SHF.R.U32.HI R6, RZ, R5, R6 ; /* 0x00000005ff067219 */
/* 0x000fce0000011606 */
/*0660*/ @!P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106068810 */
/* 0x000fca0007ffe0ff */
/*0670*/ @!P1 IMAD.SHL.U32 R6, R6, 0x2, RZ ; /* 0x0000000206069824 */
/* 0x000fca00078e00ff */
/*0680*/ LOP3.LUT R5, R6, 0x80000000, R3, 0xf8, !PT ; /* 0x8000000006057812 */
/* 0x000fe200078ef803 */
/*0690*/ BRA 0x6b0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*06a0*/ MUFU.RCP R5, R3 ; /* 0x0000000300057308 */
/* 0x0000640000001000 */
/*06b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06c0*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x002fe20000000f00 */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*06e0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff91004007950 */
/* 0x000fea0003c3ffff */
/*06f0*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0700*/ @!P0 MOV R4, R3 ; /* 0x0000000300048202 */
/* 0x000fe20000000f00 */
/*0710*/ @!P0 BRA 0x820 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0720*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fda0003f1e000 */
/*0730*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff048424 */
/* 0x000fe200078e00ff */
/*0740*/ @!P0 BRA 0x820 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0750*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*0760*/ @P0 FADD.FTZ R4, R3, 1 ; /* 0x3f80000003040421 */
/* 0x000fe20000010000 */
/*0770*/ @P0 BRA 0x820 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0780*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1d200 */
/*0790*/ @P0 FFMA R5, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003050823 */
/* 0x000fc800000000ff */
/*07a0*/ @P0 MUFU.RSQ R4, R5 ; /* 0x0000000500040308 */
/* 0x000e240000001400 */
/*07b0*/ @P0 FMUL.FTZ R6, R5, R4 ; /* 0x0000000405060220 */
/* 0x001fe40000410000 */
/*07c0*/ @P0 FMUL.FTZ R8, R4, 0.5 ; /* 0x3f00000004080820 */
/* 0x000fe20000410000 */
/*07d0*/ @!P0 MOV R4, R3 ; /* 0x0000000300048202 */
/* 0x000fe20000000f00 */
/*07e0*/ @P0 FADD.FTZ R7, -R6, -RZ ; /* 0x800000ff06070221 */
/* 0x000fc80000010100 */
/*07f0*/ @P0 FFMA R7, R6, R7, R5 ; /* 0x0000000706070223 */
/* 0x000fc80000000005 */
/*0800*/ @P0 FFMA R7, R7, R8, R6 ; /* 0x0000000807070223 */
/* 0x000fc80000000006 */
/*0810*/ @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007040820 */
/* 0x000fc80000410000 */
/*0820*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0004 */
/*0830*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*0840*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0850*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff7a004007950 */
/* 0x000fea0003c3ffff */
/*0860*/ BRA 0x860; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14zupdate2_dummyPfS_S_fii
.globl _Z14zupdate2_dummyPfS_S_fii
.p2align 8
.type _Z14zupdate2_dummyPfS_S_fii,@function
_Z14zupdate2_dummyPfS_S_fii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v6, v4, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v6, v6, v6 :: v_dual_fmac_f32 v5, s1, v4
v_mul_f32_e32 v7, 0x4f800000, v6
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_sqrt_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, -1, v7
v_add_nc_u32_e32 v9, 1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, -v8, v7, v6
v_fma_f32 v11, -v9, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_f32_e64 s2, 0, v10
v_cmp_lt_f32_e64 s0, 0, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, v7, v8, s2
v_cndmask_b32_e64 v7, v7, v9, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, 0x37800000, v7
v_cndmask_b32_e32 v7, v7, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v6, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
v_fma_f32 v6, v6, s1, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v7, null, v6, v6, 1.0
v_div_scale_f32 v10, vcc_lo, 1.0, v6, 1.0
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v7, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v8
v_mul_f32_e32 v9, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v7, v9, v10
v_fmac_f32_e32 v9, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v7, v9, v10
v_div_fmas_f32 v7, v7, v8, v9
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v6, v7, v6, 1.0
v_mul_f32_e32 v5, v5, v6
global_store_b32 v[2:3], v5, off
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, s1, v4
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v6
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14zupdate2_dummyPfS_S_fii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14zupdate2_dummyPfS_S_fii, .Lfunc_end0-_Z14zupdate2_dummyPfS_S_fii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14zupdate2_dummyPfS_S_fii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14zupdate2_dummyPfS_S_fii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001327ba_00000000-6_zupdate2_dummy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14zupdate2_dummyPfS_S_fiiPfS_S_fii
.type _Z41__device_stub__Z14zupdate2_dummyPfS_S_fiiPfS_S_fii, @function
_Z41__device_stub__Z14zupdate2_dummyPfS_S_fiiPfS_S_fii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14zupdate2_dummyPfS_S_fii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14zupdate2_dummyPfS_S_fiiPfS_S_fii, .-_Z41__device_stub__Z14zupdate2_dummyPfS_S_fiiPfS_S_fii
.globl _Z14zupdate2_dummyPfS_S_fii
.type _Z14zupdate2_dummyPfS_S_fii, @function
_Z14zupdate2_dummyPfS_S_fii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14zupdate2_dummyPfS_S_fiiPfS_S_fii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14zupdate2_dummyPfS_S_fii, .-_Z14zupdate2_dummyPfS_S_fii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14zupdate2_dummyPfS_S_fii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14zupdate2_dummyPfS_S_fii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "zupdate2_dummy.hip"
.globl _Z29__device_stub__zupdate2_dummyPfS_S_fii # -- Begin function _Z29__device_stub__zupdate2_dummyPfS_S_fii
.p2align 4, 0x90
.type _Z29__device_stub__zupdate2_dummyPfS_S_fii,@function
_Z29__device_stub__zupdate2_dummyPfS_S_fii: # @_Z29__device_stub__zupdate2_dummyPfS_S_fii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14zupdate2_dummyPfS_S_fii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__zupdate2_dummyPfS_S_fii, .Lfunc_end0-_Z29__device_stub__zupdate2_dummyPfS_S_fii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14zupdate2_dummyPfS_S_fii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14zupdate2_dummyPfS_S_fii,@object # @_Z14zupdate2_dummyPfS_S_fii
.section .rodata,"a",@progbits
.globl _Z14zupdate2_dummyPfS_S_fii
.p2align 3, 0x0
_Z14zupdate2_dummyPfS_S_fii:
.quad _Z29__device_stub__zupdate2_dummyPfS_S_fii
.size _Z14zupdate2_dummyPfS_S_fii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14zupdate2_dummyPfS_S_fii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__zupdate2_dummyPfS_S_fii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14zupdate2_dummyPfS_S_fii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // a cuda app. we will convert this to opencl, and run it :-)
#include <iostream>
#include <memory>
#include <cassert>
using namespace std;
#include <cuda_runtime.h>
__global__ void setValue(char *data, int idx, char value) {
if(threadIdx.x == 0) {
data[idx] = value;
// data[idx] = 15;
}
}
int main(int argc, char *argv[]) {
int N = 1024;
char *gpuChars;
cudaMalloc((void**)(&gpuChars), N * sizeof(char));
setValue<<<dim3(32, 1, 1), dim3(32, 1, 1)>>>(gpuChars, 2, (char)89);
char hostChars[4];
cudaMemcpy(hostChars, gpuChars, 4 * sizeof(char), cudaMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 89);
setValue<<<dim3(32, 1, 1), dim3(32, 1, 1)>>>(gpuChars, 2, (char)23);
cudaMemcpy(hostChars, gpuChars, 4 * sizeof(char), cudaMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 23);
hostChars[2] = 44;
cudaMemcpy(gpuChars, hostChars, 4 * sizeof(char), cudaMemcpyHostToDevice);
hostChars[2] = 55;
cudaMemcpy(hostChars, gpuChars, 4 * sizeof(char), cudaMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 44);
cudaFree(gpuChars);
return 0;
} | code for sm_80
Function : _Z8setValuePcic
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ LDC.S8 R5, c[0x0][0x16c] ; /* 0x00005b00ff057b82 */
/* 0x000e220000000200 */
/*0050*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe40000000800 */
/*0060*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0070*/ UIADD3 UR4, UP0, UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fc8000ff1e03f */
/*0080*/ ULEA.HI.X.SX32 UR5, UR5, UR7, 0x1, UP0 ; /* 0x0000000705057291 */
/* 0x000fe400080f0e3f */
/*0090*/ MOV R2, UR4 ; /* 0x0000000400027c02 */
/* 0x000fc80008000f00 */
/*00a0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ PRMT R5, R5, 0x7710, RZ ; /* 0x0000771005057816 */
/* 0x001fca00000000ff */
/*00d0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // a cuda app. we will convert this to opencl, and run it :-)
#include <iostream>
#include <memory>
#include <cassert>
using namespace std;
#include <cuda_runtime.h>
__global__ void setValue(char *data, int idx, char value) {
if(threadIdx.x == 0) {
data[idx] = value;
// data[idx] = 15;
}
}
int main(int argc, char *argv[]) {
int N = 1024;
char *gpuChars;
cudaMalloc((void**)(&gpuChars), N * sizeof(char));
setValue<<<dim3(32, 1, 1), dim3(32, 1, 1)>>>(gpuChars, 2, (char)89);
char hostChars[4];
cudaMemcpy(hostChars, gpuChars, 4 * sizeof(char), cudaMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 89);
setValue<<<dim3(32, 1, 1), dim3(32, 1, 1)>>>(gpuChars, 2, (char)23);
cudaMemcpy(hostChars, gpuChars, 4 * sizeof(char), cudaMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 23);
hostChars[2] = 44;
cudaMemcpy(gpuChars, hostChars, 4 * sizeof(char), cudaMemcpyHostToDevice);
hostChars[2] = 55;
cudaMemcpy(hostChars, gpuChars, 4 * sizeof(char), cudaMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 44);
cudaFree(gpuChars);
return 0;
} | .file "tmpxft_00049197_00000000-6_test_char.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4316:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4316:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8setValuePcicPcic
.type _Z29__device_stub__Z8setValuePcicPcic, @function
_Z29__device_stub__Z8setValuePcicPcic:
.LFB4338:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movb %dl, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8setValuePcic(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4338:
.size _Z29__device_stub__Z8setValuePcicPcic, .-_Z29__device_stub__Z8setValuePcicPcic
.globl _Z8setValuePcic
.type _Z8setValuePcic, @function
_Z8setValuePcic:
.LFB4339:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movsbl %dl, %edx
call _Z29__device_stub__Z8setValuePcicPcic
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4339:
.size _Z8setValuePcic, .-_Z8setValuePcic
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hostChars[2] "
.text
.globl main
.type main, @function
main:
.LFB4313:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $32, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
leaq 36(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsbl 38(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $32, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
leaq 36(%rsp), %rbx
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %r12
movq %r12, %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsbl 38(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movb $44, 38(%rsp)
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movb $55, 38(%rsp)
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %r12, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsbl 38(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $89, %edx
movl $2, %esi
movq (%rsp), %rdi
call _Z29__device_stub__Z8setValuePcicPcic
jmp .L12
.L17:
movl $23, %edx
movl $2, %esi
movq (%rsp), %rdi
call _Z29__device_stub__Z8setValuePcicPcic
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4313:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8setValuePcic"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4341:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8setValuePcic(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4341:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // a cuda app. we will convert this to opencl, and run it :-)
#include <iostream>
#include <memory>
#include <cassert>
using namespace std;
#include <cuda_runtime.h>
__global__ void setValue(char *data, int idx, char value) {
if(threadIdx.x == 0) {
data[idx] = value;
// data[idx] = 15;
}
}
int main(int argc, char *argv[]) {
int N = 1024;
char *gpuChars;
cudaMalloc((void**)(&gpuChars), N * sizeof(char));
setValue<<<dim3(32, 1, 1), dim3(32, 1, 1)>>>(gpuChars, 2, (char)89);
char hostChars[4];
cudaMemcpy(hostChars, gpuChars, 4 * sizeof(char), cudaMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 89);
setValue<<<dim3(32, 1, 1), dim3(32, 1, 1)>>>(gpuChars, 2, (char)23);
cudaMemcpy(hostChars, gpuChars, 4 * sizeof(char), cudaMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 23);
hostChars[2] = 44;
cudaMemcpy(gpuChars, hostChars, 4 * sizeof(char), cudaMemcpyHostToDevice);
hostChars[2] = 55;
cudaMemcpy(hostChars, gpuChars, 4 * sizeof(char), cudaMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 44);
cudaFree(gpuChars);
return 0;
} | // a cuda app. we will convert this to opencl, and run it :-)
#include <iostream>
#include <memory>
#include <cassert>
using namespace std;
#include <hip/hip_runtime.h>
__global__ void setValue(char *data, int idx, char value) {
if(threadIdx.x == 0) {
data[idx] = value;
// data[idx] = 15;
}
}
int main(int argc, char *argv[]) {
int N = 1024;
char *gpuChars;
hipMalloc((void**)(&gpuChars), N * sizeof(char));
setValue<<<dim3(32, 1, 1), dim3(32, 1, 1)>>>(gpuChars, 2, (char)89);
char hostChars[4];
hipMemcpy(hostChars, gpuChars, 4 * sizeof(char), hipMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 89);
setValue<<<dim3(32, 1, 1), dim3(32, 1, 1)>>>(gpuChars, 2, (char)23);
hipMemcpy(hostChars, gpuChars, 4 * sizeof(char), hipMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 23);
hostChars[2] = 44;
hipMemcpy(gpuChars, hostChars, 4 * sizeof(char), hipMemcpyHostToDevice);
hostChars[2] = 55;
hipMemcpy(hostChars, gpuChars, 4 * sizeof(char), hipMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 44);
hipFree(gpuChars);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // a cuda app. we will convert this to opencl, and run it :-)
#include <iostream>
#include <memory>
#include <cassert>
using namespace std;
#include <hip/hip_runtime.h>
__global__ void setValue(char *data, int idx, char value) {
if(threadIdx.x == 0) {
data[idx] = value;
// data[idx] = 15;
}
}
int main(int argc, char *argv[]) {
int N = 1024;
char *gpuChars;
hipMalloc((void**)(&gpuChars), N * sizeof(char));
setValue<<<dim3(32, 1, 1), dim3(32, 1, 1)>>>(gpuChars, 2, (char)89);
char hostChars[4];
hipMemcpy(hostChars, gpuChars, 4 * sizeof(char), hipMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 89);
setValue<<<dim3(32, 1, 1), dim3(32, 1, 1)>>>(gpuChars, 2, (char)23);
hipMemcpy(hostChars, gpuChars, 4 * sizeof(char), hipMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 23);
hostChars[2] = 44;
hipMemcpy(gpuChars, hostChars, 4 * sizeof(char), hipMemcpyHostToDevice);
hostChars[2] = 55;
hipMemcpy(hostChars, gpuChars, 4 * sizeof(char), hipMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 44);
hipFree(gpuChars);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8setValuePcic
.globl _Z8setValuePcic
.p2align 8
.type _Z8setValuePcic,@function
_Z8setValuePcic:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
s_ashr_i32 s3, s2, 31
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b8 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8setValuePcic
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8setValuePcic, .Lfunc_end0-_Z8setValuePcic
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 1
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8setValuePcic
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z8setValuePcic.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // a cuda app. we will convert this to opencl, and run it :-)
#include <iostream>
#include <memory>
#include <cassert>
using namespace std;
#include <hip/hip_runtime.h>
__global__ void setValue(char *data, int idx, char value) {
if(threadIdx.x == 0) {
data[idx] = value;
// data[idx] = 15;
}
}
int main(int argc, char *argv[]) {
int N = 1024;
char *gpuChars;
hipMalloc((void**)(&gpuChars), N * sizeof(char));
setValue<<<dim3(32, 1, 1), dim3(32, 1, 1)>>>(gpuChars, 2, (char)89);
char hostChars[4];
hipMemcpy(hostChars, gpuChars, 4 * sizeof(char), hipMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 89);
setValue<<<dim3(32, 1, 1), dim3(32, 1, 1)>>>(gpuChars, 2, (char)23);
hipMemcpy(hostChars, gpuChars, 4 * sizeof(char), hipMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 23);
hostChars[2] = 44;
hipMemcpy(gpuChars, hostChars, 4 * sizeof(char), hipMemcpyHostToDevice);
hostChars[2] = 55;
hipMemcpy(hostChars, gpuChars, 4 * sizeof(char), hipMemcpyDeviceToHost);
cout << "hostChars[2] " << (int)hostChars[2] << endl;
assert(hostChars[2] == 44);
hipFree(gpuChars);
return 0;
} | .text
.file "test_char.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__setValuePcic # -- Begin function _Z23__device_stub__setValuePcic
.p2align 4, 0x90
.type _Z23__device_stub__setValuePcic,@function
_Z23__device_stub__setValuePcic: # @_Z23__device_stub__setValuePcic
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movb %dl, 3(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 3(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8setValuePcic, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__setValuePcic, .Lfunc_end0-_Z23__device_stub__setValuePcic
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967328, %rbx # imm = 0x100000020
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $2, 20(%rsp)
movb $89, 3(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 3(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8setValuePcic, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 3(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsbl 5(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_17
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_5
# %bb.4:
movzbl 67(%r14), %ecx
jmp .LBB1_6
.LBB1_5:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $2, 20(%rsp)
movb $23, 7(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 7(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8setValuePcic, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 8(%rsp), %rsi
leaq 3(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsbl 5(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_17
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movb $44, 5(%rsp)
movq 8(%rsp), %rdi
leaq 3(%rsp), %rbx
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movb $55, 5(%rsp)
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsbl 5(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_17
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8setValuePcic, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8setValuePcic,@object # @_Z8setValuePcic
.section .rodata,"a",@progbits
.globl _Z8setValuePcic
.p2align 3, 0x0
_Z8setValuePcic:
.quad _Z23__device_stub__setValuePcic
.size _Z8setValuePcic, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hostChars[2] "
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8setValuePcic"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__setValuePcic
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8setValuePcic
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8setValuePcic
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ LDC.S8 R5, c[0x0][0x16c] ; /* 0x00005b00ff057b82 */
/* 0x000e220000000200 */
/*0050*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe40000000800 */
/*0060*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0070*/ UIADD3 UR4, UP0, UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fc8000ff1e03f */
/*0080*/ ULEA.HI.X.SX32 UR5, UR5, UR7, 0x1, UP0 ; /* 0x0000000705057291 */
/* 0x000fe400080f0e3f */
/*0090*/ MOV R2, UR4 ; /* 0x0000000400027c02 */
/* 0x000fc80008000f00 */
/*00a0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ PRMT R5, R5, 0x7710, RZ ; /* 0x0000771005057816 */
/* 0x001fca00000000ff */
/*00d0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8setValuePcic
.globl _Z8setValuePcic
.p2align 8
.type _Z8setValuePcic,@function
_Z8setValuePcic:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
s_ashr_i32 s3, s2, 31
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b8 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8setValuePcic
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8setValuePcic, .Lfunc_end0-_Z8setValuePcic
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 1
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8setValuePcic
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z8setValuePcic.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00049197_00000000-6_test_char.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4316:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4316:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8setValuePcicPcic
.type _Z29__device_stub__Z8setValuePcicPcic, @function
_Z29__device_stub__Z8setValuePcicPcic:
.LFB4338:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movb %dl, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8setValuePcic(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4338:
.size _Z29__device_stub__Z8setValuePcicPcic, .-_Z29__device_stub__Z8setValuePcicPcic
.globl _Z8setValuePcic
.type _Z8setValuePcic, @function
_Z8setValuePcic:
.LFB4339:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movsbl %dl, %edx
call _Z29__device_stub__Z8setValuePcicPcic
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4339:
.size _Z8setValuePcic, .-_Z8setValuePcic
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hostChars[2] "
.text
.globl main
.type main, @function
main:
.LFB4313:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $32, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
leaq 36(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsbl 38(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $32, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $32, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
leaq 36(%rsp), %rbx
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %r12
movq %r12, %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsbl 38(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movb $44, 38(%rsp)
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movb $55, 38(%rsp)
movl $2, %ecx
movl $4, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %r12, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsbl 38(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $89, %edx
movl $2, %esi
movq (%rsp), %rdi
call _Z29__device_stub__Z8setValuePcicPcic
jmp .L12
.L17:
movl $23, %edx
movl $2, %esi
movq (%rsp), %rdi
call _Z29__device_stub__Z8setValuePcicPcic
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4313:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8setValuePcic"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4341:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8setValuePcic(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4341:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_char.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__setValuePcic # -- Begin function _Z23__device_stub__setValuePcic
.p2align 4, 0x90
.type _Z23__device_stub__setValuePcic,@function
_Z23__device_stub__setValuePcic: # @_Z23__device_stub__setValuePcic
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movb %dl, 3(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 3(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8setValuePcic, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__setValuePcic, .Lfunc_end0-_Z23__device_stub__setValuePcic
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967328, %rbx # imm = 0x100000020
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $2, 20(%rsp)
movb $89, 3(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 3(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8setValuePcic, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 3(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsbl 5(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_17
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_5
# %bb.4:
movzbl 67(%r14), %ecx
jmp .LBB1_6
.LBB1_5:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $2, 20(%rsp)
movb $23, 7(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 7(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8setValuePcic, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 8(%rsp), %rsi
leaq 3(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsbl 5(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_17
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movb $44, 5(%rsp)
movq 8(%rsp), %rdi
leaq 3(%rsp), %rbx
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movb $55, 5(%rsp)
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsbl 5(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_17
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8setValuePcic, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8setValuePcic,@object # @_Z8setValuePcic
.section .rodata,"a",@progbits
.globl _Z8setValuePcic
.p2align 3, 0x0
_Z8setValuePcic:
.quad _Z23__device_stub__setValuePcic
.size _Z8setValuePcic, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hostChars[2] "
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8setValuePcic"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__setValuePcic
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8setValuePcic
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include <optixu/optixu_math_namespace.h>
////#include "optixPathTracer.h"
//
//using namespace optix;
//
//// Adaptive post processing variables and buffers
//
//rtDeclareVariable(unsigned int, window_size, , );
////rtDeclareVariable(unsigned int, max_ray_budget_total, , ) = static_cast<uint>(50u);
//rtDeclareVariable(unsigned int, max_per_frame_samples_budget, , ) = static_cast<uint>(5u); /* this variable can be written by the user */
//
////
//// Adaptive version of pathtracing begin
////
//
///*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
///* Adaptive additional rays variables */
//rtBuffer<int4, 2> adaptive_samples_budget_buffer; /* this buffer will be initialized by the host, but must also be modified by the graphics device */
// //rtBuffer<int4, 2> hoelder_refinement_buffer; /* this buffer contains the information, where refinement will take place according to
// //hoelder regularity criterion, everywhere where refinement is needed value is 1, else zero */
//
//// For debug!
//rtBuffer<float4, 2> per_window_variance_buffer_output;
//
//rtBuffer<float4, 2> input_buffer; /* this buffer contains the initially rendered picture to be post processed */
//
////rtBuffer<float4, 2> post_process_output_buffer; /* this buffer contains the result, processed with additional adaptive rays */
//
//static __device__ __inline__ float compute_window_variance(uint2 center, uint window_size)
//{
// uint2 screen = make_uint2(input_buffer.size().x, input_buffer.size().y);
//
// float mean = 0.f;
// float variance = 0.f;
// if (per_window_variance_buffer_output[center].x < 0.0f)
// {
// uint squared_window_size = window_size * window_size;
// uint half_window_size = (window_size / 2) + (window_size % 2);
// uint2 top_left_window_corner = make_uint2(center.x - half_window_size, center.y - half_window_size);
//
// //rtPrintf("Top left window corner: [ %d , %d ]\n\n", top_left_window_corner.x, top_left_window_corner.y);
// //post_process_output_buffer[center] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
//
// /* compute mean value */
// for (uint i = 0; i < squared_window_size; i++)
// {
// uint2 idx = make_uint2((i % window_size + top_left_window_corner.x) % screen.x, (i / window_size + top_left_window_corner.y) % screen.y);
// float3 input_buffer_val = make_float3(input_buffer[idx].x, input_buffer[idx].y, input_buffer[idx].z);
// mean += 1.f / 3.f * (input_buffer_val.x + input_buffer_val.y + input_buffer_val.z);
// //if (i % window_size <= i / window_size)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == 0 && i / window_size == 0)
// //{
// // //rtPrintf("Left lower corner, with window size: %d!!! \n\n", window_size);
// // //rtPrintf("Center: [ %d , %d ], Current global window index: [ %d , %d ] \n\n", center.x, center.y, idx.x, idx.y);
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == window_size - 1 && i / window_size == 0)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == 0 && i / window_size == window_size - 1)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == window_size - 1 && i / window_size == window_size - 1)
// //{
// //post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //post_process_output_buffer[top_left_window_corner] = make_float4(100.0f, 0.0f, 0.0f, 1.0f);
// //}
// }
//
// /*mean *= 1.f/ squared_window_size;*/
// mean = 1.f / squared_window_size * mean;
//
// /* compute variance */
// for (uint i = 0; i < squared_window_size; i++)
// {
// uint2 idx = make_uint2((i % window_size + top_left_window_corner.x) % screen.x, (i / window_size + top_left_window_corner.y) % screen.x);
// float3 input_buffer_val = make_float3(input_buffer[idx].x, input_buffer[idx].y, input_buffer[idx].z);
// float var = 1.f / 3.f * (input_buffer_val.x + input_buffer_val.y + input_buffer_val.z);
// /*variance += var * var;*/
// variance += (var * var - 2.0f * mean * var + mean * mean);
// }
//
// //variance = 1.f / squared_window_size * (variance) - (mean * mean);
// variance = 1.f / squared_window_size * variance;
//
// per_window_variance_buffer_output[center] = make_float4(variance);
// //atomicExch(&per_window_variance_buffer_output[center].x, variance);
//
// rtPrintf("Set variance!!!\n\n");
// }
// else
// {
// rtPrintf("Reuse variance!!!\n\n");
// variance = per_window_variance_buffer_output[center].x;
// }
//
// return variance;
//};
//
//static __device__ __inline__ uint compute_samples_number(uint2 current_launch_index, float variance)
//{
// uint samples_number = 0;
//
// if (adaptive_samples_budget_buffer[current_launch_index].x > 0)
// {
// samples_number = static_cast<uint>(clamp(static_cast<float>(variance * max_per_frame_samples_budget), 0.0f, static_cast<float>(max_per_frame_samples_budget)));
// adaptive_samples_budget_buffer[current_launch_index] = make_int4(adaptive_samples_budget_buffer[current_launch_index].x - static_cast<int>(samples_number));
// }
//
// return samples_number;
//};
//
//static __device__ __inline__ uint compute_current_samples_number(uint2 current_launch_index, uint window_size)
//{
// uint sample_number = 0;
//
// //uint additional_samples_number = 0;
//
// size_t2 screen = input_buffer.size();
//
// uint times_width = screen.x / window_size;
// uint times_height = screen.y / window_size;
//
// uint horizontal_padding = static_cast<uint>(0.5f * (screen.x - (times_width * window_size)));
// uint vertical_padding = static_cast<uint>(0.5f * (screen.y - (times_height * window_size)));
//
// uint half_window_size = (window_size / 2) + (window_size % 2);
//
// uint2 times_launch_index = make_uint2(((current_launch_index.x / window_size) * window_size) % screen.x, ((current_launch_index.y / window_size) * window_size) % screen.y);
//
// uint2 current_window_center = make_uint2(times_launch_index.x + horizontal_padding + half_window_size, times_launch_index.y + vertical_padding + half_window_size);
//
// float variance = compute_window_variance(current_window_center, window_size);
//
// sample_number = compute_samples_number(current_launch_index, (30.0f * variance));
//
// return sample_number;
//}; | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include <optixu/optixu_math_namespace.h>
////#include "optixPathTracer.h"
//
//using namespace optix;
//
//// Adaptive post processing variables and buffers
//
//rtDeclareVariable(unsigned int, window_size, , );
////rtDeclareVariable(unsigned int, max_ray_budget_total, , ) = static_cast<uint>(50u);
//rtDeclareVariable(unsigned int, max_per_frame_samples_budget, , ) = static_cast<uint>(5u); /* this variable can be written by the user */
//
////
//// Adaptive version of pathtracing begin
////
//
///*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
///* Adaptive additional rays variables */
//rtBuffer<int4, 2> adaptive_samples_budget_buffer; /* this buffer will be initialized by the host, but must also be modified by the graphics device */
// //rtBuffer<int4, 2> hoelder_refinement_buffer; /* this buffer contains the information, where refinement will take place according to
// //hoelder regularity criterion, everywhere where refinement is needed value is 1, else zero */
//
//// For debug!
//rtBuffer<float4, 2> per_window_variance_buffer_output;
//
//rtBuffer<float4, 2> input_buffer; /* this buffer contains the initially rendered picture to be post processed */
//
////rtBuffer<float4, 2> post_process_output_buffer; /* this buffer contains the result, processed with additional adaptive rays */
//
//static __device__ __inline__ float compute_window_variance(uint2 center, uint window_size)
//{
// uint2 screen = make_uint2(input_buffer.size().x, input_buffer.size().y);
//
// float mean = 0.f;
// float variance = 0.f;
// if (per_window_variance_buffer_output[center].x < 0.0f)
// {
// uint squared_window_size = window_size * window_size;
// uint half_window_size = (window_size / 2) + (window_size % 2);
// uint2 top_left_window_corner = make_uint2(center.x - half_window_size, center.y - half_window_size);
//
// //rtPrintf("Top left window corner: [ %d , %d ]\n\n", top_left_window_corner.x, top_left_window_corner.y);
// //post_process_output_buffer[center] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
//
// /* compute mean value */
// for (uint i = 0; i < squared_window_size; i++)
// {
// uint2 idx = make_uint2((i % window_size + top_left_window_corner.x) % screen.x, (i / window_size + top_left_window_corner.y) % screen.y);
// float3 input_buffer_val = make_float3(input_buffer[idx].x, input_buffer[idx].y, input_buffer[idx].z);
// mean += 1.f / 3.f * (input_buffer_val.x + input_buffer_val.y + input_buffer_val.z);
// //if (i % window_size <= i / window_size)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == 0 && i / window_size == 0)
// //{
// // //rtPrintf("Left lower corner, with window size: %d!!! \n\n", window_size);
// // //rtPrintf("Center: [ %d , %d ], Current global window index: [ %d , %d ] \n\n", center.x, center.y, idx.x, idx.y);
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == window_size - 1 && i / window_size == 0)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == 0 && i / window_size == window_size - 1)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == window_size - 1 && i / window_size == window_size - 1)
// //{
// //post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //post_process_output_buffer[top_left_window_corner] = make_float4(100.0f, 0.0f, 0.0f, 1.0f);
// //}
// }
//
// /*mean *= 1.f/ squared_window_size;*/
// mean = 1.f / squared_window_size * mean;
//
// /* compute variance */
// for (uint i = 0; i < squared_window_size; i++)
// {
// uint2 idx = make_uint2((i % window_size + top_left_window_corner.x) % screen.x, (i / window_size + top_left_window_corner.y) % screen.x);
// float3 input_buffer_val = make_float3(input_buffer[idx].x, input_buffer[idx].y, input_buffer[idx].z);
// float var = 1.f / 3.f * (input_buffer_val.x + input_buffer_val.y + input_buffer_val.z);
// /*variance += var * var;*/
// variance += (var * var - 2.0f * mean * var + mean * mean);
// }
//
// //variance = 1.f / squared_window_size * (variance) - (mean * mean);
// variance = 1.f / squared_window_size * variance;
//
// per_window_variance_buffer_output[center] = make_float4(variance);
// //atomicExch(&per_window_variance_buffer_output[center].x, variance);
//
// rtPrintf("Set variance!!!\n\n");
// }
// else
// {
// rtPrintf("Reuse variance!!!\n\n");
// variance = per_window_variance_buffer_output[center].x;
// }
//
// return variance;
//};
//
//static __device__ __inline__ uint compute_samples_number(uint2 current_launch_index, float variance)
//{
// uint samples_number = 0;
//
// if (adaptive_samples_budget_buffer[current_launch_index].x > 0)
// {
// samples_number = static_cast<uint>(clamp(static_cast<float>(variance * max_per_frame_samples_budget), 0.0f, static_cast<float>(max_per_frame_samples_budget)));
// adaptive_samples_budget_buffer[current_launch_index] = make_int4(adaptive_samples_budget_buffer[current_launch_index].x - static_cast<int>(samples_number));
// }
//
// return samples_number;
//};
//
//static __device__ __inline__ uint compute_current_samples_number(uint2 current_launch_index, uint window_size)
//{
// uint sample_number = 0;
//
// //uint additional_samples_number = 0;
//
// size_t2 screen = input_buffer.size();
//
// uint times_width = screen.x / window_size;
// uint times_height = screen.y / window_size;
//
// uint horizontal_padding = static_cast<uint>(0.5f * (screen.x - (times_width * window_size)));
// uint vertical_padding = static_cast<uint>(0.5f * (screen.y - (times_height * window_size)));
//
// uint half_window_size = (window_size / 2) + (window_size % 2);
//
// uint2 times_launch_index = make_uint2(((current_launch_index.x / window_size) * window_size) % screen.x, ((current_launch_index.y / window_size) * window_size) % screen.y);
//
// uint2 current_window_center = make_uint2(times_launch_index.x + horizontal_padding + half_window_size, times_launch_index.y + vertical_padding + half_window_size);
//
// float variance = compute_window_variance(current_window_center, window_size);
//
// sample_number = compute_samples_number(current_launch_index, (30.0f * variance));
//
// return sample_number;
//}; | .file "tmpxft_00053467_00000000-6_variance_adaptive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include <optixu/optixu_math_namespace.h>
////#include "optixPathTracer.h"
//
//using namespace optix;
//
//// Adaptive post processing variables and buffers
//
//rtDeclareVariable(unsigned int, window_size, , );
////rtDeclareVariable(unsigned int, max_ray_budget_total, , ) = static_cast<uint>(50u);
//rtDeclareVariable(unsigned int, max_per_frame_samples_budget, , ) = static_cast<uint>(5u); /* this variable can be written by the user */
//
////
//// Adaptive version of pathtracing begin
////
//
///*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
///* Adaptive additional rays variables */
//rtBuffer<int4, 2> adaptive_samples_budget_buffer; /* this buffer will be initialized by the host, but must also be modified by the graphics device */
// //rtBuffer<int4, 2> hoelder_refinement_buffer; /* this buffer contains the information, where refinement will take place according to
// //hoelder regularity criterion, everywhere where refinement is needed value is 1, else zero */
//
//// For debug!
//rtBuffer<float4, 2> per_window_variance_buffer_output;
//
//rtBuffer<float4, 2> input_buffer; /* this buffer contains the initially rendered picture to be post processed */
//
////rtBuffer<float4, 2> post_process_output_buffer; /* this buffer contains the result, processed with additional adaptive rays */
//
//static __device__ __inline__ float compute_window_variance(uint2 center, uint window_size)
//{
// uint2 screen = make_uint2(input_buffer.size().x, input_buffer.size().y);
//
// float mean = 0.f;
// float variance = 0.f;
// if (per_window_variance_buffer_output[center].x < 0.0f)
// {
// uint squared_window_size = window_size * window_size;
// uint half_window_size = (window_size / 2) + (window_size % 2);
// uint2 top_left_window_corner = make_uint2(center.x - half_window_size, center.y - half_window_size);
//
// //rtPrintf("Top left window corner: [ %d , %d ]\n\n", top_left_window_corner.x, top_left_window_corner.y);
// //post_process_output_buffer[center] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
//
// /* compute mean value */
// for (uint i = 0; i < squared_window_size; i++)
// {
// uint2 idx = make_uint2((i % window_size + top_left_window_corner.x) % screen.x, (i / window_size + top_left_window_corner.y) % screen.y);
// float3 input_buffer_val = make_float3(input_buffer[idx].x, input_buffer[idx].y, input_buffer[idx].z);
// mean += 1.f / 3.f * (input_buffer_val.x + input_buffer_val.y + input_buffer_val.z);
// //if (i % window_size <= i / window_size)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == 0 && i / window_size == 0)
// //{
// // //rtPrintf("Left lower corner, with window size: %d!!! \n\n", window_size);
// // //rtPrintf("Center: [ %d , %d ], Current global window index: [ %d , %d ] \n\n", center.x, center.y, idx.x, idx.y);
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == window_size - 1 && i / window_size == 0)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == 0 && i / window_size == window_size - 1)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == window_size - 1 && i / window_size == window_size - 1)
// //{
// //post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //post_process_output_buffer[top_left_window_corner] = make_float4(100.0f, 0.0f, 0.0f, 1.0f);
// //}
// }
//
// /*mean *= 1.f/ squared_window_size;*/
// mean = 1.f / squared_window_size * mean;
//
// /* compute variance */
// for (uint i = 0; i < squared_window_size; i++)
// {
// uint2 idx = make_uint2((i % window_size + top_left_window_corner.x) % screen.x, (i / window_size + top_left_window_corner.y) % screen.x);
// float3 input_buffer_val = make_float3(input_buffer[idx].x, input_buffer[idx].y, input_buffer[idx].z);
// float var = 1.f / 3.f * (input_buffer_val.x + input_buffer_val.y + input_buffer_val.z);
// /*variance += var * var;*/
// variance += (var * var - 2.0f * mean * var + mean * mean);
// }
//
// //variance = 1.f / squared_window_size * (variance) - (mean * mean);
// variance = 1.f / squared_window_size * variance;
//
// per_window_variance_buffer_output[center] = make_float4(variance);
// //atomicExch(&per_window_variance_buffer_output[center].x, variance);
//
// rtPrintf("Set variance!!!\n\n");
// }
// else
// {
// rtPrintf("Reuse variance!!!\n\n");
// variance = per_window_variance_buffer_output[center].x;
// }
//
// return variance;
//};
//
//static __device__ __inline__ uint compute_samples_number(uint2 current_launch_index, float variance)
//{
// uint samples_number = 0;
//
// if (adaptive_samples_budget_buffer[current_launch_index].x > 0)
// {
// samples_number = static_cast<uint>(clamp(static_cast<float>(variance * max_per_frame_samples_budget), 0.0f, static_cast<float>(max_per_frame_samples_budget)));
// adaptive_samples_budget_buffer[current_launch_index] = make_int4(adaptive_samples_budget_buffer[current_launch_index].x - static_cast<int>(samples_number));
// }
//
// return samples_number;
//};
//
//static __device__ __inline__ uint compute_current_samples_number(uint2 current_launch_index, uint window_size)
//{
// uint sample_number = 0;
//
// //uint additional_samples_number = 0;
//
// size_t2 screen = input_buffer.size();
//
// uint times_width = screen.x / window_size;
// uint times_height = screen.y / window_size;
//
// uint horizontal_padding = static_cast<uint>(0.5f * (screen.x - (times_width * window_size)));
// uint vertical_padding = static_cast<uint>(0.5f * (screen.y - (times_height * window_size)));
//
// uint half_window_size = (window_size / 2) + (window_size % 2);
//
// uint2 times_launch_index = make_uint2(((current_launch_index.x / window_size) * window_size) % screen.x, ((current_launch_index.y / window_size) * window_size) % screen.y);
//
// uint2 current_window_center = make_uint2(times_launch_index.x + horizontal_padding + half_window_size, times_launch_index.y + vertical_padding + half_window_size);
//
// float variance = compute_window_variance(current_window_center, window_size);
//
// sample_number = compute_samples_number(current_launch_index, (30.0f * variance));
//
// return sample_number;
//}; | #include <hip/hip_runtime.h>
//#include <optixu/optixu_math_namespace.h>
////#include "optixPathTracer.h"
//
//using namespace optix;
//
//// Adaptive post processing variables and buffers
//
//rtDeclareVariable(unsigned int, window_size, , );
////rtDeclareVariable(unsigned int, max_ray_budget_total, , ) = static_cast<uint>(50u);
//rtDeclareVariable(unsigned int, max_per_frame_samples_budget, , ) = static_cast<uint>(5u); /* this variable can be written by the user */
//
////
//// Adaptive version of pathtracing begin
////
//
///*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
///* Adaptive additional rays variables */
//rtBuffer<int4, 2> adaptive_samples_budget_buffer; /* this buffer will be initialized by the host, but must also be modified by the graphics device */
// //rtBuffer<int4, 2> hoelder_refinement_buffer; /* this buffer contains the information, where refinement will take place according to
// //hoelder regularity criterion, everywhere where refinement is needed value is 1, else zero */
//
//// For debug!
//rtBuffer<float4, 2> per_window_variance_buffer_output;
//
//rtBuffer<float4, 2> input_buffer; /* this buffer contains the initially rendered picture to be post processed */
//
////rtBuffer<float4, 2> post_process_output_buffer; /* this buffer contains the result, processed with additional adaptive rays */
//
//static __device__ __inline__ float compute_window_variance(uint2 center, uint window_size)
//{
// uint2 screen = make_uint2(input_buffer.size().x, input_buffer.size().y);
//
// float mean = 0.f;
// float variance = 0.f;
// if (per_window_variance_buffer_output[center].x < 0.0f)
// {
// uint squared_window_size = window_size * window_size;
// uint half_window_size = (window_size / 2) + (window_size % 2);
// uint2 top_left_window_corner = make_uint2(center.x - half_window_size, center.y - half_window_size);
//
// //rtPrintf("Top left window corner: [ %d , %d ]\n\n", top_left_window_corner.x, top_left_window_corner.y);
// //post_process_output_buffer[center] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
//
// /* compute mean value */
// for (uint i = 0; i < squared_window_size; i++)
// {
// uint2 idx = make_uint2((i % window_size + top_left_window_corner.x) % screen.x, (i / window_size + top_left_window_corner.y) % screen.y);
// float3 input_buffer_val = make_float3(input_buffer[idx].x, input_buffer[idx].y, input_buffer[idx].z);
// mean += 1.f / 3.f * (input_buffer_val.x + input_buffer_val.y + input_buffer_val.z);
// //if (i % window_size <= i / window_size)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == 0 && i / window_size == 0)
// //{
// // //rtPrintf("Left lower corner, with window size: %d!!! \n\n", window_size);
// // //rtPrintf("Center: [ %d , %d ], Current global window index: [ %d , %d ] \n\n", center.x, center.y, idx.x, idx.y);
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == window_size - 1 && i / window_size == 0)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == 0 && i / window_size == window_size - 1)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == window_size - 1 && i / window_size == window_size - 1)
// //{
// //post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //post_process_output_buffer[top_left_window_corner] = make_float4(100.0f, 0.0f, 0.0f, 1.0f);
// //}
// }
//
// /*mean *= 1.f/ squared_window_size;*/
// mean = 1.f / squared_window_size * mean;
//
// /* compute variance */
// for (uint i = 0; i < squared_window_size; i++)
// {
// uint2 idx = make_uint2((i % window_size + top_left_window_corner.x) % screen.x, (i / window_size + top_left_window_corner.y) % screen.x);
// float3 input_buffer_val = make_float3(input_buffer[idx].x, input_buffer[idx].y, input_buffer[idx].z);
// float var = 1.f / 3.f * (input_buffer_val.x + input_buffer_val.y + input_buffer_val.z);
// /*variance += var * var;*/
// variance += (var * var - 2.0f * mean * var + mean * mean);
// }
//
// //variance = 1.f / squared_window_size * (variance) - (mean * mean);
// variance = 1.f / squared_window_size * variance;
//
// per_window_variance_buffer_output[center] = make_float4(variance);
// //atomicExch(&per_window_variance_buffer_output[center].x, variance);
//
// rtPrintf("Set variance!!!\n\n");
// }
// else
// {
// rtPrintf("Reuse variance!!!\n\n");
// variance = per_window_variance_buffer_output[center].x;
// }
//
// return variance;
//};
//
//static __device__ __inline__ uint compute_samples_number(uint2 current_launch_index, float variance)
//{
// uint samples_number = 0;
//
// if (adaptive_samples_budget_buffer[current_launch_index].x > 0)
// {
// samples_number = static_cast<uint>(clamp(static_cast<float>(variance * max_per_frame_samples_budget), 0.0f, static_cast<float>(max_per_frame_samples_budget)));
// adaptive_samples_budget_buffer[current_launch_index] = make_int4(adaptive_samples_budget_buffer[current_launch_index].x - static_cast<int>(samples_number));
// }
//
// return samples_number;
//};
//
//static __device__ __inline__ uint compute_current_samples_number(uint2 current_launch_index, uint window_size)
//{
// uint sample_number = 0;
//
// //uint additional_samples_number = 0;
//
// size_t2 screen = input_buffer.size();
//
// uint times_width = screen.x / window_size;
// uint times_height = screen.y / window_size;
//
// uint horizontal_padding = static_cast<uint>(0.5f * (screen.x - (times_width * window_size)));
// uint vertical_padding = static_cast<uint>(0.5f * (screen.y - (times_height * window_size)));
//
// uint half_window_size = (window_size / 2) + (window_size % 2);
//
// uint2 times_launch_index = make_uint2(((current_launch_index.x / window_size) * window_size) % screen.x, ((current_launch_index.y / window_size) * window_size) % screen.y);
//
// uint2 current_window_center = make_uint2(times_launch_index.x + horizontal_padding + half_window_size, times_launch_index.y + vertical_padding + half_window_size);
//
// float variance = compute_window_variance(current_window_center, window_size);
//
// sample_number = compute_samples_number(current_launch_index, (30.0f * variance));
//
// return sample_number;
//}; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include <optixu/optixu_math_namespace.h>
////#include "optixPathTracer.h"
//
//using namespace optix;
//
//// Adaptive post processing variables and buffers
//
//rtDeclareVariable(unsigned int, window_size, , );
////rtDeclareVariable(unsigned int, max_ray_budget_total, , ) = static_cast<uint>(50u);
//rtDeclareVariable(unsigned int, max_per_frame_samples_budget, , ) = static_cast<uint>(5u); /* this variable can be written by the user */
//
////
//// Adaptive version of pathtracing begin
////
//
///*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
///* Adaptive additional rays variables */
//rtBuffer<int4, 2> adaptive_samples_budget_buffer; /* this buffer will be initialized by the host, but must also be modified by the graphics device */
// //rtBuffer<int4, 2> hoelder_refinement_buffer; /* this buffer contains the information, where refinement will take place according to
// //hoelder regularity criterion, everywhere where refinement is needed value is 1, else zero */
//
//// For debug!
//rtBuffer<float4, 2> per_window_variance_buffer_output;
//
//rtBuffer<float4, 2> input_buffer; /* this buffer contains the initially rendered picture to be post processed */
//
////rtBuffer<float4, 2> post_process_output_buffer; /* this buffer contains the result, processed with additional adaptive rays */
//
//static __device__ __inline__ float compute_window_variance(uint2 center, uint window_size)
//{
// uint2 screen = make_uint2(input_buffer.size().x, input_buffer.size().y);
//
// float mean = 0.f;
// float variance = 0.f;
// if (per_window_variance_buffer_output[center].x < 0.0f)
// {
// uint squared_window_size = window_size * window_size;
// uint half_window_size = (window_size / 2) + (window_size % 2);
// uint2 top_left_window_corner = make_uint2(center.x - half_window_size, center.y - half_window_size);
//
// //rtPrintf("Top left window corner: [ %d , %d ]\n\n", top_left_window_corner.x, top_left_window_corner.y);
// //post_process_output_buffer[center] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
//
// /* compute mean value */
// for (uint i = 0; i < squared_window_size; i++)
// {
// uint2 idx = make_uint2((i % window_size + top_left_window_corner.x) % screen.x, (i / window_size + top_left_window_corner.y) % screen.y);
// float3 input_buffer_val = make_float3(input_buffer[idx].x, input_buffer[idx].y, input_buffer[idx].z);
// mean += 1.f / 3.f * (input_buffer_val.x + input_buffer_val.y + input_buffer_val.z);
// //if (i % window_size <= i / window_size)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == 0 && i / window_size == 0)
// //{
// // //rtPrintf("Left lower corner, with window size: %d!!! \n\n", window_size);
// // //rtPrintf("Center: [ %d , %d ], Current global window index: [ %d , %d ] \n\n", center.x, center.y, idx.x, idx.y);
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == window_size - 1 && i / window_size == 0)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == 0 && i / window_size == window_size - 1)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == window_size - 1 && i / window_size == window_size - 1)
// //{
// //post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //post_process_output_buffer[top_left_window_corner] = make_float4(100.0f, 0.0f, 0.0f, 1.0f);
// //}
// }
//
// /*mean *= 1.f/ squared_window_size;*/
// mean = 1.f / squared_window_size * mean;
//
// /* compute variance */
// for (uint i = 0; i < squared_window_size; i++)
// {
// uint2 idx = make_uint2((i % window_size + top_left_window_corner.x) % screen.x, (i / window_size + top_left_window_corner.y) % screen.x);
// float3 input_buffer_val = make_float3(input_buffer[idx].x, input_buffer[idx].y, input_buffer[idx].z);
// float var = 1.f / 3.f * (input_buffer_val.x + input_buffer_val.y + input_buffer_val.z);
// /*variance += var * var;*/
// variance += (var * var - 2.0f * mean * var + mean * mean);
// }
//
// //variance = 1.f / squared_window_size * (variance) - (mean * mean);
// variance = 1.f / squared_window_size * variance;
//
// per_window_variance_buffer_output[center] = make_float4(variance);
// //atomicExch(&per_window_variance_buffer_output[center].x, variance);
//
// rtPrintf("Set variance!!!\n\n");
// }
// else
// {
// rtPrintf("Reuse variance!!!\n\n");
// variance = per_window_variance_buffer_output[center].x;
// }
//
// return variance;
//};
//
//static __device__ __inline__ uint compute_samples_number(uint2 current_launch_index, float variance)
//{
// uint samples_number = 0;
//
// if (adaptive_samples_budget_buffer[current_launch_index].x > 0)
// {
// samples_number = static_cast<uint>(clamp(static_cast<float>(variance * max_per_frame_samples_budget), 0.0f, static_cast<float>(max_per_frame_samples_budget)));
// adaptive_samples_budget_buffer[current_launch_index] = make_int4(adaptive_samples_budget_buffer[current_launch_index].x - static_cast<int>(samples_number));
// }
//
// return samples_number;
//};
//
//static __device__ __inline__ uint compute_current_samples_number(uint2 current_launch_index, uint window_size)
//{
// uint sample_number = 0;
//
// //uint additional_samples_number = 0;
//
// size_t2 screen = input_buffer.size();
//
// uint times_width = screen.x / window_size;
// uint times_height = screen.y / window_size;
//
// uint horizontal_padding = static_cast<uint>(0.5f * (screen.x - (times_width * window_size)));
// uint vertical_padding = static_cast<uint>(0.5f * (screen.y - (times_height * window_size)));
//
// uint half_window_size = (window_size / 2) + (window_size % 2);
//
// uint2 times_launch_index = make_uint2(((current_launch_index.x / window_size) * window_size) % screen.x, ((current_launch_index.y / window_size) * window_size) % screen.y);
//
// uint2 current_window_center = make_uint2(times_launch_index.x + horizontal_padding + half_window_size, times_launch_index.y + vertical_padding + half_window_size);
//
// float variance = compute_window_variance(current_window_center, window_size);
//
// sample_number = compute_samples_number(current_launch_index, (30.0f * variance));
//
// return sample_number;
//}; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include <optixu/optixu_math_namespace.h>
////#include "optixPathTracer.h"
//
//using namespace optix;
//
//// Adaptive post processing variables and buffers
//
//rtDeclareVariable(unsigned int, window_size, , );
////rtDeclareVariable(unsigned int, max_ray_budget_total, , ) = static_cast<uint>(50u);
//rtDeclareVariable(unsigned int, max_per_frame_samples_budget, , ) = static_cast<uint>(5u); /* this variable can be written by the user */
//
////
//// Adaptive version of pathtracing begin
////
//
///*--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
///* Adaptive additional rays variables */
//rtBuffer<int4, 2> adaptive_samples_budget_buffer; /* this buffer will be initialized by the host, but must also be modified by the graphics device */
// //rtBuffer<int4, 2> hoelder_refinement_buffer; /* this buffer contains the information, where refinement will take place according to
// //hoelder regularity criterion, everywhere where refinement is needed value is 1, else zero */
//
//// For debug!
//rtBuffer<float4, 2> per_window_variance_buffer_output;
//
//rtBuffer<float4, 2> input_buffer; /* this buffer contains the initially rendered picture to be post processed */
//
////rtBuffer<float4, 2> post_process_output_buffer; /* this buffer contains the result, processed with additional adaptive rays */
//
//static __device__ __inline__ float compute_window_variance(uint2 center, uint window_size)
//{
// uint2 screen = make_uint2(input_buffer.size().x, input_buffer.size().y);
//
// float mean = 0.f;
// float variance = 0.f;
// if (per_window_variance_buffer_output[center].x < 0.0f)
// {
// uint squared_window_size = window_size * window_size;
// uint half_window_size = (window_size / 2) + (window_size % 2);
// uint2 top_left_window_corner = make_uint2(center.x - half_window_size, center.y - half_window_size);
//
// //rtPrintf("Top left window corner: [ %d , %d ]\n\n", top_left_window_corner.x, top_left_window_corner.y);
// //post_process_output_buffer[center] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
//
// /* compute mean value */
// for (uint i = 0; i < squared_window_size; i++)
// {
// uint2 idx = make_uint2((i % window_size + top_left_window_corner.x) % screen.x, (i / window_size + top_left_window_corner.y) % screen.y);
// float3 input_buffer_val = make_float3(input_buffer[idx].x, input_buffer[idx].y, input_buffer[idx].z);
// mean += 1.f / 3.f * (input_buffer_val.x + input_buffer_val.y + input_buffer_val.z);
// //if (i % window_size <= i / window_size)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == 0 && i / window_size == 0)
// //{
// // //rtPrintf("Left lower corner, with window size: %d!!! \n\n", window_size);
// // //rtPrintf("Center: [ %d , %d ], Current global window index: [ %d , %d ] \n\n", center.x, center.y, idx.x, idx.y);
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == window_size - 1 && i / window_size == 0)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == 0 && i / window_size == window_size - 1)
// //{
// // post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //}
// //if (i % window_size == window_size - 1 && i / window_size == window_size - 1)
// //{
// //post_process_output_buffer[idx] = make_float4(100.0f, 0.0f, 100.0f, 1.0f);
// //post_process_output_buffer[top_left_window_corner] = make_float4(100.0f, 0.0f, 0.0f, 1.0f);
// //}
// }
//
// /*mean *= 1.f/ squared_window_size;*/
// mean = 1.f / squared_window_size * mean;
//
// /* compute variance */
// for (uint i = 0; i < squared_window_size; i++)
// {
// uint2 idx = make_uint2((i % window_size + top_left_window_corner.x) % screen.x, (i / window_size + top_left_window_corner.y) % screen.x);
// float3 input_buffer_val = make_float3(input_buffer[idx].x, input_buffer[idx].y, input_buffer[idx].z);
// float var = 1.f / 3.f * (input_buffer_val.x + input_buffer_val.y + input_buffer_val.z);
// /*variance += var * var;*/
// variance += (var * var - 2.0f * mean * var + mean * mean);
// }
//
// //variance = 1.f / squared_window_size * (variance) - (mean * mean);
// variance = 1.f / squared_window_size * variance;
//
// per_window_variance_buffer_output[center] = make_float4(variance);
// //atomicExch(&per_window_variance_buffer_output[center].x, variance);
//
// rtPrintf("Set variance!!!\n\n");
// }
// else
// {
// rtPrintf("Reuse variance!!!\n\n");
// variance = per_window_variance_buffer_output[center].x;
// }
//
// return variance;
//};
//
//static __device__ __inline__ uint compute_samples_number(uint2 current_launch_index, float variance)
//{
// uint samples_number = 0;
//
// if (adaptive_samples_budget_buffer[current_launch_index].x > 0)
// {
// samples_number = static_cast<uint>(clamp(static_cast<float>(variance * max_per_frame_samples_budget), 0.0f, static_cast<float>(max_per_frame_samples_budget)));
// adaptive_samples_budget_buffer[current_launch_index] = make_int4(adaptive_samples_budget_buffer[current_launch_index].x - static_cast<int>(samples_number));
// }
//
// return samples_number;
//};
//
//static __device__ __inline__ uint compute_current_samples_number(uint2 current_launch_index, uint window_size)
//{
// uint sample_number = 0;
//
// //uint additional_samples_number = 0;
//
// size_t2 screen = input_buffer.size();
//
// uint times_width = screen.x / window_size;
// uint times_height = screen.y / window_size;
//
// uint horizontal_padding = static_cast<uint>(0.5f * (screen.x - (times_width * window_size)));
// uint vertical_padding = static_cast<uint>(0.5f * (screen.y - (times_height * window_size)));
//
// uint half_window_size = (window_size / 2) + (window_size % 2);
//
// uint2 times_launch_index = make_uint2(((current_launch_index.x / window_size) * window_size) % screen.x, ((current_launch_index.y / window_size) * window_size) % screen.y);
//
// uint2 current_window_center = make_uint2(times_launch_index.x + horizontal_padding + half_window_size, times_launch_index.y + vertical_padding + half_window_size);
//
// float variance = compute_window_variance(current_window_center, window_size);
//
// sample_number = compute_samples_number(current_launch_index, (30.0f * variance));
//
// return sample_number;
//}; | .text
.file "variance_adaptive.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00053467_00000000-6_variance_adaptive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "variance_adaptive.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void assignInitialClusters_64(int width, int height, int nPixels, int clusterCount, int* cluster, int filterCount, float* responses, int* intResponses) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
int pixel = y * width + x;
if ((x < width) && (y < height)) {
int xBlock = x / ((width - 1) / 8 + 1);
int yBlock = y / ((height - 1) / 8 + 1);
int assignedCluster = yBlock * 8 + xBlock;
cluster[y * width + x] = assignedCluster;
for(int i = 0; i < filterCount; i++) {
int index = pixel + i * nPixels;
int response = (int)(INTCONFACTOR * responses[index]);
intResponses[index] = response;
}
}
} | code for sm_80
Function : _Z24assignInitialClusters_64iiiiPiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x160], P0 ; /* 0x0000580003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ MOV R4, c[0x0][0x164] ; /* 0x0000590000047a02 */
/* 0x000fe40000000f00 */
/*00d0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*00e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*00f0*/ SHF.R.S32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff057819 */
/* 0x000fe40000011402 */
/*0100*/ IABS R14, R3 ; /* 0x00000003000e7213 */
/* 0x000fc40000000000 */
/*0110*/ LEA.HI R2, R5, R2, RZ, 0x3 ; /* 0x0000000205027211 */
/* 0x000fe400078f18ff */
/*0120*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*0130*/ LEA.HI.SX32 R2, R2, 0x1, 0x1d ; /* 0x0000000102027811 */
/* 0x000fe400078feaff */
/*0140*/ LEA.HI R5, R5, R4, RZ, 0x3 ; /* 0x0000000405057211 */
/* 0x000fe400078f18ff */
/*0150*/ IABS R4, R2 ; /* 0x0000000200047213 */
/* 0x000fe40000000000 */
/*0160*/ LEA.HI.SX32 R5, R5, 0x1, 0x1d ; /* 0x0000000105057811 */
/* 0x000fc400078feaff */
/*0170*/ I2F.RP R7, R4 ; /* 0x0000000400077306 */
/* 0x000e240000209400 */
/*0180*/ IABS R6, R5 ; /* 0x0000000500067213 */
/* 0x000fcc0000000000 */
/*0190*/ I2F.RP R12, R6 ; /* 0x00000006000c7306 */
/* 0x000e700000209400 */
/*01a0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e300000001000 */
/*01b0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x002e620000001000 */
/*01c0*/ IADD3 R10, R7, 0xffffffe, RZ ; /* 0x0ffffffe070a7810 */
/* 0x001fce0007ffe0ff */
/*01d0*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x0000a2000021f000 */
/*01e0*/ IADD3 R8, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c087810 */
/* 0x002fe40007ffe0ff */
/*01f0*/ IABS R12, R2 ; /* 0x00000002000c7213 */
/* 0x000fca0000000000 */
/*0200*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x0002e2000021f000 */
/*0210*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x001fe200000001ff */
/*0220*/ IADD3 R12, RZ, -R12, RZ ; /* 0x8000000cff0c7210 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R13, RZ, -R11, RZ ; /* 0x8000000bff0d7210 */
/* 0x004fe20007ffe0ff */
/*0240*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x002fc800000001ff */
/*0250*/ IMAD R13, R13, R4, RZ ; /* 0x000000040d0d7224 */
/* 0x000fe200078e02ff */
/*0260*/ IADD3 R7, RZ, -R9, RZ ; /* 0x80000009ff077210 */
/* 0x008fc60007ffe0ff */
/*0270*/ IMAD.HI.U32 R11, R11, R13, R10 ; /* 0x0000000d0b0b7227 */
/* 0x000fe200078e000a */
/*0280*/ MOV R10, R14 ; /* 0x0000000e000a7202 */
/* 0x000fe40000000f00 */
/*0290*/ IABS R13, R0 ; /* 0x00000000000d7213 */
/* 0x000fe20000000000 */
/*02a0*/ IMAD R7, R7, R6, RZ ; /* 0x0000000607077224 */
/* 0x000fe200078e02ff */
/*02b0*/ IABS R14, R5 ; /* 0x00000005000e7213 */
/* 0x000fe20000000000 */
/*02c0*/ IMAD.HI.U32 R11, R11, R10, RZ ; /* 0x0000000a0b0b7227 */
/* 0x000fc600078e00ff */
/*02d0*/ IADD3 R14, RZ, -R14, RZ ; /* 0x8000000eff0e7210 */
/* 0x000fe20007ffe0ff */
/*02e0*/ IMAD.HI.U32 R8, R9, R7, R8 ; /* 0x0000000709087227 */
/* 0x000fe200078e0008 */
/*02f0*/ MOV R7, R12 ; /* 0x0000000c00077202 */
/* 0x000fe40000000f00 */
/*0300*/ MOV R9, R13 ; /* 0x0000000d00097202 */
/* 0x000fe40000000f00 */
/*0310*/ MOV R12, R14 ; /* 0x0000000e000c7202 */
/* 0x000fe20000000f00 */
/*0320*/ IMAD R7, R11, R7, R10 ; /* 0x000000070b077224 */
/* 0x000fe400078e020a */
/*0330*/ IMAD.HI.U32 R8, R8, R9, RZ ; /* 0x0000000908087227 */
/* 0x000fc600078e00ff */
/*0340*/ ISETP.GT.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe20003f04070 */
/*0350*/ IMAD R9, R8, R12, R9 ; /* 0x0000000c08097224 */
/* 0x000fca00078e0209 */
/*0360*/ ISETP.GT.U32.AND P4, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fce0003f84070 */
/*0370*/ @!P0 IADD3 R7, R7, -R4.reuse, RZ ; /* 0x8000000407078210 */
/* 0x080fe40007ffe0ff */
/*0380*/ @!P0 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b8810 */
/* 0x000fe40007ffe0ff */
/*0390*/ ISETP.GE.U32.AND P5, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fe40003fa6070 */
/*03a0*/ LOP3.LUT R4, R3, R2, RZ, 0x3c, !PT ; /* 0x0000000203047212 */
/* 0x000fe400078e3cff */
/*03b0*/ @!P4 IADD3 R9, R9, -R6, RZ ; /* 0x800000060909c210 */
/* 0x000fe40007ffe0ff */
/*03c0*/ ISETP.GE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc40003f46270 */
/*03d0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*03e0*/ ISETP.GE.U32.AND P3, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe20003f66070 */
/*03f0*/ IMAD R9, R0.reuse, c[0x0][0x160], R3 ; /* 0x0000580000097a24 */
/* 0x040fe200078e0203 */
/*0400*/ LOP3.LUT R6, R0, R5, RZ, 0x3c, !PT ; /* 0x0000000500067212 */
/* 0x000fe400078e3cff */
/*0410*/ @!P4 IADD3 R8, R8, 0x1, RZ ; /* 0x000000010808c810 */
/* 0x000fe40007ffe0ff */
/*0420*/ ISETP.GE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f26270 */
/*0430*/ ISETP.NE.AND P4, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc40003f85270 */
/*0440*/ @P5 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b5810 */
/* 0x000fe40007ffe0ff */
/*0450*/ MOV R6, c[0x0][0x178] ; /* 0x00005e0000067a02 */
/* 0x000fe40000000f00 */
/*0460*/ @!P2 IADD3 R11, -R11, RZ, RZ ; /* 0x000000ff0b0ba210 */
/* 0x000fe40007ffe1ff */
/*0470*/ @!P0 LOP3.LUT R11, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff0b8212 */
/* 0x000fe200078e33ff */
/*0480*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0490*/ @P3 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108083810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc40003f06270 */
/*04b0*/ @!P1 IADD3 R8, -R8, RZ, RZ ; /* 0x000000ff08089210 */
/* 0x000fe40007ffe1ff */
/*04c0*/ @!P4 LOP3.LUT R8, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff08c212 */
/* 0x000fc600078e33ff */
/*04d0*/ IMAD.WIDE R4, R9, R2, c[0x0][0x170] ; /* 0x00005c0009047625 */
/* 0x000fe200078e0202 */
/*04e0*/ LEA R7, R8, R11, 0x3 ; /* 0x0000000b08077211 */
/* 0x000fca00078e18ff */
/*04f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101904 */
/*0500*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0510*/ IADD3 R4, R6, -0x1, RZ ; /* 0xffffffff06047810 */
/* 0x001fc80007ffe0ff */
/*0520*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0530*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306047812 */
/* 0x000fe400078ec0ff */
/*0540*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*0550*/ @!P0 BRA 0x11c0 ; /* 0x00000c6000008947 */
/* 0x000fea0003800000 */
/*0560*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe40007ffe1ff */
/*0570*/ SHF.L.U32 R8, R9, 0x2, RZ ; /* 0x0000000209087819 */
/* 0x000fe400000006ff */
/*0580*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*0590*/ SHF.R.S32.HI R6, RZ, 0x1f, R9 ; /* 0x0000001fff067819 */
/* 0x000fe40000011409 */
/*05a0*/ IADD3 R10, P1, R8, c[0x0][0x180], RZ ; /* 0x00006000080a7a10 */
/* 0x000fe40007f3e0ff */
/*05b0*/ SHF.L.U64.HI R6, R9, 0x2, R6 ; /* 0x0000000209067819 */
/* 0x000fc40000010206 */
/*05c0*/ IADD3 R8, P2, R8, c[0x0][0x188], RZ ; /* 0x0000620008087a10 */
/* 0x000fe40007f5e0ff */
/*05d0*/ IADD3.X R11, R6.reuse, c[0x0][0x184], RZ, P1, !PT ; /* 0x00006100060b7a10 */
/* 0x040fe40000ffe4ff */
/*05e0*/ IADD3.X R9, R6, c[0x0][0x18c], RZ, P2, !PT ; /* 0x0000630006097a10 */
/* 0x000fe200017fe4ff */
/*05f0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0600*/ @!P0 BRA 0x1000 ; /* 0x000009f000008947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0620*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0630*/ @!P1 BRA 0xc90 ; /* 0x0000065000009947 */
/* 0x000fea0003800000 */
/*0640*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0650*/ LDG.E R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x002ea2000c1e1900 */
/*0660*/ IMAD.WIDE R12, R2, c[0x0][0x168], R10 ; /* 0x00005a00020c7a25 */
/* 0x000fc800078e020a */
/*0670*/ FMUL R7, R7, 100000 ; /* 0x47c3500007077820 */
/* 0x004fcc0000400000 */
/*0680*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000020f100 */
/*0690*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0011e8000c101904 */
/*06a0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ IMAD.WIDE R16, R2, c[0x0][0x168], R12 ; /* 0x00005a0002107a25 */
/* 0x000fc800078e020c */
/*06c0*/ FMUL R18, R14, 100000 ; /* 0x47c350000e127820 */
/* 0x004fe40000400000 */
/*06d0*/ IMAD.WIDE R14, R2.reuse, c[0x0][0x168], R8 ; /* 0x00005a00020e7a25 */
/* 0x040fe400078e0208 */
/*06e0*/ F2I.TRUNC.NTZ R21, R18 ; /* 0x0000001200157305 */
/* 0x000e66000020f100 */
/*06f0*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0023e8000c101904 */
/*0700*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ea2000c1e1900 */
/*0710*/ IMAD.WIDE R8, R2, c[0x0][0x168], R16 ; /* 0x00005a0002087a25 */
/* 0x001fc800078e0210 */
/*0720*/ FMUL R20, R10, 100000 ; /* 0x47c350000a147820 */
/* 0x004fe40000400000 */
/*0730*/ IMAD.WIDE R10, R2.reuse, c[0x0][0x168], R14 ; /* 0x00005a00020a7a25 */
/* 0x040fe400078e020e */
/*0740*/ F2I.TRUNC.NTZ R23, R20 ; /* 0x0000001400177305 */
/* 0x000e26000020f100 */
/*0750*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0011e8000c101904 */
/*0760*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea2000c1e1900 */
/*0770*/ IMAD.WIDE R18, R2, c[0x0][0x168], R10 ; /* 0x00005a0002127a25 */
/* 0x000fc800078e020a */
/*0780*/ IMAD.WIDE R12, R2, c[0x0][0x168], R8 ; /* 0x00005a00020c7a25 */
/* 0x000fc800078e0208 */
/*0790*/ FMUL R7, R7, 100000 ; /* 0x47c3500007077820 */
/* 0x004fcc0000400000 */
/*07a0*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000ea4000020f100 */
/*07b0*/ STG.E [R18.64], R7 ; /* 0x0000000712007986 */
/* 0x0045e8000c101904 */
/*07c0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x002ee2000c1e1900 */
/*07d0*/ IMAD.WIDE R10, R2, c[0x0][0x168], R12 ; /* 0x00005a00020a7a25 */
/* 0x001fc800078e020c */
/*07e0*/ FMUL R20, R14, 100000 ; /* 0x47c350000e147820 */
/* 0x008fe40000400000 */
/*07f0*/ IMAD.WIDE R14, R2.reuse, c[0x0][0x168], R18 ; /* 0x00005a00020e7a25 */
/* 0x040fe400078e0212 */
/*0800*/ F2I.TRUNC.NTZ R21, R20 ; /* 0x0000001400157305 */
/* 0x000e26000020f100 */
/*0810*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0011e8000c101904 */
/*0820*/ LDG.E R8, [R10.64] ; /* 0x000000040a087981 */
/* 0x000ee2000c1e1900 */
/*0830*/ IMAD.WIDE R16, R2, c[0x0][0x168], R10 ; /* 0x00005a0002107a25 */
/* 0x000fc800078e020a */
/*0840*/ FMUL R22, R8, 100000 ; /* 0x47c3500008167820 */
/* 0x008fe40000400000 */
/*0850*/ IMAD.WIDE R8, R2.reuse, c[0x0][0x168], R14 ; /* 0x00005a0002087a25 */
/* 0x040fe400078e020e */
/*0860*/ F2I.TRUNC.NTZ R23, R22 ; /* 0x0000001600177305 */
/* 0x000e66000020f100 */
/*0870*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0023e8000c101904 */
/*0880*/ LDG.E R7, [R16.64] ; /* 0x0000000410077981 */
/* 0x004ea2000c1e1900 */
/*0890*/ IMAD.WIDE R12, R2, c[0x0][0x168], R8 ; /* 0x00005a00020c7a25 */
/* 0x000fc800078e0208 */
/*08a0*/ IMAD.WIDE R14, R2, c[0x0][0x168], R16 ; /* 0x00005a00020e7a25 */
/* 0x001fc800078e0210 */
/*08b0*/ FMUL R7, R7, 100000 ; /* 0x47c3500007077820 */
/* 0x004fcc0000400000 */
/*08c0*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000020f100 */
/*08d0*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x0011e8000c101904 */
/*08e0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*08f0*/ IMAD.WIDE R8, R2, c[0x0][0x168], R14 ; /* 0x00005a0002087a25 */
/* 0x002fc800078e020e */
/*0900*/ FMUL R18, R10, 100000 ; /* 0x47c350000a127820 */
/* 0x004fe40000400000 */
/*0910*/ IMAD.WIDE R10, R2.reuse, c[0x0][0x168], R12 ; /* 0x00005a00020a7a25 */
/* 0x040fe400078e020c */
/*0920*/ F2I.TRUNC.NTZ R19, R18 ; /* 0x0000001200137305 */
/* 0x000e66000020f100 */
/*0930*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0023e8000c101904 */
/*0940*/ LDG.E R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x000ea2000c1e1900 */
/*0950*/ IMAD.WIDE R12, R2, c[0x0][0x168], R8 ; /* 0x00005a00020c7a25 */
/* 0x001fc800078e0208 */
/*0960*/ FMUL R20, R16, 100000 ; /* 0x47c3500010147820 */
/* 0x004fe40000400000 */
/*0970*/ IMAD.WIDE R16, R2.reuse, c[0x0][0x168], R10 ; /* 0x00005a0002107a25 */
/* 0x040fe400078e020a */
/*0980*/ F2I.TRUNC.NTZ R21, R20 ; /* 0x0000001400157305 */
/* 0x000e26000020f100 */
/*0990*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0011e8000c101904 */
/*09a0*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x000ea2000c1e1900 */
/*09b0*/ IMAD.WIDE R14, R2, c[0x0][0x168], R16 ; /* 0x00005a00020e7a25 */
/* 0x000fc800078e0210 */
/*09c0*/ IMAD.WIDE R10, R2, c[0x0][0x168], R12 ; /* 0x00005a00020a7a25 */
/* 0x002fc800078e020c */
/*09d0*/ FMUL R7, R7, 100000 ; /* 0x47c3500007077820 */
/* 0x004fcc0000400000 */
/*09e0*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e64000020f100 */
/*09f0*/ STG.E [R14.64], R7 ; /* 0x000000070e007986 */
/* 0x0023e8000c101904 */
/*0a00*/ LDG.E R8, [R10.64] ; /* 0x000000040a087981 */
/* 0x000ea2000c1e1900 */
/*0a10*/ IMAD.WIDE R16, R2, c[0x0][0x168], R10 ; /* 0x00005a0002107a25 */
/* 0x001fc800078e020a */
/*0a20*/ FMUL R20, R8, 100000 ; /* 0x47c3500008147820 */
/* 0x004fe40000400000 */
/*0a30*/ IMAD.WIDE R8, R2.reuse, c[0x0][0x168], R14 ; /* 0x00005a0002087a25 */
/* 0x040fe400078e020e */
/*0a40*/ F2I.TRUNC.NTZ R23, R20 ; /* 0x0000001400177305 */
/* 0x000e26000020f100 */
/*0a50*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0011e8000c101904 */
/*0a60*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea2000c1e1900 */
/*0a70*/ IMAD.WIDE R18, R2, c[0x0][0x168], R8 ; /* 0x00005a0002127a25 */
/* 0x000fc800078e0208 */
/*0a80*/ FMUL R21, R12, 100000 ; /* 0x47c350000c157820 */
/* 0x004fe40000400000 */
/*0a90*/ IMAD.WIDE R12, R2, c[0x0][0x168], R16 ; /* 0x00005a00020c7a25 */
/* 0x000fc800078e0210 */
/*0aa0*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000ea4000020f100 */
/*0ab0*/ STG.E [R18.64], R21 ; /* 0x0000001512007986 */
/* 0x0045e8000c101904 */
/*0ac0*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x002ee2000c1e1900 */
/*0ad0*/ IMAD.WIDE R10, R2, c[0x0][0x168], R18 ; /* 0x00005a00020a7a25 */
/* 0x000fc800078e0212 */
/*0ae0*/ IMAD.WIDE R8, R2, c[0x0][0x168], R12 ; /* 0x00005a0002087a25 */
/* 0x001fc800078e020c */
/*0af0*/ FMUL R7, R7, 100000 ; /* 0x47c3500007077820 */
/* 0x008fcc0000400000 */
/*0b00*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000020f100 */
/*0b10*/ STG.E [R10.64], R7 ; /* 0x000000070a007986 */
/* 0x0011e8000c101904 */
/*0b20*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x000ee2000c1e1900 */
/*0b30*/ IMAD.WIDE R16, R2, c[0x0][0x168], R8 ; /* 0x00005a0002107a25 */
/* 0x000fc800078e0208 */
/*0b40*/ FMUL R20, R14, 100000 ; /* 0x47c350000e147820 */
/* 0x008fe40000400000 */
/*0b50*/ IMAD.WIDE R14, R2.reuse, c[0x0][0x168], R10 ; /* 0x00005a00020e7a25 */
/* 0x040fe400078e020a */
/*0b60*/ F2I.TRUNC.NTZ R23, R20 ; /* 0x0000001400177305 */
/* 0x000e66000020f100 */
/*0b70*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0023e8000c101904 */
/*0b80*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee2000c1e1900 */
/*0b90*/ IMAD.WIDE R18, R2, c[0x0][0x168], R16 ; /* 0x00005a0002127a25 */
/* 0x004fc800078e0210 */
/*0ba0*/ FMUL R22, R12, 100000 ; /* 0x47c350000c167820 */
/* 0x008fe40000400000 */
/*0bb0*/ IMAD.WIDE R12, R2.reuse, c[0x0][0x168], R14 ; /* 0x00005a00020c7a25 */
/* 0x040fe400078e020e */
/*0bc0*/ F2I.TRUNC.NTZ R25, R22 ; /* 0x0000001600197305 */
/* 0x000ea6000020f100 */
/*0bd0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0043e8000c101904 */
/*0be0*/ LDG.E R7, [R18.64] ; /* 0x0000000412077981 */
/* 0x001ea2000c1e1900 */
/*0bf0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe20007ffe0ff */
/*0c00*/ IMAD.WIDE R20, R2, c[0x0][0x168], R12 ; /* 0x00005a0002147a25 */
/* 0x000fe200078e020c */
/*0c10*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc40007ffe0ff */
/*0c20*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0c30*/ IMAD.WIDE R10, R2, c[0x0][0x168], R18 ; /* 0x00005a00020a7a25 */
/* 0x000fc800078e0212 */
/*0c40*/ IMAD.WIDE R8, R2, c[0x0][0x168], R20 ; /* 0x00005a0002087a25 */
/* 0x000fc800078e0214 */
/*0c50*/ FMUL R7, R7, 100000 ; /* 0x47c3500007077820 */
/* 0x004fcc0000400000 */
/*0c60*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000020f100 */
/*0c70*/ STG.E [R20.64], R7 ; /* 0x0000000714007986 */
/* 0x0013e2000c101904 */
/*0c80*/ @P1 BRA 0x650 ; /* 0xfffff9c000001947 */
/* 0x000fea000383ffff */
/*0c90*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0ca0*/ @!P1 BRA 0xfe0 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*0cb0*/ LDG.E R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x002ea2000c1e1900 */
/*0cc0*/ IMAD.WIDE R12, R2, c[0x0][0x168], R10 ; /* 0x00005a00020c7a25 */
/* 0x000fc800078e020a */
/*0cd0*/ FMUL R7, R7, 100000 ; /* 0x47c3500007077820 */
/* 0x004fcc0000400000 */
/*0ce0*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000020f100 */
/*0cf0*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0011e8000c101904 */
/*0d00*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*0d10*/ IMAD.WIDE R16, R2, c[0x0][0x168], R12 ; /* 0x00005a0002107a25 */
/* 0x000fc800078e020c */
/*0d20*/ FMUL R18, R14, 100000 ; /* 0x47c350000e127820 */
/* 0x004fe40000400000 */
/*0d30*/ IMAD.WIDE R14, R2.reuse, c[0x0][0x168], R8 ; /* 0x00005a00020e7a25 */
/* 0x040fe400078e0208 */
/*0d40*/ F2I.TRUNC.NTZ R21, R18 ; /* 0x0000001200157305 */
/* 0x000e66000020f100 */
/*0d50*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0023e8000c101904 */
/*0d60*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ea2000c1e1900 */
/*0d70*/ IMAD.WIDE R8, R2, c[0x0][0x168], R16 ; /* 0x00005a0002087a25 */
/* 0x001fc800078e0210 */
/*0d80*/ FMUL R20, R10, 100000 ; /* 0x47c350000a147820 */
/* 0x004fe40000400000 */
/*0d90*/ IMAD.WIDE R10, R2.reuse, c[0x0][0x168], R14 ; /* 0x00005a00020a7a25 */
/* 0x040fe400078e020e */
/*0da0*/ F2I.TRUNC.NTZ R23, R20 ; /* 0x0000001400177305 */
/* 0x000e26000020f100 */
/*0db0*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0011e8000c101904 */
/*0dc0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea2000c1e1900 */
/*0dd0*/ IMAD.WIDE R18, R2, c[0x0][0x168], R10 ; /* 0x00005a0002127a25 */
/* 0x000fc800078e020a */
/*0de0*/ IMAD.WIDE R12, R2, c[0x0][0x168], R8 ; /* 0x00005a00020c7a25 */
/* 0x000fc800078e0208 */
/*0df0*/ FMUL R7, R7, 100000 ; /* 0x47c3500007077820 */
/* 0x004fcc0000400000 */
/*0e00*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000ea4000020f100 */
/*0e10*/ STG.E [R18.64], R7 ; /* 0x0000000712007986 */
/* 0x0045e8000c101904 */
/*0e20*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x002ee2000c1e1900 */
/*0e30*/ IMAD.WIDE R10, R2, c[0x0][0x168], R12 ; /* 0x00005a00020a7a25 */
/* 0x001fc800078e020c */
/*0e40*/ FMUL R20, R14, 100000 ; /* 0x47c350000e147820 */
/* 0x008fe40000400000 */
/*0e50*/ IMAD.WIDE R14, R2.reuse, c[0x0][0x168], R18 ; /* 0x00005a00020e7a25 */
/* 0x040fe400078e0212 */
/*0e60*/ F2I.TRUNC.NTZ R21, R20 ; /* 0x0000001400157305 */
/* 0x000e26000020f100 */
/*0e70*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0011e8000c101904 */
/*0e80*/ LDG.E R8, [R10.64] ; /* 0x000000040a087981 */
/* 0x000ee2000c1e1900 */
/*0e90*/ IMAD.WIDE R16, R2, c[0x0][0x168], R10 ; /* 0x00005a0002107a25 */
/* 0x000fc800078e020a */
/*0ea0*/ FMUL R22, R8, 100000 ; /* 0x47c3500008167820 */
/* 0x008fe40000400000 */
/*0eb0*/ IMAD.WIDE R8, R2.reuse, c[0x0][0x168], R14 ; /* 0x00005a0002087a25 */
/* 0x040fe400078e020e */
/*0ec0*/ F2I.TRUNC.NTZ R23, R22 ; /* 0x0000001600177305 */
/* 0x000e66000020f100 */
/*0ed0*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0023e8000c101904 */
/*0ee0*/ LDG.E R7, [R16.64] ; /* 0x0000000410077981 */
/* 0x004ea2000c1e1900 */
/*0ef0*/ IMAD.WIDE R12, R2, c[0x0][0x168], R8 ; /* 0x00005a00020c7a25 */
/* 0x000fc800078e0208 */
/*0f00*/ IMAD.WIDE R14, R2, c[0x0][0x168], R16 ; /* 0x00005a00020e7a25 */
/* 0x001fc800078e0210 */
/*0f10*/ FMUL R7, R7, 100000 ; /* 0x47c3500007077820 */
/* 0x004fcc0000400000 */
/*0f20*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000020f100 */
/*0f30*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x0011e8000c101904 */
/*0f40*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0f50*/ IMAD.WIDE R18, R2, c[0x0][0x168], R12 ; /* 0x00005a0002127a25 */
/* 0x000fe200078e020c */
/*0f60*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0f70*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fc40007ffe0ff */
/*0f80*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*0f90*/ IMAD.WIDE R8, R2, c[0x0][0x168], R18 ; /* 0x00005a0002087a25 */
/* 0x002fc800078e0212 */
/*0fa0*/ FMUL R20, R10, 100000 ; /* 0x47c350000a147820 */
/* 0x004fe40000400000 */
/*0fb0*/ IMAD.WIDE R10, R2, c[0x0][0x168], R14 ; /* 0x00005a00020a7a25 */
/* 0x000fe400078e020e */
/*0fc0*/ F2I.TRUNC.NTZ R21, R20 ; /* 0x0000001400157305 */
/* 0x000e64000020f100 */
/*0fd0*/ STG.E [R18.64], R21 ; /* 0x0000001512007986 */
/* 0x0021e6000c101904 */
/*0fe0*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0ff0*/ @!P0 BRA 0x11c0 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*1000*/ LDG.E R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x003ea2000c1e1900 */
/*1010*/ IMAD.WIDE R12, R2, c[0x0][0x168], R10 ; /* 0x00005a00020c7a25 */
/* 0x000fc800078e020a */
/*1020*/ FMUL R7, R7, 100000 ; /* 0x47c3500007077820 */
/* 0x004fcc0000400000 */
/*1030*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000020f100 */
/*1040*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0011e8000c101904 */
/*1050*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*1060*/ IMAD.WIDE R16, R2, c[0x0][0x168], R12 ; /* 0x00005a0002107a25 */
/* 0x000fc800078e020c */
/*1070*/ FMUL R22, R14, 100000 ; /* 0x47c350000e167820 */
/* 0x004fe40000400000 */
/*1080*/ IMAD.WIDE R14, R2.reuse, c[0x0][0x168], R8 ; /* 0x00005a00020e7a25 */
/* 0x040fe400078e0208 */
/*1090*/ F2I.TRUNC.NTZ R23, R22 ; /* 0x0000001600177305 */
/* 0x000e66000020f100 */
/*10a0*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0023e8000c101904 */
/*10b0*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ea2000c1e1900 */
/*10c0*/ IMAD.WIDE R18, R2, c[0x0][0x168], R14 ; /* 0x00005a0002127a25 */
/* 0x000fc800078e020e */
/*10d0*/ IMAD.WIDE R20, R2, c[0x0][0x168], R16 ; /* 0x00005a0002147a25 */
/* 0x000fc800078e0210 */
/*10e0*/ FMUL R10, R10, 100000 ; /* 0x47c350000a0a7820 */
/* 0x004fc80000400000 */
/*10f0*/ F2I.TRUNC.NTZ R25, R10 ; /* 0x0000000a00197305 */
/* 0x000ea4000020f100 */
/*1100*/ STG.E [R18.64], R25 ; /* 0x0000001912007986 */
/* 0x0043e8000c101904 */
/*1110*/ LDG.E R7, [R20.64] ; /* 0x0000000414077981 */
/* 0x001ea2000c1e1900 */
/*1120*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*1130*/ IMAD.WIDE R12, R2, c[0x0][0x168], R18 ; /* 0x00005a00020c7a25 */
/* 0x000fe200078e0212 */
/*1140*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*1150*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*1160*/ IMAD.WIDE R10, R2, c[0x0][0x168], R20 ; /* 0x00005a00020a7a25 */
/* 0x000fc800078e0214 */
/*1170*/ IMAD.WIDE R8, R2, c[0x0][0x168], R12 ; /* 0x00005a0002087a25 */
/* 0x000fc800078e020c */
/*1180*/ FMUL R7, R7, 100000 ; /* 0x47c3500007077820 */
/* 0x004fcc0000400000 */
/*1190*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000020f100 */
/*11a0*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x0013e4000c101904 */
/*11b0*/ @P0 BRA 0x1000 ; /* 0xfffffe4000000947 */
/* 0x002fea000383ffff */
/*11c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*11d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*11e0*/ IMAD R3, R6, c[0x0][0x168], R3 ; /* 0x00005a0006037a24 */
/* 0x000fc800078e0203 */
/*11f0*/ IMAD R3, R0, c[0x0][0x160], R3 ; /* 0x0000580000037a24 */
/* 0x000fc800078e0203 */
/*1200*/ IMAD.WIDE R6, R3, R2, c[0x0][0x188] ; /* 0x0000620003067625 */
/* 0x003fc800078e0202 */
/*1210*/ IMAD.WIDE R8, R3, R2, c[0x0][0x180] ; /* 0x0000600003087625 */
/* 0x000fca00078e0202 */
/*1220*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0000a2000c1e1900 */
/*1230*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*1240*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*1250*/ IMAD.WIDE R8, R2, c[0x0][0x168], R8 ; /* 0x00005a0002087a25 */
/* 0x001fc800078e0208 */
/*1260*/ FMUL R0, R0, 100000 ; /* 0x47c3500000007820 */
/* 0x004fc80000400000 */
/*1270*/ F2I.TRUNC.NTZ R3, R0 ; /* 0x0000000000037305 */
/* 0x000e24000020f100 */
/*1280*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0011e4000c101904 */
/*1290*/ IMAD.WIDE R6, R2, c[0x0][0x168], R6 ; /* 0x00005a0002067a25 */
/* 0x001fe200078e0206 */
/*12a0*/ @P0 BRA 0x1220 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*12b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*12c0*/ BRA 0x12c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void assignInitialClusters_64(int width, int height, int nPixels, int clusterCount, int* cluster, int filterCount, float* responses, int* intResponses) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
int pixel = y * width + x;
if ((x < width) && (y < height)) {
int xBlock = x / ((width - 1) / 8 + 1);
int yBlock = y / ((height - 1) / 8 + 1);
int assignedCluster = yBlock * 8 + xBlock;
cluster[y * width + x] = assignedCluster;
for(int i = 0; i < filterCount; i++) {
int index = pixel + i * nPixels;
int response = (int)(INTCONFACTOR * responses[index]);
intResponses[index] = response;
}
}
} | .file "tmpxft_0017b8ca_00000000-6_assignInitialClusters_64.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z24assignInitialClusters_64iiiiPiiPfS_iiiiPiiPfS_
.type _Z53__device_stub__Z24assignInitialClusters_64iiiiPiiPfS_iiiiPiiPfS_, @function
_Z53__device_stub__Z24assignInitialClusters_64iiiiPiiPfS_iiiiPiiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24assignInitialClusters_64iiiiPiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z24assignInitialClusters_64iiiiPiiPfS_iiiiPiiPfS_, .-_Z53__device_stub__Z24assignInitialClusters_64iiiiPiiPfS_iiiiPiiPfS_
.globl _Z24assignInitialClusters_64iiiiPiiPfS_
.type _Z24assignInitialClusters_64iiiiPiiPfS_, @function
_Z24assignInitialClusters_64iiiiPiiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z53__device_stub__Z24assignInitialClusters_64iiiiPiiPfS_iiiiPiiPfS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24assignInitialClusters_64iiiiPiiPfS_, .-_Z24assignInitialClusters_64iiiiPiiPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24assignInitialClusters_64iiiiPiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24assignInitialClusters_64iiiiPiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void assignInitialClusters_64(int width, int height, int nPixels, int clusterCount, int* cluster, int filterCount, float* responses, int* intResponses) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
int pixel = y * width + x;
if ((x < width) && (y < height)) {
int xBlock = x / ((width - 1) / 8 + 1);
int yBlock = y / ((height - 1) / 8 + 1);
int assignedCluster = yBlock * 8 + xBlock;
cluster[y * width + x] = assignedCluster;
for(int i = 0; i < filterCount; i++) {
int index = pixel + i * nPixels;
int response = (int)(INTCONFACTOR * responses[index]);
intResponses[index] = response;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void assignInitialClusters_64(int width, int height, int nPixels, int clusterCount, int* cluster, int filterCount, float* responses, int* intResponses) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
int pixel = y * width + x;
if ((x < width) && (y < height)) {
int xBlock = x / ((width - 1) / 8 + 1);
int yBlock = y / ((height - 1) / 8 + 1);
int assignedCluster = yBlock * 8 + xBlock;
cluster[y * width + x] = assignedCluster;
for(int i = 0; i < filterCount; i++) {
int index = pixel + i * nPixels;
int response = (int)(INTCONFACTOR * responses[index]);
intResponses[index] = response;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void assignInitialClusters_64(int width, int height, int nPixels, int clusterCount, int* cluster, int filterCount, float* responses, int* intResponses) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
int pixel = y * width + x;
if ((x < width) && (y < height)) {
int xBlock = x / ((width - 1) / 8 + 1);
int yBlock = y / ((height - 1) / 8 + 1);
int assignedCluster = yBlock * 8 + xBlock;
cluster[y * width + x] = assignedCluster;
for(int i = 0; i < filterCount; i++) {
int index = pixel + i * nPixels;
int response = (int)(INTCONFACTOR * responses[index]);
intResponses[index] = response;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24assignInitialClusters_64iiiiPiiPfS_
.globl _Z24assignInitialClusters_64iiiiPiiPfS_
.p2align 8
.type _Z24assignInitialClusters_64iiiiPiiPfS_,@function
_Z24assignInitialClusters_64iiiiPiiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_add_i32 s2, s4, -1
s_add_i32 s5, s5, -1
s_ashr_i32 s3, s2, 31
s_ashr_i32 s6, s5, 31
s_lshr_b32 s3, s3, 29
v_ashrrev_i32_e32 v6, 31, v0
s_add_i32 s2, s2, s3
s_lshr_b32 s3, s6, 29
s_ashr_i32 s2, s2, 3
s_add_i32 s5, s5, s3
s_add_i32 s2, s2, 1
s_ashr_i32 s3, s5, 3
s_ashr_i32 s5, s2, 31
s_add_i32 s3, s3, 1
s_add_i32 s2, s2, s5
s_ashr_i32 s8, s3, 31
s_xor_b32 s9, s2, s5
s_add_i32 s3, s3, s8
v_cvt_f32_u32_e32 v2, s9
s_xor_b32 s3, s3, s8
s_sub_i32 s2, 0, s9
v_cvt_f32_u32_e32 v3, s3
v_add_nc_u32_e32 v8, v0, v6
v_rcp_iflag_f32_e32 v2, v2
v_ashrrev_i32_e32 v7, 31, v1
s_load_b64 s[6:7], s[0:1], 0x10
v_rcp_iflag_f32_e32 v3, v3
v_xor_b32_e32 v8, v8, v6
v_xor_b32_e32 v6, s5, v6
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v4, s2, v2
s_sub_i32 s2, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v5, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v4, v2, v4
v_mul_hi_u32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v8, v2
v_mul_lo_u32 v2, v5, s9
v_add_nc_u32_e32 v11, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v8, v2
v_cmp_le_u32_e32 vcc_lo, s9, v8
v_add_nc_u32_e32 v9, v1, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v9, v7
v_xor_b32_e32 v7, s8, v7
v_mul_hi_u32 v9, v4, v3
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_cndmask_b32_e32 v3, v5, v11, vcc_lo
s_load_b32 s4, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v10, v9, s3
v_add_nc_u32_e32 v1, 1, v9
v_sub_nc_u32_e32 v0, v4, v10
v_subrev_nc_u32_e32 v4, s9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s3, v0
v_cndmask_b32_e32 v4, v8, v4, vcc_lo
v_cmp_le_u32_e64 s2, s3, v0
v_add_nc_u32_e32 v8, 1, v3
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
v_cmp_le_u32_e32 vcc_lo, s9, v4
v_cndmask_b32_e64 v1, v9, v1, s2
v_cndmask_b32_e64 v0, v0, v5, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 1, v1
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v1, v5, vcc_lo
v_xor_b32_e32 v1, v3, v6
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v0, v0, v7
v_sub_nc_u32_e32 v4, v1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v5, v0, v7
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v3, v5, 3, v4
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b32 s5, s[0:1], 0x8
s_load_b128 s[0:3], s[0:1], 0x20
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0x47c35000, v3
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v3, v3
global_store_b32 v[0:1], v3, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24assignInitialClusters_64iiiiPiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24assignInitialClusters_64iiiiPiiPfS_, .Lfunc_end0-_Z24assignInitialClusters_64iiiiPiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24assignInitialClusters_64iiiiPiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24assignInitialClusters_64iiiiPiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void assignInitialClusters_64(int width, int height, int nPixels, int clusterCount, int* cluster, int filterCount, float* responses, int* intResponses) {
int x = blockDim.x * blockIdx.x + threadIdx.x;
int y = blockDim.y * blockIdx.y + threadIdx.y;
int pixel = y * width + x;
if ((x < width) && (y < height)) {
int xBlock = x / ((width - 1) / 8 + 1);
int yBlock = y / ((height - 1) / 8 + 1);
int assignedCluster = yBlock * 8 + xBlock;
cluster[y * width + x] = assignedCluster;
for(int i = 0; i < filterCount; i++) {
int index = pixel + i * nPixels;
int response = (int)(INTCONFACTOR * responses[index]);
intResponses[index] = response;
}
}
} | .text
.file "assignInitialClusters_64.hip"
.globl _Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_ # -- Begin function _Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_
.p2align 4, 0x90
.type _Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_,@function
_Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_: # @_Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24assignInitialClusters_64iiiiPiiPfS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_, .Lfunc_end0-_Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24assignInitialClusters_64iiiiPiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24assignInitialClusters_64iiiiPiiPfS_,@object # @_Z24assignInitialClusters_64iiiiPiiPfS_
.section .rodata,"a",@progbits
.globl _Z24assignInitialClusters_64iiiiPiiPfS_
.p2align 3, 0x0
_Z24assignInitialClusters_64iiiiPiiPfS_:
.quad _Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_
.size _Z24assignInitialClusters_64iiiiPiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24assignInitialClusters_64iiiiPiiPfS_"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24assignInitialClusters_64iiiiPiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017b8ca_00000000-6_assignInitialClusters_64.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z24assignInitialClusters_64iiiiPiiPfS_iiiiPiiPfS_
.type _Z53__device_stub__Z24assignInitialClusters_64iiiiPiiPfS_iiiiPiiPfS_, @function
_Z53__device_stub__Z24assignInitialClusters_64iiiiPiiPfS_iiiiPiiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24assignInitialClusters_64iiiiPiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z53__device_stub__Z24assignInitialClusters_64iiiiPiiPfS_iiiiPiiPfS_, .-_Z53__device_stub__Z24assignInitialClusters_64iiiiPiiPfS_iiiiPiiPfS_
.globl _Z24assignInitialClusters_64iiiiPiiPfS_
.type _Z24assignInitialClusters_64iiiiPiiPfS_, @function
_Z24assignInitialClusters_64iiiiPiiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z53__device_stub__Z24assignInitialClusters_64iiiiPiiPfS_iiiiPiiPfS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24assignInitialClusters_64iiiiPiiPfS_, .-_Z24assignInitialClusters_64iiiiPiiPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24assignInitialClusters_64iiiiPiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24assignInitialClusters_64iiiiPiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "assignInitialClusters_64.hip"
.globl _Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_ # -- Begin function _Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_
.p2align 4, 0x90
.type _Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_,@function
_Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_: # @_Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24assignInitialClusters_64iiiiPiiPfS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_, .Lfunc_end0-_Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24assignInitialClusters_64iiiiPiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24assignInitialClusters_64iiiiPiiPfS_,@object # @_Z24assignInitialClusters_64iiiiPiiPfS_
.section .rodata,"a",@progbits
.globl _Z24assignInitialClusters_64iiiiPiiPfS_
.p2align 3, 0x0
_Z24assignInitialClusters_64iiiiPiiPfS_:
.quad _Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_
.size _Z24assignInitialClusters_64iiiiPiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24assignInitialClusters_64iiiiPiiPfS_"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__assignInitialClusters_64iiiiPiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24assignInitialClusters_64iiiiPiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void multiplyBy2(int *size, int *in, int *out) {
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < *size) {
out[ix] = in[ix] * 2;
}
} | code for sm_80
Function : _Z11multiplyBy2PiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x004fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0205 */
/*00e0*/ SHF.L.U32 R7, R2, 0x1, RZ ; /* 0x0000000102077819 */
/* 0x004fca00000006ff */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void multiplyBy2(int *size, int *in, int *out) {
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < *size) {
out[ix] = in[ix] * 2;
}
} | .file "tmpxft_001ae1b9_00000000-6_multiplyBy2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11multiplyBy2PiS_S_PiS_S_
.type _Z35__device_stub__Z11multiplyBy2PiS_S_PiS_S_, @function
_Z35__device_stub__Z11multiplyBy2PiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11multiplyBy2PiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11multiplyBy2PiS_S_PiS_S_, .-_Z35__device_stub__Z11multiplyBy2PiS_S_PiS_S_
.globl _Z11multiplyBy2PiS_S_
.type _Z11multiplyBy2PiS_S_, @function
_Z11multiplyBy2PiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11multiplyBy2PiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11multiplyBy2PiS_S_, .-_Z11multiplyBy2PiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11multiplyBy2PiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11multiplyBy2PiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void multiplyBy2(int *size, int *in, int *out) {
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < *size) {
out[ix] = in[ix] * 2;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multiplyBy2(int *size, int *in, int *out) {
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < *size) {
out[ix] = in[ix] * 2;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multiplyBy2(int *size, int *in, int *out) {
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < *size) {
out[ix] = in[ix] * 2;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11multiplyBy2PiS_S_
.globl _Z11multiplyBy2PiS_S_
.p2align 8
.type _Z11multiplyBy2PiS_S_,@function
_Z11multiplyBy2PiS_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11multiplyBy2PiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11multiplyBy2PiS_S_, .Lfunc_end0-_Z11multiplyBy2PiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11multiplyBy2PiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11multiplyBy2PiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multiplyBy2(int *size, int *in, int *out) {
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < *size) {
out[ix] = in[ix] * 2;
}
} | .text
.file "multiplyBy2.hip"
.globl _Z26__device_stub__multiplyBy2PiS_S_ # -- Begin function _Z26__device_stub__multiplyBy2PiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__multiplyBy2PiS_S_,@function
_Z26__device_stub__multiplyBy2PiS_S_: # @_Z26__device_stub__multiplyBy2PiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11multiplyBy2PiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__multiplyBy2PiS_S_, .Lfunc_end0-_Z26__device_stub__multiplyBy2PiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11multiplyBy2PiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11multiplyBy2PiS_S_,@object # @_Z11multiplyBy2PiS_S_
.section .rodata,"a",@progbits
.globl _Z11multiplyBy2PiS_S_
.p2align 3, 0x0
_Z11multiplyBy2PiS_S_:
.quad _Z26__device_stub__multiplyBy2PiS_S_
.size _Z11multiplyBy2PiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11multiplyBy2PiS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__multiplyBy2PiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11multiplyBy2PiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11multiplyBy2PiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x004fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0205 */
/*00e0*/ SHF.L.U32 R7, R2, 0x1, RZ ; /* 0x0000000102077819 */
/* 0x004fca00000006ff */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11multiplyBy2PiS_S_
.globl _Z11multiplyBy2PiS_S_
.p2align 8
.type _Z11multiplyBy2PiS_S_,@function
_Z11multiplyBy2PiS_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11multiplyBy2PiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11multiplyBy2PiS_S_, .Lfunc_end0-_Z11multiplyBy2PiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11multiplyBy2PiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11multiplyBy2PiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ae1b9_00000000-6_multiplyBy2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11multiplyBy2PiS_S_PiS_S_
.type _Z35__device_stub__Z11multiplyBy2PiS_S_PiS_S_, @function
_Z35__device_stub__Z11multiplyBy2PiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11multiplyBy2PiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11multiplyBy2PiS_S_PiS_S_, .-_Z35__device_stub__Z11multiplyBy2PiS_S_PiS_S_
.globl _Z11multiplyBy2PiS_S_
.type _Z11multiplyBy2PiS_S_, @function
_Z11multiplyBy2PiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11multiplyBy2PiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11multiplyBy2PiS_S_, .-_Z11multiplyBy2PiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11multiplyBy2PiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11multiplyBy2PiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multiplyBy2.hip"
.globl _Z26__device_stub__multiplyBy2PiS_S_ # -- Begin function _Z26__device_stub__multiplyBy2PiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__multiplyBy2PiS_S_,@function
_Z26__device_stub__multiplyBy2PiS_S_: # @_Z26__device_stub__multiplyBy2PiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11multiplyBy2PiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__multiplyBy2PiS_S_, .Lfunc_end0-_Z26__device_stub__multiplyBy2PiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11multiplyBy2PiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11multiplyBy2PiS_S_,@object # @_Z11multiplyBy2PiS_S_
.section .rodata,"a",@progbits
.globl _Z11multiplyBy2PiS_S_
.p2align 3, 0x0
_Z11multiplyBy2PiS_S_:
.quad _Z26__device_stub__multiplyBy2PiS_S_
.size _Z11multiplyBy2PiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11multiplyBy2PiS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__multiplyBy2PiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11multiplyBy2PiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <curand.h>
#include <curand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void erode(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
unsigned int dim, int m) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
int c1 = 255,c2 = 255,c3 = 255;
int end = dim/2, ini = -end;
for (int i = ini; i <= end; i++) {
ximg = x + i;
for (int j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
if(R_input[offset2]+G_input[offset2]+B_input[offset2]<c1+c2+c3)
c1 = R_input[offset2];
c2 = G_input[offset2];
c3 = B_input[offset2];
}
}
r_dataC[offset] = c1;
g_dataC[offset] = c2;
b_dataC[offset] = c3;
}
__global__ void dilate(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
unsigned int dim, int m) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
int c1 = 0,c2 = 0,c3 = 0;
int end = dim/2, ini = -end;
for (int i = ini; i <= end; i++) {
ximg = x + i;
for (int j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
if(R_input[offset2]+G_input[offset2]+B_input[offset2]>c1+c2+c3)
c1 = R_input[offset2];
c2 = G_input[offset2];
c3 = B_input[offset2];
}
}
r_dataC[offset] = c1;
g_dataC[offset] = c2;
b_dataC[offset] = c3;
}
__global__ void median_filter(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
unsigned int dim) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0, temp;
int end = dim/2, ini = -end, k = 0, n = 0, i, j;
int hr[9];
int hg[9];
int hb[9];
for (i = ini; i <= end; i++) {
ximg = x + i;
for (j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0) {
hr[n] = R_input[offset2];
hg[n] = G_input[offset2];
hb[n] = B_input[offset2];
n++;}
k++;
}
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hr[j] < hr[i]) {
temp = hr[j];
hr[j] = hr[i];
hr[i] = temp;}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hg[j] < hg[i]) {
temp = hg[j];
hg[j] = hg[i];
hg[i] = temp;}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hb[j] < hb[i]) {
temp = hb[j];
hb[j] = hb[i];
hb[i] = temp;}
if(n%2 == 1){
temp_r = hr[(n/2)];
temp_g = hg[(n/2)];
temp_b = hb[(n/2)];
}else{
temp_r = hr[(n/2)] + hr[(n/2) - 1];
temp_g = hg[(n/2)] + hg[(n/2) - 1];
temp_b = hb[(n/2)] + hb[(n/2) - 1];}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
}
__global__ void Operador_Convolucion(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
float *mask, unsigned int dim) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0;
int end = dim/2, ini = -end, k = 0;
for (int i = ini; i <= end; i++) {
ximg = x + i;
for (int j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0) {
temp_r += R_input[offset2]*mask[k];
temp_g += G_input[offset2]*mask[k];
temp_b += B_input[offset2]*mask[k];}
k++;
}
}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
} | .file "tmpxft_000124c5_00000000-6_convolutions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2243:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2243:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z5erodePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji
.type _Z39__device_stub__Z5erodePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji, @function
_Z39__device_stub__Z5erodePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji:
.LFB2265:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z5erodePhS_S_mS_S_S_mmji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2265:
.size _Z39__device_stub__Z5erodePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji, .-_Z39__device_stub__Z5erodePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji
.globl _Z5erodePhS_S_mS_S_S_mmji
.type _Z5erodePhS_S_mS_S_S_mmji, @function
_Z5erodePhS_S_mS_S_S_mmji:
.LFB2266:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z39__device_stub__Z5erodePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2266:
.size _Z5erodePhS_S_mS_S_S_mmji, .-_Z5erodePhS_S_mS_S_S_mmji
.globl _Z40__device_stub__Z6dilatePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji
.type _Z40__device_stub__Z6dilatePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji, @function
_Z40__device_stub__Z6dilatePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji:
.LFB2267:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6dilatePhS_S_mS_S_S_mmji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2267:
.size _Z40__device_stub__Z6dilatePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji, .-_Z40__device_stub__Z6dilatePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji
.globl _Z6dilatePhS_S_mS_S_S_mmji
.type _Z6dilatePhS_S_mS_S_S_mmji, @function
_Z6dilatePhS_S_mS_S_S_mmji:
.LFB2268:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z40__device_stub__Z6dilatePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2268:
.size _Z6dilatePhS_S_mS_S_S_mmji, .-_Z6dilatePhS_S_mS_S_S_mmji
.globl _Z47__device_stub__Z13median_filterPhS_S_mS_S_S_mmjPhS_S_mS_S_S_mmj
.type _Z47__device_stub__Z13median_filterPhS_S_mS_S_S_mmjPhS_S_mS_S_S_mmj, @function
_Z47__device_stub__Z13median_filterPhS_S_mS_S_S_mmjPhS_S_mS_S_S_mmj:
.LFB2269:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13median_filterPhS_S_mS_S_S_mmj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2269:
.size _Z47__device_stub__Z13median_filterPhS_S_mS_S_S_mmjPhS_S_mS_S_S_mmj, .-_Z47__device_stub__Z13median_filterPhS_S_mS_S_S_mmjPhS_S_mS_S_S_mmj
.globl _Z13median_filterPhS_S_mS_S_S_mmj
.type _Z13median_filterPhS_S_mS_S_S_mmj, @function
_Z13median_filterPhS_S_mS_S_S_mmj:
.LFB2270:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z47__device_stub__Z13median_filterPhS_S_mS_S_S_mmjPhS_S_mS_S_S_mmj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2270:
.size _Z13median_filterPhS_S_mS_S_S_mmj, .-_Z13median_filterPhS_S_mS_S_S_mmj
.globl _Z56__device_stub__Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfjPhS_S_mS_S_S_mmPfj
.type _Z56__device_stub__Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfjPhS_S_mS_S_S_mmPfj, @function
_Z56__device_stub__Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfjPhS_S_mS_S_S_mmPfj:
.LFB2271:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq 264(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size _Z56__device_stub__Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfjPhS_S_mS_S_S_mmPfj, .-_Z56__device_stub__Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfjPhS_S_mS_S_S_mmPfj
.globl _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.type _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, @function
_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj:
.LFB2272:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z56__device_stub__Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfjPhS_S_mS_S_S_mmPfj
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2272:
.size _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, .-_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj"
.align 8
.LC1:
.string "_Z13median_filterPhS_S_mS_S_S_mmj"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z6dilatePhS_S_mS_S_S_mmji"
.LC3:
.string "_Z5erodePhS_S_mS_S_S_mmji"
.LC4:
.string "precalc_xorwow_matrix"
.LC5:
.string "precalc_xorwow_offset_matrix"
.LC6:
.string "mrg32k3aM1"
.LC7:
.string "mrg32k3aM2"
.LC8:
.string "mrg32k3aM1SubSeq"
.LC9:
.string "mrg32k3aM2SubSeq"
.LC10:
.string "mrg32k3aM1Seq"
.LC11:
.string "mrg32k3aM2Seq"
.LC12:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2274:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13median_filterPhS_S_mS_S_S_mmj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6dilatePhS_S_mS_S_S_mmji(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5erodePhS_S_mS_S_S_mmji(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <curand.h>
#include <curand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void erode(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
unsigned int dim, int m) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
int c1 = 255,c2 = 255,c3 = 255;
int end = dim/2, ini = -end;
for (int i = ini; i <= end; i++) {
ximg = x + i;
for (int j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
if(R_input[offset2]+G_input[offset2]+B_input[offset2]<c1+c2+c3)
c1 = R_input[offset2];
c2 = G_input[offset2];
c3 = B_input[offset2];
}
}
r_dataC[offset] = c1;
g_dataC[offset] = c2;
b_dataC[offset] = c3;
}
__global__ void dilate(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
unsigned int dim, int m) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
int c1 = 0,c2 = 0,c3 = 0;
int end = dim/2, ini = -end;
for (int i = ini; i <= end; i++) {
ximg = x + i;
for (int j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
if(R_input[offset2]+G_input[offset2]+B_input[offset2]>c1+c2+c3)
c1 = R_input[offset2];
c2 = G_input[offset2];
c3 = B_input[offset2];
}
}
r_dataC[offset] = c1;
g_dataC[offset] = c2;
b_dataC[offset] = c3;
}
__global__ void median_filter(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
unsigned int dim) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0, temp;
int end = dim/2, ini = -end, k = 0, n = 0, i, j;
int hr[9];
int hg[9];
int hb[9];
for (i = ini; i <= end; i++) {
ximg = x + i;
for (j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0) {
hr[n] = R_input[offset2];
hg[n] = G_input[offset2];
hb[n] = B_input[offset2];
n++;}
k++;
}
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hr[j] < hr[i]) {
temp = hr[j];
hr[j] = hr[i];
hr[i] = temp;}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hg[j] < hg[i]) {
temp = hg[j];
hg[j] = hg[i];
hg[i] = temp;}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hb[j] < hb[i]) {
temp = hb[j];
hb[j] = hb[i];
hb[i] = temp;}
if(n%2 == 1){
temp_r = hr[(n/2)];
temp_g = hg[(n/2)];
temp_b = hb[(n/2)];
}else{
temp_r = hr[(n/2)] + hr[(n/2) - 1];
temp_g = hg[(n/2)] + hg[(n/2) - 1];
temp_b = hb[(n/2)] + hb[(n/2) - 1];}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
}
__global__ void Operador_Convolucion(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
float *mask, unsigned int dim) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0;
int end = dim/2, ini = -end, k = 0;
for (int i = ini; i <= end; i++) {
ximg = x + i;
for (int j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0) {
temp_r += R_input[offset2]*mask[k];
temp_g += G_input[offset2]*mask[k];
temp_b += B_input[offset2]*mask[k];}
k++;
}
}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
} | #include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void erode(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
unsigned int dim, int m) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
int c1 = 255,c2 = 255,c3 = 255;
int end = dim/2, ini = -end;
for (int i = ini; i <= end; i++) {
ximg = x + i;
for (int j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
if(R_input[offset2]+G_input[offset2]+B_input[offset2]<c1+c2+c3)
c1 = R_input[offset2];
c2 = G_input[offset2];
c3 = B_input[offset2];
}
}
r_dataC[offset] = c1;
g_dataC[offset] = c2;
b_dataC[offset] = c3;
}
__global__ void dilate(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
unsigned int dim, int m) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
int c1 = 0,c2 = 0,c3 = 0;
int end = dim/2, ini = -end;
for (int i = ini; i <= end; i++) {
ximg = x + i;
for (int j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
if(R_input[offset2]+G_input[offset2]+B_input[offset2]>c1+c2+c3)
c1 = R_input[offset2];
c2 = G_input[offset2];
c3 = B_input[offset2];
}
}
r_dataC[offset] = c1;
g_dataC[offset] = c2;
b_dataC[offset] = c3;
}
__global__ void median_filter(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
unsigned int dim) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0, temp;
int end = dim/2, ini = -end, k = 0, n = 0, i, j;
int hr[9];
int hg[9];
int hb[9];
for (i = ini; i <= end; i++) {
ximg = x + i;
for (j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0) {
hr[n] = R_input[offset2];
hg[n] = G_input[offset2];
hb[n] = B_input[offset2];
n++;}
k++;
}
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hr[j] < hr[i]) {
temp = hr[j];
hr[j] = hr[i];
hr[i] = temp;}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hg[j] < hg[i]) {
temp = hg[j];
hg[j] = hg[i];
hg[i] = temp;}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hb[j] < hb[i]) {
temp = hb[j];
hb[j] = hb[i];
hb[i] = temp;}
if(n%2 == 1){
temp_r = hr[(n/2)];
temp_g = hg[(n/2)];
temp_b = hb[(n/2)];
}else{
temp_r = hr[(n/2)] + hr[(n/2) - 1];
temp_g = hg[(n/2)] + hg[(n/2) - 1];
temp_b = hb[(n/2)] + hb[(n/2) - 1];}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
}
__global__ void Operador_Convolucion(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
float *mask, unsigned int dim) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0;
int end = dim/2, ini = -end, k = 0;
for (int i = ini; i <= end; i++) {
ximg = x + i;
for (int j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0) {
temp_r += R_input[offset2]*mask[k];
temp_g += G_input[offset2]*mask[k];
temp_b += B_input[offset2]*mask[k];}
k++;
}
}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define DIM 1600
#define PI 3.14159265
__global__ void erode(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
unsigned int dim, int m) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
int c1 = 255,c2 = 255,c3 = 255;
int end = dim/2, ini = -end;
for (int i = ini; i <= end; i++) {
ximg = x + i;
for (int j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
if(R_input[offset2]+G_input[offset2]+B_input[offset2]<c1+c2+c3)
c1 = R_input[offset2];
c2 = G_input[offset2];
c3 = B_input[offset2];
}
}
r_dataC[offset] = c1;
g_dataC[offset] = c2;
b_dataC[offset] = c3;
}
__global__ void dilate(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
unsigned int dim, int m) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
int c1 = 0,c2 = 0,c3 = 0;
int end = dim/2, ini = -end;
for (int i = ini; i <= end; i++) {
ximg = x + i;
for (int j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0)
if(R_input[offset2]+G_input[offset2]+B_input[offset2]>c1+c2+c3)
c1 = R_input[offset2];
c2 = G_input[offset2];
c3 = B_input[offset2];
}
}
r_dataC[offset] = c1;
g_dataC[offset] = c2;
b_dataC[offset] = c3;
}
__global__ void median_filter(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
unsigned int dim) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0, temp;
int end = dim/2, ini = -end, k = 0, n = 0, i, j;
int hr[9];
int hg[9];
int hb[9];
for (i = ini; i <= end; i++) {
ximg = x + i;
for (j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0) {
hr[n] = R_input[offset2];
hg[n] = G_input[offset2];
hb[n] = B_input[offset2];
n++;}
k++;
}
}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hr[j] < hr[i]) {
temp = hr[j];
hr[j] = hr[i];
hr[i] = temp;}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hg[j] < hg[i]) {
temp = hg[j];
hg[j] = hg[i];
hg[i] = temp;}
for (i = 0; i < n; i++)
for (j= i + 1; j < n; j++)
if (hb[j] < hb[i]) {
temp = hb[j];
hb[j] = hb[i];
hb[i] = temp;}
if(n%2 == 1){
temp_r = hr[(n/2)];
temp_g = hg[(n/2)];
temp_b = hb[(n/2)];
}else{
temp_r = hr[(n/2)] + hr[(n/2) - 1];
temp_g = hg[(n/2)] + hg[(n/2) - 1];
temp_b = hb[(n/2)] + hb[(n/2) - 1];}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
}
__global__ void Operador_Convolucion(unsigned char *R_input, unsigned char *G_input,
unsigned char *B_input, size_t i_size,
unsigned char *r_dataC, unsigned char *g_dataC,
unsigned char *b_dataC, unsigned long col, unsigned long row,
float *mask, unsigned int dim) {
int x = threadIdx.x + (blockIdx.x * blockDim.x);
int y = threadIdx.y + (blockIdx.y * blockDim.y);
int offset = x + y * i_size;
int offset2, ximg, yimg;
unsigned char temp_r = 0, temp_g = 0, temp_b = 0;
int end = dim/2, ini = -end, k = 0;
for (int i = ini; i <= end; i++) {
ximg = x + i;
for (int j = ini; j <= end; j++) {
yimg = y + j;
offset2 = ximg + yimg * i_size;
if (ximg < col && yimg < row)
if (ximg > 0 && yimg > 0) {
temp_r += R_input[offset2]*mask[k];
temp_g += G_input[offset2]*mask[k];
temp_b += B_input[offset2]*mask[k];}
k++;
}
}
r_dataC[offset] = temp_r;
g_dataC[offset] = temp_g;
b_dataC[offset] = temp_b;
} | .text
.file "convolutions.hip"
.globl _Z20__device_stub__erodePhS_S_mS_S_S_mmji # -- Begin function _Z20__device_stub__erodePhS_S_mS_S_S_mmji
.p2align 4, 0x90
.type _Z20__device_stub__erodePhS_S_mS_S_S_mmji,@function
_Z20__device_stub__erodePhS_S_mS_S_S_mmji: # @_Z20__device_stub__erodePhS_S_mS_S_S_mmji
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5erodePhS_S_mS_S_S_mmji, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z20__device_stub__erodePhS_S_mS_S_S_mmji, .Lfunc_end0-_Z20__device_stub__erodePhS_S_mS_S_S_mmji
.cfi_endproc
# -- End function
.globl _Z21__device_stub__dilatePhS_S_mS_S_S_mmji # -- Begin function _Z21__device_stub__dilatePhS_S_mS_S_S_mmji
.p2align 4, 0x90
.type _Z21__device_stub__dilatePhS_S_mS_S_S_mmji,@function
_Z21__device_stub__dilatePhS_S_mS_S_S_mmji: # @_Z21__device_stub__dilatePhS_S_mS_S_S_mmji
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6dilatePhS_S_mS_S_S_mmji, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z21__device_stub__dilatePhS_S_mS_S_S_mmji, .Lfunc_end1-_Z21__device_stub__dilatePhS_S_mS_S_S_mmji
.cfi_endproc
# -- End function
.globl _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj # -- Begin function _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.p2align 4, 0x90
.type _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj,@function
_Z28__device_stub__median_filterPhS_S_mS_S_S_mmj: # @_Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13median_filterPhS_S_mS_S_S_mmj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj, .Lfunc_end2-_Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.cfi_endproc
# -- End function
.globl _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj # -- Begin function _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.p2align 4, 0x90
.type _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj,@function
_Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj: # @_Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end3:
.size _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj, .Lfunc_end3-_Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5erodePhS_S_mS_S_S_mmji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6dilatePhS_S_mS_S_S_mmji, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13median_filterPhS_S_mS_S_S_mmj, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5erodePhS_S_mS_S_S_mmji,@object # @_Z5erodePhS_S_mS_S_S_mmji
.section .rodata,"a",@progbits
.globl _Z5erodePhS_S_mS_S_S_mmji
.p2align 3, 0x0
_Z5erodePhS_S_mS_S_S_mmji:
.quad _Z20__device_stub__erodePhS_S_mS_S_S_mmji
.size _Z5erodePhS_S_mS_S_S_mmji, 8
.type _Z6dilatePhS_S_mS_S_S_mmji,@object # @_Z6dilatePhS_S_mS_S_S_mmji
.globl _Z6dilatePhS_S_mS_S_S_mmji
.p2align 3, 0x0
_Z6dilatePhS_S_mS_S_S_mmji:
.quad _Z21__device_stub__dilatePhS_S_mS_S_S_mmji
.size _Z6dilatePhS_S_mS_S_S_mmji, 8
.type _Z13median_filterPhS_S_mS_S_S_mmj,@object # @_Z13median_filterPhS_S_mS_S_S_mmj
.globl _Z13median_filterPhS_S_mS_S_S_mmj
.p2align 3, 0x0
_Z13median_filterPhS_S_mS_S_S_mmj:
.quad _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.size _Z13median_filterPhS_S_mS_S_S_mmj, 8
.type _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj,@object # @_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.globl _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.p2align 3, 0x0
_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj:
.quad _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.size _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5erodePhS_S_mS_S_S_mmji"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6dilatePhS_S_mS_S_S_mmji"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13median_filterPhS_S_mS_S_S_mmj"
.size .L__unnamed_3, 34
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj"
.size .L__unnamed_4, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__erodePhS_S_mS_S_S_mmji
.addrsig_sym _Z21__device_stub__dilatePhS_S_mS_S_S_mmji
.addrsig_sym _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.addrsig_sym _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5erodePhS_S_mS_S_S_mmji
.addrsig_sym _Z6dilatePhS_S_mS_S_S_mmji
.addrsig_sym _Z13median_filterPhS_S_mS_S_S_mmj
.addrsig_sym _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000124c5_00000000-6_convolutions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2243:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2243:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z5erodePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji
.type _Z39__device_stub__Z5erodePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji, @function
_Z39__device_stub__Z5erodePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji:
.LFB2265:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z5erodePhS_S_mS_S_S_mmji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2265:
.size _Z39__device_stub__Z5erodePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji, .-_Z39__device_stub__Z5erodePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji
.globl _Z5erodePhS_S_mS_S_S_mmji
.type _Z5erodePhS_S_mS_S_S_mmji, @function
_Z5erodePhS_S_mS_S_S_mmji:
.LFB2266:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z39__device_stub__Z5erodePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2266:
.size _Z5erodePhS_S_mS_S_S_mmji, .-_Z5erodePhS_S_mS_S_S_mmji
.globl _Z40__device_stub__Z6dilatePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji
.type _Z40__device_stub__Z6dilatePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji, @function
_Z40__device_stub__Z6dilatePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji:
.LFB2267:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6dilatePhS_S_mS_S_S_mmji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2267:
.size _Z40__device_stub__Z6dilatePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji, .-_Z40__device_stub__Z6dilatePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji
.globl _Z6dilatePhS_S_mS_S_S_mmji
.type _Z6dilatePhS_S_mS_S_S_mmji, @function
_Z6dilatePhS_S_mS_S_S_mmji:
.LFB2268:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z40__device_stub__Z6dilatePhS_S_mS_S_S_mmjiPhS_S_mS_S_S_mmji
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2268:
.size _Z6dilatePhS_S_mS_S_S_mmji, .-_Z6dilatePhS_S_mS_S_S_mmji
.globl _Z47__device_stub__Z13median_filterPhS_S_mS_S_S_mmjPhS_S_mS_S_S_mmj
.type _Z47__device_stub__Z13median_filterPhS_S_mS_S_S_mmjPhS_S_mS_S_S_mmj, @function
_Z47__device_stub__Z13median_filterPhS_S_mS_S_S_mmjPhS_S_mS_S_S_mmj:
.LFB2269:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13median_filterPhS_S_mS_S_S_mmj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2269:
.size _Z47__device_stub__Z13median_filterPhS_S_mS_S_S_mmjPhS_S_mS_S_S_mmj, .-_Z47__device_stub__Z13median_filterPhS_S_mS_S_S_mmjPhS_S_mS_S_S_mmj
.globl _Z13median_filterPhS_S_mS_S_S_mmj
.type _Z13median_filterPhS_S_mS_S_S_mmj, @function
_Z13median_filterPhS_S_mS_S_S_mmj:
.LFB2270:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z47__device_stub__Z13median_filterPhS_S_mS_S_S_mmjPhS_S_mS_S_S_mmj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2270:
.size _Z13median_filterPhS_S_mS_S_S_mmj, .-_Z13median_filterPhS_S_mS_S_S_mmj
.globl _Z56__device_stub__Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfjPhS_S_mS_S_S_mmPfj
.type _Z56__device_stub__Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfjPhS_S_mS_S_S_mmPfj, @function
_Z56__device_stub__Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfjPhS_S_mS_S_S_mmPfj:
.LFB2271:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq 264(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size _Z56__device_stub__Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfjPhS_S_mS_S_S_mmPfj, .-_Z56__device_stub__Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfjPhS_S_mS_S_S_mmPfj
.globl _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.type _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, @function
_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj:
.LFB2272:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z56__device_stub__Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfjPhS_S_mS_S_S_mmPfj
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2272:
.size _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, .-_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj"
.align 8
.LC1:
.string "_Z13median_filterPhS_S_mS_S_S_mmj"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z6dilatePhS_S_mS_S_S_mmji"
.LC3:
.string "_Z5erodePhS_S_mS_S_S_mmji"
.LC4:
.string "precalc_xorwow_matrix"
.LC5:
.string "precalc_xorwow_offset_matrix"
.LC6:
.string "mrg32k3aM1"
.LC7:
.string "mrg32k3aM2"
.LC8:
.string "mrg32k3aM1SubSeq"
.LC9:
.string "mrg32k3aM2SubSeq"
.LC10:
.string "mrg32k3aM1Seq"
.LC11:
.string "mrg32k3aM2Seq"
.LC12:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2274:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13median_filterPhS_S_mS_S_S_mmj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6dilatePhS_S_mS_S_S_mmji(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5erodePhS_S_mS_S_S_mmji(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convolutions.hip"
.globl _Z20__device_stub__erodePhS_S_mS_S_S_mmji # -- Begin function _Z20__device_stub__erodePhS_S_mS_S_S_mmji
.p2align 4, 0x90
.type _Z20__device_stub__erodePhS_S_mS_S_S_mmji,@function
_Z20__device_stub__erodePhS_S_mS_S_S_mmji: # @_Z20__device_stub__erodePhS_S_mS_S_S_mmji
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5erodePhS_S_mS_S_S_mmji, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z20__device_stub__erodePhS_S_mS_S_S_mmji, .Lfunc_end0-_Z20__device_stub__erodePhS_S_mS_S_S_mmji
.cfi_endproc
# -- End function
.globl _Z21__device_stub__dilatePhS_S_mS_S_S_mmji # -- Begin function _Z21__device_stub__dilatePhS_S_mS_S_S_mmji
.p2align 4, 0x90
.type _Z21__device_stub__dilatePhS_S_mS_S_S_mmji,@function
_Z21__device_stub__dilatePhS_S_mS_S_S_mmji: # @_Z21__device_stub__dilatePhS_S_mS_S_S_mmji
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6dilatePhS_S_mS_S_S_mmji, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z21__device_stub__dilatePhS_S_mS_S_S_mmji, .Lfunc_end1-_Z21__device_stub__dilatePhS_S_mS_S_S_mmji
.cfi_endproc
# -- End function
.globl _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj # -- Begin function _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.p2align 4, 0x90
.type _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj,@function
_Z28__device_stub__median_filterPhS_S_mS_S_S_mmj: # @_Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13median_filterPhS_S_mS_S_S_mmj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj, .Lfunc_end2-_Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.cfi_endproc
# -- End function
.globl _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj # -- Begin function _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.p2align 4, 0x90
.type _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj,@function
_Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj: # @_Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end3:
.size _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj, .Lfunc_end3-_Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5erodePhS_S_mS_S_S_mmji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6dilatePhS_S_mS_S_S_mmji, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13median_filterPhS_S_mS_S_S_mmj, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5erodePhS_S_mS_S_S_mmji,@object # @_Z5erodePhS_S_mS_S_S_mmji
.section .rodata,"a",@progbits
.globl _Z5erodePhS_S_mS_S_S_mmji
.p2align 3, 0x0
_Z5erodePhS_S_mS_S_S_mmji:
.quad _Z20__device_stub__erodePhS_S_mS_S_S_mmji
.size _Z5erodePhS_S_mS_S_S_mmji, 8
.type _Z6dilatePhS_S_mS_S_S_mmji,@object # @_Z6dilatePhS_S_mS_S_S_mmji
.globl _Z6dilatePhS_S_mS_S_S_mmji
.p2align 3, 0x0
_Z6dilatePhS_S_mS_S_S_mmji:
.quad _Z21__device_stub__dilatePhS_S_mS_S_S_mmji
.size _Z6dilatePhS_S_mS_S_S_mmji, 8
.type _Z13median_filterPhS_S_mS_S_S_mmj,@object # @_Z13median_filterPhS_S_mS_S_S_mmj
.globl _Z13median_filterPhS_S_mS_S_S_mmj
.p2align 3, 0x0
_Z13median_filterPhS_S_mS_S_S_mmj:
.quad _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.size _Z13median_filterPhS_S_mS_S_S_mmj, 8
.type _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj,@object # @_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.globl _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.p2align 3, 0x0
_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj:
.quad _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.size _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5erodePhS_S_mS_S_S_mmji"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6dilatePhS_S_mS_S_S_mmji"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13median_filterPhS_S_mS_S_S_mmj"
.size .L__unnamed_3, 34
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj"
.size .L__unnamed_4, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__erodePhS_S_mS_S_S_mmji
.addrsig_sym _Z21__device_stub__dilatePhS_S_mS_S_S_mmji
.addrsig_sym _Z28__device_stub__median_filterPhS_S_mS_S_S_mmj
.addrsig_sym _Z35__device_stub__Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5erodePhS_S_mS_S_S_mmji
.addrsig_sym _Z6dilatePhS_S_mS_S_S_mmji
.addrsig_sym _Z13median_filterPhS_S_mS_S_S_mmj
.addrsig_sym _Z20Operador_ConvolucionPhS_S_mS_S_S_mmPfj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //=============================================================================================
// Name : thread2d.cu
// Author : Jose Refojo
// Version : 29-06-2012
// Creation date : 18-06-2010
// Copyright : Copyright belongs to Trinity Centre for High Performance Computing
// Description : This program will initialize a number of arrays,
// then it will grab data from each thread (such as thread position inside the block and block),
// save it, send it back into the main memory, and print it
//=============================================================================================
#include "stdio.h"
__global__ void scanTheadInformationGPU(int *threadXIdsGPU,int *threadYIdsGPU,int *blockXIdsGPU,int *blockYIdsGPU,int N,int M) {
int idx=blockIdx.x*blockDim.x+threadIdx.x;
int idy=blockIdx.y*blockDim.y+threadIdx.y;
if ( idx < N ) {
if ( idy < M ) {
threadXIdsGPU[idx+idy*N]=threadIdx.x;
threadYIdsGPU[idx+idy*N]=threadIdx.y;
blockXIdsGPU[idx+idy*N]=blockIdx.x;
blockYIdsGPU[idx+idy*N]=blockIdx.y;
}
}
}
int main() {
// pointers to host memory matrices
int **threadXIds, **threadYIds;
int *threadXIds1d = NULL;
int *threadYIds1d = NULL;
int **blockXIds, **blockYIds;
int *blockXIds1d = NULL;
int *blockYIds1d = NULL;
// pointers to device memory matrices
int *threadXIdsGPU, *threadYIdsGPU;
int *blockXIdsGPU, *blockYIdsGPU;
// N and M are the total size that we want, N is number of rows and M is number of columns
int N=3,M=3;
int i,j;
// Allocate arrays threadIds and blockIds on host
// threadIds
// threadXIds is the pointer to all the array malloced in one dimension
threadXIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
threadYIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
// thread*Ids will be just pointers to the one dimension array
threadXIds = (int**) malloc((N)*sizeof(int*));
threadYIds = (int**) malloc((N)*sizeof(int*));
for (i=0;i<N;i++) {
threadXIds[i]=(&(threadXIds1d[i*M]));
threadYIds[i]=(&(threadYIds1d[i*M]));
}
// blockIds
// blockIds is the pointer to all the array malloced in one dimension
blockXIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
blockYIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
// block*Ids will be just pointers to the one dimension array
blockXIds = (int**) malloc((N)*sizeof(int*));
blockYIds = (int**) malloc((N)*sizeof(int*));
for (i=0;i<N;i++) {
blockXIds[i]=(&(blockXIds1d[i*M]));
blockYIds[i]=(&(blockYIds1d[i*M]));
}
// Allocate arrays threadIdsGPU and blockIdsGPU on device
cudaMalloc ((void **) &threadXIdsGPU, sizeof(int)*N*M);
cudaMalloc ((void **) &threadYIdsGPU, sizeof(int)*N*M);
cudaMalloc ((void **) &blockXIdsGPU, sizeof(int)*N*M);
cudaMalloc ((void **) &blockYIdsGPU, sizeof(int)*N*M);
/*
// Copy data from host memory to device memory (not needed)
cudaMemcpy(threadXIdsGPU, threadXIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(threadYIdsGPU, threadYIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(blockXIdsGPU, blockXIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(blockYIdsGPU, blockYIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
*/
// Compute the execution configuration
int block_size=2;
dim3 dimBlock(block_size,block_size);
dim3 dimGrid ( (N/dimBlock.x) + (!(N%dimBlock.x)?0:1),(M/dimBlock.y) + (!(M%dimBlock.y)?0:1) );
// Scan information from the threads
scanTheadInformationGPU<<<dimGrid,dimBlock>>>(threadXIdsGPU,threadYIdsGPU,blockXIdsGPU,blockYIdsGPU,N,M);
// Copy data from device memory to host memory
cudaMemcpy(threadXIds1d, threadXIdsGPU, sizeof(int)*N*M, cudaMemcpyDeviceToHost);
cudaMemcpy(threadYIds1d, threadYIdsGPU, sizeof(int)*N*M, cudaMemcpyDeviceToHost);
cudaMemcpy(blockXIds1d, blockXIdsGPU, sizeof(int)*N*M, cudaMemcpyDeviceToHost);
cudaMemcpy(blockYIds1d, blockYIdsGPU, sizeof(int)*N*M, cudaMemcpyDeviceToHost);
// Print all the data about the threads
printf(" dimGrid = %d %d\n",dimGrid.x,dimGrid.y);
for (i=0; i<N; i++) {
for (j=0; j<M; j++) {
printf(" threadIds[%d][%d]= %d , %d\n",i,j,threadXIds[i][j],threadYIds[i][j]);
}
}
for (i=0; i<N; i++) {
for (j=0; j<M; j++) {
printf(" blockIds[%d][%d]= %d , %d\n",i,j,blockXIds[i][j],blockYIds[i][j]);
}
}
// Free the memory
free(threadXIds);
free(threadXIds1d);
free(threadYIds);
free(threadYIds1d);
free(blockXIds);
free(blockXIds1d);
free(blockYIds);
free(blockYIds1d);
cudaFree(threadXIdsGPU);
cudaFree(threadYIdsGPU);
cudaFree(blockXIdsGPU);
cudaFree(blockYIdsGPU);
} | code for sm_80
Function : _Z23scanTheadInformationGPUPiS_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000e280000002600 */
/*0020*/ S2R R12, SR_TID.Y ; /* 0x00000000000c7919 */
/* 0x000e280000002200 */
/*0030*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e680000002500 */
/*0040*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R13, c[0x0][0x4], R12 ; /* 0x000001000d037a24 */
/* 0x001fca00078e020c */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x184], PT ; /* 0x0000610003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R11, c[0x0][0x0], R10 ; /* 0x000000000b007a24 */
/* 0x002fca00078e020a */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x180], P0 ; /* 0x0000600000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x180], R0 ; /* 0x0000600003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe200078e0209 */
/*00f0*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe6000c101904 */
/*0100*/ IMAD.WIDE R6, R0.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x0c0fe200078e0209 */
/*0110*/ STG.E [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x000fe6000c101904 */
/*0120*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fe200078e0209 */
/*0130*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0140*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //=============================================================================================
// Name : thread2d.cu
// Author : Jose Refojo
// Version : 29-06-2012
// Creation date : 18-06-2010
// Copyright : Copyright belongs to Trinity Centre for High Performance Computing
// Description : This program will initialize a number of arrays,
// then it will grab data from each thread (such as thread position inside the block and block),
// save it, send it back into the main memory, and print it
//=============================================================================================
#include "stdio.h"
__global__ void scanTheadInformationGPU(int *threadXIdsGPU,int *threadYIdsGPU,int *blockXIdsGPU,int *blockYIdsGPU,int N,int M) {
int idx=blockIdx.x*blockDim.x+threadIdx.x;
int idy=blockIdx.y*blockDim.y+threadIdx.y;
if ( idx < N ) {
if ( idy < M ) {
threadXIdsGPU[idx+idy*N]=threadIdx.x;
threadYIdsGPU[idx+idy*N]=threadIdx.y;
blockXIdsGPU[idx+idy*N]=blockIdx.x;
blockYIdsGPU[idx+idy*N]=blockIdx.y;
}
}
}
int main() {
// pointers to host memory matrices
int **threadXIds, **threadYIds;
int *threadXIds1d = NULL;
int *threadYIds1d = NULL;
int **blockXIds, **blockYIds;
int *blockXIds1d = NULL;
int *blockYIds1d = NULL;
// pointers to device memory matrices
int *threadXIdsGPU, *threadYIdsGPU;
int *blockXIdsGPU, *blockYIdsGPU;
// N and M are the total size that we want, N is number of rows and M is number of columns
int N=3,M=3;
int i,j;
// Allocate arrays threadIds and blockIds on host
// threadIds
// threadXIds is the pointer to all the array malloced in one dimension
threadXIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
threadYIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
// thread*Ids will be just pointers to the one dimension array
threadXIds = (int**) malloc((N)*sizeof(int*));
threadYIds = (int**) malloc((N)*sizeof(int*));
for (i=0;i<N;i++) {
threadXIds[i]=(&(threadXIds1d[i*M]));
threadYIds[i]=(&(threadYIds1d[i*M]));
}
// blockIds
// blockIds is the pointer to all the array malloced in one dimension
blockXIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
blockYIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
// block*Ids will be just pointers to the one dimension array
blockXIds = (int**) malloc((N)*sizeof(int*));
blockYIds = (int**) malloc((N)*sizeof(int*));
for (i=0;i<N;i++) {
blockXIds[i]=(&(blockXIds1d[i*M]));
blockYIds[i]=(&(blockYIds1d[i*M]));
}
// Allocate arrays threadIdsGPU and blockIdsGPU on device
cudaMalloc ((void **) &threadXIdsGPU, sizeof(int)*N*M);
cudaMalloc ((void **) &threadYIdsGPU, sizeof(int)*N*M);
cudaMalloc ((void **) &blockXIdsGPU, sizeof(int)*N*M);
cudaMalloc ((void **) &blockYIdsGPU, sizeof(int)*N*M);
/*
// Copy data from host memory to device memory (not needed)
cudaMemcpy(threadXIdsGPU, threadXIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(threadYIdsGPU, threadYIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(blockXIdsGPU, blockXIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(blockYIdsGPU, blockYIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
*/
// Compute the execution configuration
int block_size=2;
dim3 dimBlock(block_size,block_size);
dim3 dimGrid ( (N/dimBlock.x) + (!(N%dimBlock.x)?0:1),(M/dimBlock.y) + (!(M%dimBlock.y)?0:1) );
// Scan information from the threads
scanTheadInformationGPU<<<dimGrid,dimBlock>>>(threadXIdsGPU,threadYIdsGPU,blockXIdsGPU,blockYIdsGPU,N,M);
// Copy data from device memory to host memory
cudaMemcpy(threadXIds1d, threadXIdsGPU, sizeof(int)*N*M, cudaMemcpyDeviceToHost);
cudaMemcpy(threadYIds1d, threadYIdsGPU, sizeof(int)*N*M, cudaMemcpyDeviceToHost);
cudaMemcpy(blockXIds1d, blockXIdsGPU, sizeof(int)*N*M, cudaMemcpyDeviceToHost);
cudaMemcpy(blockYIds1d, blockYIdsGPU, sizeof(int)*N*M, cudaMemcpyDeviceToHost);
// Print all the data about the threads
printf(" dimGrid = %d %d\n",dimGrid.x,dimGrid.y);
for (i=0; i<N; i++) {
for (j=0; j<M; j++) {
printf(" threadIds[%d][%d]= %d , %d\n",i,j,threadXIds[i][j],threadYIds[i][j]);
}
}
for (i=0; i<N; i++) {
for (j=0; j<M; j++) {
printf(" blockIds[%d][%d]= %d , %d\n",i,j,blockXIds[i][j],blockYIds[i][j]);
}
}
// Free the memory
free(threadXIds);
free(threadXIds1d);
free(threadYIds);
free(threadYIds1d);
free(blockXIds);
free(blockXIds1d);
free(blockYIds);
free(blockYIds1d);
cudaFree(threadXIdsGPU);
cudaFree(threadYIdsGPU);
cudaFree(blockXIdsGPU);
cudaFree(blockYIdsGPU);
} | .file "tmpxft_0017f451_00000000-6_thread2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii
.type _Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii, @function
_Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23scanTheadInformationGPUPiS_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii, .-_Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii
.globl _Z23scanTheadInformationGPUPiS_S_S_ii
.type _Z23scanTheadInformationGPUPiS_S_S_ii, @function
_Z23scanTheadInformationGPUPiS_S_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z23scanTheadInformationGPUPiS_S_S_ii, .-_Z23scanTheadInformationGPUPiS_S_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " dimGrid = %d %d\n"
.LC1:
.string " threadIds[%d][%d]= %d , %d\n"
.LC2:
.string " blockIds[%d][%d]= %d , %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $36, %edi
call malloc@PLT
movq %rax, %r13
movl $36, %edi
call malloc@PLT
movq %rax, %rbx
movl $24, %edi
call malloc@PLT
movq %rax, %r14
movl $24, %edi
call malloc@PLT
movq %rax, %rsi
movq %rax, 8(%rsp)
movq %r13, (%r14)
movq %rbx, (%rax)
leaq 12(%r13), %rax
movq %rax, 8(%r14)
leaq 12(%rbx), %rax
movq %rax, 8(%rsi)
leaq 24(%r13), %rax
movq %rax, 16(%r14)
leaq 24(%rbx), %rax
movq %rax, 16(%rsi)
movl $36, %edi
call malloc@PLT
movq %rax, %rbp
movq %rax, 16(%rsp)
movl $36, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $24, %edi
call malloc@PLT
movq %rax, %r12
movl $24, %edi
call malloc@PLT
movq %rax, %r15
movq %rbp, (%r12)
movq (%rsp), %rdi
movq %rdi, (%rax)
leaq 12(%rbp), %rax
movq %rax, 8(%r12)
leaq 12(%rdi), %rax
movq %rax, 8(%r15)
leaq 24(%rbp), %rax
movq %rax, 16(%r12)
leaq 24(%rdi), %rax
movq %rax, 16(%r15)
leaq 48(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl $1, 88(%rsp)
movl $1, 100(%rsp)
movl $2, 92(%rsp)
movl $2, 96(%rsp)
movl $2, 80(%rsp)
movl $2, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L12:
movl $2, %ecx
movl $36, %edx
movq 48(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $36, %edx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $36, %edx
movq 64(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $36, %edx
movq 72(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $2, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
movq %r13, 24(%rsp)
movq %rbx, 32(%rsp)
movq 8(%rsp), %r13
movq %r12, 40(%rsp)
jmp .L13
.L24:
movl $3, %r9d
movl $3, %r8d
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii
jmp .L12
.L25:
addq $1, %rbp
cmpq $3, %rbp
je .L19
.L13:
movl %ebp, %r12d
movl $0, %ebx
.L14:
movq 0(%r13,%rbp,8), %rdx
movq (%r14,%rbp,8), %rax
movl (%rdx,%rbx,4), %r9d
movl (%rax,%rbx,4), %r8d
movl %ebx, %ecx
movl %r12d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L14
jmp .L25
.L19:
movq 40(%rsp), %r12
movl $0, %ebp
.L15:
movl %ebp, %r13d
movl $0, %ebx
.L16:
movq (%r15,%rbp,8), %rdx
movq (%r12,%rbp,8), %rax
movl (%rdx,%rbx,4), %r9d
movl (%rax,%rbx,4), %r8d
movl %ebx, %ecx
movl %r13d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L16
addq $1, %rbp
cmpq $3, %rbp
jne .L15
movq 24(%rsp), %r13
movq 32(%rsp), %rbx
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z23scanTheadInformationGPUPiS_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z23scanTheadInformationGPUPiS_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //=============================================================================================
// Name : thread2d.cu
// Author : Jose Refojo
// Version : 29-06-2012
// Creation date : 18-06-2010
// Copyright : Copyright belongs to Trinity Centre for High Performance Computing
// Description : This program will initialize a number of arrays,
// then it will grab data from each thread (such as thread position inside the block and block),
// save it, send it back into the main memory, and print it
//=============================================================================================
#include "stdio.h"
__global__ void scanTheadInformationGPU(int *threadXIdsGPU,int *threadYIdsGPU,int *blockXIdsGPU,int *blockYIdsGPU,int N,int M) {
int idx=blockIdx.x*blockDim.x+threadIdx.x;
int idy=blockIdx.y*blockDim.y+threadIdx.y;
if ( idx < N ) {
if ( idy < M ) {
threadXIdsGPU[idx+idy*N]=threadIdx.x;
threadYIdsGPU[idx+idy*N]=threadIdx.y;
blockXIdsGPU[idx+idy*N]=blockIdx.x;
blockYIdsGPU[idx+idy*N]=blockIdx.y;
}
}
}
int main() {
// pointers to host memory matrices
int **threadXIds, **threadYIds;
int *threadXIds1d = NULL;
int *threadYIds1d = NULL;
int **blockXIds, **blockYIds;
int *blockXIds1d = NULL;
int *blockYIds1d = NULL;
// pointers to device memory matrices
int *threadXIdsGPU, *threadYIdsGPU;
int *blockXIdsGPU, *blockYIdsGPU;
// N and M are the total size that we want, N is number of rows and M is number of columns
int N=3,M=3;
int i,j;
// Allocate arrays threadIds and blockIds on host
// threadIds
// threadXIds is the pointer to all the array malloced in one dimension
threadXIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
threadYIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
// thread*Ids will be just pointers to the one dimension array
threadXIds = (int**) malloc((N)*sizeof(int*));
threadYIds = (int**) malloc((N)*sizeof(int*));
for (i=0;i<N;i++) {
threadXIds[i]=(&(threadXIds1d[i*M]));
threadYIds[i]=(&(threadYIds1d[i*M]));
}
// blockIds
// blockIds is the pointer to all the array malloced in one dimension
blockXIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
blockYIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
// block*Ids will be just pointers to the one dimension array
blockXIds = (int**) malloc((N)*sizeof(int*));
blockYIds = (int**) malloc((N)*sizeof(int*));
for (i=0;i<N;i++) {
blockXIds[i]=(&(blockXIds1d[i*M]));
blockYIds[i]=(&(blockYIds1d[i*M]));
}
// Allocate arrays threadIdsGPU and blockIdsGPU on device
cudaMalloc ((void **) &threadXIdsGPU, sizeof(int)*N*M);
cudaMalloc ((void **) &threadYIdsGPU, sizeof(int)*N*M);
cudaMalloc ((void **) &blockXIdsGPU, sizeof(int)*N*M);
cudaMalloc ((void **) &blockYIdsGPU, sizeof(int)*N*M);
/*
// Copy data from host memory to device memory (not needed)
cudaMemcpy(threadXIdsGPU, threadXIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(threadYIdsGPU, threadYIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(blockXIdsGPU, blockXIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(blockYIdsGPU, blockYIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
*/
// Compute the execution configuration
int block_size=2;
dim3 dimBlock(block_size,block_size);
dim3 dimGrid ( (N/dimBlock.x) + (!(N%dimBlock.x)?0:1),(M/dimBlock.y) + (!(M%dimBlock.y)?0:1) );
// Scan information from the threads
scanTheadInformationGPU<<<dimGrid,dimBlock>>>(threadXIdsGPU,threadYIdsGPU,blockXIdsGPU,blockYIdsGPU,N,M);
// Copy data from device memory to host memory
cudaMemcpy(threadXIds1d, threadXIdsGPU, sizeof(int)*N*M, cudaMemcpyDeviceToHost);
cudaMemcpy(threadYIds1d, threadYIdsGPU, sizeof(int)*N*M, cudaMemcpyDeviceToHost);
cudaMemcpy(blockXIds1d, blockXIdsGPU, sizeof(int)*N*M, cudaMemcpyDeviceToHost);
cudaMemcpy(blockYIds1d, blockYIdsGPU, sizeof(int)*N*M, cudaMemcpyDeviceToHost);
// Print all the data about the threads
printf(" dimGrid = %d %d\n",dimGrid.x,dimGrid.y);
for (i=0; i<N; i++) {
for (j=0; j<M; j++) {
printf(" threadIds[%d][%d]= %d , %d\n",i,j,threadXIds[i][j],threadYIds[i][j]);
}
}
for (i=0; i<N; i++) {
for (j=0; j<M; j++) {
printf(" blockIds[%d][%d]= %d , %d\n",i,j,blockXIds[i][j],blockYIds[i][j]);
}
}
// Free the memory
free(threadXIds);
free(threadXIds1d);
free(threadYIds);
free(threadYIds1d);
free(blockXIds);
free(blockXIds1d);
free(blockYIds);
free(blockYIds1d);
cudaFree(threadXIdsGPU);
cudaFree(threadYIdsGPU);
cudaFree(blockXIdsGPU);
cudaFree(blockYIdsGPU);
} | //=============================================================================================
// Name : thread2d.cu
// Author : Jose Refojo
// Version : 29-06-2012
// Creation date : 18-06-2010
// Copyright : Copyright belongs to Trinity Centre for High Performance Computing
// Description : This program will initialize a number of arrays,
// then it will grab data from each thread (such as thread position inside the block and block),
// save it, send it back into the main memory, and print it
//=============================================================================================
#include <hip/hip_runtime.h>
#include "stdio.h"
__global__ void scanTheadInformationGPU(int *threadXIdsGPU,int *threadYIdsGPU,int *blockXIdsGPU,int *blockYIdsGPU,int N,int M) {
int idx=blockIdx.x*blockDim.x+threadIdx.x;
int idy=blockIdx.y*blockDim.y+threadIdx.y;
if ( idx < N ) {
if ( idy < M ) {
threadXIdsGPU[idx+idy*N]=threadIdx.x;
threadYIdsGPU[idx+idy*N]=threadIdx.y;
blockXIdsGPU[idx+idy*N]=blockIdx.x;
blockYIdsGPU[idx+idy*N]=blockIdx.y;
}
}
}
int main() {
// pointers to host memory matrices
int **threadXIds, **threadYIds;
int *threadXIds1d = NULL;
int *threadYIds1d = NULL;
int **blockXIds, **blockYIds;
int *blockXIds1d = NULL;
int *blockYIds1d = NULL;
// pointers to device memory matrices
int *threadXIdsGPU, *threadYIdsGPU;
int *blockXIdsGPU, *blockYIdsGPU;
// N and M are the total size that we want, N is number of rows and M is number of columns
int N=3,M=3;
int i,j;
// Allocate arrays threadIds and blockIds on host
// threadIds
// threadXIds is the pointer to all the array malloced in one dimension
threadXIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
threadYIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
// thread*Ids will be just pointers to the one dimension array
threadXIds = (int**) malloc((N)*sizeof(int*));
threadYIds = (int**) malloc((N)*sizeof(int*));
for (i=0;i<N;i++) {
threadXIds[i]=(&(threadXIds1d[i*M]));
threadYIds[i]=(&(threadYIds1d[i*M]));
}
// blockIds
// blockIds is the pointer to all the array malloced in one dimension
blockXIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
blockYIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
// block*Ids will be just pointers to the one dimension array
blockXIds = (int**) malloc((N)*sizeof(int*));
blockYIds = (int**) malloc((N)*sizeof(int*));
for (i=0;i<N;i++) {
blockXIds[i]=(&(blockXIds1d[i*M]));
blockYIds[i]=(&(blockYIds1d[i*M]));
}
// Allocate arrays threadIdsGPU and blockIdsGPU on device
hipMalloc ((void **) &threadXIdsGPU, sizeof(int)*N*M);
hipMalloc ((void **) &threadYIdsGPU, sizeof(int)*N*M);
hipMalloc ((void **) &blockXIdsGPU, sizeof(int)*N*M);
hipMalloc ((void **) &blockYIdsGPU, sizeof(int)*N*M);
/*
// Copy data from host memory to device memory (not needed)
cudaMemcpy(threadXIdsGPU, threadXIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(threadYIdsGPU, threadYIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(blockXIdsGPU, blockXIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(blockYIdsGPU, blockYIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
*/
// Compute the execution configuration
int block_size=2;
dim3 dimBlock(block_size,block_size);
dim3 dimGrid ( (N/dimBlock.x) + (!(N%dimBlock.x)?0:1),(M/dimBlock.y) + (!(M%dimBlock.y)?0:1) );
// Scan information from the threads
scanTheadInformationGPU<<<dimGrid,dimBlock>>>(threadXIdsGPU,threadYIdsGPU,blockXIdsGPU,blockYIdsGPU,N,M);
// Copy data from device memory to host memory
hipMemcpy(threadXIds1d, threadXIdsGPU, sizeof(int)*N*M, hipMemcpyDeviceToHost);
hipMemcpy(threadYIds1d, threadYIdsGPU, sizeof(int)*N*M, hipMemcpyDeviceToHost);
hipMemcpy(blockXIds1d, blockXIdsGPU, sizeof(int)*N*M, hipMemcpyDeviceToHost);
hipMemcpy(blockYIds1d, blockYIdsGPU, sizeof(int)*N*M, hipMemcpyDeviceToHost);
// Print all the data about the threads
printf(" dimGrid = %d %d\n",dimGrid.x,dimGrid.y);
for (i=0; i<N; i++) {
for (j=0; j<M; j++) {
printf(" threadIds[%d][%d]= %d , %d\n",i,j,threadXIds[i][j],threadYIds[i][j]);
}
}
for (i=0; i<N; i++) {
for (j=0; j<M; j++) {
printf(" blockIds[%d][%d]= %d , %d\n",i,j,blockXIds[i][j],blockYIds[i][j]);
}
}
// Free the memory
free(threadXIds);
free(threadXIds1d);
free(threadYIds);
free(threadYIds1d);
free(blockXIds);
free(blockXIds1d);
free(blockYIds);
free(blockYIds1d);
hipFree(threadXIdsGPU);
hipFree(threadYIdsGPU);
hipFree(blockXIdsGPU);
hipFree(blockYIdsGPU);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //=============================================================================================
// Name : thread2d.cu
// Author : Jose Refojo
// Version : 29-06-2012
// Creation date : 18-06-2010
// Copyright : Copyright belongs to Trinity Centre for High Performance Computing
// Description : This program will initialize a number of arrays,
// then it will grab data from each thread (such as thread position inside the block and block),
// save it, send it back into the main memory, and print it
//=============================================================================================
#include <hip/hip_runtime.h>
#include "stdio.h"
__global__ void scanTheadInformationGPU(int *threadXIdsGPU,int *threadYIdsGPU,int *blockXIdsGPU,int *blockYIdsGPU,int N,int M) {
int idx=blockIdx.x*blockDim.x+threadIdx.x;
int idy=blockIdx.y*blockDim.y+threadIdx.y;
if ( idx < N ) {
if ( idy < M ) {
threadXIdsGPU[idx+idy*N]=threadIdx.x;
threadYIdsGPU[idx+idy*N]=threadIdx.y;
blockXIdsGPU[idx+idy*N]=blockIdx.x;
blockYIdsGPU[idx+idy*N]=blockIdx.y;
}
}
}
int main() {
// pointers to host memory matrices
int **threadXIds, **threadYIds;
int *threadXIds1d = NULL;
int *threadYIds1d = NULL;
int **blockXIds, **blockYIds;
int *blockXIds1d = NULL;
int *blockYIds1d = NULL;
// pointers to device memory matrices
int *threadXIdsGPU, *threadYIdsGPU;
int *blockXIdsGPU, *blockYIdsGPU;
// N and M are the total size that we want, N is number of rows and M is number of columns
int N=3,M=3;
int i,j;
// Allocate arrays threadIds and blockIds on host
// threadIds
// threadXIds is the pointer to all the array malloced in one dimension
threadXIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
threadYIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
// thread*Ids will be just pointers to the one dimension array
threadXIds = (int**) malloc((N)*sizeof(int*));
threadYIds = (int**) malloc((N)*sizeof(int*));
for (i=0;i<N;i++) {
threadXIds[i]=(&(threadXIds1d[i*M]));
threadYIds[i]=(&(threadYIds1d[i*M]));
}
// blockIds
// blockIds is the pointer to all the array malloced in one dimension
blockXIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
blockYIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
// block*Ids will be just pointers to the one dimension array
blockXIds = (int**) malloc((N)*sizeof(int*));
blockYIds = (int**) malloc((N)*sizeof(int*));
for (i=0;i<N;i++) {
blockXIds[i]=(&(blockXIds1d[i*M]));
blockYIds[i]=(&(blockYIds1d[i*M]));
}
// Allocate arrays threadIdsGPU and blockIdsGPU on device
hipMalloc ((void **) &threadXIdsGPU, sizeof(int)*N*M);
hipMalloc ((void **) &threadYIdsGPU, sizeof(int)*N*M);
hipMalloc ((void **) &blockXIdsGPU, sizeof(int)*N*M);
hipMalloc ((void **) &blockYIdsGPU, sizeof(int)*N*M);
/*
// Copy data from host memory to device memory (not needed)
cudaMemcpy(threadXIdsGPU, threadXIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(threadYIdsGPU, threadYIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(blockXIdsGPU, blockXIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(blockYIdsGPU, blockYIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
*/
// Compute the execution configuration
int block_size=2;
dim3 dimBlock(block_size,block_size);
dim3 dimGrid ( (N/dimBlock.x) + (!(N%dimBlock.x)?0:1),(M/dimBlock.y) + (!(M%dimBlock.y)?0:1) );
// Scan information from the threads
scanTheadInformationGPU<<<dimGrid,dimBlock>>>(threadXIdsGPU,threadYIdsGPU,blockXIdsGPU,blockYIdsGPU,N,M);
// Copy data from device memory to host memory
hipMemcpy(threadXIds1d, threadXIdsGPU, sizeof(int)*N*M, hipMemcpyDeviceToHost);
hipMemcpy(threadYIds1d, threadYIdsGPU, sizeof(int)*N*M, hipMemcpyDeviceToHost);
hipMemcpy(blockXIds1d, blockXIdsGPU, sizeof(int)*N*M, hipMemcpyDeviceToHost);
hipMemcpy(blockYIds1d, blockYIdsGPU, sizeof(int)*N*M, hipMemcpyDeviceToHost);
// Print all the data about the threads
printf(" dimGrid = %d %d\n",dimGrid.x,dimGrid.y);
for (i=0; i<N; i++) {
for (j=0; j<M; j++) {
printf(" threadIds[%d][%d]= %d , %d\n",i,j,threadXIds[i][j],threadYIds[i][j]);
}
}
for (i=0; i<N; i++) {
for (j=0; j<M; j++) {
printf(" blockIds[%d][%d]= %d , %d\n",i,j,blockXIds[i][j],blockYIds[i][j]);
}
}
// Free the memory
free(threadXIds);
free(threadXIds1d);
free(threadYIds);
free(threadYIds1d);
free(blockXIds);
free(blockXIds1d);
free(blockYIds);
free(blockYIds1d);
hipFree(threadXIdsGPU);
hipFree(threadYIdsGPU);
hipFree(blockXIdsGPU);
hipFree(blockYIdsGPU);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23scanTheadInformationGPUPiS_S_S_ii
.globl _Z23scanTheadInformationGPUPiS_S_S_ii
.p2align 8
.type _Z23scanTheadInformationGPUPiS_S_S_ii,@function
_Z23scanTheadInformationGPUPiS_S_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x20
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b256 s[16:23], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3]
v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s16, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s17, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s18, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s19, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s20, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s21, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s22, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s23, v3, vcc_lo
global_store_b32 v[4:5], v1, off
global_store_b32 v[6:7], v0, off
global_store_b32 v[8:9], v10, off
global_store_b32 v[2:3], v11, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23scanTheadInformationGPUPiS_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23scanTheadInformationGPUPiS_S_S_ii, .Lfunc_end0-_Z23scanTheadInformationGPUPiS_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23scanTheadInformationGPUPiS_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z23scanTheadInformationGPUPiS_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //=============================================================================================
// Name : thread2d.cu
// Author : Jose Refojo
// Version : 29-06-2012
// Creation date : 18-06-2010
// Copyright : Copyright belongs to Trinity Centre for High Performance Computing
// Description : This program will initialize a number of arrays,
// then it will grab data from each thread (such as thread position inside the block and block),
// save it, send it back into the main memory, and print it
//=============================================================================================
#include <hip/hip_runtime.h>
#include "stdio.h"
__global__ void scanTheadInformationGPU(int *threadXIdsGPU,int *threadYIdsGPU,int *blockXIdsGPU,int *blockYIdsGPU,int N,int M) {
int idx=blockIdx.x*blockDim.x+threadIdx.x;
int idy=blockIdx.y*blockDim.y+threadIdx.y;
if ( idx < N ) {
if ( idy < M ) {
threadXIdsGPU[idx+idy*N]=threadIdx.x;
threadYIdsGPU[idx+idy*N]=threadIdx.y;
blockXIdsGPU[idx+idy*N]=blockIdx.x;
blockYIdsGPU[idx+idy*N]=blockIdx.y;
}
}
}
int main() {
// pointers to host memory matrices
int **threadXIds, **threadYIds;
int *threadXIds1d = NULL;
int *threadYIds1d = NULL;
int **blockXIds, **blockYIds;
int *blockXIds1d = NULL;
int *blockYIds1d = NULL;
// pointers to device memory matrices
int *threadXIdsGPU, *threadYIdsGPU;
int *blockXIdsGPU, *blockYIdsGPU;
// N and M are the total size that we want, N is number of rows and M is number of columns
int N=3,M=3;
int i,j;
// Allocate arrays threadIds and blockIds on host
// threadIds
// threadXIds is the pointer to all the array malloced in one dimension
threadXIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
threadYIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
// thread*Ids will be just pointers to the one dimension array
threadXIds = (int**) malloc((N)*sizeof(int*));
threadYIds = (int**) malloc((N)*sizeof(int*));
for (i=0;i<N;i++) {
threadXIds[i]=(&(threadXIds1d[i*M]));
threadYIds[i]=(&(threadYIds1d[i*M]));
}
// blockIds
// blockIds is the pointer to all the array malloced in one dimension
blockXIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
blockYIds1d = (int*) malloc( (N)*(M)*sizeof(int) );
// block*Ids will be just pointers to the one dimension array
blockXIds = (int**) malloc((N)*sizeof(int*));
blockYIds = (int**) malloc((N)*sizeof(int*));
for (i=0;i<N;i++) {
blockXIds[i]=(&(blockXIds1d[i*M]));
blockYIds[i]=(&(blockYIds1d[i*M]));
}
// Allocate arrays threadIdsGPU and blockIdsGPU on device
hipMalloc ((void **) &threadXIdsGPU, sizeof(int)*N*M);
hipMalloc ((void **) &threadYIdsGPU, sizeof(int)*N*M);
hipMalloc ((void **) &blockXIdsGPU, sizeof(int)*N*M);
hipMalloc ((void **) &blockYIdsGPU, sizeof(int)*N*M);
/*
// Copy data from host memory to device memory (not needed)
cudaMemcpy(threadXIdsGPU, threadXIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(threadYIdsGPU, threadYIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(blockXIdsGPU, blockXIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
cudaMemcpy(blockYIdsGPU, blockYIds1d, sizeof(int)*N*M, cudaMemcpyHostToDevice);
*/
// Compute the execution configuration
int block_size=2;
dim3 dimBlock(block_size,block_size);
dim3 dimGrid ( (N/dimBlock.x) + (!(N%dimBlock.x)?0:1),(M/dimBlock.y) + (!(M%dimBlock.y)?0:1) );
// Scan information from the threads
scanTheadInformationGPU<<<dimGrid,dimBlock>>>(threadXIdsGPU,threadYIdsGPU,blockXIdsGPU,blockYIdsGPU,N,M);
// Copy data from device memory to host memory
hipMemcpy(threadXIds1d, threadXIdsGPU, sizeof(int)*N*M, hipMemcpyDeviceToHost);
hipMemcpy(threadYIds1d, threadYIdsGPU, sizeof(int)*N*M, hipMemcpyDeviceToHost);
hipMemcpy(blockXIds1d, blockXIdsGPU, sizeof(int)*N*M, hipMemcpyDeviceToHost);
hipMemcpy(blockYIds1d, blockYIdsGPU, sizeof(int)*N*M, hipMemcpyDeviceToHost);
// Print all the data about the threads
printf(" dimGrid = %d %d\n",dimGrid.x,dimGrid.y);
for (i=0; i<N; i++) {
for (j=0; j<M; j++) {
printf(" threadIds[%d][%d]= %d , %d\n",i,j,threadXIds[i][j],threadYIds[i][j]);
}
}
for (i=0; i<N; i++) {
for (j=0; j<M; j++) {
printf(" blockIds[%d][%d]= %d , %d\n",i,j,blockXIds[i][j],blockYIds[i][j]);
}
}
// Free the memory
free(threadXIds);
free(threadXIds1d);
free(threadYIds);
free(threadYIds1d);
free(blockXIds);
free(blockXIds1d);
free(blockYIds);
free(blockYIds1d);
hipFree(threadXIdsGPU);
hipFree(threadYIdsGPU);
hipFree(blockXIdsGPU);
hipFree(blockYIdsGPU);
} | .text
.file "thread2d.hip"
.globl _Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii # -- Begin function _Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii
.p2align 4, 0x90
.type _Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii,@function
_Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii: # @_Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23scanTheadInformationGPUPiS_S_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii, .Lfunc_end0-_Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $36, %edi
callq malloc
movq %rax, %r12
movl $36, %edi
callq malloc
movq %rax, %r15
movl $24, %edi
callq malloc
movq %rax, %rbx
movl $24, %edi
callq malloc
xorl %esi, %esi
movq %r12, %rcx
movq %r15, %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rsi,8)
movq %rdx, (%rax,%rsi,8)
incq %rsi
addq $12, %rdx
addq $12, %rcx
cmpq $3, %rsi
jne .LBB1_1
# %bb.2:
movq %rbx, 48(%rsp) # 8-byte Spill
movq %rax, 56(%rsp) # 8-byte Spill
movl $36, %edi
callq malloc
movq %rax, %rbp
movl $36, %edi
callq malloc
movq %rax, %r13
movl $24, %edi
callq malloc
movq %rax, %r14
movl $24, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
movq %rbp, %rcx
movq %r13, %rdx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rcx, (%r14,%rax,8)
movq %rdx, (%rbx,%rax,8)
incq %rax
addq $12, %rdx
addq $12, %rcx
cmpq $3, %rax
jne .LBB1_3
# %bb.4:
leaq 32(%rsp), %rdi
movl $36, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $36, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $36, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $36, %esi
callq hipMalloc
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq %rsi, 144(%rsp)
movl $3, 44(%rsp)
movl $3, 40(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 44(%rsp), %rax
movq %rax, 208(%rsp)
leaq 40(%rsp), %rax
movq %rax, 216(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z23scanTheadInformationGPUPiS_S_S_ii, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 32(%rsp), %rsi
movl $36, %edx
movq %r12, 80(%rsp) # 8-byte Spill
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movl $36, %edx
movq %r15, 88(%rsp) # 8-byte Spill
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $36, %edx
movq %rbp, 64(%rsp) # 8-byte Spill
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $36, %edx
movq %r13, 72(%rsp) # 8-byte Spill
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl $2, %esi
movl $2, %edx
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_7: # %.preheader117
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
movq 48(%rsp), %rax # 8-byte Reload
movq (%rax,%r13,8), %r15
movq 56(%rsp), %rax # 8-byte Reload
movq (%rax,%r13,8), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%rbp,4), %ecx
movl (%r12,%rbp,4), %r8d
movl $.L.str.1, %edi
movl %r13d, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
incq %rbp
cmpq $3, %rbp
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
incq %r13
cmpq $3, %r13
jne .LBB1_7
# %bb.10: # %.preheader.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
movq (%r14,%r13,8), %r15
movq (%rbx,%r13,8), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%rbp,4), %ecx
movl (%r12,%rbp,4), %r8d
movl $.L.str.2, %edi
movl %r13d, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
incq %rbp
cmpq $3, %rbp
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
incq %r13
cmpq $3, %r13
jne .LBB1_11
# %bb.14:
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq 80(%rsp), %rdi # 8-byte Reload
callq free
movq 56(%rsp), %rdi # 8-byte Reload
callq free
movq 88(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
movq 72(%rsp), %rdi # 8-byte Reload
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23scanTheadInformationGPUPiS_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23scanTheadInformationGPUPiS_S_S_ii,@object # @_Z23scanTheadInformationGPUPiS_S_S_ii
.section .rodata,"a",@progbits
.globl _Z23scanTheadInformationGPUPiS_S_S_ii
.p2align 3, 0x0
_Z23scanTheadInformationGPUPiS_S_S_ii:
.quad _Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii
.size _Z23scanTheadInformationGPUPiS_S_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " dimGrid = %d %d\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " threadIds[%d][%d]= %d , %d\n"
.size .L.str.1, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " blockIds[%d][%d]= %d , %d\n"
.size .L.str.2, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23scanTheadInformationGPUPiS_S_S_ii"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23scanTheadInformationGPUPiS_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23scanTheadInformationGPUPiS_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000e280000002600 */
/*0020*/ S2R R12, SR_TID.Y ; /* 0x00000000000c7919 */
/* 0x000e280000002200 */
/*0030*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e680000002500 */
/*0040*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R13, c[0x0][0x4], R12 ; /* 0x000001000d037a24 */
/* 0x001fca00078e020c */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x184], PT ; /* 0x0000610003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R11, c[0x0][0x0], R10 ; /* 0x000000000b007a24 */
/* 0x002fca00078e020a */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x180], P0 ; /* 0x0000600000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x180], R0 ; /* 0x0000600003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe200078e0209 */
/*00f0*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe6000c101904 */
/*0100*/ IMAD.WIDE R6, R0.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x0c0fe200078e0209 */
/*0110*/ STG.E [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x000fe6000c101904 */
/*0120*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fe200078e0209 */
/*0130*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0140*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23scanTheadInformationGPUPiS_S_S_ii
.globl _Z23scanTheadInformationGPUPiS_S_S_ii
.p2align 8
.type _Z23scanTheadInformationGPUPiS_S_S_ii,@function
_Z23scanTheadInformationGPUPiS_S_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x20
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b256 s[16:23], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3]
v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s16, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s17, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s18, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s19, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s20, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s21, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s22, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s23, v3, vcc_lo
global_store_b32 v[4:5], v1, off
global_store_b32 v[6:7], v0, off
global_store_b32 v[8:9], v10, off
global_store_b32 v[2:3], v11, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23scanTheadInformationGPUPiS_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23scanTheadInformationGPUPiS_S_S_ii, .Lfunc_end0-_Z23scanTheadInformationGPUPiS_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23scanTheadInformationGPUPiS_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z23scanTheadInformationGPUPiS_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017f451_00000000-6_thread2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii
.type _Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii, @function
_Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23scanTheadInformationGPUPiS_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii, .-_Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii
.globl _Z23scanTheadInformationGPUPiS_S_S_ii
.type _Z23scanTheadInformationGPUPiS_S_S_ii, @function
_Z23scanTheadInformationGPUPiS_S_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z23scanTheadInformationGPUPiS_S_S_ii, .-_Z23scanTheadInformationGPUPiS_S_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " dimGrid = %d %d\n"
.LC1:
.string " threadIds[%d][%d]= %d , %d\n"
.LC2:
.string " blockIds[%d][%d]= %d , %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $36, %edi
call malloc@PLT
movq %rax, %r13
movl $36, %edi
call malloc@PLT
movq %rax, %rbx
movl $24, %edi
call malloc@PLT
movq %rax, %r14
movl $24, %edi
call malloc@PLT
movq %rax, %rsi
movq %rax, 8(%rsp)
movq %r13, (%r14)
movq %rbx, (%rax)
leaq 12(%r13), %rax
movq %rax, 8(%r14)
leaq 12(%rbx), %rax
movq %rax, 8(%rsi)
leaq 24(%r13), %rax
movq %rax, 16(%r14)
leaq 24(%rbx), %rax
movq %rax, 16(%rsi)
movl $36, %edi
call malloc@PLT
movq %rax, %rbp
movq %rax, 16(%rsp)
movl $36, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $24, %edi
call malloc@PLT
movq %rax, %r12
movl $24, %edi
call malloc@PLT
movq %rax, %r15
movq %rbp, (%r12)
movq (%rsp), %rdi
movq %rdi, (%rax)
leaq 12(%rbp), %rax
movq %rax, 8(%r12)
leaq 12(%rdi), %rax
movq %rax, 8(%r15)
leaq 24(%rbp), %rax
movq %rax, 16(%r12)
leaq 24(%rdi), %rax
movq %rax, 16(%r15)
leaq 48(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl $1, 88(%rsp)
movl $1, 100(%rsp)
movl $2, 92(%rsp)
movl $2, 96(%rsp)
movl $2, 80(%rsp)
movl $2, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L12:
movl $2, %ecx
movl $36, %edx
movq 48(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $36, %edx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $36, %edx
movq 64(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $36, %edx
movq 72(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $2, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
movq %r13, 24(%rsp)
movq %rbx, 32(%rsp)
movq 8(%rsp), %r13
movq %r12, 40(%rsp)
jmp .L13
.L24:
movl $3, %r9d
movl $3, %r8d
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z51__device_stub__Z23scanTheadInformationGPUPiS_S_S_iiPiS_S_S_ii
jmp .L12
.L25:
addq $1, %rbp
cmpq $3, %rbp
je .L19
.L13:
movl %ebp, %r12d
movl $0, %ebx
.L14:
movq 0(%r13,%rbp,8), %rdx
movq (%r14,%rbp,8), %rax
movl (%rdx,%rbx,4), %r9d
movl (%rax,%rbx,4), %r8d
movl %ebx, %ecx
movl %r12d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L14
jmp .L25
.L19:
movq 40(%rsp), %r12
movl $0, %ebp
.L15:
movl %ebp, %r13d
movl $0, %ebx
.L16:
movq (%r15,%rbp,8), %rdx
movq (%r12,%rbp,8), %rax
movl (%rdx,%rbx,4), %r9d
movl (%rax,%rbx,4), %r8d
movl %ebx, %ecx
movl %r13d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L16
addq $1, %rbp
cmpq $3, %rbp
jne .L15
movq 24(%rsp), %r13
movq 32(%rsp), %rbx
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z23scanTheadInformationGPUPiS_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z23scanTheadInformationGPUPiS_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "thread2d.hip"
.globl _Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii # -- Begin function _Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii
.p2align 4, 0x90
.type _Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii,@function
_Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii: # @_Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23scanTheadInformationGPUPiS_S_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii, .Lfunc_end0-_Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $36, %edi
callq malloc
movq %rax, %r12
movl $36, %edi
callq malloc
movq %rax, %r15
movl $24, %edi
callq malloc
movq %rax, %rbx
movl $24, %edi
callq malloc
xorl %esi, %esi
movq %r12, %rcx
movq %r15, %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rsi,8)
movq %rdx, (%rax,%rsi,8)
incq %rsi
addq $12, %rdx
addq $12, %rcx
cmpq $3, %rsi
jne .LBB1_1
# %bb.2:
movq %rbx, 48(%rsp) # 8-byte Spill
movq %rax, 56(%rsp) # 8-byte Spill
movl $36, %edi
callq malloc
movq %rax, %rbp
movl $36, %edi
callq malloc
movq %rax, %r13
movl $24, %edi
callq malloc
movq %rax, %r14
movl $24, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
movq %rbp, %rcx
movq %r13, %rdx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %rcx, (%r14,%rax,8)
movq %rdx, (%rbx,%rax,8)
incq %rax
addq $12, %rdx
addq $12, %rcx
cmpq $3, %rax
jne .LBB1_3
# %bb.4:
leaq 32(%rsp), %rdi
movl $36, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $36, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $36, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $36, %esi
callq hipMalloc
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq %rsi, 144(%rsp)
movl $3, 44(%rsp)
movl $3, 40(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 144(%rsp), %rax
movq %rax, 200(%rsp)
leaq 44(%rsp), %rax
movq %rax, 208(%rsp)
leaq 40(%rsp), %rax
movq %rax, 216(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z23scanTheadInformationGPUPiS_S_S_ii, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 32(%rsp), %rsi
movl $36, %edx
movq %r12, 80(%rsp) # 8-byte Spill
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movl $36, %edx
movq %r15, 88(%rsp) # 8-byte Spill
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $36, %edx
movq %rbp, 64(%rsp) # 8-byte Spill
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $36, %edx
movq %r13, 72(%rsp) # 8-byte Spill
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl $2, %esi
movl $2, %edx
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_7: # %.preheader117
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
movq 48(%rsp), %rax # 8-byte Reload
movq (%rax,%r13,8), %r15
movq 56(%rsp), %rax # 8-byte Reload
movq (%rax,%r13,8), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%rbp,4), %ecx
movl (%r12,%rbp,4), %r8d
movl $.L.str.1, %edi
movl %r13d, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
incq %rbp
cmpq $3, %rbp
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
incq %r13
cmpq $3, %r13
jne .LBB1_7
# %bb.10: # %.preheader.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
movq (%r14,%r13,8), %r15
movq (%rbx,%r13,8), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%rbp,4), %ecx
movl (%r12,%rbp,4), %r8d
movl $.L.str.2, %edi
movl %r13d, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
incq %rbp
cmpq $3, %rbp
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
incq %r13
cmpq $3, %r13
jne .LBB1_11
# %bb.14:
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq 80(%rsp), %rdi # 8-byte Reload
callq free
movq 56(%rsp), %rdi # 8-byte Reload
callq free
movq 88(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq 64(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
movq 72(%rsp), %rdi # 8-byte Reload
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23scanTheadInformationGPUPiS_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23scanTheadInformationGPUPiS_S_S_ii,@object # @_Z23scanTheadInformationGPUPiS_S_S_ii
.section .rodata,"a",@progbits
.globl _Z23scanTheadInformationGPUPiS_S_S_ii
.p2align 3, 0x0
_Z23scanTheadInformationGPUPiS_S_S_ii:
.quad _Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii
.size _Z23scanTheadInformationGPUPiS_S_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " dimGrid = %d %d\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " threadIds[%d][%d]= %d , %d\n"
.size .L.str.1, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " blockIds[%d][%d]= %d , %d\n"
.size .L.str.2, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23scanTheadInformationGPUPiS_S_S_ii"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__scanTheadInformationGPUPiS_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23scanTheadInformationGPUPiS_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdint>
#include <iostream>
__global__ void iota_kernel(float * input, uint64_t size) {
uint64_t thid = blockIdx.x*blockDim.x+threadIdx.x;
for (uint64_t i = thid; i < size; i += gridDim.x*blockDim.x)
input[i] = i;
}
int main () {
uint64_t size = 1UL << 20;
float * input = nullptr;
cudaMallocHost(&input, sizeof(float)*size);
iota_kernel<<<1024, 1024>>>(input, size);
cudaDeviceSynchronize();
for (uint64_t i = 0; i < 20; i++)
std::cout << input[i] << std::endl;
} | code for sm_80
Function : _Z11iota_kernelPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff067624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x001fe200078e0007 */
/*00b0*/ MOV R2, R0 ; /* 0x0000000000027202 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD R9, R6, c[0x0][0x0], RZ ; /* 0x0000000006097a24 */
/* 0x000fe200078e02ff */
/*00d0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fc600078010ff */
/*00e0*/ I2F.U64 R3, R2 ; /* 0x0000000200037312 */
/* 0x000e220000301000 */
/*00f0*/ LEA.HI.X R5, R0, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fe400000f1407 */
/*0100*/ IADD3 R0, P0, R9, R0, RZ ; /* 0x0000000009007210 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R7, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff077210 */
/* 0x000fe400007fe4ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0130*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x16c], PT, P0 ; /* 0x00005b0007007a0c */
/* 0x000fe20003f06100 */
/*0140*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0011d8000c101904 */
/*0150*/ @!P0 BRA 0xa0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdint>
#include <iostream>
__global__ void iota_kernel(float * input, uint64_t size) {
uint64_t thid = blockIdx.x*blockDim.x+threadIdx.x;
for (uint64_t i = thid; i < size; i += gridDim.x*blockDim.x)
input[i] = i;
}
int main () {
uint64_t size = 1UL << 20;
float * input = nullptr;
cudaMallocHost(&input, sizeof(float)*size);
iota_kernel<<<1024, 1024>>>(input, size);
cudaDeviceSynchronize();
for (uint64_t i = 0; i < 20; i++)
std::cout << input[i] << std::endl;
} | .file "tmpxft_000a0b89_00000000-6_uvm_minimal_example.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11iota_kernelPfmPfm
.type _Z32__device_stub__Z11iota_kernelPfmPfm, @function
_Z32__device_stub__Z11iota_kernelPfmPfm:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11iota_kernelPfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z11iota_kernelPfmPfm, .-_Z32__device_stub__Z11iota_kernelPfmPfm
.globl _Z11iota_kernelPfm
.type _Z11iota_kernelPfm, @function
_Z11iota_kernelPfm:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11iota_kernelPfmPfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z11iota_kernelPfm, .-_Z11iota_kernelPfm
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $0, %edx
movl $4194304, %esi
call cudaHostAlloc@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r12
jmp .L17
.L21:
movl $1048576, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z11iota_kernelPfmPfm
jmp .L12
.L24:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L15:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbp
cmpq $80, %rbp
je .L23
.L17:
movq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .L24
cmpb $0, 56(%r13)
je .L15
movzbl 67(%r13), %esi
jmp .L16
.L23:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11iota_kernelPfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11iota_kernelPfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdint>
#include <iostream>
__global__ void iota_kernel(float * input, uint64_t size) {
uint64_t thid = blockIdx.x*blockDim.x+threadIdx.x;
for (uint64_t i = thid; i < size; i += gridDim.x*blockDim.x)
input[i] = i;
}
int main () {
uint64_t size = 1UL << 20;
float * input = nullptr;
cudaMallocHost(&input, sizeof(float)*size);
iota_kernel<<<1024, 1024>>>(input, size);
cudaDeviceSynchronize();
for (uint64_t i = 0; i < 20; i++)
std::cout << input[i] << std::endl;
} | #include <hip/hip_runtime.h>
#include <cstdint>
#include <iostream>
__global__ void iota_kernel(float * input, uint64_t size) {
uint64_t thid = blockIdx.x*blockDim.x+threadIdx.x;
for (uint64_t i = thid; i < size; i += gridDim.x*blockDim.x)
input[i] = i;
}
int main () {
uint64_t size = 1UL << 20;
float * input = nullptr;
hipHostMalloc(&input, sizeof(float)*size, hipHostMallocDefault);
iota_kernel<<<1024, 1024>>>(input, size);
hipDeviceSynchronize();
for (uint64_t i = 0; i < 20; i++)
std::cout << input[i] << std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdint>
#include <iostream>
__global__ void iota_kernel(float * input, uint64_t size) {
uint64_t thid = blockIdx.x*blockDim.x+threadIdx.x;
for (uint64_t i = thid; i < size; i += gridDim.x*blockDim.x)
input[i] = i;
}
int main () {
uint64_t size = 1UL << 20;
float * input = nullptr;
hipHostMalloc(&input, sizeof(float)*size, hipHostMallocDefault);
iota_kernel<<<1024, 1024>>>(input, size);
hipDeviceSynchronize();
for (uint64_t i = 0; i < 20; i++)
std::cout << input[i] << std::endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11iota_kernelPfm
.globl _Z11iota_kernelPfm
.p2align 8
.type _Z11iota_kernelPfm,@function
_Z11iota_kernelPfm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s4, s[4:5], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s1, s5
.p2align 6
.LBB0_2:
v_clz_i32_u32_e32 v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v0, 32, v0
v_lshlrev_b64 v[5:6], v0, v[1:2]
v_sub_nc_u32_e32 v0, 32, v0
v_add_co_u32 v1, vcc_lo, v1, s4
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v5, 1, v5
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v5, v6, v5
s_or_b32 s1, vcc_lo, s1
v_cvt_f32_u32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ldexp_f32 v0, v5, v0
global_store_b32 v[3:4], v0, off
v_add_co_u32 v3, s0, v3, s6
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11iota_kernelPfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11iota_kernelPfm, .Lfunc_end0-_Z11iota_kernelPfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11iota_kernelPfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11iota_kernelPfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdint>
#include <iostream>
__global__ void iota_kernel(float * input, uint64_t size) {
uint64_t thid = blockIdx.x*blockDim.x+threadIdx.x;
for (uint64_t i = thid; i < size; i += gridDim.x*blockDim.x)
input[i] = i;
}
int main () {
uint64_t size = 1UL << 20;
float * input = nullptr;
hipHostMalloc(&input, sizeof(float)*size, hipHostMallocDefault);
iota_kernel<<<1024, 1024>>>(input, size);
hipDeviceSynchronize();
for (uint64_t i = 0; i < 20; i++)
std::cout << input[i] << std::endl;
} | .text
.file "uvm_minimal_example.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__iota_kernelPfm # -- Begin function _Z26__device_stub__iota_kernelPfm
.p2align 4, 0x90
.type _Z26__device_stub__iota_kernelPfm,@function
_Z26__device_stub__iota_kernelPfm: # @_Z26__device_stub__iota_kernelPfm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11iota_kernelPfm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__iota_kernelPfm, .Lfunc_end0-_Z26__device_stub__iota_kernelPfm
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostMalloc
movabsq $4294968320, %rdi # imm = 0x100000400
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq $1048576, 64(%rsp) # imm = 0x100000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11iota_kernelPfm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %r14d, %r14d
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_3 Depth=1
movq %rbx, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_3 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $20, %r14
je .LBB1_8
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_9
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_3 Depth=1
cmpb $0, 56(%rbx)
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movzbl 67(%rbx), %ecx
jmp .LBB1_7
.LBB1_8:
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11iota_kernelPfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11iota_kernelPfm,@object # @_Z11iota_kernelPfm
.section .rodata,"a",@progbits
.globl _Z11iota_kernelPfm
.p2align 3, 0x0
_Z11iota_kernelPfm:
.quad _Z26__device_stub__iota_kernelPfm
.size _Z11iota_kernelPfm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11iota_kernelPfm"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__iota_kernelPfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11iota_kernelPfm
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11iota_kernelPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff067624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x001fe200078e0007 */
/*00b0*/ MOV R2, R0 ; /* 0x0000000000027202 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD R9, R6, c[0x0][0x0], RZ ; /* 0x0000000006097a24 */
/* 0x000fe200078e02ff */
/*00d0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fc600078010ff */
/*00e0*/ I2F.U64 R3, R2 ; /* 0x0000000200037312 */
/* 0x000e220000301000 */
/*00f0*/ LEA.HI.X R5, R0, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fe400000f1407 */
/*0100*/ IADD3 R0, P0, R9, R0, RZ ; /* 0x0000000009007210 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R7, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff077210 */
/* 0x000fe400007fe4ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0130*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x16c], PT, P0 ; /* 0x00005b0007007a0c */
/* 0x000fe20003f06100 */
/*0140*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0011d8000c101904 */
/*0150*/ @!P0 BRA 0xa0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11iota_kernelPfm
.globl _Z11iota_kernelPfm
.p2align 8
.type _Z11iota_kernelPfm,@function
_Z11iota_kernelPfm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s4, s[4:5], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s1, s5
.p2align 6
.LBB0_2:
v_clz_i32_u32_e32 v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v0, 32, v0
v_lshlrev_b64 v[5:6], v0, v[1:2]
v_sub_nc_u32_e32 v0, 32, v0
v_add_co_u32 v1, vcc_lo, v1, s4
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v5, 1, v5
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_or_b32_e32 v5, v6, v5
s_or_b32 s1, vcc_lo, s1
v_cvt_f32_u32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ldexp_f32 v0, v5, v0
global_store_b32 v[3:4], v0, off
v_add_co_u32 v3, s0, v3, s6
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11iota_kernelPfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11iota_kernelPfm, .Lfunc_end0-_Z11iota_kernelPfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11iota_kernelPfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11iota_kernelPfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a0b89_00000000-6_uvm_minimal_example.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11iota_kernelPfmPfm
.type _Z32__device_stub__Z11iota_kernelPfmPfm, @function
_Z32__device_stub__Z11iota_kernelPfmPfm:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11iota_kernelPfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z11iota_kernelPfmPfm, .-_Z32__device_stub__Z11iota_kernelPfmPfm
.globl _Z11iota_kernelPfm
.type _Z11iota_kernelPfm, @function
_Z11iota_kernelPfm:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11iota_kernelPfmPfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z11iota_kernelPfm, .-_Z11iota_kernelPfm
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $0, %edx
movl $4194304, %esi
call cudaHostAlloc@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r12
jmp .L17
.L21:
movl $1048576, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z11iota_kernelPfmPfm
jmp .L12
.L24:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L15:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbp
cmpq $80, %rbp
je .L23
.L17:
movq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .L24
cmpb $0, 56(%r13)
je .L15
movzbl 67(%r13), %esi
jmp .L16
.L23:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11iota_kernelPfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11iota_kernelPfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "uvm_minimal_example.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__iota_kernelPfm # -- Begin function _Z26__device_stub__iota_kernelPfm
.p2align 4, 0x90
.type _Z26__device_stub__iota_kernelPfm,@function
_Z26__device_stub__iota_kernelPfm: # @_Z26__device_stub__iota_kernelPfm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11iota_kernelPfm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__iota_kernelPfm, .Lfunc_end0-_Z26__device_stub__iota_kernelPfm
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostMalloc
movabsq $4294968320, %rdi # imm = 0x100000400
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq $1048576, 64(%rsp) # imm = 0x100000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11iota_kernelPfm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %r14d, %r14d
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_3 Depth=1
movq %rbx, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_3 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $20, %r14
je .LBB1_8
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_9
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_3 Depth=1
cmpb $0, 56(%rbx)
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movzbl 67(%rbx), %ecx
jmp .LBB1_7
.LBB1_8:
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11iota_kernelPfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11iota_kernelPfm,@object # @_Z11iota_kernelPfm
.section .rodata,"a",@progbits
.globl _Z11iota_kernelPfm
.p2align 3, 0x0
_Z11iota_kernelPfm:
.quad _Z26__device_stub__iota_kernelPfm
.size _Z11iota_kernelPfm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11iota_kernelPfm"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__iota_kernelPfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11iota_kernelPfm
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sigmoid(float *inout, float *bias, int rows, int cols) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
if (j >= cols || i >= rows) return;
float t = inout[i * cols + j];
inout[i * cols + j] = 1 / (1 + expf(-t)) + bias[i];
} | code for sm_80
Function : _Z7sigmoidPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R2, c[0x0][0x4], R5 ; /* 0x0000010002007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R0, c[0x0][0x174], R3 ; /* 0x00005d0000037a24 */
/* 0x000fc800078e0203 */
/*00d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00e0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ HFMA2.MMA R6, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff067435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff057424 */
/* 0x000fe200078e00ff */
/*0110*/ BSSY B0, 0x260 ; /* 0x0000014000007945 */
/* 0x000fe60003800000 */
/*0120*/ FFMA.SAT R5, -R4, R5, 0.5 ; /* 0x3f00000004057423 */
/* 0x004fca0000002105 */
/*0130*/ FFMA.RM R5, R5, R6, 12582913 ; /* 0x4b40000105057423 */
/* 0x000fc80000004006 */
/*0140*/ FADD R7, R5.reuse, -12583039 ; /* 0xcb40007f05077421 */
/* 0x040fe40000000000 */
/*0150*/ IMAD.SHL.U32 R5, R5, 0x800000, RZ ; /* 0x0080000005057824 */
/* 0x000fe400078e00ff */
/*0160*/ FFMA R7, -R4, 1.4426950216293334961, -R7 ; /* 0x3fb8aa3b04077823 */
/* 0x000fc80000000907 */
/*0170*/ FFMA R7, -R4, 1.925963033500011079e-08, R7 ; /* 0x32a5706004077823 */
/* 0x000fc80000000107 */
/*0180*/ MUFU.EX2 R4, R7 ; /* 0x0000000700047308 */
/* 0x000e240000000800 */
/*0190*/ FFMA R5, R5, R4, 1 ; /* 0x3f80000005057423 */
/* 0x001fca0000000004 */
/*01a0*/ IADD3 R4, R5, 0x1800000, RZ ; /* 0x0180000005047810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000004047812 */
/* 0x000fc800078ec0ff */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ffffff, PT ; /* 0x01ffffff0400780c */
/* 0x000fda0003f04070 */
/*01d0*/ @P0 BRA 0x210 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*01e0*/ MOV R4, 0x200 ; /* 0x0000020000047802 */
/* 0x000fe40000000f00 */
/*01f0*/ CALL.REL.NOINC 0x2c0 ; /* 0x000000c000007944 */
/* 0x000fea0003c00000 */
/*0200*/ BRA 0x250 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0210*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e240000001000 */
/*0220*/ FFMA R4, R5, R6, -1 ; /* 0xbf80000005047423 */
/* 0x001fc80000000006 */
/*0230*/ FADD.FTZ R7, -R4, -RZ ; /* 0x800000ff04077221 */
/* 0x000fc80000010100 */
/*0240*/ FFMA R6, R6, R7, R6 ; /* 0x0000000706067223 */
/* 0x000fe40000000006 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0205 */
/*0280*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FADD R7, R5, R6 ; /* 0x0000000605077221 */
/* 0x006fca0000000000 */
/*02a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ SHF.L.U32 R6, R5, 0x1, RZ ; /* 0x0000000105067819 */
/* 0x000fe200000006ff */
/*02d0*/ BSSY B1, 0x5e0 ; /* 0x0000030000017945 */
/* 0x000fe60003800000 */
/*02e0*/ SHF.R.U32.HI R6, RZ, 0x18, R6 ; /* 0x00000018ff067819 */
/* 0x000fc80000011606 */
/*02f0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05070 */
/*0300*/ @P0 BRA 0x3b0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0310*/ IMAD.SHL.U32 R6, R5, 0x2, RZ ; /* 0x0000000205067824 */
/* 0x000fca00078e00ff */
/*0320*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0330*/ @P0 FFMA R7, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005070823 */
/* 0x000fe200000000ff */
/*0340*/ @!P0 MUFU.RCP R6, R5 ; /* 0x0000000500068308 */
/* 0x000ff00000001000 */
/*0350*/ @P0 MUFU.RCP R8, R7 ; /* 0x0000000700080308 */
/* 0x000e240000001000 */
/*0360*/ @P0 FFMA R9, R7, R8, -1 ; /* 0xbf80000007090423 */
/* 0x001fc80000000008 */
/*0370*/ @P0 FADD.FTZ R9, -R9, -RZ ; /* 0x800000ff09090221 */
/* 0x000fc80000010100 */
/*0380*/ @P0 FFMA R9, R8, R9, R8 ; /* 0x0000000908090223 */
/* 0x000fc80000000008 */
/*0390*/ @P0 FFMA R6, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009060823 */
/* 0x000fe200000000ff */
/*03a0*/ BRA 0x5d0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*03b0*/ IADD3 R7, R6, -0xfd, RZ ; /* 0xffffff0306077810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.GT.U32.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f04070 */
/*03d0*/ @P0 BRA 0x5c0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*03e0*/ LOP3.LUT R8, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05087812 */
/* 0x000fe200078ec0ff */
/*03f0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3 ; /* 0x00000003ff0c7424 */
/* 0x000fc600078e00ff */
/*0400*/ LOP3.LUT R8, R8, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000008087812 */
/* 0x000fe400078efcff */
/*0410*/ SHF.L.U32 R13, R12, R7, RZ ; /* 0x000000070c0d7219 */
/* 0x000fe400000006ff */
/*0420*/ MUFU.RCP R9, R8 ; /* 0x0000000800097308 */
/* 0x000e240000001000 */
/*0430*/ FFMA R10, R8, R9, -1 ; /* 0xbf800000080a7423 */
/* 0x001fc80000000009 */
/*0440*/ FADD.FTZ R10, -R10, -RZ ; /* 0x800000ff0a0a7221 */
/* 0x000fc80000010100 */
/*0450*/ FFMA.RM R11, R9.reuse, R10.reuse, R9.reuse ; /* 0x0000000a090b7223 */
/* 0x1c0fe40000004009 */
/*0460*/ FFMA.RP R10, R9, R10, R9 ; /* 0x0000000a090a7223 */
/* 0x000fc60000008009 */
/*0470*/ LOP3.LUT R9, R11.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b097812 */
/* 0x040fe400078ec0ff */
/*0480*/ FSETP.NEU.FTZ.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720b */
/* 0x000fe40003f1d000 */
/*0490*/ LOP3.LUT R10, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x00800000090a7812 */
/* 0x000fe400078efcff */
/*04a0*/ SEL R9, RZ, 0xffffffff, !P0 ; /* 0xffffffffff097807 */
/* 0x000fe40004000000 */
/*04b0*/ LOP3.LUT R8, R13, R10, RZ, 0xc0, !PT ; /* 0x0000000a0d087212 */
/* 0x000fe400078ec0ff */
/*04c0*/ IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09097210 */
/* 0x000fc40007ffe1ff */
/*04d0*/ SHF.R.U32.HI R8, RZ, R7.reuse, R8 ; /* 0x00000007ff087219 */
/* 0x080fe40000011608 */
/*04e0*/ LOP3.LUT P1, RZ, R9, R7, R10, 0xf8, !PT ; /* 0x0000000709ff7212 */
/* 0x000fe4000782f80a */
/*04f0*/ LOP3.LUT P0, RZ, R8.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108ff7812 */
/* 0x040fe4000780c0ff */
/*0500*/ LOP3.LUT P2, RZ, R8, 0x2, RZ, 0xc0, !PT ; /* 0x0000000208ff7812 */
/* 0x000fc8000784c0ff */
/*0510*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0520*/ LOP3.LUT P1, RZ, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05ff7812 */
/* 0x000fe4000782c0ff */
/*0530*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*0540*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a07 */
/*0550*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f06270 */
/*0560*/ IADD3 R7, R6, -0xfc, RZ ; /* 0xffffff0406077810 */
/* 0x000fc80007ffe0ff */
/*0570*/ SHF.R.U32.HI R6, RZ, R7, R10 ; /* 0x00000007ff067219 */
/* 0x000fce000001160a */
/*0580*/ @!P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106068810 */
/* 0x000fca0007ffe0ff */
/*0590*/ @!P1 IMAD.SHL.U32 R6, R6, 0x2, RZ ; /* 0x0000000206069824 */
/* 0x000fca00078e00ff */
/*05a0*/ LOP3.LUT R6, R6, 0x80000000, R5, 0xf8, !PT ; /* 0x8000000006067812 */
/* 0x000fe200078ef805 */
/*05b0*/ BRA 0x5d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*05c0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x0000640000001000 */
/*05d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05e0*/ MOV R5, 0x0 ; /* 0x0000000000057802 */
/* 0x001fc80000000f00 */
/*05f0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffa0004007950 */
/* 0x000fea0003c3ffff */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sigmoid(float *inout, float *bias, int rows, int cols) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
if (j >= cols || i >= rows) return;
float t = inout[i * cols + j];
inout[i * cols + j] = 1 / (1 + expf(-t)) + bias[i];
} | .file "tmpxft_0013c8ce_00000000-6_sigmoid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7sigmoidPfS_iiPfS_ii
.type _Z30__device_stub__Z7sigmoidPfS_iiPfS_ii, @function
_Z30__device_stub__Z7sigmoidPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7sigmoidPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7sigmoidPfS_iiPfS_ii, .-_Z30__device_stub__Z7sigmoidPfS_iiPfS_ii
.globl _Z7sigmoidPfS_ii
.type _Z7sigmoidPfS_ii, @function
_Z7sigmoidPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7sigmoidPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7sigmoidPfS_ii, .-_Z7sigmoidPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7sigmoidPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sigmoidPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sigmoid(float *inout, float *bias, int rows, int cols) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
if (j >= cols || i >= rows) return;
float t = inout[i * cols + j];
inout[i * cols + j] = 1 / (1 + expf(-t)) + bias[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sigmoid(float *inout, float *bias, int rows, int cols) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
if (j >= cols || i >= rows) return;
float t = inout[i * cols + j];
inout[i * cols + j] = 1 / (1 + expf(-t)) + bias[i];
} |
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