system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sigmoid(float *inout, float *bias, int rows, int cols) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
if (j >= cols || i >= rows) return;
float t = inout[i * cols + j];
inout[i * cols + j] = 1 / (1 + expf(-t)) + bias[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sigmoidPfS_ii
.globl _Z7sigmoidPfS_ii
.p2align 8
.type _Z7sigmoidPfS_ii,@function
_Z7sigmoidPfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v2
v_cmp_gt_i32_e64 s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v0, s3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
global_load_b32 v2, v[3:4], off
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v1, 0xbfb8aa3b, v2
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v5, v2, 0xbfb8aa3b, -v1
v_rndne_f32_e32 v6, v1
v_fmamk_f32 v5, v2, 0xb2a5705f, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v1, v1, v6
v_add_f32_e32 v1, v1, v5
v_cvt_i32_f32_e32 v5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_ldexp_f32 v1, v1, v5
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, 0x7f800000, v1, vcc_lo
v_add_f32_e32 v1, 1.0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v2, null, v1, v1, 1.0
v_rcp_f32_e32 v5, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v2, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, 1.0, v1, 1.0
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v2, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v7, v6
v_div_fmas_f32 v2, v2, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v1, v2, v1, 1.0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v[3:4], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sigmoidPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sigmoidPfS_ii, .Lfunc_end0-_Z7sigmoidPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sigmoidPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7sigmoidPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sigmoid(float *inout, float *bias, int rows, int cols) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
if (j >= cols || i >= rows) return;
float t = inout[i * cols + j];
inout[i * cols + j] = 1 / (1 + expf(-t)) + bias[i];
} | .text
.file "sigmoid.hip"
.globl _Z22__device_stub__sigmoidPfS_ii # -- Begin function _Z22__device_stub__sigmoidPfS_ii
.p2align 4, 0x90
.type _Z22__device_stub__sigmoidPfS_ii,@function
_Z22__device_stub__sigmoidPfS_ii: # @_Z22__device_stub__sigmoidPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sigmoidPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__sigmoidPfS_ii, .Lfunc_end0-_Z22__device_stub__sigmoidPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sigmoidPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7sigmoidPfS_ii,@object # @_Z7sigmoidPfS_ii
.section .rodata,"a",@progbits
.globl _Z7sigmoidPfS_ii
.p2align 3, 0x0
_Z7sigmoidPfS_ii:
.quad _Z22__device_stub__sigmoidPfS_ii
.size _Z7sigmoidPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7sigmoidPfS_ii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sigmoidPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sigmoidPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7sigmoidPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R2, c[0x0][0x4], R5 ; /* 0x0000010002007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R0, c[0x0][0x174], R3 ; /* 0x00005d0000037a24 */
/* 0x000fc800078e0203 */
/*00d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00e0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ HFMA2.MMA R6, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff067435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff057424 */
/* 0x000fe200078e00ff */
/*0110*/ BSSY B0, 0x260 ; /* 0x0000014000007945 */
/* 0x000fe60003800000 */
/*0120*/ FFMA.SAT R5, -R4, R5, 0.5 ; /* 0x3f00000004057423 */
/* 0x004fca0000002105 */
/*0130*/ FFMA.RM R5, R5, R6, 12582913 ; /* 0x4b40000105057423 */
/* 0x000fc80000004006 */
/*0140*/ FADD R7, R5.reuse, -12583039 ; /* 0xcb40007f05077421 */
/* 0x040fe40000000000 */
/*0150*/ IMAD.SHL.U32 R5, R5, 0x800000, RZ ; /* 0x0080000005057824 */
/* 0x000fe400078e00ff */
/*0160*/ FFMA R7, -R4, 1.4426950216293334961, -R7 ; /* 0x3fb8aa3b04077823 */
/* 0x000fc80000000907 */
/*0170*/ FFMA R7, -R4, 1.925963033500011079e-08, R7 ; /* 0x32a5706004077823 */
/* 0x000fc80000000107 */
/*0180*/ MUFU.EX2 R4, R7 ; /* 0x0000000700047308 */
/* 0x000e240000000800 */
/*0190*/ FFMA R5, R5, R4, 1 ; /* 0x3f80000005057423 */
/* 0x001fca0000000004 */
/*01a0*/ IADD3 R4, R5, 0x1800000, RZ ; /* 0x0180000005047810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000004047812 */
/* 0x000fc800078ec0ff */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ffffff, PT ; /* 0x01ffffff0400780c */
/* 0x000fda0003f04070 */
/*01d0*/ @P0 BRA 0x210 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*01e0*/ MOV R4, 0x200 ; /* 0x0000020000047802 */
/* 0x000fe40000000f00 */
/*01f0*/ CALL.REL.NOINC 0x2c0 ; /* 0x000000c000007944 */
/* 0x000fea0003c00000 */
/*0200*/ BRA 0x250 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0210*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e240000001000 */
/*0220*/ FFMA R4, R5, R6, -1 ; /* 0xbf80000005047423 */
/* 0x001fc80000000006 */
/*0230*/ FADD.FTZ R7, -R4, -RZ ; /* 0x800000ff04077221 */
/* 0x000fc80000010100 */
/*0240*/ FFMA R6, R6, R7, R6 ; /* 0x0000000706067223 */
/* 0x000fe40000000006 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0205 */
/*0280*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FADD R7, R5, R6 ; /* 0x0000000605077221 */
/* 0x006fca0000000000 */
/*02a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ SHF.L.U32 R6, R5, 0x1, RZ ; /* 0x0000000105067819 */
/* 0x000fe200000006ff */
/*02d0*/ BSSY B1, 0x5e0 ; /* 0x0000030000017945 */
/* 0x000fe60003800000 */
/*02e0*/ SHF.R.U32.HI R6, RZ, 0x18, R6 ; /* 0x00000018ff067819 */
/* 0x000fc80000011606 */
/*02f0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05070 */
/*0300*/ @P0 BRA 0x3b0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0310*/ IMAD.SHL.U32 R6, R5, 0x2, RZ ; /* 0x0000000205067824 */
/* 0x000fca00078e00ff */
/*0320*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0330*/ @P0 FFMA R7, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005070823 */
/* 0x000fe200000000ff */
/*0340*/ @!P0 MUFU.RCP R6, R5 ; /* 0x0000000500068308 */
/* 0x000ff00000001000 */
/*0350*/ @P0 MUFU.RCP R8, R7 ; /* 0x0000000700080308 */
/* 0x000e240000001000 */
/*0360*/ @P0 FFMA R9, R7, R8, -1 ; /* 0xbf80000007090423 */
/* 0x001fc80000000008 */
/*0370*/ @P0 FADD.FTZ R9, -R9, -RZ ; /* 0x800000ff09090221 */
/* 0x000fc80000010100 */
/*0380*/ @P0 FFMA R9, R8, R9, R8 ; /* 0x0000000908090223 */
/* 0x000fc80000000008 */
/*0390*/ @P0 FFMA R6, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009060823 */
/* 0x000fe200000000ff */
/*03a0*/ BRA 0x5d0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*03b0*/ IADD3 R7, R6, -0xfd, RZ ; /* 0xffffff0306077810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.GT.U32.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f04070 */
/*03d0*/ @P0 BRA 0x5c0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*03e0*/ LOP3.LUT R8, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05087812 */
/* 0x000fe200078ec0ff */
/*03f0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3 ; /* 0x00000003ff0c7424 */
/* 0x000fc600078e00ff */
/*0400*/ LOP3.LUT R8, R8, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000008087812 */
/* 0x000fe400078efcff */
/*0410*/ SHF.L.U32 R13, R12, R7, RZ ; /* 0x000000070c0d7219 */
/* 0x000fe400000006ff */
/*0420*/ MUFU.RCP R9, R8 ; /* 0x0000000800097308 */
/* 0x000e240000001000 */
/*0430*/ FFMA R10, R8, R9, -1 ; /* 0xbf800000080a7423 */
/* 0x001fc80000000009 */
/*0440*/ FADD.FTZ R10, -R10, -RZ ; /* 0x800000ff0a0a7221 */
/* 0x000fc80000010100 */
/*0450*/ FFMA.RM R11, R9.reuse, R10.reuse, R9.reuse ; /* 0x0000000a090b7223 */
/* 0x1c0fe40000004009 */
/*0460*/ FFMA.RP R10, R9, R10, R9 ; /* 0x0000000a090a7223 */
/* 0x000fc60000008009 */
/*0470*/ LOP3.LUT R9, R11.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b097812 */
/* 0x040fe400078ec0ff */
/*0480*/ FSETP.NEU.FTZ.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720b */
/* 0x000fe40003f1d000 */
/*0490*/ LOP3.LUT R10, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x00800000090a7812 */
/* 0x000fe400078efcff */
/*04a0*/ SEL R9, RZ, 0xffffffff, !P0 ; /* 0xffffffffff097807 */
/* 0x000fe40004000000 */
/*04b0*/ LOP3.LUT R8, R13, R10, RZ, 0xc0, !PT ; /* 0x0000000a0d087212 */
/* 0x000fe400078ec0ff */
/*04c0*/ IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09097210 */
/* 0x000fc40007ffe1ff */
/*04d0*/ SHF.R.U32.HI R8, RZ, R7.reuse, R8 ; /* 0x00000007ff087219 */
/* 0x080fe40000011608 */
/*04e0*/ LOP3.LUT P1, RZ, R9, R7, R10, 0xf8, !PT ; /* 0x0000000709ff7212 */
/* 0x000fe4000782f80a */
/*04f0*/ LOP3.LUT P0, RZ, R8.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108ff7812 */
/* 0x040fe4000780c0ff */
/*0500*/ LOP3.LUT P2, RZ, R8, 0x2, RZ, 0xc0, !PT ; /* 0x0000000208ff7812 */
/* 0x000fc8000784c0ff */
/*0510*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0520*/ LOP3.LUT P1, RZ, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05ff7812 */
/* 0x000fe4000782c0ff */
/*0530*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*0540*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a07 */
/*0550*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f06270 */
/*0560*/ IADD3 R7, R6, -0xfc, RZ ; /* 0xffffff0406077810 */
/* 0x000fc80007ffe0ff */
/*0570*/ SHF.R.U32.HI R6, RZ, R7, R10 ; /* 0x00000007ff067219 */
/* 0x000fce000001160a */
/*0580*/ @!P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106068810 */
/* 0x000fca0007ffe0ff */
/*0590*/ @!P1 IMAD.SHL.U32 R6, R6, 0x2, RZ ; /* 0x0000000206069824 */
/* 0x000fca00078e00ff */
/*05a0*/ LOP3.LUT R6, R6, 0x80000000, R5, 0xf8, !PT ; /* 0x8000000006067812 */
/* 0x000fe200078ef805 */
/*05b0*/ BRA 0x5d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*05c0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x0000640000001000 */
/*05d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05e0*/ MOV R5, 0x0 ; /* 0x0000000000057802 */
/* 0x001fc80000000f00 */
/*05f0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffa0004007950 */
/* 0x000fea0003c3ffff */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sigmoidPfS_ii
.globl _Z7sigmoidPfS_ii
.p2align 8
.type _Z7sigmoidPfS_ii,@function
_Z7sigmoidPfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s4, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v2
v_cmp_gt_i32_e64 s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v0, s3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
global_load_b32 v2, v[3:4], off
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v1, 0xbfb8aa3b, v2
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v5, v2, 0xbfb8aa3b, -v1
v_rndne_f32_e32 v6, v1
v_fmamk_f32 v5, v2, 0xb2a5705f, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v1, v1, v6
v_add_f32_e32 v1, v1, v5
v_cvt_i32_f32_e32 v5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_ldexp_f32 v1, v1, v5
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, 0x7f800000, v1, vcc_lo
v_add_f32_e32 v1, 1.0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v2, null, v1, v1, 1.0
v_rcp_f32_e32 v5, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v2, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, 1.0, v1, 1.0
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v2, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v7, v6
v_div_fmas_f32 v2, v2, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v1, v2, v1, 1.0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v1
global_store_b32 v[3:4], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sigmoidPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sigmoidPfS_ii, .Lfunc_end0-_Z7sigmoidPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sigmoidPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7sigmoidPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013c8ce_00000000-6_sigmoid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7sigmoidPfS_iiPfS_ii
.type _Z30__device_stub__Z7sigmoidPfS_iiPfS_ii, @function
_Z30__device_stub__Z7sigmoidPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7sigmoidPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7sigmoidPfS_iiPfS_ii, .-_Z30__device_stub__Z7sigmoidPfS_iiPfS_ii
.globl _Z7sigmoidPfS_ii
.type _Z7sigmoidPfS_ii, @function
_Z7sigmoidPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7sigmoidPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7sigmoidPfS_ii, .-_Z7sigmoidPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7sigmoidPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sigmoidPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sigmoid.hip"
.globl _Z22__device_stub__sigmoidPfS_ii # -- Begin function _Z22__device_stub__sigmoidPfS_ii
.p2align 4, 0x90
.type _Z22__device_stub__sigmoidPfS_ii,@function
_Z22__device_stub__sigmoidPfS_ii: # @_Z22__device_stub__sigmoidPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sigmoidPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__sigmoidPfS_ii, .Lfunc_end0-_Z22__device_stub__sigmoidPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sigmoidPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7sigmoidPfS_ii,@object # @_Z7sigmoidPfS_ii
.section .rodata,"a",@progbits
.globl _Z7sigmoidPfS_ii
.p2align 3, 0x0
_Z7sigmoidPfS_ii:
.quad _Z22__device_stub__sigmoidPfS_ii
.size _Z7sigmoidPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7sigmoidPfS_ii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sigmoidPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sigmoidPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
#include <cstdint>
#include <time.h>
#include <cstdio>
#include <stdio.h>
#include <stdlib.h>
void cpuProcess(int n, double *arr){
double localMax = -1;
for (int i = 0; i < n; i ++){
if (arr[i] > localMax) localMax = arr[i];
}
arr[0] = localMax;
}
__global__ void gpuProcess(int n, double *arr){
double localMax = -1;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
if (arr[i] > localMax) localMax = arr[i];
}
arr[index] = localMax;
}
int main(int argc, char *argv[]){
clock_t start, diff;
int N = atoi(argv[1]) * 1000000;
double *h_arr = new double[N];
for (int i = 0; i < N; i++) {
double r = rand()/1000000.0;
h_arr[i] = r;
}
start = clock();
cpuProcess(N, h_arr);
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
std::cout << "CPU MAX: " << h_arr[0] << std::endl;
printf("Time taken for cpu: %d milliseconds\n\n", diff);
start = clock();
double *d_arr;
cudaMalloc(&d_arr, sizeof(double)*N);
cudaMemcpy(d_arr, h_arr, N*sizeof(double), cudaMemcpyHostToDevice);
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
printf("Time taken to copy arr to device: %d milliseconds\n", diff);
int numThreads = N;
int threadsPerBlock = 256;
start = clock();
do {
numThreads = N/16;
if (numThreads == 0) numThreads = 1;
if (numThreads < threadsPerBlock) threadsPerBlock = numThreads;
int numBlocks = (numThreads + threadsPerBlock - 1)/threadsPerBlock;
gpuProcess<<<numBlocks, threadsPerBlock>>>(N, d_arr);
std::cout << "Launching " << numThreads << " threads: " << numBlocks << " blocks and " << threadsPerBlock << " threads/block" << std::endl;
cudaDeviceSynchronize();
N = numBlocks * threadsPerBlock;
} while(numThreads > 1);
cudaMemcpy(h_arr, d_arr, 1*sizeof(double), cudaMemcpyDeviceToHost);
std::cout << "GPU MAX: " << h_arr[0] << std::endl;
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
printf("Time taken for gpu: %d milliseconds\n", diff);
// Free memory
cudaFree(d_arr);
return 0;
} | code for sm_80
Function : _Z10gpuProcessiPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x530 ; /* 0x000004f000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, -0x40100000 ; /* 0xbff00000ff037424 */
/* 0x000fc600078e00ff */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0x520 ; /* 0x0000048000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ BSSY B1, 0x380 ; /* 0x000002c000017945 */
/* 0x000fe20003800000 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0000 */
/*00d0*/ IMAD R4, R6, c[0x0][0xc], RZ ; /* 0x0000030006047a24 */
/* 0x000fc800078e02ff */
/*00e0*/ I2F.U32.RP R8, R4 ; /* 0x0000000400087306 */
/* 0x000e220000209000 */
/*00f0*/ IADD3 R2, R5, R4, RZ ; /* 0x0000000405027210 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.MOV R9, RZ, RZ, -R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a04 */
/*0110*/ ISETP.NE.U32.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f45070 */
/*0120*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fe200078e33ff */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0140*/ IADD3 R7, R7, c[0x0][0x160], R4 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe004 */
/*0150*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0160*/ IADD3 R3, R8, 0xffffffe, RZ ; /* 0x0ffffffe08037810 */
/* 0x001fcc0007ffe0ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*0180*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x001fc800078e02ff */
/*0190*/ IMAD.HI.U32 R2, R3, R9, R2 ; /* 0x0000000903027227 */
/* 0x000fcc00078e0002 */
/*01a0*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*01c0*/ IMAD R7, R4, R3, R7 ; /* 0x0000000304077224 */
/* 0x000fca00078e0207 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 IMAD.IADD R7, R7, 0x1, -R4 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a04 */
/*01f0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f26070 */
/*0210*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0220*/ @!P2 LOP3.LUT R2, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff02a212 */
/* 0x000fc800078e33ff */
/*0230*/ IADD3 R3, R2.reuse, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x040fe40007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0250*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT P1, R7, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303077812 */
/* 0x000fe2000782c0ff */
/*0270*/ HFMA2.MMA R3, -RZ, RZ, -1.984375, 0 ; /* 0xbff00000ff037435 */
/* 0x000fd800000001ff */
/*0280*/ @!P1 BRA 0x370 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*02a0*/ MOV R3, 0xbff00000 ; /* 0xbff0000000037802 */
/* 0x000fe20000000f00 */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0000 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe400078e00ff */
/*02d0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fca00078e0209 */
/*02e0*/ LDG.E.64 R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a2000c1e1b00 */
/*02f0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe20007ffe0ff */
/*0300*/ IMAD R5, R6, c[0x0][0xc], R5 ; /* 0x0000030006057a24 */
/* 0x000fc600078e0205 */
/*0310*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f45270 */
/*0320*/ IMAD.WIDE R8, R4, 0x8, R8 ; /* 0x0000000804087825 */
/* 0x001fe200078e0208 */
/*0330*/ DSETP.GT.AND P1, PT, R10, R2, PT ; /* 0x000000020a00722a */
/* 0x004e0c0003f24000 */
/*0340*/ FSEL R2, R10, R2, P1 ; /* 0x000000020a027208 */
/* 0x001fe40000800000 */
/*0350*/ FSEL R3, R11, R3, P1 ; /* 0x000000030b037208 */
/* 0x000fc60000800000 */
/*0360*/ @P2 BRA 0x2e0 ; /* 0xffffff7000002947 */
/* 0x000fea000383ffff */
/*0370*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0380*/ @!P0 BRA 0x520 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0390*/ IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; /* 0x00000008ff067424 */
/* 0x000fc800078e00ff */
/*03a0*/ IMAD.WIDE R6, R5, R6, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fca00078e0206 */
/*03b0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea2000c1e1b00 */
/*03c0*/ IMAD.WIDE R10, R4, 0x8, R6 ; /* 0x00000008040a7825 */
/* 0x000fca00078e0206 */
/*03d0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ee2000c1e1b00 */
/*03e0*/ IMAD.WIDE R14, R4, 0x8, R10 ; /* 0x00000008040e7825 */
/* 0x000fca00078e020a */
/*03f0*/ LDG.E.64 R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000f22000c1e1b00 */
/*0400*/ IMAD.WIDE R18, R4, 0x8, R14 ; /* 0x0000000804127825 */
/* 0x000fcc00078e020e */
/*0410*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1b00 */
/*0420*/ IADD3 R5, R4, R5, R4 ; /* 0x0000000504057210 */
/* 0x000fc80007ffe004 */
/*0430*/ IADD3 R5, R4, R5, R4 ; /* 0x0000000504057210 */
/* 0x000fc80007ffe004 */
/*0440*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x160], PT ; /* 0x0000580005007a0c */
/* 0x000fe20003f26270 */
/*0450*/ DSETP.GT.AND P0, PT, R8, R2, PT ; /* 0x000000020800722a */
/* 0x004e0c0003f04000 */
/*0460*/ FSEL R2, R8, R2, P0 ; /* 0x0000000208027208 */
/* 0x001fe40000000000 */
/*0470*/ FSEL R3, R9, R3, P0 ; /* 0x0000000309037208 */
/* 0x000fcc0000000000 */
/*0480*/ DSETP.GT.AND P0, PT, R12, R2, PT ; /* 0x000000020c00722a */
/* 0x008e0c0003f04000 */
/*0490*/ FSEL R2, R12, R2, P0 ; /* 0x000000020c027208 */
/* 0x001fe40000000000 */
/*04a0*/ FSEL R3, R13, R3, P0 ; /* 0x000000030d037208 */
/* 0x000fcc0000000000 */
/*04b0*/ DSETP.GT.AND P0, PT, R16, R2, PT ; /* 0x000000021000722a */
/* 0x010e0c0003f04000 */
/*04c0*/ FSEL R2, R16, R2, P0 ; /* 0x0000000210027208 */
/* 0x001fe40000000000 */
/*04d0*/ FSEL R3, R17, R3, P0 ; /* 0x0000000311037208 */
/* 0x000fcc0000000000 */
/*04e0*/ DSETP.GT.AND P0, PT, R18, R2, PT ; /* 0x000000021200722a */
/* 0x020e0c0003f04000 */
/*04f0*/ FSEL R2, R18, R2, P0 ; /* 0x0000000212027208 */
/* 0x001fe40000000000 */
/*0500*/ FSEL R3, R19, R3, P0 ; /* 0x0000000313037208 */
/* 0x000fe20000000000 */
/*0510*/ @!P1 BRA 0x390 ; /* 0xfffffe7000009947 */
/* 0x000fea000383ffff */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0540*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*0550*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
#include <cstdint>
#include <time.h>
#include <cstdio>
#include <stdio.h>
#include <stdlib.h>
void cpuProcess(int n, double *arr){
double localMax = -1;
for (int i = 0; i < n; i ++){
if (arr[i] > localMax) localMax = arr[i];
}
arr[0] = localMax;
}
__global__ void gpuProcess(int n, double *arr){
double localMax = -1;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
if (arr[i] > localMax) localMax = arr[i];
}
arr[index] = localMax;
}
int main(int argc, char *argv[]){
clock_t start, diff;
int N = atoi(argv[1]) * 1000000;
double *h_arr = new double[N];
for (int i = 0; i < N; i++) {
double r = rand()/1000000.0;
h_arr[i] = r;
}
start = clock();
cpuProcess(N, h_arr);
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
std::cout << "CPU MAX: " << h_arr[0] << std::endl;
printf("Time taken for cpu: %d milliseconds\n\n", diff);
start = clock();
double *d_arr;
cudaMalloc(&d_arr, sizeof(double)*N);
cudaMemcpy(d_arr, h_arr, N*sizeof(double), cudaMemcpyHostToDevice);
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
printf("Time taken to copy arr to device: %d milliseconds\n", diff);
int numThreads = N;
int threadsPerBlock = 256;
start = clock();
do {
numThreads = N/16;
if (numThreads == 0) numThreads = 1;
if (numThreads < threadsPerBlock) threadsPerBlock = numThreads;
int numBlocks = (numThreads + threadsPerBlock - 1)/threadsPerBlock;
gpuProcess<<<numBlocks, threadsPerBlock>>>(N, d_arr);
std::cout << "Launching " << numThreads << " threads: " << numBlocks << " blocks and " << threadsPerBlock << " threads/block" << std::endl;
cudaDeviceSynchronize();
N = numBlocks * threadsPerBlock;
} while(numThreads > 1);
cudaMemcpy(h_arr, d_arr, 1*sizeof(double), cudaMemcpyDeviceToHost);
std::cout << "GPU MAX: " << h_arr[0] << std::endl;
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
printf("Time taken for gpu: %d milliseconds\n", diff);
// Free memory
cudaFree(d_arr);
return 0;
} | .file "tmpxft_0009b3ec_00000000-6_max_element.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10cpuProcessiPd
.type _Z10cpuProcessiPd, @function
_Z10cpuProcessiPd:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L7
movq %rsi, %rax
movslq %edi, %rdi
leaq (%rsi,%rdi,8), %rdx
movsd .LC0(%rip), %xmm0
.L6:
movsd (%rax), %xmm1
maxsd %xmm0, %xmm1
movapd %xmm1, %xmm0
addq $8, %rax
cmpq %rdx, %rax
jne .L6
.L4:
movsd %xmm0, (%rsi)
ret
.L7:
movsd .LC0(%rip), %xmm0
jmp .L4
.cfi_endproc
.LFE3669:
.size _Z10cpuProcessiPd, .-_Z10cpuProcessiPd
.globl _Z31__device_stub__Z10gpuProcessiPdiPd
.type _Z31__device_stub__Z10gpuProcessiPdiPd, @function
_Z31__device_stub__Z10gpuProcessiPdiPd:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10gpuProcessiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z31__device_stub__Z10gpuProcessiPdiPd, .-_Z31__device_stub__Z10gpuProcessiPdiPd
.globl _Z10gpuProcessiPd
.type _Z10gpuProcessiPd, @function
_Z10gpuProcessiPd:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10gpuProcessiPdiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z10gpuProcessiPd, .-_Z10gpuProcessiPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CPU MAX: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Time taken for cpu: %d milliseconds\n\n"
.align 8
.LC4:
.string "Time taken to copy arr to device: %d milliseconds\n"
.section .rodata.str1.1
.LC5:
.string "Launching "
.LC6:
.string " threads: "
.LC7:
.string " blocks and "
.LC8:
.string " threads/block"
.LC9:
.string "GPU MAX: "
.section .rodata.str1.8
.align 8
.LC10:
.string "Time taken for gpu: %d milliseconds\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
imull $1000000, %eax, %r13d
movslq %r13d, %r12
movq %r12, %rax
shrq $60, %rax
jne .L19
salq $3, %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, %r15
testl %r13d, %r13d
jle .L21
movq %rax, %rbx
imull $1000000, %ebp, %ebp
leal -1(%rbp), %eax
leaq 8(%r15,%rax,8), %rbp
.L23:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC1(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L23
.L21:
call clock@PLT
movq %rax, %rbp
movq %r15, %rsi
movl %r13d, %edi
call _Z10cpuProcessiPd
call clock@PLT
movq %rax, %rbx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd (%r15), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rcx
subq %rbp, %rcx
movabsq $2361183241434822607, %rbx
movq %rcx, %rax
imulq %rbx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbp
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %rbp, %rax
movq %rax, %rcx
imulq %rbx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movl $256, %ebp
movl $1, %r14d
movq %r15, (%rsp)
movq %rax, 8(%rsp)
jmp .L30
.L19:
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L22
call __stack_chk_fail@PLT
.L22:
call __cxa_throw_bad_array_new_length@PLT
.L38:
movq 24(%rsp), %rsi
movl %r13d, %edi
call _Z31__device_stub__Z10gpuProcessiPdiPd
jmp .L25
.L39:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
call _ZSt16__throw_bad_castv@PLT
.L36:
call __stack_chk_fail@PLT
.L40:
movzbl 67(%r15), %esi
.L29:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call cudaDeviceSynchronize@PLT
imull %ebp, %r12d
movl %r12d, %r13d
cmpl $1, %ebx
jle .L37
.L30:
leal 15(%r13), %ebx
testl %r13d, %r13d
cmovns %r13d, %ebx
sarl $4, %ebx
cmove %r14d, %ebx
cmpl %ebx, %ebp
cmovg %ebx, %ebp
leal -1(%rbx,%rbp), %eax
cltd
idivl %ebp
movl %eax, %r12d
movl %ebp, 44(%rsp)
movl %r14d, 48(%rsp)
movl %r14d, 52(%rsp)
movl %eax, 32(%rsp)
movl %r14d, 36(%rsp)
movl %r14d, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl %r14d, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L25:
movl $10, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movl $10, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movl $12, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movl $14, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r15
testq %r15, %r15
je .L39
cmpb $0, 56(%r15)
jne .L40
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L29
.L37:
movq (%rsp), %r15
movq 8(%rsp), %rbx
movl $2, %ecx
movl $8, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd (%r15), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z10gpuProcessiPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gpuProcessiPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long -1074790400
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
#include <cstdint>
#include <time.h>
#include <cstdio>
#include <stdio.h>
#include <stdlib.h>
void cpuProcess(int n, double *arr){
double localMax = -1;
for (int i = 0; i < n; i ++){
if (arr[i] > localMax) localMax = arr[i];
}
arr[0] = localMax;
}
__global__ void gpuProcess(int n, double *arr){
double localMax = -1;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
if (arr[i] > localMax) localMax = arr[i];
}
arr[index] = localMax;
}
int main(int argc, char *argv[]){
clock_t start, diff;
int N = atoi(argv[1]) * 1000000;
double *h_arr = new double[N];
for (int i = 0; i < N; i++) {
double r = rand()/1000000.0;
h_arr[i] = r;
}
start = clock();
cpuProcess(N, h_arr);
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
std::cout << "CPU MAX: " << h_arr[0] << std::endl;
printf("Time taken for cpu: %d milliseconds\n\n", diff);
start = clock();
double *d_arr;
cudaMalloc(&d_arr, sizeof(double)*N);
cudaMemcpy(d_arr, h_arr, N*sizeof(double), cudaMemcpyHostToDevice);
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
printf("Time taken to copy arr to device: %d milliseconds\n", diff);
int numThreads = N;
int threadsPerBlock = 256;
start = clock();
do {
numThreads = N/16;
if (numThreads == 0) numThreads = 1;
if (numThreads < threadsPerBlock) threadsPerBlock = numThreads;
int numBlocks = (numThreads + threadsPerBlock - 1)/threadsPerBlock;
gpuProcess<<<numBlocks, threadsPerBlock>>>(N, d_arr);
std::cout << "Launching " << numThreads << " threads: " << numBlocks << " blocks and " << threadsPerBlock << " threads/block" << std::endl;
cudaDeviceSynchronize();
N = numBlocks * threadsPerBlock;
} while(numThreads > 1);
cudaMemcpy(h_arr, d_arr, 1*sizeof(double), cudaMemcpyDeviceToHost);
std::cout << "GPU MAX: " << h_arr[0] << std::endl;
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
printf("Time taken for gpu: %d milliseconds\n", diff);
// Free memory
cudaFree(d_arr);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <cstdint>
#include <time.h>
#include <cstdio>
#include <stdio.h>
#include <stdlib.h>
void cpuProcess(int n, double *arr){
double localMax = -1;
for (int i = 0; i < n; i ++){
if (arr[i] > localMax) localMax = arr[i];
}
arr[0] = localMax;
}
__global__ void gpuProcess(int n, double *arr){
double localMax = -1;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
if (arr[i] > localMax) localMax = arr[i];
}
arr[index] = localMax;
}
int main(int argc, char *argv[]){
clock_t start, diff;
int N = atoi(argv[1]) * 1000000;
double *h_arr = new double[N];
for (int i = 0; i < N; i++) {
double r = rand()/1000000.0;
h_arr[i] = r;
}
start = clock();
cpuProcess(N, h_arr);
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
std::cout << "CPU MAX: " << h_arr[0] << std::endl;
printf("Time taken for cpu: %d milliseconds\n\n", diff);
start = clock();
double *d_arr;
hipMalloc(&d_arr, sizeof(double)*N);
hipMemcpy(d_arr, h_arr, N*sizeof(double), hipMemcpyHostToDevice);
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
printf("Time taken to copy arr to device: %d milliseconds\n", diff);
int numThreads = N;
int threadsPerBlock = 256;
start = clock();
do {
numThreads = N/16;
if (numThreads == 0) numThreads = 1;
if (numThreads < threadsPerBlock) threadsPerBlock = numThreads;
int numBlocks = (numThreads + threadsPerBlock - 1)/threadsPerBlock;
gpuProcess<<<numBlocks, threadsPerBlock>>>(N, d_arr);
std::cout << "Launching " << numThreads << " threads: " << numBlocks << " blocks and " << threadsPerBlock << " threads/block" << std::endl;
hipDeviceSynchronize();
N = numBlocks * threadsPerBlock;
} while(numThreads > 1);
hipMemcpy(h_arr, d_arr, 1*sizeof(double), hipMemcpyDeviceToHost);
std::cout << "GPU MAX: " << h_arr[0] << std::endl;
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
printf("Time taken for gpu: %d milliseconds\n", diff);
// Free memory
hipFree(d_arr);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <cstdint>
#include <time.h>
#include <cstdio>
#include <stdio.h>
#include <stdlib.h>
void cpuProcess(int n, double *arr){
double localMax = -1;
for (int i = 0; i < n; i ++){
if (arr[i] > localMax) localMax = arr[i];
}
arr[0] = localMax;
}
__global__ void gpuProcess(int n, double *arr){
double localMax = -1;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
if (arr[i] > localMax) localMax = arr[i];
}
arr[index] = localMax;
}
int main(int argc, char *argv[]){
clock_t start, diff;
int N = atoi(argv[1]) * 1000000;
double *h_arr = new double[N];
for (int i = 0; i < N; i++) {
double r = rand()/1000000.0;
h_arr[i] = r;
}
start = clock();
cpuProcess(N, h_arr);
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
std::cout << "CPU MAX: " << h_arr[0] << std::endl;
printf("Time taken for cpu: %d milliseconds\n\n", diff);
start = clock();
double *d_arr;
hipMalloc(&d_arr, sizeof(double)*N);
hipMemcpy(d_arr, h_arr, N*sizeof(double), hipMemcpyHostToDevice);
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
printf("Time taken to copy arr to device: %d milliseconds\n", diff);
int numThreads = N;
int threadsPerBlock = 256;
start = clock();
do {
numThreads = N/16;
if (numThreads == 0) numThreads = 1;
if (numThreads < threadsPerBlock) threadsPerBlock = numThreads;
int numBlocks = (numThreads + threadsPerBlock - 1)/threadsPerBlock;
gpuProcess<<<numBlocks, threadsPerBlock>>>(N, d_arr);
std::cout << "Launching " << numThreads << " threads: " << numBlocks << " blocks and " << threadsPerBlock << " threads/block" << std::endl;
hipDeviceSynchronize();
N = numBlocks * threadsPerBlock;
} while(numThreads > 1);
hipMemcpy(h_arr, d_arr, 1*sizeof(double), hipMemcpyDeviceToHost);
std::cout << "GPU MAX: " << h_arr[0] << std::endl;
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
printf("Time taken for gpu: %d milliseconds\n", diff);
// Free memory
hipFree(d_arr);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10gpuProcessiPd
.globl _Z10gpuProcessiPd
.p2align 8
.type _Z10gpuProcessiPd,@function
_Z10gpuProcessiPd:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s8, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s0, s0, 16
s_addc_u32 s1, s1, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0xbff00000
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_4
s_load_b32 s0, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, v1
v_mov_b32_e32 v4, 0xbff00000
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s0, s4
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[4:5], 3
s_mov_b32 s5, 0
.LBB0_2:
global_load_b64 v[7:8], v[5:6], off
v_add_co_u32 v5, s0, v5, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
s_waitcnt vmcnt(0)
v_cmp_gt_f64_e32 vcc_lo, v[7:8], v[3:4]
v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v0, s4, v0
v_cmp_le_i32_e64 s1, s8, v0
v_cndmask_b32_e32 v4, v4, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s5, s1, s5
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s9
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10gpuProcessiPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10gpuProcessiPd, .Lfunc_end0-_Z10gpuProcessiPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10gpuProcessiPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10gpuProcessiPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <cstdint>
#include <time.h>
#include <cstdio>
#include <stdio.h>
#include <stdlib.h>
void cpuProcess(int n, double *arr){
double localMax = -1;
for (int i = 0; i < n; i ++){
if (arr[i] > localMax) localMax = arr[i];
}
arr[0] = localMax;
}
__global__ void gpuProcess(int n, double *arr){
double localMax = -1;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
if (arr[i] > localMax) localMax = arr[i];
}
arr[index] = localMax;
}
int main(int argc, char *argv[]){
clock_t start, diff;
int N = atoi(argv[1]) * 1000000;
double *h_arr = new double[N];
for (int i = 0; i < N; i++) {
double r = rand()/1000000.0;
h_arr[i] = r;
}
start = clock();
cpuProcess(N, h_arr);
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
std::cout << "CPU MAX: " << h_arr[0] << std::endl;
printf("Time taken for cpu: %d milliseconds\n\n", diff);
start = clock();
double *d_arr;
hipMalloc(&d_arr, sizeof(double)*N);
hipMemcpy(d_arr, h_arr, N*sizeof(double), hipMemcpyHostToDevice);
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
printf("Time taken to copy arr to device: %d milliseconds\n", diff);
int numThreads = N;
int threadsPerBlock = 256;
start = clock();
do {
numThreads = N/16;
if (numThreads == 0) numThreads = 1;
if (numThreads < threadsPerBlock) threadsPerBlock = numThreads;
int numBlocks = (numThreads + threadsPerBlock - 1)/threadsPerBlock;
gpuProcess<<<numBlocks, threadsPerBlock>>>(N, d_arr);
std::cout << "Launching " << numThreads << " threads: " << numBlocks << " blocks and " << threadsPerBlock << " threads/block" << std::endl;
hipDeviceSynchronize();
N = numBlocks * threadsPerBlock;
} while(numThreads > 1);
hipMemcpy(h_arr, d_arr, 1*sizeof(double), hipMemcpyDeviceToHost);
std::cout << "GPU MAX: " << h_arr[0] << std::endl;
diff = (clock() - start) * 1000 / CLOCKS_PER_SEC;
printf("Time taken for gpu: %d milliseconds\n", diff);
// Free memory
hipFree(d_arr);
return 0;
} | .text
.file "max_element.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10cpuProcessiPd
.LCPI0_0:
.quad 0xbff0000000000000 # double -1
.text
.globl _Z10cpuProcessiPd
.p2align 4, 0x90
.type _Z10cpuProcessiPd,@function
_Z10cpuProcessiPd: # @_Z10cpuProcessiPd
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_1
# %bb.3: # %.lr.ph.preheader
movl %edi, %eax
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rsi,%rcx,8), %xmm0 # xmm0 = mem[0],zero
maxsd %xmm1, %xmm0
incq %rcx
movapd %xmm0, %xmm1
cmpq %rcx, %rax
jne .LBB0_4
# %bb.2: # %._crit_edge
movsd %xmm0, (%rsi)
retq
.LBB0_1:
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rsi)
retq
.Lfunc_end0:
.size _Z10cpuProcessiPd, .Lfunc_end0-_Z10cpuProcessiPd
.cfi_endproc
# -- End function
.globl _Z25__device_stub__gpuProcessiPd # -- Begin function _Z25__device_stub__gpuProcessiPd
.p2align 4, 0x90
.type _Z25__device_stub__gpuProcessiPd,@function
_Z25__device_stub__gpuProcessiPd: # @_Z25__device_stub__gpuProcessiPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10gpuProcessiPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__gpuProcessiPd, .Lfunc_end1-_Z25__device_stub__gpuProcessiPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_1:
.quad 0xbff0000000000000 # double -1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
imull $1000000, %r15d, %r14d # imm = 0xF4240
movslq %r14d, %r13
shlq $3, %r13
testl %r15d, %r15d
movq $-1, %rdi
cmovnsq %r13, %rdi
callq _Znam
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
cmpl $2, %r14d
movl $1, %r12d
cmovgel %r14d, %r12d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, (%rbx,%rbp,8)
incq %rbp
cmpq %rbp, %r12
jne .LBB2_2
.LBB2_3: # %._crit_edge
callq clock
movq %rax, %r12
testl %r15d, %r15d
jle .LBB2_4
# %bb.5: # %.lr.ph.preheader.i
movl %r14d, %eax
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rcx,8), %xmm0 # xmm0 = mem[0],zero
maxsd %xmm1, %xmm0
incq %rcx
movapd %xmm0, %xmm1
cmpq %rcx, %rax
jne .LBB2_6
jmp .LBB2_7
.LBB2_4:
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
.LBB2_7: # %_Z10cpuProcessiPd.exit
movsd %xmm0, (%rbx)
callq clock
subq %r12, %rax
movabsq $2361183241434822607, %rbp # imm = 0x20C49BA5E353F7CF
imulq %rbp
movq %rdx, %r15
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%rbx), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_26
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
movq %r15, %rcx
shrq $63, %rcx
sarq $7, %r15
addq %rcx, %r15
cmpb $0, 56(%r12)
je .LBB2_10
# %bb.9:
movzbl 67(%r12), %ecx
jmp .LBB2_11
.LBB2_10:
movq %r12, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
movabsq $2361183241434822607, %rbp # imm = 0x20C49BA5E353F7CF
.LBB2_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.1, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
callq clock
movq %rax, %r15
movq %rsp, %rdi
movq %r13, %rsi
callq hipMalloc
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
callq clock
subq %r15, %rax
imulq %rbp
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $256, %r15d # imm = 0x100
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_18: # in Loop: Header=BB2_12 Depth=1
movzbl 67(%r12), %eax
.LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit48
# in Loop: Header=BB2_12 Depth=1
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
imull %r15d, %ebp
movl %ebp, %r14d
cmpl $1, %r13d
jle .LBB2_21
.LBB2_12: # =>This Inner Loop Header: Depth=1
leal 15(%r14), %eax
movl $1, %r13d
cmpl $31, %eax
jb .LBB2_14
# %bb.13: # %select.false.sink
# in Loop: Header=BB2_12 Depth=1
testl %r14d, %r14d
cmovnsl %r14d, %eax
sarl $4, %eax
movl %eax, %r13d
.LBB2_14: # %select.end
# in Loop: Header=BB2_12 Depth=1
cmpl %r15d, %r13d
cmovll %r13d, %r15d
leal (%r15,%r13), %eax
decl %eax
cltd
idivl %r15d
movl %eax, %ebp
movq %rbp, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movq %r15, %rdx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15: # in Loop: Header=BB2_12 Depth=1
movq (%rsp), %rax
movl %r14d, 12(%rsp)
movq %rax, 72(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z10gpuProcessiPd, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_16: # in Loop: Header=BB2_12 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r13d, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.4, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.5, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.6, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r12
testq %r12, %r12
je .LBB2_26
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i45
# in Loop: Header=BB2_12 Depth=1
cmpb $0, 56(%r12)
jne .LBB2_18
# %bb.19: # in Loop: Header=BB2_12 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB2_20
.LBB2_21:
movq (%rsp), %rsi
movl $8, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%rbx), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_26
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i50
cmpb $0, 56(%rbx)
movabsq $2361183241434822607, %r15 # imm = 0x20C49BA5E353F7CF
je .LBB2_24
# %bb.23:
movzbl 67(%rbx), %ecx
jmp .LBB2_25
.LBB2_24:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit53
movq 16(%rsp), %rbx # 8-byte Reload
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
subq %rbx, %rax
imulq %r15
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_26:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gpuProcessiPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10gpuProcessiPd,@object # @_Z10gpuProcessiPd
.section .rodata,"a",@progbits
.globl _Z10gpuProcessiPd
.p2align 3, 0x0
_Z10gpuProcessiPd:
.quad _Z25__device_stub__gpuProcessiPd
.size _Z10gpuProcessiPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU MAX: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time taken for cpu: %d milliseconds\n\n"
.size .L.str.1, 38
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time taken to copy arr to device: %d milliseconds\n"
.size .L.str.2, 51
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Launching "
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " threads: "
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " blocks and "
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " threads/block"
.size .L.str.6, 15
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU MAX: "
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Time taken for gpu: %d milliseconds\n"
.size .L.str.8, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10gpuProcessiPd"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gpuProcessiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gpuProcessiPd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10gpuProcessiPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x530 ; /* 0x000004f000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, -0x40100000 ; /* 0xbff00000ff037424 */
/* 0x000fc600078e00ff */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0x520 ; /* 0x0000048000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ BSSY B1, 0x380 ; /* 0x000002c000017945 */
/* 0x000fe20003800000 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0000 */
/*00d0*/ IMAD R4, R6, c[0x0][0xc], RZ ; /* 0x0000030006047a24 */
/* 0x000fc800078e02ff */
/*00e0*/ I2F.U32.RP R8, R4 ; /* 0x0000000400087306 */
/* 0x000e220000209000 */
/*00f0*/ IADD3 R2, R5, R4, RZ ; /* 0x0000000405027210 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.MOV R9, RZ, RZ, -R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a04 */
/*0110*/ ISETP.NE.U32.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f45070 */
/*0120*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fe200078e33ff */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0140*/ IADD3 R7, R7, c[0x0][0x160], R4 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe004 */
/*0150*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0160*/ IADD3 R3, R8, 0xffffffe, RZ ; /* 0x0ffffffe08037810 */
/* 0x001fcc0007ffe0ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*0180*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x001fc800078e02ff */
/*0190*/ IMAD.HI.U32 R2, R3, R9, R2 ; /* 0x0000000903027227 */
/* 0x000fcc00078e0002 */
/*01a0*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*01c0*/ IMAD R7, R4, R3, R7 ; /* 0x0000000304077224 */
/* 0x000fca00078e0207 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 IMAD.IADD R7, R7, 0x1, -R4 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a04 */
/*01f0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f26070 */
/*0210*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0220*/ @!P2 LOP3.LUT R2, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff02a212 */
/* 0x000fc800078e33ff */
/*0230*/ IADD3 R3, R2.reuse, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x040fe40007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0250*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT P1, R7, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303077812 */
/* 0x000fe2000782c0ff */
/*0270*/ HFMA2.MMA R3, -RZ, RZ, -1.984375, 0 ; /* 0xbff00000ff037435 */
/* 0x000fd800000001ff */
/*0280*/ @!P1 BRA 0x370 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*02a0*/ MOV R3, 0xbff00000 ; /* 0xbff0000000037802 */
/* 0x000fe20000000f00 */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0000 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe400078e00ff */
/*02d0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fca00078e0209 */
/*02e0*/ LDG.E.64 R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a2000c1e1b00 */
/*02f0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe20007ffe0ff */
/*0300*/ IMAD R5, R6, c[0x0][0xc], R5 ; /* 0x0000030006057a24 */
/* 0x000fc600078e0205 */
/*0310*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f45270 */
/*0320*/ IMAD.WIDE R8, R4, 0x8, R8 ; /* 0x0000000804087825 */
/* 0x001fe200078e0208 */
/*0330*/ DSETP.GT.AND P1, PT, R10, R2, PT ; /* 0x000000020a00722a */
/* 0x004e0c0003f24000 */
/*0340*/ FSEL R2, R10, R2, P1 ; /* 0x000000020a027208 */
/* 0x001fe40000800000 */
/*0350*/ FSEL R3, R11, R3, P1 ; /* 0x000000030b037208 */
/* 0x000fc60000800000 */
/*0360*/ @P2 BRA 0x2e0 ; /* 0xffffff7000002947 */
/* 0x000fea000383ffff */
/*0370*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0380*/ @!P0 BRA 0x520 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0390*/ IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; /* 0x00000008ff067424 */
/* 0x000fc800078e00ff */
/*03a0*/ IMAD.WIDE R6, R5, R6, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fca00078e0206 */
/*03b0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea2000c1e1b00 */
/*03c0*/ IMAD.WIDE R10, R4, 0x8, R6 ; /* 0x00000008040a7825 */
/* 0x000fca00078e0206 */
/*03d0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ee2000c1e1b00 */
/*03e0*/ IMAD.WIDE R14, R4, 0x8, R10 ; /* 0x00000008040e7825 */
/* 0x000fca00078e020a */
/*03f0*/ LDG.E.64 R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000f22000c1e1b00 */
/*0400*/ IMAD.WIDE R18, R4, 0x8, R14 ; /* 0x0000000804127825 */
/* 0x000fcc00078e020e */
/*0410*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1b00 */
/*0420*/ IADD3 R5, R4, R5, R4 ; /* 0x0000000504057210 */
/* 0x000fc80007ffe004 */
/*0430*/ IADD3 R5, R4, R5, R4 ; /* 0x0000000504057210 */
/* 0x000fc80007ffe004 */
/*0440*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x160], PT ; /* 0x0000580005007a0c */
/* 0x000fe20003f26270 */
/*0450*/ DSETP.GT.AND P0, PT, R8, R2, PT ; /* 0x000000020800722a */
/* 0x004e0c0003f04000 */
/*0460*/ FSEL R2, R8, R2, P0 ; /* 0x0000000208027208 */
/* 0x001fe40000000000 */
/*0470*/ FSEL R3, R9, R3, P0 ; /* 0x0000000309037208 */
/* 0x000fcc0000000000 */
/*0480*/ DSETP.GT.AND P0, PT, R12, R2, PT ; /* 0x000000020c00722a */
/* 0x008e0c0003f04000 */
/*0490*/ FSEL R2, R12, R2, P0 ; /* 0x000000020c027208 */
/* 0x001fe40000000000 */
/*04a0*/ FSEL R3, R13, R3, P0 ; /* 0x000000030d037208 */
/* 0x000fcc0000000000 */
/*04b0*/ DSETP.GT.AND P0, PT, R16, R2, PT ; /* 0x000000021000722a */
/* 0x010e0c0003f04000 */
/*04c0*/ FSEL R2, R16, R2, P0 ; /* 0x0000000210027208 */
/* 0x001fe40000000000 */
/*04d0*/ FSEL R3, R17, R3, P0 ; /* 0x0000000311037208 */
/* 0x000fcc0000000000 */
/*04e0*/ DSETP.GT.AND P0, PT, R18, R2, PT ; /* 0x000000021200722a */
/* 0x020e0c0003f04000 */
/*04f0*/ FSEL R2, R18, R2, P0 ; /* 0x0000000212027208 */
/* 0x001fe40000000000 */
/*0500*/ FSEL R3, R19, R3, P0 ; /* 0x0000000313037208 */
/* 0x000fe20000000000 */
/*0510*/ @!P1 BRA 0x390 ; /* 0xfffffe7000009947 */
/* 0x000fea000383ffff */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0540*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*0550*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10gpuProcessiPd
.globl _Z10gpuProcessiPd
.p2align 8
.type _Z10gpuProcessiPd,@function
_Z10gpuProcessiPd:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s8, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s0, s0, 16
s_addc_u32 s1, s1, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0xbff00000
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_4
s_load_b32 s0, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, v1
v_mov_b32_e32 v4, 0xbff00000
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s0, s4
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[4:5], 3
s_mov_b32 s5, 0
.LBB0_2:
global_load_b64 v[7:8], v[5:6], off
v_add_co_u32 v5, s0, v5, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
s_waitcnt vmcnt(0)
v_cmp_gt_f64_e32 vcc_lo, v[7:8], v[3:4]
v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v0, s4, v0
v_cmp_le_i32_e64 s1, s8, v0
v_cndmask_b32_e32 v4, v4, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s5, s1, s5
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s9
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10gpuProcessiPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10gpuProcessiPd, .Lfunc_end0-_Z10gpuProcessiPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10gpuProcessiPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10gpuProcessiPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009b3ec_00000000-6_max_element.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10cpuProcessiPd
.type _Z10cpuProcessiPd, @function
_Z10cpuProcessiPd:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L7
movq %rsi, %rax
movslq %edi, %rdi
leaq (%rsi,%rdi,8), %rdx
movsd .LC0(%rip), %xmm0
.L6:
movsd (%rax), %xmm1
maxsd %xmm0, %xmm1
movapd %xmm1, %xmm0
addq $8, %rax
cmpq %rdx, %rax
jne .L6
.L4:
movsd %xmm0, (%rsi)
ret
.L7:
movsd .LC0(%rip), %xmm0
jmp .L4
.cfi_endproc
.LFE3669:
.size _Z10cpuProcessiPd, .-_Z10cpuProcessiPd
.globl _Z31__device_stub__Z10gpuProcessiPdiPd
.type _Z31__device_stub__Z10gpuProcessiPdiPd, @function
_Z31__device_stub__Z10gpuProcessiPdiPd:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10gpuProcessiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z31__device_stub__Z10gpuProcessiPdiPd, .-_Z31__device_stub__Z10gpuProcessiPdiPd
.globl _Z10gpuProcessiPd
.type _Z10gpuProcessiPd, @function
_Z10gpuProcessiPd:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10gpuProcessiPdiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z10gpuProcessiPd, .-_Z10gpuProcessiPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "CPU MAX: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Time taken for cpu: %d milliseconds\n\n"
.align 8
.LC4:
.string "Time taken to copy arr to device: %d milliseconds\n"
.section .rodata.str1.1
.LC5:
.string "Launching "
.LC6:
.string " threads: "
.LC7:
.string " blocks and "
.LC8:
.string " threads/block"
.LC9:
.string "GPU MAX: "
.section .rodata.str1.8
.align 8
.LC10:
.string "Time taken for gpu: %d milliseconds\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
imull $1000000, %eax, %r13d
movslq %r13d, %r12
movq %r12, %rax
shrq $60, %rax
jne .L19
salq $3, %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, %r15
testl %r13d, %r13d
jle .L21
movq %rax, %rbx
imull $1000000, %ebp, %ebp
leal -1(%rbp), %eax
leaq 8(%r15,%rax,8), %rbp
.L23:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC1(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L23
.L21:
call clock@PLT
movq %rax, %rbp
movq %r15, %rsi
movl %r13d, %edi
call _Z10cpuProcessiPd
call clock@PLT
movq %rax, %rbx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd (%r15), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %rcx
subq %rbp, %rcx
movabsq $2361183241434822607, %rbx
movq %rcx, %rax
imulq %rbx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbp
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %rbp, %rax
movq %rax, %rcx
imulq %rbx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movl $256, %ebp
movl $1, %r14d
movq %r15, (%rsp)
movq %rax, 8(%rsp)
jmp .L30
.L19:
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L22
call __stack_chk_fail@PLT
.L22:
call __cxa_throw_bad_array_new_length@PLT
.L38:
movq 24(%rsp), %rsi
movl %r13d, %edi
call _Z31__device_stub__Z10gpuProcessiPdiPd
jmp .L25
.L39:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
call _ZSt16__throw_bad_castv@PLT
.L36:
call __stack_chk_fail@PLT
.L40:
movzbl 67(%r15), %esi
.L29:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call cudaDeviceSynchronize@PLT
imull %ebp, %r12d
movl %r12d, %r13d
cmpl $1, %ebx
jle .L37
.L30:
leal 15(%r13), %ebx
testl %r13d, %r13d
cmovns %r13d, %ebx
sarl $4, %ebx
cmove %r14d, %ebx
cmpl %ebx, %ebp
cmovg %ebx, %ebp
leal -1(%rbx,%rbp), %eax
cltd
idivl %ebp
movl %eax, %r12d
movl %ebp, 44(%rsp)
movl %r14d, 48(%rsp)
movl %r14d, 52(%rsp)
movl %eax, 32(%rsp)
movl %r14d, 36(%rsp)
movl %r14d, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl %r14d, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L25:
movl $10, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movl $10, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movl $12, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movl $14, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r15
testq %r15, %r15
je .L39
cmpb $0, 56(%r15)
jne .L40
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L29
.L37:
movq (%rsp), %r15
movq 8(%rsp), %rbx
movl $2, %ecx
movl $8, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd (%r15), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z10gpuProcessiPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gpuProcessiPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long -1074790400
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "max_element.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10cpuProcessiPd
.LCPI0_0:
.quad 0xbff0000000000000 # double -1
.text
.globl _Z10cpuProcessiPd
.p2align 4, 0x90
.type _Z10cpuProcessiPd,@function
_Z10cpuProcessiPd: # @_Z10cpuProcessiPd
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_1
# %bb.3: # %.lr.ph.preheader
movl %edi, %eax
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rsi,%rcx,8), %xmm0 # xmm0 = mem[0],zero
maxsd %xmm1, %xmm0
incq %rcx
movapd %xmm0, %xmm1
cmpq %rcx, %rax
jne .LBB0_4
# %bb.2: # %._crit_edge
movsd %xmm0, (%rsi)
retq
.LBB0_1:
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rsi)
retq
.Lfunc_end0:
.size _Z10cpuProcessiPd, .Lfunc_end0-_Z10cpuProcessiPd
.cfi_endproc
# -- End function
.globl _Z25__device_stub__gpuProcessiPd # -- Begin function _Z25__device_stub__gpuProcessiPd
.p2align 4, 0x90
.type _Z25__device_stub__gpuProcessiPd,@function
_Z25__device_stub__gpuProcessiPd: # @_Z25__device_stub__gpuProcessiPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10gpuProcessiPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__gpuProcessiPd, .Lfunc_end1-_Z25__device_stub__gpuProcessiPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_1:
.quad 0xbff0000000000000 # double -1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
imull $1000000, %r15d, %r14d # imm = 0xF4240
movslq %r14d, %r13
shlq $3, %r13
testl %r15d, %r15d
movq $-1, %rdi
cmovnsq %r13, %rdi
callq _Znam
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
cmpl $2, %r14d
movl $1, %r12d
cmovgel %r14d, %r12d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, (%rbx,%rbp,8)
incq %rbp
cmpq %rbp, %r12
jne .LBB2_2
.LBB2_3: # %._crit_edge
callq clock
movq %rax, %r12
testl %r15d, %r15d
jle .LBB2_4
# %bb.5: # %.lr.ph.preheader.i
movl %r14d, %eax
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rcx,8), %xmm0 # xmm0 = mem[0],zero
maxsd %xmm1, %xmm0
incq %rcx
movapd %xmm0, %xmm1
cmpq %rcx, %rax
jne .LBB2_6
jmp .LBB2_7
.LBB2_4:
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
.LBB2_7: # %_Z10cpuProcessiPd.exit
movsd %xmm0, (%rbx)
callq clock
subq %r12, %rax
movabsq $2361183241434822607, %rbp # imm = 0x20C49BA5E353F7CF
imulq %rbp
movq %rdx, %r15
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%rbx), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_26
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
movq %r15, %rcx
shrq $63, %rcx
sarq $7, %r15
addq %rcx, %r15
cmpb $0, 56(%r12)
je .LBB2_10
# %bb.9:
movzbl 67(%r12), %ecx
jmp .LBB2_11
.LBB2_10:
movq %r12, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
movabsq $2361183241434822607, %rbp # imm = 0x20C49BA5E353F7CF
.LBB2_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.1, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
callq clock
movq %rax, %r15
movq %rsp, %rdi
movq %r13, %rsi
callq hipMalloc
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
callq clock
subq %r15, %rax
imulq %rbp
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $256, %r15d # imm = 0x100
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_18: # in Loop: Header=BB2_12 Depth=1
movzbl 67(%r12), %eax
.LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit48
# in Loop: Header=BB2_12 Depth=1
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
imull %r15d, %ebp
movl %ebp, %r14d
cmpl $1, %r13d
jle .LBB2_21
.LBB2_12: # =>This Inner Loop Header: Depth=1
leal 15(%r14), %eax
movl $1, %r13d
cmpl $31, %eax
jb .LBB2_14
# %bb.13: # %select.false.sink
# in Loop: Header=BB2_12 Depth=1
testl %r14d, %r14d
cmovnsl %r14d, %eax
sarl $4, %eax
movl %eax, %r13d
.LBB2_14: # %select.end
# in Loop: Header=BB2_12 Depth=1
cmpl %r15d, %r13d
cmovll %r13d, %r15d
leal (%r15,%r13), %eax
decl %eax
cltd
idivl %r15d
movl %eax, %ebp
movq %rbp, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movq %r15, %rdx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_16
# %bb.15: # in Loop: Header=BB2_12 Depth=1
movq (%rsp), %rax
movl %r14d, 12(%rsp)
movq %rax, 72(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z10gpuProcessiPd, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_16: # in Loop: Header=BB2_12 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r13d, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.4, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.5, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.6, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r12
testq %r12, %r12
je .LBB2_26
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i45
# in Loop: Header=BB2_12 Depth=1
cmpb $0, 56(%r12)
jne .LBB2_18
# %bb.19: # in Loop: Header=BB2_12 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB2_20
.LBB2_21:
movq (%rsp), %rsi
movl $8, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%rbx), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_26
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i50
cmpb $0, 56(%rbx)
movabsq $2361183241434822607, %r15 # imm = 0x20C49BA5E353F7CF
je .LBB2_24
# %bb.23:
movzbl 67(%rbx), %ecx
jmp .LBB2_25
.LBB2_24:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit53
movq 16(%rsp), %rbx # 8-byte Reload
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq clock
subq %rbx, %rax
imulq %r15
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_26:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gpuProcessiPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10gpuProcessiPd,@object # @_Z10gpuProcessiPd
.section .rodata,"a",@progbits
.globl _Z10gpuProcessiPd
.p2align 3, 0x0
_Z10gpuProcessiPd:
.quad _Z25__device_stub__gpuProcessiPd
.size _Z10gpuProcessiPd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU MAX: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time taken for cpu: %d milliseconds\n\n"
.size .L.str.1, 38
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time taken to copy arr to device: %d milliseconds\n"
.size .L.str.2, 51
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Launching "
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " threads: "
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " blocks and "
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " threads/block"
.size .L.str.6, 15
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU MAX: "
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Time taken for gpu: %d milliseconds\n"
.size .L.str.8, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10gpuProcessiPd"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gpuProcessiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gpuProcessiPd
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* 日期： 2019-1-24
* 时间： 14:42
* 姓名： 杨丰拓
*/
//******************************************************************************************************************//
//对大量数据进行归约操作（例如，最大，最小，求和等）可通过使用共享内存缩短归约操作的时间．
//本程序预设目标归约2^20~2^30个数据，核划分为一维网格一维线程块，通过三次归约操作求出最大值．
//实际可处理数据为0~2^26.
//本程序可以处理0~2^20个数据，但实际上相对与处理的数据来说代码略有多余．在处理0~2^10个数据时仅需调用一次核函数，
//在处理2^10~2^20个数据时仅需调用两次核函数．当需要处理的数据量达到2^26时，网格内x维度上有65536个块，而网格的x,
//y,z方向上的维度最大值是 65535 ，块的数量超出维度上限，所以会出现结果输出为零的情况．
//若需要处理更多的数据，那么网格的维度需要变为二维乃至三维才能正常处理．
//******************************************************************************************************************//
#include <iostream>
#include <cuda_runtime.h>
#include <stdio.h>
#define k1 1024
#define k2 1024
//检查宏，用于检测cuda编程出错位置及原因
#define CHECK(call) \
{ \
const cudaError_t error=call; \
if(error!=cudaSuccess) \
{ \
printf("Error:%s:%d,",__FILE__,__LINE__); \
printf("code:%d,reason:%s\n",error,cudaGetErrorString(error)); \
exit(1); \
} \
} \
using namespace std;
/* ＠property 核函数
* ＠func 归约求每个共享内存内的最大值
* ＠param_in in 指向待归约的数据
* ＠param_in num 输入的数据量
* ＠param_out out 指向数据的输出地址
*/
__global__ void reduce(int *in,int *out,int num)
{
int tid=threadIdx.x; //块内线程的索引
int idx=blockIdx.x*blockDim.x+threadIdx.x; //线程的实际索引
extern __shared__ int data[]; //共享内存，空间大小在核函数调用时(func<<<,,共享内存字节数>>>)分配
if(idx>=num)return; //防止索引越界
data[tid]=in[idx];
__syncthreads(); //等待共享内存拷贝数据结束
for(unsigned int s=blockDim.x/2;s>0;s>>=1) //块内归约操作
{
if(tid<s)
{
data[tid]=max(data[tid],data[tid+s]);
}
__syncthreads();
}
if(tid==0)out[blockIdx.x]=data[0]; //输出每个块内的归约结果
}
int main()
{
int a;
cout <<"数据量为2的几次方？(a<=25)"<<endl;
cin>>a;
int arraysize=1<<a;
int arraybytes=arraysize*sizeof(int);
int grid1,grid2;
int *h_in,*h_cpu,*h_gpu,*d_in,*d_out,*d_tmp1,*d_tmp2;
clock_t start,end;
double time;
h_in=(int *)malloc(arraybytes);
h_cpu=(int *)malloc(sizeof(int));
h_gpu=(int *)malloc(sizeof(int));
cout <<"数据量: "<<arraysize<<endl;
for(int i=0;i<arraysize;i++) //生成数据
{
//h_in[i]=(int)random();
h_in[i]=i;
}
*h_cpu=0;
start=clock();
for(int i=0;i<arraysize;i++) //CPU串行求最大值
{
*h_cpu=max(*h_cpu,h_in[i]);
}
end=clock();
time=end-start;
cout <<"cpu时间: "<<time/1000<<"ms"<<endl;
grid1=(arraysize-1)/k1+1; //设置网格大小(一维)
cout <<"网格1大小："<<grid1 <<endl;
grid2=(grid1-1)/k2+1; //设置网格大小(一维)
cout <<"网格2大小："<<grid2 <<endl;
cudaMalloc((void **)&d_in,arraybytes); //分配显存
cudaMalloc((void **)&d_tmp1,grid1*sizeof(int));
cudaMalloc((void **)&d_tmp2,grid2*sizeof(int));
cudaMalloc((void **)&d_out,sizeof(int));
/* for(int i=0;i<arraysize;i++)
{
cout << h_in[i] <<" ";
}
打印数据
*/
CHECK(cudaMemcpy(d_in,h_in,arraybytes,cudaMemcpyHostToDevice));
reduce<<<grid1,k1,k1*sizeof(int)>>>(d_in,d_tmp1,arraysize);
// CHECK(cudaDeviceSynchronize()); 检查核函数运行错误，输出错误位置及错误信息
reduce<<<grid2,k2,k2*sizeof(int)>>>(d_tmp1,d_tmp2,grid1);
// CHECK(cudaDeviceSynchronize());
reduce<<<1,grid2,grid2*sizeof(int)>>>(d_tmp2,d_out,grid2);
// CHECK(cudaDeviceSynchronize());
CHECK(cudaMemcpy(h_gpu,d_out,sizeof(int),cudaMemcpyDeviceToHost));
cout <<"cpu归约结果:"<<*h_cpu<<endl;
cout << "gpu归约结果:"<<*h_gpu <<endl;
free(h_in); //释放内存
free(h_cpu);
free(h_gpu);
cudaFree(d_in); //释放显存
cudaFree(d_tmp1);
cudaFree(d_tmp2);
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z6reducePiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00d0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00e0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0100*/ @!P1 BRA 0x1d0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0120*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0130*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0140*/ @!P1 IMAD R4, R3, 0x4, R0 ; /* 0x0000000403049824 */
/* 0x000fe200078e0200 */
/*0150*/ @!P1 LDS R2, [R7.X4] ; /* 0x0000000007029984 */
/* 0x000fe20000004800 */
/*0160*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0170*/ @!P1 LDS R5, [R4] ; /* 0x0000000004059984 */
/* 0x000e240000000800 */
/*0180*/ @!P1 IMNMX R2, R2, R5, !PT ; /* 0x0000000502029217 */
/* 0x001fca0007800200 */
/*0190*/ @!P1 STS [R7.X4], R2 ; /* 0x0000000207009388 */
/* 0x0001e80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01c0*/ @P1 BRA 0x130 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0200*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* 日期： 2019-1-24
* 时间： 14:42
* 姓名： 杨丰拓
*/
//******************************************************************************************************************//
//对大量数据进行归约操作（例如，最大，最小，求和等）可通过使用共享内存缩短归约操作的时间．
//本程序预设目标归约2^20~2^30个数据，核划分为一维网格一维线程块，通过三次归约操作求出最大值．
//实际可处理数据为0~2^26.
//本程序可以处理0~2^20个数据，但实际上相对与处理的数据来说代码略有多余．在处理0~2^10个数据时仅需调用一次核函数，
//在处理2^10~2^20个数据时仅需调用两次核函数．当需要处理的数据量达到2^26时，网格内x维度上有65536个块，而网格的x,
//y,z方向上的维度最大值是 65535 ，块的数量超出维度上限，所以会出现结果输出为零的情况．
//若需要处理更多的数据，那么网格的维度需要变为二维乃至三维才能正常处理．
//******************************************************************************************************************//
#include <iostream>
#include <cuda_runtime.h>
#include <stdio.h>
#define k1 1024
#define k2 1024
//检查宏，用于检测cuda编程出错位置及原因
#define CHECK(call) \
{ \
const cudaError_t error=call; \
if(error!=cudaSuccess) \
{ \
printf("Error:%s:%d,",__FILE__,__LINE__); \
printf("code:%d,reason:%s\n",error,cudaGetErrorString(error)); \
exit(1); \
} \
} \
using namespace std;
/* ＠property 核函数
* ＠func 归约求每个共享内存内的最大值
* ＠param_in in 指向待归约的数据
* ＠param_in num 输入的数据量
* ＠param_out out 指向数据的输出地址
*/
__global__ void reduce(int *in,int *out,int num)
{
int tid=threadIdx.x; //块内线程的索引
int idx=blockIdx.x*blockDim.x+threadIdx.x; //线程的实际索引
extern __shared__ int data[]; //共享内存，空间大小在核函数调用时(func<<<,,共享内存字节数>>>)分配
if(idx>=num)return; //防止索引越界
data[tid]=in[idx];
__syncthreads(); //等待共享内存拷贝数据结束
for(unsigned int s=blockDim.x/2;s>0;s>>=1) //块内归约操作
{
if(tid<s)
{
data[tid]=max(data[tid],data[tid+s]);
}
__syncthreads();
}
if(tid==0)out[blockIdx.x]=data[0]; //输出每个块内的归约结果
}
int main()
{
int a;
cout <<"数据量为2的几次方？(a<=25)"<<endl;
cin>>a;
int arraysize=1<<a;
int arraybytes=arraysize*sizeof(int);
int grid1,grid2;
int *h_in,*h_cpu,*h_gpu,*d_in,*d_out,*d_tmp1,*d_tmp2;
clock_t start,end;
double time;
h_in=(int *)malloc(arraybytes);
h_cpu=(int *)malloc(sizeof(int));
h_gpu=(int *)malloc(sizeof(int));
cout <<"数据量: "<<arraysize<<endl;
for(int i=0;i<arraysize;i++) //生成数据
{
//h_in[i]=(int)random();
h_in[i]=i;
}
*h_cpu=0;
start=clock();
for(int i=0;i<arraysize;i++) //CPU串行求最大值
{
*h_cpu=max(*h_cpu,h_in[i]);
}
end=clock();
time=end-start;
cout <<"cpu时间: "<<time/1000<<"ms"<<endl;
grid1=(arraysize-1)/k1+1; //设置网格大小(一维)
cout <<"网格1大小："<<grid1 <<endl;
grid2=(grid1-1)/k2+1; //设置网格大小(一维)
cout <<"网格2大小："<<grid2 <<endl;
cudaMalloc((void **)&d_in,arraybytes); //分配显存
cudaMalloc((void **)&d_tmp1,grid1*sizeof(int));
cudaMalloc((void **)&d_tmp2,grid2*sizeof(int));
cudaMalloc((void **)&d_out,sizeof(int));
/* for(int i=0;i<arraysize;i++)
{
cout << h_in[i] <<" ";
}
打印数据
*/
CHECK(cudaMemcpy(d_in,h_in,arraybytes,cudaMemcpyHostToDevice));
reduce<<<grid1,k1,k1*sizeof(int)>>>(d_in,d_tmp1,arraysize);
// CHECK(cudaDeviceSynchronize()); 检查核函数运行错误，输出错误位置及错误信息
reduce<<<grid2,k2,k2*sizeof(int)>>>(d_tmp1,d_tmp2,grid1);
// CHECK(cudaDeviceSynchronize());
reduce<<<1,grid2,grid2*sizeof(int)>>>(d_tmp2,d_out,grid2);
// CHECK(cudaDeviceSynchronize());
CHECK(cudaMemcpy(h_gpu,d_out,sizeof(int),cudaMemcpyDeviceToHost));
cout <<"cpu归约结果:"<<*h_cpu<<endl;
cout << "gpu归约结果:"<<*h_gpu <<endl;
free(h_in); //释放内存
free(h_cpu);
free(h_gpu);
cudaFree(d_in); //释放显存
cudaFree(d_tmp1);
cudaFree(d_tmp2);
cudaFree(d_out);
return 0;
} | .file "tmpxft_000143b1_00000000-6_reduce.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6reducePiS_iPiS_i
.type _Z28__device_stub__Z6reducePiS_iPiS_i, @function
_Z28__device_stub__Z6reducePiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reducePiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z28__device_stub__Z6reducePiS_iPiS_i, .-_Z28__device_stub__Z6reducePiS_iPiS_i
.globl _Z6reducePiS_i
.type _Z6reducePiS_i, @function
_Z6reducePiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6reducePiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6reducePiS_i, .-_Z6reducePiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\346\225\260\346\215\256\351\207\217\344\270\2722\347\232\204\345\207\240\346\254\241\346\226\271\357\274\237(a<=25)"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\346\225\260\346\215\256\351\207\217: "
.LC2:
.string "cpu\346\227\266\351\227\264: "
.LC4:
.string "ms"
.LC5:
.string "\347\275\221\346\240\2741\345\244\247\345\260\217\357\274\232"
.LC6:
.string "\347\275\221\346\240\2742\345\244\247\345\260\217\357\274\232"
.section .rodata.str1.8
.align 8
.LC7:
.string "/home/ubuntu/Datasets/stackv2/train-structured/yft1996/CUDA/master/reduce.cu"
.section .rodata.str1.1
.LC8:
.string "Error:%s:%d,"
.LC9:
.string "code:%d,reason:%s\n"
.LC10:
.string "cpu\345\275\222\347\272\246\347\273\223\346\236\234:"
.LC11:
.string "gpu\345\275\222\347\272\246\347\273\223\346\236\234:"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 28(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 28(%rsp), %ecx
movl $1, %r12d
sall %cl, %r12d
leal 0(,%r12,4), %eax
cltq
movq %rax, (%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %r14
movl $4, %edi
call malloc@PLT
movq %rax, %r13
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %r12d, %r12d
jle .L12
movslq %r12d, %r15
movl $0, %ebx
.L13:
movl %ebx, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq %rbx, %r15
jne .L13
call clock@PLT
movq %rax, %r15
movq %rbp, %rax
leaq 0(%rbp,%rbx,4), %rsi
movl $0, %edx
.L14:
movl (%rax), %ecx
cmpl %ecx, %edx
cmovl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L14
movl %edx, (%r14)
.L20:
call clock@PLT
subq %r15, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movq %xmm1, %rbx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
divsd .LC3(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leal 1022(%r12), %r15d
movl %r12d, %ebx
subl $1, %ebx
cmovns %ebx, %r15d
sarl $10, %r15d
addl $1, %r15d
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r15d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leal 1048574(%r12), %eax
testl %ebx, %ebx
cmovs %eax, %ebx
sarl $20, %ebx
addl $1, %ebx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 32(%rsp), %rdi
movq (%rsp), %rsi
call cudaMalloc@PLT
movslq %r15d, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movslq %ebx, %rax
salq $2, %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rdi
movq %rax, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq (%rsp), %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, (%rsp)
testl %eax, %eax
jne .L26
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r15d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L16:
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %ebx, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L17:
movl %ebx, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movq 8(%rsp), %r8
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L18:
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%r14), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 0(%r13), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl $114, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rsp), %ebx
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %r12d, %edx
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z28__device_stub__Z6reducePiS_iPiS_i
jmp .L16
.L28:
movl %r15d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z28__device_stub__Z6reducePiS_iPiS_i
jmp .L17
.L29:
movl %ebx, %edx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z28__device_stub__Z6reducePiS_iPiS_i
jmp .L18
.L30:
movl $121, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L12:
movl $0, (%r14)
call clock@PLT
movq %rax, %r15
jmp .L20
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z6reducePiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* 日期： 2019-1-24
* 时间： 14:42
* 姓名： 杨丰拓
*/
//******************************************************************************************************************//
//对大量数据进行归约操作（例如，最大，最小，求和等）可通过使用共享内存缩短归约操作的时间．
//本程序预设目标归约2^20~2^30个数据，核划分为一维网格一维线程块，通过三次归约操作求出最大值．
//实际可处理数据为0~2^26.
//本程序可以处理0~2^20个数据，但实际上相对与处理的数据来说代码略有多余．在处理0~2^10个数据时仅需调用一次核函数，
//在处理2^10~2^20个数据时仅需调用两次核函数．当需要处理的数据量达到2^26时，网格内x维度上有65536个块，而网格的x,
//y,z方向上的维度最大值是 65535 ，块的数量超出维度上限，所以会出现结果输出为零的情况．
//若需要处理更多的数据，那么网格的维度需要变为二维乃至三维才能正常处理．
//******************************************************************************************************************//
#include <iostream>
#include <cuda_runtime.h>
#include <stdio.h>
#define k1 1024
#define k2 1024
//检查宏，用于检测cuda编程出错位置及原因
#define CHECK(call) \
{ \
const cudaError_t error=call; \
if(error!=cudaSuccess) \
{ \
printf("Error:%s:%d,",__FILE__,__LINE__); \
printf("code:%d,reason:%s\n",error,cudaGetErrorString(error)); \
exit(1); \
} \
} \
using namespace std;
/* ＠property 核函数
* ＠func 归约求每个共享内存内的最大值
* ＠param_in in 指向待归约的数据
* ＠param_in num 输入的数据量
* ＠param_out out 指向数据的输出地址
*/
__global__ void reduce(int *in,int *out,int num)
{
int tid=threadIdx.x; //块内线程的索引
int idx=blockIdx.x*blockDim.x+threadIdx.x; //线程的实际索引
extern __shared__ int data[]; //共享内存，空间大小在核函数调用时(func<<<,,共享内存字节数>>>)分配
if(idx>=num)return; //防止索引越界
data[tid]=in[idx];
__syncthreads(); //等待共享内存拷贝数据结束
for(unsigned int s=blockDim.x/2;s>0;s>>=1) //块内归约操作
{
if(tid<s)
{
data[tid]=max(data[tid],data[tid+s]);
}
__syncthreads();
}
if(tid==0)out[blockIdx.x]=data[0]; //输出每个块内的归约结果
}
int main()
{
int a;
cout <<"数据量为2的几次方？(a<=25)"<<endl;
cin>>a;
int arraysize=1<<a;
int arraybytes=arraysize*sizeof(int);
int grid1,grid2;
int *h_in,*h_cpu,*h_gpu,*d_in,*d_out,*d_tmp1,*d_tmp2;
clock_t start,end;
double time;
h_in=(int *)malloc(arraybytes);
h_cpu=(int *)malloc(sizeof(int));
h_gpu=(int *)malloc(sizeof(int));
cout <<"数据量: "<<arraysize<<endl;
for(int i=0;i<arraysize;i++) //生成数据
{
//h_in[i]=(int)random();
h_in[i]=i;
}
*h_cpu=0;
start=clock();
for(int i=0;i<arraysize;i++) //CPU串行求最大值
{
*h_cpu=max(*h_cpu,h_in[i]);
}
end=clock();
time=end-start;
cout <<"cpu时间: "<<time/1000<<"ms"<<endl;
grid1=(arraysize-1)/k1+1; //设置网格大小(一维)
cout <<"网格1大小："<<grid1 <<endl;
grid2=(grid1-1)/k2+1; //设置网格大小(一维)
cout <<"网格2大小："<<grid2 <<endl;
cudaMalloc((void **)&d_in,arraybytes); //分配显存
cudaMalloc((void **)&d_tmp1,grid1*sizeof(int));
cudaMalloc((void **)&d_tmp2,grid2*sizeof(int));
cudaMalloc((void **)&d_out,sizeof(int));
/* for(int i=0;i<arraysize;i++)
{
cout << h_in[i] <<" ";
}
打印数据
*/
CHECK(cudaMemcpy(d_in,h_in,arraybytes,cudaMemcpyHostToDevice));
reduce<<<grid1,k1,k1*sizeof(int)>>>(d_in,d_tmp1,arraysize);
// CHECK(cudaDeviceSynchronize()); 检查核函数运行错误，输出错误位置及错误信息
reduce<<<grid2,k2,k2*sizeof(int)>>>(d_tmp1,d_tmp2,grid1);
// CHECK(cudaDeviceSynchronize());
reduce<<<1,grid2,grid2*sizeof(int)>>>(d_tmp2,d_out,grid2);
// CHECK(cudaDeviceSynchronize());
CHECK(cudaMemcpy(h_gpu,d_out,sizeof(int),cudaMemcpyDeviceToHost));
cout <<"cpu归约结果:"<<*h_cpu<<endl;
cout << "gpu归约结果:"<<*h_gpu <<endl;
free(h_in); //释放内存
free(h_cpu);
free(h_gpu);
cudaFree(d_in); //释放显存
cudaFree(d_tmp1);
cudaFree(d_tmp2);
cudaFree(d_out);
return 0;
} | /*
* 日期： 2019-1-24
* 时间： 14:42
* 姓名： 杨丰拓
*/
//******************************************************************************************************************//
//对大量数据进行归约操作（例如，最大，最小，求和等）可通过使用共享内存缩短归约操作的时间．
//本程序预设目标归约2^20~2^30个数据，核划分为一维网格一维线程块，通过三次归约操作求出最大值．
//实际可处理数据为0~2^26.
//本程序可以处理0~2^20个数据，但实际上相对与处理的数据来说代码略有多余．在处理0~2^10个数据时仅需调用一次核函数，
//在处理2^10~2^20个数据时仅需调用两次核函数．当需要处理的数据量达到2^26时，网格内x维度上有65536个块，而网格的x,
//y,z方向上的维度最大值是 65535 ，块的数量超出维度上限，所以会出现结果输出为零的情况．
//若需要处理更多的数据，那么网格的维度需要变为二维乃至三维才能正常处理．
//******************************************************************************************************************//
#include <iostream>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define k1 1024
#define k2 1024
//检查宏，用于检测cuda编程出错位置及原因
#define CHECK(call) \
{ \
const hipError_t error=call; \
if(error!=hipSuccess) \
{ \
printf("Error:%s:%d,",__FILE__,__LINE__); \
printf("code:%d,reason:%s\n",error,hipGetErrorString(error)); \
exit(1); \
} \
} \
using namespace std;
/* ＠property 核函数
* ＠func 归约求每个共享内存内的最大值
* ＠param_in in 指向待归约的数据
* ＠param_in num 输入的数据量
* ＠param_out out 指向数据的输出地址
*/
__global__ void reduce(int *in,int *out,int num)
{
int tid=threadIdx.x; //块内线程的索引
int idx=blockIdx.x*blockDim.x+threadIdx.x; //线程的实际索引
extern __shared__ int data[]; //共享内存，空间大小在核函数调用时(func<<<,,共享内存字节数>>>)分配
if(idx>=num)return; //防止索引越界
data[tid]=in[idx];
__syncthreads(); //等待共享内存拷贝数据结束
for(unsigned int s=blockDim.x/2;s>0;s>>=1) //块内归约操作
{
if(tid<s)
{
data[tid]=max(data[tid],data[tid+s]);
}
__syncthreads();
}
if(tid==0)out[blockIdx.x]=data[0]; //输出每个块内的归约结果
}
int main()
{
int a;
cout <<"数据量为2的几次方？(a<=25)"<<endl;
cin>>a;
int arraysize=1<<a;
int arraybytes=arraysize*sizeof(int);
int grid1,grid2;
int *h_in,*h_cpu,*h_gpu,*d_in,*d_out,*d_tmp1,*d_tmp2;
clock_t start,end;
double time;
h_in=(int *)malloc(arraybytes);
h_cpu=(int *)malloc(sizeof(int));
h_gpu=(int *)malloc(sizeof(int));
cout <<"数据量: "<<arraysize<<endl;
for(int i=0;i<arraysize;i++) //生成数据
{
//h_in[i]=(int)random();
h_in[i]=i;
}
*h_cpu=0;
start=clock();
for(int i=0;i<arraysize;i++) //CPU串行求最大值
{
*h_cpu=max(*h_cpu,h_in[i]);
}
end=clock();
time=end-start;
cout <<"cpu时间: "<<time/1000<<"ms"<<endl;
grid1=(arraysize-1)/k1+1; //设置网格大小(一维)
cout <<"网格1大小："<<grid1 <<endl;
grid2=(grid1-1)/k2+1; //设置网格大小(一维)
cout <<"网格2大小："<<grid2 <<endl;
hipMalloc((void **)&d_in,arraybytes); //分配显存
hipMalloc((void **)&d_tmp1,grid1*sizeof(int));
hipMalloc((void **)&d_tmp2,grid2*sizeof(int));
hipMalloc((void **)&d_out,sizeof(int));
/* for(int i=0;i<arraysize;i++)
{
cout << h_in[i] <<" ";
}
打印数据
*/
CHECK(hipMemcpy(d_in,h_in,arraybytes,hipMemcpyHostToDevice));
reduce<<<grid1,k1,k1*sizeof(int)>>>(d_in,d_tmp1,arraysize);
// CHECK(cudaDeviceSynchronize()); 检查核函数运行错误，输出错误位置及错误信息
reduce<<<grid2,k2,k2*sizeof(int)>>>(d_tmp1,d_tmp2,grid1);
// CHECK(cudaDeviceSynchronize());
reduce<<<1,grid2,grid2*sizeof(int)>>>(d_tmp2,d_out,grid2);
// CHECK(cudaDeviceSynchronize());
CHECK(hipMemcpy(h_gpu,d_out,sizeof(int),hipMemcpyDeviceToHost));
cout <<"cpu归约结果:"<<*h_cpu<<endl;
cout << "gpu归约结果:"<<*h_gpu <<endl;
free(h_in); //释放内存
free(h_cpu);
free(h_gpu);
hipFree(d_in); //释放显存
hipFree(d_tmp1);
hipFree(d_tmp2);
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* 日期： 2019-1-24
* 时间： 14:42
* 姓名： 杨丰拓
*/
//******************************************************************************************************************//
//对大量数据进行归约操作（例如，最大，最小，求和等）可通过使用共享内存缩短归约操作的时间．
//本程序预设目标归约2^20~2^30个数据，核划分为一维网格一维线程块，通过三次归约操作求出最大值．
//实际可处理数据为0~2^26.
//本程序可以处理0~2^20个数据，但实际上相对与处理的数据来说代码略有多余．在处理0~2^10个数据时仅需调用一次核函数，
//在处理2^10~2^20个数据时仅需调用两次核函数．当需要处理的数据量达到2^26时，网格内x维度上有65536个块，而网格的x,
//y,z方向上的维度最大值是 65535 ，块的数量超出维度上限，所以会出现结果输出为零的情况．
//若需要处理更多的数据，那么网格的维度需要变为二维乃至三维才能正常处理．
//******************************************************************************************************************//
#include <iostream>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define k1 1024
#define k2 1024
//检查宏，用于检测cuda编程出错位置及原因
#define CHECK(call) \
{ \
const hipError_t error=call; \
if(error!=hipSuccess) \
{ \
printf("Error:%s:%d,",__FILE__,__LINE__); \
printf("code:%d,reason:%s\n",error,hipGetErrorString(error)); \
exit(1); \
} \
} \
using namespace std;
/* ＠property 核函数
* ＠func 归约求每个共享内存内的最大值
* ＠param_in in 指向待归约的数据
* ＠param_in num 输入的数据量
* ＠param_out out 指向数据的输出地址
*/
__global__ void reduce(int *in,int *out,int num)
{
int tid=threadIdx.x; //块内线程的索引
int idx=blockIdx.x*blockDim.x+threadIdx.x; //线程的实际索引
extern __shared__ int data[]; //共享内存，空间大小在核函数调用时(func<<<,,共享内存字节数>>>)分配
if(idx>=num)return; //防止索引越界
data[tid]=in[idx];
__syncthreads(); //等待共享内存拷贝数据结束
for(unsigned int s=blockDim.x/2;s>0;s>>=1) //块内归约操作
{
if(tid<s)
{
data[tid]=max(data[tid],data[tid+s]);
}
__syncthreads();
}
if(tid==0)out[blockIdx.x]=data[0]; //输出每个块内的归约结果
}
int main()
{
int a;
cout <<"数据量为2的几次方？(a<=25)"<<endl;
cin>>a;
int arraysize=1<<a;
int arraybytes=arraysize*sizeof(int);
int grid1,grid2;
int *h_in,*h_cpu,*h_gpu,*d_in,*d_out,*d_tmp1,*d_tmp2;
clock_t start,end;
double time;
h_in=(int *)malloc(arraybytes);
h_cpu=(int *)malloc(sizeof(int));
h_gpu=(int *)malloc(sizeof(int));
cout <<"数据量: "<<arraysize<<endl;
for(int i=0;i<arraysize;i++) //生成数据
{
//h_in[i]=(int)random();
h_in[i]=i;
}
*h_cpu=0;
start=clock();
for(int i=0;i<arraysize;i++) //CPU串行求最大值
{
*h_cpu=max(*h_cpu,h_in[i]);
}
end=clock();
time=end-start;
cout <<"cpu时间: "<<time/1000<<"ms"<<endl;
grid1=(arraysize-1)/k1+1; //设置网格大小(一维)
cout <<"网格1大小："<<grid1 <<endl;
grid2=(grid1-1)/k2+1; //设置网格大小(一维)
cout <<"网格2大小："<<grid2 <<endl;
hipMalloc((void **)&d_in,arraybytes); //分配显存
hipMalloc((void **)&d_tmp1,grid1*sizeof(int));
hipMalloc((void **)&d_tmp2,grid2*sizeof(int));
hipMalloc((void **)&d_out,sizeof(int));
/* for(int i=0;i<arraysize;i++)
{
cout << h_in[i] <<" ";
}
打印数据
*/
CHECK(hipMemcpy(d_in,h_in,arraybytes,hipMemcpyHostToDevice));
reduce<<<grid1,k1,k1*sizeof(int)>>>(d_in,d_tmp1,arraysize);
// CHECK(cudaDeviceSynchronize()); 检查核函数运行错误，输出错误位置及错误信息
reduce<<<grid2,k2,k2*sizeof(int)>>>(d_tmp1,d_tmp2,grid1);
// CHECK(cudaDeviceSynchronize());
reduce<<<1,grid2,grid2*sizeof(int)>>>(d_tmp2,d_out,grid2);
// CHECK(cudaDeviceSynchronize());
CHECK(hipMemcpy(h_gpu,d_out,sizeof(int),hipMemcpyDeviceToHost));
cout <<"cpu归约结果:"<<*h_cpu<<endl;
cout << "gpu归约结果:"<<*h_gpu <<endl;
free(h_in); //释放内存
free(h_cpu);
free(h_gpu);
hipFree(d_in); //释放显存
hipFree(d_tmp1);
hipFree(d_tmp2);
hipFree(d_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6reducePiS_i
.globl _Z6reducePiS_i
.p2align 8
.type _Z6reducePiS_i,@function
_Z6reducePiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_u32 s3, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_3:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_6:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reducePiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6reducePiS_i, .Lfunc_end0-_Z6reducePiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reducePiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reducePiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* 日期： 2019-1-24
* 时间： 14:42
* 姓名： 杨丰拓
*/
//******************************************************************************************************************//
//对大量数据进行归约操作（例如，最大，最小，求和等）可通过使用共享内存缩短归约操作的时间．
//本程序预设目标归约2^20~2^30个数据，核划分为一维网格一维线程块，通过三次归约操作求出最大值．
//实际可处理数据为0~2^26.
//本程序可以处理0~2^20个数据，但实际上相对与处理的数据来说代码略有多余．在处理0~2^10个数据时仅需调用一次核函数，
//在处理2^10~2^20个数据时仅需调用两次核函数．当需要处理的数据量达到2^26时，网格内x维度上有65536个块，而网格的x,
//y,z方向上的维度最大值是 65535 ，块的数量超出维度上限，所以会出现结果输出为零的情况．
//若需要处理更多的数据，那么网格的维度需要变为二维乃至三维才能正常处理．
//******************************************************************************************************************//
#include <iostream>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define k1 1024
#define k2 1024
//检查宏，用于检测cuda编程出错位置及原因
#define CHECK(call) \
{ \
const hipError_t error=call; \
if(error!=hipSuccess) \
{ \
printf("Error:%s:%d,",__FILE__,__LINE__); \
printf("code:%d,reason:%s\n",error,hipGetErrorString(error)); \
exit(1); \
} \
} \
using namespace std;
/* ＠property 核函数
* ＠func 归约求每个共享内存内的最大值
* ＠param_in in 指向待归约的数据
* ＠param_in num 输入的数据量
* ＠param_out out 指向数据的输出地址
*/
__global__ void reduce(int *in,int *out,int num)
{
int tid=threadIdx.x; //块内线程的索引
int idx=blockIdx.x*blockDim.x+threadIdx.x; //线程的实际索引
extern __shared__ int data[]; //共享内存，空间大小在核函数调用时(func<<<,,共享内存字节数>>>)分配
if(idx>=num)return; //防止索引越界
data[tid]=in[idx];
__syncthreads(); //等待共享内存拷贝数据结束
for(unsigned int s=blockDim.x/2;s>0;s>>=1) //块内归约操作
{
if(tid<s)
{
data[tid]=max(data[tid],data[tid+s]);
}
__syncthreads();
}
if(tid==0)out[blockIdx.x]=data[0]; //输出每个块内的归约结果
}
int main()
{
int a;
cout <<"数据量为2的几次方？(a<=25)"<<endl;
cin>>a;
int arraysize=1<<a;
int arraybytes=arraysize*sizeof(int);
int grid1,grid2;
int *h_in,*h_cpu,*h_gpu,*d_in,*d_out,*d_tmp1,*d_tmp2;
clock_t start,end;
double time;
h_in=(int *)malloc(arraybytes);
h_cpu=(int *)malloc(sizeof(int));
h_gpu=(int *)malloc(sizeof(int));
cout <<"数据量: "<<arraysize<<endl;
for(int i=0;i<arraysize;i++) //生成数据
{
//h_in[i]=(int)random();
h_in[i]=i;
}
*h_cpu=0;
start=clock();
for(int i=0;i<arraysize;i++) //CPU串行求最大值
{
*h_cpu=max(*h_cpu,h_in[i]);
}
end=clock();
time=end-start;
cout <<"cpu时间: "<<time/1000<<"ms"<<endl;
grid1=(arraysize-1)/k1+1; //设置网格大小(一维)
cout <<"网格1大小："<<grid1 <<endl;
grid2=(grid1-1)/k2+1; //设置网格大小(一维)
cout <<"网格2大小："<<grid2 <<endl;
hipMalloc((void **)&d_in,arraybytes); //分配显存
hipMalloc((void **)&d_tmp1,grid1*sizeof(int));
hipMalloc((void **)&d_tmp2,grid2*sizeof(int));
hipMalloc((void **)&d_out,sizeof(int));
/* for(int i=0;i<arraysize;i++)
{
cout << h_in[i] <<" ";
}
打印数据
*/
CHECK(hipMemcpy(d_in,h_in,arraybytes,hipMemcpyHostToDevice));
reduce<<<grid1,k1,k1*sizeof(int)>>>(d_in,d_tmp1,arraysize);
// CHECK(cudaDeviceSynchronize()); 检查核函数运行错误，输出错误位置及错误信息
reduce<<<grid2,k2,k2*sizeof(int)>>>(d_tmp1,d_tmp2,grid1);
// CHECK(cudaDeviceSynchronize());
reduce<<<1,grid2,grid2*sizeof(int)>>>(d_tmp2,d_out,grid2);
// CHECK(cudaDeviceSynchronize());
CHECK(hipMemcpy(h_gpu,d_out,sizeof(int),hipMemcpyDeviceToHost));
cout <<"cpu归约结果:"<<*h_cpu<<endl;
cout << "gpu归约结果:"<<*h_gpu <<endl;
free(h_in); //释放内存
free(h_cpu);
free(h_gpu);
hipFree(d_in); //释放显存
hipFree(d_tmp1);
hipFree(d_tmp2);
hipFree(d_out);
return 0;
} | .text
.file "reduce.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__reducePiS_i # -- Begin function _Z21__device_stub__reducePiS_i
.p2align 4, 0x90
.type _Z21__device_stub__reducePiS_i,@function
_Z21__device_stub__reducePiS_i: # @_Z21__device_stub__reducePiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__reducePiS_i, .Lfunc_end0-_Z21__device_stub__reducePiS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_47
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 148(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 148(%rsp), %ebp
movl $1, %r12d
movl %ebp, %ecx
shll %cl, %r12d
movl $4, %eax
shll %cl, %eax
movslq %eax, %rdi
movq %rdi, 168(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r13
movl $4, %edi
callq malloc
movq %rax, 160(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_47
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i78
cmpb $0, 56(%r14)
je .LBB1_7
# %bb.6:
movzbl 67(%r14), %ecx
jmp .LBB1_8
.LBB1_7:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit81
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $31, %ebp
je .LBB1_11
# %bb.9: # %.lr.ph.preheader
cmpl $2, %r12d
movl $1, %eax
cmovgel %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_10
.LBB1_11: # %._crit_edge
movl $0, (%r13)
callq clock
movq %rax, %r14
cmpl $31, %ebp
je .LBB1_15
# %bb.12: # %.lr.ph125
movl (%r13), %eax
cmpl $2, %r12d
movl $1, %ecx
cmovgel %r12d, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
movl %eax, %esi
movl (%rbx,%rdx,4), %eax
cmpl %eax, %esi
cmovgl %esi, %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB1_13
# %bb.14: # %._crit_edge126
movl %eax, (%r13)
.LBB1_15:
callq clock
subq %r14, %rax
cvtsi2sd %rax, %xmm0
movsd %xmm0, 176(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI1_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_47
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i83
cmpb $0, 56(%r15)
movq %r13, 152(%rsp) # 8-byte Spill
je .LBB1_18
# %bb.17:
movzbl 67(%r15), %eax
jmp .LBB1_19
.LBB1_18:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit86
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leal -1(%r12), %r13d
leal 1022(%r12), %ebp
testl %r13d, %r13d
cmovnsl %r13d, %ebp
sarl $10, %ebp
incl %ebp
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_47
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i88
cmpb $0, 56(%r14)
je .LBB1_22
# %bb.21:
movzbl 67(%r14), %ecx
jmp .LBB1_23
.LBB1_22:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit91
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leal 1048575(%r13), %r15d
testl %r13d, %r13d
cmovnsl %r13d, %r15d
sarl $20, %r15d
incl %r15d
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_47
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i93
cmpb $0, 56(%r14)
je .LBB1_26
# %bb.25:
movzbl 67(%r14), %ecx
jmp .LBB1_27
.LBB1_26:
movq %r14, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit96
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 136(%rsp), %rdi
movq 168(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
callq hipMalloc
movslq %ebp, %rsi
shlq $2, %rsi
leaq 120(%rsp), %rdi
callq hipMalloc
movslq %r15d, %r14
shlq $2, %r14
leaq 112(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 128(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 136(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_28
# %bb.30:
movabsq $4294967296, %r13 # imm = 0x100000000
movl %ebp, %edi
orq %r13, %rdi
leaq 1024(%r13), %rdx
movl $4096, %r8d # imm = 0x1000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_32
# %bb.31:
movq 136(%rsp), %rax
movq 120(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r12d, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_32:
movl %r15d, %r12d
orq %r13, %r12
leaq 1024(%r13), %rdx
movl $4096, %r8d # imm = 0x1000
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_34
# %bb.33:
movq 120(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %ebp, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_34:
incq %r13
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
movq %r14, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_36
# %bb.35:
movq 112(%rsp), %rax
movq 128(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r15d, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_36:
movq 128(%rsp), %rsi
movl $4, %edx
movq 160(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
movq 152(%rsp), %r12 # 8-byte Reload
jne .LBB1_37
# %bb.38:
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r12), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_47
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i98
cmpb $0, 56(%r14)
je .LBB1_41
# %bb.40:
movzbl 67(%r14), %ecx
jmp .LBB1_42
.LBB1_41:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit101
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r13), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_47
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i103
cmpb $0, 56(%r14)
je .LBB1_45
# %bb.44:
movzbl 67(%r14), %ecx
jmp .LBB1_46
.LBB1_45:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit106
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq 136(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_47:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.LBB1_28:
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $114, %edx
jmp .LBB1_29
.LBB1_37:
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $121, %edx
.LBB1_29:
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6reducePiS_i,@object # @_Z6reducePiS_i
.section .rodata,"a",@progbits
.globl _Z6reducePiS_i
.p2align 3, 0x0
_Z6reducePiS_i:
.quad _Z21__device_stub__reducePiS_i
.size _Z6reducePiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\346\225\260\346\215\256\351\207\217\344\270\2722\347\232\204\345\207\240\346\254\241\346\226\271\357\274\237(a<=25)"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\346\225\260\346\215\256\351\207\217: "
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cpu\346\227\266\351\227\264: "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ms"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\347\275\221\346\240\2741\345\244\247\345\260\217\357\274\232"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\347\275\221\346\240\2742\345\244\247\345\260\217\357\274\232"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error:%s:%d,"
.size .L.str.6, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/yft1996/CUDA/master/reduce.hip"
.size .L.str.7, 88
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "code:%d,reason:%s\n"
.size .L.str.8, 19
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "cpu\345\275\222\347\272\246\347\273\223\346\236\234:"
.size .L.str.9, 17
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "gpu\345\275\222\347\272\246\347\273\223\346\236\234:"
.size .L.str.10, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6reducePiS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__reducePiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6reducePiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6reducePiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00d0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00e0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0100*/ @!P1 BRA 0x1d0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0120*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0130*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0140*/ @!P1 IMAD R4, R3, 0x4, R0 ; /* 0x0000000403049824 */
/* 0x000fe200078e0200 */
/*0150*/ @!P1 LDS R2, [R7.X4] ; /* 0x0000000007029984 */
/* 0x000fe20000004800 */
/*0160*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0170*/ @!P1 LDS R5, [R4] ; /* 0x0000000004059984 */
/* 0x000e240000000800 */
/*0180*/ @!P1 IMNMX R2, R2, R5, !PT ; /* 0x0000000502029217 */
/* 0x001fca0007800200 */
/*0190*/ @!P1 STS [R7.X4], R2 ; /* 0x0000000207009388 */
/* 0x0001e80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01c0*/ @P1 BRA 0x130 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0200*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6reducePiS_i
.globl _Z6reducePiS_i
.p2align 8
.type _Z6reducePiS_i,@function
_Z6reducePiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_u32 s3, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_3:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_max_i32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_6:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reducePiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6reducePiS_i, .Lfunc_end0-_Z6reducePiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reducePiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reducePiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000143b1_00000000-6_reduce.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z6reducePiS_iPiS_i
.type _Z28__device_stub__Z6reducePiS_iPiS_i, @function
_Z28__device_stub__Z6reducePiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reducePiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z28__device_stub__Z6reducePiS_iPiS_i, .-_Z28__device_stub__Z6reducePiS_iPiS_i
.globl _Z6reducePiS_i
.type _Z6reducePiS_i, @function
_Z6reducePiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6reducePiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6reducePiS_i, .-_Z6reducePiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\346\225\260\346\215\256\351\207\217\344\270\2722\347\232\204\345\207\240\346\254\241\346\226\271\357\274\237(a<=25)"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\346\225\260\346\215\256\351\207\217: "
.LC2:
.string "cpu\346\227\266\351\227\264: "
.LC4:
.string "ms"
.LC5:
.string "\347\275\221\346\240\2741\345\244\247\345\260\217\357\274\232"
.LC6:
.string "\347\275\221\346\240\2742\345\244\247\345\260\217\357\274\232"
.section .rodata.str1.8
.align 8
.LC7:
.string "/home/ubuntu/Datasets/stackv2/train-structured/yft1996/CUDA/master/reduce.cu"
.section .rodata.str1.1
.LC8:
.string "Error:%s:%d,"
.LC9:
.string "code:%d,reason:%s\n"
.LC10:
.string "cpu\345\275\222\347\272\246\347\273\223\346\236\234:"
.LC11:
.string "gpu\345\275\222\347\272\246\347\273\223\346\236\234:"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 28(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 28(%rsp), %ecx
movl $1, %r12d
sall %cl, %r12d
leal 0(,%r12,4), %eax
cltq
movq %rax, (%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %r14
movl $4, %edi
call malloc@PLT
movq %rax, %r13
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %r12d, %r12d
jle .L12
movslq %r12d, %r15
movl $0, %ebx
.L13:
movl %ebx, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq %rbx, %r15
jne .L13
call clock@PLT
movq %rax, %r15
movq %rbp, %rax
leaq 0(%rbp,%rbx,4), %rsi
movl $0, %edx
.L14:
movl (%rax), %ecx
cmpl %ecx, %edx
cmovl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L14
movl %edx, (%r14)
.L20:
call clock@PLT
subq %r15, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movq %xmm1, %rbx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
divsd .LC3(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leal 1022(%r12), %r15d
movl %r12d, %ebx
subl $1, %ebx
cmovns %ebx, %r15d
sarl $10, %r15d
addl $1, %r15d
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r15d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leal 1048574(%r12), %eax
testl %ebx, %ebx
cmovs %eax, %ebx
sarl $20, %ebx
addl $1, %ebx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 32(%rsp), %rdi
movq (%rsp), %rsi
call cudaMalloc@PLT
movslq %r15d, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movslq %ebx, %rax
salq $2, %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rdi
movq %rax, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq (%rsp), %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, (%rsp)
testl %eax, %eax
jne .L26
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r15d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L16:
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %ebx, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L17:
movl %ebx, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movq 8(%rsp), %r8
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L18:
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%r14), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 0(%r13), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl $114, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rsp), %ebx
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %r12d, %edx
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z28__device_stub__Z6reducePiS_iPiS_i
jmp .L16
.L28:
movl %r15d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z28__device_stub__Z6reducePiS_iPiS_i
jmp .L17
.L29:
movl %ebx, %edx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z28__device_stub__Z6reducePiS_iPiS_i
jmp .L18
.L30:
movl $121, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L12:
movl $0, (%r14)
call clock@PLT
movq %rax, %r15
jmp .L20
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z6reducePiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduce.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__reducePiS_i # -- Begin function _Z21__device_stub__reducePiS_i
.p2align 4, 0x90
.type _Z21__device_stub__reducePiS_i,@function
_Z21__device_stub__reducePiS_i: # @_Z21__device_stub__reducePiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__reducePiS_i, .Lfunc_end0-_Z21__device_stub__reducePiS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_47
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 148(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 148(%rsp), %ebp
movl $1, %r12d
movl %ebp, %ecx
shll %cl, %r12d
movl $4, %eax
shll %cl, %eax
movslq %eax, %rdi
movq %rdi, 168(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r13
movl $4, %edi
callq malloc
movq %rax, 160(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_47
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i78
cmpb $0, 56(%r14)
je .LBB1_7
# %bb.6:
movzbl 67(%r14), %ecx
jmp .LBB1_8
.LBB1_7:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit81
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $31, %ebp
je .LBB1_11
# %bb.9: # %.lr.ph.preheader
cmpl $2, %r12d
movl $1, %eax
cmovgel %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_10
.LBB1_11: # %._crit_edge
movl $0, (%r13)
callq clock
movq %rax, %r14
cmpl $31, %ebp
je .LBB1_15
# %bb.12: # %.lr.ph125
movl (%r13), %eax
cmpl $2, %r12d
movl $1, %ecx
cmovgel %r12d, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_13: # =>This Inner Loop Header: Depth=1
movl %eax, %esi
movl (%rbx,%rdx,4), %eax
cmpl %eax, %esi
cmovgl %esi, %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB1_13
# %bb.14: # %._crit_edge126
movl %eax, (%r13)
.LBB1_15:
callq clock
subq %r14, %rax
cvtsi2sd %rax, %xmm0
movsd %xmm0, 176(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI1_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.3, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_47
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i83
cmpb $0, 56(%r15)
movq %r13, 152(%rsp) # 8-byte Spill
je .LBB1_18
# %bb.17:
movzbl 67(%r15), %eax
jmp .LBB1_19
.LBB1_18:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit86
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leal -1(%r12), %r13d
leal 1022(%r12), %ebp
testl %r13d, %r13d
cmovnsl %r13d, %ebp
sarl $10, %ebp
incl %ebp
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_47
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i88
cmpb $0, 56(%r14)
je .LBB1_22
# %bb.21:
movzbl 67(%r14), %ecx
jmp .LBB1_23
.LBB1_22:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit91
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leal 1048575(%r13), %r15d
testl %r13d, %r13d
cmovnsl %r13d, %r15d
sarl $20, %r15d
incl %r15d
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_47
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i93
cmpb $0, 56(%r14)
je .LBB1_26
# %bb.25:
movzbl 67(%r14), %ecx
jmp .LBB1_27
.LBB1_26:
movq %r14, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit96
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 136(%rsp), %rdi
movq 168(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
callq hipMalloc
movslq %ebp, %rsi
shlq $2, %rsi
leaq 120(%rsp), %rdi
callq hipMalloc
movslq %r15d, %r14
shlq $2, %r14
leaq 112(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 128(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 136(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_28
# %bb.30:
movabsq $4294967296, %r13 # imm = 0x100000000
movl %ebp, %edi
orq %r13, %rdi
leaq 1024(%r13), %rdx
movl $4096, %r8d # imm = 0x1000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_32
# %bb.31:
movq 136(%rsp), %rax
movq 120(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r12d, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_32:
movl %r15d, %r12d
orq %r13, %r12
leaq 1024(%r13), %rdx
movl $4096, %r8d # imm = 0x1000
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_34
# %bb.33:
movq 120(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %ebp, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_34:
incq %r13
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
movq %r14, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_36
# %bb.35:
movq 112(%rsp), %rax
movq 128(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r15d, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_36:
movq 128(%rsp), %rsi
movl $4, %edx
movq 160(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
movq 152(%rsp), %r12 # 8-byte Reload
jne .LBB1_37
# %bb.38:
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r12), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_47
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i98
cmpb $0, 56(%r14)
je .LBB1_41
# %bb.40:
movzbl 67(%r14), %ecx
jmp .LBB1_42
.LBB1_41:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit101
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r13), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_47
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i103
cmpb $0, 56(%r14)
je .LBB1_45
# %bb.44:
movzbl 67(%r14), %ecx
jmp .LBB1_46
.LBB1_45:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit106
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq 136(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_47:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.LBB1_28:
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $114, %edx
jmp .LBB1_29
.LBB1_37:
movl $.L.str.6, %edi
movl $.L.str.7, %esi
movl $121, %edx
.LBB1_29:
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6reducePiS_i,@object # @_Z6reducePiS_i
.section .rodata,"a",@progbits
.globl _Z6reducePiS_i
.p2align 3, 0x0
_Z6reducePiS_i:
.quad _Z21__device_stub__reducePiS_i
.size _Z6reducePiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\346\225\260\346\215\256\351\207\217\344\270\2722\347\232\204\345\207\240\346\254\241\346\226\271\357\274\237(a<=25)"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\346\225\260\346\215\256\351\207\217: "
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cpu\346\227\266\351\227\264: "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ms"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\347\275\221\346\240\2741\345\244\247\345\260\217\357\274\232"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\347\275\221\346\240\2742\345\244\247\345\260\217\357\274\232"
.size .L.str.5, 17
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error:%s:%d,"
.size .L.str.6, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/yft1996/CUDA/master/reduce.hip"
.size .L.str.7, 88
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "code:%d,reason:%s\n"
.size .L.str.8, 19
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "cpu\345\275\222\347\272\246\347\273\223\346\236\234:"
.size .L.str.9, 17
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "gpu\345\275\222\347\272\246\347\273\223\346\236\234:"
.size .L.str.10, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6reducePiS_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__reducePiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6reducePiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //TEST CASE PASS IN GPU_VERIFY. IT IS NOT VERIFY ARRAY BOUNDS VIOLATION
#include <stdio.h>
#include <cuda.h>
#include <assert.h>
#define N 2//64
__global__ void foo(int* p) {
int* q;
q = p + 1;
p[threadIdx.x] = q[threadIdx.x];
} | code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //TEST CASE PASS IN GPU_VERIFY. IT IS NOT VERIFY ARRAY BOUNDS VIOLATION
#include <stdio.h>
#include <cuda.h>
#include <assert.h>
#define N 2//64
__global__ void foo(int* p) {
int* q;
q = p + 1;
p[threadIdx.x] = q[threadIdx.x];
} | .file "tmpxft_0010e575_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z3fooPi, .-_Z3fooPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //TEST CASE PASS IN GPU_VERIFY. IT IS NOT VERIFY ARRAY BOUNDS VIOLATION
#include <stdio.h>
#include <cuda.h>
#include <assert.h>
#define N 2//64
__global__ void foo(int* p) {
int* q;
q = p + 1;
p[threadIdx.x] = q[threadIdx.x];
} | //TEST CASE PASS IN GPU_VERIFY. IT IS NOT VERIFY ARRAY BOUNDS VIOLATION
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <assert.h>
#define N 2//64
__global__ void foo(int* p) {
int* q;
q = p + 1;
p[threadIdx.x] = q[threadIdx.x];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //TEST CASE PASS IN GPU_VERIFY. IT IS NOT VERIFY ARRAY BOUNDS VIOLATION
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <assert.h>
#define N 2//64
__global__ void foo(int* p) {
int* q;
q = p + 1;
p[threadIdx.x] = q[threadIdx.x];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1] offset:4
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //TEST CASE PASS IN GPU_VERIFY. IT IS NOT VERIFY ARRAY BOUNDS VIOLATION
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <assert.h>
#define N 2//64
__global__ void foo(int* p) {
int* q;
q = p + 1;
p[threadIdx.x] = q[threadIdx.x];
} | .text
.file "main.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1] offset:4
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010e575_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z3fooPi, .-_Z3fooPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cstdio>
using namespace std;
__global__ void add(const int *a, const int *b, int *c)
{
int i = threadIdx.x;
c[i] = a[i] * *b;
}
int main(void)
{
int count = 100;
int size = sizeof(int) * count;
int *cpu_a = (int *)malloc(size); int *gpu_a; cudaMalloc((void**)&gpu_a, size);
int cpu_b = 5; int *gpu_b; cudaMalloc((void**)&gpu_b, sizeof(int));
int *cpu_c = (int *)malloc(size); int *gpu_c; cudaMalloc((void**)&gpu_c, size);
for(int i=0; i<count; i++) cpu_a[i]=i;
cudaMemcpy(gpu_a, cpu_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_b, &cpu_b, sizeof(int), cudaMemcpyHostToDevice);
add<<<1, count>>>(gpu_a, gpu_b, gpu_c);
cudaMemcpy(cpu_c, gpu_c, size, cudaMemcpyDeviceToHost);
for(int i=0; i<count; i++)
printf("%d * %d = %dn", cpu_a[i], cpu_b, cpu_c[i]);
free(cpu_a); cudaFree(gpu_a);
cudaFree(gpu_b);
free(cpu_c); cudaFree(gpu_c);
} | code for sm_80
Function : _Z3addPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fca0000000f00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0070*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fcc00078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cstdio>
using namespace std;
__global__ void add(const int *a, const int *b, int *c)
{
int i = threadIdx.x;
c[i] = a[i] * *b;
}
int main(void)
{
int count = 100;
int size = sizeof(int) * count;
int *cpu_a = (int *)malloc(size); int *gpu_a; cudaMalloc((void**)&gpu_a, size);
int cpu_b = 5; int *gpu_b; cudaMalloc((void**)&gpu_b, sizeof(int));
int *cpu_c = (int *)malloc(size); int *gpu_c; cudaMalloc((void**)&gpu_c, size);
for(int i=0; i<count; i++) cpu_a[i]=i;
cudaMemcpy(gpu_a, cpu_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_b, &cpu_b, sizeof(int), cudaMemcpyHostToDevice);
add<<<1, count>>>(gpu_a, gpu_b, gpu_c);
cudaMemcpy(cpu_c, gpu_c, size, cudaMemcpyDeviceToHost);
for(int i=0; i<count; i++)
printf("%d * %d = %dn", cpu_a[i], cpu_b, cpu_c[i]);
free(cpu_a); cudaFree(gpu_a);
cudaFree(gpu_b);
free(cpu_c); cudaFree(gpu_c);
} | .file "tmpxft_000cfdba_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi
.type _Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi, @function
_Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPKiS0_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi, .-_Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi
.globl _Z3addPKiS0_Pi
.type _Z3addPKiS0_Pi, @function
_Z3addPKiS0_Pi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPKiS0_Pi, .-_Z3addPKiS0_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d * %d = %dn"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $5, 4(%rsp)
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $400, %edi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $100, %rax
jne .L12
movl $1, %ecx
movl $400, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $100, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $400, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r13
.L14:
movl 0(%rbp,%rbx), %edx
movl (%r12,%rbx), %r8d
movl 4(%rsp), %ecx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $400, %rbx
jne .L14
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPKiS0_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPKiS0_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cstdio>
using namespace std;
__global__ void add(const int *a, const int *b, int *c)
{
int i = threadIdx.x;
c[i] = a[i] * *b;
}
int main(void)
{
int count = 100;
int size = sizeof(int) * count;
int *cpu_a = (int *)malloc(size); int *gpu_a; cudaMalloc((void**)&gpu_a, size);
int cpu_b = 5; int *gpu_b; cudaMalloc((void**)&gpu_b, sizeof(int));
int *cpu_c = (int *)malloc(size); int *gpu_c; cudaMalloc((void**)&gpu_c, size);
for(int i=0; i<count; i++) cpu_a[i]=i;
cudaMemcpy(gpu_a, cpu_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_b, &cpu_b, sizeof(int), cudaMemcpyHostToDevice);
add<<<1, count>>>(gpu_a, gpu_b, gpu_c);
cudaMemcpy(cpu_c, gpu_c, size, cudaMemcpyDeviceToHost);
for(int i=0; i<count; i++)
printf("%d * %d = %dn", cpu_a[i], cpu_b, cpu_c[i]);
free(cpu_a); cudaFree(gpu_a);
cudaFree(gpu_b);
free(cpu_c); cudaFree(gpu_c);
} | #include <hip/hip_runtime.h>
#include<cstdio>
using namespace std;
__global__ void add(const int *a, const int *b, int *c)
{
int i = threadIdx.x;
c[i] = a[i] * *b;
}
int main(void)
{
int count = 100;
int size = sizeof(int) * count;
int *cpu_a = (int *)malloc(size); int *gpu_a; hipMalloc((void**)&gpu_a, size);
int cpu_b = 5; int *gpu_b; hipMalloc((void**)&gpu_b, sizeof(int));
int *cpu_c = (int *)malloc(size); int *gpu_c; hipMalloc((void**)&gpu_c, size);
for(int i=0; i<count; i++) cpu_a[i]=i;
hipMemcpy(gpu_a, cpu_a, size, hipMemcpyHostToDevice);
hipMemcpy(gpu_b, &cpu_b, sizeof(int), hipMemcpyHostToDevice);
add<<<1, count>>>(gpu_a, gpu_b, gpu_c);
hipMemcpy(cpu_c, gpu_c, size, hipMemcpyDeviceToHost);
for(int i=0; i<count; i++)
printf("%d * %d = %dn", cpu_a[i], cpu_b, cpu_c[i]);
free(cpu_a); hipFree(gpu_a);
hipFree(gpu_b);
free(cpu_c); hipFree(gpu_c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<cstdio>
using namespace std;
__global__ void add(const int *a, const int *b, int *c)
{
int i = threadIdx.x;
c[i] = a[i] * *b;
}
int main(void)
{
int count = 100;
int size = sizeof(int) * count;
int *cpu_a = (int *)malloc(size); int *gpu_a; hipMalloc((void**)&gpu_a, size);
int cpu_b = 5; int *gpu_b; hipMalloc((void**)&gpu_b, sizeof(int));
int *cpu_c = (int *)malloc(size); int *gpu_c; hipMalloc((void**)&gpu_c, size);
for(int i=0; i<count; i++) cpu_a[i]=i;
hipMemcpy(gpu_a, cpu_a, size, hipMemcpyHostToDevice);
hipMemcpy(gpu_b, &cpu_b, sizeof(int), hipMemcpyHostToDevice);
add<<<1, count>>>(gpu_a, gpu_b, gpu_c);
hipMemcpy(cpu_c, gpu_c, size, hipMemcpyDeviceToHost);
for(int i=0; i<count; i++)
printf("%d * %d = %dn", cpu_a[i], cpu_b, cpu_c[i]);
free(cpu_a); hipFree(gpu_a);
hipFree(gpu_b);
free(cpu_c); hipFree(gpu_c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPKiS0_Pi
.globl _Z3addPKiS0_Pi
.p2align 8
.type _Z3addPKiS0_Pi,@function
_Z3addPKiS0_Pi:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[4:5]
s_load_b32 s2, s[6:7], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_lo_u32 v1, s2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPKiS0_Pi, .Lfunc_end0-_Z3addPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<cstdio>
using namespace std;
__global__ void add(const int *a, const int *b, int *c)
{
int i = threadIdx.x;
c[i] = a[i] * *b;
}
int main(void)
{
int count = 100;
int size = sizeof(int) * count;
int *cpu_a = (int *)malloc(size); int *gpu_a; hipMalloc((void**)&gpu_a, size);
int cpu_b = 5; int *gpu_b; hipMalloc((void**)&gpu_b, sizeof(int));
int *cpu_c = (int *)malloc(size); int *gpu_c; hipMalloc((void**)&gpu_c, size);
for(int i=0; i<count; i++) cpu_a[i]=i;
hipMemcpy(gpu_a, cpu_a, size, hipMemcpyHostToDevice);
hipMemcpy(gpu_b, &cpu_b, sizeof(int), hipMemcpyHostToDevice);
add<<<1, count>>>(gpu_a, gpu_b, gpu_c);
hipMemcpy(cpu_c, gpu_c, size, hipMemcpyDeviceToHost);
for(int i=0; i<count; i++)
printf("%d * %d = %dn", cpu_a[i], cpu_b, cpu_c[i]);
free(cpu_a); hipFree(gpu_a);
hipFree(gpu_b);
free(cpu_c); hipFree(gpu_c);
} | .text
.file "test.hip"
.globl _Z18__device_stub__addPKiS0_Pi # -- Begin function _Z18__device_stub__addPKiS0_Pi
.p2align 4, 0x90
.type _Z18__device_stub__addPKiS0_Pi,@function
_Z18__device_stub__addPKiS0_Pi: # @_Z18__device_stub__addPKiS0_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPKiS0_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPKiS0_Pi, .Lfunc_end0-_Z18__device_stub__addPKiS0_Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movl $5, 12(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $100, %rax
jne .LBB1_1
# %bb.2:
movq 32(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 99(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPKiS0_Pi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl 12(%rsp), %edx
movl (%r14,%r15,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $100, %r15
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPKiS0_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPKiS0_Pi,@object # @_Z3addPKiS0_Pi
.section .rodata,"a",@progbits
.globl _Z3addPKiS0_Pi
.p2align 3, 0x0
_Z3addPKiS0_Pi:
.quad _Z18__device_stub__addPKiS0_Pi
.size _Z3addPKiS0_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d * %d = %dn"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPKiS0_Pi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPKiS0_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPKiS0_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fca0000000f00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0070*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fcc00078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPKiS0_Pi
.globl _Z3addPKiS0_Pi
.p2align 8
.type _Z3addPKiS0_Pi,@function
_Z3addPKiS0_Pi:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[4:5]
s_load_b32 s2, s[6:7], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_lo_u32 v1, s2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPKiS0_Pi, .Lfunc_end0-_Z3addPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cfdba_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi
.type _Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi, @function
_Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPKiS0_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi, .-_Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi
.globl _Z3addPKiS0_Pi
.type _Z3addPKiS0_Pi, @function
_Z3addPKiS0_Pi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPKiS0_Pi, .-_Z3addPKiS0_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d * %d = %dn"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $5, 4(%rsp)
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $400, %edi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $100, %rax
jne .L12
movl $1, %ecx
movl $400, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $100, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $400, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r13
.L14:
movl 0(%rbp,%rbx), %edx
movl (%r12,%rbx), %r8d
movl 4(%rsp), %ecx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $400, %rbx
jne .L14
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z3addPKiS0_PiPKiS0_Pi
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPKiS0_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPKiS0_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z18__device_stub__addPKiS0_Pi # -- Begin function _Z18__device_stub__addPKiS0_Pi
.p2align 4, 0x90
.type _Z18__device_stub__addPKiS0_Pi,@function
_Z18__device_stub__addPKiS0_Pi: # @_Z18__device_stub__addPKiS0_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPKiS0_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPKiS0_Pi, .Lfunc_end0-_Z18__device_stub__addPKiS0_Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movl $5, 12(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $100, %rax
jne .LBB1_1
# %bb.2:
movq 32(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 99(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPKiS0_Pi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl 12(%rsp), %edx
movl (%r14,%r15,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $100, %r15
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPKiS0_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPKiS0_Pi,@object # @_Z3addPKiS0_Pi
.section .rodata,"a",@progbits
.globl _Z3addPKiS0_Pi
.p2align 3, 0x0
_Z3addPKiS0_Pi:
.quad _Z18__device_stub__addPKiS0_Pi
.size _Z3addPKiS0_Pi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d * %d = %dn"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPKiS0_Pi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPKiS0_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPKiS0_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* \file TestShortCircuit.cu
\author Gregory Diamos <gregory.diamos@gatech.edu>
\date Tuesday November 9, 2010
\brief A CUDA assembly test for short-circuiting control flow.
*/
const unsigned int threads = 512;
__device__ bool out[threads];
__global__ void short_circuit()
{
unsigned int id = threadIdx.x;
bool b0 = (id >> 0) & 0x1;
bool b1 = (id >> 1) & 0x1;
bool b2 = (id >> 2) & 0x1;
bool b3 = (id >> 3) & 0x1;
bool b4 = (id >> 4) & 0x1;
bool b5 = (id >> 5) & 0x1;
bool b6 = (id >> 6) & 0x1;
bool b7 = (id >> 7) & 0x1;
bool b8 = (id >> 8) & 0x1;
if(((b0 && (b1 || b2)) || (b3 || (b4 && b5))) && (b6 || (b7 && b8)))
{
out[id] = true;
}
else
{
out[id] = false;
}
}
int main(int argc, char** argv)
{
short_circuit<<<1, threads>>>();
} | code for sm_80
Function : _Z13short_circuitv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ SHF.R.U32.HI R0, RZ, 0x3, R3.reuse ; /* 0x00000003ff007819 */
/* 0x101fe40000011603 */
/*0040*/ SHF.R.U32.HI R2, RZ, 0x6, R3 ; /* 0x00000006ff027819 */
/* 0x000fe40000011603 */
/*0050*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x000fe400078ec0ff */
/*0060*/ LOP3.LUT R2, R2, 0x1, RZ, 0xc0, !PT ; /* 0x0000000102027812 */
/* 0x000fe400078ec0ff */
/*0070*/ ISETP.NE.U32.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc40003f25070 */
/*0080*/ ISETP.NE.U32.AND P2, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f45070 */
/*0090*/ LOP3.LUT P0, RZ, R3.reuse, 0x6, RZ, 0xc0, !PT ; /* 0x0000000603ff7812 */
/* 0x040fe4000780c0ff */
/*00a0*/ LOP3.LUT R0, R3.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000103007812 */
/* 0x040fe400078ec0ff */
/*00b0*/ LOP3.LUT R2, R3.reuse, 0x30, RZ, 0xc0, !PT ; /* 0x0000003003027812 */
/* 0x040fe400078ec0ff */
/*00c0*/ LOP3.LUT R4, R3, 0x180, RZ, 0xc0, !PT ; /* 0x0000018003047812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.EQ.U32.AND P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fc40000702070 */
/*00e0*/ ISETP.EQ.OR P1, PT, R2, 0x30, !P1 ; /* 0x000000300200780c */
/* 0x000fe40004f22670 */
/*00f0*/ ISETP.EQ.OR P2, PT, R4, 0x180, !P2 ; /* 0x000001800400780c */
/* 0x000fe40005742670 */
/*0100*/ IADD3 R2, P3, R3, c[0x4][0x0], RZ ; /* 0x0100000003027a10 */
/* 0x000fe40007f7e0ff */
/*0110*/ PLOP3.LUT P0, PT, P2, P0, P1, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60001701c10 */
/*0120*/ IMAD.X R3, RZ, RZ, c[0x4][0x4], P3 ; /* 0x01000100ff037624 */
/* 0x000fe200018e06ff */
/*0130*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0140*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* \file TestShortCircuit.cu
\author Gregory Diamos <gregory.diamos@gatech.edu>
\date Tuesday November 9, 2010
\brief A CUDA assembly test for short-circuiting control flow.
*/
const unsigned int threads = 512;
__device__ bool out[threads];
__global__ void short_circuit()
{
unsigned int id = threadIdx.x;
bool b0 = (id >> 0) & 0x1;
bool b1 = (id >> 1) & 0x1;
bool b2 = (id >> 2) & 0x1;
bool b3 = (id >> 3) & 0x1;
bool b4 = (id >> 4) & 0x1;
bool b5 = (id >> 5) & 0x1;
bool b6 = (id >> 6) & 0x1;
bool b7 = (id >> 7) & 0x1;
bool b8 = (id >> 8) & 0x1;
if(((b0 && (b1 || b2)) || (b3 || (b4 && b5))) && (b6 || (b7 && b8)))
{
out[id] = true;
}
else
{
out[id] = false;
}
}
int main(int argc, char** argv)
{
short_circuit<<<1, threads>>>();
} | .file "tmpxft_00017420_00000000-6_TestShortCircuit.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13short_circuitvv
.type _Z32__device_stub__Z13short_circuitvv, @function
_Z32__device_stub__Z13short_circuitvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13short_circuitv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z32__device_stub__Z13short_circuitvv, .-_Z32__device_stub__Z13short_circuitvv
.globl _Z13short_circuitv
.type _Z13short_circuitv, @function
_Z13short_circuitv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13short_circuitvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13short_circuitv, .-_Z13short_circuitv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z32__device_stub__Z13short_circuitvv
jmp .L12
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13short_circuitv"
.LC1:
.string "out"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13short_circuitv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $512, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3out(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3out
.comm _ZL3out,512,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* \file TestShortCircuit.cu
\author Gregory Diamos <gregory.diamos@gatech.edu>
\date Tuesday November 9, 2010
\brief A CUDA assembly test for short-circuiting control flow.
*/
const unsigned int threads = 512;
__device__ bool out[threads];
__global__ void short_circuit()
{
unsigned int id = threadIdx.x;
bool b0 = (id >> 0) & 0x1;
bool b1 = (id >> 1) & 0x1;
bool b2 = (id >> 2) & 0x1;
bool b3 = (id >> 3) & 0x1;
bool b4 = (id >> 4) & 0x1;
bool b5 = (id >> 5) & 0x1;
bool b6 = (id >> 6) & 0x1;
bool b7 = (id >> 7) & 0x1;
bool b8 = (id >> 8) & 0x1;
if(((b0 && (b1 || b2)) || (b3 || (b4 && b5))) && (b6 || (b7 && b8)))
{
out[id] = true;
}
else
{
out[id] = false;
}
}
int main(int argc, char** argv)
{
short_circuit<<<1, threads>>>();
} | #include <hip/hip_runtime.h>
/* \file TestShortCircuit.cu
\author Gregory Diamos <gregory.diamos@gatech.edu>
\date Tuesday November 9, 2010
\brief A CUDA assembly test for short-circuiting control flow.
*/
const unsigned int threads = 512;
__device__ bool out[threads];
__global__ void short_circuit()
{
unsigned int id = threadIdx.x;
bool b0 = (id >> 0) & 0x1;
bool b1 = (id >> 1) & 0x1;
bool b2 = (id >> 2) & 0x1;
bool b3 = (id >> 3) & 0x1;
bool b4 = (id >> 4) & 0x1;
bool b5 = (id >> 5) & 0x1;
bool b6 = (id >> 6) & 0x1;
bool b7 = (id >> 7) & 0x1;
bool b8 = (id >> 8) & 0x1;
if(((b0 && (b1 || b2)) || (b3 || (b4 && b5))) && (b6 || (b7 && b8)))
{
out[id] = true;
}
else
{
out[id] = false;
}
}
int main(int argc, char** argv)
{
short_circuit<<<1, threads>>>();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/* \file TestShortCircuit.cu
\author Gregory Diamos <gregory.diamos@gatech.edu>
\date Tuesday November 9, 2010
\brief A CUDA assembly test for short-circuiting control flow.
*/
const unsigned int threads = 512;
__device__ bool out[threads];
__global__ void short_circuit()
{
unsigned int id = threadIdx.x;
bool b0 = (id >> 0) & 0x1;
bool b1 = (id >> 1) & 0x1;
bool b2 = (id >> 2) & 0x1;
bool b3 = (id >> 3) & 0x1;
bool b4 = (id >> 4) & 0x1;
bool b5 = (id >> 5) & 0x1;
bool b6 = (id >> 6) & 0x1;
bool b7 = (id >> 7) & 0x1;
bool b8 = (id >> 8) & 0x1;
if(((b0 && (b1 || b2)) || (b3 || (b4 && b5))) && (b6 || (b7 && b8)))
{
out[id] = true;
}
else
{
out[id] = false;
}
}
int main(int argc, char** argv)
{
short_circuit<<<1, threads>>>();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13short_circuitv
.globl _Z13short_circuitv
.p2align 8
.type _Z13short_circuitv,@function
_Z13short_circuitv:
v_and_b32_e32 v2, 48, v0
v_and_b32_e32 v1, 1, v0
s_mov_b32 s2, 0
s_mov_b32 s1, 0
s_mov_b32 s3, exec_lo
v_cmp_ne_u32_e32 vcc_lo, 48, v2
v_cmpx_eq_u32_e32 1, v1
s_xor_b32 s3, exec_lo, s3
v_and_b32_e32 v1, 14, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 0, v1
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, s0, -1
s_and_b32 s1, s0, exec_lo
s_and_b32 s2, s2, exec_lo
s_and_not1_saveexec_b32 s3, s3
v_and_b32_e32 v1, 8, v0
s_and_not1_b32 s1, s1, exec_lo
s_and_not1_b32 s2, s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 0, v1
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, s0, -1
s_and_b32 s0, s0, exec_lo
s_and_b32 s4, s4, exec_lo
s_or_b32 s1, s1, s0
s_or_b32 s2, s2, s4
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
v_and_b32_e32 v1, 64, v0
v_and_b32_e32 v2, 0x180, v0
s_and_not1_b32 s1, s1, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cmp_ne_u32_e64 s0, 0x180, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 s2, s0, exec_lo
s_mov_b32 s0, 1
s_or_b32 s1, s1, s2
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v1, s0
s_and_saveexec_b32 s0, s1
v_mov_b32_e32 v1, 0
s_or_b32 exec_lo, exec_lo, s0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, out@rel32@lo+4
s_addc_u32 s1, s1, out@rel32@hi+12
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13short_circuitv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13short_circuitv, .Lfunc_end0-_Z13short_circuitv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected out
.type out,@object
.section .bss,"aw",@nobits
.globl out
.p2align 4, 0x0
out:
.zero 512
.size out, 512
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym out
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13short_circuitv
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z13short_circuitv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/* \file TestShortCircuit.cu
\author Gregory Diamos <gregory.diamos@gatech.edu>
\date Tuesday November 9, 2010
\brief A CUDA assembly test for short-circuiting control flow.
*/
const unsigned int threads = 512;
__device__ bool out[threads];
__global__ void short_circuit()
{
unsigned int id = threadIdx.x;
bool b0 = (id >> 0) & 0x1;
bool b1 = (id >> 1) & 0x1;
bool b2 = (id >> 2) & 0x1;
bool b3 = (id >> 3) & 0x1;
bool b4 = (id >> 4) & 0x1;
bool b5 = (id >> 5) & 0x1;
bool b6 = (id >> 6) & 0x1;
bool b7 = (id >> 7) & 0x1;
bool b8 = (id >> 8) & 0x1;
if(((b0 && (b1 || b2)) || (b3 || (b4 && b5))) && (b6 || (b7 && b8)))
{
out[id] = true;
}
else
{
out[id] = false;
}
}
int main(int argc, char** argv)
{
short_circuit<<<1, threads>>>();
} | .text
.file "TestShortCircuit.hip"
.globl _Z28__device_stub__short_circuitv # -- Begin function _Z28__device_stub__short_circuitv
.p2align 4, 0x90
.type _Z28__device_stub__short_circuitv,@function
_Z28__device_stub__short_circuitv: # @_Z28__device_stub__short_circuitv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13short_circuitv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z28__device_stub__short_circuitv, .Lfunc_end0-_Z28__device_stub__short_circuitv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13short_circuitv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13short_circuitv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $out, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $512, %r9d # imm = 0x200
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type out,@object # @out
.local out
.comm out,512,16
.type _Z13short_circuitv,@object # @_Z13short_circuitv
.section .rodata,"a",@progbits
.globl _Z13short_circuitv
.p2align 3, 0x0
_Z13short_circuitv:
.quad _Z28__device_stub__short_circuitv
.size _Z13short_circuitv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13short_circuitv"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "out"
.size .L__unnamed_2, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__short_circuitv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym out
.addrsig_sym _Z13short_circuitv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13short_circuitv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ SHF.R.U32.HI R0, RZ, 0x3, R3.reuse ; /* 0x00000003ff007819 */
/* 0x101fe40000011603 */
/*0040*/ SHF.R.U32.HI R2, RZ, 0x6, R3 ; /* 0x00000006ff027819 */
/* 0x000fe40000011603 */
/*0050*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x000fe400078ec0ff */
/*0060*/ LOP3.LUT R2, R2, 0x1, RZ, 0xc0, !PT ; /* 0x0000000102027812 */
/* 0x000fe400078ec0ff */
/*0070*/ ISETP.NE.U32.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc40003f25070 */
/*0080*/ ISETP.NE.U32.AND P2, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f45070 */
/*0090*/ LOP3.LUT P0, RZ, R3.reuse, 0x6, RZ, 0xc0, !PT ; /* 0x0000000603ff7812 */
/* 0x040fe4000780c0ff */
/*00a0*/ LOP3.LUT R0, R3.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000103007812 */
/* 0x040fe400078ec0ff */
/*00b0*/ LOP3.LUT R2, R3.reuse, 0x30, RZ, 0xc0, !PT ; /* 0x0000003003027812 */
/* 0x040fe400078ec0ff */
/*00c0*/ LOP3.LUT R4, R3, 0x180, RZ, 0xc0, !PT ; /* 0x0000018003047812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.EQ.U32.AND P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fc40000702070 */
/*00e0*/ ISETP.EQ.OR P1, PT, R2, 0x30, !P1 ; /* 0x000000300200780c */
/* 0x000fe40004f22670 */
/*00f0*/ ISETP.EQ.OR P2, PT, R4, 0x180, !P2 ; /* 0x000001800400780c */
/* 0x000fe40005742670 */
/*0100*/ IADD3 R2, P3, R3, c[0x4][0x0], RZ ; /* 0x0100000003027a10 */
/* 0x000fe40007f7e0ff */
/*0110*/ PLOP3.LUT P0, PT, P2, P0, P1, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60001701c10 */
/*0120*/ IMAD.X R3, RZ, RZ, c[0x4][0x4], P3 ; /* 0x01000100ff037624 */
/* 0x000fe200018e06ff */
/*0130*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0140*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13short_circuitv
.globl _Z13short_circuitv
.p2align 8
.type _Z13short_circuitv,@function
_Z13short_circuitv:
v_and_b32_e32 v2, 48, v0
v_and_b32_e32 v1, 1, v0
s_mov_b32 s2, 0
s_mov_b32 s1, 0
s_mov_b32 s3, exec_lo
v_cmp_ne_u32_e32 vcc_lo, 48, v2
v_cmpx_eq_u32_e32 1, v1
s_xor_b32 s3, exec_lo, s3
v_and_b32_e32 v1, 14, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 0, v1
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, s0, -1
s_and_b32 s1, s0, exec_lo
s_and_b32 s2, s2, exec_lo
s_and_not1_saveexec_b32 s3, s3
v_and_b32_e32 v1, 8, v0
s_and_not1_b32 s1, s1, exec_lo
s_and_not1_b32 s2, s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 0, v1
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, s0, -1
s_and_b32 s0, s0, exec_lo
s_and_b32 s4, s4, exec_lo
s_or_b32 s1, s1, s0
s_or_b32 s2, s2, s4
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
v_and_b32_e32 v1, 64, v0
v_and_b32_e32 v2, 0x180, v0
s_and_not1_b32 s1, s1, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cmp_ne_u32_e64 s0, 0x180, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 s2, s0, exec_lo
s_mov_b32 s0, 1
s_or_b32 s1, s1, s2
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v1, s0
s_and_saveexec_b32 s0, s1
v_mov_b32_e32 v1, 0
s_or_b32 exec_lo, exec_lo, s0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, out@rel32@lo+4
s_addc_u32 s1, s1, out@rel32@hi+12
global_store_b8 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13short_circuitv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13short_circuitv, .Lfunc_end0-_Z13short_circuitv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected out
.type out,@object
.section .bss,"aw",@nobits
.globl out
.p2align 4, 0x0
out:
.zero 512
.size out, 512
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym out
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13short_circuitv
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z13short_circuitv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00017420_00000000-6_TestShortCircuit.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13short_circuitvv
.type _Z32__device_stub__Z13short_circuitvv, @function
_Z32__device_stub__Z13short_circuitvv:
.LFB2052:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13short_circuitv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z32__device_stub__Z13short_circuitvv, .-_Z32__device_stub__Z13short_circuitvv
.globl _Z13short_circuitv
.type _Z13short_circuitv, @function
_Z13short_circuitv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13short_circuitvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13short_circuitv, .-_Z13short_circuitv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z32__device_stub__Z13short_circuitvv
jmp .L12
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13short_circuitv"
.LC1:
.string "out"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13short_circuitv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $512, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3out(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3out
.comm _ZL3out,512,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "TestShortCircuit.hip"
.globl _Z28__device_stub__short_circuitv # -- Begin function _Z28__device_stub__short_circuitv
.p2align 4, 0x90
.type _Z28__device_stub__short_circuitv,@function
_Z28__device_stub__short_circuitv: # @_Z28__device_stub__short_circuitv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13short_circuitv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z28__device_stub__short_circuitv, .Lfunc_end0-_Z28__device_stub__short_circuitv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13short_circuitv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13short_circuitv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $out, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $512, %r9d # imm = 0x200
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type out,@object # @out
.local out
.comm out,512,16
.type _Z13short_circuitv,@object # @_Z13short_circuitv
.section .rodata,"a",@progbits
.globl _Z13short_circuitv
.p2align 3, 0x0
_Z13short_circuitv:
.quad _Z28__device_stub__short_circuitv
.size _Z13short_circuitv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13short_circuitv"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "out"
.size .L__unnamed_2, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__short_circuitv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym out
.addrsig_sym _Z13short_circuitv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Second CUDA program
// Ping-Che Chen
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda_runtime.h>
#define BLOCK_SIZE 16
__global__ static void matMultCUDA(const float* a, size_t lda, const float* b, size_t ldb, float* c, size_t ldc, int n)
{
__shared__ float matA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float matB[BLOCK_SIZE][BLOCK_SIZE];
const int tidc = threadIdx.x;
const int tidr = threadIdx.y;
const int bidc = blockIdx.x * BLOCK_SIZE;
const int bidr = blockIdx.y * BLOCK_SIZE;
int i, j;
float results = 0;
float comp = 0;
for(j = 0; j < n; j += BLOCK_SIZE) {
matA[tidr][tidc] = a[(tidr + bidr) * lda + tidc + j];
matB[tidr][tidc] = b[(tidr + j) * ldb + tidc + bidc];
__syncthreads();
for(i = 0; i < BLOCK_SIZE; i++) {
float t;
comp -= matA[tidr][i] * matB[i][tidc];
t = results - comp;
comp = (t - results) + comp;
results = t;
}
__syncthreads();
}
c[(tidr + bidr) * ldc + tidc + bidc] = results;
} | code for sm_80
Function : _Z11matMultCUDAPKfmS0_mPfmi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R15, SR_TID.Y ; /* 0x00000000000f7919 */
/* 0x000e680000002200 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000ea20000002100 */
/*0060*/ SHF.L.U32 R9, R9, 0x4, RZ ; /* 0x0000000409097819 */
/* 0x001fe400000006ff */
/*0070*/ LEA R5, R2, R15, 0x4 ; /* 0x0000000f02057211 */
/* 0x002fc400078e20ff */
/*0080*/ SHF.R.S32.HI R6, RZ, 0x1f, R0 ; /* 0x0000001fff067819 */
/* 0x004fe40000011400 */
/*0090*/ IADD3 R2, P0, R9.reuse, R0, RZ ; /* 0x0000000009027210 */
/* 0x040fe40007f1e0ff */
/*00a0*/ SHF.R.S32.HI R4, RZ, 0x1f, R5 ; /* 0x0000001fff047819 */
/* 0x000fe40000011405 */
/*00b0*/ LEA.HI.X.SX32 R3, R9, R6, 0x1, P0 ; /* 0x0000000609037211 */
/* 0x000fe400000f0eff */
/*00c0*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x190], PT ; /* 0x00006400ff007a0c */
/* 0x000fe20003f01270 */
/*00d0*/ IMAD R6, R4, c[0x0][0x188], RZ ; /* 0x0000620004067a24 */
/* 0x000fe400078e02ff */
/*00e0*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x188], R2 ; /* 0x0000620005027a25 */
/* 0x000fc800078e0002 */
/*00f0*/ IMAD R7, R5, c[0x0][0x18c], R6 ; /* 0x0000630005077a24 */
/* 0x000fe200078e0206 */
/*0100*/ LEA R12, P1, R2, c[0x0][0x180], 0x2 ; /* 0x00006000020c7a11 */
/* 0x000fc800078210ff */
/*0110*/ IADD3 R3, R3, R7, RZ ; /* 0x0000000703037210 */
/* 0x000fe40007ffe0ff */
/*0120*/ @!P0 MOV R7, RZ ; /* 0x000000ff00078202 */
/* 0x000fe40000000f00 */
/*0130*/ LEA.HI.X R13, R2, c[0x0][0x184], R3, 0x2, P1 ; /* 0x00006100020d7a11 */
/* 0x000fe200008f1403 */
/*0140*/ @!P0 BRA 0x8e0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD R4, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a24 */
/* 0x000fe200078e02ff */
/*0160*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*0170*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*0180*/ MOV R2, R0.reuse ; /* 0x0000000000027202 */
/* 0x080fe20000000f00 */
/*0190*/ IMAD R19, R5, c[0x0][0x16c], R4 ; /* 0x00005b0005137a24 */
/* 0x000fe200078e0204 */
/*01a0*/ SHF.L.U32 R17, R15, 0x6, RZ ; /* 0x000000060f117819 */
/* 0x000fe200000006ff */
/*01b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*01c0*/ SHF.R.S32.HI R18, RZ, 0x1f, R15 ; /* 0x0000001fff127819 */
/* 0x000fe2000001140f */
/*01d0*/ IMAD.WIDE.U32 R4, R5, c[0x0][0x168], R2 ; /* 0x00005a0005047a25 */
/* 0x000fe200078e0002 */
/*01e0*/ IADD3 R2, P0, R9, R0, RZ ; /* 0x0000000009027210 */
/* 0x000fc40007f1e0ff */
/*01f0*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe40000000f00 */
/*0200*/ IADD3 R19, R5, R19, RZ ; /* 0x0000001305137210 */
/* 0x000fe40007ffe0ff */
/*0210*/ LEA R14, P1, R4.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800040e7a11 */
/* 0x040fe400078210ff */
/*0220*/ LEA.HI.X.SX32 R3, R9, R3, 0x1, P0 ; /* 0x0000000309037211 */
/* 0x000fe400000f0eff */
/*0230*/ LEA.HI.X R19, R4, c[0x0][0x164], R19, 0x2, P1 ; /* 0x0000590004137a11 */
/* 0x000fe400008f1413 */
/*0240*/ LEA R16, R0, R17, 0x2 ; /* 0x0000001100107211 */
/* 0x000fc400078e10ff */
/*0250*/ IMAD R4, R18, c[0x0][0x178], RZ ; /* 0x00005e0012047a24 */
/* 0x000fe200078e02ff */
/*0260*/ MOV R25, R19 ; /* 0x0000001300197202 */
/* 0x000fe20000000f00 */
/*0270*/ IMAD.WIDE.U32 R8, R15, c[0x0][0x178], R2 ; /* 0x00005e000f087a25 */
/* 0x000fe200078e0002 */
/*0280*/ MOV R24, R14 ; /* 0x0000000e00187202 */
/* 0x000fc60000000f00 */
/*0290*/ IMAD R5, R15, c[0x0][0x17c], R4 ; /* 0x00005f000f057a24 */
/* 0x000fe200078e0204 */
/*02a0*/ LEA R4, P0, R8, c[0x0][0x170], 0x2 ; /* 0x00005c0008047a11 */
/* 0x000fe200078010ff */
/*02b0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea6000c1e1900 */
/*02c0*/ IADD3 R5, R9, R5, RZ ; /* 0x0000000509057210 */
/* 0x000fc80007ffe0ff */
/*02d0*/ LEA.HI.X R5, R8, c[0x0][0x174], R5, 0x2, P0 ; /* 0x00005d0008057a11 */
/* 0x000fcc00000f1405 */
/*02e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee8000c1e1900 */
/*02f0*/ STS [R16], R25 ; /* 0x0000001910007388 */
/* 0x004fe80000000800 */
/*0300*/ STS [R16+0x400], R5 ; /* 0x0004000510007388 */
/* 0x008fe80000000800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0320*/ LDS R6, [R0.X4+0x400] ; /* 0x0004000000067984 */
/* 0x000fe80000004800 */
/*0330*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*0340*/ LDS R26, [R0.X4+0x440] ; /* 0x00044000001a7984 */
/* 0x000e680000004800 */
/*0350*/ LDS R21, [R0.X4+0x480] ; /* 0x0004800000157984 */
/* 0x000ea20000004800 */
/*0360*/ FFMA R6, R6, -R8, R23 ; /* 0x8000000806067223 */
/* 0x001fc60000000017 */
/*0370*/ LDS R8, [R0.X4+0x4c0] ; /* 0x0004c00000087984 */
/* 0x000e220000004800 */
/*0380*/ FADD R22, -R6, R7 ; /* 0x0000000706167221 */
/* 0x000fc80000000100 */
/*0390*/ FADD R7, R22, -R7 ; /* 0x8000000716077221 */
/* 0x000fc80000000000 */
/*03a0*/ FADD R6, R6, R7 ; /* 0x0000000706067221 */
/* 0x000fc80000000000 */
/*03b0*/ FFMA R23, R26, -R9, R6 ; /* 0x800000091a177223 */
/* 0x002fe40000000006 */
/*03c0*/ LDS R9, [R0.X4+0x500] ; /* 0x0005000000097984 */
/* 0x000fe40000004800 */
/*03d0*/ FADD R25, R22.reuse, -R23 ; /* 0x8000001716197221 */
/* 0x040fe40000000000 */
/*03e0*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000e640000000c00 */
/*03f0*/ FADD R22, -R22, R25 ; /* 0x0000001916167221 */
/* 0x000fc80000000100 */
/*0400*/ FADD R22, R23, R22 ; /* 0x0000001617167221 */
/* 0x000fc80000000000 */
/*0410*/ FFMA R22, R21, -R10, R22 ; /* 0x8000000a15167223 */
/* 0x004fe40000000016 */
/*0420*/ LDS R10, [R0.X4+0x540] ; /* 0x00054000000a7984 */
/* 0x000ea40000004800 */
/*0430*/ FADD R24, R25.reuse, -R22 ; /* 0x8000001619187221 */
/* 0x040fe40000000000 */
/*0440*/ LDS R21, [R0.X4+0x580] ; /* 0x0005800000157984 */
/* 0x000ee40000004800 */
/*0450*/ FADD R25, -R25, R24 ; /* 0x0000001819197221 */
/* 0x000fc80000000100 */
/*0460*/ FADD R25, R22, R25 ; /* 0x0000001916197221 */
/* 0x000fc80000000000 */
/*0470*/ FFMA R11, R8, -R11, R25 ; /* 0x8000000b080b7223 */
/* 0x001fc80000000019 */
/*0480*/ FADD R23, R24, -R11 ; /* 0x8000000b18177221 */
/* 0x000fc80000000000 */
/*0490*/ FADD R24, -R24, R23 ; /* 0x0000001718187221 */
/* 0x000fc80000000100 */
/*04a0*/ FADD R24, R11, R24 ; /* 0x000000180b187221 */
/* 0x000fc80000000000 */
/*04b0*/ FFMA R24, R9, -R4, R24 ; /* 0x8000000409187223 */
/* 0x002fe40000000018 */
/*04c0*/ LDS R4, [R0.X4+0x5c0] ; /* 0x0005c00000047984 */
/* 0x000e240000004800 */
/*04d0*/ FADD R22, R23, -R24 ; /* 0x8000001817167221 */
/* 0x000fc80000000000 */
/*04e0*/ FADD R23, -R23, R22 ; /* 0x0000001617177221 */
/* 0x000fc80000000100 */
/*04f0*/ FADD R23, R24, R23 ; /* 0x0000001718177221 */
/* 0x000fc80000000000 */
/*0500*/ FFMA R23, R10, -R5, R23 ; /* 0x800000050a177223 */
/* 0x004fe40000000017 */
/*0510*/ LDS R5, [R0.X4+0x600] ; /* 0x0006000000057984 */
/* 0x000fe40000004800 */
/*0520*/ FADD R25, R22.reuse, -R23 ; /* 0x8000001716197221 */
/* 0x040fe40000000000 */
/*0530*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e640000000c00 */
/*0540*/ FADD R22, -R22, R25 ; /* 0x0000001916167221 */
/* 0x000fc80000000100 */
/*0550*/ FADD R22, R23, R22 ; /* 0x0000001617167221 */
/* 0x000fc80000000000 */
/*0560*/ FFMA R22, R21, -R6, R22 ; /* 0x8000000615167223 */
/* 0x008fe40000000016 */
/*0570*/ LDS R6, [R0.X4+0x640] ; /* 0x0006400000067984 */
/* 0x000ea40000004800 */
/*0580*/ FADD R24, R25.reuse, -R22 ; /* 0x8000001619187221 */
/* 0x040fe40000000000 */
/*0590*/ LDS R21, [R0.X4+0x680] ; /* 0x0006800000157984 */
/* 0x000ee40000004800 */
/*05a0*/ FADD R25, -R25, R24 ; /* 0x0000001819197221 */
/* 0x000fc80000000100 */
/*05b0*/ FADD R25, R22, R25 ; /* 0x0000001916197221 */
/* 0x000fc80000000000 */
/*05c0*/ FFMA R7, R4, -R7, R25 ; /* 0x8000000704077223 */
/* 0x001fc80000000019 */
/*05d0*/ FADD R23, R24, -R7 ; /* 0x8000000718177221 */
/* 0x000fc80000000000 */
/*05e0*/ FADD R24, -R24, R23 ; /* 0x0000001718187221 */
/* 0x000fc80000000100 */
/*05f0*/ FADD R24, R7, R24 ; /* 0x0000001807187221 */
/* 0x000fc80000000000 */
/*0600*/ FFMA R24, R5, -R8, R24 ; /* 0x8000000805187223 */
/* 0x002fe40000000018 */
/*0610*/ LDS R8, [R0.X4+0x6c0] ; /* 0x0006c00000087984 */
/* 0x000e240000004800 */
/*0620*/ FADD R22, R23, -R24 ; /* 0x8000001817167221 */
/* 0x000fc80000000000 */
/*0630*/ FADD R23, -R23, R22 ; /* 0x0000001617177221 */
/* 0x000fc80000000100 */
/*0640*/ FADD R23, R24, R23 ; /* 0x0000001718177221 */
/* 0x000fc80000000000 */
/*0650*/ FFMA R23, R6, -R9, R23 ; /* 0x8000000906177223 */
/* 0x004fe40000000017 */
/*0660*/ LDS R9, [R0.X4+0x700] ; /* 0x0007000000097984 */
/* 0x000fe40000004800 */
/*0670*/ FADD R25, R22.reuse, -R23 ; /* 0x8000001716197221 */
/* 0x040fe40000000000 */
/*0680*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000e640000000c00 */
/*0690*/ FADD R22, -R22, R25 ; /* 0x0000001916167221 */
/* 0x000fc80000000100 */
/*06a0*/ FADD R22, R23, R22 ; /* 0x0000001617167221 */
/* 0x000fc80000000000 */
/*06b0*/ FFMA R22, R21, -R10, R22 ; /* 0x8000000a15167223 */
/* 0x008fe40000000016 */
/*06c0*/ LDS R10, [R0.X4+0x740] ; /* 0x00074000000a7984 */
/* 0x000ea40000004800 */
/*06d0*/ FADD R24, R25, -R22 ; /* 0x8000001619187221 */
/* 0x000fc80000000000 */
/*06e0*/ FADD R25, -R25, R24 ; /* 0x0000001819197221 */
/* 0x000fc80000000100 */
/*06f0*/ FADD R25, R22, R25 ; /* 0x0000001916197221 */
/* 0x000fc80000000000 */
/*0700*/ FFMA R25, R8, -R11, R25 ; /* 0x8000000b08197223 */
/* 0x001fe40000000019 */
/*0710*/ LDS R11, [R0.X4+0x780] ; /* 0x00078000000b7984 */
/* 0x000e240000004800 */
/*0720*/ FADD R21, R24, -R25 ; /* 0x8000001918157221 */
/* 0x000fc80000000000 */
/*0730*/ FADD R24, -R24, R21 ; /* 0x0000001518187221 */
/* 0x000fc80000000100 */
/*0740*/ FADD R24, R25, R24 ; /* 0x0000001819187221 */
/* 0x000fc80000000000 */
/*0750*/ FFMA R24, R9, -R4, R24 ; /* 0x8000000409187223 */
/* 0x002fe40000000018 */
/*0760*/ LDS R4, [R0.X4+0x7c0] ; /* 0x0007c00000047984 */
/* 0x000e640000004800 */
/*0770*/ FADD R8, R21, -R24 ; /* 0x8000001815087221 */
/* 0x000fc80000000000 */
/*0780*/ FADD R21, -R21, R8 ; /* 0x0000000815157221 */
/* 0x000fc80000000100 */
/*0790*/ FADD R21, R24, R21 ; /* 0x0000001518157221 */
/* 0x000fc80000000000 */
/*07a0*/ FFMA R5, R10, -R5, R21 ; /* 0x800000050a057223 */
/* 0x004fc80000000015 */
/*07b0*/ FADD R9, R8, -R5 ; /* 0x8000000508097221 */
/* 0x000fc80000000000 */
/*07c0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x000fc80000000100 */
/*07d0*/ FADD R8, R5, R8 ; /* 0x0000000805087221 */
/* 0x000fc80000000000 */
/*07e0*/ FFMA R6, R11, -R6, R8 ; /* 0x800000060b067223 */
/* 0x001fc80000000008 */
/*07f0*/ FADD R8, R9, -R6 ; /* 0x8000000609087221 */
/* 0x000fe20000000000 */
/*0800*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x000fc60007ffe0ff */
/*0810*/ FADD R9, -R9, R8 ; /* 0x0000000809097221 */
/* 0x000fe20000000100 */
/*0820*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0830*/ ISETP.GE.AND P0, PT, R20, c[0x0][0x190], PT ; /* 0x0000640014007a0c */
/* 0x000fe40003f06270 */
/*0840*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x000fc80000000000 */
/*0850*/ FFMA R9, R4, -R7, R9 ; /* 0x8000000704097223 */
/* 0x002fc80000000009 */
/*0860*/ FADD R7, R8, -R9 ; /* 0x8000000908077221 */
/* 0x000fe20000000000 */
/*0870*/ IADD3 R14, P1, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe40007f3e0ff */
/*0880*/ IADD3 R15, P2, R15, 0x10, RZ ; /* 0x000000100f0f7810 */
/* 0x000fe20007f5e0ff */
/*0890*/ FADD R8, -R8, R7 ; /* 0x0000000708087221 */
/* 0x000fe20000000100 */
/*08a0*/ IADD3.X R19, RZ, R19, RZ, P1, !PT ; /* 0x00000013ff137210 */
/* 0x000fe40000ffe4ff */
/*08b0*/ IADD3.X R18, RZ, R18, RZ, P2, !PT ; /* 0x00000012ff127210 */
/* 0x000fe200017fe4ff */
/*08c0*/ FADD R23, R9, R8 ; /* 0x0000000809177221 */
/* 0x000fe20000000000 */
/*08d0*/ @!P0 BRA 0x250 ; /* 0xfffff97000008947 */
/* 0x000fea000383ffff */
/*08e0*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x000fe2000c101904 */
/*08f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Second CUDA program
// Ping-Che Chen
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda_runtime.h>
#define BLOCK_SIZE 16
__global__ static void matMultCUDA(const float* a, size_t lda, const float* b, size_t ldb, float* c, size_t ldc, int n)
{
__shared__ float matA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float matB[BLOCK_SIZE][BLOCK_SIZE];
const int tidc = threadIdx.x;
const int tidr = threadIdx.y;
const int bidc = blockIdx.x * BLOCK_SIZE;
const int bidr = blockIdx.y * BLOCK_SIZE;
int i, j;
float results = 0;
float comp = 0;
for(j = 0; j < n; j += BLOCK_SIZE) {
matA[tidr][tidc] = a[(tidr + bidr) * lda + tidc + j];
matB[tidr][tidc] = b[(tidr + j) * ldb + tidc + bidc];
__syncthreads();
for(i = 0; i < BLOCK_SIZE; i++) {
float t;
comp -= matA[tidr][i] * matB[i][tidc];
t = results - comp;
comp = (t - results) + comp;
results = t;
}
__syncthreads();
}
c[(tidr + bidr) * ldc + tidc + bidc] = results;
} | .file "tmpxft_00099b09_00000000-6_second_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL11matMultCUDAPKfmS0_mPfmi, @function
_ZL11matMultCUDAPKfmS0_mPfmi:
.LFB2082:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
movl 208(%rsp), %eax
movl %eax, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _ZL11matMultCUDAPKfmS0_mPfmi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _ZL11matMultCUDAPKfmS0_mPfmi, .-_ZL11matMultCUDAPKfmS0_mPfmi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11matMultCUDAPKfmS0_mPfmi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11matMultCUDAPKfmS0_mPfmi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Second CUDA program
// Ping-Che Chen
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda_runtime.h>
#define BLOCK_SIZE 16
__global__ static void matMultCUDA(const float* a, size_t lda, const float* b, size_t ldb, float* c, size_t ldc, int n)
{
__shared__ float matA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float matB[BLOCK_SIZE][BLOCK_SIZE];
const int tidc = threadIdx.x;
const int tidr = threadIdx.y;
const int bidc = blockIdx.x * BLOCK_SIZE;
const int bidr = blockIdx.y * BLOCK_SIZE;
int i, j;
float results = 0;
float comp = 0;
for(j = 0; j < n; j += BLOCK_SIZE) {
matA[tidr][tidc] = a[(tidr + bidr) * lda + tidc + j];
matB[tidr][tidc] = b[(tidr + j) * ldb + tidc + bidc];
__syncthreads();
for(i = 0; i < BLOCK_SIZE; i++) {
float t;
comp -= matA[tidr][i] * matB[i][tidc];
t = results - comp;
comp = (t - results) + comp;
results = t;
}
__syncthreads();
}
c[(tidr + bidr) * ldc + tidc + bidc] = results;
} | // Second CUDA program
// Ping-Che Chen
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 16
__global__ static void matMultCUDA(const float* a, size_t lda, const float* b, size_t ldb, float* c, size_t ldc, int n)
{
__shared__ float matA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float matB[BLOCK_SIZE][BLOCK_SIZE];
const int tidc = threadIdx.x;
const int tidr = threadIdx.y;
const int bidc = blockIdx.x * BLOCK_SIZE;
const int bidr = blockIdx.y * BLOCK_SIZE;
int i, j;
float results = 0;
float comp = 0;
for(j = 0; j < n; j += BLOCK_SIZE) {
matA[tidr][tidc] = a[(tidr + bidr) * lda + tidc + j];
matB[tidr][tidc] = b[(tidr + j) * ldb + tidc + bidc];
__syncthreads();
for(i = 0; i < BLOCK_SIZE; i++) {
float t;
comp -= matA[tidr][i] * matB[i][tidc];
t = results - comp;
comp = (t - results) + comp;
results = t;
}
__syncthreads();
}
c[(tidr + bidr) * ldc + tidc + bidc] = results;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Second CUDA program
// Ping-Che Chen
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 16
__global__ static void matMultCUDA(const float* a, size_t lda, const float* b, size_t ldb, float* c, size_t ldc, int n)
{
__shared__ float matA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float matB[BLOCK_SIZE][BLOCK_SIZE];
const int tidc = threadIdx.x;
const int tidr = threadIdx.y;
const int bidc = blockIdx.x * BLOCK_SIZE;
const int bidr = blockIdx.y * BLOCK_SIZE;
int i, j;
float results = 0;
float comp = 0;
for(j = 0; j < n; j += BLOCK_SIZE) {
matA[tidr][tidc] = a[(tidr + bidr) * lda + tidc + j];
matB[tidr][tidc] = b[(tidr + j) * ldb + tidc + bidc];
__syncthreads();
for(i = 0; i < BLOCK_SIZE; i++) {
float t;
comp -= matA[tidr][i] * matB[i][tidc];
t = results - comp;
comp = (t - results) + comp;
results = t;
}
__syncthreads();
}
c[(tidr + bidr) * ldc + tidc + bidc] = results;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL11matMultCUDAPKfmS0_mPfmi,"axG",@progbits,_ZL11matMultCUDAPKfmS0_mPfmi,comdat
.globl _ZL11matMultCUDAPKfmS0_mPfmi
.p2align 8
.type _ZL11matMultCUDAPKfmS0_mPfmi,@function
_ZL11matMultCUDAPKfmS0_mPfmi:
s_load_b32 s12, s[0:1], 0x30
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s2, s15, 4
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v1, s2, v2
s_lshl_b32 s2, s14, 4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_5
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v1
v_dual_mov_b32 v8, 0 :: v_dual_lshlrev_b32 v11, 2, v0
s_ashr_i32 s3, s2, 31
v_lshlrev_b32_e32 v4, 6, v2
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v3, v3, s6
v_mul_lo_u32 v5, v1, s7
v_mad_u64_u32 v[6:7], null, v1, s6, 0
s_lshl_b64 s[6:7], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s3, s6, s8
s_addc_u32 s6, s7, s9
v_add3_u32 v7, v7, v5, v3
v_add_nc_u32_e32 v5, 0x400, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[6:7]
v_add_nc_u32_e32 v6, v4, v11
v_add_co_u32 v3, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v9, s3, s3, v11
v_add_co_u32 v11, vcc_lo, v3, v11
v_mov_b32_e32 v3, 0
v_add_nc_u32_e32 v7, v5, v4
v_add_co_ci_u32_e64 v10, null, s6, 0, s3
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s4, s5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v17, s4, v2
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[13:14], null, v17, s10, 0
v_mad_u64_u32 v[15:16], null, v17, s11, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mov_b32_e32 v14, v15
v_add_co_u32 v15, vcc_lo, v11, s6
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v12, vcc_lo
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, v9, v13
v_add_co_ci_u32_e32 v14, vcc_lo, v10, v14, vcc_lo
global_load_b32 v15, v[15:16], off
global_load_b32 v14, v[13:14], off
v_mov_b32_e32 v13, v5
s_waitcnt vmcnt(1)
ds_store_b32 v6, v15
s_waitcnt vmcnt(0)
ds_store_b32 v7, v14
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v14, s3, v4
v_mov_b32_e32 v16, v3
s_add_i32 s3, s3, 4
ds_load_b32 v15, v13
ds_load_b32 v14, v14
v_add_nc_u32_e32 v13, 64, v13
s_cmp_lg_u32 s3, 64
s_waitcnt lgkmcnt(0)
v_fma_f32 v8, -v14, v15, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v16, v8
v_sub_f32_e32 v14, v3, v16
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v8, v8, v14
s_cbranch_scc1 .LBB0_3
s_add_i32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s4, s12
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v3, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b128 s[4:7], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v0, 2, v0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v2, s6
v_mul_lo_u32 v6, v1, s7
v_mad_u64_u32 v[4:5], null, v1, s6, 0
v_add3_u32 v5, v5, v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[4:5]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, s0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL11matMultCUDAPKfmS0_mPfmi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 52
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL11matMultCUDAPKfmS0_mPfmi,"axG",@progbits,_ZL11matMultCUDAPKfmS0_mPfmi,comdat
.Lfunc_end0:
.size _ZL11matMultCUDAPKfmS0_mPfmi, .Lfunc_end0-_ZL11matMultCUDAPKfmS0_mPfmi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 52
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL11matMultCUDAPKfmS0_mPfmi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL11matMultCUDAPKfmS0_mPfmi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Second CUDA program
// Ping-Che Chen
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 16
__global__ static void matMultCUDA(const float* a, size_t lda, const float* b, size_t ldb, float* c, size_t ldc, int n)
{
__shared__ float matA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float matB[BLOCK_SIZE][BLOCK_SIZE];
const int tidc = threadIdx.x;
const int tidr = threadIdx.y;
const int bidc = blockIdx.x * BLOCK_SIZE;
const int bidr = blockIdx.y * BLOCK_SIZE;
int i, j;
float results = 0;
float comp = 0;
for(j = 0; j < n; j += BLOCK_SIZE) {
matA[tidr][tidc] = a[(tidr + bidr) * lda + tidc + j];
matB[tidr][tidc] = b[(tidr + j) * ldb + tidc + bidc];
__syncthreads();
for(i = 0; i < BLOCK_SIZE; i++) {
float t;
comp -= matA[tidr][i] * matB[i][tidc];
t = results - comp;
comp = (t - results) + comp;
results = t;
}
__syncthreads();
}
c[(tidr + bidr) * ldc + tidc + bidc] = results;
} | .text
.file "second_cuda.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11matMultCUDAPKfmS0_mPfmi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R15, SR_TID.Y ; /* 0x00000000000f7919 */
/* 0x000e680000002200 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000ea20000002100 */
/*0060*/ SHF.L.U32 R9, R9, 0x4, RZ ; /* 0x0000000409097819 */
/* 0x001fe400000006ff */
/*0070*/ LEA R5, R2, R15, 0x4 ; /* 0x0000000f02057211 */
/* 0x002fc400078e20ff */
/*0080*/ SHF.R.S32.HI R6, RZ, 0x1f, R0 ; /* 0x0000001fff067819 */
/* 0x004fe40000011400 */
/*0090*/ IADD3 R2, P0, R9.reuse, R0, RZ ; /* 0x0000000009027210 */
/* 0x040fe40007f1e0ff */
/*00a0*/ SHF.R.S32.HI R4, RZ, 0x1f, R5 ; /* 0x0000001fff047819 */
/* 0x000fe40000011405 */
/*00b0*/ LEA.HI.X.SX32 R3, R9, R6, 0x1, P0 ; /* 0x0000000609037211 */
/* 0x000fe400000f0eff */
/*00c0*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x190], PT ; /* 0x00006400ff007a0c */
/* 0x000fe20003f01270 */
/*00d0*/ IMAD R6, R4, c[0x0][0x188], RZ ; /* 0x0000620004067a24 */
/* 0x000fe400078e02ff */
/*00e0*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x188], R2 ; /* 0x0000620005027a25 */
/* 0x000fc800078e0002 */
/*00f0*/ IMAD R7, R5, c[0x0][0x18c], R6 ; /* 0x0000630005077a24 */
/* 0x000fe200078e0206 */
/*0100*/ LEA R12, P1, R2, c[0x0][0x180], 0x2 ; /* 0x00006000020c7a11 */
/* 0x000fc800078210ff */
/*0110*/ IADD3 R3, R3, R7, RZ ; /* 0x0000000703037210 */
/* 0x000fe40007ffe0ff */
/*0120*/ @!P0 MOV R7, RZ ; /* 0x000000ff00078202 */
/* 0x000fe40000000f00 */
/*0130*/ LEA.HI.X R13, R2, c[0x0][0x184], R3, 0x2, P1 ; /* 0x00006100020d7a11 */
/* 0x000fe200008f1403 */
/*0140*/ @!P0 BRA 0x8e0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD R4, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a24 */
/* 0x000fe200078e02ff */
/*0160*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*0170*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*0180*/ MOV R2, R0.reuse ; /* 0x0000000000027202 */
/* 0x080fe20000000f00 */
/*0190*/ IMAD R19, R5, c[0x0][0x16c], R4 ; /* 0x00005b0005137a24 */
/* 0x000fe200078e0204 */
/*01a0*/ SHF.L.U32 R17, R15, 0x6, RZ ; /* 0x000000060f117819 */
/* 0x000fe200000006ff */
/*01b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*01c0*/ SHF.R.S32.HI R18, RZ, 0x1f, R15 ; /* 0x0000001fff127819 */
/* 0x000fe2000001140f */
/*01d0*/ IMAD.WIDE.U32 R4, R5, c[0x0][0x168], R2 ; /* 0x00005a0005047a25 */
/* 0x000fe200078e0002 */
/*01e0*/ IADD3 R2, P0, R9, R0, RZ ; /* 0x0000000009027210 */
/* 0x000fc40007f1e0ff */
/*01f0*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe40000000f00 */
/*0200*/ IADD3 R19, R5, R19, RZ ; /* 0x0000001305137210 */
/* 0x000fe40007ffe0ff */
/*0210*/ LEA R14, P1, R4.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800040e7a11 */
/* 0x040fe400078210ff */
/*0220*/ LEA.HI.X.SX32 R3, R9, R3, 0x1, P0 ; /* 0x0000000309037211 */
/* 0x000fe400000f0eff */
/*0230*/ LEA.HI.X R19, R4, c[0x0][0x164], R19, 0x2, P1 ; /* 0x0000590004137a11 */
/* 0x000fe400008f1413 */
/*0240*/ LEA R16, R0, R17, 0x2 ; /* 0x0000001100107211 */
/* 0x000fc400078e10ff */
/*0250*/ IMAD R4, R18, c[0x0][0x178], RZ ; /* 0x00005e0012047a24 */
/* 0x000fe200078e02ff */
/*0260*/ MOV R25, R19 ; /* 0x0000001300197202 */
/* 0x000fe20000000f00 */
/*0270*/ IMAD.WIDE.U32 R8, R15, c[0x0][0x178], R2 ; /* 0x00005e000f087a25 */
/* 0x000fe200078e0002 */
/*0280*/ MOV R24, R14 ; /* 0x0000000e00187202 */
/* 0x000fc60000000f00 */
/*0290*/ IMAD R5, R15, c[0x0][0x17c], R4 ; /* 0x00005f000f057a24 */
/* 0x000fe200078e0204 */
/*02a0*/ LEA R4, P0, R8, c[0x0][0x170], 0x2 ; /* 0x00005c0008047a11 */
/* 0x000fe200078010ff */
/*02b0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea6000c1e1900 */
/*02c0*/ IADD3 R5, R9, R5, RZ ; /* 0x0000000509057210 */
/* 0x000fc80007ffe0ff */
/*02d0*/ LEA.HI.X R5, R8, c[0x0][0x174], R5, 0x2, P0 ; /* 0x00005d0008057a11 */
/* 0x000fcc00000f1405 */
/*02e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee8000c1e1900 */
/*02f0*/ STS [R16], R25 ; /* 0x0000001910007388 */
/* 0x004fe80000000800 */
/*0300*/ STS [R16+0x400], R5 ; /* 0x0004000510007388 */
/* 0x008fe80000000800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0320*/ LDS R6, [R0.X4+0x400] ; /* 0x0004000000067984 */
/* 0x000fe80000004800 */
/*0330*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*0340*/ LDS R26, [R0.X4+0x440] ; /* 0x00044000001a7984 */
/* 0x000e680000004800 */
/*0350*/ LDS R21, [R0.X4+0x480] ; /* 0x0004800000157984 */
/* 0x000ea20000004800 */
/*0360*/ FFMA R6, R6, -R8, R23 ; /* 0x8000000806067223 */
/* 0x001fc60000000017 */
/*0370*/ LDS R8, [R0.X4+0x4c0] ; /* 0x0004c00000087984 */
/* 0x000e220000004800 */
/*0380*/ FADD R22, -R6, R7 ; /* 0x0000000706167221 */
/* 0x000fc80000000100 */
/*0390*/ FADD R7, R22, -R7 ; /* 0x8000000716077221 */
/* 0x000fc80000000000 */
/*03a0*/ FADD R6, R6, R7 ; /* 0x0000000706067221 */
/* 0x000fc80000000000 */
/*03b0*/ FFMA R23, R26, -R9, R6 ; /* 0x800000091a177223 */
/* 0x002fe40000000006 */
/*03c0*/ LDS R9, [R0.X4+0x500] ; /* 0x0005000000097984 */
/* 0x000fe40000004800 */
/*03d0*/ FADD R25, R22.reuse, -R23 ; /* 0x8000001716197221 */
/* 0x040fe40000000000 */
/*03e0*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000e640000000c00 */
/*03f0*/ FADD R22, -R22, R25 ; /* 0x0000001916167221 */
/* 0x000fc80000000100 */
/*0400*/ FADD R22, R23, R22 ; /* 0x0000001617167221 */
/* 0x000fc80000000000 */
/*0410*/ FFMA R22, R21, -R10, R22 ; /* 0x8000000a15167223 */
/* 0x004fe40000000016 */
/*0420*/ LDS R10, [R0.X4+0x540] ; /* 0x00054000000a7984 */
/* 0x000ea40000004800 */
/*0430*/ FADD R24, R25.reuse, -R22 ; /* 0x8000001619187221 */
/* 0x040fe40000000000 */
/*0440*/ LDS R21, [R0.X4+0x580] ; /* 0x0005800000157984 */
/* 0x000ee40000004800 */
/*0450*/ FADD R25, -R25, R24 ; /* 0x0000001819197221 */
/* 0x000fc80000000100 */
/*0460*/ FADD R25, R22, R25 ; /* 0x0000001916197221 */
/* 0x000fc80000000000 */
/*0470*/ FFMA R11, R8, -R11, R25 ; /* 0x8000000b080b7223 */
/* 0x001fc80000000019 */
/*0480*/ FADD R23, R24, -R11 ; /* 0x8000000b18177221 */
/* 0x000fc80000000000 */
/*0490*/ FADD R24, -R24, R23 ; /* 0x0000001718187221 */
/* 0x000fc80000000100 */
/*04a0*/ FADD R24, R11, R24 ; /* 0x000000180b187221 */
/* 0x000fc80000000000 */
/*04b0*/ FFMA R24, R9, -R4, R24 ; /* 0x8000000409187223 */
/* 0x002fe40000000018 */
/*04c0*/ LDS R4, [R0.X4+0x5c0] ; /* 0x0005c00000047984 */
/* 0x000e240000004800 */
/*04d0*/ FADD R22, R23, -R24 ; /* 0x8000001817167221 */
/* 0x000fc80000000000 */
/*04e0*/ FADD R23, -R23, R22 ; /* 0x0000001617177221 */
/* 0x000fc80000000100 */
/*04f0*/ FADD R23, R24, R23 ; /* 0x0000001718177221 */
/* 0x000fc80000000000 */
/*0500*/ FFMA R23, R10, -R5, R23 ; /* 0x800000050a177223 */
/* 0x004fe40000000017 */
/*0510*/ LDS R5, [R0.X4+0x600] ; /* 0x0006000000057984 */
/* 0x000fe40000004800 */
/*0520*/ FADD R25, R22.reuse, -R23 ; /* 0x8000001716197221 */
/* 0x040fe40000000000 */
/*0530*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e640000000c00 */
/*0540*/ FADD R22, -R22, R25 ; /* 0x0000001916167221 */
/* 0x000fc80000000100 */
/*0550*/ FADD R22, R23, R22 ; /* 0x0000001617167221 */
/* 0x000fc80000000000 */
/*0560*/ FFMA R22, R21, -R6, R22 ; /* 0x8000000615167223 */
/* 0x008fe40000000016 */
/*0570*/ LDS R6, [R0.X4+0x640] ; /* 0x0006400000067984 */
/* 0x000ea40000004800 */
/*0580*/ FADD R24, R25.reuse, -R22 ; /* 0x8000001619187221 */
/* 0x040fe40000000000 */
/*0590*/ LDS R21, [R0.X4+0x680] ; /* 0x0006800000157984 */
/* 0x000ee40000004800 */
/*05a0*/ FADD R25, -R25, R24 ; /* 0x0000001819197221 */
/* 0x000fc80000000100 */
/*05b0*/ FADD R25, R22, R25 ; /* 0x0000001916197221 */
/* 0x000fc80000000000 */
/*05c0*/ FFMA R7, R4, -R7, R25 ; /* 0x8000000704077223 */
/* 0x001fc80000000019 */
/*05d0*/ FADD R23, R24, -R7 ; /* 0x8000000718177221 */
/* 0x000fc80000000000 */
/*05e0*/ FADD R24, -R24, R23 ; /* 0x0000001718187221 */
/* 0x000fc80000000100 */
/*05f0*/ FADD R24, R7, R24 ; /* 0x0000001807187221 */
/* 0x000fc80000000000 */
/*0600*/ FFMA R24, R5, -R8, R24 ; /* 0x8000000805187223 */
/* 0x002fe40000000018 */
/*0610*/ LDS R8, [R0.X4+0x6c0] ; /* 0x0006c00000087984 */
/* 0x000e240000004800 */
/*0620*/ FADD R22, R23, -R24 ; /* 0x8000001817167221 */
/* 0x000fc80000000000 */
/*0630*/ FADD R23, -R23, R22 ; /* 0x0000001617177221 */
/* 0x000fc80000000100 */
/*0640*/ FADD R23, R24, R23 ; /* 0x0000001718177221 */
/* 0x000fc80000000000 */
/*0650*/ FFMA R23, R6, -R9, R23 ; /* 0x8000000906177223 */
/* 0x004fe40000000017 */
/*0660*/ LDS R9, [R0.X4+0x700] ; /* 0x0007000000097984 */
/* 0x000fe40000004800 */
/*0670*/ FADD R25, R22.reuse, -R23 ; /* 0x8000001716197221 */
/* 0x040fe40000000000 */
/*0680*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000e640000000c00 */
/*0690*/ FADD R22, -R22, R25 ; /* 0x0000001916167221 */
/* 0x000fc80000000100 */
/*06a0*/ FADD R22, R23, R22 ; /* 0x0000001617167221 */
/* 0x000fc80000000000 */
/*06b0*/ FFMA R22, R21, -R10, R22 ; /* 0x8000000a15167223 */
/* 0x008fe40000000016 */
/*06c0*/ LDS R10, [R0.X4+0x740] ; /* 0x00074000000a7984 */
/* 0x000ea40000004800 */
/*06d0*/ FADD R24, R25, -R22 ; /* 0x8000001619187221 */
/* 0x000fc80000000000 */
/*06e0*/ FADD R25, -R25, R24 ; /* 0x0000001819197221 */
/* 0x000fc80000000100 */
/*06f0*/ FADD R25, R22, R25 ; /* 0x0000001916197221 */
/* 0x000fc80000000000 */
/*0700*/ FFMA R25, R8, -R11, R25 ; /* 0x8000000b08197223 */
/* 0x001fe40000000019 */
/*0710*/ LDS R11, [R0.X4+0x780] ; /* 0x00078000000b7984 */
/* 0x000e240000004800 */
/*0720*/ FADD R21, R24, -R25 ; /* 0x8000001918157221 */
/* 0x000fc80000000000 */
/*0730*/ FADD R24, -R24, R21 ; /* 0x0000001518187221 */
/* 0x000fc80000000100 */
/*0740*/ FADD R24, R25, R24 ; /* 0x0000001819187221 */
/* 0x000fc80000000000 */
/*0750*/ FFMA R24, R9, -R4, R24 ; /* 0x8000000409187223 */
/* 0x002fe40000000018 */
/*0760*/ LDS R4, [R0.X4+0x7c0] ; /* 0x0007c00000047984 */
/* 0x000e640000004800 */
/*0770*/ FADD R8, R21, -R24 ; /* 0x8000001815087221 */
/* 0x000fc80000000000 */
/*0780*/ FADD R21, -R21, R8 ; /* 0x0000000815157221 */
/* 0x000fc80000000100 */
/*0790*/ FADD R21, R24, R21 ; /* 0x0000001518157221 */
/* 0x000fc80000000000 */
/*07a0*/ FFMA R5, R10, -R5, R21 ; /* 0x800000050a057223 */
/* 0x004fc80000000015 */
/*07b0*/ FADD R9, R8, -R5 ; /* 0x8000000508097221 */
/* 0x000fc80000000000 */
/*07c0*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x000fc80000000100 */
/*07d0*/ FADD R8, R5, R8 ; /* 0x0000000805087221 */
/* 0x000fc80000000000 */
/*07e0*/ FFMA R6, R11, -R6, R8 ; /* 0x800000060b067223 */
/* 0x001fc80000000008 */
/*07f0*/ FADD R8, R9, -R6 ; /* 0x8000000609087221 */
/* 0x000fe20000000000 */
/*0800*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x000fc60007ffe0ff */
/*0810*/ FADD R9, -R9, R8 ; /* 0x0000000809097221 */
/* 0x000fe20000000100 */
/*0820*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0830*/ ISETP.GE.AND P0, PT, R20, c[0x0][0x190], PT ; /* 0x0000640014007a0c */
/* 0x000fe40003f06270 */
/*0840*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x000fc80000000000 */
/*0850*/ FFMA R9, R4, -R7, R9 ; /* 0x8000000704097223 */
/* 0x002fc80000000009 */
/*0860*/ FADD R7, R8, -R9 ; /* 0x8000000908077221 */
/* 0x000fe20000000000 */
/*0870*/ IADD3 R14, P1, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe40007f3e0ff */
/*0880*/ IADD3 R15, P2, R15, 0x10, RZ ; /* 0x000000100f0f7810 */
/* 0x000fe20007f5e0ff */
/*0890*/ FADD R8, -R8, R7 ; /* 0x0000000708087221 */
/* 0x000fe20000000100 */
/*08a0*/ IADD3.X R19, RZ, R19, RZ, P1, !PT ; /* 0x00000013ff137210 */
/* 0x000fe40000ffe4ff */
/*08b0*/ IADD3.X R18, RZ, R18, RZ, P2, !PT ; /* 0x00000012ff127210 */
/* 0x000fe200017fe4ff */
/*08c0*/ FADD R23, R9, R8 ; /* 0x0000000809177221 */
/* 0x000fe20000000000 */
/*08d0*/ @!P0 BRA 0x250 ; /* 0xfffff97000008947 */
/* 0x000fea000383ffff */
/*08e0*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x000fe2000c101904 */
/*08f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL11matMultCUDAPKfmS0_mPfmi,"axG",@progbits,_ZL11matMultCUDAPKfmS0_mPfmi,comdat
.globl _ZL11matMultCUDAPKfmS0_mPfmi
.p2align 8
.type _ZL11matMultCUDAPKfmS0_mPfmi,@function
_ZL11matMultCUDAPKfmS0_mPfmi:
s_load_b32 s12, s[0:1], 0x30
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s2, s15, 4
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v1, s2, v2
s_lshl_b32 s2, s14, 4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_5
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v1
v_dual_mov_b32 v8, 0 :: v_dual_lshlrev_b32 v11, 2, v0
s_ashr_i32 s3, s2, 31
v_lshlrev_b32_e32 v4, 6, v2
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v3, v3, s6
v_mul_lo_u32 v5, v1, s7
v_mad_u64_u32 v[6:7], null, v1, s6, 0
s_lshl_b64 s[6:7], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s3, s6, s8
s_addc_u32 s6, s7, s9
v_add3_u32 v7, v7, v5, v3
v_add_nc_u32_e32 v5, 0x400, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[6:7]
v_add_nc_u32_e32 v6, v4, v11
v_add_co_u32 v3, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v9, s3, s3, v11
v_add_co_u32 v11, vcc_lo, v3, v11
v_mov_b32_e32 v3, 0
v_add_nc_u32_e32 v7, v5, v4
v_add_co_ci_u32_e64 v10, null, s6, 0, s3
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s4, s5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v17, s4, v2
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[13:14], null, v17, s10, 0
v_mad_u64_u32 v[15:16], null, v17, s11, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mov_b32_e32 v14, v15
v_add_co_u32 v15, vcc_lo, v11, s6
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v12, vcc_lo
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, v9, v13
v_add_co_ci_u32_e32 v14, vcc_lo, v10, v14, vcc_lo
global_load_b32 v15, v[15:16], off
global_load_b32 v14, v[13:14], off
v_mov_b32_e32 v13, v5
s_waitcnt vmcnt(1)
ds_store_b32 v6, v15
s_waitcnt vmcnt(0)
ds_store_b32 v7, v14
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v14, s3, v4
v_mov_b32_e32 v16, v3
s_add_i32 s3, s3, 4
ds_load_b32 v15, v13
ds_load_b32 v14, v14
v_add_nc_u32_e32 v13, 64, v13
s_cmp_lg_u32 s3, 64
s_waitcnt lgkmcnt(0)
v_fma_f32 v8, -v14, v15, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v16, v8
v_sub_f32_e32 v14, v3, v16
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v8, v8, v14
s_cbranch_scc1 .LBB0_3
s_add_i32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s4, s12
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v3, 0
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b128 s[4:7], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v0, 2, v0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v2, s6
v_mul_lo_u32 v6, v1, s7
v_mad_u64_u32 v[4:5], null, v1, s6, 0
v_add3_u32 v5, v5, v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[4:5]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, s0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL11matMultCUDAPKfmS0_mPfmi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 52
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL11matMultCUDAPKfmS0_mPfmi,"axG",@progbits,_ZL11matMultCUDAPKfmS0_mPfmi,comdat
.Lfunc_end0:
.size _ZL11matMultCUDAPKfmS0_mPfmi, .Lfunc_end0-_ZL11matMultCUDAPKfmS0_mPfmi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 52
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL11matMultCUDAPKfmS0_mPfmi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL11matMultCUDAPKfmS0_mPfmi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00099b09_00000000-6_second_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL11matMultCUDAPKfmS0_mPfmi, @function
_ZL11matMultCUDAPKfmS0_mPfmi:
.LFB2082:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
movl 208(%rsp), %eax
movl %eax, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _ZL11matMultCUDAPKfmS0_mPfmi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _ZL11matMultCUDAPKfmS0_mPfmi, .-_ZL11matMultCUDAPKfmS0_mPfmi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11matMultCUDAPKfmS0_mPfmi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11matMultCUDAPKfmS0_mPfmi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "second_cuda.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __host__ __device__ inline bool is_I_up(float a, float y, float Cp, float Cn) {
return (y > 0 && a < Cp) || (y < 0 && a > 0);
}
__host__ __device__ inline bool is_I_low(float a, float y, float Cp, float Cn) {
return (y > 0 && a > 0) || (y < 0 && a < Cn);
}
__host__ __device__ inline bool is_free(float a, float y, float Cp, float Cn) {
return a > 0 && (y > 0 ? a < Cp : a < Cn);
}
__host__ __device__ inline bool min_t(float a, float y) {
return a > y ? y : a;
}
__host__ __device__ inline bool max_t(float a, float y) {
return a > y ? a : y;
}
__device__ int get_block_min_t(const float *values, int *index) {
int tid = threadIdx.x;
index[tid] = tid;
__syncthreads();
//block size is always the power of 2
for (int offset = blockDim.x / 2; offset > 0; offset >>= 1) {
if (tid < offset) {
if (values[index[tid + offset]] < values[index[tid]]) {
index[tid] = index[tid + offset];
}
}
__syncthreads();
}
return index[0];
}
__global__ void
c_smo_solve_kernel(const int *label, float *f_val, float *alpha, float *alpha_diff,
const int *working_set, int ws_size,
float Cp, float Cn, const float *k_mat_rows, const float *k_mat_diag, int row_len,
float eps,
float *diff, int max_t_iter) {
//"row_len" equals to the number of instances in the original training dataset.
//allocate shared memory
__shared__ int shared_mem[256];
int *f_idx2reduce = shared_mem; //temporary memory for reduction
float *f_val2reduce = (float *) &shared_mem[ws_size]; //f values used for reduction.
float *alpha_i_diff = (float *) &shared_mem[ws_size + ws_size * sizeof(float) / sizeof(int)]; //delta alpha_i
float *alpha_j_diff = &alpha_i_diff[1];
float *kd = (float *) &alpha_j_diff[1]; // diagonal elements for kernel matrix
//index, f value and alpha for each instance
int tid = threadIdx.x;
int wsi = working_set[tid];
kd[tid] = k_mat_diag[wsi];
float y = label[wsi];
float f = f_val[wsi];
float a = alpha[wsi];
float aold = a;
__syncthreads();
float local_eps;
int numOfIter = 0;
while (1) {
//select fUp and fLow
if (is_I_up(a, y, Cp, Cn))
f_val2reduce[tid] = f;
else
f_val2reduce[tid] = INFINITY;
int i = get_block_min_t(f_val2reduce, f_idx2reduce);
float up_value = f_val2reduce[i];
float kIwsI = k_mat_rows[row_len * i + wsi];//K[i, wsi]
__syncthreads();
if (is_I_low(a, y, Cp, Cn))
f_val2reduce[tid] = -f;
else
f_val2reduce[tid] = INFINITY;
int j1 = get_block_min_t(f_val2reduce, f_idx2reduce);
float low_value = -f_val2reduce[j1];
float local_diff = low_value - up_value;
if (numOfIter == 0) {
local_eps = max_t(eps, 0.1f * local_diff);
if (tid == 0) {
diff[0] = local_diff;
}
}
if (numOfIter > max_t_iter || local_diff < local_eps) {
alpha[wsi] = a;
alpha_diff[tid] = -(a - aold) * y;
diff[1] = numOfIter;
break;
}
__syncthreads();
//select j2 using second order heuristic
if (-up_value > -f && (is_I_low(a, y, Cp, Cn))) {
float aIJ = kd[i] + kd[tid] - 2 * kIwsI;
float bIJ = -up_value + f;
f_val2reduce[tid] = (-bIJ * bIJ / aIJ);
} else
f_val2reduce[tid] = INFINITY;
int j2 = get_block_min_t(f_val2reduce, f_idx2reduce);
//update alpha
if (tid == i)
*alpha_i_diff = y > 0 ? Cp - a : a;
if (tid == j2)
*alpha_j_diff = min_t(y > 0 ? a : Cn - a, (-up_value + f) / (kd[i] + kd[j2] - 2 * kIwsI));
__syncthreads();
float l = min_t(*alpha_i_diff, *alpha_j_diff);
if (tid == i)
a += l * y;
if (tid == j2)
a -= l * y;
//update f
float kJ2wsI = k_mat_rows[row_len * j2 + wsi];//K[J2, wsi]
f -= l * (kJ2wsI - kIwsI);
numOfIter++;
}
} | .file "tmpxft_00132439_00000000-6_new-fun.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15get_block_min_tPKfPi
.type _Z15get_block_min_tPKfPi, @function
_Z15get_block_min_tPKfPi:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z15get_block_min_tPKfPi, .-_Z15get_block_min_tPKfPi
.globl _Z65__device_stub__Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_iPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.type _Z65__device_stub__Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_iPKiPfS1_S1_S0_iffPKfS3_ifS1_i, @function
_Z65__device_stub__Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_iPKiPfS1_S1_S0_iffPKfS3_ifS1_i:
.LFB2057:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movl %r9d, 36(%rsp)
movss %xmm0, 32(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm2, 24(%rsp)
movq 288(%rsp), %rax
movq %rax, 16(%rsp)
movq 296(%rsp), %rax
movq %rax, 8(%rsp)
movq 312(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
movq %rsp, %rax
movq %rax, 240(%rsp)
leaq 320(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z65__device_stub__Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_iPKiPfS1_S1_S0_iffPKfS3_ifS1_i, .-_Z65__device_stub__Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_iPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.globl _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.type _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, @function
_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i:
.LFB2058:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z65__device_stub__Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_iPKiPfS1_S1_S0_iffPKfS3_ifS1_i
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, .-_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __host__ __device__ inline bool is_I_up(float a, float y, float Cp, float Cn) {
return (y > 0 && a < Cp) || (y < 0 && a > 0);
}
__host__ __device__ inline bool is_I_low(float a, float y, float Cp, float Cn) {
return (y > 0 && a > 0) || (y < 0 && a < Cn);
}
__host__ __device__ inline bool is_free(float a, float y, float Cp, float Cn) {
return a > 0 && (y > 0 ? a < Cp : a < Cn);
}
__host__ __device__ inline bool min_t(float a, float y) {
return a > y ? y : a;
}
__host__ __device__ inline bool max_t(float a, float y) {
return a > y ? a : y;
}
__device__ int get_block_min_t(const float *values, int *index) {
int tid = threadIdx.x;
index[tid] = tid;
__syncthreads();
//block size is always the power of 2
for (int offset = blockDim.x / 2; offset > 0; offset >>= 1) {
if (tid < offset) {
if (values[index[tid + offset]] < values[index[tid]]) {
index[tid] = index[tid + offset];
}
}
__syncthreads();
}
return index[0];
}
__global__ void
c_smo_solve_kernel(const int *label, float *f_val, float *alpha, float *alpha_diff,
const int *working_set, int ws_size,
float Cp, float Cn, const float *k_mat_rows, const float *k_mat_diag, int row_len,
float eps,
float *diff, int max_t_iter) {
//"row_len" equals to the number of instances in the original training dataset.
//allocate shared memory
__shared__ int shared_mem[256];
int *f_idx2reduce = shared_mem; //temporary memory for reduction
float *f_val2reduce = (float *) &shared_mem[ws_size]; //f values used for reduction.
float *alpha_i_diff = (float *) &shared_mem[ws_size + ws_size * sizeof(float) / sizeof(int)]; //delta alpha_i
float *alpha_j_diff = &alpha_i_diff[1];
float *kd = (float *) &alpha_j_diff[1]; // diagonal elements for kernel matrix
//index, f value and alpha for each instance
int tid = threadIdx.x;
int wsi = working_set[tid];
kd[tid] = k_mat_diag[wsi];
float y = label[wsi];
float f = f_val[wsi];
float a = alpha[wsi];
float aold = a;
__syncthreads();
float local_eps;
int numOfIter = 0;
while (1) {
//select fUp and fLow
if (is_I_up(a, y, Cp, Cn))
f_val2reduce[tid] = f;
else
f_val2reduce[tid] = INFINITY;
int i = get_block_min_t(f_val2reduce, f_idx2reduce);
float up_value = f_val2reduce[i];
float kIwsI = k_mat_rows[row_len * i + wsi];//K[i, wsi]
__syncthreads();
if (is_I_low(a, y, Cp, Cn))
f_val2reduce[tid] = -f;
else
f_val2reduce[tid] = INFINITY;
int j1 = get_block_min_t(f_val2reduce, f_idx2reduce);
float low_value = -f_val2reduce[j1];
float local_diff = low_value - up_value;
if (numOfIter == 0) {
local_eps = max_t(eps, 0.1f * local_diff);
if (tid == 0) {
diff[0] = local_diff;
}
}
if (numOfIter > max_t_iter || local_diff < local_eps) {
alpha[wsi] = a;
alpha_diff[tid] = -(a - aold) * y;
diff[1] = numOfIter;
break;
}
__syncthreads();
//select j2 using second order heuristic
if (-up_value > -f && (is_I_low(a, y, Cp, Cn))) {
float aIJ = kd[i] + kd[tid] - 2 * kIwsI;
float bIJ = -up_value + f;
f_val2reduce[tid] = (-bIJ * bIJ / aIJ);
} else
f_val2reduce[tid] = INFINITY;
int j2 = get_block_min_t(f_val2reduce, f_idx2reduce);
//update alpha
if (tid == i)
*alpha_i_diff = y > 0 ? Cp - a : a;
if (tid == j2)
*alpha_j_diff = min_t(y > 0 ? a : Cn - a, (-up_value + f) / (kd[i] + kd[j2] - 2 * kIwsI));
__syncthreads();
float l = min_t(*alpha_i_diff, *alpha_j_diff);
if (tid == i)
a += l * y;
if (tid == j2)
a -= l * y;
//update f
float kJ2wsI = k_mat_rows[row_len * j2 + wsi];//K[J2, wsi]
f -= l * (kJ2wsI - kIwsI);
numOfIter++;
}
} | #include <hip/hip_runtime.h>
__host__ __device__ inline bool is_I_up(float a, float y, float Cp, float Cn) {
return (y > 0 && a < Cp) || (y < 0 && a > 0);
}
__host__ __device__ inline bool is_I_low(float a, float y, float Cp, float Cn) {
return (y > 0 && a > 0) || (y < 0 && a < Cn);
}
__host__ __device__ inline bool is_free(float a, float y, float Cp, float Cn) {
return a > 0 && (y > 0 ? a < Cp : a < Cn);
}
__host__ __device__ inline bool min_t(float a, float y) {
return a > y ? y : a;
}
__host__ __device__ inline bool max_t(float a, float y) {
return a > y ? a : y;
}
__device__ int get_block_min_t(const float *values, int *index) {
int tid = threadIdx.x;
index[tid] = tid;
__syncthreads();
//block size is always the power of 2
for (int offset = blockDim.x / 2; offset > 0; offset >>= 1) {
if (tid < offset) {
if (values[index[tid + offset]] < values[index[tid]]) {
index[tid] = index[tid + offset];
}
}
__syncthreads();
}
return index[0];
}
__global__ void
c_smo_solve_kernel(const int *label, float *f_val, float *alpha, float *alpha_diff,
const int *working_set, int ws_size,
float Cp, float Cn, const float *k_mat_rows, const float *k_mat_diag, int row_len,
float eps,
float *diff, int max_t_iter) {
//"row_len" equals to the number of instances in the original training dataset.
//allocate shared memory
__shared__ int shared_mem[256];
int *f_idx2reduce = shared_mem; //temporary memory for reduction
float *f_val2reduce = (float *) &shared_mem[ws_size]; //f values used for reduction.
float *alpha_i_diff = (float *) &shared_mem[ws_size + ws_size * sizeof(float) / sizeof(int)]; //delta alpha_i
float *alpha_j_diff = &alpha_i_diff[1];
float *kd = (float *) &alpha_j_diff[1]; // diagonal elements for kernel matrix
//index, f value and alpha for each instance
int tid = threadIdx.x;
int wsi = working_set[tid];
kd[tid] = k_mat_diag[wsi];
float y = label[wsi];
float f = f_val[wsi];
float a = alpha[wsi];
float aold = a;
__syncthreads();
float local_eps;
int numOfIter = 0;
while (1) {
//select fUp and fLow
if (is_I_up(a, y, Cp, Cn))
f_val2reduce[tid] = f;
else
f_val2reduce[tid] = INFINITY;
int i = get_block_min_t(f_val2reduce, f_idx2reduce);
float up_value = f_val2reduce[i];
float kIwsI = k_mat_rows[row_len * i + wsi];//K[i, wsi]
__syncthreads();
if (is_I_low(a, y, Cp, Cn))
f_val2reduce[tid] = -f;
else
f_val2reduce[tid] = INFINITY;
int j1 = get_block_min_t(f_val2reduce, f_idx2reduce);
float low_value = -f_val2reduce[j1];
float local_diff = low_value - up_value;
if (numOfIter == 0) {
local_eps = max_t(eps, 0.1f * local_diff);
if (tid == 0) {
diff[0] = local_diff;
}
}
if (numOfIter > max_t_iter || local_diff < local_eps) {
alpha[wsi] = a;
alpha_diff[tid] = -(a - aold) * y;
diff[1] = numOfIter;
break;
}
__syncthreads();
//select j2 using second order heuristic
if (-up_value > -f && (is_I_low(a, y, Cp, Cn))) {
float aIJ = kd[i] + kd[tid] - 2 * kIwsI;
float bIJ = -up_value + f;
f_val2reduce[tid] = (-bIJ * bIJ / aIJ);
} else
f_val2reduce[tid] = INFINITY;
int j2 = get_block_min_t(f_val2reduce, f_idx2reduce);
//update alpha
if (tid == i)
*alpha_i_diff = y > 0 ? Cp - a : a;
if (tid == j2)
*alpha_j_diff = min_t(y > 0 ? a : Cn - a, (-up_value + f) / (kd[i] + kd[j2] - 2 * kIwsI));
__syncthreads();
float l = min_t(*alpha_i_diff, *alpha_j_diff);
if (tid == i)
a += l * y;
if (tid == j2)
a -= l * y;
//update f
float kJ2wsI = k_mat_rows[row_len * j2 + wsi];//K[J2, wsi]
f -= l * (kJ2wsI - kIwsI);
numOfIter++;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__host__ __device__ inline bool is_I_up(float a, float y, float Cp, float Cn) {
return (y > 0 && a < Cp) || (y < 0 && a > 0);
}
__host__ __device__ inline bool is_I_low(float a, float y, float Cp, float Cn) {
return (y > 0 && a > 0) || (y < 0 && a < Cn);
}
__host__ __device__ inline bool is_free(float a, float y, float Cp, float Cn) {
return a > 0 && (y > 0 ? a < Cp : a < Cn);
}
__host__ __device__ inline bool min_t(float a, float y) {
return a > y ? y : a;
}
__host__ __device__ inline bool max_t(float a, float y) {
return a > y ? a : y;
}
__device__ int get_block_min_t(const float *values, int *index) {
int tid = threadIdx.x;
index[tid] = tid;
__syncthreads();
//block size is always the power of 2
for (int offset = blockDim.x / 2; offset > 0; offset >>= 1) {
if (tid < offset) {
if (values[index[tid + offset]] < values[index[tid]]) {
index[tid] = index[tid + offset];
}
}
__syncthreads();
}
return index[0];
}
__global__ void
c_smo_solve_kernel(const int *label, float *f_val, float *alpha, float *alpha_diff,
const int *working_set, int ws_size,
float Cp, float Cn, const float *k_mat_rows, const float *k_mat_diag, int row_len,
float eps,
float *diff, int max_t_iter) {
//"row_len" equals to the number of instances in the original training dataset.
//allocate shared memory
__shared__ int shared_mem[256];
int *f_idx2reduce = shared_mem; //temporary memory for reduction
float *f_val2reduce = (float *) &shared_mem[ws_size]; //f values used for reduction.
float *alpha_i_diff = (float *) &shared_mem[ws_size + ws_size * sizeof(float) / sizeof(int)]; //delta alpha_i
float *alpha_j_diff = &alpha_i_diff[1];
float *kd = (float *) &alpha_j_diff[1]; // diagonal elements for kernel matrix
//index, f value and alpha for each instance
int tid = threadIdx.x;
int wsi = working_set[tid];
kd[tid] = k_mat_diag[wsi];
float y = label[wsi];
float f = f_val[wsi];
float a = alpha[wsi];
float aold = a;
__syncthreads();
float local_eps;
int numOfIter = 0;
while (1) {
//select fUp and fLow
if (is_I_up(a, y, Cp, Cn))
f_val2reduce[tid] = f;
else
f_val2reduce[tid] = INFINITY;
int i = get_block_min_t(f_val2reduce, f_idx2reduce);
float up_value = f_val2reduce[i];
float kIwsI = k_mat_rows[row_len * i + wsi];//K[i, wsi]
__syncthreads();
if (is_I_low(a, y, Cp, Cn))
f_val2reduce[tid] = -f;
else
f_val2reduce[tid] = INFINITY;
int j1 = get_block_min_t(f_val2reduce, f_idx2reduce);
float low_value = -f_val2reduce[j1];
float local_diff = low_value - up_value;
if (numOfIter == 0) {
local_eps = max_t(eps, 0.1f * local_diff);
if (tid == 0) {
diff[0] = local_diff;
}
}
if (numOfIter > max_t_iter || local_diff < local_eps) {
alpha[wsi] = a;
alpha_diff[tid] = -(a - aold) * y;
diff[1] = numOfIter;
break;
}
__syncthreads();
//select j2 using second order heuristic
if (-up_value > -f && (is_I_low(a, y, Cp, Cn))) {
float aIJ = kd[i] + kd[tid] - 2 * kIwsI;
float bIJ = -up_value + f;
f_val2reduce[tid] = (-bIJ * bIJ / aIJ);
} else
f_val2reduce[tid] = INFINITY;
int j2 = get_block_min_t(f_val2reduce, f_idx2reduce);
//update alpha
if (tid == i)
*alpha_i_diff = y > 0 ? Cp - a : a;
if (tid == j2)
*alpha_j_diff = min_t(y > 0 ? a : Cn - a, (-up_value + f) / (kd[i] + kd[j2] - 2 * kIwsI));
__syncthreads();
float l = min_t(*alpha_i_diff, *alpha_j_diff);
if (tid == i)
a += l * y;
if (tid == j2)
a -= l * y;
//update f
float kJ2wsI = k_mat_rows[row_len * j2 + wsi];//K[J2, wsi]
f -= l * (kJ2wsI - kIwsI);
numOfIter++;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.globl _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.p2align 8
.type _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i,@function
_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b32 s24, s[0:1], 0x30
v_dual_mov_b32 v11, 0x7f800000 :: v_dual_lshlrev_b32 v6, 2, v0
s_clause 0x1
s_load_b256 s[8:15], s[0:1], 0x38
s_load_b256 s[16:23], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v6, s[4:5]
s_lshl_b32 s5, s6, 3
s_lshl_b32 s6, s6, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v12, s6, v6
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v5, vcc_lo
s_add_i32 s10, s5, 8
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v9, s10, v6
global_load_b32 v10, v[2:3], off
v_add_co_u32 v2, vcc_lo, s16, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v5, vcc_lo
s_mov_b32 s17, 0
global_load_b32 v14, v[2:3], off
v_add_co_u32 v2, vcc_lo, s20, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s21, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s18, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s19, v5, vcc_lo
global_load_b32 v7, v[2:3], off
global_load_b32 v8, v[4:5], off
s_waitcnt vmcnt(3)
ds_store_b32 v9, v10
v_mov_b32_e32 v10, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s3, s[0:1], 0x6c
s_load_b32 s11, s[0:1], 0x58
v_add_co_u32 v4, s1, s22, v6
v_cmp_eq_u32_e64 s0, 0, v0
v_add_co_ci_u32_e64 v5, null, s23, 0, s1
v_cvt_f32_i32_e32 v13, v14
v_cmp_lt_i32_e64 s1, 0, v14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s2, 1
v_cmp_gt_i32_e64 s2, 0, v14
v_mov_b32_e32 v14, v7
s_cselect_b32 s16, -1, 0
s_bfe_u32 s18, s3, 0xf0001
s_branch .LBB0_3
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s20
v_mad_u64_u32 v[17:18], null, v20, s12, v[1:2]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_add_i32 s17, s17, 1
v_ashrrev_i32_e32 v18, 31, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_add_co_u32 v17, vcc_lo, s8, v17
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v18, vcc_lo, s9, v18, vcc_lo
global_load_b32 v19, v[17:18], off
v_mov_b32_e32 v17, s5
ds_load_2addr_b32 v[17:18], v17 offset1:1
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v17, v18
s_waitcnt vmcnt(0)
v_dual_cndmask_b32 v17, v17, v18 :: v_dual_sub_f32 v16, v19, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_neq_f32_e32 vcc_lo, 0, v17
v_cndmask_b32_e64 v17, 0, 1.0, vcc_lo
v_mul_f32_e32 v18, v13, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v16, v17, v8
v_cndmask_b32_e64 v20, 0x80000000, v18, s3
v_cndmask_b32_e64 v18, 0, v18, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v14, v14, v20
v_sub_f32_e32 v14, v14, v18
.LBB0_2:
s_xor_b32 s3, s19, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_43
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, s7, v14
v_cmp_lt_f32_e64 s3, 0, v14
s_and_b32 s4, s1, vcc_lo
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s4, s3
s_xor_b32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_xor_b32 s3, exec_lo, s4
s_cbranch_execz .LBB0_5
ds_store_b32 v12, v11
.LBB0_5:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_7
ds_store_b32 v12, v8
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s16
s_mov_b32 s3, s18
ds_store_b32 v6, v0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_32
.LBB0_8:
ds_load_b32 v18, v10
v_cmp_gt_f32_e64 s3, s24, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_and_b32 s3, s2, s3
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[16:17], null, v18, s12, v[1:2]
v_ashrrev_i32_e32 v17, 31, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[16:17], 2, v[16:17]
v_add_co_u32 v16, vcc_lo, s8, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v17, vcc_lo, s9, v17, vcc_lo
v_cmp_lt_f32_e32 vcc_lo, 0, v14
global_load_b32 v16, v[16:17], off
v_lshlrev_b32_e32 v17, 2, v18
s_and_b32 s4, s1, vcc_lo
s_or_b32 s3, s4, s3
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v19, s6, v17
s_xor_b32 s3, s3, -1
ds_load_b32 v19, v19
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s19, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s19
s_cbranch_execz .LBB0_10
ds_store_b32 v12, v11
.LBB0_10:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_12
v_xor_b32_e32 v20, 0x80000000, v8
ds_store_b32 v12, v20
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s16
s_mov_b32 s3, s18
ds_store_b32 v6, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_36
.LBB0_13:
ds_load_b32 v20, v10
s_cmp_lg_u32 s17, 0
s_waitcnt lgkmcnt(0)
v_lshlrev_b32_e32 v20, 2, v20
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v20, s6, v20
ds_load_b32 v20, v20
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v20, -v20, v19
s_cbranch_scc1 .LBB0_17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v15, 0x3dcccccd, v20
v_cmp_gt_f32_e32 vcc_lo, s13, v15
v_cndmask_b32_e64 v15, v15, s13, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_neq_f32_e32 vcc_lo, 0, v15
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB0_16
global_store_b32 v10, v20, s[14:15]
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s3
v_cndmask_b32_e64 v15, 0, 1.0, vcc_lo
.LBB0_17:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f32_e32 vcc_lo, v20, v15
s_cmp_le_i32 s17, s11
s_cselect_b32 s3, -1, 0
s_and_b32 s19, s3, vcc_lo
s_mov_b32 s3, -1
s_and_b32 vcc_lo, exec_lo, s19
s_cbranch_vccnz .LBB0_19
v_sub_f32_e32 v20, v14, v7
v_cvt_f32_i32_e32 v21, s17
s_mov_b32 s3, 0
global_store_b32 v[2:3], v14, off
v_mul_f32_e64 v20, v13, -v20
global_store_b32 v[4:5], v20, off
global_store_b32 v10, v21, s[14:15] offset:4
.LBB0_19:
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_2
v_cmp_nlt_f32_e64 s20, v19, v8
s_mov_b32 s3, 0
s_mov_b32 s21, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_lt_f32_e32 v19, v8
v_cmp_gt_f32_e32 vcc_lo, s24, v14
s_and_not1_b32 s20, s20, exec_lo
s_mov_b32 s3, exec_lo
s_and_b32 s22, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s4, s4, s22
s_xor_b32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, s4, exec_lo
s_or_b32 s20, s20, s4
s_or_b32 exec_lo, exec_lo, s21
s_and_saveexec_b32 s4, s20
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_24
s_and_not1_b32 s3, s3, exec_lo
ds_store_b32 v12, v11
.LBB0_24:
s_or_b32 exec_lo, exec_lo, s4
v_sub_f32_e32 v19, v8, v19
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_26
v_add_nc_u32_e32 v20, s10, v17
ds_load_b32 v20, v20
ds_load_b32 v21, v9
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v20, v20, v21
v_mul_f32_e64 v21, v19, -v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v20, -2.0, v16
v_div_scale_f32 v22, null, v20, v20, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v23, v22
s_waitcnt_depctr 0xfff
v_fma_f32 v24, -v22, v23, 1.0
v_fmac_f32_e32 v23, v24, v23
v_div_scale_f32 v24, vcc_lo, v21, v20, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v25, v24, v23
v_fma_f32 v26, -v22, v25, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v25, v26, v23
v_fma_f32 v22, -v22, v25, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v22, v22, v23, v25
v_div_fixup_f32 v20, v22, v20, v21
ds_store_b32 v12, v20
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s16
s_mov_b32 s3, s18
ds_store_b32 v6, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_40
.LBB0_27:
ds_load_b32 v20, v10
v_cmp_eq_u32_e64 s3, v0, v18
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_29
v_dual_sub_f32 v18, s7, v14 :: v_dual_mov_b32 v21, s5
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v18, v14, v18, s1
ds_store_b32 v21, v18
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e64 s4, v0, v20
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s20, s4
s_cbranch_execz .LBB0_1
v_lshlrev_b32_e32 v18, 2, v20
v_add_nc_u32_e32 v17, s10, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v18, s10, v18
ds_load_b32 v17, v17
ds_load_b32 v18, v18
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v17, v17, v18
v_fmac_f32_e32 v17, -2.0, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v18, null, v17, v17, v19
v_div_scale_f32 v23, vcc_lo, v19, v17, v19
v_rcp_f32_e32 v21, v18
s_waitcnt_depctr 0xfff
v_fma_f32 v22, -v18, v21, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v21, v22, v21
v_mul_f32_e32 v22, v23, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v24, -v18, v22, v23
v_fmac_f32_e32 v22, v24, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v18, -v18, v22, v23
v_sub_f32_e32 v23, s24, v14
v_div_fmas_f32 v18, v18, v21, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v21, v23, v14, s1
v_div_fixup_f32 v17, v18, v17, v19
v_mov_b32_e32 v18, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, v21, v17
v_cndmask_b32_e32 v17, v21, v17, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v17
v_cndmask_b32_e64 v17, 0, 1.0, vcc_lo
ds_store_b32 v18, v17 offset:4
s_branch .LBB0_1
.p2align 6
.LBB0_31:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_8
.LBB0_32:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_31
v_lshl_add_u32 v16, s3, 2, v6
ds_load_b32 v16, v16
ds_load_b32 v17, v6
s_waitcnt lgkmcnt(1)
v_lshl_add_u32 v18, v16, 2, s6
s_waitcnt lgkmcnt(0)
v_lshl_add_u32 v17, v17, 2, s6
ds_load_b32 v18, v18
ds_load_b32 v17, v17
s_waitcnt lgkmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v18, v17
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_31
ds_store_b32 v6, v16
s_branch .LBB0_31
.p2align 6
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s19
s_lshr_b32 s19, s3, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s19
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_13
.LBB0_36:
s_mov_b32 s19, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_35
v_lshl_add_u32 v20, s3, 2, v6
ds_load_b32 v20, v20
ds_load_b32 v21, v6
s_waitcnt lgkmcnt(1)
v_lshl_add_u32 v22, v20, 2, s6
s_waitcnt lgkmcnt(0)
v_lshl_add_u32 v21, v21, 2, s6
ds_load_b32 v22, v22
ds_load_b32 v21, v21
s_waitcnt lgkmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v22, v21
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_35
ds_store_b32 v6, v20
s_branch .LBB0_35
.p2align 6
.LBB0_39:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_27
.LBB0_40:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_39
v_lshl_add_u32 v20, s3, 2, v6
ds_load_b32 v20, v20
ds_load_b32 v21, v6
s_waitcnt lgkmcnt(1)
v_lshl_add_u32 v22, v20, 2, s6
s_waitcnt lgkmcnt(0)
v_lshl_add_u32 v21, v21, 2, s6
ds_load_b32 v22, v22
ds_load_b32 v21, v21
s_waitcnt lgkmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v22, v21
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_39
ds_store_b32 v6, v20
s_branch .LBB0_39
.LBB0_43:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 352
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, .Lfunc_end0-_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .offset: 88
.size: 4
.value_kind: by_value
- .offset: 96
.size: 4
.value_kind: hidden_block_count_x
- .offset: 100
.size: 4
.value_kind: hidden_block_count_y
- .offset: 104
.size: 4
.value_kind: hidden_block_count_z
- .offset: 108
.size: 2
.value_kind: hidden_group_size_x
- .offset: 110
.size: 2
.value_kind: hidden_group_size_y
- .offset: 112
.size: 2
.value_kind: hidden_group_size_z
- .offset: 114
.size: 2
.value_kind: hidden_remainder_x
- .offset: 116
.size: 2
.value_kind: hidden_remainder_y
- .offset: 118
.size: 2
.value_kind: hidden_remainder_z
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 160
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 352
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__host__ __device__ inline bool is_I_up(float a, float y, float Cp, float Cn) {
return (y > 0 && a < Cp) || (y < 0 && a > 0);
}
__host__ __device__ inline bool is_I_low(float a, float y, float Cp, float Cn) {
return (y > 0 && a > 0) || (y < 0 && a < Cn);
}
__host__ __device__ inline bool is_free(float a, float y, float Cp, float Cn) {
return a > 0 && (y > 0 ? a < Cp : a < Cn);
}
__host__ __device__ inline bool min_t(float a, float y) {
return a > y ? y : a;
}
__host__ __device__ inline bool max_t(float a, float y) {
return a > y ? a : y;
}
__device__ int get_block_min_t(const float *values, int *index) {
int tid = threadIdx.x;
index[tid] = tid;
__syncthreads();
//block size is always the power of 2
for (int offset = blockDim.x / 2; offset > 0; offset >>= 1) {
if (tid < offset) {
if (values[index[tid + offset]] < values[index[tid]]) {
index[tid] = index[tid + offset];
}
}
__syncthreads();
}
return index[0];
}
__global__ void
c_smo_solve_kernel(const int *label, float *f_val, float *alpha, float *alpha_diff,
const int *working_set, int ws_size,
float Cp, float Cn, const float *k_mat_rows, const float *k_mat_diag, int row_len,
float eps,
float *diff, int max_t_iter) {
//"row_len" equals to the number of instances in the original training dataset.
//allocate shared memory
__shared__ int shared_mem[256];
int *f_idx2reduce = shared_mem; //temporary memory for reduction
float *f_val2reduce = (float *) &shared_mem[ws_size]; //f values used for reduction.
float *alpha_i_diff = (float *) &shared_mem[ws_size + ws_size * sizeof(float) / sizeof(int)]; //delta alpha_i
float *alpha_j_diff = &alpha_i_diff[1];
float *kd = (float *) &alpha_j_diff[1]; // diagonal elements for kernel matrix
//index, f value and alpha for each instance
int tid = threadIdx.x;
int wsi = working_set[tid];
kd[tid] = k_mat_diag[wsi];
float y = label[wsi];
float f = f_val[wsi];
float a = alpha[wsi];
float aold = a;
__syncthreads();
float local_eps;
int numOfIter = 0;
while (1) {
//select fUp and fLow
if (is_I_up(a, y, Cp, Cn))
f_val2reduce[tid] = f;
else
f_val2reduce[tid] = INFINITY;
int i = get_block_min_t(f_val2reduce, f_idx2reduce);
float up_value = f_val2reduce[i];
float kIwsI = k_mat_rows[row_len * i + wsi];//K[i, wsi]
__syncthreads();
if (is_I_low(a, y, Cp, Cn))
f_val2reduce[tid] = -f;
else
f_val2reduce[tid] = INFINITY;
int j1 = get_block_min_t(f_val2reduce, f_idx2reduce);
float low_value = -f_val2reduce[j1];
float local_diff = low_value - up_value;
if (numOfIter == 0) {
local_eps = max_t(eps, 0.1f * local_diff);
if (tid == 0) {
diff[0] = local_diff;
}
}
if (numOfIter > max_t_iter || local_diff < local_eps) {
alpha[wsi] = a;
alpha_diff[tid] = -(a - aold) * y;
diff[1] = numOfIter;
break;
}
__syncthreads();
//select j2 using second order heuristic
if (-up_value > -f && (is_I_low(a, y, Cp, Cn))) {
float aIJ = kd[i] + kd[tid] - 2 * kIwsI;
float bIJ = -up_value + f;
f_val2reduce[tid] = (-bIJ * bIJ / aIJ);
} else
f_val2reduce[tid] = INFINITY;
int j2 = get_block_min_t(f_val2reduce, f_idx2reduce);
//update alpha
if (tid == i)
*alpha_i_diff = y > 0 ? Cp - a : a;
if (tid == j2)
*alpha_j_diff = min_t(y > 0 ? a : Cn - a, (-up_value + f) / (kd[i] + kd[j2] - 2 * kIwsI));
__syncthreads();
float l = min_t(*alpha_i_diff, *alpha_j_diff);
if (tid == i)
a += l * y;
if (tid == j2)
a -= l * y;
//update f
float kJ2wsI = k_mat_rows[row_len * j2 + wsi];//K[J2, wsi]
f -= l * (kJ2wsI - kIwsI);
numOfIter++;
}
} | .text
.file "new-fun.hip"
.globl _Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i # -- Begin function _Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.p2align 4, 0x90
.type _Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i,@function
_Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i: # @_Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 272(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, .Lfunc_end0-_Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i,@object # @_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.section .rodata,"a",@progbits
.globl _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.p2align 3, 0x0
_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i:
.quad _Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.size _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i"
.size .L__unnamed_1, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00132439_00000000-6_new-fun.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15get_block_min_tPKfPi
.type _Z15get_block_min_tPKfPi, @function
_Z15get_block_min_tPKfPi:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z15get_block_min_tPKfPi, .-_Z15get_block_min_tPKfPi
.globl _Z65__device_stub__Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_iPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.type _Z65__device_stub__Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_iPKiPfS1_S1_S0_iffPKfS3_ifS1_i, @function
_Z65__device_stub__Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_iPKiPfS1_S1_S0_iffPKfS3_ifS1_i:
.LFB2057:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movl %r9d, 36(%rsp)
movss %xmm0, 32(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm2, 24(%rsp)
movq 288(%rsp), %rax
movq %rax, 16(%rsp)
movq 296(%rsp), %rax
movq %rax, 8(%rsp)
movq 312(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
movq %rsp, %rax
movq %rax, 240(%rsp)
leaq 320(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z65__device_stub__Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_iPKiPfS1_S1_S0_iffPKfS3_ifS1_i, .-_Z65__device_stub__Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_iPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.globl _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.type _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, @function
_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i:
.LFB2058:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z65__device_stub__Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_iPKiPfS1_S1_S0_iffPKfS3_ifS1_i
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, .-_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "new-fun.hip"
.globl _Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i # -- Begin function _Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.p2align 4, 0x90
.type _Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i,@function
_Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i: # @_Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 272(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, .Lfunc_end0-_Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i,@object # @_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.section .rodata,"a",@progbits
.globl _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.p2align 3, 0x0
_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i:
.quad _Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.size _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i"
.size .L__unnamed_1, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18c_smo_solve_kernelPKiPfS1_S1_S0_iffPKfS3_ifS1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #pragma once
struct Mat4
{
float elements[16];
__device__ float operator[](int i)
{
return elements[i];
}
};
__device__ float3 operator+(float3 v1, float3 v2)
{
return make_float3(v1.x + v2.x, v1.y + v2.y, v1.z + v2.z);
}
__device__ float3 operator+(float3 v, float f)
{
return make_float3(v.x + f, v.y + f, v.z + f);
}
__device__ float3 operator-(float3 v1, float3 v2)
{
return make_float3(v1.x - v2.x, v1.y - v2.y, v1.z - v2.z);
}
__device__ float3 operator*(float3 v1, float3 v2)
{
return make_float3(v1.x * v2.x, v1.y * v2.y, v1.z * v2.z);
}
__device__ float3 operator*(float3 v, float f)
{
return make_float3(v.x * f, v.y * f, v.z * f);
}
__device__ float3 operator-(float3 v)
{
return make_float3(-v.x, -v.y, -v.z);
}
__device__ float3 operator/(float3 v1, float3 v2)
{
return make_float3(v1.x / v2.x, v1.y / v2.y, v1.z / v2.z);
}
__device__ float3 operator/(float3 v, float f)
{
return make_float3(v.x / f, v.y / f, v.z / f);
}
__device__ float3 operator/(float f, float3 v)
{
return make_float3(f / v.x, f / v.y, f / v.z);
}
__device__ bool operator!=(float3 v1, float3 v2)
{
return v1.x != v2.x || v1.y != v2.y || v1.z != v2.z;
}
__device__ bool operator!=(int3 v1, int3 v2)
{
return v1.x != v2.x || v1.y != v2.y || v1.z != v2.z;
}
__device__ bool operator==(float3 v1, float3 v2)
{
return v1.x == v2.x && v1.y == v2.y && v1.z == v2.z;
}
__device__ bool operator==(int3 v1, int3 v2)
{
return v1.x == v2.x && v1.y == v2.y && v1.z == v2.z;
}
__device__ void operator-=(float3& v, float f)
{
v.x -= f;
v.y -= f;
v.z -= f;
}
__device__ float3 operator*(Mat4& m, float3 v)
{
float x = m[0] * v.x + m[4] * v.y + m[8] * v.z + m[12];
float y = m[1] * v.x + m[5] * v.y + m[9] * v.z + m[13];
float z = m[2] * v.x + m[6] * v.y + m[10] * v.z + m[14];
float w = m[3] * v.x + m[7] * v.y + m[11] * v.z + m[15];
return make_float3(x, y, z);
}
__device__ float get(float3 v, int index)
{
float* ptr = (float*)&v;
return *(ptr + index);
}
__device__ void set(float3& v, int index, float value)
{
float* ptr = (float*)&v;
*(ptr + index) = value;
}
__device__ float sign(float f)
{
return f < 0.0f ? -1.0f : (f > 0.0f ? 1.0f : 0.0f);
}
__device__ float3 sign(float3 v)
{
return make_float3(sign(v.x), sign(v.y), sign(v.z));
}
__device__ float min(float3 v)
{
return min(v.x, min(v.y, v.z));
}
__device__ float max(float3 v)
{
return max(v.x, max(v.y, v.z));
}
__device__ float3 abs(float3 v)
{
return make_float3(abs(v.x), abs(v.y), abs(v.z));
}
__device__ int3 toInt3(float3 v)
{
return make_int3(floor(v.x), floor(v.y), floor(v.z));
}
__device__ float3 toFloat3(int3 v)
{
return make_float3(float(v.x), float(v.y), float(v.z));
}
__device__ float3 cross(float3 v1, float3 v2)
{
return make_float3(
v1.y * v2.z - v1.z * v2.y,
v1.z * v2.x - v1.x * v2.z,
v1.x * v2.y - v1.y * v2.x);
}
__device__ float dot(float3 v1, float3 v2)
{
return v1.x * v2.x + v1.y * v2.y + v1.z * v2.z;
}
__device__ float length(float3 v)
{
return sqrt(v.x * v.x + v.y * v.y + v.z * v.z);
}
__device__ float3 normalize(float3 v)
{
return v / length(v);
}
__device__ void swap(float3& v1, float3& v2)
{
float3 tmp = v1;
v1 = v2;
v2 = tmp;
}
__device__
int2 operator*(int2 v1, int2 v2)
{
return make_int2(v1.x * v2.x, v1.y * v2.y);
}
__device__
int3 operator+(int3 v1, int3 v2)
{
return make_int3(v1.x + v2.x, v1.y + v2.y, v1.z + v2.z);
}
__device__
int3 operator-(int3 v1, int3 v2)
{
return make_int3(v1.x - v2.x, v1.y - v2.y, v1.z - v2.z);
}
__device__
int3 operator*(int3 v1, int3 v2)
{
return make_int3(v1.x * v2.x, v1.y * v2.y, v1.z * v2.z);
}
__device__
int3 operator*(int3 v, int i)
{
return make_int3(v.x * i, v.y * i, v.z * i);
}
__device__
void operator-=(int3& v, int i)
{
v.x -= i;
v.y -= i;
v.z -= i;
}
__device__ int& get(int3& v, int index)
{
return *((int*)&v + index);
}
__device__ void set(int3& v, int index, int value)
{
int* ptr = ((int*)&v + index);
*ptr = value;
}
__device__
int2 toInt2(int3 v, int axis1, int axis2)
{
return make_int2(get(v, axis1), get(v, axis2));
}
__device__
int min(int3 v)
{
return min(v.x, min(v.y, v.z));
}
__device__
int sign(int i)
{
return i < 0 ? -1 : (i > 0 ? 1 : 0);
}
__device__
int3 sign(int3 v)
{
return make_int3(sign(v.x), sign(v.y), sign(v.z));
}
__device__
int3 abs(int3 v)
{
return make_int3(abs(v.x), abs(v.y), abs(v.z));
}
__device__
int dot(int2 v1, int2 v2)
{
return v1.x * v2.x + v1.y * v2.y;
}
__device__
int3 cross(int3 v1, int3 v2)
{
return make_int3(
v1.y * v2.z - v1.z * v2.y,
v1.z * v2.x - v1.x * v2.z,
v1.x * v2.y - v1.y * v2.x);
}
__device__ int max(int3 v)
{
return max(v.x, max(v.y, v.z));
}
__device__
int sum(int2 v)
{
return v.x + v.y;
}
__device__
void swap(int3& v1, int3& v2)
{
int3 tmp = v1;
v1 = v2;
v2 = tmp;
}
__device__ float2 operator+(float2 v1, float2 v2)
{
return make_float2(v1.x + v2.x, v1.y + v2.y);
}
__device__ float2 operator-(float2 v1, float2 v2)
{
return make_float2(v1.x - v2.x, v1.y - v2.y);
}
__device__ float2 operator*(float2 v, float f)
{
return make_float2(v.x * f, v.y * f);
}
__device__ float2 operator/(float2 v, float f)
{
return make_float2(v.x / f, v.y / f);
}
__device__ float& get(float2& v, int index)
{
float* ptr = (float*)&v;
return *(ptr + index);
}
__device__ float length(float2 v)
{
return sqrt(v.x * v.x + v.y * v.y);
}
__device__ float2 toFloat2(float3 v, int axis1, int axis2)
{
return make_float2(get(v, axis1), get(v, axis2));
}
__device__ float2 normalize(float2 v)
{
return v / length(v);
}
__device__ float dot(float2 v1, float2 v2)
{
return v1.x * v2.x + v1.y * v2.y;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #pragma once
struct Mat4
{
float elements[16];
__device__ float operator[](int i)
{
return elements[i];
}
};
__device__ float3 operator+(float3 v1, float3 v2)
{
return make_float3(v1.x + v2.x, v1.y + v2.y, v1.z + v2.z);
}
__device__ float3 operator+(float3 v, float f)
{
return make_float3(v.x + f, v.y + f, v.z + f);
}
__device__ float3 operator-(float3 v1, float3 v2)
{
return make_float3(v1.x - v2.x, v1.y - v2.y, v1.z - v2.z);
}
__device__ float3 operator*(float3 v1, float3 v2)
{
return make_float3(v1.x * v2.x, v1.y * v2.y, v1.z * v2.z);
}
__device__ float3 operator*(float3 v, float f)
{
return make_float3(v.x * f, v.y * f, v.z * f);
}
__device__ float3 operator-(float3 v)
{
return make_float3(-v.x, -v.y, -v.z);
}
__device__ float3 operator/(float3 v1, float3 v2)
{
return make_float3(v1.x / v2.x, v1.y / v2.y, v1.z / v2.z);
}
__device__ float3 operator/(float3 v, float f)
{
return make_float3(v.x / f, v.y / f, v.z / f);
}
__device__ float3 operator/(float f, float3 v)
{
return make_float3(f / v.x, f / v.y, f / v.z);
}
__device__ bool operator!=(float3 v1, float3 v2)
{
return v1.x != v2.x || v1.y != v2.y || v1.z != v2.z;
}
__device__ bool operator!=(int3 v1, int3 v2)
{
return v1.x != v2.x || v1.y != v2.y || v1.z != v2.z;
}
__device__ bool operator==(float3 v1, float3 v2)
{
return v1.x == v2.x && v1.y == v2.y && v1.z == v2.z;
}
__device__ bool operator==(int3 v1, int3 v2)
{
return v1.x == v2.x && v1.y == v2.y && v1.z == v2.z;
}
__device__ void operator-=(float3& v, float f)
{
v.x -= f;
v.y -= f;
v.z -= f;
}
__device__ float3 operator*(Mat4& m, float3 v)
{
float x = m[0] * v.x + m[4] * v.y + m[8] * v.z + m[12];
float y = m[1] * v.x + m[5] * v.y + m[9] * v.z + m[13];
float z = m[2] * v.x + m[6] * v.y + m[10] * v.z + m[14];
float w = m[3] * v.x + m[7] * v.y + m[11] * v.z + m[15];
return make_float3(x, y, z);
}
__device__ float get(float3 v, int index)
{
float* ptr = (float*)&v;
return *(ptr + index);
}
__device__ void set(float3& v, int index, float value)
{
float* ptr = (float*)&v;
*(ptr + index) = value;
}
__device__ float sign(float f)
{
return f < 0.0f ? -1.0f : (f > 0.0f ? 1.0f : 0.0f);
}
__device__ float3 sign(float3 v)
{
return make_float3(sign(v.x), sign(v.y), sign(v.z));
}
__device__ float min(float3 v)
{
return min(v.x, min(v.y, v.z));
}
__device__ float max(float3 v)
{
return max(v.x, max(v.y, v.z));
}
__device__ float3 abs(float3 v)
{
return make_float3(abs(v.x), abs(v.y), abs(v.z));
}
__device__ int3 toInt3(float3 v)
{
return make_int3(floor(v.x), floor(v.y), floor(v.z));
}
__device__ float3 toFloat3(int3 v)
{
return make_float3(float(v.x), float(v.y), float(v.z));
}
__device__ float3 cross(float3 v1, float3 v2)
{
return make_float3(
v1.y * v2.z - v1.z * v2.y,
v1.z * v2.x - v1.x * v2.z,
v1.x * v2.y - v1.y * v2.x);
}
__device__ float dot(float3 v1, float3 v2)
{
return v1.x * v2.x + v1.y * v2.y + v1.z * v2.z;
}
__device__ float length(float3 v)
{
return sqrt(v.x * v.x + v.y * v.y + v.z * v.z);
}
__device__ float3 normalize(float3 v)
{
return v / length(v);
}
__device__ void swap(float3& v1, float3& v2)
{
float3 tmp = v1;
v1 = v2;
v2 = tmp;
}
__device__
int2 operator*(int2 v1, int2 v2)
{
return make_int2(v1.x * v2.x, v1.y * v2.y);
}
__device__
int3 operator+(int3 v1, int3 v2)
{
return make_int3(v1.x + v2.x, v1.y + v2.y, v1.z + v2.z);
}
__device__
int3 operator-(int3 v1, int3 v2)
{
return make_int3(v1.x - v2.x, v1.y - v2.y, v1.z - v2.z);
}
__device__
int3 operator*(int3 v1, int3 v2)
{
return make_int3(v1.x * v2.x, v1.y * v2.y, v1.z * v2.z);
}
__device__
int3 operator*(int3 v, int i)
{
return make_int3(v.x * i, v.y * i, v.z * i);
}
__device__
void operator-=(int3& v, int i)
{
v.x -= i;
v.y -= i;
v.z -= i;
}
__device__ int& get(int3& v, int index)
{
return *((int*)&v + index);
}
__device__ void set(int3& v, int index, int value)
{
int* ptr = ((int*)&v + index);
*ptr = value;
}
__device__
int2 toInt2(int3 v, int axis1, int axis2)
{
return make_int2(get(v, axis1), get(v, axis2));
}
__device__
int min(int3 v)
{
return min(v.x, min(v.y, v.z));
}
__device__
int sign(int i)
{
return i < 0 ? -1 : (i > 0 ? 1 : 0);
}
__device__
int3 sign(int3 v)
{
return make_int3(sign(v.x), sign(v.y), sign(v.z));
}
__device__
int3 abs(int3 v)
{
return make_int3(abs(v.x), abs(v.y), abs(v.z));
}
__device__
int dot(int2 v1, int2 v2)
{
return v1.x * v2.x + v1.y * v2.y;
}
__device__
int3 cross(int3 v1, int3 v2)
{
return make_int3(
v1.y * v2.z - v1.z * v2.y,
v1.z * v2.x - v1.x * v2.z,
v1.x * v2.y - v1.y * v2.x);
}
__device__ int max(int3 v)
{
return max(v.x, max(v.y, v.z));
}
__device__
int sum(int2 v)
{
return v.x + v.y;
}
__device__
void swap(int3& v1, int3& v2)
{
int3 tmp = v1;
v1 = v2;
v2 = tmp;
}
__device__ float2 operator+(float2 v1, float2 v2)
{
return make_float2(v1.x + v2.x, v1.y + v2.y);
}
__device__ float2 operator-(float2 v1, float2 v2)
{
return make_float2(v1.x - v2.x, v1.y - v2.y);
}
__device__ float2 operator*(float2 v, float f)
{
return make_float2(v.x * f, v.y * f);
}
__device__ float2 operator/(float2 v, float f)
{
return make_float2(v.x / f, v.y / f);
}
__device__ float& get(float2& v, int index)
{
float* ptr = (float*)&v;
return *(ptr + index);
}
__device__ float length(float2 v)
{
return sqrt(v.x * v.x + v.y * v.y);
}
__device__ float2 toFloat2(float3 v, int axis1, int axis2)
{
return make_float2(get(v, axis1), get(v, axis2));
}
__device__ float2 normalize(float2 v)
{
return v / length(v);
}
__device__ float dot(float2 v1, float2 v2)
{
return v1.x * v2.x + v1.y * v2.y;
} | .file "tmpxft_0014dbcf_00000000-6_VectorMath.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Zpl6float3S_
.type _Zpl6float3S_, @function
_Zpl6float3S_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Zpl6float3S_, .-_Zpl6float3S_
.globl _Zpl6float3f
.type _Zpl6float3f, @function
_Zpl6float3f:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Zpl6float3f, .-_Zpl6float3f
.globl _Zmi6float3S_
.type _Zmi6float3S_, @function
_Zmi6float3S_:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Zmi6float3S_, .-_Zmi6float3S_
.globl _Zml6float3S_
.type _Zml6float3S_, @function
_Zml6float3S_:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Zml6float3S_, .-_Zml6float3S_
.globl _Zml6float3f
.type _Zml6float3f, @function
_Zml6float3f:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Zml6float3f, .-_Zml6float3f
.globl _Zng6float3
.type _Zng6float3, @function
_Zng6float3:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Zng6float3, .-_Zng6float3
.globl _Zdv6float3S_
.type _Zdv6float3S_, @function
_Zdv6float3S_:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Zdv6float3S_, .-_Zdv6float3S_
.globl _Zdv6float3f
.type _Zdv6float3f, @function
_Zdv6float3f:
.LFB2035:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2035:
.size _Zdv6float3f, .-_Zdv6float3f
.globl _Zdvf6float3
.type _Zdvf6float3, @function
_Zdvf6float3:
.LFB2036:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm1, (%rsp)
movss %xmm2, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2036:
.size _Zdvf6float3, .-_Zdvf6float3
.globl _Zne6float3S_
.type _Zne6float3S_, @function
_Zne6float3S_:
.LFB2037:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2037:
.size _Zne6float3S_, .-_Zne6float3S_
.globl _Zne4int3S_
.type _Zne4int3S_, @function
_Zne4int3S_:
.LFB2038:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2038:
.size _Zne4int3S_, .-_Zne4int3S_
.globl _Zeq6float3S_
.type _Zeq6float3S_, @function
_Zeq6float3S_:
.LFB2039:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2039:
.size _Zeq6float3S_, .-_Zeq6float3S_
.globl _Zeq4int3S_
.type _Zeq4int3S_, @function
_Zeq4int3S_:
.LFB2040:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2040:
.size _Zeq4int3S_, .-_Zeq4int3S_
.globl _ZmIR6float3f
.type _ZmIR6float3f, @function
_ZmIR6float3f:
.LFB2041:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2041:
.size _ZmIR6float3f, .-_ZmIR6float3f
.globl _ZmlR4Mat46float3
.type _ZmlR4Mat46float3, @function
_ZmlR4Mat46float3:
.LFB2042:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2042:
.size _ZmlR4Mat46float3, .-_ZmlR4Mat46float3
.globl _Z3get6float3i
.type _Z3get6float3i, @function
_Z3get6float3i:
.LFB2043:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2043:
.size _Z3get6float3i, .-_Z3get6float3i
.globl _Z3setR6float3if
.type _Z3setR6float3if, @function
_Z3setR6float3if:
.LFB2044:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2044:
.size _Z3setR6float3if, .-_Z3setR6float3if
.globl _Z4signf
.type _Z4signf, @function
_Z4signf:
.LFB2045:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2045:
.size _Z4signf, .-_Z4signf
.globl _Z4sign6float3
.type _Z4sign6float3, @function
_Z4sign6float3:
.LFB2046:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2046:
.size _Z4sign6float3, .-_Z4sign6float3
.globl _Z3min6float3
.type _Z3min6float3, @function
_Z3min6float3:
.LFB2047:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2047:
.size _Z3min6float3, .-_Z3min6float3
.globl _Z3max6float3
.type _Z3max6float3, @function
_Z3max6float3:
.LFB2048:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2048:
.size _Z3max6float3, .-_Z3max6float3
.globl _Z3abs6float3
.type _Z3abs6float3, @function
_Z3abs6float3:
.LFB2049:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2049:
.size _Z3abs6float3, .-_Z3abs6float3
.globl _Z6toInt36float3
.type _Z6toInt36float3, @function
_Z6toInt36float3:
.LFB2050:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2050:
.size _Z6toInt36float3, .-_Z6toInt36float3
.globl _Z8toFloat34int3
.type _Z8toFloat34int3, @function
_Z8toFloat34int3:
.LFB2051:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2051:
.size _Z8toFloat34int3, .-_Z8toFloat34int3
.globl _Z5cross6float3S_
.type _Z5cross6float3S_, @function
_Z5cross6float3S_:
.LFB2052:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2052:
.size _Z5cross6float3S_, .-_Z5cross6float3S_
.globl _Z3dot6float3S_
.type _Z3dot6float3S_, @function
_Z3dot6float3S_:
.LFB2053:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2053:
.size _Z3dot6float3S_, .-_Z3dot6float3S_
.globl _Z6length6float3
.type _Z6length6float3, @function
_Z6length6float3:
.LFB2054:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2054:
.size _Z6length6float3, .-_Z6length6float3
.globl _Z9normalize6float3
.type _Z9normalize6float3, @function
_Z9normalize6float3:
.LFB2055:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2055:
.size _Z9normalize6float3, .-_Z9normalize6float3
.globl _Z4swapR6float3S0_
.type _Z4swapR6float3S0_, @function
_Z4swapR6float3S0_:
.LFB2056:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2056:
.size _Z4swapR6float3S0_, .-_Z4swapR6float3S0_
.globl _Zml4int2S_
.type _Zml4int2S_, @function
_Zml4int2S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Zml4int2S_, .-_Zml4int2S_
.globl _Zpl4int3S_
.type _Zpl4int3S_, @function
_Zpl4int3S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Zpl4int3S_, .-_Zpl4int3S_
.globl _Zmi4int3S_
.type _Zmi4int3S_, @function
_Zmi4int3S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Zmi4int3S_, .-_Zmi4int3S_
.globl _Zml4int3S_
.type _Zml4int3S_, @function
_Zml4int3S_:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Zml4int3S_, .-_Zml4int3S_
.globl _Zml4int3i
.type _Zml4int3i, @function
_Zml4int3i:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Zml4int3i, .-_Zml4int3i
.globl _ZmIR4int3i
.type _ZmIR4int3i, @function
_ZmIR4int3i:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _ZmIR4int3i, .-_ZmIR4int3i
.globl _Z3getR4int3i
.type _Z3getR4int3i, @function
_Z3getR4int3i:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z3getR4int3i, .-_Z3getR4int3i
.globl _Z3setR4int3ii
.type _Z3setR4int3ii, @function
_Z3setR4int3ii:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z3setR4int3ii, .-_Z3setR4int3ii
.globl _Z6toInt24int3ii
.type _Z6toInt24int3ii, @function
_Z6toInt24int3ii:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z6toInt24int3ii, .-_Z6toInt24int3ii
.globl _Z3min4int3
.type _Z3min4int3, @function
_Z3min4int3:
.LFB2066:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size _Z3min4int3, .-_Z3min4int3
.globl _Z4signi
.type _Z4signi, @function
_Z4signi:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z4signi, .-_Z4signi
.globl _Z4sign4int3
.type _Z4sign4int3, @function
_Z4sign4int3:
.LFB2068:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2068:
.size _Z4sign4int3, .-_Z4sign4int3
.globl _Z3abs4int3
.type _Z3abs4int3, @function
_Z3abs4int3:
.LFB2069:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2069:
.size _Z3abs4int3, .-_Z3abs4int3
.globl _Z3dot4int2S_
.type _Z3dot4int2S_, @function
_Z3dot4int2S_:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z3dot4int2S_, .-_Z3dot4int2S_
.globl _Z5cross4int3S_
.type _Z5cross4int3S_, @function
_Z5cross4int3S_:
.LFB2071:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size _Z5cross4int3S_, .-_Z5cross4int3S_
.globl _Z3max4int3
.type _Z3max4int3, @function
_Z3max4int3:
.LFB2072:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2072:
.size _Z3max4int3, .-_Z3max4int3
.globl _Z3sum4int2
.type _Z3sum4int2, @function
_Z3sum4int2:
.LFB2073:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2073:
.size _Z3sum4int2, .-_Z3sum4int2
.globl _Z4swapR4int3S0_
.type _Z4swapR4int3S0_, @function
_Z4swapR4int3S0_:
.LFB2074:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2074:
.size _Z4swapR4int3S0_, .-_Z4swapR4int3S0_
.globl _Zpl6float2S_
.type _Zpl6float2S_, @function
_Zpl6float2S_:
.LFB2075:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2075:
.size _Zpl6float2S_, .-_Zpl6float2S_
.globl _Zmi6float2S_
.type _Zmi6float2S_, @function
_Zmi6float2S_:
.LFB2076:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2076:
.size _Zmi6float2S_, .-_Zmi6float2S_
.globl _Zml6float2f
.type _Zml6float2f, @function
_Zml6float2f:
.LFB2077:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2077:
.size _Zml6float2f, .-_Zml6float2f
.globl _Zdv6float2f
.type _Zdv6float2f, @function
_Zdv6float2f:
.LFB2078:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2078:
.size _Zdv6float2f, .-_Zdv6float2f
.globl _Z3getR6float2i
.type _Z3getR6float2i, @function
_Z3getR6float2i:
.LFB2079:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2079:
.size _Z3getR6float2i, .-_Z3getR6float2i
.globl _Z6length6float2
.type _Z6length6float2, @function
_Z6length6float2:
.LFB2080:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2080:
.size _Z6length6float2, .-_Z6length6float2
.globl _Z8toFloat26float3ii
.type _Z8toFloat26float3ii, @function
_Z8toFloat26float3ii:
.LFB2081:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2081:
.size _Z8toFloat26float3ii, .-_Z8toFloat26float3ii
.globl _Z9normalize6float2
.type _Z9normalize6float2, @function
_Z9normalize6float2:
.LFB2082:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2082:
.size _Z9normalize6float2, .-_Z9normalize6float2
.globl _Z3dot6float2S_
.type _Z3dot6float2S_, @function
_Z3dot6float2S_:
.LFB2083:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2083:
.size _Z3dot6float2S_, .-_Z3dot6float2S_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2109:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #pragma once
struct Mat4
{
float elements[16];
__device__ float operator[](int i)
{
return elements[i];
}
};
__device__ float3 operator+(float3 v1, float3 v2)
{
return make_float3(v1.x + v2.x, v1.y + v2.y, v1.z + v2.z);
}
__device__ float3 operator+(float3 v, float f)
{
return make_float3(v.x + f, v.y + f, v.z + f);
}
__device__ float3 operator-(float3 v1, float3 v2)
{
return make_float3(v1.x - v2.x, v1.y - v2.y, v1.z - v2.z);
}
__device__ float3 operator*(float3 v1, float3 v2)
{
return make_float3(v1.x * v2.x, v1.y * v2.y, v1.z * v2.z);
}
__device__ float3 operator*(float3 v, float f)
{
return make_float3(v.x * f, v.y * f, v.z * f);
}
__device__ float3 operator-(float3 v)
{
return make_float3(-v.x, -v.y, -v.z);
}
__device__ float3 operator/(float3 v1, float3 v2)
{
return make_float3(v1.x / v2.x, v1.y / v2.y, v1.z / v2.z);
}
__device__ float3 operator/(float3 v, float f)
{
return make_float3(v.x / f, v.y / f, v.z / f);
}
__device__ float3 operator/(float f, float3 v)
{
return make_float3(f / v.x, f / v.y, f / v.z);
}
__device__ bool operator!=(float3 v1, float3 v2)
{
return v1.x != v2.x || v1.y != v2.y || v1.z != v2.z;
}
__device__ bool operator!=(int3 v1, int3 v2)
{
return v1.x != v2.x || v1.y != v2.y || v1.z != v2.z;
}
__device__ bool operator==(float3 v1, float3 v2)
{
return v1.x == v2.x && v1.y == v2.y && v1.z == v2.z;
}
__device__ bool operator==(int3 v1, int3 v2)
{
return v1.x == v2.x && v1.y == v2.y && v1.z == v2.z;
}
__device__ void operator-=(float3& v, float f)
{
v.x -= f;
v.y -= f;
v.z -= f;
}
__device__ float3 operator*(Mat4& m, float3 v)
{
float x = m[0] * v.x + m[4] * v.y + m[8] * v.z + m[12];
float y = m[1] * v.x + m[5] * v.y + m[9] * v.z + m[13];
float z = m[2] * v.x + m[6] * v.y + m[10] * v.z + m[14];
float w = m[3] * v.x + m[7] * v.y + m[11] * v.z + m[15];
return make_float3(x, y, z);
}
__device__ float get(float3 v, int index)
{
float* ptr = (float*)&v;
return *(ptr + index);
}
__device__ void set(float3& v, int index, float value)
{
float* ptr = (float*)&v;
*(ptr + index) = value;
}
__device__ float sign(float f)
{
return f < 0.0f ? -1.0f : (f > 0.0f ? 1.0f : 0.0f);
}
__device__ float3 sign(float3 v)
{
return make_float3(sign(v.x), sign(v.y), sign(v.z));
}
__device__ float min(float3 v)
{
return min(v.x, min(v.y, v.z));
}
__device__ float max(float3 v)
{
return max(v.x, max(v.y, v.z));
}
__device__ float3 abs(float3 v)
{
return make_float3(abs(v.x), abs(v.y), abs(v.z));
}
__device__ int3 toInt3(float3 v)
{
return make_int3(floor(v.x), floor(v.y), floor(v.z));
}
__device__ float3 toFloat3(int3 v)
{
return make_float3(float(v.x), float(v.y), float(v.z));
}
__device__ float3 cross(float3 v1, float3 v2)
{
return make_float3(
v1.y * v2.z - v1.z * v2.y,
v1.z * v2.x - v1.x * v2.z,
v1.x * v2.y - v1.y * v2.x);
}
__device__ float dot(float3 v1, float3 v2)
{
return v1.x * v2.x + v1.y * v2.y + v1.z * v2.z;
}
__device__ float length(float3 v)
{
return sqrt(v.x * v.x + v.y * v.y + v.z * v.z);
}
__device__ float3 normalize(float3 v)
{
return v / length(v);
}
__device__ void swap(float3& v1, float3& v2)
{
float3 tmp = v1;
v1 = v2;
v2 = tmp;
}
__device__
int2 operator*(int2 v1, int2 v2)
{
return make_int2(v1.x * v2.x, v1.y * v2.y);
}
__device__
int3 operator+(int3 v1, int3 v2)
{
return make_int3(v1.x + v2.x, v1.y + v2.y, v1.z + v2.z);
}
__device__
int3 operator-(int3 v1, int3 v2)
{
return make_int3(v1.x - v2.x, v1.y - v2.y, v1.z - v2.z);
}
__device__
int3 operator*(int3 v1, int3 v2)
{
return make_int3(v1.x * v2.x, v1.y * v2.y, v1.z * v2.z);
}
__device__
int3 operator*(int3 v, int i)
{
return make_int3(v.x * i, v.y * i, v.z * i);
}
__device__
void operator-=(int3& v, int i)
{
v.x -= i;
v.y -= i;
v.z -= i;
}
__device__ int& get(int3& v, int index)
{
return *((int*)&v + index);
}
__device__ void set(int3& v, int index, int value)
{
int* ptr = ((int*)&v + index);
*ptr = value;
}
__device__
int2 toInt2(int3 v, int axis1, int axis2)
{
return make_int2(get(v, axis1), get(v, axis2));
}
__device__
int min(int3 v)
{
return min(v.x, min(v.y, v.z));
}
__device__
int sign(int i)
{
return i < 0 ? -1 : (i > 0 ? 1 : 0);
}
__device__
int3 sign(int3 v)
{
return make_int3(sign(v.x), sign(v.y), sign(v.z));
}
__device__
int3 abs(int3 v)
{
return make_int3(abs(v.x), abs(v.y), abs(v.z));
}
__device__
int dot(int2 v1, int2 v2)
{
return v1.x * v2.x + v1.y * v2.y;
}
__device__
int3 cross(int3 v1, int3 v2)
{
return make_int3(
v1.y * v2.z - v1.z * v2.y,
v1.z * v2.x - v1.x * v2.z,
v1.x * v2.y - v1.y * v2.x);
}
__device__ int max(int3 v)
{
return max(v.x, max(v.y, v.z));
}
__device__
int sum(int2 v)
{
return v.x + v.y;
}
__device__
void swap(int3& v1, int3& v2)
{
int3 tmp = v1;
v1 = v2;
v2 = tmp;
}
__device__ float2 operator+(float2 v1, float2 v2)
{
return make_float2(v1.x + v2.x, v1.y + v2.y);
}
__device__ float2 operator-(float2 v1, float2 v2)
{
return make_float2(v1.x - v2.x, v1.y - v2.y);
}
__device__ float2 operator*(float2 v, float f)
{
return make_float2(v.x * f, v.y * f);
}
__device__ float2 operator/(float2 v, float f)
{
return make_float2(v.x / f, v.y / f);
}
__device__ float& get(float2& v, int index)
{
float* ptr = (float*)&v;
return *(ptr + index);
}
__device__ float length(float2 v)
{
return sqrt(v.x * v.x + v.y * v.y);
}
__device__ float2 toFloat2(float3 v, int axis1, int axis2)
{
return make_float2(get(v, axis1), get(v, axis2));
}
__device__ float2 normalize(float2 v)
{
return v / length(v);
}
__device__ float dot(float2 v1, float2 v2)
{
return v1.x * v2.x + v1.y * v2.y;
} | #pragma once
#include <hip/hip_runtime.h>
struct Mat4
{
float elements[16];
__device__ float operator[](int i)
{
return elements[i];
}
};
__device__ float3 operator+(float3 v1, float3 v2)
{
return make_float3(v1.x + v2.x, v1.y + v2.y, v1.z + v2.z);
}
__device__ float3 operator+(float3 v, float f)
{
return make_float3(v.x + f, v.y + f, v.z + f);
}
__device__ float3 operator-(float3 v1, float3 v2)
{
return make_float3(v1.x - v2.x, v1.y - v2.y, v1.z - v2.z);
}
__device__ float3 operator*(float3 v1, float3 v2)
{
return make_float3(v1.x * v2.x, v1.y * v2.y, v1.z * v2.z);
}
__device__ float3 operator*(float3 v, float f)
{
return make_float3(v.x * f, v.y * f, v.z * f);
}
__device__ float3 operator-(float3 v)
{
return make_float3(-v.x, -v.y, -v.z);
}
__device__ float3 operator/(float3 v1, float3 v2)
{
return make_float3(v1.x / v2.x, v1.y / v2.y, v1.z / v2.z);
}
__device__ float3 operator/(float3 v, float f)
{
return make_float3(v.x / f, v.y / f, v.z / f);
}
__device__ float3 operator/(float f, float3 v)
{
return make_float3(f / v.x, f / v.y, f / v.z);
}
__device__ bool operator!=(float3 v1, float3 v2)
{
return v1.x != v2.x || v1.y != v2.y || v1.z != v2.z;
}
__device__ bool operator!=(int3 v1, int3 v2)
{
return v1.x != v2.x || v1.y != v2.y || v1.z != v2.z;
}
__device__ bool operator==(float3 v1, float3 v2)
{
return v1.x == v2.x && v1.y == v2.y && v1.z == v2.z;
}
__device__ bool operator==(int3 v1, int3 v2)
{
return v1.x == v2.x && v1.y == v2.y && v1.z == v2.z;
}
__device__ void operator-=(float3& v, float f)
{
v.x -= f;
v.y -= f;
v.z -= f;
}
__device__ float3 operator*(Mat4& m, float3 v)
{
float x = m[0] * v.x + m[4] * v.y + m[8] * v.z + m[12];
float y = m[1] * v.x + m[5] * v.y + m[9] * v.z + m[13];
float z = m[2] * v.x + m[6] * v.y + m[10] * v.z + m[14];
float w = m[3] * v.x + m[7] * v.y + m[11] * v.z + m[15];
return make_float3(x, y, z);
}
__device__ float get(float3 v, int index)
{
float* ptr = (float*)&v;
return *(ptr + index);
}
__device__ void set(float3& v, int index, float value)
{
float* ptr = (float*)&v;
*(ptr + index) = value;
}
__device__ float sign(float f)
{
return f < 0.0f ? -1.0f : (f > 0.0f ? 1.0f : 0.0f);
}
__device__ float3 sign(float3 v)
{
return make_float3(sign(v.x), sign(v.y), sign(v.z));
}
__device__ float min(float3 v)
{
return min(v.x, min(v.y, v.z));
}
__device__ float max(float3 v)
{
return max(v.x, max(v.y, v.z));
}
__device__ float3 abs(float3 v)
{
return make_float3(abs(v.x), abs(v.y), abs(v.z));
}
__device__ int3 toInt3(float3 v)
{
return make_int3(floor(v.x), floor(v.y), floor(v.z));
}
__device__ float3 toFloat3(int3 v)
{
return make_float3(float(v.x), float(v.y), float(v.z));
}
__device__ float3 cross(float3 v1, float3 v2)
{
return make_float3(
v1.y * v2.z - v1.z * v2.y,
v1.z * v2.x - v1.x * v2.z,
v1.x * v2.y - v1.y * v2.x);
}
__device__ float dot(float3 v1, float3 v2)
{
return v1.x * v2.x + v1.y * v2.y + v1.z * v2.z;
}
__device__ float length(float3 v)
{
return sqrt(v.x * v.x + v.y * v.y + v.z * v.z);
}
__device__ float3 normalize(float3 v)
{
return v / length(v);
}
__device__ void swap(float3& v1, float3& v2)
{
float3 tmp = v1;
v1 = v2;
v2 = tmp;
}
__device__
int2 operator*(int2 v1, int2 v2)
{
return make_int2(v1.x * v2.x, v1.y * v2.y);
}
__device__
int3 operator+(int3 v1, int3 v2)
{
return make_int3(v1.x + v2.x, v1.y + v2.y, v1.z + v2.z);
}
__device__
int3 operator-(int3 v1, int3 v2)
{
return make_int3(v1.x - v2.x, v1.y - v2.y, v1.z - v2.z);
}
__device__
int3 operator*(int3 v1, int3 v2)
{
return make_int3(v1.x * v2.x, v1.y * v2.y, v1.z * v2.z);
}
__device__
int3 operator*(int3 v, int i)
{
return make_int3(v.x * i, v.y * i, v.z * i);
}
__device__
void operator-=(int3& v, int i)
{
v.x -= i;
v.y -= i;
v.z -= i;
}
__device__ int& get(int3& v, int index)
{
return *((int*)&v + index);
}
__device__ void set(int3& v, int index, int value)
{
int* ptr = ((int*)&v + index);
*ptr = value;
}
__device__
int2 toInt2(int3 v, int axis1, int axis2)
{
return make_int2(get(v, axis1), get(v, axis2));
}
__device__
int min(int3 v)
{
return min(v.x, min(v.y, v.z));
}
__device__
int sign(int i)
{
return i < 0 ? -1 : (i > 0 ? 1 : 0);
}
__device__
int3 sign(int3 v)
{
return make_int3(sign(v.x), sign(v.y), sign(v.z));
}
__device__
int3 abs(int3 v)
{
return make_int3(abs(v.x), abs(v.y), abs(v.z));
}
__device__
int dot(int2 v1, int2 v2)
{
return v1.x * v2.x + v1.y * v2.y;
}
__device__
int3 cross(int3 v1, int3 v2)
{
return make_int3(
v1.y * v2.z - v1.z * v2.y,
v1.z * v2.x - v1.x * v2.z,
v1.x * v2.y - v1.y * v2.x);
}
__device__ int max(int3 v)
{
return max(v.x, max(v.y, v.z));
}
__device__
int sum(int2 v)
{
return v.x + v.y;
}
__device__
void swap(int3& v1, int3& v2)
{
int3 tmp = v1;
v1 = v2;
v2 = tmp;
}
__device__ float2 operator+(float2 v1, float2 v2)
{
return make_float2(v1.x + v2.x, v1.y + v2.y);
}
__device__ float2 operator-(float2 v1, float2 v2)
{
return make_float2(v1.x - v2.x, v1.y - v2.y);
}
__device__ float2 operator*(float2 v, float f)
{
return make_float2(v.x * f, v.y * f);
}
__device__ float2 operator/(float2 v, float f)
{
return make_float2(v.x / f, v.y / f);
}
__device__ float& get(float2& v, int index)
{
float* ptr = (float*)&v;
return *(ptr + index);
}
__device__ float length(float2 v)
{
return sqrt(v.x * v.x + v.y * v.y);
}
__device__ float2 toFloat2(float3 v, int axis1, int axis2)
{
return make_float2(get(v, axis1), get(v, axis2));
}
__device__ float2 normalize(float2 v)
{
return v / length(v);
}
__device__ float dot(float2 v1, float2 v2)
{
return v1.x * v2.x + v1.y * v2.y;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
struct Mat4
{
float elements[16];
__device__ float operator[](int i)
{
return elements[i];
}
};
__device__ float3 operator+(float3 v1, float3 v2)
{
return make_float3(v1.x + v2.x, v1.y + v2.y, v1.z + v2.z);
}
__device__ float3 operator+(float3 v, float f)
{
return make_float3(v.x + f, v.y + f, v.z + f);
}
__device__ float3 operator-(float3 v1, float3 v2)
{
return make_float3(v1.x - v2.x, v1.y - v2.y, v1.z - v2.z);
}
__device__ float3 operator*(float3 v1, float3 v2)
{
return make_float3(v1.x * v2.x, v1.y * v2.y, v1.z * v2.z);
}
__device__ float3 operator*(float3 v, float f)
{
return make_float3(v.x * f, v.y * f, v.z * f);
}
__device__ float3 operator-(float3 v)
{
return make_float3(-v.x, -v.y, -v.z);
}
__device__ float3 operator/(float3 v1, float3 v2)
{
return make_float3(v1.x / v2.x, v1.y / v2.y, v1.z / v2.z);
}
__device__ float3 operator/(float3 v, float f)
{
return make_float3(v.x / f, v.y / f, v.z / f);
}
__device__ float3 operator/(float f, float3 v)
{
return make_float3(f / v.x, f / v.y, f / v.z);
}
__device__ bool operator!=(float3 v1, float3 v2)
{
return v1.x != v2.x || v1.y != v2.y || v1.z != v2.z;
}
__device__ bool operator!=(int3 v1, int3 v2)
{
return v1.x != v2.x || v1.y != v2.y || v1.z != v2.z;
}
__device__ bool operator==(float3 v1, float3 v2)
{
return v1.x == v2.x && v1.y == v2.y && v1.z == v2.z;
}
__device__ bool operator==(int3 v1, int3 v2)
{
return v1.x == v2.x && v1.y == v2.y && v1.z == v2.z;
}
__device__ void operator-=(float3& v, float f)
{
v.x -= f;
v.y -= f;
v.z -= f;
}
__device__ float3 operator*(Mat4& m, float3 v)
{
float x = m[0] * v.x + m[4] * v.y + m[8] * v.z + m[12];
float y = m[1] * v.x + m[5] * v.y + m[9] * v.z + m[13];
float z = m[2] * v.x + m[6] * v.y + m[10] * v.z + m[14];
float w = m[3] * v.x + m[7] * v.y + m[11] * v.z + m[15];
return make_float3(x, y, z);
}
__device__ float get(float3 v, int index)
{
float* ptr = (float*)&v;
return *(ptr + index);
}
__device__ void set(float3& v, int index, float value)
{
float* ptr = (float*)&v;
*(ptr + index) = value;
}
__device__ float sign(float f)
{
return f < 0.0f ? -1.0f : (f > 0.0f ? 1.0f : 0.0f);
}
__device__ float3 sign(float3 v)
{
return make_float3(sign(v.x), sign(v.y), sign(v.z));
}
__device__ float min(float3 v)
{
return min(v.x, min(v.y, v.z));
}
__device__ float max(float3 v)
{
return max(v.x, max(v.y, v.z));
}
__device__ float3 abs(float3 v)
{
return make_float3(abs(v.x), abs(v.y), abs(v.z));
}
__device__ int3 toInt3(float3 v)
{
return make_int3(floor(v.x), floor(v.y), floor(v.z));
}
__device__ float3 toFloat3(int3 v)
{
return make_float3(float(v.x), float(v.y), float(v.z));
}
__device__ float3 cross(float3 v1, float3 v2)
{
return make_float3(
v1.y * v2.z - v1.z * v2.y,
v1.z * v2.x - v1.x * v2.z,
v1.x * v2.y - v1.y * v2.x);
}
__device__ float dot(float3 v1, float3 v2)
{
return v1.x * v2.x + v1.y * v2.y + v1.z * v2.z;
}
__device__ float length(float3 v)
{
return sqrt(v.x * v.x + v.y * v.y + v.z * v.z);
}
__device__ float3 normalize(float3 v)
{
return v / length(v);
}
__device__ void swap(float3& v1, float3& v2)
{
float3 tmp = v1;
v1 = v2;
v2 = tmp;
}
__device__
int2 operator*(int2 v1, int2 v2)
{
return make_int2(v1.x * v2.x, v1.y * v2.y);
}
__device__
int3 operator+(int3 v1, int3 v2)
{
return make_int3(v1.x + v2.x, v1.y + v2.y, v1.z + v2.z);
}
__device__
int3 operator-(int3 v1, int3 v2)
{
return make_int3(v1.x - v2.x, v1.y - v2.y, v1.z - v2.z);
}
__device__
int3 operator*(int3 v1, int3 v2)
{
return make_int3(v1.x * v2.x, v1.y * v2.y, v1.z * v2.z);
}
__device__
int3 operator*(int3 v, int i)
{
return make_int3(v.x * i, v.y * i, v.z * i);
}
__device__
void operator-=(int3& v, int i)
{
v.x -= i;
v.y -= i;
v.z -= i;
}
__device__ int& get(int3& v, int index)
{
return *((int*)&v + index);
}
__device__ void set(int3& v, int index, int value)
{
int* ptr = ((int*)&v + index);
*ptr = value;
}
__device__
int2 toInt2(int3 v, int axis1, int axis2)
{
return make_int2(get(v, axis1), get(v, axis2));
}
__device__
int min(int3 v)
{
return min(v.x, min(v.y, v.z));
}
__device__
int sign(int i)
{
return i < 0 ? -1 : (i > 0 ? 1 : 0);
}
__device__
int3 sign(int3 v)
{
return make_int3(sign(v.x), sign(v.y), sign(v.z));
}
__device__
int3 abs(int3 v)
{
return make_int3(abs(v.x), abs(v.y), abs(v.z));
}
__device__
int dot(int2 v1, int2 v2)
{
return v1.x * v2.x + v1.y * v2.y;
}
__device__
int3 cross(int3 v1, int3 v2)
{
return make_int3(
v1.y * v2.z - v1.z * v2.y,
v1.z * v2.x - v1.x * v2.z,
v1.x * v2.y - v1.y * v2.x);
}
__device__ int max(int3 v)
{
return max(v.x, max(v.y, v.z));
}
__device__
int sum(int2 v)
{
return v.x + v.y;
}
__device__
void swap(int3& v1, int3& v2)
{
int3 tmp = v1;
v1 = v2;
v2 = tmp;
}
__device__ float2 operator+(float2 v1, float2 v2)
{
return make_float2(v1.x + v2.x, v1.y + v2.y);
}
__device__ float2 operator-(float2 v1, float2 v2)
{
return make_float2(v1.x - v2.x, v1.y - v2.y);
}
__device__ float2 operator*(float2 v, float f)
{
return make_float2(v.x * f, v.y * f);
}
__device__ float2 operator/(float2 v, float f)
{
return make_float2(v.x / f, v.y / f);
}
__device__ float& get(float2& v, int index)
{
float* ptr = (float*)&v;
return *(ptr + index);
}
__device__ float length(float2 v)
{
return sqrt(v.x * v.x + v.y * v.y);
}
__device__ float2 toFloat2(float3 v, int axis1, int axis2)
{
return make_float2(get(v, axis1), get(v, axis2));
}
__device__ float2 normalize(float2 v)
{
return v / length(v);
}
__device__ float dot(float2 v1, float2 v2)
{
return v1.x * v2.x + v1.y * v2.y;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
struct Mat4
{
float elements[16];
__device__ float operator[](int i)
{
return elements[i];
}
};
__device__ float3 operator+(float3 v1, float3 v2)
{
return make_float3(v1.x + v2.x, v1.y + v2.y, v1.z + v2.z);
}
__device__ float3 operator+(float3 v, float f)
{
return make_float3(v.x + f, v.y + f, v.z + f);
}
__device__ float3 operator-(float3 v1, float3 v2)
{
return make_float3(v1.x - v2.x, v1.y - v2.y, v1.z - v2.z);
}
__device__ float3 operator*(float3 v1, float3 v2)
{
return make_float3(v1.x * v2.x, v1.y * v2.y, v1.z * v2.z);
}
__device__ float3 operator*(float3 v, float f)
{
return make_float3(v.x * f, v.y * f, v.z * f);
}
__device__ float3 operator-(float3 v)
{
return make_float3(-v.x, -v.y, -v.z);
}
__device__ float3 operator/(float3 v1, float3 v2)
{
return make_float3(v1.x / v2.x, v1.y / v2.y, v1.z / v2.z);
}
__device__ float3 operator/(float3 v, float f)
{
return make_float3(v.x / f, v.y / f, v.z / f);
}
__device__ float3 operator/(float f, float3 v)
{
return make_float3(f / v.x, f / v.y, f / v.z);
}
__device__ bool operator!=(float3 v1, float3 v2)
{
return v1.x != v2.x || v1.y != v2.y || v1.z != v2.z;
}
__device__ bool operator!=(int3 v1, int3 v2)
{
return v1.x != v2.x || v1.y != v2.y || v1.z != v2.z;
}
__device__ bool operator==(float3 v1, float3 v2)
{
return v1.x == v2.x && v1.y == v2.y && v1.z == v2.z;
}
__device__ bool operator==(int3 v1, int3 v2)
{
return v1.x == v2.x && v1.y == v2.y && v1.z == v2.z;
}
__device__ void operator-=(float3& v, float f)
{
v.x -= f;
v.y -= f;
v.z -= f;
}
__device__ float3 operator*(Mat4& m, float3 v)
{
float x = m[0] * v.x + m[4] * v.y + m[8] * v.z + m[12];
float y = m[1] * v.x + m[5] * v.y + m[9] * v.z + m[13];
float z = m[2] * v.x + m[6] * v.y + m[10] * v.z + m[14];
float w = m[3] * v.x + m[7] * v.y + m[11] * v.z + m[15];
return make_float3(x, y, z);
}
__device__ float get(float3 v, int index)
{
float* ptr = (float*)&v;
return *(ptr + index);
}
__device__ void set(float3& v, int index, float value)
{
float* ptr = (float*)&v;
*(ptr + index) = value;
}
__device__ float sign(float f)
{
return f < 0.0f ? -1.0f : (f > 0.0f ? 1.0f : 0.0f);
}
__device__ float3 sign(float3 v)
{
return make_float3(sign(v.x), sign(v.y), sign(v.z));
}
__device__ float min(float3 v)
{
return min(v.x, min(v.y, v.z));
}
__device__ float max(float3 v)
{
return max(v.x, max(v.y, v.z));
}
__device__ float3 abs(float3 v)
{
return make_float3(abs(v.x), abs(v.y), abs(v.z));
}
__device__ int3 toInt3(float3 v)
{
return make_int3(floor(v.x), floor(v.y), floor(v.z));
}
__device__ float3 toFloat3(int3 v)
{
return make_float3(float(v.x), float(v.y), float(v.z));
}
__device__ float3 cross(float3 v1, float3 v2)
{
return make_float3(
v1.y * v2.z - v1.z * v2.y,
v1.z * v2.x - v1.x * v2.z,
v1.x * v2.y - v1.y * v2.x);
}
__device__ float dot(float3 v1, float3 v2)
{
return v1.x * v2.x + v1.y * v2.y + v1.z * v2.z;
}
__device__ float length(float3 v)
{
return sqrt(v.x * v.x + v.y * v.y + v.z * v.z);
}
__device__ float3 normalize(float3 v)
{
return v / length(v);
}
__device__ void swap(float3& v1, float3& v2)
{
float3 tmp = v1;
v1 = v2;
v2 = tmp;
}
__device__
int2 operator*(int2 v1, int2 v2)
{
return make_int2(v1.x * v2.x, v1.y * v2.y);
}
__device__
int3 operator+(int3 v1, int3 v2)
{
return make_int3(v1.x + v2.x, v1.y + v2.y, v1.z + v2.z);
}
__device__
int3 operator-(int3 v1, int3 v2)
{
return make_int3(v1.x - v2.x, v1.y - v2.y, v1.z - v2.z);
}
__device__
int3 operator*(int3 v1, int3 v2)
{
return make_int3(v1.x * v2.x, v1.y * v2.y, v1.z * v2.z);
}
__device__
int3 operator*(int3 v, int i)
{
return make_int3(v.x * i, v.y * i, v.z * i);
}
__device__
void operator-=(int3& v, int i)
{
v.x -= i;
v.y -= i;
v.z -= i;
}
__device__ int& get(int3& v, int index)
{
return *((int*)&v + index);
}
__device__ void set(int3& v, int index, int value)
{
int* ptr = ((int*)&v + index);
*ptr = value;
}
__device__
int2 toInt2(int3 v, int axis1, int axis2)
{
return make_int2(get(v, axis1), get(v, axis2));
}
__device__
int min(int3 v)
{
return min(v.x, min(v.y, v.z));
}
__device__
int sign(int i)
{
return i < 0 ? -1 : (i > 0 ? 1 : 0);
}
__device__
int3 sign(int3 v)
{
return make_int3(sign(v.x), sign(v.y), sign(v.z));
}
__device__
int3 abs(int3 v)
{
return make_int3(abs(v.x), abs(v.y), abs(v.z));
}
__device__
int dot(int2 v1, int2 v2)
{
return v1.x * v2.x + v1.y * v2.y;
}
__device__
int3 cross(int3 v1, int3 v2)
{
return make_int3(
v1.y * v2.z - v1.z * v2.y,
v1.z * v2.x - v1.x * v2.z,
v1.x * v2.y - v1.y * v2.x);
}
__device__ int max(int3 v)
{
return max(v.x, max(v.y, v.z));
}
__device__
int sum(int2 v)
{
return v.x + v.y;
}
__device__
void swap(int3& v1, int3& v2)
{
int3 tmp = v1;
v1 = v2;
v2 = tmp;
}
__device__ float2 operator+(float2 v1, float2 v2)
{
return make_float2(v1.x + v2.x, v1.y + v2.y);
}
__device__ float2 operator-(float2 v1, float2 v2)
{
return make_float2(v1.x - v2.x, v1.y - v2.y);
}
__device__ float2 operator*(float2 v, float f)
{
return make_float2(v.x * f, v.y * f);
}
__device__ float2 operator/(float2 v, float f)
{
return make_float2(v.x / f, v.y / f);
}
__device__ float& get(float2& v, int index)
{
float* ptr = (float*)&v;
return *(ptr + index);
}
__device__ float length(float2 v)
{
return sqrt(v.x * v.x + v.y * v.y);
}
__device__ float2 toFloat2(float3 v, int axis1, int axis2)
{
return make_float2(get(v, axis1), get(v, axis2));
}
__device__ float2 normalize(float2 v)
{
return v / length(v);
}
__device__ float dot(float2 v1, float2 v2)
{
return v1.x * v2.x + v1.y * v2.y;
} | .text
.file "VectorMath.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014dbcf_00000000-6_VectorMath.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Zpl6float3S_
.type _Zpl6float3S_, @function
_Zpl6float3S_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Zpl6float3S_, .-_Zpl6float3S_
.globl _Zpl6float3f
.type _Zpl6float3f, @function
_Zpl6float3f:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Zpl6float3f, .-_Zpl6float3f
.globl _Zmi6float3S_
.type _Zmi6float3S_, @function
_Zmi6float3S_:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Zmi6float3S_, .-_Zmi6float3S_
.globl _Zml6float3S_
.type _Zml6float3S_, @function
_Zml6float3S_:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Zml6float3S_, .-_Zml6float3S_
.globl _Zml6float3f
.type _Zml6float3f, @function
_Zml6float3f:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Zml6float3f, .-_Zml6float3f
.globl _Zng6float3
.type _Zng6float3, @function
_Zng6float3:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Zng6float3, .-_Zng6float3
.globl _Zdv6float3S_
.type _Zdv6float3S_, @function
_Zdv6float3S_:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Zdv6float3S_, .-_Zdv6float3S_
.globl _Zdv6float3f
.type _Zdv6float3f, @function
_Zdv6float3f:
.LFB2035:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2035:
.size _Zdv6float3f, .-_Zdv6float3f
.globl _Zdvf6float3
.type _Zdvf6float3, @function
_Zdvf6float3:
.LFB2036:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm1, (%rsp)
movss %xmm2, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2036:
.size _Zdvf6float3, .-_Zdvf6float3
.globl _Zne6float3S_
.type _Zne6float3S_, @function
_Zne6float3S_:
.LFB2037:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2037:
.size _Zne6float3S_, .-_Zne6float3S_
.globl _Zne4int3S_
.type _Zne4int3S_, @function
_Zne4int3S_:
.LFB2038:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2038:
.size _Zne4int3S_, .-_Zne4int3S_
.globl _Zeq6float3S_
.type _Zeq6float3S_, @function
_Zeq6float3S_:
.LFB2039:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2039:
.size _Zeq6float3S_, .-_Zeq6float3S_
.globl _Zeq4int3S_
.type _Zeq4int3S_, @function
_Zeq4int3S_:
.LFB2040:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2040:
.size _Zeq4int3S_, .-_Zeq4int3S_
.globl _ZmIR6float3f
.type _ZmIR6float3f, @function
_ZmIR6float3f:
.LFB2041:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2041:
.size _ZmIR6float3f, .-_ZmIR6float3f
.globl _ZmlR4Mat46float3
.type _ZmlR4Mat46float3, @function
_ZmlR4Mat46float3:
.LFB2042:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2042:
.size _ZmlR4Mat46float3, .-_ZmlR4Mat46float3
.globl _Z3get6float3i
.type _Z3get6float3i, @function
_Z3get6float3i:
.LFB2043:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2043:
.size _Z3get6float3i, .-_Z3get6float3i
.globl _Z3setR6float3if
.type _Z3setR6float3if, @function
_Z3setR6float3if:
.LFB2044:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2044:
.size _Z3setR6float3if, .-_Z3setR6float3if
.globl _Z4signf
.type _Z4signf, @function
_Z4signf:
.LFB2045:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2045:
.size _Z4signf, .-_Z4signf
.globl _Z4sign6float3
.type _Z4sign6float3, @function
_Z4sign6float3:
.LFB2046:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2046:
.size _Z4sign6float3, .-_Z4sign6float3
.globl _Z3min6float3
.type _Z3min6float3, @function
_Z3min6float3:
.LFB2047:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2047:
.size _Z3min6float3, .-_Z3min6float3
.globl _Z3max6float3
.type _Z3max6float3, @function
_Z3max6float3:
.LFB2048:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2048:
.size _Z3max6float3, .-_Z3max6float3
.globl _Z3abs6float3
.type _Z3abs6float3, @function
_Z3abs6float3:
.LFB2049:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2049:
.size _Z3abs6float3, .-_Z3abs6float3
.globl _Z6toInt36float3
.type _Z6toInt36float3, @function
_Z6toInt36float3:
.LFB2050:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2050:
.size _Z6toInt36float3, .-_Z6toInt36float3
.globl _Z8toFloat34int3
.type _Z8toFloat34int3, @function
_Z8toFloat34int3:
.LFB2051:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2051:
.size _Z8toFloat34int3, .-_Z8toFloat34int3
.globl _Z5cross6float3S_
.type _Z5cross6float3S_, @function
_Z5cross6float3S_:
.LFB2052:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2052:
.size _Z5cross6float3S_, .-_Z5cross6float3S_
.globl _Z3dot6float3S_
.type _Z3dot6float3S_, @function
_Z3dot6float3S_:
.LFB2053:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %xmm0, 16(%rsp)
movss %xmm1, 24(%rsp)
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2053:
.size _Z3dot6float3S_, .-_Z3dot6float3S_
.globl _Z6length6float3
.type _Z6length6float3, @function
_Z6length6float3:
.LFB2054:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2054:
.size _Z6length6float3, .-_Z6length6float3
.globl _Z9normalize6float3
.type _Z9normalize6float3, @function
_Z9normalize6float3:
.LFB2055:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2055:
.size _Z9normalize6float3, .-_Z9normalize6float3
.globl _Z4swapR6float3S0_
.type _Z4swapR6float3S0_, @function
_Z4swapR6float3S0_:
.LFB2056:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2056:
.size _Z4swapR6float3S0_, .-_Z4swapR6float3S0_
.globl _Zml4int2S_
.type _Zml4int2S_, @function
_Zml4int2S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Zml4int2S_, .-_Zml4int2S_
.globl _Zpl4int3S_
.type _Zpl4int3S_, @function
_Zpl4int3S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Zpl4int3S_, .-_Zpl4int3S_
.globl _Zmi4int3S_
.type _Zmi4int3S_, @function
_Zmi4int3S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Zmi4int3S_, .-_Zmi4int3S_
.globl _Zml4int3S_
.type _Zml4int3S_, @function
_Zml4int3S_:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Zml4int3S_, .-_Zml4int3S_
.globl _Zml4int3i
.type _Zml4int3i, @function
_Zml4int3i:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Zml4int3i, .-_Zml4int3i
.globl _ZmIR4int3i
.type _ZmIR4int3i, @function
_ZmIR4int3i:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _ZmIR4int3i, .-_ZmIR4int3i
.globl _Z3getR4int3i
.type _Z3getR4int3i, @function
_Z3getR4int3i:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z3getR4int3i, .-_Z3getR4int3i
.globl _Z3setR4int3ii
.type _Z3setR4int3ii, @function
_Z3setR4int3ii:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z3setR4int3ii, .-_Z3setR4int3ii
.globl _Z6toInt24int3ii
.type _Z6toInt24int3ii, @function
_Z6toInt24int3ii:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z6toInt24int3ii, .-_Z6toInt24int3ii
.globl _Z3min4int3
.type _Z3min4int3, @function
_Z3min4int3:
.LFB2066:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size _Z3min4int3, .-_Z3min4int3
.globl _Z4signi
.type _Z4signi, @function
_Z4signi:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z4signi, .-_Z4signi
.globl _Z4sign4int3
.type _Z4sign4int3, @function
_Z4sign4int3:
.LFB2068:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2068:
.size _Z4sign4int3, .-_Z4sign4int3
.globl _Z3abs4int3
.type _Z3abs4int3, @function
_Z3abs4int3:
.LFB2069:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2069:
.size _Z3abs4int3, .-_Z3abs4int3
.globl _Z3dot4int2S_
.type _Z3dot4int2S_, @function
_Z3dot4int2S_:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z3dot4int2S_, .-_Z3dot4int2S_
.globl _Z5cross4int3S_
.type _Z5cross4int3S_, @function
_Z5cross4int3S_:
.LFB2071:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 16(%rsp)
movl %esi, 24(%rsp)
movq %rdx, (%rsp)
movl %ecx, 8(%rsp)
movl $1, 44(%rsp)
movl 44(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size _Z5cross4int3S_, .-_Z5cross4int3S_
.globl _Z3max4int3
.type _Z3max4int3, @function
_Z3max4int3:
.LFB2072:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, (%rsp)
movl %esi, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2072:
.size _Z3max4int3, .-_Z3max4int3
.globl _Z3sum4int2
.type _Z3sum4int2, @function
_Z3sum4int2:
.LFB2073:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2073:
.size _Z3sum4int2, .-_Z3sum4int2
.globl _Z4swapR4int3S0_
.type _Z4swapR4int3S0_, @function
_Z4swapR4int3S0_:
.LFB2074:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2074:
.size _Z4swapR4int3S0_, .-_Z4swapR4int3S0_
.globl _Zpl6float2S_
.type _Zpl6float2S_, @function
_Zpl6float2S_:
.LFB2075:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2075:
.size _Zpl6float2S_, .-_Zpl6float2S_
.globl _Zmi6float2S_
.type _Zmi6float2S_, @function
_Zmi6float2S_:
.LFB2076:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2076:
.size _Zmi6float2S_, .-_Zmi6float2S_
.globl _Zml6float2f
.type _Zml6float2f, @function
_Zml6float2f:
.LFB2077:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2077:
.size _Zml6float2f, .-_Zml6float2f
.globl _Zdv6float2f
.type _Zdv6float2f, @function
_Zdv6float2f:
.LFB2078:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2078:
.size _Zdv6float2f, .-_Zdv6float2f
.globl _Z3getR6float2i
.type _Z3getR6float2i, @function
_Z3getR6float2i:
.LFB2079:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2079:
.size _Z3getR6float2i, .-_Z3getR6float2i
.globl _Z6length6float2
.type _Z6length6float2, @function
_Z6length6float2:
.LFB2080:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2080:
.size _Z6length6float2, .-_Z6length6float2
.globl _Z8toFloat26float3ii
.type _Z8toFloat26float3ii, @function
_Z8toFloat26float3ii:
.LFB2081:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm0, (%rsp)
movss %xmm1, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2081:
.size _Z8toFloat26float3ii, .-_Z8toFloat26float3ii
.globl _Z9normalize6float2
.type _Z9normalize6float2, @function
_Z9normalize6float2:
.LFB2082:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2082:
.size _Z9normalize6float2, .-_Z9normalize6float2
.globl _Z3dot6float2S_
.type _Z3dot6float2S_, @function
_Z3dot6float2S_:
.LFB2083:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2083:
.size _Z3dot6float2S_, .-_Z3dot6float2S_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2109:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VectorMath.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Calculates the average and standard deviation filters for the provided input.
* Note that it does not tamper with the channels BUT creates an output with 3 channels.
* Assumes that the input of the textures has the ALPHA component at the beginning.
*
*/
#define O_TILE_WIDTH 16
extern "C"
__global__ void newFilter(uchar4 *input, const int iPitchInElements,
float4 *average, float4 *stdDev, const int oPitchInElements,
const int width, const int height,
const int maskWidth) {
// get indices
int tx = threadIdx.x;
int ty = threadIdx.y;
int col_o = blockIdx.x * O_TILE_WIDTH + tx;
int row_o = blockIdx.y * O_TILE_WIDTH + ty;
int row_i = row_o - maskWidth / 2;
int col_i = col_o - maskWidth / 2;
__shared__ uchar4 tile[30][30];
if (row_i >= 0 && row_i < height && col_i >= 0 && col_i < iPitchInElements)
tile[ty][tx] = input[row_i * iPitchInElements + col_i];
// else
// tile[ty][tx] = make_uchar4(255, 0, 0, 0);
__syncthreads();
int count = maskWidth * maskWidth;
// first calculate the average
float4 sum = {0, 0, 0, 0};
float4 sumSd = {0, 0, 0, 0};
uchar4 fetched;
if (ty < O_TILE_WIDTH && tx < O_TILE_WIDTH) {
for (int i = 0 ; i < maskWidth ; i++)
for (int j = 0 ; j < maskWidth ; j++) {
fetched = tile[i + ty][j + tx];
sum.x += fetched.x;
sum.y += fetched.y;
sum.z += fetched.z;
sum.w += fetched.w;
}
sum.x /= count;
sum.y /= count;
sum.z /= count;
sum.w /= count;
for (int i = 0 ; i < maskWidth ; i++)
for (int j = 0 ; j < maskWidth ; j++) {
fetched = tile[i + ty][j + tx];
sumSd.x += pow(fetched.x - sum.x, 2);
sumSd.y += pow(fetched.y - sum.y, 2);
sumSd.z += pow(fetched.z - sum.z, 2);
sumSd.w += pow(fetched.w - sum.w, 2);
}
sumSd.x /= count;
sumSd.y /= count;
sumSd.z /= count;
sumSd.w /= count;
sumSd.x = sqrt(sumSd.x);
sumSd.y = sqrt(sumSd.y);
sumSd.z = sqrt(sumSd.z);
sumSd.w = sqrt(sumSd.w);
if (row_o < height && col_o < oPitchInElements) {
average[row_o * oPitchInElements + col_o] = sum;
stdDev[row_o * oPitchInElements + col_o] = sumSd;
}
}
} | .file "tmpxft_000b57fa_00000000-6_shared-filters.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z9newFilterP6uchar4iP6float4S2_iiiiP6uchar4iP6float4S2_iiii
.type _Z50__device_stub__Z9newFilterP6uchar4iP6float4S2_iiiiP6uchar4iP6float4S2_iiii, @function
_Z50__device_stub__Z9newFilterP6uchar4iP6float4S2_iiiiP6uchar4iP6float4S2_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 32(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq newFilter(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z9newFilterP6uchar4iP6float4S2_iiiiP6uchar4iP6float4S2_iiii, .-_Z50__device_stub__Z9newFilterP6uchar4iP6float4S2_iiiiP6uchar4iP6float4S2_iiii
.globl newFilter
.type newFilter, @function
newFilter:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z50__device_stub__Z9newFilterP6uchar4iP6float4S2_iiiiP6uchar4iP6float4S2_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size newFilter, .-newFilter
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "newFilter"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq newFilter(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Calculates the average and standard deviation filters for the provided input.
* Note that it does not tamper with the channels BUT creates an output with 3 channels.
* Assumes that the input of the textures has the ALPHA component at the beginning.
*
*/
#define O_TILE_WIDTH 16
extern "C"
__global__ void newFilter(uchar4 *input, const int iPitchInElements,
float4 *average, float4 *stdDev, const int oPitchInElements,
const int width, const int height,
const int maskWidth) {
// get indices
int tx = threadIdx.x;
int ty = threadIdx.y;
int col_o = blockIdx.x * O_TILE_WIDTH + tx;
int row_o = blockIdx.y * O_TILE_WIDTH + ty;
int row_i = row_o - maskWidth / 2;
int col_i = col_o - maskWidth / 2;
__shared__ uchar4 tile[30][30];
if (row_i >= 0 && row_i < height && col_i >= 0 && col_i < iPitchInElements)
tile[ty][tx] = input[row_i * iPitchInElements + col_i];
// else
// tile[ty][tx] = make_uchar4(255, 0, 0, 0);
__syncthreads();
int count = maskWidth * maskWidth;
// first calculate the average
float4 sum = {0, 0, 0, 0};
float4 sumSd = {0, 0, 0, 0};
uchar4 fetched;
if (ty < O_TILE_WIDTH && tx < O_TILE_WIDTH) {
for (int i = 0 ; i < maskWidth ; i++)
for (int j = 0 ; j < maskWidth ; j++) {
fetched = tile[i + ty][j + tx];
sum.x += fetched.x;
sum.y += fetched.y;
sum.z += fetched.z;
sum.w += fetched.w;
}
sum.x /= count;
sum.y /= count;
sum.z /= count;
sum.w /= count;
for (int i = 0 ; i < maskWidth ; i++)
for (int j = 0 ; j < maskWidth ; j++) {
fetched = tile[i + ty][j + tx];
sumSd.x += pow(fetched.x - sum.x, 2);
sumSd.y += pow(fetched.y - sum.y, 2);
sumSd.z += pow(fetched.z - sum.z, 2);
sumSd.w += pow(fetched.w - sum.w, 2);
}
sumSd.x /= count;
sumSd.y /= count;
sumSd.z /= count;
sumSd.w /= count;
sumSd.x = sqrt(sumSd.x);
sumSd.y = sqrt(sumSd.y);
sumSd.z = sqrt(sumSd.z);
sumSd.w = sqrt(sumSd.w);
if (row_o < height && col_o < oPitchInElements) {
average[row_o * oPitchInElements + col_o] = sum;
stdDev[row_o * oPitchInElements + col_o] = sumSd;
}
}
} | #include <hip/hip_runtime.h>
/**
* Calculates the average and standard deviation filters for the provided input.
* Note that it does not tamper with the channels BUT creates an output with 3 channels.
* Assumes that the input of the textures has the ALPHA component at the beginning.
*
*/
#define O_TILE_WIDTH 16
extern "C"
__global__ void newFilter(uchar4 *input, const int iPitchInElements,
float4 *average, float4 *stdDev, const int oPitchInElements,
const int width, const int height,
const int maskWidth) {
// get indices
int tx = threadIdx.x;
int ty = threadIdx.y;
int col_o = blockIdx.x * O_TILE_WIDTH + tx;
int row_o = blockIdx.y * O_TILE_WIDTH + ty;
int row_i = row_o - maskWidth / 2;
int col_i = col_o - maskWidth / 2;
__shared__ uchar4 tile[30][30];
if (row_i >= 0 && row_i < height && col_i >= 0 && col_i < iPitchInElements)
tile[ty][tx] = input[row_i * iPitchInElements + col_i];
// else
// tile[ty][tx] = make_uchar4(255, 0, 0, 0);
__syncthreads();
int count = maskWidth * maskWidth;
// first calculate the average
float4 sum = {0, 0, 0, 0};
float4 sumSd = {0, 0, 0, 0};
uchar4 fetched;
if (ty < O_TILE_WIDTH && tx < O_TILE_WIDTH) {
for (int i = 0 ; i < maskWidth ; i++)
for (int j = 0 ; j < maskWidth ; j++) {
fetched = tile[i + ty][j + tx];
sum.x += fetched.x;
sum.y += fetched.y;
sum.z += fetched.z;
sum.w += fetched.w;
}
sum.x /= count;
sum.y /= count;
sum.z /= count;
sum.w /= count;
for (int i = 0 ; i < maskWidth ; i++)
for (int j = 0 ; j < maskWidth ; j++) {
fetched = tile[i + ty][j + tx];
sumSd.x += pow(fetched.x - sum.x, 2);
sumSd.y += pow(fetched.y - sum.y, 2);
sumSd.z += pow(fetched.z - sum.z, 2);
sumSd.w += pow(fetched.w - sum.w, 2);
}
sumSd.x /= count;
sumSd.y /= count;
sumSd.z /= count;
sumSd.w /= count;
sumSd.x = sqrt(sumSd.x);
sumSd.y = sqrt(sumSd.y);
sumSd.z = sqrt(sumSd.z);
sumSd.w = sqrt(sumSd.w);
if (row_o < height && col_o < oPitchInElements) {
average[row_o * oPitchInElements + col_o] = sum;
stdDev[row_o * oPitchInElements + col_o] = sumSd;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/**
* Calculates the average and standard deviation filters for the provided input.
* Note that it does not tamper with the channels BUT creates an output with 3 channels.
* Assumes that the input of the textures has the ALPHA component at the beginning.
*
*/
#define O_TILE_WIDTH 16
extern "C"
__global__ void newFilter(uchar4 *input, const int iPitchInElements,
float4 *average, float4 *stdDev, const int oPitchInElements,
const int width, const int height,
const int maskWidth) {
// get indices
int tx = threadIdx.x;
int ty = threadIdx.y;
int col_o = blockIdx.x * O_TILE_WIDTH + tx;
int row_o = blockIdx.y * O_TILE_WIDTH + ty;
int row_i = row_o - maskWidth / 2;
int col_i = col_o - maskWidth / 2;
__shared__ uchar4 tile[30][30];
if (row_i >= 0 && row_i < height && col_i >= 0 && col_i < iPitchInElements)
tile[ty][tx] = input[row_i * iPitchInElements + col_i];
// else
// tile[ty][tx] = make_uchar4(255, 0, 0, 0);
__syncthreads();
int count = maskWidth * maskWidth;
// first calculate the average
float4 sum = {0, 0, 0, 0};
float4 sumSd = {0, 0, 0, 0};
uchar4 fetched;
if (ty < O_TILE_WIDTH && tx < O_TILE_WIDTH) {
for (int i = 0 ; i < maskWidth ; i++)
for (int j = 0 ; j < maskWidth ; j++) {
fetched = tile[i + ty][j + tx];
sum.x += fetched.x;
sum.y += fetched.y;
sum.z += fetched.z;
sum.w += fetched.w;
}
sum.x /= count;
sum.y /= count;
sum.z /= count;
sum.w /= count;
for (int i = 0 ; i < maskWidth ; i++)
for (int j = 0 ; j < maskWidth ; j++) {
fetched = tile[i + ty][j + tx];
sumSd.x += pow(fetched.x - sum.x, 2);
sumSd.y += pow(fetched.y - sum.y, 2);
sumSd.z += pow(fetched.z - sum.z, 2);
sumSd.w += pow(fetched.w - sum.w, 2);
}
sumSd.x /= count;
sumSd.y /= count;
sumSd.z /= count;
sumSd.w /= count;
sumSd.x = sqrt(sumSd.x);
sumSd.y = sqrt(sumSd.y);
sumSd.z = sqrt(sumSd.z);
sumSd.w = sqrt(sumSd.w);
if (row_o < height && col_o < oPitchInElements) {
average[row_o * oPitchInElements + col_o] = sum;
stdDev[row_o * oPitchInElements + col_o] = sumSd;
}
}
} | .text
.file "shared-filters.hip"
.globl __device_stub__newFilter # -- Begin function __device_stub__newFilter
.p2align 4, 0x90
.type __device_stub__newFilter,@function
__device_stub__newFilter: # @__device_stub__newFilter
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $newFilter, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__newFilter, .Lfunc_end0-__device_stub__newFilter
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $newFilter, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type newFilter,@object # @newFilter
.section .rodata,"a",@progbits
.globl newFilter
.p2align 3, 0x0
newFilter:
.quad __device_stub__newFilter
.size newFilter, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "newFilter"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__newFilter
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym newFilter
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b57fa_00000000-6_shared-filters.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z9newFilterP6uchar4iP6float4S2_iiiiP6uchar4iP6float4S2_iiii
.type _Z50__device_stub__Z9newFilterP6uchar4iP6float4S2_iiiiP6uchar4iP6float4S2_iiii, @function
_Z50__device_stub__Z9newFilterP6uchar4iP6float4S2_iiiiP6uchar4iP6float4S2_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 32(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq newFilter(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z9newFilterP6uchar4iP6float4S2_iiiiP6uchar4iP6float4S2_iiii, .-_Z50__device_stub__Z9newFilterP6uchar4iP6float4S2_iiiiP6uchar4iP6float4S2_iiii
.globl newFilter
.type newFilter, @function
newFilter:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z50__device_stub__Z9newFilterP6uchar4iP6float4S2_iiiiP6uchar4iP6float4S2_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size newFilter, .-newFilter
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "newFilter"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq newFilter(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "shared-filters.hip"
.globl __device_stub__newFilter # -- Begin function __device_stub__newFilter
.p2align 4, 0x90
.type __device_stub__newFilter,@function
__device_stub__newFilter: # @__device_stub__newFilter
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $newFilter, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__newFilter, .Lfunc_end0-__device_stub__newFilter
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $newFilter, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type newFilter,@object # @newFilter
.section .rodata,"a",@progbits
.globl newFilter
.p2align 3, 0x0
newFilter:
.quad __device_stub__newFilter
.size newFilter, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "newFilter"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__newFilter
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym newFilter
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda.h>
constexpr int N = 10;
/*
* NOTE:
* Come back to this function when directed to.
*
* - - - - - - - - - - - - - - - - - - - - - - -
*
* Hopefully by now you've seen how we allocate memory
* on the host and the device. Now that we've copied our
* data from the host to the device and called our kernel,
* we can take a look at our kernel.
*
* Please note how similar this is to our `1-threads` example.
* Each thread sets one index of c. This time, we don't manually
* pass the thread index to the thread because it's taken care of by
* CUDA, the library we are using.
*
* after examining the kernel you may return to where we called the kernel.
*/
__global__
void add_vectors(
double* a,
double* b,
double* c)
{
const int thread_id = blockIdx.x;
c[thread_id] = a[thread_id] + b[thread_id];
}
/*
*
* - - - - - - - - - - - - - - - - - - - - - - -
*
*/
int main(int, char**)
{
/*
* We are setting up the arrays in the same way
* as before
*/
std::cout << "Setting a=3, b=5, c=0\n";
auto a = new double[N];
auto b = new double[N];
auto c = new double[N];
for (int i=0; i<N; i++)
{
a[i] = 3.0;
b[i] = 5.0;
c[i] = 0.0;
}
/*
* This time, we also have to allocate
* memory on the 'device' which is our graphics card.
* our 'host' is the CPU, where this main function will run.
*/
double* device_a;
double* device_b;
double* device_c;
/*
* when we call `auto c = new double[N];` we are telling the CPU
* to allocate enough memory to fit N doubles. Now that we're also
* using a GPU, we have to tell the GPU to allocate enough memory
* for N doubles as well. We acomplish this with a cuda function:
*/
cudaMalloc(&device_a, N * sizeof(double));
cudaMalloc(&device_b, N * sizeof(double));
cudaMalloc(&device_c, N * sizeof(double));
/*
* Now we have a, b, and c allocated and set to 3, 5, and 0
* on the host. On the device however, we have only allocated
* the memory. The memory is uninitialized.
*
* To fix this, we will copy the values from a on the host
* into the memory allocated for a on the device, and same
* goes for b and c.
*/
cudaMemcpy(device_a, a, N * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(device_b, b, N * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(device_c, c, N * sizeof(double), cudaMemcpyHostToDevice);
/*
* Now that we have our memory copied from the host (cpu) to the
* device (gpu) we can call our cuda kernel. The kernel can *only*
* operate on memory allocated on the GPU.
*
* After examining the function call below, you may return to the
* top of the file to take a look at the kernel.
*
* Calling the function with function_name<<< , >>>(parameters);
* is how we inform cuda how it should configure our kernel.
*
* the first parameter to the triple angle brackets is the number of blocks
* per grid that should be allocated, and the second parameter is the number
* of threads per block that should be allocated.
* The grid is the largest unit of computation when calling a kernel.
*
* Note: grids and blocks are entirely defined in software. threads and
* warps are determined by the hardware. By aligning the number of
* blocks and threads in software with the threads in the physical
* hardware, we can achieve very large increases in performance.
*
* For example, calling `add_vectors<<<10, 1>>>(a, b, c)` would tell cuda
* to allocate it 10 blocks per grid, and 1 thread per block.
* Alternatively, calling `add_vectors<<<4, 10>>>(a, b, c)` would tell
* cuda to allocate 4 blocks, each with 10 threads per block totalling
* 40 threads.
*/
add_vectors<<<N, 1>>>(device_a, device_b, device_c);
/*
* Hopefully by now you have some understanding of the calling conventions
* for cuda kernels and the nature of the grid, blocks, and threads.
*
* Now let us copy the data back from the device to the host, and see if
* we still get what we expect.
*/
cudaMemcpy(c, device_c, N * sizeof(double), cudaMemcpyDeviceToHost);
for (int i=0; i<N; i++)
{
std::cout << "c["<<i<<"] = " << c[i] << "\n";
}
delete[] a;
delete[] b;
delete[] c;
/*
* We also have to free memory on the device since we allocated
* it in two places.
*/
cudaFree(device_a);
cudaFree(device_b);
cudaFree(device_c);
return 0;
} | code for sm_80
Function : _Z11add_vectorsPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x001fc800078e0209 */
/*0050*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe400078e0209 */
/*0060*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*0090*/ DADD R6, R2, R4 ; /* 0x0000000002067229 */
/* 0x004e0e0000000004 */
/*00a0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda.h>
constexpr int N = 10;
/*
* NOTE:
* Come back to this function when directed to.
*
* - - - - - - - - - - - - - - - - - - - - - - -
*
* Hopefully by now you've seen how we allocate memory
* on the host and the device. Now that we've copied our
* data from the host to the device and called our kernel,
* we can take a look at our kernel.
*
* Please note how similar this is to our `1-threads` example.
* Each thread sets one index of c. This time, we don't manually
* pass the thread index to the thread because it's taken care of by
* CUDA, the library we are using.
*
* after examining the kernel you may return to where we called the kernel.
*/
__global__
void add_vectors(
double* a,
double* b,
double* c)
{
const int thread_id = blockIdx.x;
c[thread_id] = a[thread_id] + b[thread_id];
}
/*
*
* - - - - - - - - - - - - - - - - - - - - - - -
*
*/
int main(int, char**)
{
/*
* We are setting up the arrays in the same way
* as before
*/
std::cout << "Setting a=3, b=5, c=0\n";
auto a = new double[N];
auto b = new double[N];
auto c = new double[N];
for (int i=0; i<N; i++)
{
a[i] = 3.0;
b[i] = 5.0;
c[i] = 0.0;
}
/*
* This time, we also have to allocate
* memory on the 'device' which is our graphics card.
* our 'host' is the CPU, where this main function will run.
*/
double* device_a;
double* device_b;
double* device_c;
/*
* when we call `auto c = new double[N];` we are telling the CPU
* to allocate enough memory to fit N doubles. Now that we're also
* using a GPU, we have to tell the GPU to allocate enough memory
* for N doubles as well. We acomplish this with a cuda function:
*/
cudaMalloc(&device_a, N * sizeof(double));
cudaMalloc(&device_b, N * sizeof(double));
cudaMalloc(&device_c, N * sizeof(double));
/*
* Now we have a, b, and c allocated and set to 3, 5, and 0
* on the host. On the device however, we have only allocated
* the memory. The memory is uninitialized.
*
* To fix this, we will copy the values from a on the host
* into the memory allocated for a on the device, and same
* goes for b and c.
*/
cudaMemcpy(device_a, a, N * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(device_b, b, N * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(device_c, c, N * sizeof(double), cudaMemcpyHostToDevice);
/*
* Now that we have our memory copied from the host (cpu) to the
* device (gpu) we can call our cuda kernel. The kernel can *only*
* operate on memory allocated on the GPU.
*
* After examining the function call below, you may return to the
* top of the file to take a look at the kernel.
*
* Calling the function with function_name<<< , >>>(parameters);
* is how we inform cuda how it should configure our kernel.
*
* the first parameter to the triple angle brackets is the number of blocks
* per grid that should be allocated, and the second parameter is the number
* of threads per block that should be allocated.
* The grid is the largest unit of computation when calling a kernel.
*
* Note: grids and blocks are entirely defined in software. threads and
* warps are determined by the hardware. By aligning the number of
* blocks and threads in software with the threads in the physical
* hardware, we can achieve very large increases in performance.
*
* For example, calling `add_vectors<<<10, 1>>>(a, b, c)` would tell cuda
* to allocate it 10 blocks per grid, and 1 thread per block.
* Alternatively, calling `add_vectors<<<4, 10>>>(a, b, c)` would tell
* cuda to allocate 4 blocks, each with 10 threads per block totalling
* 40 threads.
*/
add_vectors<<<N, 1>>>(device_a, device_b, device_c);
/*
* Hopefully by now you have some understanding of the calling conventions
* for cuda kernels and the nature of the grid, blocks, and threads.
*
* Now let us copy the data back from the device to the host, and see if
* we still get what we expect.
*/
cudaMemcpy(c, device_c, N * sizeof(double), cudaMemcpyDeviceToHost);
for (int i=0; i<N; i++)
{
std::cout << "c["<<i<<"] = " << c[i] << "\n";
}
delete[] a;
delete[] b;
delete[] c;
/*
* We also have to free memory on the device since we allocated
* it in two places.
*/
cudaFree(device_a);
cudaFree(device_b);
cudaFree(device_c);
return 0;
} | .file "tmpxft_0006d6b0_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_
.type _Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_, @function
_Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11add_vectorsPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_, .-_Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_
.globl _Z11add_vectorsPdS_S_
.type _Z11add_vectorsPdS_S_, @function
_Z11add_vectorsPdS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z11add_vectorsPdS_S_, .-_Z11add_vectorsPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Setting a=3, b=5, c=0\n"
.LC4:
.string "c["
.LC5:
.string "] = "
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $80, %edi
call _Znam@PLT
movq %rax, %r15
movl $80, %edi
call _Znam@PLT
movq %rax, %r14
movl $80, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
movsd .LC1(%rip), %xmm1
movsd .LC2(%rip), %xmm0
.L12:
movsd %xmm1, (%r15,%rax)
movsd %xmm0, (%r14,%rax)
movq $0x000000000, (%r12,%rax)
addq $8, %rax
cmpq $80, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $80, %edx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $80, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %r13
.L14:
movl $2, %edx
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $4, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd (%r12,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC6(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
movq %r15, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z11add_vectorsPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z11add_vectorsPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1074266112
.align 8
.LC2:
.long 0
.long 1075052544
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda.h>
constexpr int N = 10;
/*
* NOTE:
* Come back to this function when directed to.
*
* - - - - - - - - - - - - - - - - - - - - - - -
*
* Hopefully by now you've seen how we allocate memory
* on the host and the device. Now that we've copied our
* data from the host to the device and called our kernel,
* we can take a look at our kernel.
*
* Please note how similar this is to our `1-threads` example.
* Each thread sets one index of c. This time, we don't manually
* pass the thread index to the thread because it's taken care of by
* CUDA, the library we are using.
*
* after examining the kernel you may return to where we called the kernel.
*/
__global__
void add_vectors(
double* a,
double* b,
double* c)
{
const int thread_id = blockIdx.x;
c[thread_id] = a[thread_id] + b[thread_id];
}
/*
*
* - - - - - - - - - - - - - - - - - - - - - - -
*
*/
int main(int, char**)
{
/*
* We are setting up the arrays in the same way
* as before
*/
std::cout << "Setting a=3, b=5, c=0\n";
auto a = new double[N];
auto b = new double[N];
auto c = new double[N];
for (int i=0; i<N; i++)
{
a[i] = 3.0;
b[i] = 5.0;
c[i] = 0.0;
}
/*
* This time, we also have to allocate
* memory on the 'device' which is our graphics card.
* our 'host' is the CPU, where this main function will run.
*/
double* device_a;
double* device_b;
double* device_c;
/*
* when we call `auto c = new double[N];` we are telling the CPU
* to allocate enough memory to fit N doubles. Now that we're also
* using a GPU, we have to tell the GPU to allocate enough memory
* for N doubles as well. We acomplish this with a cuda function:
*/
cudaMalloc(&device_a, N * sizeof(double));
cudaMalloc(&device_b, N * sizeof(double));
cudaMalloc(&device_c, N * sizeof(double));
/*
* Now we have a, b, and c allocated and set to 3, 5, and 0
* on the host. On the device however, we have only allocated
* the memory. The memory is uninitialized.
*
* To fix this, we will copy the values from a on the host
* into the memory allocated for a on the device, and same
* goes for b and c.
*/
cudaMemcpy(device_a, a, N * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(device_b, b, N * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(device_c, c, N * sizeof(double), cudaMemcpyHostToDevice);
/*
* Now that we have our memory copied from the host (cpu) to the
* device (gpu) we can call our cuda kernel. The kernel can *only*
* operate on memory allocated on the GPU.
*
* After examining the function call below, you may return to the
* top of the file to take a look at the kernel.
*
* Calling the function with function_name<<< , >>>(parameters);
* is how we inform cuda how it should configure our kernel.
*
* the first parameter to the triple angle brackets is the number of blocks
* per grid that should be allocated, and the second parameter is the number
* of threads per block that should be allocated.
* The grid is the largest unit of computation when calling a kernel.
*
* Note: grids and blocks are entirely defined in software. threads and
* warps are determined by the hardware. By aligning the number of
* blocks and threads in software with the threads in the physical
* hardware, we can achieve very large increases in performance.
*
* For example, calling `add_vectors<<<10, 1>>>(a, b, c)` would tell cuda
* to allocate it 10 blocks per grid, and 1 thread per block.
* Alternatively, calling `add_vectors<<<4, 10>>>(a, b, c)` would tell
* cuda to allocate 4 blocks, each with 10 threads per block totalling
* 40 threads.
*/
add_vectors<<<N, 1>>>(device_a, device_b, device_c);
/*
* Hopefully by now you have some understanding of the calling conventions
* for cuda kernels and the nature of the grid, blocks, and threads.
*
* Now let us copy the data back from the device to the host, and see if
* we still get what we expect.
*/
cudaMemcpy(c, device_c, N * sizeof(double), cudaMemcpyDeviceToHost);
for (int i=0; i<N; i++)
{
std::cout << "c["<<i<<"] = " << c[i] << "\n";
}
delete[] a;
delete[] b;
delete[] c;
/*
* We also have to free memory on the device since we allocated
* it in two places.
*/
cudaFree(device_a);
cudaFree(device_b);
cudaFree(device_c);
return 0;
} | #include <iostream>
#include <hip/hip_runtime.h>
constexpr int N = 10;
/*
* NOTE:
* Come back to this function when directed to.
*
* - - - - - - - - - - - - - - - - - - - - - - -
*
* Hopefully by now you've seen how we allocate memory
* on the host and the device. Now that we've copied our
* data from the host to the device and called our kernel,
* we can take a look at our kernel.
*
* Please note how similar this is to our `1-threads` example.
* Each thread sets one index of c. This time, we don't manually
* pass the thread index to the thread because it's taken care of by
* CUDA, the library we are using.
*
* after examining the kernel you may return to where we called the kernel.
*/
__global__
void add_vectors(
double* a,
double* b,
double* c)
{
const int thread_id = blockIdx.x;
c[thread_id] = a[thread_id] + b[thread_id];
}
/*
*
* - - - - - - - - - - - - - - - - - - - - - - -
*
*/
int main(int, char**)
{
/*
* We are setting up the arrays in the same way
* as before
*/
std::cout << "Setting a=3, b=5, c=0\n";
auto a = new double[N];
auto b = new double[N];
auto c = new double[N];
for (int i=0; i<N; i++)
{
a[i] = 3.0;
b[i] = 5.0;
c[i] = 0.0;
}
/*
* This time, we also have to allocate
* memory on the 'device' which is our graphics card.
* our 'host' is the CPU, where this main function will run.
*/
double* device_a;
double* device_b;
double* device_c;
/*
* when we call `auto c = new double[N];` we are telling the CPU
* to allocate enough memory to fit N doubles. Now that we're also
* using a GPU, we have to tell the GPU to allocate enough memory
* for N doubles as well. We acomplish this with a cuda function:
*/
hipMalloc(&device_a, N * sizeof(double));
hipMalloc(&device_b, N * sizeof(double));
hipMalloc(&device_c, N * sizeof(double));
/*
* Now we have a, b, and c allocated and set to 3, 5, and 0
* on the host. On the device however, we have only allocated
* the memory. The memory is uninitialized.
*
* To fix this, we will copy the values from a on the host
* into the memory allocated for a on the device, and same
* goes for b and c.
*/
hipMemcpy(device_a, a, N * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(device_b, b, N * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(device_c, c, N * sizeof(double), hipMemcpyHostToDevice);
/*
* Now that we have our memory copied from the host (cpu) to the
* device (gpu) we can call our cuda kernel. The kernel can *only*
* operate on memory allocated on the GPU.
*
* After examining the function call below, you may return to the
* top of the file to take a look at the kernel.
*
* Calling the function with function_name<<< , >>>(parameters);
* is how we inform cuda how it should configure our kernel.
*
* the first parameter to the triple angle brackets is the number of blocks
* per grid that should be allocated, and the second parameter is the number
* of threads per block that should be allocated.
* The grid is the largest unit of computation when calling a kernel.
*
* Note: grids and blocks are entirely defined in software. threads and
* warps are determined by the hardware. By aligning the number of
* blocks and threads in software with the threads in the physical
* hardware, we can achieve very large increases in performance.
*
* For example, calling `add_vectors<<<10, 1>>>(a, b, c)` would tell cuda
* to allocate it 10 blocks per grid, and 1 thread per block.
* Alternatively, calling `add_vectors<<<4, 10>>>(a, b, c)` would tell
* cuda to allocate 4 blocks, each with 10 threads per block totalling
* 40 threads.
*/
add_vectors<<<N, 1>>>(device_a, device_b, device_c);
/*
* Hopefully by now you have some understanding of the calling conventions
* for cuda kernels and the nature of the grid, blocks, and threads.
*
* Now let us copy the data back from the device to the host, and see if
* we still get what we expect.
*/
hipMemcpy(c, device_c, N * sizeof(double), hipMemcpyDeviceToHost);
for (int i=0; i<N; i++)
{
std::cout << "c["<<i<<"] = " << c[i] << "\n";
}
delete[] a;
delete[] b;
delete[] c;
/*
* We also have to free memory on the device since we allocated
* it in two places.
*/
hipFree(device_a);
hipFree(device_b);
hipFree(device_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
constexpr int N = 10;
/*
* NOTE:
* Come back to this function when directed to.
*
* - - - - - - - - - - - - - - - - - - - - - - -
*
* Hopefully by now you've seen how we allocate memory
* on the host and the device. Now that we've copied our
* data from the host to the device and called our kernel,
* we can take a look at our kernel.
*
* Please note how similar this is to our `1-threads` example.
* Each thread sets one index of c. This time, we don't manually
* pass the thread index to the thread because it's taken care of by
* CUDA, the library we are using.
*
* after examining the kernel you may return to where we called the kernel.
*/
__global__
void add_vectors(
double* a,
double* b,
double* c)
{
const int thread_id = blockIdx.x;
c[thread_id] = a[thread_id] + b[thread_id];
}
/*
*
* - - - - - - - - - - - - - - - - - - - - - - -
*
*/
int main(int, char**)
{
/*
* We are setting up the arrays in the same way
* as before
*/
std::cout << "Setting a=3, b=5, c=0\n";
auto a = new double[N];
auto b = new double[N];
auto c = new double[N];
for (int i=0; i<N; i++)
{
a[i] = 3.0;
b[i] = 5.0;
c[i] = 0.0;
}
/*
* This time, we also have to allocate
* memory on the 'device' which is our graphics card.
* our 'host' is the CPU, where this main function will run.
*/
double* device_a;
double* device_b;
double* device_c;
/*
* when we call `auto c = new double[N];` we are telling the CPU
* to allocate enough memory to fit N doubles. Now that we're also
* using a GPU, we have to tell the GPU to allocate enough memory
* for N doubles as well. We acomplish this with a cuda function:
*/
hipMalloc(&device_a, N * sizeof(double));
hipMalloc(&device_b, N * sizeof(double));
hipMalloc(&device_c, N * sizeof(double));
/*
* Now we have a, b, and c allocated and set to 3, 5, and 0
* on the host. On the device however, we have only allocated
* the memory. The memory is uninitialized.
*
* To fix this, we will copy the values from a on the host
* into the memory allocated for a on the device, and same
* goes for b and c.
*/
hipMemcpy(device_a, a, N * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(device_b, b, N * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(device_c, c, N * sizeof(double), hipMemcpyHostToDevice);
/*
* Now that we have our memory copied from the host (cpu) to the
* device (gpu) we can call our cuda kernel. The kernel can *only*
* operate on memory allocated on the GPU.
*
* After examining the function call below, you may return to the
* top of the file to take a look at the kernel.
*
* Calling the function with function_name<<< , >>>(parameters);
* is how we inform cuda how it should configure our kernel.
*
* the first parameter to the triple angle brackets is the number of blocks
* per grid that should be allocated, and the second parameter is the number
* of threads per block that should be allocated.
* The grid is the largest unit of computation when calling a kernel.
*
* Note: grids and blocks are entirely defined in software. threads and
* warps are determined by the hardware. By aligning the number of
* blocks and threads in software with the threads in the physical
* hardware, we can achieve very large increases in performance.
*
* For example, calling `add_vectors<<<10, 1>>>(a, b, c)` would tell cuda
* to allocate it 10 blocks per grid, and 1 thread per block.
* Alternatively, calling `add_vectors<<<4, 10>>>(a, b, c)` would tell
* cuda to allocate 4 blocks, each with 10 threads per block totalling
* 40 threads.
*/
add_vectors<<<N, 1>>>(device_a, device_b, device_c);
/*
* Hopefully by now you have some understanding of the calling conventions
* for cuda kernels and the nature of the grid, blocks, and threads.
*
* Now let us copy the data back from the device to the host, and see if
* we still get what we expect.
*/
hipMemcpy(c, device_c, N * sizeof(double), hipMemcpyDeviceToHost);
for (int i=0; i<N; i++)
{
std::cout << "c["<<i<<"] = " << c[i] << "\n";
}
delete[] a;
delete[] b;
delete[] c;
/*
* We also have to free memory on the device since we allocated
* it in two places.
*/
hipFree(device_a);
hipFree(device_b);
hipFree(device_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11add_vectorsPdS_S_
.globl _Z11add_vectorsPdS_S_
.p2align 8
.type _Z11add_vectorsPdS_S_,@function
_Z11add_vectorsPdS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 3
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b64 s[4:5], s[4:5], 0x0
s_load_b64 s[6:7], s[6:7], 0x0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
v_add_f64 v[0:1], s[4:5], s[6:7]
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11add_vectorsPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11add_vectorsPdS_S_, .Lfunc_end0-_Z11add_vectorsPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11add_vectorsPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z11add_vectorsPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
constexpr int N = 10;
/*
* NOTE:
* Come back to this function when directed to.
*
* - - - - - - - - - - - - - - - - - - - - - - -
*
* Hopefully by now you've seen how we allocate memory
* on the host and the device. Now that we've copied our
* data from the host to the device and called our kernel,
* we can take a look at our kernel.
*
* Please note how similar this is to our `1-threads` example.
* Each thread sets one index of c. This time, we don't manually
* pass the thread index to the thread because it's taken care of by
* CUDA, the library we are using.
*
* after examining the kernel you may return to where we called the kernel.
*/
__global__
void add_vectors(
double* a,
double* b,
double* c)
{
const int thread_id = blockIdx.x;
c[thread_id] = a[thread_id] + b[thread_id];
}
/*
*
* - - - - - - - - - - - - - - - - - - - - - - -
*
*/
int main(int, char**)
{
/*
* We are setting up the arrays in the same way
* as before
*/
std::cout << "Setting a=3, b=5, c=0\n";
auto a = new double[N];
auto b = new double[N];
auto c = new double[N];
for (int i=0; i<N; i++)
{
a[i] = 3.0;
b[i] = 5.0;
c[i] = 0.0;
}
/*
* This time, we also have to allocate
* memory on the 'device' which is our graphics card.
* our 'host' is the CPU, where this main function will run.
*/
double* device_a;
double* device_b;
double* device_c;
/*
* when we call `auto c = new double[N];` we are telling the CPU
* to allocate enough memory to fit N doubles. Now that we're also
* using a GPU, we have to tell the GPU to allocate enough memory
* for N doubles as well. We acomplish this with a cuda function:
*/
hipMalloc(&device_a, N * sizeof(double));
hipMalloc(&device_b, N * sizeof(double));
hipMalloc(&device_c, N * sizeof(double));
/*
* Now we have a, b, and c allocated and set to 3, 5, and 0
* on the host. On the device however, we have only allocated
* the memory. The memory is uninitialized.
*
* To fix this, we will copy the values from a on the host
* into the memory allocated for a on the device, and same
* goes for b and c.
*/
hipMemcpy(device_a, a, N * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(device_b, b, N * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(device_c, c, N * sizeof(double), hipMemcpyHostToDevice);
/*
* Now that we have our memory copied from the host (cpu) to the
* device (gpu) we can call our cuda kernel. The kernel can *only*
* operate on memory allocated on the GPU.
*
* After examining the function call below, you may return to the
* top of the file to take a look at the kernel.
*
* Calling the function with function_name<<< , >>>(parameters);
* is how we inform cuda how it should configure our kernel.
*
* the first parameter to the triple angle brackets is the number of blocks
* per grid that should be allocated, and the second parameter is the number
* of threads per block that should be allocated.
* The grid is the largest unit of computation when calling a kernel.
*
* Note: grids and blocks are entirely defined in software. threads and
* warps are determined by the hardware. By aligning the number of
* blocks and threads in software with the threads in the physical
* hardware, we can achieve very large increases in performance.
*
* For example, calling `add_vectors<<<10, 1>>>(a, b, c)` would tell cuda
* to allocate it 10 blocks per grid, and 1 thread per block.
* Alternatively, calling `add_vectors<<<4, 10>>>(a, b, c)` would tell
* cuda to allocate 4 blocks, each with 10 threads per block totalling
* 40 threads.
*/
add_vectors<<<N, 1>>>(device_a, device_b, device_c);
/*
* Hopefully by now you have some understanding of the calling conventions
* for cuda kernels and the nature of the grid, blocks, and threads.
*
* Now let us copy the data back from the device to the host, and see if
* we still get what we expect.
*/
hipMemcpy(c, device_c, N * sizeof(double), hipMemcpyDeviceToHost);
for (int i=0; i<N; i++)
{
std::cout << "c["<<i<<"] = " << c[i] << "\n";
}
delete[] a;
delete[] b;
delete[] c;
/*
* We also have to free memory on the device since we allocated
* it in two places.
*/
hipFree(device_a);
hipFree(device_b);
hipFree(device_c);
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__add_vectorsPdS_S_ # -- Begin function _Z26__device_stub__add_vectorsPdS_S_
.p2align 4, 0x90
.type _Z26__device_stub__add_vectorsPdS_S_,@function
_Z26__device_stub__add_vectorsPdS_S_: # @_Z26__device_stub__add_vectorsPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11add_vectorsPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__add_vectorsPdS_S_, .Lfunc_end0-_Z26__device_stub__add_vectorsPdS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $80, %edi
callq _Znam
movq %rax, %rbx
movl $80, %edi
callq _Znam
movq %rax, %r14
movl $80, %edi
callq _Znam
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
xorl %eax, %eax
movabsq $4613937818241073152, %rcx # imm = 0x4008000000000000
movabsq $4617315517961601024, %rdx # imm = 0x4014000000000000
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax,8)
movq %rdx, (%r14,%rax,8)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movq %rsp, %rdi
movl $80, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $80, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11add_vectorsPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $80, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.2, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $10, %r12
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11add_vectorsPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11add_vectorsPdS_S_,@object # @_Z11add_vectorsPdS_S_
.section .rodata,"a",@progbits
.globl _Z11add_vectorsPdS_S_
.p2align 3, 0x0
_Z11add_vectorsPdS_S_:
.quad _Z26__device_stub__add_vectorsPdS_S_
.size _Z11add_vectorsPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Setting a=3, b=5, c=0\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "c["
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "] = "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11add_vectorsPdS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__add_vectorsPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11add_vectorsPdS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11add_vectorsPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R8, R9, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x001fc800078e0209 */
/*0050*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x0c0fe400078e0209 */
/*0060*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*0090*/ DADD R6, R2, R4 ; /* 0x0000000002067229 */
/* 0x004e0e0000000004 */
/*00a0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11add_vectorsPdS_S_
.globl _Z11add_vectorsPdS_S_
.p2align 8
.type _Z11add_vectorsPdS_S_,@function
_Z11add_vectorsPdS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 3
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b64 s[4:5], s[4:5], 0x0
s_load_b64 s[6:7], s[6:7], 0x0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
v_add_f64 v[0:1], s[4:5], s[6:7]
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11add_vectorsPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11add_vectorsPdS_S_, .Lfunc_end0-_Z11add_vectorsPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11add_vectorsPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z11add_vectorsPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006d6b0_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_
.type _Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_, @function
_Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11add_vectorsPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_, .-_Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_
.globl _Z11add_vectorsPdS_S_
.type _Z11add_vectorsPdS_S_, @function
_Z11add_vectorsPdS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z11add_vectorsPdS_S_, .-_Z11add_vectorsPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Setting a=3, b=5, c=0\n"
.LC4:
.string "c["
.LC5:
.string "] = "
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $80, %edi
call _Znam@PLT
movq %rax, %r15
movl $80, %edi
call _Znam@PLT
movq %rax, %r14
movl $80, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
movsd .LC1(%rip), %xmm1
movsd .LC2(%rip), %xmm0
.L12:
movsd %xmm1, (%r15,%rax)
movsd %xmm0, (%r14,%rax)
movq $0x000000000, (%r12,%rax)
addq $8, %rax
cmpq $80, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $80, %edx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $80, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %r13
.L14:
movl $2, %edx
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $4, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd (%r12,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC6(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
movq %r15, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z11add_vectorsPdS_S_PdS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z11add_vectorsPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z11add_vectorsPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1074266112
.align 8
.LC2:
.long 0
.long 1075052544
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__add_vectorsPdS_S_ # -- Begin function _Z26__device_stub__add_vectorsPdS_S_
.p2align 4, 0x90
.type _Z26__device_stub__add_vectorsPdS_S_,@function
_Z26__device_stub__add_vectorsPdS_S_: # @_Z26__device_stub__add_vectorsPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11add_vectorsPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__add_vectorsPdS_S_, .Lfunc_end0-_Z26__device_stub__add_vectorsPdS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $80, %edi
callq _Znam
movq %rax, %rbx
movl $80, %edi
callq _Znam
movq %rax, %r14
movl $80, %edi
callq _Znam
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
xorl %eax, %eax
movabsq $4613937818241073152, %rcx # imm = 0x4008000000000000
movabsq $4617315517961601024, %rdx # imm = 0x4014000000000000
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax,8)
movq %rdx, (%r14,%rax,8)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movq %rsp, %rdi
movl $80, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $80, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11add_vectorsPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $80, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.2, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $10, %r12
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11add_vectorsPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11add_vectorsPdS_S_,@object # @_Z11add_vectorsPdS_S_
.section .rodata,"a",@progbits
.globl _Z11add_vectorsPdS_S_
.p2align 3, 0x0
_Z11add_vectorsPdS_S_:
.quad _Z26__device_stub__add_vectorsPdS_S_
.size _Z11add_vectorsPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Setting a=3, b=5, c=0\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "c["
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "] = "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11add_vectorsPdS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__add_vectorsPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11add_vectorsPdS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
/*Lx2Cuda performs the 2-D convolution of matrices A and row vector B*/
__global__ void Lx2(const float *d_in,float *d_out,int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((4<Row) && (Row<numRows-5) && (4<Col) && (Col<numCols-5)){
d_out[Col*numRows+Row]=mask[0]*d_in[Col*numRows+Row]+
mask[1]*(d_in[(Col-1)*numRows+Row]+d_in[(Col+1)*numRows+Row])+
mask[2]*(d_in[(Col-2)*numRows+Row]+d_in[(Col+2)*numRows+Row])+
mask[3]*(d_in[(Col-3)*numRows+Row]+d_in[(Col+3)*numRows+Row])+
mask[4]*(d_in[(Col-4)*numRows+Row]+d_in[(Col+4)*numRows+Row])+
mask[5]*(d_in[(Col-5)*numRows+Row]+d_in[(Col+5)*numRows+Row]);
}
}
/*Lz2 performs the 2-D convolution of matrices A and column vector B*/
__global__ void Lz2(const float *d_in,float *d_out,int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((4<Row) && (Row<numRows-5) && (4<Col) && (Col<numCols-5)){
int Loc = Col*numRows+Row;
d_out[Loc]=mask[0]*d_in[Loc]+
mask[1]*(d_in[Loc-1]+d_in[Loc+1])+
mask[2]*(d_in[Loc-2]+d_in[Loc+2])+
mask[3]*(d_in[Loc-3]+d_in[Loc+3])+
mask[4]*(d_in[Loc-4]+d_in[Loc+4])+
mask[5]*(d_in[Loc-5]+d_in[Loc+5]);
}
}
/*Lz1 performs the 2-D convolution of matrices A and column vector C1*/
__global__ void Lz1(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
int Loc = Col*numRows+Row;
d_out[Loc]=
mask[0]*(d_in[Loc+1]-d_in[Loc-1])+
mask[1]*(d_in[Loc+2]-d_in[Loc-2])+
mask[2]*(d_in[Loc+3]-d_in[Loc-3])+
mask[3]*(d_in[Loc+4]-d_in[Loc-4])+
mask[4]*(d_in[Loc+5]-d_in[Loc-5])+
mask[5]*(d_in[Loc+6]-d_in[Loc-6]);
}
}
/*Lx1 performs the 2-D convolution of matrices A and row vector C1*/
__global__ void Lx1(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_out[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
mask[1]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
mask[2]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
mask[3]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
mask[4]*(d_in[(Col+5)*numRows+Row]-d_in[(Col-5)*numRows+Row])+
mask[5]*(d_in[(Col+6)*numRows+Row]-d_in[(Col-6)*numRows+Row]);
}
}
/*sbLx performs the 2-D convolution of matrices A and row vector S1*/
__global__ void sbLx(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_out[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-0)*numRows+Row])+
mask[1]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
mask[2]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
mask[3]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
mask[4]*(d_in[(Col+5)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
mask[5]*(d_in[(Col+6)*numRows+Row]+d_in[(Col-5)*numRows+Row]);
}
}
/*sfLx performs the 2-D convolution of matrices A and row vector S1*/
__global__ void sfLx(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_out[Col*numRows+Row]=
mask[0]*(d_in[(Col+0)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
mask[1]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
mask[2]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
mask[3]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
mask[4]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-5)*numRows+Row])+
mask[5]*(d_in[(Col+5)*numRows+Row]+d_in[(Col-6)*numRows+Row]);
}
}
/*sbLz performs the 2-D convolution of matrices A and column vector S1*/
__global__ void sbLz(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
int Loc = Col*numRows+Row;
d_out[Col*numRows+Row]=
mask[0]*(d_in[Loc+1]-d_in[Loc-0])+
mask[1]*(d_in[Loc+2]-d_in[Loc-1])+
mask[2]*(d_in[Loc+3]-d_in[Loc-2])+
mask[3]*(d_in[Loc+4]-d_in[Loc-3])+
mask[4]*(d_in[Loc+5]-d_in[Loc-4])+
mask[5]*(d_in[Loc+6]+d_in[Loc-5]);
}
}
/*sfLz performs the 2-D convolution of matrices A and column vector S1*/
__global__ void sfLz(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
int Loc = Col*numRows+Row;
d_out[Loc]=
mask[0]*(d_in[Loc+0]-d_in[Loc-1])+
mask[1]*(d_in[Loc+1]-d_in[Loc-2])+
mask[2]*(d_in[Loc+2]-d_in[Loc-3])+
mask[3]*(d_in[Loc+3]-d_in[Loc-4])+
mask[4]*(d_in[Loc+4]-d_in[Loc-5])+
mask[5]*(d_in[Loc+5]+d_in[Loc-6]);
}
}
/*rsgffd performs the 2-D forward rotated staggered-grid finite difference*/
__global__ void rsgffd(const float *d_in,float *d_outx,float *d_outz,const int numRows,int numCols,float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_outx[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row-0]-d_in[(Col-0)*numRows+Row+1])+
mask[1]*(d_in[(Col+2)*numRows+Row-1]-d_in[(Col-1)*numRows+Row+2])+
mask[2]*(d_in[(Col+3)*numRows+Row-2]-d_in[(Col-2)*numRows+Row+3])+
mask[3]*(d_in[(Col+4)*numRows+Row-3]-d_in[(Col-3)*numRows+Row+4])+
mask[4]*(d_in[(Col+5)*numRows+Row-4]-d_in[(Col-4)*numRows+Row+5])+
mask[5]*(d_in[(Col+6)*numRows+Row-5]-d_in[(Col-5)*numRows+Row+6]);
d_outz[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row+1]-d_in[(Col-0)*numRows+Row-0])+
mask[1]*(d_in[(Col+2)*numRows+Row+2]-d_in[(Col-1)*numRows+Row-1])+
mask[2]*(d_in[(Col+3)*numRows+Row+3]-d_in[(Col-2)*numRows+Row-2])+
mask[3]*(d_in[(Col+4)*numRows+Row+4]-d_in[(Col-3)*numRows+Row-3])+
mask[4]*(d_in[(Col+5)*numRows+Row+5]-d_in[(Col-4)*numRows+Row-4])+
mask[5]*(d_in[(Col+6)*numRows+Row+6]-d_in[(Col-5)*numRows+Row-5]);
}
}
/*rsgbfd performs the 2-D backward rotated staggered-grid finite difference*/
__global__ void rsgbfd(const float *d_in,float *d_outx,float *d_outz,int numRows,int numCols,float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_outx[Col*numRows+Row]=
mask[0]*(d_in[(Col+0)*numRows+Row-1]-d_in[(Col-1)*numRows+Row+0])+
mask[1]*(d_in[(Col+1)*numRows+Row-2]-d_in[(Col-2)*numRows+Row+1])+
mask[2]*(d_in[(Col+2)*numRows+Row-3]-d_in[(Col-3)*numRows+Row+2])+
mask[3]*(d_in[(Col+3)*numRows+Row-4]-d_in[(Col-4)*numRows+Row+3])+
mask[4]*(d_in[(Col+4)*numRows+Row-5]-d_in[(Col-5)*numRows+Row+4])+
mask[5]*(d_in[(Col+5)*numRows+Row-6]-d_in[(Col-6)*numRows+Row+5]);
d_outz[Col*numRows+Row]=
mask[0]*(d_in[(Col+0)*numRows+Row+0]-d_in[(Col-1)*numRows+Row-1])+
mask[1]*(d_in[(Col+1)*numRows+Row+1]-d_in[(Col-2)*numRows+Row-2])+
mask[2]*(d_in[(Col+2)*numRows+Row+2]-d_in[(Col-3)*numRows+Row-3])+
mask[3]*(d_in[(Col+3)*numRows+Row+3]-d_in[(Col-4)*numRows+Row-4])+
mask[4]*(d_in[(Col+4)*numRows+Row+4]-d_in[(Col-5)*numRows+Row-5])+
mask[5]*(d_in[(Col+5)*numRows+Row+5]-d_in[(Col-6)*numRows+Row-6]);
}
} | .file "tmpxft_000b2be5_00000000-6_gfconvn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_
.type _Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_, @function
_Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3Lx2PKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_, .-_Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_
.globl _Z3Lx2PKfPfiiS1_
.type _Z3Lx2PKfPfiiS1_, @function
_Z3Lx2PKfPfiiS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3Lx2PKfPfiiS1_, .-_Z3Lx2PKfPfiiS1_
.globl _Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_
.type _Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_, @function
_Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3Lz2PKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_, .-_Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_
.globl _Z3Lz2PKfPfiiS1_
.type _Z3Lz2PKfPfiiS1_, @function
_Z3Lz2PKfPfiiS1_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z3Lz2PKfPfiiS1_, .-_Z3Lz2PKfPfiiS1_
.globl _Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_
.type _Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_, @function
_Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3Lz1PKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_, .-_Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_
.globl _Z3Lz1PKfPfiiS1_
.type _Z3Lz1PKfPfiiS1_, @function
_Z3Lz1PKfPfiiS1_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z3Lz1PKfPfiiS1_, .-_Z3Lz1PKfPfiiS1_
.globl _Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_
.type _Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_, @function
_Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3Lx1PKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_, .-_Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_
.globl _Z3Lx1PKfPfiiS1_
.type _Z3Lx1PKfPfiiS1_, @function
_Z3Lx1PKfPfiiS1_:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z3Lx1PKfPfiiS1_, .-_Z3Lx1PKfPfiiS1_
.globl _Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_
.type _Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_, @function
_Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_:
.LFB2059:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sbLxPKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_, .-_Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_
.globl _Z4sbLxPKfPfiiS1_
.type _Z4sbLxPKfPfiiS1_, @function
_Z4sbLxPKfPfiiS1_:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z4sbLxPKfPfiiS1_, .-_Z4sbLxPKfPfiiS1_
.globl _Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_
.type _Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_, @function
_Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_:
.LFB2061:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sfLxPKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_, .-_Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_
.globl _Z4sfLxPKfPfiiS1_
.type _Z4sfLxPKfPfiiS1_, @function
_Z4sfLxPKfPfiiS1_:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z4sfLxPKfPfiiS1_, .-_Z4sfLxPKfPfiiS1_
.globl _Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_
.type _Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_, @function
_Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_:
.LFB2063:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sbLzPKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_, .-_Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_
.globl _Z4sbLzPKfPfiiS1_
.type _Z4sbLzPKfPfiiS1_, @function
_Z4sbLzPKfPfiiS1_:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z4sbLzPKfPfiiS1_, .-_Z4sbLzPKfPfiiS1_
.globl _Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_
.type _Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_, @function
_Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_:
.LFB2065:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sfLzPKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_, .-_Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_
.globl _Z4sfLzPKfPfiiS1_
.type _Z4sfLzPKfPfiiS1_, @function
_Z4sfLzPKfPfiiS1_:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _Z4sfLzPKfPfiiS1_, .-_Z4sfLzPKfPfiiS1_
.globl _Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_
.type _Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_, @function
_Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_:
.LFB2067:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L71
.L67:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L72
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6rsgffdPKfPfS1_iiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L67
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2067:
.size _Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_, .-_Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_
.globl _Z6rsgffdPKfPfS1_iiS1_
.type _Z6rsgffdPKfPfS1_iiS1_, @function
_Z6rsgffdPKfPfS1_iiS1_:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _Z6rsgffdPKfPfS1_iiS1_, .-_Z6rsgffdPKfPfS1_iiS1_
.globl _Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_
.type _Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_, @function
_Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_:
.LFB2069:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L79
.L75:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6rsgbfdPKfPfS1_iiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L75
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2069:
.size _Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_, .-_Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_
.globl _Z6rsgbfdPKfPfS1_iiS1_
.type _Z6rsgbfdPKfPfS1_iiS1_, @function
_Z6rsgbfdPKfPfS1_iiS1_:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z6rsgbfdPKfPfS1_iiS1_, .-_Z6rsgbfdPKfPfS1_iiS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6rsgbfdPKfPfS1_iiS1_"
.LC1:
.string "_Z6rsgffdPKfPfS1_iiS1_"
.LC2:
.string "_Z4sfLzPKfPfiiS1_"
.LC3:
.string "_Z4sbLzPKfPfiiS1_"
.LC4:
.string "_Z4sfLxPKfPfiiS1_"
.LC5:
.string "_Z4sbLxPKfPfiiS1_"
.LC6:
.string "_Z3Lx1PKfPfiiS1_"
.LC7:
.string "_Z3Lz1PKfPfiiS1_"
.LC8:
.string "_Z3Lz2PKfPfiiS1_"
.LC9:
.string "_Z3Lx2PKfPfiiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2072:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6rsgbfdPKfPfS1_iiS1_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6rsgffdPKfPfS1_iiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sfLzPKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sbLzPKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sfLxPKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sbLxPKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3Lx1PKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3Lz1PKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3Lz2PKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z3Lx2PKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
/*Lx2Cuda performs the 2-D convolution of matrices A and row vector B*/
__global__ void Lx2(const float *d_in,float *d_out,int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((4<Row) && (Row<numRows-5) && (4<Col) && (Col<numCols-5)){
d_out[Col*numRows+Row]=mask[0]*d_in[Col*numRows+Row]+
mask[1]*(d_in[(Col-1)*numRows+Row]+d_in[(Col+1)*numRows+Row])+
mask[2]*(d_in[(Col-2)*numRows+Row]+d_in[(Col+2)*numRows+Row])+
mask[3]*(d_in[(Col-3)*numRows+Row]+d_in[(Col+3)*numRows+Row])+
mask[4]*(d_in[(Col-4)*numRows+Row]+d_in[(Col+4)*numRows+Row])+
mask[5]*(d_in[(Col-5)*numRows+Row]+d_in[(Col+5)*numRows+Row]);
}
}
/*Lz2 performs the 2-D convolution of matrices A and column vector B*/
__global__ void Lz2(const float *d_in,float *d_out,int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((4<Row) && (Row<numRows-5) && (4<Col) && (Col<numCols-5)){
int Loc = Col*numRows+Row;
d_out[Loc]=mask[0]*d_in[Loc]+
mask[1]*(d_in[Loc-1]+d_in[Loc+1])+
mask[2]*(d_in[Loc-2]+d_in[Loc+2])+
mask[3]*(d_in[Loc-3]+d_in[Loc+3])+
mask[4]*(d_in[Loc-4]+d_in[Loc+4])+
mask[5]*(d_in[Loc-5]+d_in[Loc+5]);
}
}
/*Lz1 performs the 2-D convolution of matrices A and column vector C1*/
__global__ void Lz1(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
int Loc = Col*numRows+Row;
d_out[Loc]=
mask[0]*(d_in[Loc+1]-d_in[Loc-1])+
mask[1]*(d_in[Loc+2]-d_in[Loc-2])+
mask[2]*(d_in[Loc+3]-d_in[Loc-3])+
mask[3]*(d_in[Loc+4]-d_in[Loc-4])+
mask[4]*(d_in[Loc+5]-d_in[Loc-5])+
mask[5]*(d_in[Loc+6]-d_in[Loc-6]);
}
}
/*Lx1 performs the 2-D convolution of matrices A and row vector C1*/
__global__ void Lx1(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_out[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
mask[1]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
mask[2]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
mask[3]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
mask[4]*(d_in[(Col+5)*numRows+Row]-d_in[(Col-5)*numRows+Row])+
mask[5]*(d_in[(Col+6)*numRows+Row]-d_in[(Col-6)*numRows+Row]);
}
}
/*sbLx performs the 2-D convolution of matrices A and row vector S1*/
__global__ void sbLx(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_out[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-0)*numRows+Row])+
mask[1]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
mask[2]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
mask[3]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
mask[4]*(d_in[(Col+5)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
mask[5]*(d_in[(Col+6)*numRows+Row]+d_in[(Col-5)*numRows+Row]);
}
}
/*sfLx performs the 2-D convolution of matrices A and row vector S1*/
__global__ void sfLx(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_out[Col*numRows+Row]=
mask[0]*(d_in[(Col+0)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
mask[1]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
mask[2]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
mask[3]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
mask[4]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-5)*numRows+Row])+
mask[5]*(d_in[(Col+5)*numRows+Row]+d_in[(Col-6)*numRows+Row]);
}
}
/*sbLz performs the 2-D convolution of matrices A and column vector S1*/
__global__ void sbLz(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
int Loc = Col*numRows+Row;
d_out[Col*numRows+Row]=
mask[0]*(d_in[Loc+1]-d_in[Loc-0])+
mask[1]*(d_in[Loc+2]-d_in[Loc-1])+
mask[2]*(d_in[Loc+3]-d_in[Loc-2])+
mask[3]*(d_in[Loc+4]-d_in[Loc-3])+
mask[4]*(d_in[Loc+5]-d_in[Loc-4])+
mask[5]*(d_in[Loc+6]+d_in[Loc-5]);
}
}
/*sfLz performs the 2-D convolution of matrices A and column vector S1*/
__global__ void sfLz(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
int Loc = Col*numRows+Row;
d_out[Loc]=
mask[0]*(d_in[Loc+0]-d_in[Loc-1])+
mask[1]*(d_in[Loc+1]-d_in[Loc-2])+
mask[2]*(d_in[Loc+2]-d_in[Loc-3])+
mask[3]*(d_in[Loc+3]-d_in[Loc-4])+
mask[4]*(d_in[Loc+4]-d_in[Loc-5])+
mask[5]*(d_in[Loc+5]+d_in[Loc-6]);
}
}
/*rsgffd performs the 2-D forward rotated staggered-grid finite difference*/
__global__ void rsgffd(const float *d_in,float *d_outx,float *d_outz,const int numRows,int numCols,float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_outx[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row-0]-d_in[(Col-0)*numRows+Row+1])+
mask[1]*(d_in[(Col+2)*numRows+Row-1]-d_in[(Col-1)*numRows+Row+2])+
mask[2]*(d_in[(Col+3)*numRows+Row-2]-d_in[(Col-2)*numRows+Row+3])+
mask[3]*(d_in[(Col+4)*numRows+Row-3]-d_in[(Col-3)*numRows+Row+4])+
mask[4]*(d_in[(Col+5)*numRows+Row-4]-d_in[(Col-4)*numRows+Row+5])+
mask[5]*(d_in[(Col+6)*numRows+Row-5]-d_in[(Col-5)*numRows+Row+6]);
d_outz[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row+1]-d_in[(Col-0)*numRows+Row-0])+
mask[1]*(d_in[(Col+2)*numRows+Row+2]-d_in[(Col-1)*numRows+Row-1])+
mask[2]*(d_in[(Col+3)*numRows+Row+3]-d_in[(Col-2)*numRows+Row-2])+
mask[3]*(d_in[(Col+4)*numRows+Row+4]-d_in[(Col-3)*numRows+Row-3])+
mask[4]*(d_in[(Col+5)*numRows+Row+5]-d_in[(Col-4)*numRows+Row-4])+
mask[5]*(d_in[(Col+6)*numRows+Row+6]-d_in[(Col-5)*numRows+Row-5]);
}
}
/*rsgbfd performs the 2-D backward rotated staggered-grid finite difference*/
__global__ void rsgbfd(const float *d_in,float *d_outx,float *d_outz,int numRows,int numCols,float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_outx[Col*numRows+Row]=
mask[0]*(d_in[(Col+0)*numRows+Row-1]-d_in[(Col-1)*numRows+Row+0])+
mask[1]*(d_in[(Col+1)*numRows+Row-2]-d_in[(Col-2)*numRows+Row+1])+
mask[2]*(d_in[(Col+2)*numRows+Row-3]-d_in[(Col-3)*numRows+Row+2])+
mask[3]*(d_in[(Col+3)*numRows+Row-4]-d_in[(Col-4)*numRows+Row+3])+
mask[4]*(d_in[(Col+4)*numRows+Row-5]-d_in[(Col-5)*numRows+Row+4])+
mask[5]*(d_in[(Col+5)*numRows+Row-6]-d_in[(Col-6)*numRows+Row+5]);
d_outz[Col*numRows+Row]=
mask[0]*(d_in[(Col+0)*numRows+Row+0]-d_in[(Col-1)*numRows+Row-1])+
mask[1]*(d_in[(Col+1)*numRows+Row+1]-d_in[(Col-2)*numRows+Row-2])+
mask[2]*(d_in[(Col+2)*numRows+Row+2]-d_in[(Col-3)*numRows+Row-3])+
mask[3]*(d_in[(Col+3)*numRows+Row+3]-d_in[(Col-4)*numRows+Row-4])+
mask[4]*(d_in[(Col+4)*numRows+Row+4]-d_in[(Col-5)*numRows+Row-5])+
mask[5]*(d_in[(Col+5)*numRows+Row+5]-d_in[(Col-6)*numRows+Row-6]);
}
} | #include <hip/hip_runtime.h>
/*Lx2Cuda performs the 2-D convolution of matrices A and row vector B*/
__global__ void Lx2(const float *d_in,float *d_out,int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((4<Row) && (Row<numRows-5) && (4<Col) && (Col<numCols-5)){
d_out[Col*numRows+Row]=mask[0]*d_in[Col*numRows+Row]+
mask[1]*(d_in[(Col-1)*numRows+Row]+d_in[(Col+1)*numRows+Row])+
mask[2]*(d_in[(Col-2)*numRows+Row]+d_in[(Col+2)*numRows+Row])+
mask[3]*(d_in[(Col-3)*numRows+Row]+d_in[(Col+3)*numRows+Row])+
mask[4]*(d_in[(Col-4)*numRows+Row]+d_in[(Col+4)*numRows+Row])+
mask[5]*(d_in[(Col-5)*numRows+Row]+d_in[(Col+5)*numRows+Row]);
}
}
/*Lz2 performs the 2-D convolution of matrices A and column vector B*/
__global__ void Lz2(const float *d_in,float *d_out,int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((4<Row) && (Row<numRows-5) && (4<Col) && (Col<numCols-5)){
int Loc = Col*numRows+Row;
d_out[Loc]=mask[0]*d_in[Loc]+
mask[1]*(d_in[Loc-1]+d_in[Loc+1])+
mask[2]*(d_in[Loc-2]+d_in[Loc+2])+
mask[3]*(d_in[Loc-3]+d_in[Loc+3])+
mask[4]*(d_in[Loc-4]+d_in[Loc+4])+
mask[5]*(d_in[Loc-5]+d_in[Loc+5]);
}
}
/*Lz1 performs the 2-D convolution of matrices A and column vector C1*/
__global__ void Lz1(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
int Loc = Col*numRows+Row;
d_out[Loc]=
mask[0]*(d_in[Loc+1]-d_in[Loc-1])+
mask[1]*(d_in[Loc+2]-d_in[Loc-2])+
mask[2]*(d_in[Loc+3]-d_in[Loc-3])+
mask[3]*(d_in[Loc+4]-d_in[Loc-4])+
mask[4]*(d_in[Loc+5]-d_in[Loc-5])+
mask[5]*(d_in[Loc+6]-d_in[Loc-6]);
}
}
/*Lx1 performs the 2-D convolution of matrices A and row vector C1*/
__global__ void Lx1(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_out[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
mask[1]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
mask[2]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
mask[3]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
mask[4]*(d_in[(Col+5)*numRows+Row]-d_in[(Col-5)*numRows+Row])+
mask[5]*(d_in[(Col+6)*numRows+Row]-d_in[(Col-6)*numRows+Row]);
}
}
/*sbLx performs the 2-D convolution of matrices A and row vector S1*/
__global__ void sbLx(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_out[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-0)*numRows+Row])+
mask[1]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
mask[2]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
mask[3]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
mask[4]*(d_in[(Col+5)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
mask[5]*(d_in[(Col+6)*numRows+Row]+d_in[(Col-5)*numRows+Row]);
}
}
/*sfLx performs the 2-D convolution of matrices A and row vector S1*/
__global__ void sfLx(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_out[Col*numRows+Row]=
mask[0]*(d_in[(Col+0)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
mask[1]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
mask[2]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
mask[3]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
mask[4]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-5)*numRows+Row])+
mask[5]*(d_in[(Col+5)*numRows+Row]+d_in[(Col-6)*numRows+Row]);
}
}
/*sbLz performs the 2-D convolution of matrices A and column vector S1*/
__global__ void sbLz(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
int Loc = Col*numRows+Row;
d_out[Col*numRows+Row]=
mask[0]*(d_in[Loc+1]-d_in[Loc-0])+
mask[1]*(d_in[Loc+2]-d_in[Loc-1])+
mask[2]*(d_in[Loc+3]-d_in[Loc-2])+
mask[3]*(d_in[Loc+4]-d_in[Loc-3])+
mask[4]*(d_in[Loc+5]-d_in[Loc-4])+
mask[5]*(d_in[Loc+6]+d_in[Loc-5]);
}
}
/*sfLz performs the 2-D convolution of matrices A and column vector S1*/
__global__ void sfLz(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
int Loc = Col*numRows+Row;
d_out[Loc]=
mask[0]*(d_in[Loc+0]-d_in[Loc-1])+
mask[1]*(d_in[Loc+1]-d_in[Loc-2])+
mask[2]*(d_in[Loc+2]-d_in[Loc-3])+
mask[3]*(d_in[Loc+3]-d_in[Loc-4])+
mask[4]*(d_in[Loc+4]-d_in[Loc-5])+
mask[5]*(d_in[Loc+5]+d_in[Loc-6]);
}
}
/*rsgffd performs the 2-D forward rotated staggered-grid finite difference*/
__global__ void rsgffd(const float *d_in,float *d_outx,float *d_outz,const int numRows,int numCols,float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_outx[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row-0]-d_in[(Col-0)*numRows+Row+1])+
mask[1]*(d_in[(Col+2)*numRows+Row-1]-d_in[(Col-1)*numRows+Row+2])+
mask[2]*(d_in[(Col+3)*numRows+Row-2]-d_in[(Col-2)*numRows+Row+3])+
mask[3]*(d_in[(Col+4)*numRows+Row-3]-d_in[(Col-3)*numRows+Row+4])+
mask[4]*(d_in[(Col+5)*numRows+Row-4]-d_in[(Col-4)*numRows+Row+5])+
mask[5]*(d_in[(Col+6)*numRows+Row-5]-d_in[(Col-5)*numRows+Row+6]);
d_outz[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row+1]-d_in[(Col-0)*numRows+Row-0])+
mask[1]*(d_in[(Col+2)*numRows+Row+2]-d_in[(Col-1)*numRows+Row-1])+
mask[2]*(d_in[(Col+3)*numRows+Row+3]-d_in[(Col-2)*numRows+Row-2])+
mask[3]*(d_in[(Col+4)*numRows+Row+4]-d_in[(Col-3)*numRows+Row-3])+
mask[4]*(d_in[(Col+5)*numRows+Row+5]-d_in[(Col-4)*numRows+Row-4])+
mask[5]*(d_in[(Col+6)*numRows+Row+6]-d_in[(Col-5)*numRows+Row-5]);
}
}
/*rsgbfd performs the 2-D backward rotated staggered-grid finite difference*/
__global__ void rsgbfd(const float *d_in,float *d_outx,float *d_outz,int numRows,int numCols,float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_outx[Col*numRows+Row]=
mask[0]*(d_in[(Col+0)*numRows+Row-1]-d_in[(Col-1)*numRows+Row+0])+
mask[1]*(d_in[(Col+1)*numRows+Row-2]-d_in[(Col-2)*numRows+Row+1])+
mask[2]*(d_in[(Col+2)*numRows+Row-3]-d_in[(Col-3)*numRows+Row+2])+
mask[3]*(d_in[(Col+3)*numRows+Row-4]-d_in[(Col-4)*numRows+Row+3])+
mask[4]*(d_in[(Col+4)*numRows+Row-5]-d_in[(Col-5)*numRows+Row+4])+
mask[5]*(d_in[(Col+5)*numRows+Row-6]-d_in[(Col-6)*numRows+Row+5]);
d_outz[Col*numRows+Row]=
mask[0]*(d_in[(Col+0)*numRows+Row+0]-d_in[(Col-1)*numRows+Row-1])+
mask[1]*(d_in[(Col+1)*numRows+Row+1]-d_in[(Col-2)*numRows+Row-2])+
mask[2]*(d_in[(Col+2)*numRows+Row+2]-d_in[(Col-3)*numRows+Row-3])+
mask[3]*(d_in[(Col+3)*numRows+Row+3]-d_in[(Col-4)*numRows+Row-4])+
mask[4]*(d_in[(Col+4)*numRows+Row+4]-d_in[(Col-5)*numRows+Row-5])+
mask[5]*(d_in[(Col+5)*numRows+Row+5]-d_in[(Col-6)*numRows+Row-6]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*Lx2Cuda performs the 2-D convolution of matrices A and row vector B*/
__global__ void Lx2(const float *d_in,float *d_out,int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((4<Row) && (Row<numRows-5) && (4<Col) && (Col<numCols-5)){
d_out[Col*numRows+Row]=mask[0]*d_in[Col*numRows+Row]+
mask[1]*(d_in[(Col-1)*numRows+Row]+d_in[(Col+1)*numRows+Row])+
mask[2]*(d_in[(Col-2)*numRows+Row]+d_in[(Col+2)*numRows+Row])+
mask[3]*(d_in[(Col-3)*numRows+Row]+d_in[(Col+3)*numRows+Row])+
mask[4]*(d_in[(Col-4)*numRows+Row]+d_in[(Col+4)*numRows+Row])+
mask[5]*(d_in[(Col-5)*numRows+Row]+d_in[(Col+5)*numRows+Row]);
}
}
/*Lz2 performs the 2-D convolution of matrices A and column vector B*/
__global__ void Lz2(const float *d_in,float *d_out,int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((4<Row) && (Row<numRows-5) && (4<Col) && (Col<numCols-5)){
int Loc = Col*numRows+Row;
d_out[Loc]=mask[0]*d_in[Loc]+
mask[1]*(d_in[Loc-1]+d_in[Loc+1])+
mask[2]*(d_in[Loc-2]+d_in[Loc+2])+
mask[3]*(d_in[Loc-3]+d_in[Loc+3])+
mask[4]*(d_in[Loc-4]+d_in[Loc+4])+
mask[5]*(d_in[Loc-5]+d_in[Loc+5]);
}
}
/*Lz1 performs the 2-D convolution of matrices A and column vector C1*/
__global__ void Lz1(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
int Loc = Col*numRows+Row;
d_out[Loc]=
mask[0]*(d_in[Loc+1]-d_in[Loc-1])+
mask[1]*(d_in[Loc+2]-d_in[Loc-2])+
mask[2]*(d_in[Loc+3]-d_in[Loc-3])+
mask[3]*(d_in[Loc+4]-d_in[Loc-4])+
mask[4]*(d_in[Loc+5]-d_in[Loc-5])+
mask[5]*(d_in[Loc+6]-d_in[Loc-6]);
}
}
/*Lx1 performs the 2-D convolution of matrices A and row vector C1*/
__global__ void Lx1(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_out[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
mask[1]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
mask[2]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
mask[3]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
mask[4]*(d_in[(Col+5)*numRows+Row]-d_in[(Col-5)*numRows+Row])+
mask[5]*(d_in[(Col+6)*numRows+Row]-d_in[(Col-6)*numRows+Row]);
}
}
/*sbLx performs the 2-D convolution of matrices A and row vector S1*/
__global__ void sbLx(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_out[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-0)*numRows+Row])+
mask[1]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
mask[2]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
mask[3]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
mask[4]*(d_in[(Col+5)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
mask[5]*(d_in[(Col+6)*numRows+Row]+d_in[(Col-5)*numRows+Row]);
}
}
/*sfLx performs the 2-D convolution of matrices A and row vector S1*/
__global__ void sfLx(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_out[Col*numRows+Row]=
mask[0]*(d_in[(Col+0)*numRows+Row]-d_in[(Col-1)*numRows+Row])+
mask[1]*(d_in[(Col+1)*numRows+Row]-d_in[(Col-2)*numRows+Row])+
mask[2]*(d_in[(Col+2)*numRows+Row]-d_in[(Col-3)*numRows+Row])+
mask[3]*(d_in[(Col+3)*numRows+Row]-d_in[(Col-4)*numRows+Row])+
mask[4]*(d_in[(Col+4)*numRows+Row]-d_in[(Col-5)*numRows+Row])+
mask[5]*(d_in[(Col+5)*numRows+Row]+d_in[(Col-6)*numRows+Row]);
}
}
/*sbLz performs the 2-D convolution of matrices A and column vector S1*/
__global__ void sbLz(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
int Loc = Col*numRows+Row;
d_out[Col*numRows+Row]=
mask[0]*(d_in[Loc+1]-d_in[Loc-0])+
mask[1]*(d_in[Loc+2]-d_in[Loc-1])+
mask[2]*(d_in[Loc+3]-d_in[Loc-2])+
mask[3]*(d_in[Loc+4]-d_in[Loc-3])+
mask[4]*(d_in[Loc+5]-d_in[Loc-4])+
mask[5]*(d_in[Loc+6]+d_in[Loc-5]);
}
}
/*sfLz performs the 2-D convolution of matrices A and column vector S1*/
__global__ void sfLz(const float *d_in,float *d_out, int numRows,int numCols, float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
int Loc = Col*numRows+Row;
d_out[Loc]=
mask[0]*(d_in[Loc+0]-d_in[Loc-1])+
mask[1]*(d_in[Loc+1]-d_in[Loc-2])+
mask[2]*(d_in[Loc+2]-d_in[Loc-3])+
mask[3]*(d_in[Loc+3]-d_in[Loc-4])+
mask[4]*(d_in[Loc+4]-d_in[Loc-5])+
mask[5]*(d_in[Loc+5]+d_in[Loc-6]);
}
}
/*rsgffd performs the 2-D forward rotated staggered-grid finite difference*/
__global__ void rsgffd(const float *d_in,float *d_outx,float *d_outz,const int numRows,int numCols,float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_outx[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row-0]-d_in[(Col-0)*numRows+Row+1])+
mask[1]*(d_in[(Col+2)*numRows+Row-1]-d_in[(Col-1)*numRows+Row+2])+
mask[2]*(d_in[(Col+3)*numRows+Row-2]-d_in[(Col-2)*numRows+Row+3])+
mask[3]*(d_in[(Col+4)*numRows+Row-3]-d_in[(Col-3)*numRows+Row+4])+
mask[4]*(d_in[(Col+5)*numRows+Row-4]-d_in[(Col-4)*numRows+Row+5])+
mask[5]*(d_in[(Col+6)*numRows+Row-5]-d_in[(Col-5)*numRows+Row+6]);
d_outz[Col*numRows+Row]=
mask[0]*(d_in[(Col+1)*numRows+Row+1]-d_in[(Col-0)*numRows+Row-0])+
mask[1]*(d_in[(Col+2)*numRows+Row+2]-d_in[(Col-1)*numRows+Row-1])+
mask[2]*(d_in[(Col+3)*numRows+Row+3]-d_in[(Col-2)*numRows+Row-2])+
mask[3]*(d_in[(Col+4)*numRows+Row+4]-d_in[(Col-3)*numRows+Row-3])+
mask[4]*(d_in[(Col+5)*numRows+Row+5]-d_in[(Col-4)*numRows+Row-4])+
mask[5]*(d_in[(Col+6)*numRows+Row+6]-d_in[(Col-5)*numRows+Row-5]);
}
}
/*rsgbfd performs the 2-D backward rotated staggered-grid finite difference*/
__global__ void rsgbfd(const float *d_in,float *d_outx,float *d_outz,int numRows,int numCols,float *mask)
{
//Calculate the row # of the d_in and d_out element to process
int Col = blockIdx.y*blockDim.y + threadIdx.y;
//Calculate the column # of the d_in and d_out element to process
int Row = blockIdx.x*blockDim.x + threadIdx.x;
// each thread computes one elements
if ((5<Row) && (Row<numRows-6) && (5<Col) && (Col<numCols-6)){
d_outx[Col*numRows+Row]=
mask[0]*(d_in[(Col+0)*numRows+Row-1]-d_in[(Col-1)*numRows+Row+0])+
mask[1]*(d_in[(Col+1)*numRows+Row-2]-d_in[(Col-2)*numRows+Row+1])+
mask[2]*(d_in[(Col+2)*numRows+Row-3]-d_in[(Col-3)*numRows+Row+2])+
mask[3]*(d_in[(Col+3)*numRows+Row-4]-d_in[(Col-4)*numRows+Row+3])+
mask[4]*(d_in[(Col+4)*numRows+Row-5]-d_in[(Col-5)*numRows+Row+4])+
mask[5]*(d_in[(Col+5)*numRows+Row-6]-d_in[(Col-6)*numRows+Row+5]);
d_outz[Col*numRows+Row]=
mask[0]*(d_in[(Col+0)*numRows+Row+0]-d_in[(Col-1)*numRows+Row-1])+
mask[1]*(d_in[(Col+1)*numRows+Row+1]-d_in[(Col-2)*numRows+Row-2])+
mask[2]*(d_in[(Col+2)*numRows+Row+2]-d_in[(Col-3)*numRows+Row-3])+
mask[3]*(d_in[(Col+3)*numRows+Row+3]-d_in[(Col-4)*numRows+Row-4])+
mask[4]*(d_in[(Col+4)*numRows+Row+4]-d_in[(Col-5)*numRows+Row-5])+
mask[5]*(d_in[(Col+5)*numRows+Row+5]-d_in[(Col-6)*numRows+Row-6]);
}
} | .text
.file "gfconvn.hip"
.globl _Z18__device_stub__Lx2PKfPfiiS1_ # -- Begin function _Z18__device_stub__Lx2PKfPfiiS1_
.p2align 4, 0x90
.type _Z18__device_stub__Lx2PKfPfiiS1_,@function
_Z18__device_stub__Lx2PKfPfiiS1_: # @_Z18__device_stub__Lx2PKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Lx2PKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__Lx2PKfPfiiS1_, .Lfunc_end0-_Z18__device_stub__Lx2PKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__Lz2PKfPfiiS1_ # -- Begin function _Z18__device_stub__Lz2PKfPfiiS1_
.p2align 4, 0x90
.type _Z18__device_stub__Lz2PKfPfiiS1_,@function
_Z18__device_stub__Lz2PKfPfiiS1_: # @_Z18__device_stub__Lz2PKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Lz2PKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z18__device_stub__Lz2PKfPfiiS1_, .Lfunc_end1-_Z18__device_stub__Lz2PKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__Lz1PKfPfiiS1_ # -- Begin function _Z18__device_stub__Lz1PKfPfiiS1_
.p2align 4, 0x90
.type _Z18__device_stub__Lz1PKfPfiiS1_,@function
_Z18__device_stub__Lz1PKfPfiiS1_: # @_Z18__device_stub__Lz1PKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Lz1PKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z18__device_stub__Lz1PKfPfiiS1_, .Lfunc_end2-_Z18__device_stub__Lz1PKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__Lx1PKfPfiiS1_ # -- Begin function _Z18__device_stub__Lx1PKfPfiiS1_
.p2align 4, 0x90
.type _Z18__device_stub__Lx1PKfPfiiS1_,@function
_Z18__device_stub__Lx1PKfPfiiS1_: # @_Z18__device_stub__Lx1PKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Lx1PKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z18__device_stub__Lx1PKfPfiiS1_, .Lfunc_end3-_Z18__device_stub__Lx1PKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sbLxPKfPfiiS1_ # -- Begin function _Z19__device_stub__sbLxPKfPfiiS1_
.p2align 4, 0x90
.type _Z19__device_stub__sbLxPKfPfiiS1_,@function
_Z19__device_stub__sbLxPKfPfiiS1_: # @_Z19__device_stub__sbLxPKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sbLxPKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z19__device_stub__sbLxPKfPfiiS1_, .Lfunc_end4-_Z19__device_stub__sbLxPKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sfLxPKfPfiiS1_ # -- Begin function _Z19__device_stub__sfLxPKfPfiiS1_
.p2align 4, 0x90
.type _Z19__device_stub__sfLxPKfPfiiS1_,@function
_Z19__device_stub__sfLxPKfPfiiS1_: # @_Z19__device_stub__sfLxPKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sfLxPKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z19__device_stub__sfLxPKfPfiiS1_, .Lfunc_end5-_Z19__device_stub__sfLxPKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sbLzPKfPfiiS1_ # -- Begin function _Z19__device_stub__sbLzPKfPfiiS1_
.p2align 4, 0x90
.type _Z19__device_stub__sbLzPKfPfiiS1_,@function
_Z19__device_stub__sbLzPKfPfiiS1_: # @_Z19__device_stub__sbLzPKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sbLzPKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z19__device_stub__sbLzPKfPfiiS1_, .Lfunc_end6-_Z19__device_stub__sbLzPKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sfLzPKfPfiiS1_ # -- Begin function _Z19__device_stub__sfLzPKfPfiiS1_
.p2align 4, 0x90
.type _Z19__device_stub__sfLzPKfPfiiS1_,@function
_Z19__device_stub__sfLzPKfPfiiS1_: # @_Z19__device_stub__sfLzPKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sfLzPKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end7:
.size _Z19__device_stub__sfLzPKfPfiiS1_, .Lfunc_end7-_Z19__device_stub__sfLzPKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__rsgffdPKfPfS1_iiS1_ # -- Begin function _Z21__device_stub__rsgffdPKfPfS1_iiS1_
.p2align 4, 0x90
.type _Z21__device_stub__rsgffdPKfPfS1_iiS1_,@function
_Z21__device_stub__rsgffdPKfPfS1_iiS1_: # @_Z21__device_stub__rsgffdPKfPfS1_iiS1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6rsgffdPKfPfS1_iiS1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end8:
.size _Z21__device_stub__rsgffdPKfPfS1_iiS1_, .Lfunc_end8-_Z21__device_stub__rsgffdPKfPfS1_iiS1_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__rsgbfdPKfPfS1_iiS1_ # -- Begin function _Z21__device_stub__rsgbfdPKfPfS1_iiS1_
.p2align 4, 0x90
.type _Z21__device_stub__rsgbfdPKfPfS1_iiS1_,@function
_Z21__device_stub__rsgbfdPKfPfS1_iiS1_: # @_Z21__device_stub__rsgbfdPKfPfS1_iiS1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6rsgbfdPKfPfS1_iiS1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end9:
.size _Z21__device_stub__rsgbfdPKfPfS1_iiS1_, .Lfunc_end9-_Z21__device_stub__rsgbfdPKfPfS1_iiS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3Lx2PKfPfiiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3Lz2PKfPfiiS1_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3Lz1PKfPfiiS1_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3Lx1PKfPfiiS1_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sbLxPKfPfiiS1_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sfLxPKfPfiiS1_, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sbLzPKfPfiiS1_, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sfLzPKfPfiiS1_, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6rsgffdPKfPfS1_iiS1_, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6rsgbfdPKfPfS1_iiS1_, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3Lx2PKfPfiiS1_,@object # @_Z3Lx2PKfPfiiS1_
.section .rodata,"a",@progbits
.globl _Z3Lx2PKfPfiiS1_
.p2align 3, 0x0
_Z3Lx2PKfPfiiS1_:
.quad _Z18__device_stub__Lx2PKfPfiiS1_
.size _Z3Lx2PKfPfiiS1_, 8
.type _Z3Lz2PKfPfiiS1_,@object # @_Z3Lz2PKfPfiiS1_
.globl _Z3Lz2PKfPfiiS1_
.p2align 3, 0x0
_Z3Lz2PKfPfiiS1_:
.quad _Z18__device_stub__Lz2PKfPfiiS1_
.size _Z3Lz2PKfPfiiS1_, 8
.type _Z3Lz1PKfPfiiS1_,@object # @_Z3Lz1PKfPfiiS1_
.globl _Z3Lz1PKfPfiiS1_
.p2align 3, 0x0
_Z3Lz1PKfPfiiS1_:
.quad _Z18__device_stub__Lz1PKfPfiiS1_
.size _Z3Lz1PKfPfiiS1_, 8
.type _Z3Lx1PKfPfiiS1_,@object # @_Z3Lx1PKfPfiiS1_
.globl _Z3Lx1PKfPfiiS1_
.p2align 3, 0x0
_Z3Lx1PKfPfiiS1_:
.quad _Z18__device_stub__Lx1PKfPfiiS1_
.size _Z3Lx1PKfPfiiS1_, 8
.type _Z4sbLxPKfPfiiS1_,@object # @_Z4sbLxPKfPfiiS1_
.globl _Z4sbLxPKfPfiiS1_
.p2align 3, 0x0
_Z4sbLxPKfPfiiS1_:
.quad _Z19__device_stub__sbLxPKfPfiiS1_
.size _Z4sbLxPKfPfiiS1_, 8
.type _Z4sfLxPKfPfiiS1_,@object # @_Z4sfLxPKfPfiiS1_
.globl _Z4sfLxPKfPfiiS1_
.p2align 3, 0x0
_Z4sfLxPKfPfiiS1_:
.quad _Z19__device_stub__sfLxPKfPfiiS1_
.size _Z4sfLxPKfPfiiS1_, 8
.type _Z4sbLzPKfPfiiS1_,@object # @_Z4sbLzPKfPfiiS1_
.globl _Z4sbLzPKfPfiiS1_
.p2align 3, 0x0
_Z4sbLzPKfPfiiS1_:
.quad _Z19__device_stub__sbLzPKfPfiiS1_
.size _Z4sbLzPKfPfiiS1_, 8
.type _Z4sfLzPKfPfiiS1_,@object # @_Z4sfLzPKfPfiiS1_
.globl _Z4sfLzPKfPfiiS1_
.p2align 3, 0x0
_Z4sfLzPKfPfiiS1_:
.quad _Z19__device_stub__sfLzPKfPfiiS1_
.size _Z4sfLzPKfPfiiS1_, 8
.type _Z6rsgffdPKfPfS1_iiS1_,@object # @_Z6rsgffdPKfPfS1_iiS1_
.globl _Z6rsgffdPKfPfS1_iiS1_
.p2align 3, 0x0
_Z6rsgffdPKfPfS1_iiS1_:
.quad _Z21__device_stub__rsgffdPKfPfS1_iiS1_
.size _Z6rsgffdPKfPfS1_iiS1_, 8
.type _Z6rsgbfdPKfPfS1_iiS1_,@object # @_Z6rsgbfdPKfPfS1_iiS1_
.globl _Z6rsgbfdPKfPfS1_iiS1_
.p2align 3, 0x0
_Z6rsgbfdPKfPfS1_iiS1_:
.quad _Z21__device_stub__rsgbfdPKfPfS1_iiS1_
.size _Z6rsgbfdPKfPfS1_iiS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3Lx2PKfPfiiS1_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3Lz2PKfPfiiS1_"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z3Lz1PKfPfiiS1_"
.size .L__unnamed_3, 17
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z3Lx1PKfPfiiS1_"
.size .L__unnamed_4, 17
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z4sbLxPKfPfiiS1_"
.size .L__unnamed_5, 18
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z4sfLxPKfPfiiS1_"
.size .L__unnamed_6, 18
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z4sbLzPKfPfiiS1_"
.size .L__unnamed_7, 18
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "_Z4sfLzPKfPfiiS1_"
.size .L__unnamed_8, 18
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "_Z6rsgffdPKfPfS1_iiS1_"
.size .L__unnamed_9, 23
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "_Z6rsgbfdPKfPfS1_iiS1_"
.size .L__unnamed_10, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__Lx2PKfPfiiS1_
.addrsig_sym _Z18__device_stub__Lz2PKfPfiiS1_
.addrsig_sym _Z18__device_stub__Lz1PKfPfiiS1_
.addrsig_sym _Z18__device_stub__Lx1PKfPfiiS1_
.addrsig_sym _Z19__device_stub__sbLxPKfPfiiS1_
.addrsig_sym _Z19__device_stub__sfLxPKfPfiiS1_
.addrsig_sym _Z19__device_stub__sbLzPKfPfiiS1_
.addrsig_sym _Z19__device_stub__sfLzPKfPfiiS1_
.addrsig_sym _Z21__device_stub__rsgffdPKfPfS1_iiS1_
.addrsig_sym _Z21__device_stub__rsgbfdPKfPfS1_iiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3Lx2PKfPfiiS1_
.addrsig_sym _Z3Lz2PKfPfiiS1_
.addrsig_sym _Z3Lz1PKfPfiiS1_
.addrsig_sym _Z3Lx1PKfPfiiS1_
.addrsig_sym _Z4sbLxPKfPfiiS1_
.addrsig_sym _Z4sfLxPKfPfiiS1_
.addrsig_sym _Z4sbLzPKfPfiiS1_
.addrsig_sym _Z4sfLzPKfPfiiS1_
.addrsig_sym _Z6rsgffdPKfPfS1_iiS1_
.addrsig_sym _Z6rsgbfdPKfPfS1_iiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b2be5_00000000-6_gfconvn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_
.type _Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_, @function
_Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3Lx2PKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_, .-_Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_
.globl _Z3Lx2PKfPfiiS1_
.type _Z3Lx2PKfPfiiS1_, @function
_Z3Lx2PKfPfiiS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3Lx2PKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3Lx2PKfPfiiS1_, .-_Z3Lx2PKfPfiiS1_
.globl _Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_
.type _Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_, @function
_Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3Lz2PKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_, .-_Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_
.globl _Z3Lz2PKfPfiiS1_
.type _Z3Lz2PKfPfiiS1_, @function
_Z3Lz2PKfPfiiS1_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3Lz2PKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z3Lz2PKfPfiiS1_, .-_Z3Lz2PKfPfiiS1_
.globl _Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_
.type _Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_, @function
_Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3Lz1PKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_, .-_Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_
.globl _Z3Lz1PKfPfiiS1_
.type _Z3Lz1PKfPfiiS1_, @function
_Z3Lz1PKfPfiiS1_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3Lz1PKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z3Lz1PKfPfiiS1_, .-_Z3Lz1PKfPfiiS1_
.globl _Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_
.type _Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_, @function
_Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3Lx1PKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_, .-_Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_
.globl _Z3Lx1PKfPfiiS1_
.type _Z3Lx1PKfPfiiS1_, @function
_Z3Lx1PKfPfiiS1_:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3Lx1PKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z3Lx1PKfPfiiS1_, .-_Z3Lx1PKfPfiiS1_
.globl _Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_
.type _Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_, @function
_Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_:
.LFB2059:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sbLxPKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_, .-_Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_
.globl _Z4sbLxPKfPfiiS1_
.type _Z4sbLxPKfPfiiS1_, @function
_Z4sbLxPKfPfiiS1_:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z4sbLxPKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z4sbLxPKfPfiiS1_, .-_Z4sbLxPKfPfiiS1_
.globl _Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_
.type _Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_, @function
_Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_:
.LFB2061:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sfLxPKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_, .-_Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_
.globl _Z4sfLxPKfPfiiS1_
.type _Z4sfLxPKfPfiiS1_, @function
_Z4sfLxPKfPfiiS1_:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z4sfLxPKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z4sfLxPKfPfiiS1_, .-_Z4sfLxPKfPfiiS1_
.globl _Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_
.type _Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_, @function
_Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_:
.LFB2063:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sbLzPKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_, .-_Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_
.globl _Z4sbLzPKfPfiiS1_
.type _Z4sbLzPKfPfiiS1_, @function
_Z4sbLzPKfPfiiS1_:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z4sbLzPKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z4sbLzPKfPfiiS1_, .-_Z4sbLzPKfPfiiS1_
.globl _Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_
.type _Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_, @function
_Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_:
.LFB2065:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sfLzPKfPfiiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_, .-_Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_
.globl _Z4sfLzPKfPfiiS1_
.type _Z4sfLzPKfPfiiS1_, @function
_Z4sfLzPKfPfiiS1_:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z4sfLzPKfPfiiS1_PKfPfiiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _Z4sfLzPKfPfiiS1_, .-_Z4sfLzPKfPfiiS1_
.globl _Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_
.type _Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_, @function
_Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_:
.LFB2067:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L71
.L67:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L72
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6rsgffdPKfPfS1_iiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L67
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2067:
.size _Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_, .-_Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_
.globl _Z6rsgffdPKfPfS1_iiS1_
.type _Z6rsgffdPKfPfS1_iiS1_, @function
_Z6rsgffdPKfPfS1_iiS1_:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z6rsgffdPKfPfS1_iiS1_PKfPfS1_iiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _Z6rsgffdPKfPfS1_iiS1_, .-_Z6rsgffdPKfPfS1_iiS1_
.globl _Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_
.type _Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_, @function
_Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_:
.LFB2069:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L79
.L75:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6rsgbfdPKfPfS1_iiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L75
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2069:
.size _Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_, .-_Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_
.globl _Z6rsgbfdPKfPfS1_iiS1_
.type _Z6rsgbfdPKfPfS1_iiS1_, @function
_Z6rsgbfdPKfPfS1_iiS1_:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z6rsgbfdPKfPfS1_iiS1_PKfPfS1_iiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z6rsgbfdPKfPfS1_iiS1_, .-_Z6rsgbfdPKfPfS1_iiS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6rsgbfdPKfPfS1_iiS1_"
.LC1:
.string "_Z6rsgffdPKfPfS1_iiS1_"
.LC2:
.string "_Z4sfLzPKfPfiiS1_"
.LC3:
.string "_Z4sbLzPKfPfiiS1_"
.LC4:
.string "_Z4sfLxPKfPfiiS1_"
.LC5:
.string "_Z4sbLxPKfPfiiS1_"
.LC6:
.string "_Z3Lx1PKfPfiiS1_"
.LC7:
.string "_Z3Lz1PKfPfiiS1_"
.LC8:
.string "_Z3Lz2PKfPfiiS1_"
.LC9:
.string "_Z3Lx2PKfPfiiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2072:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6rsgbfdPKfPfS1_iiS1_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6rsgffdPKfPfS1_iiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sfLzPKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sbLzPKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sfLxPKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sbLxPKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3Lx1PKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3Lz1PKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3Lz2PKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z3Lx2PKfPfiiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gfconvn.hip"
.globl _Z18__device_stub__Lx2PKfPfiiS1_ # -- Begin function _Z18__device_stub__Lx2PKfPfiiS1_
.p2align 4, 0x90
.type _Z18__device_stub__Lx2PKfPfiiS1_,@function
_Z18__device_stub__Lx2PKfPfiiS1_: # @_Z18__device_stub__Lx2PKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Lx2PKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__Lx2PKfPfiiS1_, .Lfunc_end0-_Z18__device_stub__Lx2PKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__Lz2PKfPfiiS1_ # -- Begin function _Z18__device_stub__Lz2PKfPfiiS1_
.p2align 4, 0x90
.type _Z18__device_stub__Lz2PKfPfiiS1_,@function
_Z18__device_stub__Lz2PKfPfiiS1_: # @_Z18__device_stub__Lz2PKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Lz2PKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z18__device_stub__Lz2PKfPfiiS1_, .Lfunc_end1-_Z18__device_stub__Lz2PKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__Lz1PKfPfiiS1_ # -- Begin function _Z18__device_stub__Lz1PKfPfiiS1_
.p2align 4, 0x90
.type _Z18__device_stub__Lz1PKfPfiiS1_,@function
_Z18__device_stub__Lz1PKfPfiiS1_: # @_Z18__device_stub__Lz1PKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Lz1PKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z18__device_stub__Lz1PKfPfiiS1_, .Lfunc_end2-_Z18__device_stub__Lz1PKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__Lx1PKfPfiiS1_ # -- Begin function _Z18__device_stub__Lx1PKfPfiiS1_
.p2align 4, 0x90
.type _Z18__device_stub__Lx1PKfPfiiS1_,@function
_Z18__device_stub__Lx1PKfPfiiS1_: # @_Z18__device_stub__Lx1PKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3Lx1PKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z18__device_stub__Lx1PKfPfiiS1_, .Lfunc_end3-_Z18__device_stub__Lx1PKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sbLxPKfPfiiS1_ # -- Begin function _Z19__device_stub__sbLxPKfPfiiS1_
.p2align 4, 0x90
.type _Z19__device_stub__sbLxPKfPfiiS1_,@function
_Z19__device_stub__sbLxPKfPfiiS1_: # @_Z19__device_stub__sbLxPKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sbLxPKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z19__device_stub__sbLxPKfPfiiS1_, .Lfunc_end4-_Z19__device_stub__sbLxPKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sfLxPKfPfiiS1_ # -- Begin function _Z19__device_stub__sfLxPKfPfiiS1_
.p2align 4, 0x90
.type _Z19__device_stub__sfLxPKfPfiiS1_,@function
_Z19__device_stub__sfLxPKfPfiiS1_: # @_Z19__device_stub__sfLxPKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sfLxPKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z19__device_stub__sfLxPKfPfiiS1_, .Lfunc_end5-_Z19__device_stub__sfLxPKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sbLzPKfPfiiS1_ # -- Begin function _Z19__device_stub__sbLzPKfPfiiS1_
.p2align 4, 0x90
.type _Z19__device_stub__sbLzPKfPfiiS1_,@function
_Z19__device_stub__sbLzPKfPfiiS1_: # @_Z19__device_stub__sbLzPKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sbLzPKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z19__device_stub__sbLzPKfPfiiS1_, .Lfunc_end6-_Z19__device_stub__sbLzPKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sfLzPKfPfiiS1_ # -- Begin function _Z19__device_stub__sfLzPKfPfiiS1_
.p2align 4, 0x90
.type _Z19__device_stub__sfLzPKfPfiiS1_,@function
_Z19__device_stub__sfLzPKfPfiiS1_: # @_Z19__device_stub__sfLzPKfPfiiS1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sfLzPKfPfiiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end7:
.size _Z19__device_stub__sfLzPKfPfiiS1_, .Lfunc_end7-_Z19__device_stub__sfLzPKfPfiiS1_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__rsgffdPKfPfS1_iiS1_ # -- Begin function _Z21__device_stub__rsgffdPKfPfS1_iiS1_
.p2align 4, 0x90
.type _Z21__device_stub__rsgffdPKfPfS1_iiS1_,@function
_Z21__device_stub__rsgffdPKfPfS1_iiS1_: # @_Z21__device_stub__rsgffdPKfPfS1_iiS1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6rsgffdPKfPfS1_iiS1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end8:
.size _Z21__device_stub__rsgffdPKfPfS1_iiS1_, .Lfunc_end8-_Z21__device_stub__rsgffdPKfPfS1_iiS1_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__rsgbfdPKfPfS1_iiS1_ # -- Begin function _Z21__device_stub__rsgbfdPKfPfS1_iiS1_
.p2align 4, 0x90
.type _Z21__device_stub__rsgbfdPKfPfS1_iiS1_,@function
_Z21__device_stub__rsgbfdPKfPfS1_iiS1_: # @_Z21__device_stub__rsgbfdPKfPfS1_iiS1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6rsgbfdPKfPfS1_iiS1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end9:
.size _Z21__device_stub__rsgbfdPKfPfS1_iiS1_, .Lfunc_end9-_Z21__device_stub__rsgbfdPKfPfS1_iiS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3Lx2PKfPfiiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3Lz2PKfPfiiS1_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3Lz1PKfPfiiS1_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3Lx1PKfPfiiS1_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sbLxPKfPfiiS1_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sfLxPKfPfiiS1_, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sbLzPKfPfiiS1_, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sfLzPKfPfiiS1_, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6rsgffdPKfPfS1_iiS1_, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6rsgbfdPKfPfS1_iiS1_, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3Lx2PKfPfiiS1_,@object # @_Z3Lx2PKfPfiiS1_
.section .rodata,"a",@progbits
.globl _Z3Lx2PKfPfiiS1_
.p2align 3, 0x0
_Z3Lx2PKfPfiiS1_:
.quad _Z18__device_stub__Lx2PKfPfiiS1_
.size _Z3Lx2PKfPfiiS1_, 8
.type _Z3Lz2PKfPfiiS1_,@object # @_Z3Lz2PKfPfiiS1_
.globl _Z3Lz2PKfPfiiS1_
.p2align 3, 0x0
_Z3Lz2PKfPfiiS1_:
.quad _Z18__device_stub__Lz2PKfPfiiS1_
.size _Z3Lz2PKfPfiiS1_, 8
.type _Z3Lz1PKfPfiiS1_,@object # @_Z3Lz1PKfPfiiS1_
.globl _Z3Lz1PKfPfiiS1_
.p2align 3, 0x0
_Z3Lz1PKfPfiiS1_:
.quad _Z18__device_stub__Lz1PKfPfiiS1_
.size _Z3Lz1PKfPfiiS1_, 8
.type _Z3Lx1PKfPfiiS1_,@object # @_Z3Lx1PKfPfiiS1_
.globl _Z3Lx1PKfPfiiS1_
.p2align 3, 0x0
_Z3Lx1PKfPfiiS1_:
.quad _Z18__device_stub__Lx1PKfPfiiS1_
.size _Z3Lx1PKfPfiiS1_, 8
.type _Z4sbLxPKfPfiiS1_,@object # @_Z4sbLxPKfPfiiS1_
.globl _Z4sbLxPKfPfiiS1_
.p2align 3, 0x0
_Z4sbLxPKfPfiiS1_:
.quad _Z19__device_stub__sbLxPKfPfiiS1_
.size _Z4sbLxPKfPfiiS1_, 8
.type _Z4sfLxPKfPfiiS1_,@object # @_Z4sfLxPKfPfiiS1_
.globl _Z4sfLxPKfPfiiS1_
.p2align 3, 0x0
_Z4sfLxPKfPfiiS1_:
.quad _Z19__device_stub__sfLxPKfPfiiS1_
.size _Z4sfLxPKfPfiiS1_, 8
.type _Z4sbLzPKfPfiiS1_,@object # @_Z4sbLzPKfPfiiS1_
.globl _Z4sbLzPKfPfiiS1_
.p2align 3, 0x0
_Z4sbLzPKfPfiiS1_:
.quad _Z19__device_stub__sbLzPKfPfiiS1_
.size _Z4sbLzPKfPfiiS1_, 8
.type _Z4sfLzPKfPfiiS1_,@object # @_Z4sfLzPKfPfiiS1_
.globl _Z4sfLzPKfPfiiS1_
.p2align 3, 0x0
_Z4sfLzPKfPfiiS1_:
.quad _Z19__device_stub__sfLzPKfPfiiS1_
.size _Z4sfLzPKfPfiiS1_, 8
.type _Z6rsgffdPKfPfS1_iiS1_,@object # @_Z6rsgffdPKfPfS1_iiS1_
.globl _Z6rsgffdPKfPfS1_iiS1_
.p2align 3, 0x0
_Z6rsgffdPKfPfS1_iiS1_:
.quad _Z21__device_stub__rsgffdPKfPfS1_iiS1_
.size _Z6rsgffdPKfPfS1_iiS1_, 8
.type _Z6rsgbfdPKfPfS1_iiS1_,@object # @_Z6rsgbfdPKfPfS1_iiS1_
.globl _Z6rsgbfdPKfPfS1_iiS1_
.p2align 3, 0x0
_Z6rsgbfdPKfPfS1_iiS1_:
.quad _Z21__device_stub__rsgbfdPKfPfS1_iiS1_
.size _Z6rsgbfdPKfPfS1_iiS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3Lx2PKfPfiiS1_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3Lz2PKfPfiiS1_"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z3Lz1PKfPfiiS1_"
.size .L__unnamed_3, 17
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z3Lx1PKfPfiiS1_"
.size .L__unnamed_4, 17
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z4sbLxPKfPfiiS1_"
.size .L__unnamed_5, 18
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z4sfLxPKfPfiiS1_"
.size .L__unnamed_6, 18
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z4sbLzPKfPfiiS1_"
.size .L__unnamed_7, 18
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "_Z4sfLzPKfPfiiS1_"
.size .L__unnamed_8, 18
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "_Z6rsgffdPKfPfS1_iiS1_"
.size .L__unnamed_9, 23
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "_Z6rsgbfdPKfPfS1_iiS1_"
.size .L__unnamed_10, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__Lx2PKfPfiiS1_
.addrsig_sym _Z18__device_stub__Lz2PKfPfiiS1_
.addrsig_sym _Z18__device_stub__Lz1PKfPfiiS1_
.addrsig_sym _Z18__device_stub__Lx1PKfPfiiS1_
.addrsig_sym _Z19__device_stub__sbLxPKfPfiiS1_
.addrsig_sym _Z19__device_stub__sfLxPKfPfiiS1_
.addrsig_sym _Z19__device_stub__sbLzPKfPfiiS1_
.addrsig_sym _Z19__device_stub__sfLzPKfPfiiS1_
.addrsig_sym _Z21__device_stub__rsgffdPKfPfS1_iiS1_
.addrsig_sym _Z21__device_stub__rsgbfdPKfPfS1_iiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3Lx2PKfPfiiS1_
.addrsig_sym _Z3Lz2PKfPfiiS1_
.addrsig_sym _Z3Lz1PKfPfiiS1_
.addrsig_sym _Z3Lx1PKfPfiiS1_
.addrsig_sym _Z4sbLxPKfPfiiS1_
.addrsig_sym _Z4sfLxPKfPfiiS1_
.addrsig_sym _Z4sbLzPKfPfiiS1_
.addrsig_sym _Z4sfLzPKfPfiiS1_
.addrsig_sym _Z6rsgffdPKfPfS1_iiS1_
.addrsig_sym _Z6rsgbfdPKfPfS1_iiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ void get_conflict_edge(bool *dl_matrix, short *deleted_rows, int *row_group, const int conflict_node_id, const int search_depth, int *conflict_edge, const int vertex_num, const int total_dl_matrix_row_num, const int total_dl_matrix_col_num) {
//*conflict_col_id = 0;
// int idxa = 0;
// int idxb = 0;
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
// find the conflict edge that connects current node and the most closest
// node.
if (deleted_rows[i] == -conflict_node_id) {
atomicMax(conflict_edge, i);
}
if (row_group[i] == search_depth + 1 &&
deleted_rows[i] == conflict_node_id) {
atomicMax(conflict_edge + 1, i);
}
}
}
__global__ void get_conflict_edge(int *dl_matrix, int *deleted_rows, int *deleted_cols, int *row_group, const int conflict_node_id, const int search_depth, int *conflict_edge, const int vertex_num, const int total_dl_matrix_row_num, const int total_dl_matrix_col_num) {
//*conflict_col_id = 0;
//int idxa = 0;
//int idxb = 0;
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
// find the conflict edge that connects current node and the most closest
// node.
if (deleted_rows[i] == -conflict_node_id) {
atomicMax(conflict_edge, i);
}
if (row_group[i] == search_depth + 1 &&
deleted_rows[i] == conflict_node_id) {
atomicMax(conflict_edge+1, i);
}
}
__syncthreads();
} | code for sm_80
Function : _Z17get_conflict_edgePiS_S_S_iiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x194], PT ; /* 0x0000650000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 BRA 0x330 ; /* 0x000002f000000947 */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff087624 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0090*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fca00078e0207 */
/*00c0*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*00e0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x002fe20000011400 */
/*00f0*/ UIADD3 UR4, -UR4, URZ, URZ ; /* 0x0000003f04047290 */
/* 0x000fe2000fffe13f */
/*0100*/ BSSY B0, 0x1e0 ; /* 0x000000d000007945 */
/* 0x000fea0003800000 */
/*0110*/ ISETP.NE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x004fe4000bf05270 */
/*0120*/ LEA R4, P1, R0, c[0x0][0x178], 0x2 ; /* 0x00005e0000047a11 */
/* 0x000fc800078210ff */
/*0130*/ LEA.HI.X R5, R0, c[0x0][0x17c], R5, 0x2, P1 ; /* 0x00005f0000057a11 */
/* 0x000fce00008f1405 */
/*0140*/ @P0 BRA 0x1d0 ; /* 0x0000008000000947 */
/* 0x001fea0003800000 */
/*0150*/ S2R R9, SR_LANEID ; /* 0x0000000000097919 */
/* 0x000e220000000000 */
/*0160*/ REDUX.MAX.S32 UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000e620000014200 */
/*0170*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0180*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*0190*/ ISETP.EQ.U32.AND P0, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x001fe2000bf02070 */
/*01a0*/ IMAD.U32 R9, RZ, RZ, UR5 ; /* 0x00000005ff097e24 */
/* 0x002fe2000f8e00ff */
/*01b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd60000000a00 */
/*01c0*/ @P0 RED.E.MAX.S32.STRONG.GPU [R2.64], R9 ; /* 0x000000090200098e */
/* 0x0001e4000d10e384 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*01f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0200*/ BSSY B0, 0x300 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0210*/ ISETP.NE.AND P0, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x004fda0003f05270 */
/*0220*/ @P0 BRA 0x2f0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0230*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0240*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*0250*/ ISETP.NE.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x004fda0003f05270 */
/*0260*/ @P0 BRA 0x2f0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0270*/ S2R R4, SR_LANEID ; /* 0x0000000000047919 */
/* 0x000e620000000000 */
/*0280*/ REDUX.MAX.S32 UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000ea20000014200 */
/*0290*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*02a0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*02b0*/ ISETP.EQ.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x002fe2000bf02070 */
/*02c0*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x004fe2000f8e00ff */
/*02d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd60000000a00 */
/*02e0*/ @P0 RED.E.MAX.S32.STRONG.GPU [R2.64+0x4], R5 ; /* 0x000004050200098e */
/* 0x0003e4000d10e384 */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*0310*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x194], PT ; /* 0x0000650000007a0c */
/* 0x000fda0003f06270 */
/*0320*/ @!P0 BRA 0x80 ; /* 0xfffffd5000008947 */
/* 0x000fea000383ffff */
/*0330*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ void get_conflict_edge(bool *dl_matrix, short *deleted_rows, int *row_group, const int conflict_node_id, const int search_depth, int *conflict_edge, const int vertex_num, const int total_dl_matrix_row_num, const int total_dl_matrix_col_num) {
//*conflict_col_id = 0;
// int idxa = 0;
// int idxb = 0;
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
// find the conflict edge that connects current node and the most closest
// node.
if (deleted_rows[i] == -conflict_node_id) {
atomicMax(conflict_edge, i);
}
if (row_group[i] == search_depth + 1 &&
deleted_rows[i] == conflict_node_id) {
atomicMax(conflict_edge + 1, i);
}
}
}
__global__ void get_conflict_edge(int *dl_matrix, int *deleted_rows, int *deleted_cols, int *row_group, const int conflict_node_id, const int search_depth, int *conflict_edge, const int vertex_num, const int total_dl_matrix_row_num, const int total_dl_matrix_col_num) {
//*conflict_col_id = 0;
//int idxa = 0;
//int idxb = 0;
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
// find the conflict edge that connects current node and the most closest
// node.
if (deleted_rows[i] == -conflict_node_id) {
atomicMax(conflict_edge, i);
}
if (row_group[i] == search_depth + 1 &&
deleted_rows[i] == conflict_node_id) {
atomicMax(conflict_edge+1, i);
}
}
__syncthreads();
} | .file "tmpxft_00040190_00000000-6_get_conflict_edge.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17get_conflict_edgePbPsPiiiS1_iii
.type _Z17get_conflict_edgePbPsPiiiS1_iii, @function
_Z17get_conflict_edgePbPsPiiiS1_iii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z17get_conflict_edgePbPsPiiiS1_iii, .-_Z17get_conflict_edgePbPsPiiiS1_iii
.globl _Z50__device_stub__Z17get_conflict_edgePiS_S_S_iiS_iiiPiS_S_S_iiS_iii
.type _Z50__device_stub__Z17get_conflict_edgePiS_S_S_iiS_iiiPiS_S_S_iiS_iii, @function
_Z50__device_stub__Z17get_conflict_edgePiS_S_S_iiS_iiiPiS_S_S_iiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17get_conflict_edgePiS_S_S_iiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z50__device_stub__Z17get_conflict_edgePiS_S_S_iiS_iiiPiS_S_S_iiS_iii, .-_Z50__device_stub__Z17get_conflict_edgePiS_S_S_iiS_iiiPiS_S_S_iiS_iii
.globl _Z17get_conflict_edgePiS_S_S_iiS_iii
.type _Z17get_conflict_edgePiS_S_S_iiS_iii, @function
_Z17get_conflict_edgePiS_S_S_iiS_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z17get_conflict_edgePiS_S_S_iiS_iiiPiS_S_S_iiS_iii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z17get_conflict_edgePiS_S_S_iiS_iii, .-_Z17get_conflict_edgePiS_S_S_iiS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17get_conflict_edgePiS_S_S_iiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17get_conflict_edgePiS_S_S_iiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ void get_conflict_edge(bool *dl_matrix, short *deleted_rows, int *row_group, const int conflict_node_id, const int search_depth, int *conflict_edge, const int vertex_num, const int total_dl_matrix_row_num, const int total_dl_matrix_col_num) {
//*conflict_col_id = 0;
// int idxa = 0;
// int idxb = 0;
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
// find the conflict edge that connects current node and the most closest
// node.
if (deleted_rows[i] == -conflict_node_id) {
atomicMax(conflict_edge, i);
}
if (row_group[i] == search_depth + 1 &&
deleted_rows[i] == conflict_node_id) {
atomicMax(conflict_edge + 1, i);
}
}
}
__global__ void get_conflict_edge(int *dl_matrix, int *deleted_rows, int *deleted_cols, int *row_group, const int conflict_node_id, const int search_depth, int *conflict_edge, const int vertex_num, const int total_dl_matrix_row_num, const int total_dl_matrix_col_num) {
//*conflict_col_id = 0;
//int idxa = 0;
//int idxb = 0;
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
// find the conflict edge that connects current node and the most closest
// node.
if (deleted_rows[i] == -conflict_node_id) {
atomicMax(conflict_edge, i);
}
if (row_group[i] == search_depth + 1 &&
deleted_rows[i] == conflict_node_id) {
atomicMax(conflict_edge+1, i);
}
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void get_conflict_edge(bool *dl_matrix, short *deleted_rows, int *row_group, const int conflict_node_id, const int search_depth, int *conflict_edge, const int vertex_num, const int total_dl_matrix_row_num, const int total_dl_matrix_col_num) {
//*conflict_col_id = 0;
// int idxa = 0;
// int idxb = 0;
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
// find the conflict edge that connects current node and the most closest
// node.
if (deleted_rows[i] == -conflict_node_id) {
atomicMax(conflict_edge, i);
}
if (row_group[i] == search_depth + 1 &&
deleted_rows[i] == conflict_node_id) {
atomicMax(conflict_edge + 1, i);
}
}
}
__global__ void get_conflict_edge(int *dl_matrix, int *deleted_rows, int *deleted_cols, int *row_group, const int conflict_node_id, const int search_depth, int *conflict_edge, const int vertex_num, const int total_dl_matrix_row_num, const int total_dl_matrix_col_num) {
//*conflict_col_id = 0;
//int idxa = 0;
//int idxb = 0;
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
// find the conflict edge that connects current node and the most closest
// node.
if (deleted_rows[i] == -conflict_node_id) {
atomicMax(conflict_edge, i);
}
if (row_group[i] == search_depth + 1 &&
deleted_rows[i] == conflict_node_id) {
atomicMax(conflict_edge+1, i);
}
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void get_conflict_edge(bool *dl_matrix, short *deleted_rows, int *row_group, const int conflict_node_id, const int search_depth, int *conflict_edge, const int vertex_num, const int total_dl_matrix_row_num, const int total_dl_matrix_col_num) {
//*conflict_col_id = 0;
// int idxa = 0;
// int idxb = 0;
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
// find the conflict edge that connects current node and the most closest
// node.
if (deleted_rows[i] == -conflict_node_id) {
atomicMax(conflict_edge, i);
}
if (row_group[i] == search_depth + 1 &&
deleted_rows[i] == conflict_node_id) {
atomicMax(conflict_edge + 1, i);
}
}
}
__global__ void get_conflict_edge(int *dl_matrix, int *deleted_rows, int *deleted_cols, int *row_group, const int conflict_node_id, const int search_depth, int *conflict_edge, const int vertex_num, const int total_dl_matrix_row_num, const int total_dl_matrix_col_num) {
//*conflict_col_id = 0;
//int idxa = 0;
//int idxb = 0;
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
// find the conflict edge that connects current node and the most closest
// node.
if (deleted_rows[i] == -conflict_node_id) {
atomicMax(conflict_edge, i);
}
if (row_group[i] == search_depth + 1 &&
deleted_rows[i] == conflict_node_id) {
atomicMax(conflict_edge+1, i);
}
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17get_conflict_edgePiS_S_S_iiS_iii
.globl _Z17get_conflict_edgePiS_S_S_iiS_iii
.p2align 8
.type _Z17get_conflict_edgePiS_S_S_iiS_iii,@function
_Z17get_conflict_edgePiS_S_S_iiS_iii:
s_load_b32 s8, s[0:1], 0x34
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_14
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b32 s12, s[0:1], 0x4c
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v5, 0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_sub_i32 s11, 0, s4
s_add_i32 s5, s5, 1
s_and_b32 s12, s12, 0xffff
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v0, s12, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v0
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_14
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_co_u32 v1, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v4, vcc_lo
global_load_b32 v6, v[1:2], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 s11, v6
s_cbranch_execz .LBB0_8
s_mov_b32 s15, exec_lo
s_brev_b32 s14, 1
.LBB0_5:
s_ctz_i32_b32 s16, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s17, v0, s16
s_lshl_b32 s16, 1, s16
s_and_not1_b32 s15, s15, s16
s_delay_alu instid0(VALU_DEP_1)
s_max_i32 s14, s14, s17
s_cmp_lg_u32 s15, 0
s_cbranch_scc1 .LBB0_5
v_mbcnt_lo_u32_b32 v6, exec_lo, 0
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v6
s_xor_b32 s15, exec_lo, s15
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v6, s14
global_atomic_max_i32 v5, v6, s[6:7]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s13
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s13, exec_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 s5, v3
s_cbranch_execz .LBB0_2
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s4, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
s_mov_b32 s15, exec_lo
s_brev_b32 s14, 1
.LBB0_11:
s_ctz_i32_b32 s16, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s17, v0, s16
s_lshl_b32 s16, 1, s16
s_and_not1_b32 s15, s15, s16
s_delay_alu instid0(VALU_DEP_1)
s_max_i32 s14, s14, s17
s_cmp_lg_u32 s15, 0
s_cbranch_scc1 .LBB0_11
v_mbcnt_lo_u32_b32 v1, exec_lo, 0
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_xor_b32 s15, exec_lo, s15
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v1, s14
global_atomic_max_i32 v5, v1, s[6:7] offset:4
s_branch .LBB0_2
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17get_conflict_edgePiS_S_S_iiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17get_conflict_edgePiS_S_S_iiS_iii, .Lfunc_end0-_Z17get_conflict_edgePiS_S_S_iiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17get_conflict_edgePiS_S_S_iiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z17get_conflict_edgePiS_S_S_iiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void get_conflict_edge(bool *dl_matrix, short *deleted_rows, int *row_group, const int conflict_node_id, const int search_depth, int *conflict_edge, const int vertex_num, const int total_dl_matrix_row_num, const int total_dl_matrix_col_num) {
//*conflict_col_id = 0;
// int idxa = 0;
// int idxb = 0;
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
// find the conflict edge that connects current node and the most closest
// node.
if (deleted_rows[i] == -conflict_node_id) {
atomicMax(conflict_edge, i);
}
if (row_group[i] == search_depth + 1 &&
deleted_rows[i] == conflict_node_id) {
atomicMax(conflict_edge + 1, i);
}
}
}
__global__ void get_conflict_edge(int *dl_matrix, int *deleted_rows, int *deleted_cols, int *row_group, const int conflict_node_id, const int search_depth, int *conflict_edge, const int vertex_num, const int total_dl_matrix_row_num, const int total_dl_matrix_col_num) {
//*conflict_col_id = 0;
//int idxa = 0;
//int idxb = 0;
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
// find the conflict edge that connects current node and the most closest
// node.
if (deleted_rows[i] == -conflict_node_id) {
atomicMax(conflict_edge, i);
}
if (row_group[i] == search_depth + 1 &&
deleted_rows[i] == conflict_node_id) {
atomicMax(conflict_edge+1, i);
}
}
__syncthreads();
} | .text
.file "get_conflict_edge.hip"
.globl _Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii # -- Begin function _Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii
.p2align 4, 0x90
.type _Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii,@function
_Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii: # @_Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17get_conflict_edgePiS_S_S_iiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii, .Lfunc_end0-_Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17get_conflict_edgePiS_S_S_iiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17get_conflict_edgePiS_S_S_iiS_iii,@object # @_Z17get_conflict_edgePiS_S_S_iiS_iii
.section .rodata,"a",@progbits
.globl _Z17get_conflict_edgePiS_S_S_iiS_iii
.p2align 3, 0x0
_Z17get_conflict_edgePiS_S_S_iiS_iii:
.quad _Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii
.size _Z17get_conflict_edgePiS_S_S_iiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17get_conflict_edgePiS_S_S_iiS_iii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17get_conflict_edgePiS_S_S_iiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17get_conflict_edgePiS_S_S_iiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x194], PT ; /* 0x0000650000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 BRA 0x330 ; /* 0x000002f000000947 */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff087624 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0090*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fca00078e0207 */
/*00c0*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*00e0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x002fe20000011400 */
/*00f0*/ UIADD3 UR4, -UR4, URZ, URZ ; /* 0x0000003f04047290 */
/* 0x000fe2000fffe13f */
/*0100*/ BSSY B0, 0x1e0 ; /* 0x000000d000007945 */
/* 0x000fea0003800000 */
/*0110*/ ISETP.NE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x004fe4000bf05270 */
/*0120*/ LEA R4, P1, R0, c[0x0][0x178], 0x2 ; /* 0x00005e0000047a11 */
/* 0x000fc800078210ff */
/*0130*/ LEA.HI.X R5, R0, c[0x0][0x17c], R5, 0x2, P1 ; /* 0x00005f0000057a11 */
/* 0x000fce00008f1405 */
/*0140*/ @P0 BRA 0x1d0 ; /* 0x0000008000000947 */
/* 0x001fea0003800000 */
/*0150*/ S2R R9, SR_LANEID ; /* 0x0000000000097919 */
/* 0x000e220000000000 */
/*0160*/ REDUX.MAX.S32 UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000e620000014200 */
/*0170*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0180*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*0190*/ ISETP.EQ.U32.AND P0, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x001fe2000bf02070 */
/*01a0*/ IMAD.U32 R9, RZ, RZ, UR5 ; /* 0x00000005ff097e24 */
/* 0x002fe2000f8e00ff */
/*01b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd60000000a00 */
/*01c0*/ @P0 RED.E.MAX.S32.STRONG.GPU [R2.64], R9 ; /* 0x000000090200098e */
/* 0x0001e4000d10e384 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*01f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0200*/ BSSY B0, 0x300 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0210*/ ISETP.NE.AND P0, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x004fda0003f05270 */
/*0220*/ @P0 BRA 0x2f0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0230*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0240*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*0250*/ ISETP.NE.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x004fda0003f05270 */
/*0260*/ @P0 BRA 0x2f0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0270*/ S2R R4, SR_LANEID ; /* 0x0000000000047919 */
/* 0x000e620000000000 */
/*0280*/ REDUX.MAX.S32 UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000ea20000014200 */
/*0290*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*02a0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*02b0*/ ISETP.EQ.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x002fe2000bf02070 */
/*02c0*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x004fe2000f8e00ff */
/*02d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd60000000a00 */
/*02e0*/ @P0 RED.E.MAX.S32.STRONG.GPU [R2.64+0x4], R5 ; /* 0x000004050200098e */
/* 0x0003e4000d10e384 */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*0310*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x194], PT ; /* 0x0000650000007a0c */
/* 0x000fda0003f06270 */
/*0320*/ @!P0 BRA 0x80 ; /* 0xfffffd5000008947 */
/* 0x000fea000383ffff */
/*0330*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17get_conflict_edgePiS_S_S_iiS_iii
.globl _Z17get_conflict_edgePiS_S_S_iiS_iii
.p2align 8
.type _Z17get_conflict_edgePiS_S_S_iiS_iii,@function
_Z17get_conflict_edgePiS_S_S_iiS_iii:
s_load_b32 s8, s[0:1], 0x34
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_14
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b32 s12, s[0:1], 0x4c
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v5, 0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_sub_i32 s11, 0, s4
s_add_i32 s5, s5, 1
s_and_b32 s12, s12, 0xffff
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v0, s12, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v0
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_14
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_co_u32 v1, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v4, vcc_lo
global_load_b32 v6, v[1:2], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 s11, v6
s_cbranch_execz .LBB0_8
s_mov_b32 s15, exec_lo
s_brev_b32 s14, 1
.LBB0_5:
s_ctz_i32_b32 s16, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s17, v0, s16
s_lshl_b32 s16, 1, s16
s_and_not1_b32 s15, s15, s16
s_delay_alu instid0(VALU_DEP_1)
s_max_i32 s14, s14, s17
s_cmp_lg_u32 s15, 0
s_cbranch_scc1 .LBB0_5
v_mbcnt_lo_u32_b32 v6, exec_lo, 0
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v6
s_xor_b32 s15, exec_lo, s15
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v6, s14
global_atomic_max_i32 v5, v6, s[6:7]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s13
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s13, exec_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 s5, v3
s_cbranch_execz .LBB0_2
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s4, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
s_mov_b32 s15, exec_lo
s_brev_b32 s14, 1
.LBB0_11:
s_ctz_i32_b32 s16, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s17, v0, s16
s_lshl_b32 s16, 1, s16
s_and_not1_b32 s15, s15, s16
s_delay_alu instid0(VALU_DEP_1)
s_max_i32 s14, s14, s17
s_cmp_lg_u32 s15, 0
s_cbranch_scc1 .LBB0_11
v_mbcnt_lo_u32_b32 v1, exec_lo, 0
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_xor_b32 s15, exec_lo, s15
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v1, s14
global_atomic_max_i32 v5, v1, s[6:7] offset:4
s_branch .LBB0_2
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17get_conflict_edgePiS_S_S_iiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17get_conflict_edgePiS_S_S_iiS_iii, .Lfunc_end0-_Z17get_conflict_edgePiS_S_S_iiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17get_conflict_edgePiS_S_S_iiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z17get_conflict_edgePiS_S_S_iiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00040190_00000000-6_get_conflict_edge.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17get_conflict_edgePbPsPiiiS1_iii
.type _Z17get_conflict_edgePbPsPiiiS1_iii, @function
_Z17get_conflict_edgePbPsPiiiS1_iii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z17get_conflict_edgePbPsPiiiS1_iii, .-_Z17get_conflict_edgePbPsPiiiS1_iii
.globl _Z50__device_stub__Z17get_conflict_edgePiS_S_S_iiS_iiiPiS_S_S_iiS_iii
.type _Z50__device_stub__Z17get_conflict_edgePiS_S_S_iiS_iiiPiS_S_S_iiS_iii, @function
_Z50__device_stub__Z17get_conflict_edgePiS_S_S_iiS_iiiPiS_S_S_iiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17get_conflict_edgePiS_S_S_iiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z50__device_stub__Z17get_conflict_edgePiS_S_S_iiS_iiiPiS_S_S_iiS_iii, .-_Z50__device_stub__Z17get_conflict_edgePiS_S_S_iiS_iiiPiS_S_S_iiS_iii
.globl _Z17get_conflict_edgePiS_S_S_iiS_iii
.type _Z17get_conflict_edgePiS_S_S_iiS_iii, @function
_Z17get_conflict_edgePiS_S_S_iiS_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z50__device_stub__Z17get_conflict_edgePiS_S_S_iiS_iiiPiS_S_S_iiS_iii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z17get_conflict_edgePiS_S_S_iiS_iii, .-_Z17get_conflict_edgePiS_S_S_iiS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17get_conflict_edgePiS_S_S_iiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17get_conflict_edgePiS_S_S_iiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "get_conflict_edge.hip"
.globl _Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii # -- Begin function _Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii
.p2align 4, 0x90
.type _Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii,@function
_Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii: # @_Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17get_conflict_edgePiS_S_S_iiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii, .Lfunc_end0-_Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17get_conflict_edgePiS_S_S_iiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17get_conflict_edgePiS_S_S_iiS_iii,@object # @_Z17get_conflict_edgePiS_S_S_iiS_iii
.section .rodata,"a",@progbits
.globl _Z17get_conflict_edgePiS_S_S_iiS_iii
.p2align 3, 0x0
_Z17get_conflict_edgePiS_S_S_iiS_iii:
.quad _Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii
.size _Z17get_conflict_edgePiS_S_S_iiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17get_conflict_edgePiS_S_S_iiS_iii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__get_conflict_edgePiS_S_S_iiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17get_conflict_edgePiS_S_S_iiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cmath>
#include <cstdio>
#include <iostream>
#include <chrono>
using namespace std;
// check for errors using cuda runtime api
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
// Error: GPUassert: unknown error vecadd.cu 45
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void vecAdd1(float *h_A, float* h_B, float* h_C, int n) {
for (int i = 0; i < n; i++) {
h_C[i] = h_A[i] + h_B[i];
}
}
__global__
void vecAddKernel(float* A, float* B, float* C, int n) {
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
void vecAdd2(float* A, float* B, float* C, int n) {
int size = n * sizeof(float);
float *d_A, *d_B, *d_C;
cudaMalloc(&d_A, size);
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMalloc(&d_B, size);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
cudaMalloc(&d_C, size);
vecAddKernel <<< ceil(n/256.0), 256 >>> (d_A, d_B, d_C, n);
cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost);
// gpuErrchk(cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost));
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main() {
float *h_A, *h_B, *h_C;
int n = 10;
h_A = (float*)malloc(n * sizeof(float));
h_B = (float*)malloc(n * sizeof(float));
h_C = (float*)malloc(n * sizeof(float));
for (int i = 0; i < n; i++) {
h_A[i] = 10.0;
h_B[i] = 20.0;
h_C[i] = 0.0;
}
vecAdd2(h_A, h_B, h_C, n);
for(int i = 0; i<n; i++){
printf("%f ", h_C[i]);
}
printf("\n");
free(h_A);
free(h_B);
free(h_C);
return 0;
} | code for sm_80
Function : _Z12vecAddKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cmath>
#include <cstdio>
#include <iostream>
#include <chrono>
using namespace std;
// check for errors using cuda runtime api
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
// Error: GPUassert: unknown error vecadd.cu 45
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void vecAdd1(float *h_A, float* h_B, float* h_C, int n) {
for (int i = 0; i < n; i++) {
h_C[i] = h_A[i] + h_B[i];
}
}
__global__
void vecAddKernel(float* A, float* B, float* C, int n) {
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
void vecAdd2(float* A, float* B, float* C, int n) {
int size = n * sizeof(float);
float *d_A, *d_B, *d_C;
cudaMalloc(&d_A, size);
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMalloc(&d_B, size);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
cudaMalloc(&d_C, size);
vecAddKernel <<< ceil(n/256.0), 256 >>> (d_A, d_B, d_C, n);
cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost);
// gpuErrchk(cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost));
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main() {
float *h_A, *h_B, *h_C;
int n = 10;
h_A = (float*)malloc(n * sizeof(float));
h_B = (float*)malloc(n * sizeof(float));
h_C = (float*)malloc(n * sizeof(float));
for (int i = 0; i < n; i++) {
h_A[i] = 10.0;
h_B[i] = 20.0;
h_C[i] = 0.0;
}
vecAdd2(h_A, h_B, h_C, n);
for(int i = 0; i<n; i++){
printf("%f ", h_C[i]);
}
printf("\n");
free(h_A);
free(h_B);
free(h_C);
return 0;
} | .file "tmpxft_00196ebc_00000000-6_vecadd.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7vecAdd1PfS_S_i
.type _Z7vecAdd1PfS_S_i, @function
_Z7vecAdd1PfS_S_i:
.LFB3769:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L5:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3769:
.size _Z7vecAdd1PfS_S_i, .-_Z7vecAdd1PfS_S_i
.globl _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i:
.LFB3796:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
.globl _Z12vecAddKernelPfS_S_i
.type _Z12vecAddKernelPfS_S_i, @function
_Z12vecAddKernelPfS_S_i:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z12vecAddKernelPfS_S_i, .-_Z12vecAddKernelPfS_S_i
.globl _Z7vecAdd2PfS_S_i
.type _Z7vecAdd2PfS_S_i, @function
_Z7vecAdd2PfS_S_i:
.LFB3770:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L16
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L16:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
jmp .L17
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.size _Z7vecAdd2PfS_S_i, .-_Z7vecAdd2PfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "%f "
.LC9:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3771:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
movss .LC5(%rip), %xmm1
movss .LC6(%rip), %xmm0
.L23:
movss %xmm1, 0(%r13,%rax)
movss %xmm0, (%r12,%rax)
movl $0x00000000, 0(%rbp,%rax)
addq $4, %rax
cmpq $40, %rax
jne .L23
movl $10, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z7vecAdd2PfS_S_i
movq %rbp, %rbx
leaq 40(%rbp), %r15
leaq .LC8(%rip), %r14
.L24:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L24
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3771:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z12vecAddKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1064304640
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1092616192
.align 4
.LC6:
.long 1101004800
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cmath>
#include <cstdio>
#include <iostream>
#include <chrono>
using namespace std;
// check for errors using cuda runtime api
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
// Error: GPUassert: unknown error vecadd.cu 45
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void vecAdd1(float *h_A, float* h_B, float* h_C, int n) {
for (int i = 0; i < n; i++) {
h_C[i] = h_A[i] + h_B[i];
}
}
__global__
void vecAddKernel(float* A, float* B, float* C, int n) {
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
void vecAdd2(float* A, float* B, float* C, int n) {
int size = n * sizeof(float);
float *d_A, *d_B, *d_C;
cudaMalloc(&d_A, size);
cudaMemcpy(d_A, A, size, cudaMemcpyHostToDevice);
cudaMalloc(&d_B, size);
cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice);
cudaMalloc(&d_C, size);
vecAddKernel <<< ceil(n/256.0), 256 >>> (d_A, d_B, d_C, n);
cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost);
// gpuErrchk(cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost));
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
int main() {
float *h_A, *h_B, *h_C;
int n = 10;
h_A = (float*)malloc(n * sizeof(float));
h_B = (float*)malloc(n * sizeof(float));
h_C = (float*)malloc(n * sizeof(float));
for (int i = 0; i < n; i++) {
h_A[i] = 10.0;
h_B[i] = 20.0;
h_C[i] = 0.0;
}
vecAdd2(h_A, h_B, h_C, n);
for(int i = 0; i<n; i++){
printf("%f ", h_C[i]);
}
printf("\n");
free(h_A);
free(h_B);
free(h_C);
return 0;
} | #include <hip/hip_runtime.h>
#include <cmath>
#include <cstdio>
#include <iostream>
#include <chrono>
using namespace std;
// check for errors using cuda runtime api
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
// Error: GPUassert: unknown error vecadd.cu 45
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void vecAdd1(float *h_A, float* h_B, float* h_C, int n) {
for (int i = 0; i < n; i++) {
h_C[i] = h_A[i] + h_B[i];
}
}
__global__
void vecAddKernel(float* A, float* B, float* C, int n) {
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
void vecAdd2(float* A, float* B, float* C, int n) {
int size = n * sizeof(float);
float *d_A, *d_B, *d_C;
hipMalloc(&d_A, size);
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMalloc(&d_B, size);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
hipMalloc(&d_C, size);
vecAddKernel <<< ceil(n/256.0), 256 >>> (d_A, d_B, d_C, n);
hipMemcpy(C, d_C, size, hipMemcpyDeviceToHost);
// gpuErrchk(cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost));
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main() {
float *h_A, *h_B, *h_C;
int n = 10;
h_A = (float*)malloc(n * sizeof(float));
h_B = (float*)malloc(n * sizeof(float));
h_C = (float*)malloc(n * sizeof(float));
for (int i = 0; i < n; i++) {
h_A[i] = 10.0;
h_B[i] = 20.0;
h_C[i] = 0.0;
}
vecAdd2(h_A, h_B, h_C, n);
for(int i = 0; i<n; i++){
printf("%f ", h_C[i]);
}
printf("\n");
free(h_A);
free(h_B);
free(h_C);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <cstdio>
#include <iostream>
#include <chrono>
using namespace std;
// check for errors using cuda runtime api
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
// Error: GPUassert: unknown error vecadd.cu 45
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void vecAdd1(float *h_A, float* h_B, float* h_C, int n) {
for (int i = 0; i < n; i++) {
h_C[i] = h_A[i] + h_B[i];
}
}
__global__
void vecAddKernel(float* A, float* B, float* C, int n) {
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
void vecAdd2(float* A, float* B, float* C, int n) {
int size = n * sizeof(float);
float *d_A, *d_B, *d_C;
hipMalloc(&d_A, size);
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMalloc(&d_B, size);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
hipMalloc(&d_C, size);
vecAddKernel <<< ceil(n/256.0), 256 >>> (d_A, d_B, d_C, n);
hipMemcpy(C, d_C, size, hipMemcpyDeviceToHost);
// gpuErrchk(cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost));
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main() {
float *h_A, *h_B, *h_C;
int n = 10;
h_A = (float*)malloc(n * sizeof(float));
h_B = (float*)malloc(n * sizeof(float));
h_C = (float*)malloc(n * sizeof(float));
for (int i = 0; i < n; i++) {
h_A[i] = 10.0;
h_B[i] = 20.0;
h_C[i] = 0.0;
}
vecAdd2(h_A, h_B, h_C, n);
for(int i = 0; i<n; i++){
printf("%f ", h_C[i]);
}
printf("\n");
free(h_A);
free(h_B);
free(h_C);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPfS_S_i
.globl _Z12vecAddKernelPfS_S_i
.p2align 8
.type _Z12vecAddKernelPfS_S_i,@function
_Z12vecAddKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPfS_S_i, .Lfunc_end0-_Z12vecAddKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <cstdio>
#include <iostream>
#include <chrono>
using namespace std;
// check for errors using cuda runtime api
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
// Error: GPUassert: unknown error vecadd.cu 45
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void vecAdd1(float *h_A, float* h_B, float* h_C, int n) {
for (int i = 0; i < n; i++) {
h_C[i] = h_A[i] + h_B[i];
}
}
__global__
void vecAddKernel(float* A, float* B, float* C, int n) {
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
void vecAdd2(float* A, float* B, float* C, int n) {
int size = n * sizeof(float);
float *d_A, *d_B, *d_C;
hipMalloc(&d_A, size);
hipMemcpy(d_A, A, size, hipMemcpyHostToDevice);
hipMalloc(&d_B, size);
hipMemcpy(d_B, B, size, hipMemcpyHostToDevice);
hipMalloc(&d_C, size);
vecAddKernel <<< ceil(n/256.0), 256 >>> (d_A, d_B, d_C, n);
hipMemcpy(C, d_C, size, hipMemcpyDeviceToHost);
// gpuErrchk(cudaMemcpy(C, d_C, size, cudaMemcpyDeviceToHost));
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
int main() {
float *h_A, *h_B, *h_C;
int n = 10;
h_A = (float*)malloc(n * sizeof(float));
h_B = (float*)malloc(n * sizeof(float));
h_C = (float*)malloc(n * sizeof(float));
for (int i = 0; i < n; i++) {
h_A[i] = 10.0;
h_B[i] = 20.0;
h_C[i] = 0.0;
}
vecAdd2(h_A, h_B, h_C, n);
for(int i = 0; i<n; i++){
printf("%f ", h_C[i]);
}
printf("\n");
free(h_A);
free(h_B);
free(h_C);
return 0;
} | .text
.file "vecadd.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7vecAdd1PfS_S_i # -- Begin function _Z7vecAdd1PfS_S_i
.p2align 4, 0x90
.type _Z7vecAdd1PfS_S_i,@function
_Z7vecAdd1PfS_S_i: # @_Z7vecAdd1PfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z7vecAdd1PfS_S_i, .Lfunc_end0-_Z7vecAdd1PfS_S_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__vecAddKernelPfS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPfS_S_i,@function
_Z27__device_stub__vecAddKernelPfS_S_i: # @_Z27__device_stub__vecAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__vecAddKernelPfS_S_i, .Lfunc_end1-_Z27__device_stub__vecAddKernelPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7vecAdd2PfS_S_i
.LCPI2_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z7vecAdd2PfS_S_i
.p2align 4, 0x90
.type _Z7vecAdd2PfS_S_i,@function
_Z7vecAdd2PfS_S_i: # @_Z7vecAdd2PfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
cvtsi2sd %r15d, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7vecAdd2PfS_S_i, .Lfunc_end2-_Z7vecAdd2PfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movq $0, 32(%rax)
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $1092616192, (%rbx,%rax,4) # imm = 0x41200000
movl $1101004800, (%r14,%rax,4) # imm = 0x41A00000
incq %rax
cmpq $10, %rax
jne .LBB3_1
# %bb.2:
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $10, %ecx
callq _Z7vecAdd2PfS_S_i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB3_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vecAddKernelPfS_S_i,@object # @_Z12vecAddKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPfS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPfS_S_i:
.quad _Z27__device_stub__vecAddKernelPfS_S_i
.size _Z12vecAddKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12vecAddKernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12vecAddKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPfS_S_i
.globl _Z12vecAddKernelPfS_S_i
.p2align 8
.type _Z12vecAddKernelPfS_S_i,@function
_Z12vecAddKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPfS_S_i, .Lfunc_end0-_Z12vecAddKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00196ebc_00000000-6_vecadd.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7vecAdd1PfS_S_i
.type _Z7vecAdd1PfS_S_i, @function
_Z7vecAdd1PfS_S_i:
.LFB3769:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L5:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3769:
.size _Z7vecAdd1PfS_S_i, .-_Z7vecAdd1PfS_S_i
.globl _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i:
.LFB3796:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
.globl _Z12vecAddKernelPfS_S_i
.type _Z12vecAddKernelPfS_S_i, @function
_Z12vecAddKernelPfS_S_i:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z12vecAddKernelPfS_S_i, .-_Z12vecAddKernelPfS_S_i
.globl _Z7vecAdd2PfS_S_i
.type _Z7vecAdd2PfS_S_i, @function
_Z7vecAdd2PfS_S_i:
.LFB3770:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L16
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L16:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
jmp .L17
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.size _Z7vecAdd2PfS_S_i, .-_Z7vecAdd2PfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "%f "
.LC9:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3771:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
movss .LC5(%rip), %xmm1
movss .LC6(%rip), %xmm0
.L23:
movss %xmm1, 0(%r13,%rax)
movss %xmm0, (%r12,%rax)
movl $0x00000000, 0(%rbp,%rax)
addq $4, %rax
cmpq $40, %rax
jne .L23
movl $10, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z7vecAdd2PfS_S_i
movq %rbp, %rbx
leaq 40(%rbp), %r15
leaq .LC8(%rip), %r14
.L24:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L24
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3771:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z12vecAddKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1064304640
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1092616192
.align 4
.LC6:
.long 1101004800
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecadd.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7vecAdd1PfS_S_i # -- Begin function _Z7vecAdd1PfS_S_i
.p2align 4, 0x90
.type _Z7vecAdd1PfS_S_i,@function
_Z7vecAdd1PfS_S_i: # @_Z7vecAdd1PfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z7vecAdd1PfS_S_i, .Lfunc_end0-_Z7vecAdd1PfS_S_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__vecAddKernelPfS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPfS_S_i,@function
_Z27__device_stub__vecAddKernelPfS_S_i: # @_Z27__device_stub__vecAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__vecAddKernelPfS_S_i, .Lfunc_end1-_Z27__device_stub__vecAddKernelPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7vecAdd2PfS_S_i
.LCPI2_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z7vecAdd2PfS_S_i
.p2align 4, 0x90
.type _Z7vecAdd2PfS_S_i,@function
_Z7vecAdd2PfS_S_i: # @_Z7vecAdd2PfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
cvtsi2sd %r15d, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7vecAdd2PfS_S_i, .Lfunc_end2-_Z7vecAdd2PfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movq $0, 32(%rax)
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $1092616192, (%rbx,%rax,4) # imm = 0x41200000
movl $1101004800, (%r14,%rax,4) # imm = 0x41A00000
incq %rax
cmpq $10, %rax
jne .LBB3_1
# %bb.2:
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $10, %ecx
callq _Z7vecAdd2PfS_S_i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB3_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vecAddKernelPfS_S_i,@object # @_Z12vecAddKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPfS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPfS_S_i:
.quad _Z27__device_stub__vecAddKernelPfS_S_i
.size _Z12vecAddKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12vecAddKernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
__device__ unsigned long long int gcd(unsigned long long int a, unsigned long long int b){
unsigned long long int r=0;
while(b!=0){
r = a%b;
a = b;
b = r;
}
return a;
}
__global__ void MonteCarlo(unsigned long long int n, unsigned long long int *d){
unsigned long long int dtmp = 1;
unsigned long long int a = threadIdx.x;
unsigned long long int b = threadIdx.x;
while((dtmp==1||dtmp==n) && (*d==1||*d==n)){
a = a*a+a+1;
b = b*b+b+1;
b = b*b+b+1;
dtmp = gcd(a-b,n);
}
*d=dtmp;
}
int main(int argc, char *argv[]){
if(argc<2)
exit(0);
unsigned long long int n = atoll(argv[1]);
unsigned long long int *ptrd;
unsigned long long int d = 1;
cudaMalloc((void**) &ptrd, sizeof(unsigned long long int));
cudaMemcpy(ptrd, &d, sizeof(unsigned long long int),cudaMemcpyHostToDevice);
MonteCarlo<<<1,5>>>(n,ptrd);
cudaMemcpy(&d, ptrd, sizeof(unsigned long long int),cudaMemcpyDeviceToHost);
printf("%lld\n",d);
cudaFree(ptrd);
return 0;
} | code for sm_80
Function : _Z10MonteCarloyPy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0c7624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R13, c[0x0][0x16c] ; /* 0x00005b00000d7a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0050*/ BSSY B0, 0xbf0 ; /* 0x00000b9000007945 */
/* 0x000fe20003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*0070*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0080*/ ISETP.NE.U32.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x004fc80003f05070 */
/*0090*/ ISETP.NE.AND.EX P0, PT, R15, RZ, PT, P0 ; /* 0x000000ff0f00720c */
/* 0x000fda0003f05300 */
/*00a0*/ @!P0 BRA 0x5b0 ; /* 0x0000050000008947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x001fe200000001ff */
/*00c0*/ BSSY B1, 0x5a0 ; /* 0x000004d000017945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0003 */
/*0100*/ ISETP.NE.U32.AND P0, PT, R14, c[0x0][0x160], PT ; /* 0x000058000e007a0c */
/* 0x000fc80003f05070 */
/*0110*/ ISETP.NE.AND.EX P0, PT, R15, c[0x0][0x164], PT, P0 ; /* 0x000059000f007a0c */
/* 0x000fda0003f05300 */
/*0120*/ @P0 BRA 0x590 ; /* 0x0000046000000947 */
/* 0x000fea0003800000 */
/*0130*/ MOV R2, R0.reuse ; /* 0x0000000000027202 */
/* 0x080fe20000000f00 */
/*0140*/ IMAD R5, R3, R0, RZ ; /* 0x0000000003057224 */
/* 0x000fc800078e02ff */
/*0150*/ IMAD.WIDE.U32 R8, R0, R0, R2 ; /* 0x0000000000087225 */
/* 0x000fc800078e0002 */
/*0160*/ IMAD R5, R0, R3, R5 ; /* 0x0000000300057224 */
/* 0x000fe200078e0205 */
/*0170*/ IADD3 R10, P0, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007f1e0ff */
/*0180*/ IMAD R0, R7, R4, RZ ; /* 0x0000000407007224 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD.X R11, R9, 0x1, R5, P0 ; /* 0x00000001090b7824 */
/* 0x000fe200000e0605 */
/*01a0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe20003f05070 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0007 */
/*01c0*/ IMAD.WIDE.U32 R8, R10, R10, R10 ; /* 0x0000000a0a087225 */
/* 0x000fe200078e000a */
/*01d0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fc60003f05300 */
/*01e0*/ IMAD.WIDE.U32 R2, R4, R4, R4 ; /* 0x0000000404027225 */
/* 0x000fc800078e0004 */
/*01f0*/ IMAD R5, R11, R10, RZ ; /* 0x0000000a0b057224 */
/* 0x000fe400078e02ff */
/*0200*/ IMAD R7, R4, R7, R0 ; /* 0x0000000704077224 */
/* 0x000fe200078e0200 */
/*0210*/ IADD3 R4, P2, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fe20007f5e0ff */
/*0220*/ IMAD R5, R10, R11, R5 ; /* 0x0000000b0a057224 */
/* 0x000fe200078e0205 */
/*0230*/ IADD3 R0, P1, R8, 0x1, RZ ; /* 0x0000000108007810 */
/* 0x000fe40007f3e0ff */
/*0240*/ IADD3.X R7, R3, R7, RZ, P2, !PT ; /* 0x0000000703077210 */
/* 0x000fe400017fe4ff */
/*0250*/ IADD3 R2, P3, -R0, R4, RZ ; /* 0x0000000400027210 */
/* 0x000fe20007f7e1ff */
/*0260*/ IMAD.X R3, R9, 0x1, R5, P1 ; /* 0x0000000109037824 */
/* 0x000fc800008e0605 */
/*0270*/ IMAD.X R5, R7, 0x1, ~R3, P3 ; /* 0x0000000107057824 */
/* 0x000fe200018e0e03 */
/*0280*/ @!P0 BRA 0x540 ; /* 0x000002b000008947 */
/* 0x000fea0003800000 */
/*0290*/ BSSY B2, 0x540 ; /* 0x000002a000027945 */
/* 0x000fe20003800000 */
/*02a0*/ MOV R10, c[0x0][0x160] ; /* 0x00005800000a7a02 */
/* 0x000fe20000000f00 */
/*02b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0b7624 */
/* 0x000fca00078e00ff */
/*02c0*/ LOP3.LUT R6, R5, R11.reuse, RZ, 0xfc, !PT ; /* 0x0000000b05067212 */
/* 0x080fe200078efcff */
/*02d0*/ BSSY B3, 0x4e0 ; /* 0x0000020000037945 */
/* 0x000fe20003800000 */
/*02e0*/ MOV R9, R11 ; /* 0x0000000b00097202 */
/* 0x000fe40000000f00 */
/*02f0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05070 */
/*0300*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fd800078e000a */
/*0310*/ @!P0 BRA 0x3a0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0320*/ IMAD.MOV.U32 R20, RZ, RZ, R10 ; /* 0x000000ffff147224 */
/* 0x000fe200078e000a */
/*0330*/ MOV R21, R5 ; /* 0x0000000500157202 */
/* 0x000fe20000000f00 */
/*0340*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0350*/ MOV R10, 0x370 ; /* 0x00000370000a7802 */
/* 0x000fe40000000f00 */
/*0360*/ CALL.REL.NOINC 0xc20 ; /* 0x000008b000007944 */
/* 0x000fea0003c00000 */
/*0370*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0008 */
/*0380*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0011 */
/*0390*/ BRA 0x4d0 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*03a0*/ I2F.U32.RP R5, R10 ; /* 0x0000000a00057306 */
/* 0x000e220000209000 */
/*03b0*/ ISETP.NE.U32.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fce0003f25070 */
/*03c0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*03d0*/ IADD3 R16, R5, 0xffffffe, RZ ; /* 0x0ffffffe05107810 */
/* 0x001fcc0007ffe0ff */
/*03e0*/ F2I.FTZ.U32.TRUNC.NTZ R17, R16 ; /* 0x0000001000117305 */
/* 0x000064000021f000 */
/*03f0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x001fe200078e00ff */
/*0400*/ IADD3 R11, RZ, -R17, RZ ; /* 0x80000011ff0b7210 */
/* 0x002fca0007ffe0ff */
/*0410*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*0420*/ IMAD.HI.U32 R17, R17, R11, R16 ; /* 0x0000000b11117227 */
/* 0x000fe200078e0010 */
/*0430*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fca00000001ff */
/*0440*/ IMAD.HI.U32 R17, R17, R2, RZ ; /* 0x0000000211117227 */
/* 0x000fc800078e00ff */
/*0450*/ IMAD.MOV R17, RZ, RZ, -R17 ; /* 0x000000ffff117224 */
/* 0x000fc800078e0a11 */
/*0460*/ IMAD R17, R10, R17, R2 ; /* 0x000000110a117224 */
/* 0x000fca00078e0202 */
/*0470*/ ISETP.GE.U32.AND P0, PT, R17, R10, PT ; /* 0x0000000a1100720c */
/* 0x000fda0003f06070 */
/*0480*/ @P0 IADD3 R17, R17, -R10, RZ ; /* 0x8000000a11110210 */
/* 0x000fc80007ffe0ff */
/*0490*/ ISETP.GE.U32.AND P0, PT, R17, R10, PT ; /* 0x0000000a1100720c */
/* 0x000fda0003f06070 */
/*04a0*/ @P0 IMAD.IADD R17, R17, 0x1, -R10 ; /* 0x0000000111110824 */
/* 0x000fe200078e0a0a */
/*04b0*/ @!P1 LOP3.LUT R17, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff119212 */
/* 0x000fca00078e33ff */
/*04c0*/ IMAD.MOV.U32 R10, RZ, RZ, R17 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0011 */
/*04d0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*04e0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05070 */
/*04f0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*0500*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0510*/ ISETP.NE.AND.EX P0, PT, R11, RZ, PT, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0003f05300 */
/*0520*/ @P0 BRA 0x2c0 ; /* 0xfffffd9000000947 */
/* 0x000fea000383ffff */
/*0530*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0540*/ ISETP.NE.U32.AND P0, PT, R2.reuse, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x040fe40003f05070 */
/*0550*/ ISETP.EQ.U32.AND P1, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f22070 */
/*0560*/ ISETP.NE.AND.EX P0, PT, R5, c[0x0][0x164], PT, P0 ; /* 0x0000590005007a0c */
/* 0x000fc80003f05300 */
/*0570*/ ISETP.EQ.OR.EX P0, PT, R5, RZ, !P0, P1 ; /* 0x000000ff0500720c */
/* 0x000fda0004702710 */
/*0580*/ @P0 BRA 0x100 ; /* 0xfffffb7000000947 */
/* 0x000fea000383ffff */
/*0590*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05a0*/ BRA 0xbe0 ; /* 0x0000063000007947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x001fc80003f05070 */
/*05c0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f05300 */
/*05d0*/ @!P0 BRA 0xa30 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*05e0*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fe20000000f00 */
/*05f0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0003 */
/*0600*/ MOV R2, R0.reuse ; /* 0x0000000000027202 */
/* 0x080fe20000000f00 */
/*0610*/ IMAD R5, R3, R0.reuse, RZ ; /* 0x0000000003057224 */
/* 0x080fe200078e02ff */
/*0620*/ BSSY B1, 0x9d0 ; /* 0x000003a000017945 */
/* 0x000fe60003800000 */
/*0630*/ IMAD.WIDE.U32 R8, R0, R0, R2 ; /* 0x0000000000087225 */
/* 0x000fc800078e0002 */
/*0640*/ IMAD R5, R0, R3, R5 ; /* 0x0000000300057224 */
/* 0x000fe200078e0205 */
/*0650*/ IADD3 R10, P0, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007f1e0ff */
/*0660*/ IMAD R0, R7, R4, RZ ; /* 0x0000000407007224 */
/* 0x000fc800078e02ff */
/*0670*/ IMAD.X R11, R9, 0x1, R5, P0 ; /* 0x00000001090b7824 */
/* 0x000fe200000e0605 */
/*0680*/ MOV R5, R7.reuse ; /* 0x0000000700057202 */
/* 0x080fe20000000f00 */
/*0690*/ IMAD R7, R4, R7, R0 ; /* 0x0000000704077224 */
/* 0x000fe400078e0200 */
/*06a0*/ IMAD.WIDE.U32 R8, R10, R10, R10 ; /* 0x0000000a0a087225 */
/* 0x000fc800078e000a */
/*06b0*/ IMAD.WIDE.U32 R2, R4, R4, R4 ; /* 0x0000000404027225 */
/* 0x000fe200078e0004 */
/*06c0*/ IADD3 R0, P1, R8, 0x1, RZ ; /* 0x0000000108007810 */
/* 0x000fc60007f3e0ff */
/*06d0*/ IMAD R5, R11, R10, RZ ; /* 0x0000000a0b057224 */
/* 0x000fe200078e02ff */
/*06e0*/ IADD3 R4, P0, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fc60007f1e0ff */
/*06f0*/ IMAD R5, R10, R11, R5 ; /* 0x0000000b0a057224 */
/* 0x000fe200078e0205 */
/*0700*/ IADD3 R8, P2, -R0, R4, RZ ; /* 0x0000000400087210 */
/* 0x000fe20007f5e1ff */
/*0710*/ IMAD.X R7, R3, 0x1, R7, P0 ; /* 0x0000000103077824 */
/* 0x000fe200000e0607 */
/*0720*/ MOV R11, c[0x0][0x164] ; /* 0x00005900000b7a02 */
/* 0x000fe20000000f00 */
/*0730*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0a7624 */
/* 0x000fe200078e00ff */
/*0740*/ IADD3.X R3, R9, R5, RZ, P1, !PT ; /* 0x0000000509037210 */
/* 0x000fca0000ffe4ff */
/*0750*/ IMAD.X R21, R7, 0x1, ~R3, P2 ; /* 0x0000000107157824 */
/* 0x000fca00010e0e03 */
/*0760*/ LOP3.LUT R2, R21, R11, RZ, 0xfc, !PT ; /* 0x0000000b15027212 */
/* 0x000fe200078efcff */
/*0770*/ BSSY B2, 0x970 ; /* 0x000001f000027945 */
/* 0x000fe20003800000 */
/*0780*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000b */
/*0790*/ ISETP.NE.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05070 */
/*07a0*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fd60000000f00 */
/*07b0*/ @!P0 BRA 0x830 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*07c0*/ MOV R20, R2 ; /* 0x0000000200147202 */
/* 0x000fe20000000f00 */
/*07d0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0005 */
/*07e0*/ MOV R10, 0x800 ; /* 0x00000800000a7802 */
/* 0x000fe40000000f00 */
/*07f0*/ CALL.REL.NOINC 0xc20 ; /* 0x0000042000007944 */
/* 0x000fea0003c00000 */
/*0800*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fe20000000f00 */
/*0810*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0011 */
/*0820*/ BRA 0x960 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0830*/ I2F.U32.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000e220000209000 */
/*0840*/ ISETP.NE.U32.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f25070 */
/*0850*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0860*/ IADD3 R10, R6, 0xffffffe, RZ ; /* 0x0ffffffe060a7810 */
/* 0x001fcc0007ffe0ff */
/*0870*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x000064000021f000 */
/*0880*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fe200078e00ff */
/*0890*/ IADD3 R9, RZ, -R11, RZ ; /* 0x8000000bff097210 */
/* 0x002fca0007ffe0ff */
/*08a0*/ IMAD R9, R9, R2, RZ ; /* 0x0000000209097224 */
/* 0x000fc800078e02ff */
/*08b0*/ IMAD.HI.U32 R11, R11, R9, R10 ; /* 0x000000090b0b7227 */
/* 0x000fcc00078e000a */
/*08c0*/ IMAD.HI.U32 R11, R11, R8, RZ ; /* 0x000000080b0b7227 */
/* 0x000fca00078e00ff */
/*08d0*/ IADD3 R11, -R11, RZ, RZ ; /* 0x000000ff0b0b7210 */
/* 0x000fca0007ffe1ff */
/*08e0*/ IMAD R9, R2, R11, R8 ; /* 0x0000000b02097224 */
/* 0x000fe200078e0208 */
/*08f0*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fc800000001ff */
/*0900*/ ISETP.GE.U32.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f06070 */
/*0910*/ @P0 IMAD.IADD R9, R9, 0x1, -R2 ; /* 0x0000000109090824 */
/* 0x000fca00078e0a02 */
/*0920*/ ISETP.GE.U32.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f06070 */
/*0930*/ @P0 IADD3 R9, R9, -R2.reuse, RZ ; /* 0x8000000209090210 */
/* 0x080fe40007ffe0ff */
/*0940*/ @!P1 LOP3.LUT R9, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff099212 */
/* 0x000fca00078e33ff */
/*0950*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0009 */
/*0960*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0970*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05070 */
/*0980*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0990*/ MOV R21, R5 ; /* 0x0000000500157202 */
/* 0x000fe40000000f00 */
/*09a0*/ ISETP.NE.AND.EX P0, PT, R11, RZ, PT, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0003f05300 */
/*09b0*/ @P0 BRA 0x760 ; /* 0xfffffda000000947 */
/* 0x000fea000383ffff */
/*09c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09d0*/ ISETP.NE.U32.AND P0, PT, R2.reuse, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x040fe40003f05070 */
/*09e0*/ ISETP.EQ.U32.AND P1, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f22070 */
/*09f0*/ ISETP.NE.AND.EX P0, PT, R5, c[0x0][0x164], PT, P0 ; /* 0x0000590005007a0c */
/* 0x000fc80003f05300 */
/*0a00*/ ISETP.EQ.OR.EX P0, PT, R5, RZ, !P0, P1 ; /* 0x000000ff0500720c */
/* 0x000fda0004702710 */
/*0a10*/ @P0 BRA 0x600 ; /* 0xfffffbe000000947 */
/* 0x000fea000383ffff */
/*0a20*/ BRA 0xbe0 ; /* 0x000001b000007947 */
/* 0x000fea0003800000 */
/*0a30*/ BSSY B1, 0xbe0 ; /* 0x000001a000017945 */
/* 0x000fe20003800000 */
/*0a40*/ IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0000 */
/*0a50*/ MOV R8, R3 ; /* 0x0000000300087202 */
/* 0x000fe40000000f00 */
/*0a60*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0a70*/ IMAD R6, R3, R0.reuse, RZ ; /* 0x0000000003067224 */
/* 0x080fe400078e02ff */
/*0a80*/ IMAD.WIDE.U32 R4, R0, R0, R2 ; /* 0x0000000000047225 */
/* 0x000fc800078e0002 */
/*0a90*/ IMAD R3, R0, R3, R6 ; /* 0x0000000300037224 */
/* 0x000fe200078e0206 */
/*0aa0*/ IADD3 R4, P0, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe20007f1e0ff */
/*0ab0*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0009 */
/*0ac0*/ IMAD R0, R8, R9, RZ ; /* 0x0000000908007224 */
/* 0x000fe200078e02ff */
/*0ad0*/ IADD3.X R5, R5, R3, RZ, P0, !PT ; /* 0x0000000305057210 */
/* 0x000fe400007fe4ff */
/*0ae0*/ MOV R3, R8.reuse ; /* 0x0000000800037202 */
/* 0x080fe20000000f00 */
/*0af0*/ IMAD R11, R9, R8, R0 ; /* 0x00000008090b7224 */
/* 0x000fe400078e0200 */
/*0b00*/ IMAD R15, R5, R4, RZ ; /* 0x00000004050f7224 */
/* 0x000fc400078e02ff */
/*0b10*/ IMAD.WIDE.U32 R2, R9, R9, R2 ; /* 0x0000000909027225 */
/* 0x000fc800078e0002 */
/*0b20*/ IMAD.WIDE.U32 R6, R4, R4, R4 ; /* 0x0000000404067225 */
/* 0x000fe200078e0004 */
/*0b30*/ IADD3 R9, P0, R2, 0x1, RZ ; /* 0x0000000102097810 */
/* 0x000fc60007f1e0ff */
/*0b40*/ IMAD R15, R4, R5, R15 ; /* 0x00000005040f7224 */
/* 0x000fe200078e020f */
/*0b50*/ IADD3 R0, P2, R6, 0x1, RZ ; /* 0x0000000106007810 */
/* 0x000fe20007f5e0ff */
/*0b60*/ IMAD.X R8, R3, 0x1, R11, P0 ; /* 0x0000000103087824 */
/* 0x000fc600000e060b */
/*0b70*/ IADD3 R2, P1, R9, -R0, RZ ; /* 0x8000000009027210 */
/* 0x000fe40007f3e0ff */
/*0b80*/ IADD3.X R3, R7, R15, RZ, P2, !PT ; /* 0x0000000f07037210 */
/* 0x000fe400017fe4ff */
/*0b90*/ ISETP.GE.U32.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fc60003f06070 */
/*0ba0*/ IMAD.X R5, R8, 0x1, ~R3, P1 ; /* 0x0000000108057824 */
/* 0x000fca00008e0e03 */
/*0bb0*/ ISETP.GE.U32.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0003f06100 */
/*0bc0*/ @!P0 BRA 0xa60 ; /* 0xfffffe9000008947 */
/* 0x000fea000383ffff */
/*0bd0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0be0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0bf0*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x000fca0000000f00 */
/*0c00*/ STG.E.64 [R12.64], R2 ; /* 0x000000020c007986 */
/* 0x000fe2000c101b04 */
/*0c10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c20*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x000fe200078e0014 */
/*0c30*/ MOV R23, R11 ; /* 0x0000000b00177202 */
/* 0x000fca0000000f00 */
/*0c40*/ I2F.U64.RP R22, R22 ; /* 0x0000001600167312 */
/* 0x000e300000309000 */
/*0c50*/ MUFU.RCP R16, R22 ; /* 0x0000001600107308 */
/* 0x001e240000001000 */
/*0c60*/ IADD3 R16, R16, 0x1ffffffe, RZ ; /* 0x1ffffffe10107810 */
/* 0x001fcc0007ffe0ff */
/*0c70*/ F2I.U64.TRUNC R16, R16 ; /* 0x0000001000107311 */
/* 0x000e24000020d800 */
/*0c80*/ IMAD.WIDE.U32 R18, R16, R20, RZ ; /* 0x0000001410127225 */
/* 0x001fc800078e00ff */
/*0c90*/ IMAD R19, R16, R11, R19 ; /* 0x0000000b10137224 */
/* 0x000fe200078e0213 */
/*0ca0*/ IADD3 R25, P0, RZ, -R18, RZ ; /* 0x80000012ff197210 */
/* 0x000fc60007f1e0ff */
/*0cb0*/ IMAD R19, R17, R20, R19 ; /* 0x0000001411137224 */
/* 0x000fe400078e0213 */
/*0cc0*/ IMAD.HI.U32 R18, R16, R25, RZ ; /* 0x0000001910127227 */
/* 0x000fc800078e00ff */
/*0cd0*/ IMAD.X R27, RZ, RZ, ~R19, P0 ; /* 0x000000ffff1b7224 */
/* 0x000fe200000e0e13 */
/*0ce0*/ MOV R19, R16 ; /* 0x0000001000137202 */
/* 0x000fc60000000f00 */
/*0cf0*/ IMAD R29, R17, R27.reuse, RZ ; /* 0x0000001b111d7224 */
/* 0x080fe400078e02ff */
/*0d00*/ IMAD.WIDE.U32 R18, P0, R16, R27, R18 ; /* 0x0000001b10127225 */
/* 0x000fc80007800012 */
/*0d10*/ IMAD.HI.U32 R23, R17, R27, RZ ; /* 0x0000001b11177227 */
/* 0x000fc800078e00ff */
/*0d20*/ IMAD.HI.U32 R18, P1, R17, R25, R18 ; /* 0x0000001911127227 */
/* 0x000fc80007820012 */
/*0d30*/ IMAD.X R23, R23, 0x1, R17, P0 ; /* 0x0000000117177824 */
/* 0x000fe200000e0611 */
/*0d40*/ IADD3 R19, P2, R29, R18, RZ ; /* 0x000000121d137210 */
/* 0x000fc80007f5e0ff */
/*0d50*/ IADD3.X R23, RZ, RZ, R23, P2, P1 ; /* 0x000000ffff177210 */
/* 0x000fe200017e2417 */
/*0d60*/ IMAD.WIDE.U32 R16, R19, R20, RZ ; /* 0x0000001413107225 */
/* 0x000fc800078e00ff */
/*0d70*/ IMAD R17, R19, R11, R17 ; /* 0x0000000b13117224 */
/* 0x000fe200078e0211 */
/*0d80*/ IADD3 R25, P0, RZ, -R16, RZ ; /* 0x80000010ff197210 */
/* 0x000fc60007f1e0ff */
/*0d90*/ IMAD R17, R23, R20, R17 ; /* 0x0000001417117224 */
/* 0x000fe400078e0211 */
/*0da0*/ IMAD.HI.U32 R18, R19, R25, RZ ; /* 0x0000001913127227 */
/* 0x000fc600078e00ff */
/*0db0*/ IADD3.X R16, RZ, ~R17, RZ, P0, !PT ; /* 0x80000011ff107210 */
/* 0x000fe200007fe4ff */
/*0dc0*/ HFMA2.MMA R17, -RZ, RZ, 0, 0 ; /* 0x00000000ff117435 */
/* 0x000fc800000001ff */
/*0dd0*/ IMAD.WIDE.U32 R18, P0, R19, R16, R18 ; /* 0x0000001013127225 */
/* 0x000fc80007800012 */
/*0de0*/ IMAD R22, R23.reuse, R16, RZ ; /* 0x0000001017167224 */
/* 0x040fe400078e02ff */
/*0df0*/ IMAD.HI.U32 R19, P1, R23, R25, R18 ; /* 0x0000001917137227 */
/* 0x000fc80007820012 */
/*0e00*/ IMAD.HI.U32 R16, R23, R16, RZ ; /* 0x0000001017107227 */
/* 0x000fe200078e00ff */
/*0e10*/ IADD3 R19, P2, R22, R19, RZ ; /* 0x0000001316137210 */
/* 0x000fc60007f5e0ff */
/*0e20*/ IMAD.X R23, R16, 0x1, R23, P0 ; /* 0x0000000110177824 */
/* 0x000fe400000e0617 */
/*0e30*/ IMAD.HI.U32 R16, R19, R8, RZ ; /* 0x0000000813107227 */
/* 0x000fc600078e00ff */
/*0e40*/ IADD3.X R23, RZ, RZ, R23, P2, P1 ; /* 0x000000ffff177210 */
/* 0x000fc600017e2417 */
/*0e50*/ IMAD.WIDE.U32 R16, R19, R21, R16 ; /* 0x0000001513107225 */
/* 0x000fc800078e0010 */
/*0e60*/ IMAD R19, R23.reuse, R21, RZ ; /* 0x0000001517137224 */
/* 0x040fe400078e02ff */
/*0e70*/ IMAD.HI.U32 R16, P0, R23, R8, R16 ; /* 0x0000000817107227 */
/* 0x000fc80007800010 */
/*0e80*/ IMAD.HI.U32 R18, R23, R21, RZ ; /* 0x0000001517127227 */
/* 0x000fe200078e00ff */
/*0e90*/ IADD3 R19, P1, R19, R16, RZ ; /* 0x0000001013137210 */
/* 0x000fc60007f3e0ff */
/*0ea0*/ IMAD.X R18, RZ, RZ, R18, P0 ; /* 0x000000ffff127224 */
/* 0x000fe400000e0612 */
/*0eb0*/ IMAD.WIDE.U32 R16, R19, R20, RZ ; /* 0x0000001413107225 */
/* 0x000fc600078e00ff */
/*0ec0*/ IADD3.X R23, RZ, R18, RZ, P1, !PT ; /* 0x00000012ff177210 */
/* 0x000fe20000ffe4ff */
/*0ed0*/ IMAD R19, R19, R11, R17 ; /* 0x0000000b13137224 */
/* 0x000fe200078e0211 */
/*0ee0*/ IADD3 R17, P1, -R16, R8, RZ ; /* 0x0000000810117210 */
/* 0x000fc60007f3e1ff */
/*0ef0*/ IMAD R8, R23, R20.reuse, R19 ; /* 0x0000001417087224 */
/* 0x080fe200078e0213 */
/*0f00*/ ISETP.GE.U32.AND P0, PT, R17, R20, PT ; /* 0x000000141100720c */
/* 0x000fc60003f06070 */
/*0f10*/ IMAD.X R8, R21, 0x1, ~R8, P1 ; /* 0x0000000115087824 */
/* 0x000fe200008e0e08 */
/*0f20*/ IADD3 R19, P1, -R20, R17, RZ ; /* 0x0000001114137210 */
/* 0x000fc80007f3e1ff */
/*0f30*/ ISETP.GE.U32.AND.EX P0, PT, R8, R11, PT, P0 ; /* 0x0000000b0800720c */
/* 0x000fe40003f06100 */
/*0f40*/ IADD3.X R16, ~R11, R8.reuse, RZ, P1, !PT ; /* 0x000000080b107210 */
/* 0x080fe40000ffe5ff */
/*0f50*/ SEL R19, R19, R17, P0 ; /* 0x0000001113137207 */
/* 0x000fe40000000000 */
/*0f60*/ SEL R16, R16, R8, P0 ; /* 0x0000000810107207 */
/* 0x000fe40000000000 */
/*0f70*/ IADD3 R8, P2, -R20, R19, RZ ; /* 0x0000001314087210 */
/* 0x000fe40007f5e1ff */
/*0f80*/ ISETP.GE.U32.AND P0, PT, R19, R20, PT ; /* 0x000000141300720c */
/* 0x000fc40003f06070 */
/*0f90*/ ISETP.NE.U32.AND P1, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f25070 */
/*0fa0*/ IMAD.X R17, R16.reuse, 0x1, ~R11, P2 ; /* 0x0000000110117824 */
/* 0x040fe200010e0e0b */
/*0fb0*/ ISETP.GE.U32.AND.EX P0, PT, R16, R11, PT, P0 ; /* 0x0000000b1000720c */
/* 0x000fe40003f06100 */
/*0fc0*/ ISETP.NE.AND.EX P1, PT, R11, RZ, PT, P1 ; /* 0x000000ff0b00720c */
/* 0x000fe40003f25310 */
/*0fd0*/ MOV R11, 0x0 ; /* 0x00000000000b7802 */
/* 0x000fe40000000f00 */
/*0fe0*/ SEL R8, R8, R19, P0 ; /* 0x0000001308087207 */
/* 0x000fe40000000000 */
/*0ff0*/ SEL R17, R17, R16, P0 ; /* 0x0000001011117207 */
/* 0x000fc40000000000 */
/*1000*/ SEL R8, R8, 0xffffffff, P1 ; /* 0xffffffff08087807 */
/* 0x000fe40000800000 */
/*1010*/ SEL R17, R17, 0xffffffff, P1 ; /* 0xffffffff11117807 */
/* 0x000fe20000800000 */
/*1020*/ RET.REL.NODEC R10 0x0 ; /* 0xffffefd00a007950 */
/* 0x000fec0003c3ffff */
/*1030*/ BRA 0x1030; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
__device__ unsigned long long int gcd(unsigned long long int a, unsigned long long int b){
unsigned long long int r=0;
while(b!=0){
r = a%b;
a = b;
b = r;
}
return a;
}
__global__ void MonteCarlo(unsigned long long int n, unsigned long long int *d){
unsigned long long int dtmp = 1;
unsigned long long int a = threadIdx.x;
unsigned long long int b = threadIdx.x;
while((dtmp==1||dtmp==n) && (*d==1||*d==n)){
a = a*a+a+1;
b = b*b+b+1;
b = b*b+b+1;
dtmp = gcd(a-b,n);
}
*d=dtmp;
}
int main(int argc, char *argv[]){
if(argc<2)
exit(0);
unsigned long long int n = atoll(argv[1]);
unsigned long long int *ptrd;
unsigned long long int d = 1;
cudaMalloc((void**) &ptrd, sizeof(unsigned long long int));
cudaMemcpy(ptrd, &d, sizeof(unsigned long long int),cudaMemcpyHostToDevice);
MonteCarlo<<<1,5>>>(n,ptrd);
cudaMemcpy(&d, ptrd, sizeof(unsigned long long int),cudaMemcpyDeviceToHost);
printf("%lld\n",d);
cudaFree(ptrd);
return 0;
} | .file "tmpxft_00071306_00000000-6_MonteCarlo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3gcdyy
.type _Z3gcdyy, @function
_Z3gcdyy:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z3gcdyy, .-_Z3gcdyy
.globl _Z31__device_stub__Z10MonteCarloyPyyPy
.type _Z31__device_stub__Z10MonteCarloyPyyPy, @function
_Z31__device_stub__Z10MonteCarloyPyyPy:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10MonteCarloyPy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z10MonteCarloyPyyPy, .-_Z31__device_stub__Z10MonteCarloyPyyPy
.globl _Z10MonteCarloyPy
.type _Z10MonteCarloyPy, @function
_Z10MonteCarloyPy:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10MonteCarloyPyyPy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10MonteCarloyPy, .-_Z10MonteCarloyPy
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%lld\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L18
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtoll@PLT
movq %rax, %rbx
movq $1, 8(%rsp)
movq %rsp, %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
leaq 8(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl $0, %edi
call exit@PLT
.L19:
movq (%rsp), %rsi
movq %rbx, %rdi
call _Z31__device_stub__Z10MonteCarloyPyyPy
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10MonteCarloyPy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10MonteCarloyPy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
__device__ unsigned long long int gcd(unsigned long long int a, unsigned long long int b){
unsigned long long int r=0;
while(b!=0){
r = a%b;
a = b;
b = r;
}
return a;
}
__global__ void MonteCarlo(unsigned long long int n, unsigned long long int *d){
unsigned long long int dtmp = 1;
unsigned long long int a = threadIdx.x;
unsigned long long int b = threadIdx.x;
while((dtmp==1||dtmp==n) && (*d==1||*d==n)){
a = a*a+a+1;
b = b*b+b+1;
b = b*b+b+1;
dtmp = gcd(a-b,n);
}
*d=dtmp;
}
int main(int argc, char *argv[]){
if(argc<2)
exit(0);
unsigned long long int n = atoll(argv[1]);
unsigned long long int *ptrd;
unsigned long long int d = 1;
cudaMalloc((void**) &ptrd, sizeof(unsigned long long int));
cudaMemcpy(ptrd, &d, sizeof(unsigned long long int),cudaMemcpyHostToDevice);
MonteCarlo<<<1,5>>>(n,ptrd);
cudaMemcpy(&d, ptrd, sizeof(unsigned long long int),cudaMemcpyDeviceToHost);
printf("%lld\n",d);
cudaFree(ptrd);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
__device__ unsigned long long int gcd(unsigned long long int a, unsigned long long int b){
unsigned long long int r=0;
while(b!=0){
r = a%b;
a = b;
b = r;
}
return a;
}
__global__ void MonteCarlo(unsigned long long int n, unsigned long long int *d){
unsigned long long int dtmp = 1;
unsigned long long int a = threadIdx.x;
unsigned long long int b = threadIdx.x;
while((dtmp==1||dtmp==n) && (*d==1||*d==n)){
a = a*a+a+1;
b = b*b+b+1;
b = b*b+b+1;
dtmp = gcd(a-b,n);
}
*d=dtmp;
}
int main(int argc, char *argv[]){
if(argc<2)
exit(0);
unsigned long long int n = atoll(argv[1]);
unsigned long long int *ptrd;
unsigned long long int d = 1;
hipMalloc((void**) &ptrd, sizeof(unsigned long long int));
hipMemcpy(ptrd, &d, sizeof(unsigned long long int),hipMemcpyHostToDevice);
MonteCarlo<<<1,5>>>(n,ptrd);
hipMemcpy(&d, ptrd, sizeof(unsigned long long int),hipMemcpyDeviceToHost);
printf("%lld\n",d);
hipFree(ptrd);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
__device__ unsigned long long int gcd(unsigned long long int a, unsigned long long int b){
unsigned long long int r=0;
while(b!=0){
r = a%b;
a = b;
b = r;
}
return a;
}
__global__ void MonteCarlo(unsigned long long int n, unsigned long long int *d){
unsigned long long int dtmp = 1;
unsigned long long int a = threadIdx.x;
unsigned long long int b = threadIdx.x;
while((dtmp==1||dtmp==n) && (*d==1||*d==n)){
a = a*a+a+1;
b = b*b+b+1;
b = b*b+b+1;
dtmp = gcd(a-b,n);
}
*d=dtmp;
}
int main(int argc, char *argv[]){
if(argc<2)
exit(0);
unsigned long long int n = atoll(argv[1]);
unsigned long long int *ptrd;
unsigned long long int d = 1;
hipMalloc((void**) &ptrd, sizeof(unsigned long long int));
hipMemcpy(ptrd, &d, sizeof(unsigned long long int),hipMemcpyHostToDevice);
MonteCarlo<<<1,5>>>(n,ptrd);
hipMemcpy(&d, ptrd, sizeof(unsigned long long int),hipMemcpyDeviceToHost);
printf("%lld\n",d);
hipFree(ptrd);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10MonteCarloyPy
.globl _Z10MonteCarloyPy
.p2align 8
.type _Z10MonteCarloyPy,@function
_Z10MonteCarloyPy:
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, v2
v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
s_waitcnt lgkmcnt(0)
s_load_b64 s[0:1], s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[0:1], 1
s_cselect_b32 s2, -1, 0
s_cmp_eq_u64 s[0:1], s[4:5]
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s0
s_cmp_lg_u64 s[4:5], 0
s_cselect_b32 s3, -1, 0
s_branch .LBB0_3
.LBB0_1:
v_mov_b32_e32 v4, 1
v_mov_b32_e32 v5, 0
.LBB0_2:
s_and_b32 s1, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s8, s1, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_12
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s2
s_or_b32 s0, s0, exec_lo
s_cbranch_vccnz .LBB0_1
v_mul_lo_u32 v5, v0, v1
v_mad_u64_u32 v[3:4], null, v0, v0, v[0:1]
v_mul_lo_u32 v10, v8, v9
v_mad_u64_u32 v[6:7], null, v8, v8, v[8:9]
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add3_u32 v0, v5, v4, v5
v_add_co_u32 v4, vcc_lo, v3, 2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add3_u32 v7, v10, v7, v10
v_dual_mov_b32 v11, s5 :: v_dual_mov_b32 v10, s4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v8, v4, v0
v_mad_u64_u32 v[0:1], null, v4, v3, v[4:5]
v_mul_lo_u32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v1, v3, v1, v8
v_sub_co_u32 v8, vcc_lo, v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_ci_u32_e32 v9, vcc_lo, v7, v1, vcc_lo
v_mov_b32_e32 v4, v8
s_and_not1_b32 vcc_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v5, v9
s_cbranch_vccz .LBB0_6
s_branch .LBB0_11
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
v_dual_mov_b32 v9, v5 :: v_dual_mov_b32 v8, v4
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_10
.LBB0_6:
v_dual_mov_b32 v4, v10 :: v_dual_mov_b32 v5, v11
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v3, v9, v5
v_cmpx_ne_u64_e32 0, v[2:3]
s_xor_b32 s9, exec_lo, s0
s_cbranch_execz .LBB0_8
v_cvt_f32_u32_e32 v3, v4
v_cvt_f32_u32_e32 v10, v5
v_sub_co_u32 v17, vcc_lo, 0, v4
v_sub_co_ci_u32_e32 v18, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, 0x4f800000, v10
v_rcp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x5f7ffffc, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, 0x2f800000, v3
v_trunc_f32_e32 v10, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v3, 0xcf800000, v10
v_cvt_u32_f32_e32 v19, v10
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v12, v17, v19
v_mul_lo_u32 v13, v18, v3
v_mad_u64_u32 v[10:11], null, v17, v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v20, v11, v12, v13
v_mul_hi_u32 v21, v3, v10
v_mad_u64_u32 v[13:14], null, v19, v10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v3, v20, 0
v_mad_u64_u32 v[15:16], null, v19, v20, 0
v_add_co_u32 v10, vcc_lo, v21, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
v_add_co_u32 v10, vcc_lo, v10, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, v11, v14, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v16, vcc_lo
v_add_co_u32 v10, vcc_lo, v10, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v11, vcc_lo
v_mul_lo_u32 v12, v18, v3
v_mad_u64_u32 v[10:11], null, v17, v3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v13, v17, v19
v_mul_hi_u32 v18, v3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v17, v11, v13, v12
v_mad_u64_u32 v[13:14], null, v19, v10, 0
v_mad_u64_u32 v[11:12], null, v3, v17, 0
v_mad_u64_u32 v[15:16], null, v19, v17, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v10, vcc_lo, v18, v11
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v10, v13
v_add_co_ci_u32_e32 v10, vcc_lo, v11, v14, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v10, v15
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, v10
v_add_co_ci_u32_e32 v16, vcc_lo, v19, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v17, v8, v3
v_mad_u64_u32 v[12:13], null, v9, v3, 0
v_mad_u64_u32 v[10:11], null, v8, v16, 0
v_mad_u64_u32 v[14:15], null, v9, v16, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, v17, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, v12
v_add_co_ci_u32_e32 v3, vcc_lo, v10, v13, vcc_lo
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v3, v14
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v13, v5, v3
v_mad_u64_u32 v[10:11], null, v4, v3, 0
v_mul_lo_u32 v3, v4, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v8, vcc_lo, v8, v10
v_add3_u32 v3, v11, v3, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v11, v9, v3
v_sub_co_ci_u32_e64 v10, s0, v11, v5, vcc_lo
v_sub_co_ci_u32_e32 v3, vcc_lo, v9, v3, vcc_lo
v_sub_co_u32 v9, vcc_lo, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v11, s0, 0, v10, vcc_lo
v_cmp_ge_u32_e64 s0, v8, v4
v_sub_co_ci_u32_e32 v10, vcc_lo, v10, v5, vcc_lo
v_cmp_ge_u32_e32 vcc_lo, v3, v5
v_cndmask_b32_e64 v12, 0, -1, s0
v_cmp_ge_u32_e64 s0, v9, v4
v_cndmask_b32_e64 v15, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, v11, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v13, 0, -1, s0
v_cmp_ge_u32_e64 s0, v11, v5
v_cndmask_b32_e64 v14, 0, -1, s0
v_cmp_eq_u32_e64 s0, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v13, v14, v13, vcc_lo
v_sub_co_u32 v14, vcc_lo, v9, v4
v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v13
v_cndmask_b32_e64 v12, v15, v12, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v11, v10, vcc_lo
v_cndmask_b32_e32 v9, v9, v14, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v12
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v11, v3, v10 :: v_dual_cndmask_b32 v10, v8, v9
.LBB0_8:
s_and_not1_saveexec_b32 s0, s9
s_cbranch_execz .LBB0_5
v_cvt_f32_u32_e32 v3, v4
v_sub_nc_u32_e32 v9, 0, v4
v_mov_b32_e32 v11, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v9, v3
v_mul_hi_u32 v9, v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v9
v_mul_hi_u32 v3, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, v4
v_sub_nc_u32_e32 v3, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v3, v4
v_cmp_ge_u32_e32 vcc_lo, v3, v4
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v3, v4
v_cmp_ge_u32_e32 vcc_lo, v3, v4
v_cndmask_b32_e32 v10, v3, v8, vcc_lo
s_branch .LBB0_5
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s1
.LBB0_11:
v_add_co_u32 v8, vcc_lo, v6, 1
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
v_cmp_ne_u64_e32 vcc_lo, 1, v[4:5]
v_cmp_ne_u64_e64 s0, s[4:5], v[4:5]
v_add_co_u32 v0, s1, v0, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v1, s1, 0, v1, s1
s_and_b32 s0, vcc_lo, s0
s_branch .LBB0_2
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v0, 0
global_store_b64 v0, v[4:5], s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10MonteCarloyPy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10MonteCarloyPy, .Lfunc_end0-_Z10MonteCarloyPy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10MonteCarloyPy
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z10MonteCarloyPy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
__device__ unsigned long long int gcd(unsigned long long int a, unsigned long long int b){
unsigned long long int r=0;
while(b!=0){
r = a%b;
a = b;
b = r;
}
return a;
}
__global__ void MonteCarlo(unsigned long long int n, unsigned long long int *d){
unsigned long long int dtmp = 1;
unsigned long long int a = threadIdx.x;
unsigned long long int b = threadIdx.x;
while((dtmp==1||dtmp==n) && (*d==1||*d==n)){
a = a*a+a+1;
b = b*b+b+1;
b = b*b+b+1;
dtmp = gcd(a-b,n);
}
*d=dtmp;
}
int main(int argc, char *argv[]){
if(argc<2)
exit(0);
unsigned long long int n = atoll(argv[1]);
unsigned long long int *ptrd;
unsigned long long int d = 1;
hipMalloc((void**) &ptrd, sizeof(unsigned long long int));
hipMemcpy(ptrd, &d, sizeof(unsigned long long int),hipMemcpyHostToDevice);
MonteCarlo<<<1,5>>>(n,ptrd);
hipMemcpy(&d, ptrd, sizeof(unsigned long long int),hipMemcpyDeviceToHost);
printf("%lld\n",d);
hipFree(ptrd);
return 0;
} | .text
.file "MonteCarlo.hip"
.globl _Z25__device_stub__MonteCarloyPy # -- Begin function _Z25__device_stub__MonteCarloyPy
.p2align 4, 0x90
.type _Z25__device_stub__MonteCarloyPy,@function
_Z25__device_stub__MonteCarloyPy: # @_Z25__device_stub__MonteCarloyPy
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10MonteCarloyPy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__MonteCarloyPy, .Lfunc_end0-_Z25__device_stub__MonteCarloyPy
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
cmpl $1, %edi
jle .LBB1_4
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoll
movq %rax, %rbx
movq $1, 8(%rsp)
movq %rsp, %rdi
movl $8, %esi
callq hipMalloc
movq (%rsp), %rdi
leaq 8(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
movq (%rsp), %rax
movq %rbx, 72(%rsp)
movq %rax, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10MonteCarloyPy, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
movq (%rsp), %rsi
leaq 8(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 112
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10MonteCarloyPy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10MonteCarloyPy,@object # @_Z10MonteCarloyPy
.section .rodata,"a",@progbits
.globl _Z10MonteCarloyPy
.p2align 3, 0x0
_Z10MonteCarloyPy:
.quad _Z25__device_stub__MonteCarloyPy
.size _Z10MonteCarloyPy, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%lld\n"
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10MonteCarloyPy"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__MonteCarloyPy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10MonteCarloyPy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00071306_00000000-6_MonteCarlo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3gcdyy
.type _Z3gcdyy, @function
_Z3gcdyy:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z3gcdyy, .-_Z3gcdyy
.globl _Z31__device_stub__Z10MonteCarloyPyyPy
.type _Z31__device_stub__Z10MonteCarloyPyyPy, @function
_Z31__device_stub__Z10MonteCarloyPyyPy:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10MonteCarloyPy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z10MonteCarloyPyyPy, .-_Z31__device_stub__Z10MonteCarloyPyyPy
.globl _Z10MonteCarloyPy
.type _Z10MonteCarloyPy, @function
_Z10MonteCarloyPy:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10MonteCarloyPyyPy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10MonteCarloyPy, .-_Z10MonteCarloyPy
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%lld\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L18
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtoll@PLT
movq %rax, %rbx
movq $1, 8(%rsp)
movq %rsp, %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
leaq 8(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl $0, %edi
call exit@PLT
.L19:
movq (%rsp), %rsi
movq %rbx, %rdi
call _Z31__device_stub__Z10MonteCarloyPyyPy
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10MonteCarloyPy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10MonteCarloyPy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MonteCarlo.hip"
.globl _Z25__device_stub__MonteCarloyPy # -- Begin function _Z25__device_stub__MonteCarloyPy
.p2align 4, 0x90
.type _Z25__device_stub__MonteCarloyPy,@function
_Z25__device_stub__MonteCarloyPy: # @_Z25__device_stub__MonteCarloyPy
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10MonteCarloyPy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__MonteCarloyPy, .Lfunc_end0-_Z25__device_stub__MonteCarloyPy
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
cmpl $1, %edi
jle .LBB1_4
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoll
movq %rax, %rbx
movq $1, 8(%rsp)
movq %rsp, %rdi
movl $8, %esi
callq hipMalloc
movq (%rsp), %rdi
leaq 8(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
movq (%rsp), %rax
movq %rbx, 72(%rsp)
movq %rax, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10MonteCarloyPy, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
movq (%rsp), %rsi
leaq 8(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 112
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10MonteCarloyPy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10MonteCarloyPy,@object # @_Z10MonteCarloyPy
.section .rodata,"a",@progbits
.globl _Z10MonteCarloyPy
.p2align 3, 0x0
_Z10MonteCarloyPy:
.quad _Z25__device_stub__MonteCarloyPy
.size _Z10MonteCarloyPy, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%lld\n"
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10MonteCarloyPy"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__MonteCarloyPy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10MonteCarloyPy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#ifndef _MATRIXMUL_KERNEL_H_
//#define _MATRIXMUL_KERNEL_H_
/*
(define (gpu-info)
(let* ([info (cuGPUinfo)])
(values (gridDim-x info) ......)))
(: test_kernel ((Listof Float) Integer -> (Listof Float) (Listof Integer) Integer)
(define (test_kernel d_array_in d_single_in)
(let*-values ([(d_array_out) (take d_array_in 0)]
[(memstruct) (gpu-info)]
[(d_single_out) d_single_in])
(values d_array_out memstruct d_single_out)))
*/
extern "C"
/* Signature:
float* d_array_in, int count, uint single_in
->
float* d_array_out, uint* d_array_len, int* memstruct, uint* single_out
*/
/*
In typed/Racket, (test_kernel) has type:
(Vectorof Float) Integer Integer -> (Vectorof Float) Integer Integer
*/
__global__ void
test_kernel(
float* d_array_in,
uint count,
int d_single_in,
float* d_array_out,
uint* d_array_out_len,
int* d_single_out
)
{
// copy - single value
*d_single_out = d_single_in;
*(d_array_out+0) = d_array_in[0];
*(d_array_out+1) = d_array_in[1];
*(d_array_out+2) = d_array_in[2];
*(d_array_out+3) = d_array_in[3];
*(d_array_out+4) = d_array_in[4];
*d_array_out_len = count;
*d_single_out = d_single_in;
// what's problem in my for loop?
// // copy of array variables
// for(int j = 0 ; j < count ; j++)
// {
// *(d_array_out+j) = d_array_in[j];
// // *(d_array_out+j) = j;
// // *(d_array_in+j) = j;
// }
*d_array_out_len = count;
/*
// copy of default variables
unsigned int gdm_x = gridDim.x;
unsigned int gdm_y = gridDim.y;
unsigned int gdm_z = gridDim.z;
unsigned int bdm_x = blockDim.x;
unsigned int bdm_y = blockDim.y;
unsigned int bdm_z = blockDim.z;
unsigned int bid_x = blockIdx.x;
unsigned int bid_y = blockIdx.y;
unsigned int bid_z = blockIdx.z;
unsigned int tid_x = threadIdx.x;
unsigned int tid_y = threadIdx.y;
unsigned int tid_z = threadIdx.z;
*memstruct = gdm_x;
*(memstruct+1) = gdm_y;
*(memstruct+2) = gdm_z;
*(memstruct+3) = bdm_x;
*(memstruct+4) = bdm_y;
*(memstruct+5) = bdm_z;
*(memstruct+6) = bid_x;
*(memstruct+7) = bid_y;
*(memstruct+8) = bid_z;
*(memstruct+9) = tid_x;
*(memstruct+10) = tid_y;
*(memstruct+11) = tid_z;
*/
} | code for sm_80
Function : test_kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R21, c[0x0][0x16c] ; /* 0x00005b0000157a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R3, c[0x0][0x184] ; /* 0x0000610000037a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0080*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*00a0*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fca0000000f00 */
/*00b0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x004fe8000c101904 */
/*00c0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STG.E [R6.64+0x4], R13 ; /* 0x0000040d06007986 */
/* 0x004fe8000c101904 */
/*00e0*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000804040f7981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STG.E [R6.64+0x8], R15 ; /* 0x0000080f06007986 */
/* 0x004fe8000c101904 */
/*0100*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff177624 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R8, c[0x0][0x178] ; /* 0x00005e0000087a02 */
/* 0x000fc40000000f00 */
/*0130*/ STG.E [R6.64+0xc], R17 ; /* 0x00000c1106007986 */
/* 0x004fe8000c101904 */
/*0140*/ LDG.E R19, [R4.64+0x10] ; /* 0x0000100404137981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fc600078e00ff */
/*0160*/ STG.E [R6.64+0x10], R19 ; /* 0x0000101306007986 */
/* 0x004fe8000c101904 */
/*0170*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0180*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#ifndef _MATRIXMUL_KERNEL_H_
//#define _MATRIXMUL_KERNEL_H_
/*
(define (gpu-info)
(let* ([info (cuGPUinfo)])
(values (gridDim-x info) ......)))
(: test_kernel ((Listof Float) Integer -> (Listof Float) (Listof Integer) Integer)
(define (test_kernel d_array_in d_single_in)
(let*-values ([(d_array_out) (take d_array_in 0)]
[(memstruct) (gpu-info)]
[(d_single_out) d_single_in])
(values d_array_out memstruct d_single_out)))
*/
extern "C"
/* Signature:
float* d_array_in, int count, uint single_in
->
float* d_array_out, uint* d_array_len, int* memstruct, uint* single_out
*/
/*
In typed/Racket, (test_kernel) has type:
(Vectorof Float) Integer Integer -> (Vectorof Float) Integer Integer
*/
__global__ void
test_kernel(
float* d_array_in,
uint count,
int d_single_in,
float* d_array_out,
uint* d_array_out_len,
int* d_single_out
)
{
// copy - single value
*d_single_out = d_single_in;
*(d_array_out+0) = d_array_in[0];
*(d_array_out+1) = d_array_in[1];
*(d_array_out+2) = d_array_in[2];
*(d_array_out+3) = d_array_in[3];
*(d_array_out+4) = d_array_in[4];
*d_array_out_len = count;
*d_single_out = d_single_in;
// what's problem in my for loop?
// // copy of array variables
// for(int j = 0 ; j < count ; j++)
// {
// *(d_array_out+j) = d_array_in[j];
// // *(d_array_out+j) = j;
// // *(d_array_in+j) = j;
// }
*d_array_out_len = count;
/*
// copy of default variables
unsigned int gdm_x = gridDim.x;
unsigned int gdm_y = gridDim.y;
unsigned int gdm_z = gridDim.z;
unsigned int bdm_x = blockDim.x;
unsigned int bdm_y = blockDim.y;
unsigned int bdm_z = blockDim.z;
unsigned int bid_x = blockIdx.x;
unsigned int bid_y = blockIdx.y;
unsigned int bid_z = blockIdx.z;
unsigned int tid_x = threadIdx.x;
unsigned int tid_y = threadIdx.y;
unsigned int tid_z = threadIdx.z;
*memstruct = gdm_x;
*(memstruct+1) = gdm_y;
*(memstruct+2) = gdm_z;
*(memstruct+3) = bdm_x;
*(memstruct+4) = bdm_y;
*(memstruct+5) = bdm_z;
*(memstruct+6) = bid_x;
*(memstruct+7) = bid_y;
*(memstruct+8) = bid_z;
*(memstruct+9) = tid_x;
*(memstruct+10) = tid_y;
*(memstruct+11) = tid_z;
*/
} | .file "tmpxft_00126ba6_00000000-6_test_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z11test_kernelPfjiS_PjPiPfjiS_PjPi
.type _Z39__device_stub__Z11test_kernelPfjiS_PjPiPfjiS_PjPi, @function
_Z39__device_stub__Z11test_kernelPfjiS_PjPiPfjiS_PjPi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq test_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z11test_kernelPfjiS_PjPiPfjiS_PjPi, .-_Z39__device_stub__Z11test_kernelPfjiS_PjPiPfjiS_PjPi
.globl test_kernel
.type test_kernel, @function
test_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11test_kernelPfjiS_PjPiPfjiS_PjPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size test_kernel, .-test_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "test_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq test_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#ifndef _MATRIXMUL_KERNEL_H_
//#define _MATRIXMUL_KERNEL_H_
/*
(define (gpu-info)
(let* ([info (cuGPUinfo)])
(values (gridDim-x info) ......)))
(: test_kernel ((Listof Float) Integer -> (Listof Float) (Listof Integer) Integer)
(define (test_kernel d_array_in d_single_in)
(let*-values ([(d_array_out) (take d_array_in 0)]
[(memstruct) (gpu-info)]
[(d_single_out) d_single_in])
(values d_array_out memstruct d_single_out)))
*/
extern "C"
/* Signature:
float* d_array_in, int count, uint single_in
->
float* d_array_out, uint* d_array_len, int* memstruct, uint* single_out
*/
/*
In typed/Racket, (test_kernel) has type:
(Vectorof Float) Integer Integer -> (Vectorof Float) Integer Integer
*/
__global__ void
test_kernel(
float* d_array_in,
uint count,
int d_single_in,
float* d_array_out,
uint* d_array_out_len,
int* d_single_out
)
{
// copy - single value
*d_single_out = d_single_in;
*(d_array_out+0) = d_array_in[0];
*(d_array_out+1) = d_array_in[1];
*(d_array_out+2) = d_array_in[2];
*(d_array_out+3) = d_array_in[3];
*(d_array_out+4) = d_array_in[4];
*d_array_out_len = count;
*d_single_out = d_single_in;
// what's problem in my for loop?
// // copy of array variables
// for(int j = 0 ; j < count ; j++)
// {
// *(d_array_out+j) = d_array_in[j];
// // *(d_array_out+j) = j;
// // *(d_array_in+j) = j;
// }
*d_array_out_len = count;
/*
// copy of default variables
unsigned int gdm_x = gridDim.x;
unsigned int gdm_y = gridDim.y;
unsigned int gdm_z = gridDim.z;
unsigned int bdm_x = blockDim.x;
unsigned int bdm_y = blockDim.y;
unsigned int bdm_z = blockDim.z;
unsigned int bid_x = blockIdx.x;
unsigned int bid_y = blockIdx.y;
unsigned int bid_z = blockIdx.z;
unsigned int tid_x = threadIdx.x;
unsigned int tid_y = threadIdx.y;
unsigned int tid_z = threadIdx.z;
*memstruct = gdm_x;
*(memstruct+1) = gdm_y;
*(memstruct+2) = gdm_z;
*(memstruct+3) = bdm_x;
*(memstruct+4) = bdm_y;
*(memstruct+5) = bdm_z;
*(memstruct+6) = bid_x;
*(memstruct+7) = bid_y;
*(memstruct+8) = bid_z;
*(memstruct+9) = tid_x;
*(memstruct+10) = tid_y;
*(memstruct+11) = tid_z;
*/
} | #include <hip/hip_runtime.h>
//#ifndef _MATRIXMUL_KERNEL_H_
//#define _MATRIXMUL_KERNEL_H_
/*
(define (gpu-info)
(let* ([info (cuGPUinfo)])
(values (gridDim-x info) ......)))
(: test_kernel ((Listof Float) Integer -> (Listof Float) (Listof Integer) Integer)
(define (test_kernel d_array_in d_single_in)
(let*-values ([(d_array_out) (take d_array_in 0)]
[(memstruct) (gpu-info)]
[(d_single_out) d_single_in])
(values d_array_out memstruct d_single_out)))
*/
extern "C"
/* Signature:
float* d_array_in, int count, uint single_in
->
float* d_array_out, uint* d_array_len, int* memstruct, uint* single_out
*/
/*
In typed/Racket, (test_kernel) has type:
(Vectorof Float) Integer Integer -> (Vectorof Float) Integer Integer
*/
__global__ void
test_kernel(
float* d_array_in,
uint count,
int d_single_in,
float* d_array_out,
uint* d_array_out_len,
int* d_single_out
)
{
// copy - single value
*d_single_out = d_single_in;
*(d_array_out+0) = d_array_in[0];
*(d_array_out+1) = d_array_in[1];
*(d_array_out+2) = d_array_in[2];
*(d_array_out+3) = d_array_in[3];
*(d_array_out+4) = d_array_in[4];
*d_array_out_len = count;
*d_single_out = d_single_in;
// what's problem in my for loop?
// // copy of array variables
// for(int j = 0 ; j < count ; j++)
// {
// *(d_array_out+j) = d_array_in[j];
// // *(d_array_out+j) = j;
// // *(d_array_in+j) = j;
// }
*d_array_out_len = count;
/*
// copy of default variables
unsigned int gdm_x = gridDim.x;
unsigned int gdm_y = gridDim.y;
unsigned int gdm_z = gridDim.z;
unsigned int bdm_x = blockDim.x;
unsigned int bdm_y = blockDim.y;
unsigned int bdm_z = blockDim.z;
unsigned int bid_x = blockIdx.x;
unsigned int bid_y = blockIdx.y;
unsigned int bid_z = blockIdx.z;
unsigned int tid_x = threadIdx.x;
unsigned int tid_y = threadIdx.y;
unsigned int tid_z = threadIdx.z;
*memstruct = gdm_x;
*(memstruct+1) = gdm_y;
*(memstruct+2) = gdm_z;
*(memstruct+3) = bdm_x;
*(memstruct+4) = bdm_y;
*(memstruct+5) = bdm_z;
*(memstruct+6) = bid_x;
*(memstruct+7) = bid_y;
*(memstruct+8) = bid_z;
*(memstruct+9) = tid_x;
*(memstruct+10) = tid_y;
*(memstruct+11) = tid_z;
*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#ifndef _MATRIXMUL_KERNEL_H_
//#define _MATRIXMUL_KERNEL_H_
/*
(define (gpu-info)
(let* ([info (cuGPUinfo)])
(values (gridDim-x info) ......)))
(: test_kernel ((Listof Float) Integer -> (Listof Float) (Listof Integer) Integer)
(define (test_kernel d_array_in d_single_in)
(let*-values ([(d_array_out) (take d_array_in 0)]
[(memstruct) (gpu-info)]
[(d_single_out) d_single_in])
(values d_array_out memstruct d_single_out)))
*/
extern "C"
/* Signature:
float* d_array_in, int count, uint single_in
->
float* d_array_out, uint* d_array_len, int* memstruct, uint* single_out
*/
/*
In typed/Racket, (test_kernel) has type:
(Vectorof Float) Integer Integer -> (Vectorof Float) Integer Integer
*/
__global__ void
test_kernel(
float* d_array_in,
uint count,
int d_single_in,
float* d_array_out,
uint* d_array_out_len,
int* d_single_out
)
{
// copy - single value
*d_single_out = d_single_in;
*(d_array_out+0) = d_array_in[0];
*(d_array_out+1) = d_array_in[1];
*(d_array_out+2) = d_array_in[2];
*(d_array_out+3) = d_array_in[3];
*(d_array_out+4) = d_array_in[4];
*d_array_out_len = count;
*d_single_out = d_single_in;
// what's problem in my for loop?
// // copy of array variables
// for(int j = 0 ; j < count ; j++)
// {
// *(d_array_out+j) = d_array_in[j];
// // *(d_array_out+j) = j;
// // *(d_array_in+j) = j;
// }
*d_array_out_len = count;
/*
// copy of default variables
unsigned int gdm_x = gridDim.x;
unsigned int gdm_y = gridDim.y;
unsigned int gdm_z = gridDim.z;
unsigned int bdm_x = blockDim.x;
unsigned int bdm_y = blockDim.y;
unsigned int bdm_z = blockDim.z;
unsigned int bid_x = blockIdx.x;
unsigned int bid_y = blockIdx.y;
unsigned int bid_z = blockIdx.z;
unsigned int tid_x = threadIdx.x;
unsigned int tid_y = threadIdx.y;
unsigned int tid_z = threadIdx.z;
*memstruct = gdm_x;
*(memstruct+1) = gdm_y;
*(memstruct+2) = gdm_z;
*(memstruct+3) = bdm_x;
*(memstruct+4) = bdm_y;
*(memstruct+5) = bdm_z;
*(memstruct+6) = bid_x;
*(memstruct+7) = bid_y;
*(memstruct+8) = bid_z;
*(memstruct+9) = tid_x;
*(memstruct+10) = tid_y;
*(memstruct+11) = tid_z;
*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected test_kernel
.globl test_kernel
.p2align 8
.type test_kernel,@function
test_kernel:
s_load_b64 s[8:9], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s10, s[8:9], 0x0
s_load_b256 s[0:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s10
v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
global_store_b32 v0, v1, s[2:3]
global_load_b32 v1, v0, s[8:9] offset:4
global_store_b32 v0, v3, s[6:7]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3] offset:4
global_load_b32 v1, v0, s[8:9] offset:8
global_store_b32 v0, v2, s[4:5]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3] offset:8
global_load_b32 v1, v0, s[8:9] offset:12
global_store_b32 v0, v3, s[6:7]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3] offset:12
global_load_b32 v1, v0, s[8:9] offset:16
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b32 v0, v1, s[2:3] offset:16
global_store_b32 v0, v2, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel test_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 11
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size test_kernel, .Lfunc_end0-test_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: test_kernel
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: test_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#ifndef _MATRIXMUL_KERNEL_H_
//#define _MATRIXMUL_KERNEL_H_
/*
(define (gpu-info)
(let* ([info (cuGPUinfo)])
(values (gridDim-x info) ......)))
(: test_kernel ((Listof Float) Integer -> (Listof Float) (Listof Integer) Integer)
(define (test_kernel d_array_in d_single_in)
(let*-values ([(d_array_out) (take d_array_in 0)]
[(memstruct) (gpu-info)]
[(d_single_out) d_single_in])
(values d_array_out memstruct d_single_out)))
*/
extern "C"
/* Signature:
float* d_array_in, int count, uint single_in
->
float* d_array_out, uint* d_array_len, int* memstruct, uint* single_out
*/
/*
In typed/Racket, (test_kernel) has type:
(Vectorof Float) Integer Integer -> (Vectorof Float) Integer Integer
*/
__global__ void
test_kernel(
float* d_array_in,
uint count,
int d_single_in,
float* d_array_out,
uint* d_array_out_len,
int* d_single_out
)
{
// copy - single value
*d_single_out = d_single_in;
*(d_array_out+0) = d_array_in[0];
*(d_array_out+1) = d_array_in[1];
*(d_array_out+2) = d_array_in[2];
*(d_array_out+3) = d_array_in[3];
*(d_array_out+4) = d_array_in[4];
*d_array_out_len = count;
*d_single_out = d_single_in;
// what's problem in my for loop?
// // copy of array variables
// for(int j = 0 ; j < count ; j++)
// {
// *(d_array_out+j) = d_array_in[j];
// // *(d_array_out+j) = j;
// // *(d_array_in+j) = j;
// }
*d_array_out_len = count;
/*
// copy of default variables
unsigned int gdm_x = gridDim.x;
unsigned int gdm_y = gridDim.y;
unsigned int gdm_z = gridDim.z;
unsigned int bdm_x = blockDim.x;
unsigned int bdm_y = blockDim.y;
unsigned int bdm_z = blockDim.z;
unsigned int bid_x = blockIdx.x;
unsigned int bid_y = blockIdx.y;
unsigned int bid_z = blockIdx.z;
unsigned int tid_x = threadIdx.x;
unsigned int tid_y = threadIdx.y;
unsigned int tid_z = threadIdx.z;
*memstruct = gdm_x;
*(memstruct+1) = gdm_y;
*(memstruct+2) = gdm_z;
*(memstruct+3) = bdm_x;
*(memstruct+4) = bdm_y;
*(memstruct+5) = bdm_z;
*(memstruct+6) = bid_x;
*(memstruct+7) = bid_y;
*(memstruct+8) = bid_z;
*(memstruct+9) = tid_x;
*(memstruct+10) = tid_y;
*(memstruct+11) = tid_z;
*/
} | .text
.file "test_kernel.hip"
.globl __device_stub__test_kernel # -- Begin function __device_stub__test_kernel
.p2align 4, 0x90
.type __device_stub__test_kernel,@function
__device_stub__test_kernel: # @__device_stub__test_kernel
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $test_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__test_kernel, .Lfunc_end0-__device_stub__test_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $test_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type test_kernel,@object # @test_kernel
.section .rodata,"a",@progbits
.globl test_kernel
.p2align 3, 0x0
test_kernel:
.quad __device_stub__test_kernel
.size test_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "test_kernel"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__test_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym test_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : test_kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R21, c[0x0][0x16c] ; /* 0x00005b0000157a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R3, c[0x0][0x184] ; /* 0x0000610000037a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0080*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*00a0*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fca0000000f00 */
/*00b0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x004fe8000c101904 */
/*00c0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STG.E [R6.64+0x4], R13 ; /* 0x0000040d06007986 */
/* 0x004fe8000c101904 */
/*00e0*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000804040f7981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STG.E [R6.64+0x8], R15 ; /* 0x0000080f06007986 */
/* 0x004fe8000c101904 */
/*0100*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff177624 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R8, c[0x0][0x178] ; /* 0x00005e0000087a02 */
/* 0x000fc40000000f00 */
/*0130*/ STG.E [R6.64+0xc], R17 ; /* 0x00000c1106007986 */
/* 0x004fe8000c101904 */
/*0140*/ LDG.E R19, [R4.64+0x10] ; /* 0x0000100404137981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fc600078e00ff */
/*0160*/ STG.E [R6.64+0x10], R19 ; /* 0x0000101306007986 */
/* 0x004fe8000c101904 */
/*0170*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0180*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected test_kernel
.globl test_kernel
.p2align 8
.type test_kernel,@function
test_kernel:
s_load_b64 s[8:9], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s10, s[8:9], 0x0
s_load_b256 s[0:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s10
v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
global_store_b32 v0, v1, s[2:3]
global_load_b32 v1, v0, s[8:9] offset:4
global_store_b32 v0, v3, s[6:7]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3] offset:4
global_load_b32 v1, v0, s[8:9] offset:8
global_store_b32 v0, v2, s[4:5]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3] offset:8
global_load_b32 v1, v0, s[8:9] offset:12
global_store_b32 v0, v3, s[6:7]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3] offset:12
global_load_b32 v1, v0, s[8:9] offset:16
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b32 v0, v1, s[2:3] offset:16
global_store_b32 v0, v2, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel test_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 11
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size test_kernel, .Lfunc_end0-test_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: test_kernel
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: test_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00126ba6_00000000-6_test_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z11test_kernelPfjiS_PjPiPfjiS_PjPi
.type _Z39__device_stub__Z11test_kernelPfjiS_PjPiPfjiS_PjPi, @function
_Z39__device_stub__Z11test_kernelPfjiS_PjPiPfjiS_PjPi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq test_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z11test_kernelPfjiS_PjPiPfjiS_PjPi, .-_Z39__device_stub__Z11test_kernelPfjiS_PjPiPfjiS_PjPi
.globl test_kernel
.type test_kernel, @function
test_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11test_kernelPfjiS_PjPiPfjiS_PjPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size test_kernel, .-test_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "test_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq test_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_kernel.hip"
.globl __device_stub__test_kernel # -- Begin function __device_stub__test_kernel
.p2align 4, 0x90
.type __device_stub__test_kernel,@function
__device_stub__test_kernel: # @__device_stub__test_kernel
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $test_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__test_kernel, .Lfunc_end0-__device_stub__test_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $test_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type test_kernel,@object # @test_kernel
.section .rodata,"a",@progbits
.globl test_kernel
.p2align 3, 0x0
test_kernel:
.quad __device_stub__test_kernel
.size test_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "test_kernel"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__test_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym test_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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