system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cuda.h>
static const int ThreadsPerBlock = 512;
static int* d_maxlen;
static __global__ void collatz(const long start, const long stop, int* const maxlen)
{
// todo: process odd values from start (assume start to be odd) to stop (inclusively if stop is odd) with one thread per value (based o... | #include <cstdio>
#include <hip/hip_runtime.h>
static const int ThreadsPerBlock = 512;
static int* d_maxlen;
static __global__ void collatz(const long start, const long stop, int* const maxlen)
{
// todo: process odd values from start (assume start to be odd) to stop (inclusively if stop is odd) with one thread per val... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <cstdio>
#include <hip/hip_runtime.h>
static const int ThreadsPerBlock = 512;
static int* d_maxlen;
static __global__ void collatz(const long start, const long stop, int* const maxlen)
{
// todo: process odd values from start (assume start to be odd) to stop (inclusively if stop is odd) with one thread per val... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL7collatzllPi,"axG",@progbits,_ZL7collatzllPi,comdat
.globl _ZL7collatzllPi
.p2align 8
.type _ZL7collatzllPi,@function
_ZL7collatzllPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_m... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <cstdio>
#include <hip/hip_runtime.h>
static const int ThreadsPerBlock = 512;
static int* d_maxlen;
static __global__ void collatz(const long start, const long stop, int* const maxlen)
{
// todo: process odd values from start (assume start to be odd) to stop (inclusively if stop is odd) with one thread per val... | .text
.file "collatz_hyb.hip"
.globl _Z8GPU_Initv # -- Begin function _Z8GPU_Initv
.p2align 4, 0x90
.type _Z8GPU_Initv,@function
_Z8GPU_Initv: # @_Z8GPU_Initv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $0, 4(%rsp)
movl $_ZL8d_maxlen, %edi
movl $4, %esi
ca... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7collatzllPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e2200000021... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL7collatzllPi,"axG",@progbits,_ZL7collatzllPi,comdat
.globl _ZL7collatzllPi
.p2align 8
.type _ZL7collatzllPi,@function
_ZL7collatzllPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_m... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000234b5_00000000-6_collatz_hyb.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL28__device_stub__Z7collatzllPillPi, @function
_ZL28__device_stub__Z7collatzllPillPi:
.LFB2084:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %... | .text
.file "collatz_hyb.hip"
.globl _Z8GPU_Initv # -- Begin function _Z8GPU_Initv
.p2align 4, 0x90
.type _Z8GPU_Initv,@function
_Z8GPU_Initv: # @_Z8GPU_Initv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $0, 4(%rsp)
movl $_ZL8d_maxlen, %edi
movl $4, %esi
ca... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.
*
*
* These example codes are a portion of the code samples from the compan... | code for sm_80
Function : zero
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.
*
*
* These example codes are a portion of the code samples from the compan... | .file "tmpxft_0009591c_00000000-6_zero.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.
*
*
* These example codes are a portion of the code samples from the compan... | #include <hip/hip_runtime.h>
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.
*
*
* These example codes are a portion of the... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.
*
*
* These example codes are a portion of the... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected zero
.globl zero
.p2align 8
.type zero,@function
zero:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.
*
*
* These example codes are a portion of the... | .text
.file "zero.hip"
.globl __device_stub__zero # -- Begin function __device_stub__zero
.p2align 4, 0x90
.type __device_stub__zero,@function
__device_stub__zero: # @__device_stub__zero
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : zero
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected zero
.globl zero
.p2align 8
.type zero,@function
zero:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009591c_00000000-6_zero.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "zero.hip"
.globl __device_stub__zero # -- Begin function __device_stub__zero
.p2align 4, 0x90
.type __device_stub__zero,@function
__device_stub__zero: # @__device_stub__zero
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <stdint.h>
#define IN_FEATS 200
#define OUT_CLASSES 10
#define W_SIZE IN_FEATS * OUT_CLASSES
uint64_t getTimeMicroseconds64()
{
uint64_t nTime;
struct timespec tSpec;
clock_gettime(CLOCK_REALTIME, &tSpec);
nTime = (uint64_t)tSpec.tv_nse... | code for sm_80
Function : _Z8lrp_percPfS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <stdint.h>
#define IN_FEATS 200
#define OUT_CLASSES 10
#define W_SIZE IN_FEATS * OUT_CLASSES
uint64_t getTimeMicroseconds64()
{
uint64_t nTime;
struct timespec tSpec;
clock_gettime(CLOCK_REALTIME, &tSpec);
nTime = (uint64_t)tSpec.tv_nse... | .file "tmpxft_00008c99_00000000-6_dense_relu_lrp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <stdint.h>
#define IN_FEATS 200
#define OUT_CLASSES 10
#define W_SIZE IN_FEATS * OUT_CLASSES
uint64_t getTimeMicroseconds64()
{
uint64_t nTime;
struct timespec tSpec;
clock_gettime(CLOCK_REALTIME, &tSpec);
nTime = (uint64_t)tSpec.tv_nse... | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <stdint.h>
#define IN_FEATS 200
#define OUT_CLASSES 10
#define W_SIZE IN_FEATS * OUT_CLASSES
uint64_t getTimeMicroseconds64()
{
uint64_t nTime;
struct timespec tSpec;
clock_gettime(CLOCK_REALTIME, &tSpec);
n... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <stdint.h>
#define IN_FEATS 200
#define OUT_CLASSES 10
#define W_SIZE IN_FEATS * OUT_CLASSES
uint64_t getTimeMicroseconds64()
{
uint64_t nTime;
struct timespec tSpec;
clock_gettime(CLOCK_REALTIME, &tSpec);
n... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8fwd_percPfS_S_S_S_
.globl _Z8fwd_percPfS_S_S_S_
.p2align 8
.type _Z8fwd_percPfS_S_S_S_,@function
_Z8fwd_percPfS_S_S_S_:
s_mov_b32 s2, s15
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
v_mad_u64_u32 v[1:2],... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <stdint.h>
#define IN_FEATS 200
#define OUT_CLASSES 10
#define W_SIZE IN_FEATS * OUT_CLASSES
uint64_t getTimeMicroseconds64()
{
uint64_t nTime;
struct timespec tSpec;
clock_gettime(CLOCK_REALTIME, &tSpec);
n... | .text
.file "dense_relu_lrp.hip"
.globl _Z21getTimeMicroseconds64v # -- Begin function _Z21getTimeMicroseconds64v
.p2align 4, 0x90
.type _Z21getTimeMicroseconds64v,@function
_Z21getTimeMicroseconds64v: # @_Z21getTimeMicroseconds64v
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%r... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8lrp_percPfS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8fwd_percPfS_S_S_S_
.globl _Z8fwd_percPfS_S_S_S_
.p2align 8
.type _Z8fwd_percPfS_S_S_S_,@function
_Z8fwd_percPfS_S_S_S_:
s_mov_b32 s2, s15
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
v_mad_u64_u32 v[1:2],... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00008c99_00000000-6_dense_relu_lrp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... | .text
.file "dense_relu_lrp.hip"
.globl _Z21getTimeMicroseconds64v # -- Begin function _Z21getTimeMicroseconds64v
.p2align 4, 0x90
.type _Z21getTimeMicroseconds64v,@function
_Z21getTimeMicroseconds64v: # @_Z21getTimeMicroseconds64v
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%r... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define DIM 2048
#define N (DIM*DIM)
#define THREAD_PER_BLOCK 512
__global__ void add(int* a, int* b, int* c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
void randomInts(int* a, int... | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define DIM 2048
#define N (DIM*DIM)
#define THREAD_PER_BLOCK 512
__global__ void add(int* a, int* b, int* c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
void randomInts(int* a, int... | .file "tmpxft_0001f00d_00000000-6_exo2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4860:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnreg... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define DIM 2048
#define N (DIM*DIM)
#define THREAD_PER_BLOCK 512
__global__ void add(int* a, int* b, int* c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
void randomInts(int* a, int... | #include <hip/hip_runtime.h>
#include <stdio.h>
// #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define DIM 2048
#define N (DIM*DIM)
#define THREAD_PER_BLOCK 512
__global__ void add(int* a, int* b, int* c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define DIM 2048
#define N (DIM*DIM)
#define THREAD_PER_BLOCK 512
__global__ void add(int* a, int* b, int* c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define DIM 2048
#define N (DIM*DIM)
#define THREAD_PER_BLOCK 512
__global__ void add(int* a, int* b, int* c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
... | .text
.file "exo2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.typ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001f00d_00000000-6_exo2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4860:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnreg... | .text
.file "exo2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.typ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void UpdateVelocitiesKernel (double *VthetaInt, double *VradInt, double *invRmed, double *Rmed, double *Rsup, double *Rinf, double *invdiffRmed, double *invdiffRsup, double *Dens, double *invRinf, double *TAURR, double *TAURP, double *TAUPP, double DeltaT, int nrad, int nsec)
{
int j = ... | .file "tmpxft_000d2c9b_00000000-6_UpdateVelocitiesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void UpdateVelocitiesKernel (double *VthetaInt, double *VradInt, double *invRmed, double *Rmed, double *Rsup, double *Rinf, double *invdiffRmed, double *invdiffRsup, double *Dens, double *invRinf, double *TAURR, double *TAURP, double *TAUPP, double DeltaT, int nrad, int nsec)
{
int j = ... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UpdateVelocitiesKernel (double *VthetaInt, double *VradInt, double *invRmed, double *Rmed, double *Rsup, double *Rinf, double *invdiffRmed, double *invdiffRsup, double *Dens, double *invRinf, double *TAURR, double *TAURP, double *TAUPP, double DeltaT, i... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UpdateVelocitiesKernel (double *VthetaInt, double *VradInt, double *invRmed, double *Rmed, double *Rsup, double *Rinf, double *invdiffRmed, double *invdiffRsup, double *Dens, double *invRinf, double *TAURR, double *TAURP, double *TAUPP, double DeltaT, i... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.globl _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.p2align 8
.type _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii,@function
_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii:... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UpdateVelocitiesKernel (double *VthetaInt, double *VradInt, double *invRmed, double *Rmed, double *Rsup, double *Rinf, double *invdiffRmed, double *invdiffRsup, double *Dens, double *invRinf, double *TAURR, double *TAURP, double *TAUPP, double DeltaT, i... | .text
.file "UpdateVelocitiesKernel.hip"
.globl _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii # -- Begin function _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.p2align 4, 0x90
.type _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii,@function
_Z37__... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d2c9b_00000000-6_UpdateVelocitiesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT... | .text
.file "UpdateVelocitiesKernel.hip"
.globl _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii # -- Begin function _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.p2align 4, 0x90
.type _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii,@function
_Z37__... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ int addem( int a, int b ) {
return a + b;
}
__global__ void add( int a, int b, int *c ) {
*c = addem( a, b );
} | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ int addem( int a, int b ) {
return a + b;
}
__global__ void add( int a, int b, int *c ) {
*c = addem( a, b );
} | .file "tmpxft_000b9381_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ int addem( int a, int b ) {
return a + b;
}
__global__ void add( int a, int b, int *c ) {
*c = addem( a, b );
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int addem( int a, int b ) {
return a + b;
}
__global__ void add( int a, int b, int *c ) {
*c = addem( a, b );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int addem( int a, int b ) {
return a + b;
}
__global__ void add( int a, int b, int *c ) {
*c = addem( a, b );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dua... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int addem( int a, int b ) {
return a + b;
}
__global__ void add( int a, int b, int *c ) {
*c = addem( a, b );
} | .text
.file "add.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
m... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dua... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b9381_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi... | .text
.file "add.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
m... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cassert>
#include <stdio.h>
#include <cuda_runtime.h>
#include <math.h>
#include <float.h>
#include "raytraceCuda.cuh"
// flags as to whether or not reflection and refraction are included in the
// raytracing
#define REFLECTION 1
#define REFRACTION 1
#define SINGLETHREADMODE 0
#define RECURSIONDEPTH 3
#define... | #include <cstdio>
#include <math.h>
#include <hip/hip_runtime.h>
struct Point_Light;
struct Material;
struct Object;
void callRaytraceKernel(double *grid, Object *objects, Point_Light *lightsPPM,
double *data, double *bgColor, double *e1, double *e2,
double *e3, double *lookFrom, int Nx, int Ny,
bool antiAliased, int... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <cstdio>
#include <math.h>
#include <hip/hip_runtime.h>
struct Point_Light;
struct Material;
struct Object;
void callRaytraceKernel(double *grid, Object *objects, Point_Light *lightsPPM,
double *data, double *bgColor, double *e1, double *e2,
double *e3, double *lookFrom, int Nx, int Ny,
bool antiAliased, int... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <cstdio>
#include <math.h>
#include <hip/hip_runtime.h>
struct Point_Light;
struct Material;
struct Object;
void callRaytraceKernel(double *grid, Object *objects, Point_Light *lightsPPM,
double *data, double *bgColor, double *e1, double *e2,
double *e3, double *lookFrom, int Nx, int Ny,
bool antiAliased, int... | .text
.file "raytraceCuda.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-pro... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012eb29_00000000-6_raytraceCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, ... | .text
.file "raytraceCuda.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-pro... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Date March 28 2029
//Programer: Hemanta Bhattarai
// Progarm : To add two arrays and compare computation time in host and device
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h> //for random numbers
#include <time.h>
#include <sys/time.h>
#define gpuErrchk(ans){ ... | code for sm_80
Function : _Z6vecAddPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*002... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Date March 28 2029
//Programer: Hemanta Bhattarai
// Progarm : To add two arrays and compare computation time in host and device
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h> //for random numbers
#include <time.h>
#include <sys/time.h>
#define gpuErrchk(ans){ ... | .file "tmpxft_001173c7_00000000-6_add_vector_very_large.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Date March 28 2029
//Programer: Hemanta Bhattarai
// Progarm : To add two arrays and compare computation time in host and device
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h> //for random numbers
#include <time.h>
#include <sys/time.h>
#define gpuErrchk(ans){ ... | // Date March 28 2029
//Programer: Hemanta Bhattarai
// Progarm : To add two arrays and compare computation time in host and device
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h> //for random numbers
#include <time.h>
#include <sys/time.h>
#define gpuErrchk(ans){ gpuAssert((ans),__FILE__, __LINE__)... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Date March 28 2029
//Programer: Hemanta Bhattarai
// Progarm : To add two arrays and compare computation time in host and device
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h> //for random numbers
#include <time.h>
#include <sys/time.h>
#define gpuErrchk(ans){ gpuAssert((ans),__FILE__, __LINE__)... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_S_i
.globl _Z6vecAddPfS_S_S_i
.p2align 8
.type _Z6vecAddPfS_S_S_i,@function
_Z6vecAddPfS_S_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s12, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Date March 28 2029
//Programer: Hemanta Bhattarai
// Progarm : To add two arrays and compare computation time in host and device
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h> //for random numbers
#include <time.h>
#include <sys/time.h>
#define gpuErrchk(ans){ gpuAssert((ans),__FILE__, __LINE__)... | .text
.file "add_vector_very_large.hip"
.globl _Z21__device_stub__vecAddPfS_S_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_S_i,@function
_Z21__device_stub__vecAddPfS_S_S_i: # @_Z21__device_stub__vecAddPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %r... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*002... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_S_i
.globl _Z6vecAddPfS_S_S_i
.p2align 8
.type _Z6vecAddPfS_S_S_i,@function
_Z6vecAddPfS_S_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s12, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001173c7_00000000-6_add_vector_very_large.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
... | .text
.file "add_vector_very_large.hip"
.globl _Z21__device_stub__vecAddPfS_S_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_S_i,@function
_Z21__device_stub__vecAddPfS_S_S_i: # @_Z21__device_stub__vecAddPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <time.h>
#define LENGTH 10000
using namespace std;
struct aos{
int a;
int b;
int c;
};
__global__ void vector_add(aos *arr){
int i = threadIdx.x ;
if (i < LENGTH)
arr[i].c = arr[i].a + arr[i].b; // read
}
__host__ void vector_add_cpu(float a[], float b[], float *c){
for... | code for sm_80
Function : _Z10vector_addP3aos
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <time.h>
#define LENGTH 10000
using namespace std;
struct aos{
int a;
int b;
int c;
};
__global__ void vector_add(aos *arr){
int i = threadIdx.x ;
if (i < LENGTH)
arr[i].c = arr[i].a + arr[i].b; // read
}
__host__ void vector_add_cpu(float a[], float b[], float *c){
for... | .file "tmpxft_00023d51_00000000-6_aos.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregi... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <time.h>
#define LENGTH 10000
using namespace std;
struct aos{
int a;
int b;
int c;
};
__global__ void vector_add(aos *arr){
int i = threadIdx.x ;
if (i < LENGTH)
arr[i].c = arr[i].a + arr[i].b; // read
}
__host__ void vector_add_cpu(float a[], float b[], float *c){
for... | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <time.h>
#define LENGTH 10000
using namespace std;
struct aos{
int a;
int b;
int c;
};
__global__ void vector_add(aos *arr){
int i = threadIdx.x ;
if (i < LENGTH)
arr[i].c = arr[i].a + arr[i].b; // read
}
__host__ void vector_add_cpu(float a... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <time.h>
#define LENGTH 10000
using namespace std;
struct aos{
int a;
int b;
int c;
};
__global__ void vector_add(aos *arr){
int i = threadIdx.x ;
if (i < LENGTH)
arr[i].c = arr[i].a + arr[i].b; // read
}
__host__ void vector_add_cpu(float a... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addP3aos
.globl _Z10vector_addP3aos
.p2align 8
.type _Z10vector_addP3aos,@function
_Z10vector_addP3aos:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, 12, s[0:1]
global_load_b64 v[3:4], ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <time.h>
#define LENGTH 10000
using namespace std;
struct aos{
int a;
int b;
int c;
};
__global__ void vector_add(aos *arr){
int i = threadIdx.x ;
if (i < LENGTH)
arr[i].c = arr[i].a + arr[i].b; // read
}
__host__ void vector_add_cpu(float a... | .text
.file "aos.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__vector_addP3aos # -- Begin function _Z25__device_stub__vector_addP3aos
.p2align 4, 0... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10vector_addP3aos
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addP3aos
.globl _Z10vector_addP3aos
.p2align 8
.type _Z10vector_addP3aos,@function
_Z10vector_addP3aos:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, 12, s[0:1]
global_load_b64 v[3:4], ... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00023d51_00000000-6_aos.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregi... | .text
.file "aos.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__vector_addP3aos # -- Begin function _Z25__device_stub__vector_addP3aos
.p2align 4, 0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void addSubArray1 (int *A, int *B, int w, int h) {
for (int i = 0; i < w; i++) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
B[2 * j * w + i] += A[i];
B[(2 * j + 1) * w + i] -= A[i];
}
} | code for sm_80
Function : _Z12addSubArray1PiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00f... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void addSubArray1 (int *A, int *B, int w, int h) {
for (int i = 0; i < w; i++) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
B[2 * j * w + i] += A[i];
B[(2 * j + 1) * w + i] -= A[i];
}
} | .file "tmpxft_0011aae5_00000000-6_addSub1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void addSubArray1 (int *A, int *B, int w, int h) {
for (int i = 0; i < w; i++) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
B[2 * j * w + i] += A[i];
B[(2 * j + 1) * w + i] -= A[i];
}
} | #include <hip/hip_runtime.h>
__global__ void addSubArray1 (int *A, int *B, int w, int h) {
for (int i = 0; i < w; i++) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
B[2 * j * w + i] += A[i];
B[(2 * j + 1) * w + i] -= A[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void addSubArray1 (int *A, int *B, int w, int h) {
for (int i = 0; i < w; i++) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
B[2 * j * w + i] += A[i];
B[(2 * j + 1) * w + i] -= A[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12addSubArray1PiS_ii
.globl _Z12addSubArray1PiS_ii
.p2align 8
.type _Z12addSubArray1PiS_ii,@function
_Z12addSubArray1PiS_ii:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s2, s[0:1],... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void addSubArray1 (int *A, int *B, int w, int h) {
for (int i = 0; i < w; i++) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
B[2 * j * w + i] += A[i];
B[(2 * j + 1) * w + i] -= A[i];
}
} | .text
.file "addSub1.hip"
.globl _Z27__device_stub__addSubArray1PiS_ii # -- Begin function _Z27__device_stub__addSubArray1PiS_ii
.p2align 4, 0x90
.type _Z27__device_stub__addSubArray1PiS_ii,@function
_Z27__device_stub__addSubArray1PiS_ii: # @_Z27__device_stub__addSubArray1PiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12addSubArray1PiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00f... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12addSubArray1PiS_ii
.globl _Z12addSubArray1PiS_ii
.p2align 8
.type _Z12addSubArray1PiS_ii,@function
_Z12addSubArray1PiS_ii:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s2, s[0:1],... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011aae5_00000000-6_addSub1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "addSub1.hip"
.globl _Z27__device_stub__addSubArray1PiS_ii # -- Begin function _Z27__device_stub__addSubArray1PiS_ii
.p2align 4, 0x90
.type _Z27__device_stub__addSubArray1PiS_ii,@function
_Z27__device_stub__addSubArray1PiS_ii: # @_Z27__device_stub__addSubArray1PiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Exercise: Implement matrix transpose using CUDA
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/time.h>
#include<assert.h>
// #define NUM_BLOCKS 8192
#define NUM_THREADS 512
double cclock()
/* Returns elepsed seconds past from the last call to timer re... | code for sm_80
Function : _Z9trasp_matiPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e22000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Exercise: Implement matrix transpose using CUDA
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/time.h>
#include<assert.h>
// #define NUM_BLOCKS 8192
#define NUM_THREADS 512
double cclock()
/* Returns elepsed seconds past from the last call to timer re... | .file "tmpxft_0004c58f_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Exercise: Implement matrix transpose using CUDA
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/time.h>
#include<assert.h>
// #define NUM_BLOCKS 8192
#define NUM_THREADS 512
double cclock()
/* Returns elepsed seconds past from the last call to timer re... | // Exercise: Implement matrix transpose using CUDA
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/time.h>
#include<assert.h>
// #define NUM_BLOCKS 8192
#define NUM_THREADS 512
double cclock()
/* Returns elepsed seconds past f... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Exercise: Implement matrix transpose using CUDA
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/time.h>
#include<assert.h>
// #define NUM_BLOCKS 8192
#define NUM_THREADS 512
double cclock()
/* Returns elepsed seconds past f... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9trasp_matiPdS_
.globl _Z9trasp_matiPdS_
.p2align 8
.type _Z9trasp_matiPdS_,@function
_Z9trasp_matiPdS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_a... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Exercise: Implement matrix transpose using CUDA
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/time.h>
#include<assert.h>
// #define NUM_BLOCKS 8192
#define NUM_THREADS 512
double cclock()
/* Returns elepsed seconds past f... | .text
.file "transpose.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6cclockv
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z6cclockv
.p2align 4, 0x90
.type _Z6cclockv,@function
_Z6cclockv: # @_Z6ccl... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9trasp_matiPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e22000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9trasp_matiPdS_
.globl _Z9trasp_matiPdS_
.p2align 8
.type _Z9trasp_matiPdS_,@function
_Z9trasp_matiPdS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_a... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004c58f_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... | .text
.file "transpose.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6cclockv
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z6cclockv
.p2align 4, 0x90
.type _Z6cclockv,@function
_Z6cclockv: # @_Z6ccl... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Detect the number of CUDA capable devices.
*/
#include <iostream>
int main()
{
int count = 0;
cudaGetDeviceCount( &count );
std::cout << count << " device(s) found.\n";
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Detect the number of CUDA capable devices.
*/
#include <iostream>
int main()
{
int count = 0;
cudaGetDeviceCount( &count );
std::cout << count << " device(s) found.\n";
return 0;
} | .file "tmpxft_00056019_00000000-6_01-query.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaU... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Detect the number of CUDA capable devices.
*/
#include <iostream>
int main()
{
int count = 0;
cudaGetDeviceCount( &count );
std::cout << count << " device(s) found.\n";
return 0;
} | /**
* Detect the number of CUDA capable devices.
*/
#include <hip/hip_runtime.h>
#include <iostream>
int main()
{
int count = 0;
hipGetDeviceCount( &count );
std::cout << count << " device(s) found.\n";
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Detect the number of CUDA capable devices.
*/
#include <hip/hip_runtime.h>
#include <iostream>
int main()
{
int count = 0;
hipGetDeviceCount( &count );
std::cout << count << " device(s) found.\n";
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Detect the number of CUDA capable devices.
*/
#include <hip/hip_runtime.h>
#include <iostream>
int main()
{
int count = 0;
hipGetDeviceCount( &count );
std::cout << count << " device(s) found.\n";
return 0;
} | .text
.file "01-query.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
mai... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00056019_00000000-6_01-query.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaU... | .text
.file "01-query.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
mai... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <math.h>
using namespace std;
// Blocksize
#define BLOCKSIZE 1024
//*************************************************
// GLOBAL MEMORY VERSION OF THE ALGORITHM
// ************************************************
__global__ void vectorNS(float *in, floa... | .file "tmpxft_00184ff9_00000000-6_vector.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnr... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <math.h>
using namespace std;
// Blocksize
#define BLOCKSIZE 1024
//*************************************************
// GLOBAL MEMORY VERSION OF THE ALGORITHM
// ************************************************
__global__ void vectorNS(float *in, floa... | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <math.h>
using namespace std;
// Blocksize
#define BLOCKSIZE 1024
//*************************************************
// GLOBAL MEMORY VERSION OF THE ALGORITHM
// ************************************************
__global__ ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
//#define __OUTPUT_PIX__
#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];
__global__ void convert_to_luv_gpu_kernel(unsigned char *in_img, float *... | code for sm_80
Function : _Z25convert_to_luv_gpu_kernelPhPfiib
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x000000000003791... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
//#define __OUTPUT_PIX__
#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];
__global__ void convert_to_luv_gpu_kernel(unsigned char *in_img, float *... | .file "tmpxft_00172874_00000000-6_convert_to_luv_gpu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
//#define __OUTPUT_PIX__
#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];
__global__ void convert_to_luv_gpu_kernel(unsigned char *in_img, float *... | #include <hip/hip_runtime.h>
#include "includes.h"
//#define __OUTPUT_PIX__
#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];
__global__ void convert_to_luv_gpu_kernel(u... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//#define __OUTPUT_PIX__
#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];
__global__ void convert_to_luv_gpu_kernel(u... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25convert_to_luv_gpu_kernelPhPfiib
.globl _Z25convert_to_luv_gpu_kernelPhPfiib
.p2align 8
.type _Z25convert_to_luv_gpu_kernelPhPfiib,@function
_Z25convert_to_luv_gpu_kernelPhPfiib:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//#define __OUTPUT_PIX__
#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];
__global__ void convert_to_luv_gpu_kernel(u... | .text
.file "convert_to_luv_gpu_kernel.hip"
.globl _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib # -- Begin function _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib
.p2align 4, 0x90
.type _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib,@function
_Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib: # @_Z40... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25convert_to_luv_gpu_kernelPhPfiib
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x000000000003791... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25convert_to_luv_gpu_kernelPhPfiib
.globl _Z25convert_to_luv_gpu_kernelPhPfiib
.p2align 8
.type _Z25convert_to_luv_gpu_kernelPhPfiib,@function
_Z25convert_to_luv_gpu_kernelPhPfiib:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00172874_00000000-6_convert_to_luv_gpu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@... | .text
.file "convert_to_luv_gpu_kernel.hip"
.globl _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib # -- Begin function _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib
.p2align 4, 0x90
.type _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib,@function
_Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib: # @_Z40... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <string>
/*
struct PointCloud {
utility::device_vector<Eigen::Vector3f> points_;
};
namespace ply_pointcloud_reader {
struct PLYReaderState {
utility::ConsoleProgressBar *progress_bar;
HostPointCloud *pointcloud_ptr;
long vertex_index;
long vertex_num;
long normal_index;
long normal_num;
long color_index;
long... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <string>
/*
struct PointCloud {
utility::device_vector<Eigen::Vector3f> points_;
};
namespace ply_pointcloud_reader {
struct PLYReaderState {
utility::ConsoleProgressBar *progress_bar;
HostPointCloud *pointcloud_ptr;
long vertex_index;
long vertex_num;
long normal_index;
long normal_num;
long color_index;
long... | .file "tmpxft_000d2302_00000000-6_01_read_ply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <string>
/*
struct PointCloud {
utility::device_vector<Eigen::Vector3f> points_;
};
namespace ply_pointcloud_reader {
struct PLYReaderState {
utility::ConsoleProgressBar *progress_bar;
HostPointCloud *pointcloud_ptr;
long vertex_index;
long vertex_num;
long normal_index;
long normal_num;
long color_index;
long... | #include <hip/hip_runtime.h>
#include <string>
/*
struct PointCloud {
utility::device_vector<Eigen::Vector3f> points_;
};
namespace ply_pointcloud_reader {
struct PLYReaderState {
utility::ConsoleProgressBar *progress_bar;
HostPointCloud *pointcloud_ptr;
long vertex_index;
long vertex_num;
long normal_index;
long norma... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <string>
/*
struct PointCloud {
utility::device_vector<Eigen::Vector3f> points_;
};
namespace ply_pointcloud_reader {
struct PLYReaderState {
utility::ConsoleProgressBar *progress_bar;
HostPointCloud *pointcloud_ptr;
long vertex_index;
long vertex_num;
long normal_index;
long norma... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <string>
/*
struct PointCloud {
utility::device_vector<Eigen::Vector3f> points_;
};
namespace ply_pointcloud_reader {
struct PLYReaderState {
utility::ConsoleProgressBar *progress_bar;
HostPointCloud *pointcloud_ptr;
long vertex_index;
long vertex_num;
long normal_index;
long norma... | .text
.file "01_read_ply.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
#... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d2302_00000000-6_01_read_ply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... | .text
.file "01_read_ply.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
#... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gradientRowsKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[ROWS_GRAD_BLOCKDIM_Z][ROWS_GRAD_BLOCKDIM_Y][(ROWS_GRAD_RESULT_STEPS + 2 * ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X];
//Offset to the left halo edge
const int baseX = (... | code for sm_80
Function : _Z18gradientRowsKernelPfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e2200000026... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gradientRowsKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[ROWS_GRAD_BLOCKDIM_Z][ROWS_GRAD_BLOCKDIM_Y][(ROWS_GRAD_RESULT_STEPS + 2 * ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X];
//Offset to the left halo edge
const int baseX = (... | .file "tmpxft_00033b4f_00000000-6_gradientRowsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
add... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gradientRowsKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[ROWS_GRAD_BLOCKDIM_Z][ROWS_GRAD_BLOCKDIM_Y][(ROWS_GRAD_RESULT_STEPS + 2 * ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X];
//Offset to the left halo edge
const int baseX = (... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gradientRowsKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[ROWS_GRAD_BLOCKDIM_Z][ROWS_GRAD_BLOCKDIM_Y][(ROWS_GRAD_RESULT_STEPS + 2 * ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X];
//Offset to the left ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gradientRowsKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[ROWS_GRAD_BLOCKDIM_Z][ROWS_GRAD_BLOCKDIM_Y][(ROWS_GRAD_RESULT_STEPS + 2 * ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X];
//Offset to the left ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18gradientRowsKernelPfS_iii
.globl _Z18gradientRowsKernelPfS_iii
.p2align 8
.type _Z18gradientRowsKernelPfS_iii,@function
_Z18gradientRowsKernelPfS_iii:
s_load_b128 s[4:7], s[0:1], 0x8
v_bfe_u32 v5, v0, 20, 10
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u3... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gradientRowsKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[ROWS_GRAD_BLOCKDIM_Z][ROWS_GRAD_BLOCKDIM_Y][(ROWS_GRAD_RESULT_STEPS + 2 * ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X];
//Offset to the left ... | .text
.file "gradientRowsKernel.hip"
.globl _Z33__device_stub__gradientRowsKernelPfS_iii # -- Begin function _Z33__device_stub__gradientRowsKernelPfS_iii
.p2align 4, 0x90
.type _Z33__device_stub__gradientRowsKernelPfS_iii,@function
_Z33__device_stub__gradientRowsKernelPfS_iii: # @_Z33__device_stub__gradientRowsKernelPf... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18gradientRowsKernelPfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e2200000026... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18gradientRowsKernelPfS_iii
.globl _Z18gradientRowsKernelPfS_iii
.p2align 8
.type _Z18gradientRowsKernelPfS_iii,@function
_Z18gradientRowsKernelPfS_iii:
s_load_b128 s[4:7], s[0:1], 0x8
v_bfe_u32 v5, v0, 20, 10
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u3... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00033b4f_00000000-6_gradientRowsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
add... | .text
.file "gradientRowsKernel.hip"
.globl _Z33__device_stub__gradientRowsKernelPfS_iii # -- Begin function _Z33__device_stub__gradientRowsKernelPfS_iii
.p2align 4, 0x90
.type _Z33__device_stub__gradientRowsKernelPfS_iii,@function
_Z33__device_stub__gradientRowsKernelPfS_iii: # @_Z33__device_stub__gradientRowsKernelPf... |
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