system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cuda.h>
static const int ThreadsPerBlock = 512;
static int* d_maxlen;
static __global__ void collatz(const long start, const long stop, int* const maxlen)
{
// todo: process odd values from start (assume start to be odd) to stop (inclusively if stop is odd) with one thread per value (based on code from previous project)
const long i = threadIdx.x + blockIdx.x * (long)blockDim.x;
if(i+start < stop ) // Each thread does work if and only if less than the stop value
{
long val = 2*(i +((start-1)/2))+1;
int len = 1;
while(val != 1){
len++;
if((val % 2) == 0)//even
{val = val / 2;}
else //Odd
{val = 3 * val +1;}
} if(len > *maxlen){ atomicMax(maxlen, len);} // If greater than greatest length, becomes new max len;
}
}
void GPU_Init()
{
int maxlen = 0;
if (cudaSuccess != cudaMalloc((void **)&d_maxlen, sizeof(int))) {fprintf(stderr, "ERROR: could not allocate memory\n"); exit(-1);}
if (cudaSuccess != cudaMemcpy(d_maxlen, &maxlen, sizeof(int), cudaMemcpyHostToDevice)) {fprintf(stderr, "ERROR: copying to device failed\n"); exit(-1);}
}
void GPU_Exec(const long start, const long stop)
{
if (start <= stop) {
collatz<<<((stop - start + 2) / 2 + ThreadsPerBlock - 1) / ThreadsPerBlock, ThreadsPerBlock>>>(start, stop, d_maxlen);
}
}
int GPU_Fini()
{
int maxlen;
// todo: copy the result from the device to the host and free the device memory
if(cudaSuccess != cudaMemcpy(&maxlen, d_maxlen, sizeof(int), cudaMemcpyDeviceToHost)){fprintf(stderr, "Error: copying to host failed\n"); exit(-1);}
cudaFree(d_maxlen);
return maxlen;
} | #include <cstdio>
#include <hip/hip_runtime.h>
static const int ThreadsPerBlock = 512;
static int* d_maxlen;
static __global__ void collatz(const long start, const long stop, int* const maxlen)
{
// todo: process odd values from start (assume start to be odd) to stop (inclusively if stop is odd) with one thread per value (based on code from previous project)
const long i = threadIdx.x + blockIdx.x * (long)blockDim.x;
if(i+start < stop ) // Each thread does work if and only if less than the stop value
{
long val = 2*(i +((start-1)/2))+1;
int len = 1;
while(val != 1){
len++;
if((val % 2) == 0)//even
{val = val / 2;}
else //Odd
{val = 3 * val +1;}
} if(len > *maxlen){ atomicMax(maxlen, len);} // If greater than greatest length, becomes new max len;
}
}
void GPU_Init()
{
int maxlen = 0;
if (hipSuccess != hipMalloc((void **)&d_maxlen, sizeof(int))) {fprintf(stderr, "ERROR: could not allocate memory\n"); exit(-1);}
if (hipSuccess != hipMemcpy(d_maxlen, &maxlen, sizeof(int), hipMemcpyHostToDevice)) {fprintf(stderr, "ERROR: copying to device failed\n"); exit(-1);}
}
void GPU_Exec(const long start, const long stop)
{
if (start <= stop) {
collatz<<<((stop - start + 2) / 2 + ThreadsPerBlock - 1) / ThreadsPerBlock, ThreadsPerBlock>>>(start, stop, d_maxlen);
}
}
int GPU_Fini()
{
int maxlen;
// todo: copy the result from the device to the host and free the device memory
if(hipSuccess != hipMemcpy(&maxlen, d_maxlen, sizeof(int), hipMemcpyDeviceToHost)){fprintf(stderr, "Error: copying to host failed\n"); exit(-1);}
hipFree(d_maxlen);
return maxlen;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <cstdio>
#include <hip/hip_runtime.h>
static const int ThreadsPerBlock = 512;
static int* d_maxlen;
static __global__ void collatz(const long start, const long stop, int* const maxlen)
{
// todo: process odd values from start (assume start to be odd) to stop (inclusively if stop is odd) with one thread per value (based on code from previous project)
const long i = threadIdx.x + blockIdx.x * (long)blockDim.x;
if(i+start < stop ) // Each thread does work if and only if less than the stop value
{
long val = 2*(i +((start-1)/2))+1;
int len = 1;
while(val != 1){
len++;
if((val % 2) == 0)//even
{val = val / 2;}
else //Odd
{val = 3 * val +1;}
} if(len > *maxlen){ atomicMax(maxlen, len);} // If greater than greatest length, becomes new max len;
}
}
void GPU_Init()
{
int maxlen = 0;
if (hipSuccess != hipMalloc((void **)&d_maxlen, sizeof(int))) {fprintf(stderr, "ERROR: could not allocate memory\n"); exit(-1);}
if (hipSuccess != hipMemcpy(d_maxlen, &maxlen, sizeof(int), hipMemcpyHostToDevice)) {fprintf(stderr, "ERROR: copying to device failed\n"); exit(-1);}
}
void GPU_Exec(const long start, const long stop)
{
if (start <= stop) {
collatz<<<((stop - start + 2) / 2 + ThreadsPerBlock - 1) / ThreadsPerBlock, ThreadsPerBlock>>>(start, stop, d_maxlen);
}
}
int GPU_Fini()
{
int maxlen;
// todo: copy the result from the device to the host and free the device memory
if(hipSuccess != hipMemcpy(&maxlen, d_maxlen, sizeof(int), hipMemcpyDeviceToHost)){fprintf(stderr, "Error: copying to host failed\n"); exit(-1);}
hipFree(d_maxlen);
return maxlen;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL7collatzllPi,"axG",@progbits,_ZL7collatzllPi,comdat
.globl _ZL7collatzllPi
.p2align 8
.type _ZL7collatzllPi,@function
_ZL7collatzllPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s15, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB0_14
s_add_u32 s2, s4, -1
s_addc_u32 s3, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s4, s3, 31
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, 0
s_mov_b32 s4, 1
s_ashr_i64 s[2:3], s[2:3], 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_mov_b32_e32 v2, 1
s_mov_b32 s3, 0
s_mov_b32 s2, exec_lo
v_cmpx_ne_u64_e32 0, v[0:1]
s_cbranch_execz .LBB0_9
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v0, 1, v0
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u64_e32 vcc_lo, 1, v[0:1]
s_add_i32 s4, s4, 1
v_mov_b32_e32 v2, s4
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_8
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, 1, v0
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 1, v2
s_xor_b32 s5, exec_lo, s5
v_mad_u64_u32 v[2:3], null, v0, 3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v3
v_mad_u64_u32 v[3:4], null, v1, 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i64 v[0:1], 1, v[0:1]
s_branch .LBB0_3
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_mov_b32 s3, exec_lo
s_brev_b32 s2, 1
.LBB0_11:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v2, s4
s_lshl_b32 s4, 1, s4
s_and_not1_b32 s3, s3, s4
s_delay_alu instid0(VALU_DEP_1)
s_max_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_11
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_14
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_atomic_max_i32 v0, v1, s[0:1]
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL7collatzllPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL7collatzllPi,"axG",@progbits,_ZL7collatzllPi,comdat
.Lfunc_end0:
.size _ZL7collatzllPi, .Lfunc_end0-_ZL7collatzllPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL7collatzllPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL7collatzllPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <cstdio>
#include <hip/hip_runtime.h>
static const int ThreadsPerBlock = 512;
static int* d_maxlen;
static __global__ void collatz(const long start, const long stop, int* const maxlen)
{
// todo: process odd values from start (assume start to be odd) to stop (inclusively if stop is odd) with one thread per value (based on code from previous project)
const long i = threadIdx.x + blockIdx.x * (long)blockDim.x;
if(i+start < stop ) // Each thread does work if and only if less than the stop value
{
long val = 2*(i +((start-1)/2))+1;
int len = 1;
while(val != 1){
len++;
if((val % 2) == 0)//even
{val = val / 2;}
else //Odd
{val = 3 * val +1;}
} if(len > *maxlen){ atomicMax(maxlen, len);} // If greater than greatest length, becomes new max len;
}
}
void GPU_Init()
{
int maxlen = 0;
if (hipSuccess != hipMalloc((void **)&d_maxlen, sizeof(int))) {fprintf(stderr, "ERROR: could not allocate memory\n"); exit(-1);}
if (hipSuccess != hipMemcpy(d_maxlen, &maxlen, sizeof(int), hipMemcpyHostToDevice)) {fprintf(stderr, "ERROR: copying to device failed\n"); exit(-1);}
}
void GPU_Exec(const long start, const long stop)
{
if (start <= stop) {
collatz<<<((stop - start + 2) / 2 + ThreadsPerBlock - 1) / ThreadsPerBlock, ThreadsPerBlock>>>(start, stop, d_maxlen);
}
}
int GPU_Fini()
{
int maxlen;
// todo: copy the result from the device to the host and free the device memory
if(hipSuccess != hipMemcpy(&maxlen, d_maxlen, sizeof(int), hipMemcpyDeviceToHost)){fprintf(stderr, "Error: copying to host failed\n"); exit(-1);}
hipFree(d_maxlen);
return maxlen;
} | .text
.file "collatz_hyb.hip"
.globl _Z8GPU_Initv # -- Begin function _Z8GPU_Initv
.p2align 4, 0x90
.type _Z8GPU_Initv,@function
_Z8GPU_Initv: # @_Z8GPU_Initv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $0, 4(%rsp)
movl $_ZL8d_maxlen, %edi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_1
# %bb.3:
movq _ZL8d_maxlen(%rip), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_4
# %bb.5:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $33, %esi
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $32, %esi
.LBB0_2:
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z8GPU_Initv, .Lfunc_end0-_Z8GPU_Initv
.cfi_endproc
# -- End function
.globl _Z8GPU_Execll # -- Begin function _Z8GPU_Execll
.p2align 4, 0x90
.type _Z8GPU_Execll,@function
_Z8GPU_Execll: # @_Z8GPU_Execll
.cfi_startproc
# %bb.0:
movq %rsi, %rax
subq %rdi, %rax
jl .LBB1_4
# %bb.1:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
leaq 2(%rax), %rcx
shrq $63, %rcx
addq %rcx, %rax
addq $2, %rax
sarq %rax
leaq 511(%rax), %rcx
addq $1022, %rax # imm = 0x3FE
testq %rcx, %rcx
cmovnsq %rcx, %rax
shrq $9, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
movq _ZL8d_maxlen(%rip), %rax
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
movq %rax, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL7collatzllPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB1_4:
retq
.Lfunc_end1:
.size _Z8GPU_Execll, .Lfunc_end1-_Z8GPU_Execll
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL22__device_stub__collatzllPi
.type _ZL22__device_stub__collatzllPi,@function
_ZL22__device_stub__collatzllPi: # @_ZL22__device_stub__collatzllPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL7collatzllPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _ZL22__device_stub__collatzllPi, .Lfunc_end2-_ZL22__device_stub__collatzllPi
.cfi_endproc
# -- End function
.globl _Z8GPU_Finiv # -- Begin function _Z8GPU_Finiv
.p2align 4, 0x90
.type _Z8GPU_Finiv,@function
_Z8GPU_Finiv: # @_Z8GPU_Finiv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq _ZL8d_maxlen(%rip), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq _ZL8d_maxlen(%rip), %rdi
callq hipFree
movl 4(%rsp), %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $30, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end3:
.size _Z8GPU_Finiv, .Lfunc_end3-_Z8GPU_Finiv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL7collatzllPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL8d_maxlen,@object # @_ZL8d_maxlen
.local _ZL8d_maxlen
.comm _ZL8d_maxlen,8,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR: could not allocate memory\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ERROR: copying to device failed\n"
.size .L.str.1, 33
.type _ZL7collatzllPi,@object # @_ZL7collatzllPi
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL7collatzllPi:
.quad _ZL22__device_stub__collatzllPi
.size _ZL7collatzllPi, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Error: copying to host failed\n"
.size .L.str.2, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL7collatzllPi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL22__device_stub__collatzllPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL8d_maxlen
.addrsig_sym _ZL7collatzllPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7collatzllPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0040*/ IMAD.WIDE.U32 R4, R5, c[0x0][0x0], R2 ; /* 0x0000000005047a25 */
/* 0x001fca00078e0002 */
/*0050*/ IADD3 R0, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004007a10 */
/* 0x000fc80007f3e0ff */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0070*/ IADD3.X R0, R5, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005007a10 */
/* 0x000fc80000ffe4ff */
/*0080*/ ISETP.GE.AND.EX P0, PT, R0, c[0x0][0x16c], PT, P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06300 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*00d0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*00e0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000802077981 */
/* 0x000162000c1e1900 */
/*0100*/ UIADD3 UR4, UP0, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe2000ff1e13f */
/*0110*/ BSSY B0, 0x310 ; /* 0x000001f000007945 */
/* 0x000fe20003800000 */
/*0120*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fc400078e00ff */
/*0130*/ UIADD3.X UR5, UR7, -0x1, URZ, UP0, !UPT ; /* 0xffffffff07057890 */
/* 0x000fc800087fe43f */
/*0140*/ ULEA.HI UR4, UP0, UR5, UR4, URZ, 0x1 ; /* 0x0000000405047291 */
/* 0x000fc8000f81083f */
/*0150*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fc800087fe43f */
/*0160*/ USHF.R.S64 UR4, UR4, 0x1, UR5 ; /* 0x0000000104047899 */
/* 0x000fe40008001005 */
/*0170*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fc80008011405 */
/*0180*/ IADD3 R8, P0, R4, UR4, RZ ; /* 0x0000000404087c10 */
/* 0x000fc8000ff1e0ff */
/*0190*/ IADD3.X R5, R5, UR5, RZ, P0, !PT ; /* 0x0000000505057c10 */
/* 0x000fe400087fe4ff */
/*01a0*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*01b0*/ ISETP.NE.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0003f05300 */
/*01c0*/ @!P0 BRA 0x300 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.SHL.U32 R4, R8.reuse, 0x2, RZ ; /* 0x0000000208047824 */
/* 0x041fe200078e00ff */
/*01e0*/ SHF.L.U64.HI R8, R8, 0x1, R5 ; /* 0x0000000108087819 */
/* 0x000fe20000010205 */
/*01f0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fc600078e00ff */
/*0200*/ LOP3.LUT R4, R4, 0x1, RZ, 0xfc, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078efcff */
/*0210*/ LOP3.LUT R5, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104057812 */
/* 0x000fe400078ec0ff */
/*0220*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.NE.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fc80003f05070 */
/*0240*/ ISETP.NE.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05100 */
/*0250*/ @P0 LEA.HI R6, P1, R8.reuse, R4, RZ, 0x1 ; /* 0x0000000408060211 */
/* 0x040fe200078308ff */
/*0260*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x3 ; /* 0x00000003ff058424 */
/* 0x000fe400078e00ff */
/*0270*/ @!P0 IMAD R11, R8, 0x3, RZ ; /* 0x00000003080b8824 */
/* 0x000fe400078e02ff */
/*0280*/ @P0 IMAD.X R9, RZ, RZ, R8, P1 ; /* 0x000000ffff090224 */
/* 0x000fe400008e0608 */
/*0290*/ @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x2][0x0] ; /* 0x0080000004048625 */
/* 0x000fc600078e0005 */
/*02a0*/ @P0 SHF.R.S64 R4, R6, 0x1, R9 ; /* 0x0000000106040819 */
/* 0x000fe20000001009 */
/*02b0*/ @!P0 IMAD.IADD R8, R5, 0x1, R11 ; /* 0x0000000105088824 */
/* 0x000fe200078e020b */
/*02c0*/ @P0 SHF.R.S32.HI R8, RZ, 0x1, R9 ; /* 0x00000001ff080819 */
/* 0x000fe40000011409 */
/*02d0*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc80003f05070 */
/*02e0*/ ISETP.NE.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f05300 */
/*02f0*/ @P0 BRA 0x210 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0310*/ ISETP.GT.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f04270 */
/*0320*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0330*/ S2R R4, SR_LANEID ; /* 0x0000000000047919 */
/* 0x000e220000000000 */
/*0340*/ REDUX.MAX.S32 UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000e620000014200 */
/*0350*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0360*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*0370*/ ISETP.EQ.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x001fe2000bf02070 */
/*0380*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x002fd8000f8e00ff */
/*0390*/ @P0 RED.E.MAX.S32.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x000fe2000d10e388 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL7collatzllPi,"axG",@progbits,_ZL7collatzllPi,comdat
.globl _ZL7collatzllPi
.p2align 8
.type _ZL7collatzllPi,@function
_ZL7collatzllPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s15, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 s[6:7], v[0:1]
s_cbranch_execz .LBB0_14
s_add_u32 s2, s4, -1
s_addc_u32 s3, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s4, s3, 31
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, 0
s_mov_b32 s4, 1
s_ashr_i64 s[2:3], s[2:3], 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_mov_b32_e32 v2, 1
s_mov_b32 s3, 0
s_mov_b32 s2, exec_lo
v_cmpx_ne_u64_e32 0, v[0:1]
s_cbranch_execz .LBB0_9
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v0, 1, v0
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u64_e32 vcc_lo, 1, v[0:1]
s_add_i32 s4, s4, 1
v_mov_b32_e32 v2, s4
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_8
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, 1, v0
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 1, v2
s_xor_b32 s5, exec_lo, s5
v_mad_u64_u32 v[2:3], null, v0, 3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v3
v_mad_u64_u32 v[3:4], null, v1, 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i64 v[0:1], 1, v[0:1]
s_branch .LBB0_3
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_mov_b32 s3, exec_lo
s_brev_b32 s2, 1
.LBB0_11:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v2, s4
s_lshl_b32 s4, 1, s4
s_and_not1_b32 s3, s3, s4
s_delay_alu instid0(VALU_DEP_1)
s_max_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_11
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_14
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_atomic_max_i32 v0, v1, s[0:1]
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL7collatzllPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL7collatzllPi,"axG",@progbits,_ZL7collatzllPi,comdat
.Lfunc_end0:
.size _ZL7collatzllPi, .Lfunc_end0-_ZL7collatzllPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL7collatzllPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL7collatzllPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000234b5_00000000-6_collatz_hyb.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL28__device_stub__Z7collatzllPillPi, @function
_ZL28__device_stub__Z7collatzllPillPi:
.LFB2084:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL7collatzllPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _ZL28__device_stub__Z7collatzllPillPi, .-_ZL28__device_stub__Z7collatzllPillPi
.type _ZL7collatzllPi, @function
_ZL7collatzllPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL28__device_stub__Z7collatzllPillPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL7collatzllPi, .-_ZL7collatzllPi
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "ERROR: could not allocate memory\n"
.align 8
.LC1:
.string "ERROR: copying to device failed\n"
.text
.globl _Z8GPU_Initv
.type _Z8GPU_Initv, @function
_Z8GPU_Initv:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
movl $4, %esi
leaq _ZL8d_maxlen(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L16
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq _ZL8d_maxlen(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L17
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L17:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8GPU_Initv, .-_Z8GPU_Initv
.globl _Z8GPU_Execll
.type _Z8GPU_Execll, @function
_Z8GPU_Execll:
.LFB2058:
.cfi_startproc
endbr64
cmpq %rsi, %rdi
jle .L26
ret
.L26:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movq %rsi, %rdx
subq %rdi, %rdx
addq $2, %rdx
movq %rdx, %rax
shrq $63, %rax
addq %rdx, %rax
sarq %rax
leaq 1022(%rax), %rdx
addq $511, %rax
cmovs %rdx, %rax
sarq $9, %rax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L19:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq _ZL8d_maxlen(%rip), %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZL28__device_stub__Z7collatzllPillPi
jmp .L19
.cfi_endproc
.LFE2058:
.size _Z8GPU_Execll, .-_Z8GPU_Execll
.section .rodata.str1.8
.align 8
.LC2:
.string "Error: copying to host failed\n"
.text
.globl _Z8GPU_Finiv
.type _Z8GPU_Finiv, @function
_Z8GPU_Finiv:
.LFB2059:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq _ZL8d_maxlen(%rip), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
movq _ZL8d_maxlen(%rip), %rdi
call cudaFree@PLT
movl 4(%rsp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L33
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z8GPU_Finiv, .-_Z8GPU_Finiv
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z7collatzllPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7collatzllPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8d_maxlen
.comm _ZL8d_maxlen,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "collatz_hyb.hip"
.globl _Z8GPU_Initv # -- Begin function _Z8GPU_Initv
.p2align 4, 0x90
.type _Z8GPU_Initv,@function
_Z8GPU_Initv: # @_Z8GPU_Initv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $0, 4(%rsp)
movl $_ZL8d_maxlen, %edi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_1
# %bb.3:
movq _ZL8d_maxlen(%rip), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_4
# %bb.5:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $33, %esi
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $32, %esi
.LBB0_2:
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z8GPU_Initv, .Lfunc_end0-_Z8GPU_Initv
.cfi_endproc
# -- End function
.globl _Z8GPU_Execll # -- Begin function _Z8GPU_Execll
.p2align 4, 0x90
.type _Z8GPU_Execll,@function
_Z8GPU_Execll: # @_Z8GPU_Execll
.cfi_startproc
# %bb.0:
movq %rsi, %rax
subq %rdi, %rax
jl .LBB1_4
# %bb.1:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
leaq 2(%rax), %rcx
shrq $63, %rcx
addq %rcx, %rax
addq $2, %rax
sarq %rax
leaq 511(%rax), %rcx
addq $1022, %rax # imm = 0x3FE
testq %rcx, %rcx
cmovnsq %rcx, %rax
shrq $9, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
movq _ZL8d_maxlen(%rip), %rax
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
movq %rax, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL7collatzllPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB1_4:
retq
.Lfunc_end1:
.size _Z8GPU_Execll, .Lfunc_end1-_Z8GPU_Execll
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL22__device_stub__collatzllPi
.type _ZL22__device_stub__collatzllPi,@function
_ZL22__device_stub__collatzllPi: # @_ZL22__device_stub__collatzllPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL7collatzllPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _ZL22__device_stub__collatzllPi, .Lfunc_end2-_ZL22__device_stub__collatzllPi
.cfi_endproc
# -- End function
.globl _Z8GPU_Finiv # -- Begin function _Z8GPU_Finiv
.p2align 4, 0x90
.type _Z8GPU_Finiv,@function
_Z8GPU_Finiv: # @_Z8GPU_Finiv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq _ZL8d_maxlen(%rip), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq _ZL8d_maxlen(%rip), %rdi
callq hipFree
movl 4(%rsp), %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $30, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end3:
.size _Z8GPU_Finiv, .Lfunc_end3-_Z8GPU_Finiv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL7collatzllPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL8d_maxlen,@object # @_ZL8d_maxlen
.local _ZL8d_maxlen
.comm _ZL8d_maxlen,8,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR: could not allocate memory\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ERROR: copying to device failed\n"
.size .L.str.1, 33
.type _ZL7collatzllPi,@object # @_ZL7collatzllPi
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL7collatzllPi:
.quad _ZL22__device_stub__collatzllPi
.size _ZL7collatzllPi, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Error: copying to host failed\n"
.size .L.str.2, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL7collatzllPi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL22__device_stub__collatzllPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL8d_maxlen
.addrsig_sym _ZL7collatzllPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.
*
*
* These example codes are a portion of the code samples from the companion
* website to the book "CUDA Fortran for Scientists and Engineers":
*
* http://store.elsevier.com/product.jsp?isbn=9780124169708
*
*/
extern "C" __global__ void zero(float *a)
{
a[blockIdx.x*blockDim.x+threadIdx.x] = 0.0;
} | code for sm_80
Function : zero
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.
*
*
* These example codes are a portion of the code samples from the companion
* website to the book "CUDA Fortran for Scientists and Engineers":
*
* http://store.elsevier.com/product.jsp?isbn=9780124169708
*
*/
extern "C" __global__ void zero(float *a)
{
a[blockIdx.x*blockDim.x+threadIdx.x] = 0.0;
} | .file "tmpxft_0009591c_00000000-6_zero.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4zeroPfPf
.type _Z23__device_stub__Z4zeroPfPf, @function
_Z23__device_stub__Z4zeroPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq zero(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z4zeroPfPf, .-_Z23__device_stub__Z4zeroPfPf
.globl zero
.type zero, @function
zero:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4zeroPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size zero, .-zero
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "zero"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq zero(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.
*
*
* These example codes are a portion of the code samples from the companion
* website to the book "CUDA Fortran for Scientists and Engineers":
*
* http://store.elsevier.com/product.jsp?isbn=9780124169708
*
*/
extern "C" __global__ void zero(float *a)
{
a[blockIdx.x*blockDim.x+threadIdx.x] = 0.0;
} | #include <hip/hip_runtime.h>
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.
*
*
* These example codes are a portion of the code samples from the companion
* website to the book "CUDA Fortran for Scientists and Engineers":
*
* http://store.elsevier.com/product.jsp?isbn=9780124169708
*
*/
extern "C" __global__ void zero(float *a)
{
a[blockIdx.x*blockDim.x+threadIdx.x] = 0.0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.
*
*
* These example codes are a portion of the code samples from the companion
* website to the book "CUDA Fortran for Scientists and Engineers":
*
* http://store.elsevier.com/product.jsp?isbn=9780124169708
*
*/
extern "C" __global__ void zero(float *a)
{
a[blockIdx.x*blockDim.x+threadIdx.x] = 0.0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected zero
.globl zero
.p2align 8
.type zero,@function
zero:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel zero
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size zero, .Lfunc_end0-zero
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: zero
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: zero.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.
*
*
* These example codes are a portion of the code samples from the companion
* website to the book "CUDA Fortran for Scientists and Engineers":
*
* http://store.elsevier.com/product.jsp?isbn=9780124169708
*
*/
extern "C" __global__ void zero(float *a)
{
a[blockIdx.x*blockDim.x+threadIdx.x] = 0.0;
} | .text
.file "zero.hip"
.globl __device_stub__zero # -- Begin function __device_stub__zero
.p2align 4, 0x90
.type __device_stub__zero,@function
__device_stub__zero: # @__device_stub__zero
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $zero, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__zero, .Lfunc_end0-__device_stub__zero
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $zero, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type zero,@object # @zero
.section .rodata,"a",@progbits
.globl zero
.p2align 3, 0x0
zero:
.quad __device_stub__zero
.size zero, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "zero"
.size .L__unnamed_1, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__zero
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym zero
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : zero
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected zero
.globl zero
.p2align 8
.type zero,@function
zero:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel zero
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size zero, .Lfunc_end0-zero
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: zero
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: zero.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009591c_00000000-6_zero.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4zeroPfPf
.type _Z23__device_stub__Z4zeroPfPf, @function
_Z23__device_stub__Z4zeroPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq zero(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z4zeroPfPf, .-_Z23__device_stub__Z4zeroPfPf
.globl zero
.type zero, @function
zero:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4zeroPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size zero, .-zero
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "zero"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq zero(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "zero.hip"
.globl __device_stub__zero # -- Begin function __device_stub__zero
.p2align 4, 0x90
.type __device_stub__zero,@function
__device_stub__zero: # @__device_stub__zero
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $zero, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__zero, .Lfunc_end0-__device_stub__zero
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $zero, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type zero,@object # @zero
.section .rodata,"a",@progbits
.globl zero
.p2align 3, 0x0
zero:
.quad __device_stub__zero
.size zero, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "zero"
.size .L__unnamed_1, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__zero
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym zero
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <stdint.h>
#define IN_FEATS 200
#define OUT_CLASSES 10
#define W_SIZE IN_FEATS * OUT_CLASSES
uint64_t getTimeMicroseconds64()
{
uint64_t nTime;
struct timespec tSpec;
clock_gettime(CLOCK_REALTIME, &tSpec);
nTime = (uint64_t)tSpec.tv_nsec / 1000;
return nTime;
}
__global__ void fwd_perc(float *in, float *out, float *weights, float *activations, float *activation_sum)
{
int b = blockIdx.x;
int t = threadIdx.x;
__shared__ float z[IN_FEATS], sum_z;
sum_z = 0;
__syncthreads();
z[t] = in[t] * weights[b * IN_FEATS + t];
atomicAdd(&sum_z, z[t]);
__syncthreads();
activation_sum[b] = sum_z;
activations[b * IN_FEATS + t ] = z[t];
if (sum_z < 0) { out[b] = 0; } else { out[b] = sum_z; }
}
__global__ void lrp_perc(float *out, float *relevance, float *activations, float *activation_sum)
{
int b = blockIdx.x;
int t = threadIdx.x;
__shared__ float z[OUT_CLASSES], rel, sum_z[OUT_CLASSES], r_m[OUT_CLASSES];
z[t] = activations[t * IN_FEATS + b];
rel = 0;
sum_z[t] = activation_sum[t];
r_m[t] = out[t];
__syncthreads();
atomicAdd(&rel, z[t] * r_m[t] / sum_z[t]);
__syncthreads();
relevance[b] = rel;
}
void lrp_perc_gm(float *in, float *out, float *relevance, float *weights, float *activations, float *activation_sum, int n, int m)
{
for (int j = 0; j < m; j++) {
for (int i_prime = 0; i_prime < n; i_prime++) {
activations[j * n + i_prime] = in[i_prime] * weights[j * n + i_prime];
activation_sum[j] += activations[j * n + i_prime];
}
if (activation_sum[j] < 0) { out[j] = 0; } else { out[j] = activation_sum[j]; }
}
for (int i = 0; i < n; i++) {
for (int j = 0; j < m; j++) {
relevance[i] += (activations[j * n + i] * out[j]) / activation_sum[j];
}
}
}
int main(void)
{
uint64_t dT1 = 0, dT2 = 0, hT1 = 0, hT2 = 0;
float input[IN_FEATS], golden_out[OUT_CLASSES], cuda_out[OUT_CLASSES], weights[W_SIZE], golden_relevance[IN_FEATS], cuda_relevance[IN_FEATS], golden_activations[W_SIZE], cuda_activations[W_SIZE], golden_asum[OUT_CLASSES], cuda_asum[OUT_CLASSES];
cudaError_t s;
// initialize variables on host
for (int i = 0; i < IN_FEATS; i++) {
input[i] = rand() % 10;
golden_relevance[i] = 0;
cuda_relevance[i] = 0;
for (int j = 0; j < OUT_CLASSES; j++) {
weights[j * IN_FEATS + i] = rand() % 10;
golden_activations[j * IN_FEATS + i] = 0;
cuda_activations[j * IN_FEATS + i] = 0;
}
}
for (int i = 0; i < OUT_CLASSES; i++) {
golden_out[i] = 0;
cuda_out[i] = 0;
golden_asum[i] = 0;
cuda_asum[i] = 0;
}
// allocating memory for variables for device
float *input_, *weights_, *output_, *relevance_, *activations_, *asum_;
cudaMalloc(&input_, IN_FEATS * sizeof(float));
cudaMalloc(&weights_, W_SIZE * sizeof(float));
cudaMalloc(&output_, OUT_CLASSES * sizeof(float));
cudaMalloc(&relevance_, IN_FEATS * sizeof(float));
cudaMalloc(&activations_, W_SIZE * sizeof(float));
cudaMalloc(&asum_, OUT_CLASSES * sizeof(float));
// run version with static shared memory
cudaMemcpy(input_, input, IN_FEATS * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(weights_, weights, W_SIZE *sizeof(float), cudaMemcpyHostToDevice);
cudaMemset(output_, 0, OUT_CLASSES * sizeof(float));
cudaMemset(relevance_, 0, IN_FEATS * sizeof(float));
cudaMemset(activations_, 0, W_SIZE * sizeof(float));
cudaMemset(asum_, 0, OUT_CLASSES * sizeof(float));
// run cuda kernel and host function and compare the results
hT1 = getTimeMicroseconds64();
lrp_perc_gm(input, golden_out, golden_relevance, weights, golden_activations, golden_asum, IN_FEATS, OUT_CLASSES);
hT2 = getTimeMicroseconds64();
dT1 = getTimeMicroseconds64();
fwd_perc<<<OUT_CLASSES, IN_FEATS>>>(input_, output_, weights_, activations_, asum_);
lrp_perc<<<IN_FEATS, OUT_CLASSES>>>(output_, relevance_, activations_, asum_);
s = cudaDeviceSynchronize();
dT2 = getTimeMicroseconds64();
printf("%s\n", cudaGetErrorName(s));
// relvance
printf("### RELEVANCE ###\n");
s = cudaMemcpyAsync(cuda_relevance, relevance_, IN_FEATS * sizeof(float), cudaMemcpyDeviceToHost);
printf("%s\n", cudaGetErrorName(s));
for (int i = 0; i < IN_FEATS; i++) {
if (golden_relevance[i] != cuda_relevance[i]) {
printf("Error: golden_relevance[%d]!=cuda_relevance[%d] (%f, %f)\n", i, i, golden_relevance[i], cuda_relevance[i]);
}
}
// out
printf("### OUT ###\n");
s = cudaMemcpy(cuda_out, output_, OUT_CLASSES * sizeof(float), cudaMemcpyDeviceToHost);
printf("%s\n", cudaGetErrorName(s));
for (int i = 0; i < OUT_CLASSES; i++) {
if (golden_out[i] != cuda_out[i]) {
printf("Error: golden_out[%d]!=cuda_out[%d] (%f, %f)\n", i, i, golden_out[i], cuda_out[i]);
}
}
// activations
printf("### ACTIVATIONS ###\n");
s = cudaMemcpy(cuda_activations, activations_, W_SIZE * sizeof(float), cudaMemcpyDeviceToHost);
printf("%s\n", cudaGetErrorName(s));
for (int i = 0; i < W_SIZE; i++) {
if (golden_activations[i] != cuda_activations[i]) {
printf("Error: golden_activations[%d]!=cuda_activations[%d] (%f, %f)\n", i, i, golden_activations[i], cuda_activations[i]);
}
}
// asum
printf("### ASUM ###\n");
s = cudaMemcpy(cuda_asum, asum_, OUT_CLASSES * sizeof(float), cudaMemcpyDeviceToHost);
printf("%s\n", cudaGetErrorName(s));
for (int i = 0; i < OUT_CLASSES; i++) {
if (golden_asum[i] != cuda_asum[i]) {
printf("Error: golden_asum[%d]!=cuda_asum[%d] (%f, %f)\n", i, i, golden_asum[i], cuda_asum[i]);
}
}
printf("GPU time: %lu, \tCPU time: %lu\n", (dT2 - dT1) << 16, (hT2 - hT1) << 16);
cudaFree(input_);
cudaFree(weights_);
cudaFree(output_);
cudaFree(relevance_);
cudaFree(activations_);
cudaFree(asum_);
} | code for sm_80
Function : _Z8lrp_percPfS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R13.reuse, 0xc8, R0 ; /* 0x000000c80d027824 */
/* 0x041fe400078e0200 */
/*0060*/ IMAD.WIDE R4, R13, R6, c[0x0][0x178] ; /* 0x00005e000d047625 */
/* 0x000fc800078e0206 */
/*0070*/ IMAD.WIDE R2, R2, R6.reuse, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x080fe400078e0206 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0090*/ IMAD.WIDE R6, R13, R6, c[0x0][0x160] ; /* 0x000058000d067625 */
/* 0x000fe400078e0206 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee8000c1e1900 */
/*00b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*00c0*/ BSSY B0, 0x220 ; /* 0x0000015000007945 */
/* 0x000fe60003800000 */
/*00d0*/ STS [R13.X4], R2 ; /* 0x000000020d007388 */
/* 0x008fe80000004800 */
/*00e0*/ STS [0x28], RZ ; /* 0x000028ffff007388 */
/* 0x000fe80000000800 */
/*00f0*/ STS [R13.X4+0x2c], R4 ; /* 0x00002c040d007388 */
/* 0x004fe80000004800 */
/*0100*/ STS [R13.X4+0x54], R6 ; /* 0x000054060d007388 */
/* 0x010fe80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ LDS R11, [R13.X4+0x2c] ; /* 0x00002c000d0b7984 */
/* 0x000e280000004800 */
/*0130*/ LDS R8, [R13.X4] ; /* 0x000000000d087984 */
/* 0x000fe80000004800 */
/*0140*/ LDS R9, [R13.X4+0x54] ; /* 0x000054000d097984 */
/* 0x000e620000004800 */
/*0150*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x001e220000001000 */
/*0160*/ FMUL R8, R8, R9 ; /* 0x0000000908087220 */
/* 0x002fce0000400000 */
/*0170*/ FCHK P0, R8, R11 ; /* 0x0000000b08007302 */
/* 0x000e620000000000 */
/*0180*/ FFMA R3, -R11, R10, 1 ; /* 0x3f8000000b037423 */
/* 0x001fc8000000010a */
/*0190*/ FFMA R3, R10, R3, R10 ; /* 0x000000030a037223 */
/* 0x000fc8000000000a */
/*01a0*/ FFMA R2, R8, R3, RZ ; /* 0x0000000308027223 */
/* 0x000fc800000000ff */
/*01b0*/ FFMA R4, -R11, R2, R8 ; /* 0x000000020b047223 */
/* 0x000fc80000000108 */
/*01c0*/ FFMA R2, R3, R4, R2 ; /* 0x0000000403027223 */
/* 0x000fe20000000002 */
/*01d0*/ @!P0 BRA 0x210 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*01e0*/ MOV R2, 0x200 ; /* 0x0000020000027802 */
/* 0x000fe40000000f00 */
/*01f0*/ CALL.REL.NOINC 0x2f0 ; /* 0x000000f000007944 */
/* 0x000fea0003c00000 */
/*0200*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ BSSY B0, 0x290 ; /* 0x0000006000007945 */
/* 0x000fe40003800000 */
/*0230*/ LDS R4, [0x28] ; /* 0x00002800ff047984 */
/* 0x000e240000000800 */
/*0240*/ FADD R5, R2, R4 ; /* 0x0000000402057221 */
/* 0x001fcc0000000000 */
/*0250*/ ATOMS.CAST.SPIN R5, [0x28], R4, R5 ; /* 0x00002804ff05738d */
/* 0x000e240001800005 */
/*0260*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x001fda0003f02070 */
/*0270*/ @!P0 BRA 0x230 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0203 */
/*02c0*/ LDS R5, [0x28] ; /* 0x00002800ff057984 */
/* 0x000e280000000800 */
/*02d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ SHF.R.U32.HI R4, RZ, 0x17, R11.reuse ; /* 0x00000017ff047819 */
/* 0x100fe2000001160b */
/*0300*/ BSSY B1, 0x950 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0310*/ SHF.R.U32.HI R3, RZ, 0x17, R8.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011608 */
/*0320*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0008 */
/*0330*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe200078ec0ff */
/*0340*/ IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000b */
/*0350*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fc400078ec0ff */
/*0360*/ IADD3 R10, R4, -0x1, RZ ; /* 0xffffffff040a7810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IADD3 R9, R3, -0x1, RZ ; /* 0xffffffff03097810 */
/* 0x000fe40007ffe0ff */
/*0380*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*0390*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*03a0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*03b0*/ @!P0 BRA 0x530 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*03c0*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*03d0*/ FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fc80003f3c200 */
/*03e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*03f0*/ @P0 BRA 0x930 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0410*/ @!P0 BRA 0x910 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; /* 0x7f8000000800780b */
/* 0x040fe40003f5d200 */
/*0430*/ FSETP.NEU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f3d200 */
/*0440*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*0450*/ @!P1 BRA !P2, 0x910 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0460*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*0470*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0480*/ @P1 BRA 0x8f0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0490*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*04a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*04b0*/ @P0 BRA 0x8c0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*04c0*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*04d0*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*04e0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*04f0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0500*/ @!P0 FFMA R5, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008058823 */
/* 0x000fe400000000ff */
/*0510*/ @!P1 FFMA R6, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b069823 */
/* 0x000fe200000000ff */
/*0520*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0530*/ LEA R9, R4, 0xc0800000, 0x17 ; /* 0xc080000004097811 */
/* 0x000fe200078eb8ff */
/*0540*/ BSSY B2, 0x8b0 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0550*/ IMAD.IADD R9, R6, 0x1, -R9 ; /* 0x0000000106097824 */
/* 0x000fe200078e0a09 */
/*0560*/ IADD3 R6, R3, -0x7f, RZ ; /* 0xffffff8103067810 */
/* 0x000fc60007ffe0ff */
/*0570*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e220000001000 */
/*0580*/ FADD.FTZ R10, -R9, -RZ ; /* 0x800000ff090a7221 */
/* 0x000fe40000010100 */
/*0590*/ IMAD R5, R6.reuse, -0x800000, R5 ; /* 0xff80000006057824 */
/* 0x040fe200078e0205 */
/*05a0*/ IADD3 R6, R6, 0x7f, -R4 ; /* 0x0000007f06067810 */
/* 0x000fca0007ffe804 */
/*05b0*/ IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106067824 */
/* 0x000fe400078e0207 */
/*05c0*/ FFMA R3, R8, R10, 1 ; /* 0x3f80000008037423 */
/* 0x001fc8000000000a */
/*05d0*/ FFMA R12, R8, R3, R8 ; /* 0x00000003080c7223 */
/* 0x000fc80000000008 */
/*05e0*/ FFMA R3, R5, R12, RZ ; /* 0x0000000c05037223 */
/* 0x000fc800000000ff */
/*05f0*/ FFMA R8, R10, R3, R5 ; /* 0x000000030a087223 */
/* 0x000fc80000000005 */
/*0600*/ FFMA R11, R12, R8, R3 ; /* 0x000000080c0b7223 */
/* 0x000fc80000000003 */
/*0610*/ FFMA R5, R10, R11, R5 ; /* 0x0000000b0a057223 */
/* 0x000fc80000000005 */
/*0620*/ FFMA R3, R12, R5, R11 ; /* 0x000000050c037223 */
/* 0x000fca000000000b */
/*0630*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0640*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0650*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0660*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0670*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0680*/ @!P0 BRA 0x890 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0690*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*06a0*/ @P0 BRA 0x860 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*06b0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*06c0*/ @P0 BRA 0x8a0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*06e0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*06f0*/ @!P0 BRA 0x8a0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0700*/ FFMA.RZ R4, R12, R5.reuse, R11.reuse ; /* 0x000000050c047223 */
/* 0x180fe2000000c00b */
/*0710*/ IADD3 R7, R8.reuse, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x040fe40007ffe0ff */
/*0720*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*0730*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0740*/ FFMA.RP R4, R12, R5.reuse, R11.reuse ; /* 0x000000050c047223 */
/* 0x180fe2000000800b */
/*0750*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*0760*/ FFMA.RM R5, R12, R5, R11 ; /* 0x000000050c057223 */
/* 0x000fe2000000400b */
/*0770*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe200078efcff */
/*0780*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0a08 */
/*0790*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*07a0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fe40003f1d000 */
/*07b0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*07c0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*07d0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*07e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*07f0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fe40000011605 */
/*0800*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0810*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0820*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0830*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0840*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0850*/ BRA 0x8a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0860*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0870*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0880*/ BRA 0x8a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0890*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*08a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x940 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*08c0*/ LOP3.LUT R3, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fc800078e4805 */
/*08d0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*08e0*/ BRA 0x940 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08f0*/ LOP3.LUT R3, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fe200078e4805 */
/*0900*/ BRA 0x940 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0910*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0920*/ BRA 0x940 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0930*/ FADD.FTZ R3, R8, R11 ; /* 0x0000000b08037221 */
/* 0x000fe40000010000 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*0960*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0970*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff68002007950 */
/* 0x000fea0003c3ffff */
/*0980*/ BRA 0x980; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8fwd_percPfS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e680000002500 */
/*0050*/ STS [0x320], RZ ; /* 0x000320ffff007388 */
/* 0x000fe60000000800 */
/*0060*/ IMAD.WIDE R2, R13, R7, c[0x0][0x160] ; /* 0x000058000d027625 */
/* 0x001fe200078e0207 */
/*0070*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0080*/ IMAD R0, R8, 0xc8, R13 ; /* 0x000000c808007824 */
/* 0x002fc800078e020d */
/*0090*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000eaa000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*00d0*/ BSSY B0, 0x160 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*00e0*/ FMUL R6, R4, R3 ; /* 0x0000000304067220 */
/* 0x004fca0000400000 */
/*00f0*/ STS [R13.X4], R6 ; /* 0x000000060d007388 */
/* 0x0001e80000004800 */
/*0100*/ LDS R2, [0x320] ; /* 0x00032000ff027984 */
/* 0x000e640000000800 */
/*0110*/ FADD R3, R6, R2 ; /* 0x0000000206037221 */
/* 0x002fcc0000000000 */
/*0120*/ ATOMS.CAST.SPIN R3, [0x320], R2, R3 ; /* 0x00032002ff03738d */
/* 0x000e640001800003 */
/*0130*/ ISETP.EQ.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x002fda0003f02070 */
/*0140*/ @!P0 BRA 0x100 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0170*/ IMAD.WIDE R2, R8, R7, c[0x0][0x180] ; /* 0x0000600008027625 */
/* 0x000fc800078e0207 */
/*0180*/ IMAD.WIDE R4, R0, R7, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fc800078e0207 */
/*0190*/ IMAD.WIDE R6, R8, R7, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x001fe200078e0207 */
/*01a0*/ LDS R11, [0x320] ; /* 0x00032000ff0b7984 */
/* 0x000e280000000800 */
/*01b0*/ LDS R13, [R13.X4] ; /* 0x000000000d0d7984 */
/* 0x000e620000004800 */
/*01c0*/ FSETP.GEU.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x001fc60003f0e000 */
/*01d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*01e0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x002fec000c101904 */
/*01f0*/ @P0 MOV R9, R11 ; /* 0x0000000b00090202 */
/* 0x000fca0000000f00 */
/*0200*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <stdint.h>
#define IN_FEATS 200
#define OUT_CLASSES 10
#define W_SIZE IN_FEATS * OUT_CLASSES
uint64_t getTimeMicroseconds64()
{
uint64_t nTime;
struct timespec tSpec;
clock_gettime(CLOCK_REALTIME, &tSpec);
nTime = (uint64_t)tSpec.tv_nsec / 1000;
return nTime;
}
__global__ void fwd_perc(float *in, float *out, float *weights, float *activations, float *activation_sum)
{
int b = blockIdx.x;
int t = threadIdx.x;
__shared__ float z[IN_FEATS], sum_z;
sum_z = 0;
__syncthreads();
z[t] = in[t] * weights[b * IN_FEATS + t];
atomicAdd(&sum_z, z[t]);
__syncthreads();
activation_sum[b] = sum_z;
activations[b * IN_FEATS + t ] = z[t];
if (sum_z < 0) { out[b] = 0; } else { out[b] = sum_z; }
}
__global__ void lrp_perc(float *out, float *relevance, float *activations, float *activation_sum)
{
int b = blockIdx.x;
int t = threadIdx.x;
__shared__ float z[OUT_CLASSES], rel, sum_z[OUT_CLASSES], r_m[OUT_CLASSES];
z[t] = activations[t * IN_FEATS + b];
rel = 0;
sum_z[t] = activation_sum[t];
r_m[t] = out[t];
__syncthreads();
atomicAdd(&rel, z[t] * r_m[t] / sum_z[t]);
__syncthreads();
relevance[b] = rel;
}
void lrp_perc_gm(float *in, float *out, float *relevance, float *weights, float *activations, float *activation_sum, int n, int m)
{
for (int j = 0; j < m; j++) {
for (int i_prime = 0; i_prime < n; i_prime++) {
activations[j * n + i_prime] = in[i_prime] * weights[j * n + i_prime];
activation_sum[j] += activations[j * n + i_prime];
}
if (activation_sum[j] < 0) { out[j] = 0; } else { out[j] = activation_sum[j]; }
}
for (int i = 0; i < n; i++) {
for (int j = 0; j < m; j++) {
relevance[i] += (activations[j * n + i] * out[j]) / activation_sum[j];
}
}
}
int main(void)
{
uint64_t dT1 = 0, dT2 = 0, hT1 = 0, hT2 = 0;
float input[IN_FEATS], golden_out[OUT_CLASSES], cuda_out[OUT_CLASSES], weights[W_SIZE], golden_relevance[IN_FEATS], cuda_relevance[IN_FEATS], golden_activations[W_SIZE], cuda_activations[W_SIZE], golden_asum[OUT_CLASSES], cuda_asum[OUT_CLASSES];
cudaError_t s;
// initialize variables on host
for (int i = 0; i < IN_FEATS; i++) {
input[i] = rand() % 10;
golden_relevance[i] = 0;
cuda_relevance[i] = 0;
for (int j = 0; j < OUT_CLASSES; j++) {
weights[j * IN_FEATS + i] = rand() % 10;
golden_activations[j * IN_FEATS + i] = 0;
cuda_activations[j * IN_FEATS + i] = 0;
}
}
for (int i = 0; i < OUT_CLASSES; i++) {
golden_out[i] = 0;
cuda_out[i] = 0;
golden_asum[i] = 0;
cuda_asum[i] = 0;
}
// allocating memory for variables for device
float *input_, *weights_, *output_, *relevance_, *activations_, *asum_;
cudaMalloc(&input_, IN_FEATS * sizeof(float));
cudaMalloc(&weights_, W_SIZE * sizeof(float));
cudaMalloc(&output_, OUT_CLASSES * sizeof(float));
cudaMalloc(&relevance_, IN_FEATS * sizeof(float));
cudaMalloc(&activations_, W_SIZE * sizeof(float));
cudaMalloc(&asum_, OUT_CLASSES * sizeof(float));
// run version with static shared memory
cudaMemcpy(input_, input, IN_FEATS * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(weights_, weights, W_SIZE *sizeof(float), cudaMemcpyHostToDevice);
cudaMemset(output_, 0, OUT_CLASSES * sizeof(float));
cudaMemset(relevance_, 0, IN_FEATS * sizeof(float));
cudaMemset(activations_, 0, W_SIZE * sizeof(float));
cudaMemset(asum_, 0, OUT_CLASSES * sizeof(float));
// run cuda kernel and host function and compare the results
hT1 = getTimeMicroseconds64();
lrp_perc_gm(input, golden_out, golden_relevance, weights, golden_activations, golden_asum, IN_FEATS, OUT_CLASSES);
hT2 = getTimeMicroseconds64();
dT1 = getTimeMicroseconds64();
fwd_perc<<<OUT_CLASSES, IN_FEATS>>>(input_, output_, weights_, activations_, asum_);
lrp_perc<<<IN_FEATS, OUT_CLASSES>>>(output_, relevance_, activations_, asum_);
s = cudaDeviceSynchronize();
dT2 = getTimeMicroseconds64();
printf("%s\n", cudaGetErrorName(s));
// relvance
printf("### RELEVANCE ###\n");
s = cudaMemcpyAsync(cuda_relevance, relevance_, IN_FEATS * sizeof(float), cudaMemcpyDeviceToHost);
printf("%s\n", cudaGetErrorName(s));
for (int i = 0; i < IN_FEATS; i++) {
if (golden_relevance[i] != cuda_relevance[i]) {
printf("Error: golden_relevance[%d]!=cuda_relevance[%d] (%f, %f)\n", i, i, golden_relevance[i], cuda_relevance[i]);
}
}
// out
printf("### OUT ###\n");
s = cudaMemcpy(cuda_out, output_, OUT_CLASSES * sizeof(float), cudaMemcpyDeviceToHost);
printf("%s\n", cudaGetErrorName(s));
for (int i = 0; i < OUT_CLASSES; i++) {
if (golden_out[i] != cuda_out[i]) {
printf("Error: golden_out[%d]!=cuda_out[%d] (%f, %f)\n", i, i, golden_out[i], cuda_out[i]);
}
}
// activations
printf("### ACTIVATIONS ###\n");
s = cudaMemcpy(cuda_activations, activations_, W_SIZE * sizeof(float), cudaMemcpyDeviceToHost);
printf("%s\n", cudaGetErrorName(s));
for (int i = 0; i < W_SIZE; i++) {
if (golden_activations[i] != cuda_activations[i]) {
printf("Error: golden_activations[%d]!=cuda_activations[%d] (%f, %f)\n", i, i, golden_activations[i], cuda_activations[i]);
}
}
// asum
printf("### ASUM ###\n");
s = cudaMemcpy(cuda_asum, asum_, OUT_CLASSES * sizeof(float), cudaMemcpyDeviceToHost);
printf("%s\n", cudaGetErrorName(s));
for (int i = 0; i < OUT_CLASSES; i++) {
if (golden_asum[i] != cuda_asum[i]) {
printf("Error: golden_asum[%d]!=cuda_asum[%d] (%f, %f)\n", i, i, golden_asum[i], cuda_asum[i]);
}
}
printf("GPU time: %lu, \tCPU time: %lu\n", (dT2 - dT1) << 16, (hT2 - hT1) << 16);
cudaFree(input_);
cudaFree(weights_);
cudaFree(output_);
cudaFree(relevance_);
cudaFree(activations_);
cudaFree(asum_);
} | .file "tmpxft_00008c99_00000000-6_dense_relu_lrp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21getTimeMicroseconds64v
.type _Z21getTimeMicroseconds64v, @function
_Z21getTimeMicroseconds64v:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
movl $0, %edi
call clock_gettime@PLT
movq 8(%rsp), %rdx
shrq $3, %rdx
movabsq $2361183241434822607, %rcx
movq %rdx, %rax
mulq %rcx
movq %rdx, %rax
shrq $4, %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z21getTimeMicroseconds64v, .-_Z21getTimeMicroseconds64v
.globl _Z11lrp_perc_gmPfS_S_S_S_S_ii
.type _Z11lrp_perc_gmPfS_S_S_S_S_ii, @function
_Z11lrp_perc_gmPfS_S_S_S_S_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdx, %r15
movl 56(%rsp), %r11d
movl 64(%rsp), %r13d
testl %r13d, %r13d
jle .L8
movq %rcx, %r12
movq %rsi, %rbx
movq %r9, %rdx
movslq %r13d, %rax
leaq (%r9,%rax,4), %r14
movslq %r11d, %r10
salq $2, %r10
movl $0, %ebp
pxor %xmm1, %xmm1
movq %rsi, -8(%rsp)
jmp .L9
.L28:
movl $0x00000000, (%rbx)
.L13:
addq $4, %rbx
addq $4, %rdx
addl %r11d, %ebp
cmpq %r14, %rdx
je .L26
.L9:
testl %r11d, %r11d
jle .L15
movslq %ebp, %rcx
salq $2, %rcx
leaq (%r12,%rcx), %rsi
addq %r8, %rcx
movl $0, %eax
.L10:
movss (%rdi,%rax), %xmm0
mulss (%rsi,%rax), %xmm0
movss %xmm0, (%rcx,%rax)
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
cmpq %r10, %rax
jne .L10
.L15:
movss (%rdx), %xmm0
comiss %xmm0, %xmm1
ja .L28
movss %xmm0, (%rbx)
jmp .L13
.L26:
movq -8(%rsp), %rsi
.L8:
testl %r11d, %r11d
jle .L7
movq %r15, %rcx
movslq %r11d, %r10
salq $2, %r10
movslq %r13d, %rdi
salq $2, %rdi
movl $0, %ebx
jmp .L17
.L18:
movss (%rdx), %xmm0
mulss (%rsi,%rax), %xmm0
divss (%r9,%rax), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq %r10, %rdx
addq $4, %rax
cmpq %rdi, %rax
jne .L18
.L19:
addl $1, %ebx
addq $4, %r8
addq $4, %rcx
cmpl %ebx, %r11d
je .L7
.L17:
movq %r8, %rdx
movl $0, %eax
testl %r13d, %r13d
jg .L18
jmp .L19
.L7:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11lrp_perc_gmPfS_S_S_S_S_ii, .-_Z11lrp_perc_gmPfS_S_S_S_S_ii
.globl _Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_
.type _Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_, @function
_Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8fwd_percPfS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_, .-_Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_
.globl _Z8fwd_percPfS_S_S_S_
.type _Z8fwd_percPfS_S_S_S_, @function
_Z8fwd_percPfS_S_S_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8fwd_percPfS_S_S_S_, .-_Z8fwd_percPfS_S_S_S_
.globl _Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_
.type _Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_, @function
_Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8lrp_percPfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_, .-_Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_
.globl _Z8lrp_percPfS_S_S_
.type _Z8lrp_percPfS_S_S_, @function
_Z8lrp_percPfS_S_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z8lrp_percPfS_S_S_, .-_Z8lrp_percPfS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s\n"
.LC2:
.string "### RELEVANCE ###\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Error: golden_relevance[%d]!=cuda_relevance[%d] (%f, %f)\n"
.section .rodata.str1.1
.LC4:
.string "### OUT ###\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "Error: golden_out[%d]!=cuda_out[%d] (%f, %f)\n"
.section .rodata.str1.1
.LC6:
.string "### ACTIVATIONS ###\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Error: golden_activations[%d]!=cuda_activations[%d] (%f, %f)\n"
.section .rodata.str1.1
.LC8:
.string "### ASUM ###\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Error: golden_asum[%d]!=cuda_asum[%d] (%f, %f)\n"
.align 8
.LC10:
.string "GPU time: %lu, \tCPU time: %lu\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -24576(%rsp), %r11
.cfi_def_cfa 11, 24632
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2120, %rsp
.cfi_def_cfa_offset 26752
movq %fs:40, %rax
movq %rax, 26680(%rsp)
xorl %eax, %eax
movl $8000, %ebp
movl $0, %r12d
leaq -7728(%rsp), %r13
jmp .L47
.L77:
addl $1, %r12d
addq $4, %rbp
cmpl $200, %r12d
je .L76
.L47:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rbp)
movl $0x00000000, -6928(%rsp,%rbp)
movl $0x00000000, -6128(%rsp,%rbp)
leaq -8000(%rbp), %rbx
.L46:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 2672(%rsp,%rbx)
movl $0x00000000, 10672(%rsp,%rbx)
movl $0x00000000, 18672(%rsp,%rbx)
addq $800, %rbx
cmpq %rbp, %rbx
jne .L46
jmp .L77
.L76:
movl $0, %eax
.L48:
movl $0x00000000, 80(%rsp,%rax)
movl $0x00000000, 128(%rsp,%rax)
movl $0x00000000, 176(%rsp,%rax)
movl $0x00000000, 224(%rsp,%rax)
addq $4, %rax
cmpq $40, %rax
jne .L48
leaq 8(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 272(%rsp), %rbx
movl $1, %ecx
movl $800, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 2672(%rsp), %rbp
movl $1, %ecx
movl $8000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $40, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $800, %edx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
movl $8000, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl $40, %edx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
call _Z21getTimeMicroseconds64v
movq %rax, %r15
leaq 1072(%rsp), %rdx
leaq 80(%rsp), %rsi
pushq $10
.cfi_def_cfa_offset 26760
pushq $200
.cfi_def_cfa_offset 26768
leaq 192(%rsp), %r9
leaq 10688(%rsp), %r8
movq %rbp, %rcx
movq %rbx, %rdi
call _Z11lrp_perc_gmPfS_S_S_S_S_ii
call _Z21getTimeMicroseconds64v
movq %rax, %r12
call _Z21getTimeMicroseconds64v
movq %rax, %r13
movl $200, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $10, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 26752
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L78
.L49:
movl $10, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $200, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L79
.L50:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
call _Z21getTimeMicroseconds64v
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1872(%rsp), %rdi
movl $0, %r8d
movl $2, %ecx
movl $800, %edx
movq 32(%rsp), %rsi
call cudaMemcpyAsync@PLT
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %r14
jmp .L53
.L78:
movq 48(%rsp), %r8
movq 40(%rsp), %rcx
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_
jmp .L49
.L79:
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_
jmp .L50
.L64:
movl %ebx, %edx
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L51:
addq $1, %rbx
cmpq $200, %rbx
je .L80
.L53:
movss 1072(%rsp,%rbx,4), %xmm0
movss 1872(%rsp,%rbx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L64
je .L51
jmp .L64
.L80:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 128(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC5(%rip), %r14
jmp .L56
.L65:
movl %ebx, %edx
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L54:
addq $1, %rbx
cmpq $10, %rbx
je .L81
.L56:
movss 80(%rsp,%rbx,4), %xmm0
movss 128(%rsp,%rbx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L65
je .L54
jmp .L65
.L81:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 18672(%rsp), %rdi
movl $2, %ecx
movl $8000, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC7(%rip), %r14
jmp .L59
.L66:
movl %ebx, %edx
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L57:
addq $1, %rbx
cmpq $2000, %rbx
je .L82
.L59:
movss 10672(%rsp,%rbx,4), %xmm0
movss 18672(%rsp,%rbx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L66
je .L57
jmp .L66
.L82:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 224(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC9(%rip), %r14
jmp .L62
.L67:
movl %ebx, %edx
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L60:
addq $1, %rbx
cmpq $10, %rbx
je .L83
.L62:
movss 176(%rsp,%rbx,4), %xmm0
movss 224(%rsp,%rbx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L67
je .L60
jmp .L67
.L83:
movq %r12, %rcx
subq %r15, %rcx
salq $16, %rcx
movq %rbp, %rdx
subq %r13, %rdx
salq $16, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 26680(%rsp), %rax
subq %fs:40, %rax
jne .L84
movl $0, %eax
addq $26696, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z8lrp_percPfS_S_S_"
.LC12:
.string "_Z8fwd_percPfS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z8lrp_percPfS_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z8fwd_percPfS_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <stdint.h>
#define IN_FEATS 200
#define OUT_CLASSES 10
#define W_SIZE IN_FEATS * OUT_CLASSES
uint64_t getTimeMicroseconds64()
{
uint64_t nTime;
struct timespec tSpec;
clock_gettime(CLOCK_REALTIME, &tSpec);
nTime = (uint64_t)tSpec.tv_nsec / 1000;
return nTime;
}
__global__ void fwd_perc(float *in, float *out, float *weights, float *activations, float *activation_sum)
{
int b = blockIdx.x;
int t = threadIdx.x;
__shared__ float z[IN_FEATS], sum_z;
sum_z = 0;
__syncthreads();
z[t] = in[t] * weights[b * IN_FEATS + t];
atomicAdd(&sum_z, z[t]);
__syncthreads();
activation_sum[b] = sum_z;
activations[b * IN_FEATS + t ] = z[t];
if (sum_z < 0) { out[b] = 0; } else { out[b] = sum_z; }
}
__global__ void lrp_perc(float *out, float *relevance, float *activations, float *activation_sum)
{
int b = blockIdx.x;
int t = threadIdx.x;
__shared__ float z[OUT_CLASSES], rel, sum_z[OUT_CLASSES], r_m[OUT_CLASSES];
z[t] = activations[t * IN_FEATS + b];
rel = 0;
sum_z[t] = activation_sum[t];
r_m[t] = out[t];
__syncthreads();
atomicAdd(&rel, z[t] * r_m[t] / sum_z[t]);
__syncthreads();
relevance[b] = rel;
}
void lrp_perc_gm(float *in, float *out, float *relevance, float *weights, float *activations, float *activation_sum, int n, int m)
{
for (int j = 0; j < m; j++) {
for (int i_prime = 0; i_prime < n; i_prime++) {
activations[j * n + i_prime] = in[i_prime] * weights[j * n + i_prime];
activation_sum[j] += activations[j * n + i_prime];
}
if (activation_sum[j] < 0) { out[j] = 0; } else { out[j] = activation_sum[j]; }
}
for (int i = 0; i < n; i++) {
for (int j = 0; j < m; j++) {
relevance[i] += (activations[j * n + i] * out[j]) / activation_sum[j];
}
}
}
int main(void)
{
uint64_t dT1 = 0, dT2 = 0, hT1 = 0, hT2 = 0;
float input[IN_FEATS], golden_out[OUT_CLASSES], cuda_out[OUT_CLASSES], weights[W_SIZE], golden_relevance[IN_FEATS], cuda_relevance[IN_FEATS], golden_activations[W_SIZE], cuda_activations[W_SIZE], golden_asum[OUT_CLASSES], cuda_asum[OUT_CLASSES];
cudaError_t s;
// initialize variables on host
for (int i = 0; i < IN_FEATS; i++) {
input[i] = rand() % 10;
golden_relevance[i] = 0;
cuda_relevance[i] = 0;
for (int j = 0; j < OUT_CLASSES; j++) {
weights[j * IN_FEATS + i] = rand() % 10;
golden_activations[j * IN_FEATS + i] = 0;
cuda_activations[j * IN_FEATS + i] = 0;
}
}
for (int i = 0; i < OUT_CLASSES; i++) {
golden_out[i] = 0;
cuda_out[i] = 0;
golden_asum[i] = 0;
cuda_asum[i] = 0;
}
// allocating memory for variables for device
float *input_, *weights_, *output_, *relevance_, *activations_, *asum_;
cudaMalloc(&input_, IN_FEATS * sizeof(float));
cudaMalloc(&weights_, W_SIZE * sizeof(float));
cudaMalloc(&output_, OUT_CLASSES * sizeof(float));
cudaMalloc(&relevance_, IN_FEATS * sizeof(float));
cudaMalloc(&activations_, W_SIZE * sizeof(float));
cudaMalloc(&asum_, OUT_CLASSES * sizeof(float));
// run version with static shared memory
cudaMemcpy(input_, input, IN_FEATS * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(weights_, weights, W_SIZE *sizeof(float), cudaMemcpyHostToDevice);
cudaMemset(output_, 0, OUT_CLASSES * sizeof(float));
cudaMemset(relevance_, 0, IN_FEATS * sizeof(float));
cudaMemset(activations_, 0, W_SIZE * sizeof(float));
cudaMemset(asum_, 0, OUT_CLASSES * sizeof(float));
// run cuda kernel and host function and compare the results
hT1 = getTimeMicroseconds64();
lrp_perc_gm(input, golden_out, golden_relevance, weights, golden_activations, golden_asum, IN_FEATS, OUT_CLASSES);
hT2 = getTimeMicroseconds64();
dT1 = getTimeMicroseconds64();
fwd_perc<<<OUT_CLASSES, IN_FEATS>>>(input_, output_, weights_, activations_, asum_);
lrp_perc<<<IN_FEATS, OUT_CLASSES>>>(output_, relevance_, activations_, asum_);
s = cudaDeviceSynchronize();
dT2 = getTimeMicroseconds64();
printf("%s\n", cudaGetErrorName(s));
// relvance
printf("### RELEVANCE ###\n");
s = cudaMemcpyAsync(cuda_relevance, relevance_, IN_FEATS * sizeof(float), cudaMemcpyDeviceToHost);
printf("%s\n", cudaGetErrorName(s));
for (int i = 0; i < IN_FEATS; i++) {
if (golden_relevance[i] != cuda_relevance[i]) {
printf("Error: golden_relevance[%d]!=cuda_relevance[%d] (%f, %f)\n", i, i, golden_relevance[i], cuda_relevance[i]);
}
}
// out
printf("### OUT ###\n");
s = cudaMemcpy(cuda_out, output_, OUT_CLASSES * sizeof(float), cudaMemcpyDeviceToHost);
printf("%s\n", cudaGetErrorName(s));
for (int i = 0; i < OUT_CLASSES; i++) {
if (golden_out[i] != cuda_out[i]) {
printf("Error: golden_out[%d]!=cuda_out[%d] (%f, %f)\n", i, i, golden_out[i], cuda_out[i]);
}
}
// activations
printf("### ACTIVATIONS ###\n");
s = cudaMemcpy(cuda_activations, activations_, W_SIZE * sizeof(float), cudaMemcpyDeviceToHost);
printf("%s\n", cudaGetErrorName(s));
for (int i = 0; i < W_SIZE; i++) {
if (golden_activations[i] != cuda_activations[i]) {
printf("Error: golden_activations[%d]!=cuda_activations[%d] (%f, %f)\n", i, i, golden_activations[i], cuda_activations[i]);
}
}
// asum
printf("### ASUM ###\n");
s = cudaMemcpy(cuda_asum, asum_, OUT_CLASSES * sizeof(float), cudaMemcpyDeviceToHost);
printf("%s\n", cudaGetErrorName(s));
for (int i = 0; i < OUT_CLASSES; i++) {
if (golden_asum[i] != cuda_asum[i]) {
printf("Error: golden_asum[%d]!=cuda_asum[%d] (%f, %f)\n", i, i, golden_asum[i], cuda_asum[i]);
}
}
printf("GPU time: %lu, \tCPU time: %lu\n", (dT2 - dT1) << 16, (hT2 - hT1) << 16);
cudaFree(input_);
cudaFree(weights_);
cudaFree(output_);
cudaFree(relevance_);
cudaFree(activations_);
cudaFree(asum_);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <stdint.h>
#define IN_FEATS 200
#define OUT_CLASSES 10
#define W_SIZE IN_FEATS * OUT_CLASSES
uint64_t getTimeMicroseconds64()
{
uint64_t nTime;
struct timespec tSpec;
clock_gettime(CLOCK_REALTIME, &tSpec);
nTime = (uint64_t)tSpec.tv_nsec / 1000;
return nTime;
}
__global__ void fwd_perc(float *in, float *out, float *weights, float *activations, float *activation_sum)
{
int b = blockIdx.x;
int t = threadIdx.x;
__shared__ float z[IN_FEATS], sum_z;
sum_z = 0;
__syncthreads();
z[t] = in[t] * weights[b * IN_FEATS + t];
atomicAdd(&sum_z, z[t]);
__syncthreads();
activation_sum[b] = sum_z;
activations[b * IN_FEATS + t ] = z[t];
if (sum_z < 0) { out[b] = 0; } else { out[b] = sum_z; }
}
__global__ void lrp_perc(float *out, float *relevance, float *activations, float *activation_sum)
{
int b = blockIdx.x;
int t = threadIdx.x;
__shared__ float z[OUT_CLASSES], rel, sum_z[OUT_CLASSES], r_m[OUT_CLASSES];
z[t] = activations[t * IN_FEATS + b];
rel = 0;
sum_z[t] = activation_sum[t];
r_m[t] = out[t];
__syncthreads();
atomicAdd(&rel, z[t] * r_m[t] / sum_z[t]);
__syncthreads();
relevance[b] = rel;
}
void lrp_perc_gm(float *in, float *out, float *relevance, float *weights, float *activations, float *activation_sum, int n, int m)
{
for (int j = 0; j < m; j++) {
for (int i_prime = 0; i_prime < n; i_prime++) {
activations[j * n + i_prime] = in[i_prime] * weights[j * n + i_prime];
activation_sum[j] += activations[j * n + i_prime];
}
if (activation_sum[j] < 0) { out[j] = 0; } else { out[j] = activation_sum[j]; }
}
for (int i = 0; i < n; i++) {
for (int j = 0; j < m; j++) {
relevance[i] += (activations[j * n + i] * out[j]) / activation_sum[j];
}
}
}
int main(void)
{
uint64_t dT1 = 0, dT2 = 0, hT1 = 0, hT2 = 0;
float input[IN_FEATS], golden_out[OUT_CLASSES], cuda_out[OUT_CLASSES], weights[W_SIZE], golden_relevance[IN_FEATS], cuda_relevance[IN_FEATS], golden_activations[W_SIZE], cuda_activations[W_SIZE], golden_asum[OUT_CLASSES], cuda_asum[OUT_CLASSES];
hipError_t s;
// initialize variables on host
for (int i = 0; i < IN_FEATS; i++) {
input[i] = rand() % 10;
golden_relevance[i] = 0;
cuda_relevance[i] = 0;
for (int j = 0; j < OUT_CLASSES; j++) {
weights[j * IN_FEATS + i] = rand() % 10;
golden_activations[j * IN_FEATS + i] = 0;
cuda_activations[j * IN_FEATS + i] = 0;
}
}
for (int i = 0; i < OUT_CLASSES; i++) {
golden_out[i] = 0;
cuda_out[i] = 0;
golden_asum[i] = 0;
cuda_asum[i] = 0;
}
// allocating memory for variables for device
float *input_, *weights_, *output_, *relevance_, *activations_, *asum_;
hipMalloc(&input_, IN_FEATS * sizeof(float));
hipMalloc(&weights_, W_SIZE * sizeof(float));
hipMalloc(&output_, OUT_CLASSES * sizeof(float));
hipMalloc(&relevance_, IN_FEATS * sizeof(float));
hipMalloc(&activations_, W_SIZE * sizeof(float));
hipMalloc(&asum_, OUT_CLASSES * sizeof(float));
// run version with static shared memory
hipMemcpy(input_, input, IN_FEATS * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(weights_, weights, W_SIZE *sizeof(float), hipMemcpyHostToDevice);
hipMemset(output_, 0, OUT_CLASSES * sizeof(float));
hipMemset(relevance_, 0, IN_FEATS * sizeof(float));
hipMemset(activations_, 0, W_SIZE * sizeof(float));
hipMemset(asum_, 0, OUT_CLASSES * sizeof(float));
// run cuda kernel and host function and compare the results
hT1 = getTimeMicroseconds64();
lrp_perc_gm(input, golden_out, golden_relevance, weights, golden_activations, golden_asum, IN_FEATS, OUT_CLASSES);
hT2 = getTimeMicroseconds64();
dT1 = getTimeMicroseconds64();
fwd_perc<<<OUT_CLASSES, IN_FEATS>>>(input_, output_, weights_, activations_, asum_);
lrp_perc<<<IN_FEATS, OUT_CLASSES>>>(output_, relevance_, activations_, asum_);
s = hipDeviceSynchronize();
dT2 = getTimeMicroseconds64();
printf("%s\n", hipGetErrorName(s));
// relvance
printf("### RELEVANCE ###\n");
s = hipMemcpyAsync(cuda_relevance, relevance_, IN_FEATS * sizeof(float), hipMemcpyDeviceToHost);
printf("%s\n", hipGetErrorName(s));
for (int i = 0; i < IN_FEATS; i++) {
if (golden_relevance[i] != cuda_relevance[i]) {
printf("Error: golden_relevance[%d]!=cuda_relevance[%d] (%f, %f)\n", i, i, golden_relevance[i], cuda_relevance[i]);
}
}
// out
printf("### OUT ###\n");
s = hipMemcpy(cuda_out, output_, OUT_CLASSES * sizeof(float), hipMemcpyDeviceToHost);
printf("%s\n", hipGetErrorName(s));
for (int i = 0; i < OUT_CLASSES; i++) {
if (golden_out[i] != cuda_out[i]) {
printf("Error: golden_out[%d]!=cuda_out[%d] (%f, %f)\n", i, i, golden_out[i], cuda_out[i]);
}
}
// activations
printf("### ACTIVATIONS ###\n");
s = hipMemcpy(cuda_activations, activations_, W_SIZE * sizeof(float), hipMemcpyDeviceToHost);
printf("%s\n", hipGetErrorName(s));
for (int i = 0; i < W_SIZE; i++) {
if (golden_activations[i] != cuda_activations[i]) {
printf("Error: golden_activations[%d]!=cuda_activations[%d] (%f, %f)\n", i, i, golden_activations[i], cuda_activations[i]);
}
}
// asum
printf("### ASUM ###\n");
s = hipMemcpy(cuda_asum, asum_, OUT_CLASSES * sizeof(float), hipMemcpyDeviceToHost);
printf("%s\n", hipGetErrorName(s));
for (int i = 0; i < OUT_CLASSES; i++) {
if (golden_asum[i] != cuda_asum[i]) {
printf("Error: golden_asum[%d]!=cuda_asum[%d] (%f, %f)\n", i, i, golden_asum[i], cuda_asum[i]);
}
}
printf("GPU time: %lu, \tCPU time: %lu\n", (dT2 - dT1) << 16, (hT2 - hT1) << 16);
hipFree(input_);
hipFree(weights_);
hipFree(output_);
hipFree(relevance_);
hipFree(activations_);
hipFree(asum_);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <stdint.h>
#define IN_FEATS 200
#define OUT_CLASSES 10
#define W_SIZE IN_FEATS * OUT_CLASSES
uint64_t getTimeMicroseconds64()
{
uint64_t nTime;
struct timespec tSpec;
clock_gettime(CLOCK_REALTIME, &tSpec);
nTime = (uint64_t)tSpec.tv_nsec / 1000;
return nTime;
}
__global__ void fwd_perc(float *in, float *out, float *weights, float *activations, float *activation_sum)
{
int b = blockIdx.x;
int t = threadIdx.x;
__shared__ float z[IN_FEATS], sum_z;
sum_z = 0;
__syncthreads();
z[t] = in[t] * weights[b * IN_FEATS + t];
atomicAdd(&sum_z, z[t]);
__syncthreads();
activation_sum[b] = sum_z;
activations[b * IN_FEATS + t ] = z[t];
if (sum_z < 0) { out[b] = 0; } else { out[b] = sum_z; }
}
__global__ void lrp_perc(float *out, float *relevance, float *activations, float *activation_sum)
{
int b = blockIdx.x;
int t = threadIdx.x;
__shared__ float z[OUT_CLASSES], rel, sum_z[OUT_CLASSES], r_m[OUT_CLASSES];
z[t] = activations[t * IN_FEATS + b];
rel = 0;
sum_z[t] = activation_sum[t];
r_m[t] = out[t];
__syncthreads();
atomicAdd(&rel, z[t] * r_m[t] / sum_z[t]);
__syncthreads();
relevance[b] = rel;
}
void lrp_perc_gm(float *in, float *out, float *relevance, float *weights, float *activations, float *activation_sum, int n, int m)
{
for (int j = 0; j < m; j++) {
for (int i_prime = 0; i_prime < n; i_prime++) {
activations[j * n + i_prime] = in[i_prime] * weights[j * n + i_prime];
activation_sum[j] += activations[j * n + i_prime];
}
if (activation_sum[j] < 0) { out[j] = 0; } else { out[j] = activation_sum[j]; }
}
for (int i = 0; i < n; i++) {
for (int j = 0; j < m; j++) {
relevance[i] += (activations[j * n + i] * out[j]) / activation_sum[j];
}
}
}
int main(void)
{
uint64_t dT1 = 0, dT2 = 0, hT1 = 0, hT2 = 0;
float input[IN_FEATS], golden_out[OUT_CLASSES], cuda_out[OUT_CLASSES], weights[W_SIZE], golden_relevance[IN_FEATS], cuda_relevance[IN_FEATS], golden_activations[W_SIZE], cuda_activations[W_SIZE], golden_asum[OUT_CLASSES], cuda_asum[OUT_CLASSES];
hipError_t s;
// initialize variables on host
for (int i = 0; i < IN_FEATS; i++) {
input[i] = rand() % 10;
golden_relevance[i] = 0;
cuda_relevance[i] = 0;
for (int j = 0; j < OUT_CLASSES; j++) {
weights[j * IN_FEATS + i] = rand() % 10;
golden_activations[j * IN_FEATS + i] = 0;
cuda_activations[j * IN_FEATS + i] = 0;
}
}
for (int i = 0; i < OUT_CLASSES; i++) {
golden_out[i] = 0;
cuda_out[i] = 0;
golden_asum[i] = 0;
cuda_asum[i] = 0;
}
// allocating memory for variables for device
float *input_, *weights_, *output_, *relevance_, *activations_, *asum_;
hipMalloc(&input_, IN_FEATS * sizeof(float));
hipMalloc(&weights_, W_SIZE * sizeof(float));
hipMalloc(&output_, OUT_CLASSES * sizeof(float));
hipMalloc(&relevance_, IN_FEATS * sizeof(float));
hipMalloc(&activations_, W_SIZE * sizeof(float));
hipMalloc(&asum_, OUT_CLASSES * sizeof(float));
// run version with static shared memory
hipMemcpy(input_, input, IN_FEATS * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(weights_, weights, W_SIZE *sizeof(float), hipMemcpyHostToDevice);
hipMemset(output_, 0, OUT_CLASSES * sizeof(float));
hipMemset(relevance_, 0, IN_FEATS * sizeof(float));
hipMemset(activations_, 0, W_SIZE * sizeof(float));
hipMemset(asum_, 0, OUT_CLASSES * sizeof(float));
// run cuda kernel and host function and compare the results
hT1 = getTimeMicroseconds64();
lrp_perc_gm(input, golden_out, golden_relevance, weights, golden_activations, golden_asum, IN_FEATS, OUT_CLASSES);
hT2 = getTimeMicroseconds64();
dT1 = getTimeMicroseconds64();
fwd_perc<<<OUT_CLASSES, IN_FEATS>>>(input_, output_, weights_, activations_, asum_);
lrp_perc<<<IN_FEATS, OUT_CLASSES>>>(output_, relevance_, activations_, asum_);
s = hipDeviceSynchronize();
dT2 = getTimeMicroseconds64();
printf("%s\n", hipGetErrorName(s));
// relvance
printf("### RELEVANCE ###\n");
s = hipMemcpyAsync(cuda_relevance, relevance_, IN_FEATS * sizeof(float), hipMemcpyDeviceToHost);
printf("%s\n", hipGetErrorName(s));
for (int i = 0; i < IN_FEATS; i++) {
if (golden_relevance[i] != cuda_relevance[i]) {
printf("Error: golden_relevance[%d]!=cuda_relevance[%d] (%f, %f)\n", i, i, golden_relevance[i], cuda_relevance[i]);
}
}
// out
printf("### OUT ###\n");
s = hipMemcpy(cuda_out, output_, OUT_CLASSES * sizeof(float), hipMemcpyDeviceToHost);
printf("%s\n", hipGetErrorName(s));
for (int i = 0; i < OUT_CLASSES; i++) {
if (golden_out[i] != cuda_out[i]) {
printf("Error: golden_out[%d]!=cuda_out[%d] (%f, %f)\n", i, i, golden_out[i], cuda_out[i]);
}
}
// activations
printf("### ACTIVATIONS ###\n");
s = hipMemcpy(cuda_activations, activations_, W_SIZE * sizeof(float), hipMemcpyDeviceToHost);
printf("%s\n", hipGetErrorName(s));
for (int i = 0; i < W_SIZE; i++) {
if (golden_activations[i] != cuda_activations[i]) {
printf("Error: golden_activations[%d]!=cuda_activations[%d] (%f, %f)\n", i, i, golden_activations[i], cuda_activations[i]);
}
}
// asum
printf("### ASUM ###\n");
s = hipMemcpy(cuda_asum, asum_, OUT_CLASSES * sizeof(float), hipMemcpyDeviceToHost);
printf("%s\n", hipGetErrorName(s));
for (int i = 0; i < OUT_CLASSES; i++) {
if (golden_asum[i] != cuda_asum[i]) {
printf("Error: golden_asum[%d]!=cuda_asum[%d] (%f, %f)\n", i, i, golden_asum[i], cuda_asum[i]);
}
}
printf("GPU time: %lu, \tCPU time: %lu\n", (dT2 - dT1) << 16, (hT2 - hT1) << 16);
hipFree(input_);
hipFree(weights_);
hipFree(output_);
hipFree(relevance_);
hipFree(activations_);
hipFree(asum_);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8fwd_percPfS_S_S_S_
.globl _Z8fwd_percPfS_S_S_S_
.p2align 8
.type _Z8fwd_percPfS_S_S_S_,@function
_Z8fwd_percPfS_S_S_S_:
s_mov_b32 s2, s15
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s2, 0xc8, v[0:1]
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_mov_b32 s3, exec_lo
ds_store_b32 v5, v5 offset:800
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v5, v0, s[6:7]
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v5, v3
v_bfrev_b32_e32 v3, 1
ds_store_b32 v0, v4
.LBB0_1:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v4, s4
s_lshl_b32 s4, 1, s4
s_and_not1_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_add_f32_e32 v3, s5, v3
s_cbranch_scc1 .LBB0_1
v_mbcnt_lo_u32_b32 v4, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v4
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v4, 0
ds_add_f32 v4, v3 offset:800
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v3, 0
s_load_b128 s[4:7], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v3 offset:800
ds_load_b32 v5, v0
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[2:3], s[2:3], 2
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, 0, v4
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_cndmask_b32_e32 v2, 0, v4, vcc_lo
global_store_b32 v3, v4, s[6:7]
global_store_b32 v[0:1], v5, off
global_store_b32 v3, v2, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8fwd_percPfS_S_S_S_
.amdhsa_group_segment_fixed_size 804
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8fwd_percPfS_S_S_S_, .Lfunc_end0-_Z8fwd_percPfS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8lrp_percPfS_S_S_
.globl _Z8lrp_percPfS_S_S_
.p2align 8
.type _Z8lrp_percPfS_S_S_,@function
_Z8lrp_percPfS_S_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x0
s_mov_b32 s2, s15
v_lshlrev_b32_e32 v3, 2, v0
v_mad_u32_u24 v1, v0, 0xc8, s2
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo
s_clause 0x1
global_load_b32 v2, v3, s[6:7]
global_load_b32 v4, v3, s[8:9]
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
ds_store_b32 v1, v1 offset:40
s_waitcnt vmcnt(2)
ds_store_b32 v3, v2 offset:96
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v3, v0, v4 offset1:12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[0:1], v3 offset1:12
ds_load_b32 v2, v3 offset:96
s_waitcnt lgkmcnt(1)
v_mul_f32_e32 v0, v0, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v1, null, v2, v2, v0
v_div_scale_f32 v5, vcc_lo, v0, v2, v0
v_rcp_f32_e32 v3, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v1, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v3
v_mul_f32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v1, v4, v5
v_fmac_f32_e32 v4, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, -v1, v4, v5
v_div_fmas_f32 v1, v1, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v1, v1, v2, v0
v_bfrev_b32_e32 v0, 1
.LBB1_1:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v1, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s3, s3, s4
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, s5, v0
s_cbranch_scc1 .LBB1_1
v_mbcnt_lo_u32_b32 v1, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB1_4
v_mov_b32_e32 v1, 0
ds_add_f32 v1, v0 offset:40
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v0 offset:40
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8lrp_percPfS_S_S_
.amdhsa_group_segment_fixed_size 136
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8lrp_percPfS_S_S_, .Lfunc_end1-_Z8lrp_percPfS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 804
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8fwd_percPfS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8fwd_percPfS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 136
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8lrp_percPfS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8lrp_percPfS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <stdint.h>
#define IN_FEATS 200
#define OUT_CLASSES 10
#define W_SIZE IN_FEATS * OUT_CLASSES
uint64_t getTimeMicroseconds64()
{
uint64_t nTime;
struct timespec tSpec;
clock_gettime(CLOCK_REALTIME, &tSpec);
nTime = (uint64_t)tSpec.tv_nsec / 1000;
return nTime;
}
__global__ void fwd_perc(float *in, float *out, float *weights, float *activations, float *activation_sum)
{
int b = blockIdx.x;
int t = threadIdx.x;
__shared__ float z[IN_FEATS], sum_z;
sum_z = 0;
__syncthreads();
z[t] = in[t] * weights[b * IN_FEATS + t];
atomicAdd(&sum_z, z[t]);
__syncthreads();
activation_sum[b] = sum_z;
activations[b * IN_FEATS + t ] = z[t];
if (sum_z < 0) { out[b] = 0; } else { out[b] = sum_z; }
}
__global__ void lrp_perc(float *out, float *relevance, float *activations, float *activation_sum)
{
int b = blockIdx.x;
int t = threadIdx.x;
__shared__ float z[OUT_CLASSES], rel, sum_z[OUT_CLASSES], r_m[OUT_CLASSES];
z[t] = activations[t * IN_FEATS + b];
rel = 0;
sum_z[t] = activation_sum[t];
r_m[t] = out[t];
__syncthreads();
atomicAdd(&rel, z[t] * r_m[t] / sum_z[t]);
__syncthreads();
relevance[b] = rel;
}
void lrp_perc_gm(float *in, float *out, float *relevance, float *weights, float *activations, float *activation_sum, int n, int m)
{
for (int j = 0; j < m; j++) {
for (int i_prime = 0; i_prime < n; i_prime++) {
activations[j * n + i_prime] = in[i_prime] * weights[j * n + i_prime];
activation_sum[j] += activations[j * n + i_prime];
}
if (activation_sum[j] < 0) { out[j] = 0; } else { out[j] = activation_sum[j]; }
}
for (int i = 0; i < n; i++) {
for (int j = 0; j < m; j++) {
relevance[i] += (activations[j * n + i] * out[j]) / activation_sum[j];
}
}
}
int main(void)
{
uint64_t dT1 = 0, dT2 = 0, hT1 = 0, hT2 = 0;
float input[IN_FEATS], golden_out[OUT_CLASSES], cuda_out[OUT_CLASSES], weights[W_SIZE], golden_relevance[IN_FEATS], cuda_relevance[IN_FEATS], golden_activations[W_SIZE], cuda_activations[W_SIZE], golden_asum[OUT_CLASSES], cuda_asum[OUT_CLASSES];
hipError_t s;
// initialize variables on host
for (int i = 0; i < IN_FEATS; i++) {
input[i] = rand() % 10;
golden_relevance[i] = 0;
cuda_relevance[i] = 0;
for (int j = 0; j < OUT_CLASSES; j++) {
weights[j * IN_FEATS + i] = rand() % 10;
golden_activations[j * IN_FEATS + i] = 0;
cuda_activations[j * IN_FEATS + i] = 0;
}
}
for (int i = 0; i < OUT_CLASSES; i++) {
golden_out[i] = 0;
cuda_out[i] = 0;
golden_asum[i] = 0;
cuda_asum[i] = 0;
}
// allocating memory for variables for device
float *input_, *weights_, *output_, *relevance_, *activations_, *asum_;
hipMalloc(&input_, IN_FEATS * sizeof(float));
hipMalloc(&weights_, W_SIZE * sizeof(float));
hipMalloc(&output_, OUT_CLASSES * sizeof(float));
hipMalloc(&relevance_, IN_FEATS * sizeof(float));
hipMalloc(&activations_, W_SIZE * sizeof(float));
hipMalloc(&asum_, OUT_CLASSES * sizeof(float));
// run version with static shared memory
hipMemcpy(input_, input, IN_FEATS * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(weights_, weights, W_SIZE *sizeof(float), hipMemcpyHostToDevice);
hipMemset(output_, 0, OUT_CLASSES * sizeof(float));
hipMemset(relevance_, 0, IN_FEATS * sizeof(float));
hipMemset(activations_, 0, W_SIZE * sizeof(float));
hipMemset(asum_, 0, OUT_CLASSES * sizeof(float));
// run cuda kernel and host function and compare the results
hT1 = getTimeMicroseconds64();
lrp_perc_gm(input, golden_out, golden_relevance, weights, golden_activations, golden_asum, IN_FEATS, OUT_CLASSES);
hT2 = getTimeMicroseconds64();
dT1 = getTimeMicroseconds64();
fwd_perc<<<OUT_CLASSES, IN_FEATS>>>(input_, output_, weights_, activations_, asum_);
lrp_perc<<<IN_FEATS, OUT_CLASSES>>>(output_, relevance_, activations_, asum_);
s = hipDeviceSynchronize();
dT2 = getTimeMicroseconds64();
printf("%s\n", hipGetErrorName(s));
// relvance
printf("### RELEVANCE ###\n");
s = hipMemcpyAsync(cuda_relevance, relevance_, IN_FEATS * sizeof(float), hipMemcpyDeviceToHost);
printf("%s\n", hipGetErrorName(s));
for (int i = 0; i < IN_FEATS; i++) {
if (golden_relevance[i] != cuda_relevance[i]) {
printf("Error: golden_relevance[%d]!=cuda_relevance[%d] (%f, %f)\n", i, i, golden_relevance[i], cuda_relevance[i]);
}
}
// out
printf("### OUT ###\n");
s = hipMemcpy(cuda_out, output_, OUT_CLASSES * sizeof(float), hipMemcpyDeviceToHost);
printf("%s\n", hipGetErrorName(s));
for (int i = 0; i < OUT_CLASSES; i++) {
if (golden_out[i] != cuda_out[i]) {
printf("Error: golden_out[%d]!=cuda_out[%d] (%f, %f)\n", i, i, golden_out[i], cuda_out[i]);
}
}
// activations
printf("### ACTIVATIONS ###\n");
s = hipMemcpy(cuda_activations, activations_, W_SIZE * sizeof(float), hipMemcpyDeviceToHost);
printf("%s\n", hipGetErrorName(s));
for (int i = 0; i < W_SIZE; i++) {
if (golden_activations[i] != cuda_activations[i]) {
printf("Error: golden_activations[%d]!=cuda_activations[%d] (%f, %f)\n", i, i, golden_activations[i], cuda_activations[i]);
}
}
// asum
printf("### ASUM ###\n");
s = hipMemcpy(cuda_asum, asum_, OUT_CLASSES * sizeof(float), hipMemcpyDeviceToHost);
printf("%s\n", hipGetErrorName(s));
for (int i = 0; i < OUT_CLASSES; i++) {
if (golden_asum[i] != cuda_asum[i]) {
printf("Error: golden_asum[%d]!=cuda_asum[%d] (%f, %f)\n", i, i, golden_asum[i], cuda_asum[i]);
}
}
printf("GPU time: %lu, \tCPU time: %lu\n", (dT2 - dT1) << 16, (hT2 - hT1) << 16);
hipFree(input_);
hipFree(weights_);
hipFree(output_);
hipFree(relevance_);
hipFree(activations_);
hipFree(asum_);
} | .text
.file "dense_relu_lrp.hip"
.globl _Z21getTimeMicroseconds64v # -- Begin function _Z21getTimeMicroseconds64v
.p2align 4, 0x90
.type _Z21getTimeMicroseconds64v,@function
_Z21getTimeMicroseconds64v: # @_Z21getTimeMicroseconds64v
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 16(%rsp), %rax
shrq $3, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
mulq %rcx
movq %rdx, %rax
shrq $4, %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21getTimeMicroseconds64v, .Lfunc_end0-_Z21getTimeMicroseconds64v
.cfi_endproc
# -- End function
.globl _Z23__device_stub__fwd_percPfS_S_S_S_ # -- Begin function _Z23__device_stub__fwd_percPfS_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__fwd_percPfS_S_S_S_,@function
_Z23__device_stub__fwd_percPfS_S_S_S_: # @_Z23__device_stub__fwd_percPfS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8fwd_percPfS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z23__device_stub__fwd_percPfS_S_S_S_, .Lfunc_end1-_Z23__device_stub__fwd_percPfS_S_S_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__lrp_percPfS_S_S_ # -- Begin function _Z23__device_stub__lrp_percPfS_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__lrp_percPfS_S_S_,@function
_Z23__device_stub__lrp_percPfS_S_S_: # @_Z23__device_stub__lrp_percPfS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8lrp_percPfS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z23__device_stub__lrp_percPfS_S_S_, .Lfunc_end2-_Z23__device_stub__lrp_percPfS_S_S_
.cfi_endproc
# -- End function
.globl _Z11lrp_perc_gmPfS_S_S_S_S_ii # -- Begin function _Z11lrp_perc_gmPfS_S_S_S_S_ii
.p2align 4, 0x90
.type _Z11lrp_perc_gmPfS_S_S_S_S_ii,@function
_Z11lrp_perc_gmPfS_S_S_S_S_ii: # @_Z11lrp_perc_gmPfS_S_S_S_S_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl 64(%rsp), %eax
movl 56(%rsp), %ebx
movl %eax, %r10d
movl %ebx, %r11d
testl %eax, %eax
jle .LBB3_6
# %bb.1: # %.preheader52.lr.ph
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
xorps %xmm0, %xmm0
maxss (%r9,%r15,4), %xmm0
movss %xmm0, (%rsi,%r15,4)
incq %r15
addl %ebx, %r14d
cmpq %r10, %r15
je .LBB3_6
.LBB3_2: # %.preheader52
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ebx, %ebx
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r14d, %r13d
leaq (%r8,%r13,4), %r12
leaq (%rcx,%r13,4), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r13,%rbp,4), %xmm0
movss %xmm0, (%r12,%rbp,4)
addss (%r9,%r15,4), %xmm0
movss %xmm0, (%r9,%r15,4)
incq %rbp
cmpq %rbp, %r11
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %.preheader51
testl %ebx, %ebx
jle .LBB3_12
# %bb.7: # %.preheader.lr.ph
leaq (,%r11,4), %rcx
xorl %edi, %edi
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_11: # %._crit_edge57
# in Loop: Header=BB3_8 Depth=1
incq %rdi
addq $4, %r8
cmpq %r11, %rdi
je .LBB3_12
.LBB3_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
testl %eax, %eax
jle .LBB3_11
# %bb.9: # %.lr.ph56
# in Loop: Header=BB3_8 Depth=1
movss (%rdx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r8, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rsi,%r14,4), %xmm1
divss (%r9,%r14,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rdx,%rdi,4)
incq %r14
addq %rcx, %rbx
cmpq %r14, %r10
jne .LBB3_10
jmp .LBB3_11
.LBB3_12: # %._crit_edge59
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11lrp_perc_gmPfS_S_S_S_S_ii, .Lfunc_end3-_Z11lrp_perc_gmPfS_S_S_S_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $26776, %rsp # imm = 0x6898
.cfi_def_cfa_offset 26832
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 10768(%rsp), %rbx
leaq 2768(%rsp), %r14
leaq 18768(%rsp), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_1: # =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 1968(%rsp,%r12,4)
movl $0, 368(%rsp,%r12,4)
movl $0, 1168(%rsp,%r12,4)
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r13)
movl $0, (%r14,%r13)
movl $0, (%rbx,%r13)
addq $800, %r13 # imm = 0x320
cmpq $8000, %r13 # imm = 0x1F40
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %r12
addq $4, %rbx
addq $4, %r14
addq $4, %r15
cmpq $200, %r12
jne .LBB4_1
# %bb.4: # %.preheader.preheader
xorps %xmm0, %xmm0
movaps %xmm0, 240(%rsp)
movaps %xmm0, 224(%rsp)
movq $0, 256(%rsp)
movaps %xmm0, 320(%rsp)
movaps %xmm0, 336(%rsp)
movq $0, 352(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 192(%rsp)
movq $0, 208(%rsp)
movaps %xmm0, 272(%rsp)
movaps %xmm0, 288(%rsp)
movq $0, 304(%rsp)
leaq 40(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
leaq 32(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 40(%rsp), %rdi
leaq 1968(%rsp), %rsi
movl $800, %edx # imm = 0x320
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
leaq 18768(%rsp), %r14
movl $8000, %edx # imm = 0x1F40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %r15d, %r15d
movl $40, %edx
xorl %esi, %esi
callq hipMemset
movq 24(%rsp), %rdi
movl $800, %edx # imm = 0x320
xorl %esi, %esi
callq hipMemset
movq 8(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
xorl %esi, %esi
callq hipMemset
movq (%rsp), %rdi
movl $40, %edx
xorl %esi, %esi
callq hipMemset
leaq 128(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 136(%rsp), %rbx
leaq 2768(%rsp), %rax
.p2align 4, 0x90
.LBB4_5: # %.preheader52.i
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
movss 176(%rsp,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movss 1968(%rsp,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r14,%rcx,4), %xmm1
movss %xmm1, (%rax,%rcx,4)
addss %xmm1, %xmm0
incq %rcx
cmpq $200, %rcx
jne .LBB4_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB4_5 Depth=1
movss %xmm0, 176(%rsp,%r15,4)
xorps %xmm1, %xmm1
maxss %xmm0, %xmm1
movss %xmm1, 224(%rsp,%r15,4)
incq %r15
addq $800, %rax # imm = 0x320
addq $800, %r14 # imm = 0x320
cmpq $10, %r15
jne .LBB4_5
# %bb.8: # %.preheader.i.preheader
leaq 2768(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_9: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_10 Depth 2
movss 368(%rsp,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_10: # Parent Loop BB4_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss 224(%rsp,%rsi,4), %xmm1
divss 176(%rsp,%rsi,4), %xmm1
addss %xmm1, %xmm0
incq %rsi
addq $800, %rdx # imm = 0x320
cmpq $10, %rsi
jne .LBB4_10
# %bb.11: # %._crit_edge57.i
# in Loop: Header=BB4_9 Depth=1
movss %xmm0, 368(%rsp,%rcx,4)
incq %rcx
addq $4, %rax
cmpq $200, %rcx
jne .LBB4_9
# %bb.12: # %_Z11lrp_perc_gmPfS_S_S_S_S_ii.exit
movabsq $4294967306, %r12 # imm = 0x10000000A
leaq 128(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 136(%rsp), %r14
leaq 128(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 136(%rsp), %r15
leaq 190(%r12), %r13
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.13:
movq 40(%rsp), %rax
movq 16(%rsp), %rcx
movq 32(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdi, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 168(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8fwd_percPfS_S_S_S_, %edi
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_14:
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_16
# %bb.15:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8lrp_percPfS_S_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_16:
callq hipDeviceSynchronize
movl %eax, %ebp
xorl %r13d, %r13d
leaq 128(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 136(%rsp), %r12
movl %ebp, %edi
callq hipGetErrorName
movq %rax, %rdi
callq puts@PLT
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rsi
leaq 1168(%rsp), %rdi
movl $800, %edx # imm = 0x320
movl $2, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
movl %eax, %edi
callq hipGetErrorName
movq %rax, %rdi
callq puts@PLT
jmp .LBB4_17
.p2align 4, 0x90
.LBB4_19: # in Loop: Header=BB4_17 Depth=1
incq %r13
cmpq $200, %r13
je .LBB4_20
.LBB4_17: # =>This Inner Loop Header: Depth=1
movss 368(%rsp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 1168(%rsp,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_18
jnp .LBB4_19
.LBB4_18: # in Loop: Header=BB4_17 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.2, %edi
movl %r13d, %esi
movl %r13d, %edx
movb $2, %al
callq printf
jmp .LBB4_19
.LBB4_20:
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %rsi
leaq 320(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorName
movq %rax, %rdi
callq puts@PLT
xorl %r13d, %r13d
jmp .LBB4_21
.p2align 4, 0x90
.LBB4_23: # in Loop: Header=BB4_21 Depth=1
incq %r13
cmpq $10, %r13
je .LBB4_24
.LBB4_21: # =>This Inner Loop Header: Depth=1
movss 224(%rsp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 320(%rsp,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_22
jnp .LBB4_23
.LBB4_22: # in Loop: Header=BB4_21 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %edi
movl %r13d, %esi
movl %r13d, %edx
movb $2, %al
callq printf
jmp .LBB4_23
.LBB4_24:
movl $.Lstr.2, %edi
callq puts@PLT
movq 8(%rsp), %rsi
leaq 10768(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorName
movq %rax, %rdi
callq puts@PLT
xorl %r13d, %r13d
jmp .LBB4_25
.p2align 4, 0x90
.LBB4_27: # in Loop: Header=BB4_25 Depth=1
incq %r13
cmpq $2000, %r13 # imm = 0x7D0
je .LBB4_28
.LBB4_25: # =>This Inner Loop Header: Depth=1
movss 2768(%rsp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 10768(%rsp,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_26
jnp .LBB4_27
.LBB4_26: # in Loop: Header=BB4_25 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.6, %edi
movl %r13d, %esi
movl %r13d, %edx
movb $2, %al
callq printf
jmp .LBB4_27
.LBB4_28:
movl $.Lstr.3, %edi
callq puts@PLT
movq (%rsp), %rsi
leaq 272(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorName
movq %rax, %rdi
callq puts@PLT
xorl %r13d, %r13d
jmp .LBB4_29
.p2align 4, 0x90
.LBB4_31: # in Loop: Header=BB4_29 Depth=1
incq %r13
cmpq $10, %r13
je .LBB4_32
.LBB4_29: # =>This Inner Loop Header: Depth=1
movss 176(%rsp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 272(%rsp,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_30
jnp .LBB4_31
.LBB4_30: # in Loop: Header=BB4_29 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.8, %edi
movl %r13d, %esi
movl %r13d, %edx
movb $2, %al
callq printf
jmp .LBB4_31
.LBB4_32:
shrq $3, %r12
movabsq $2361183241434822607, %rdi # imm = 0x20C49BA5E353F7CF
movq %r12, %rax
mulq %rdi
movq %rdx, %rsi
shrq $4, %rsi
shrq $3, %r15
movq %r15, %rax
mulq %rdi
movq %rdx, %rcx
shrq $4, %rcx
shrq $3, %r14
movq %r14, %rax
mulq %rdi
movq %rdx, %r8
subq %rcx, %rsi
shrq $4, %r8
shrq $3, %rbx
movq %rbx, %rax
mulq %rdi
shrq $4, %rdx
subq %rdx, %r8
shlq $16, %rsi
shlq $16, %r8
movl $.L.str.9, %edi
movq %r8, %rdx
xorl %eax, %eax
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $26776, %rsp # imm = 0x6898
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8fwd_percPfS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8lrp_percPfS_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8fwd_percPfS_S_S_S_,@object # @_Z8fwd_percPfS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z8fwd_percPfS_S_S_S_
.p2align 3, 0x0
_Z8fwd_percPfS_S_S_S_:
.quad _Z23__device_stub__fwd_percPfS_S_S_S_
.size _Z8fwd_percPfS_S_S_S_, 8
.type _Z8lrp_percPfS_S_S_,@object # @_Z8lrp_percPfS_S_S_
.globl _Z8lrp_percPfS_S_S_
.p2align 3, 0x0
_Z8lrp_percPfS_S_S_:
.quad _Z23__device_stub__lrp_percPfS_S_S_
.size _Z8lrp_percPfS_S_S_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Error: golden_relevance[%d]!=cuda_relevance[%d] (%f, %f)\n"
.size .L.str.2, 58
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error: golden_out[%d]!=cuda_out[%d] (%f, %f)\n"
.size .L.str.4, 46
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error: golden_activations[%d]!=cuda_activations[%d] (%f, %f)\n"
.size .L.str.6, 62
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error: golden_asum[%d]!=cuda_asum[%d] (%f, %f)\n"
.size .L.str.8, 48
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "GPU time: %lu, \tCPU time: %lu\n"
.size .L.str.9, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8fwd_percPfS_S_S_S_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8lrp_percPfS_S_S_"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "### RELEVANCE ###"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "### OUT ###"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "### ACTIVATIONS ###"
.size .Lstr.2, 20
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "### ASUM ###"
.size .Lstr.3, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__fwd_percPfS_S_S_S_
.addrsig_sym _Z23__device_stub__lrp_percPfS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8fwd_percPfS_S_S_S_
.addrsig_sym _Z8lrp_percPfS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8lrp_percPfS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R13.reuse, 0xc8, R0 ; /* 0x000000c80d027824 */
/* 0x041fe400078e0200 */
/*0060*/ IMAD.WIDE R4, R13, R6, c[0x0][0x178] ; /* 0x00005e000d047625 */
/* 0x000fc800078e0206 */
/*0070*/ IMAD.WIDE R2, R2, R6.reuse, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x080fe400078e0206 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0090*/ IMAD.WIDE R6, R13, R6, c[0x0][0x160] ; /* 0x000058000d067625 */
/* 0x000fe400078e0206 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee8000c1e1900 */
/*00b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*00c0*/ BSSY B0, 0x220 ; /* 0x0000015000007945 */
/* 0x000fe60003800000 */
/*00d0*/ STS [R13.X4], R2 ; /* 0x000000020d007388 */
/* 0x008fe80000004800 */
/*00e0*/ STS [0x28], RZ ; /* 0x000028ffff007388 */
/* 0x000fe80000000800 */
/*00f0*/ STS [R13.X4+0x2c], R4 ; /* 0x00002c040d007388 */
/* 0x004fe80000004800 */
/*0100*/ STS [R13.X4+0x54], R6 ; /* 0x000054060d007388 */
/* 0x010fe80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ LDS R11, [R13.X4+0x2c] ; /* 0x00002c000d0b7984 */
/* 0x000e280000004800 */
/*0130*/ LDS R8, [R13.X4] ; /* 0x000000000d087984 */
/* 0x000fe80000004800 */
/*0140*/ LDS R9, [R13.X4+0x54] ; /* 0x000054000d097984 */
/* 0x000e620000004800 */
/*0150*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x001e220000001000 */
/*0160*/ FMUL R8, R8, R9 ; /* 0x0000000908087220 */
/* 0x002fce0000400000 */
/*0170*/ FCHK P0, R8, R11 ; /* 0x0000000b08007302 */
/* 0x000e620000000000 */
/*0180*/ FFMA R3, -R11, R10, 1 ; /* 0x3f8000000b037423 */
/* 0x001fc8000000010a */
/*0190*/ FFMA R3, R10, R3, R10 ; /* 0x000000030a037223 */
/* 0x000fc8000000000a */
/*01a0*/ FFMA R2, R8, R3, RZ ; /* 0x0000000308027223 */
/* 0x000fc800000000ff */
/*01b0*/ FFMA R4, -R11, R2, R8 ; /* 0x000000020b047223 */
/* 0x000fc80000000108 */
/*01c0*/ FFMA R2, R3, R4, R2 ; /* 0x0000000403027223 */
/* 0x000fe20000000002 */
/*01d0*/ @!P0 BRA 0x210 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*01e0*/ MOV R2, 0x200 ; /* 0x0000020000027802 */
/* 0x000fe40000000f00 */
/*01f0*/ CALL.REL.NOINC 0x2f0 ; /* 0x000000f000007944 */
/* 0x000fea0003c00000 */
/*0200*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ BSSY B0, 0x290 ; /* 0x0000006000007945 */
/* 0x000fe40003800000 */
/*0230*/ LDS R4, [0x28] ; /* 0x00002800ff047984 */
/* 0x000e240000000800 */
/*0240*/ FADD R5, R2, R4 ; /* 0x0000000402057221 */
/* 0x001fcc0000000000 */
/*0250*/ ATOMS.CAST.SPIN R5, [0x28], R4, R5 ; /* 0x00002804ff05738d */
/* 0x000e240001800005 */
/*0260*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x001fda0003f02070 */
/*0270*/ @!P0 BRA 0x230 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0203 */
/*02c0*/ LDS R5, [0x28] ; /* 0x00002800ff057984 */
/* 0x000e280000000800 */
/*02d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ SHF.R.U32.HI R4, RZ, 0x17, R11.reuse ; /* 0x00000017ff047819 */
/* 0x100fe2000001160b */
/*0300*/ BSSY B1, 0x950 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0310*/ SHF.R.U32.HI R3, RZ, 0x17, R8.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011608 */
/*0320*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0008 */
/*0330*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe200078ec0ff */
/*0340*/ IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000b */
/*0350*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fc400078ec0ff */
/*0360*/ IADD3 R10, R4, -0x1, RZ ; /* 0xffffffff040a7810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IADD3 R9, R3, -0x1, RZ ; /* 0xffffffff03097810 */
/* 0x000fe40007ffe0ff */
/*0380*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*0390*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*03a0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*03b0*/ @!P0 BRA 0x530 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*03c0*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*03d0*/ FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fc80003f3c200 */
/*03e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*03f0*/ @P0 BRA 0x930 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0410*/ @!P0 BRA 0x910 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; /* 0x7f8000000800780b */
/* 0x040fe40003f5d200 */
/*0430*/ FSETP.NEU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f3d200 */
/*0440*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*0450*/ @!P1 BRA !P2, 0x910 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0460*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*0470*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0480*/ @P1 BRA 0x8f0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0490*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*04a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*04b0*/ @P0 BRA 0x8c0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*04c0*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*04d0*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*04e0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*04f0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0500*/ @!P0 FFMA R5, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008058823 */
/* 0x000fe400000000ff */
/*0510*/ @!P1 FFMA R6, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b069823 */
/* 0x000fe200000000ff */
/*0520*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0530*/ LEA R9, R4, 0xc0800000, 0x17 ; /* 0xc080000004097811 */
/* 0x000fe200078eb8ff */
/*0540*/ BSSY B2, 0x8b0 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0550*/ IMAD.IADD R9, R6, 0x1, -R9 ; /* 0x0000000106097824 */
/* 0x000fe200078e0a09 */
/*0560*/ IADD3 R6, R3, -0x7f, RZ ; /* 0xffffff8103067810 */
/* 0x000fc60007ffe0ff */
/*0570*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e220000001000 */
/*0580*/ FADD.FTZ R10, -R9, -RZ ; /* 0x800000ff090a7221 */
/* 0x000fe40000010100 */
/*0590*/ IMAD R5, R6.reuse, -0x800000, R5 ; /* 0xff80000006057824 */
/* 0x040fe200078e0205 */
/*05a0*/ IADD3 R6, R6, 0x7f, -R4 ; /* 0x0000007f06067810 */
/* 0x000fca0007ffe804 */
/*05b0*/ IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106067824 */
/* 0x000fe400078e0207 */
/*05c0*/ FFMA R3, R8, R10, 1 ; /* 0x3f80000008037423 */
/* 0x001fc8000000000a */
/*05d0*/ FFMA R12, R8, R3, R8 ; /* 0x00000003080c7223 */
/* 0x000fc80000000008 */
/*05e0*/ FFMA R3, R5, R12, RZ ; /* 0x0000000c05037223 */
/* 0x000fc800000000ff */
/*05f0*/ FFMA R8, R10, R3, R5 ; /* 0x000000030a087223 */
/* 0x000fc80000000005 */
/*0600*/ FFMA R11, R12, R8, R3 ; /* 0x000000080c0b7223 */
/* 0x000fc80000000003 */
/*0610*/ FFMA R5, R10, R11, R5 ; /* 0x0000000b0a057223 */
/* 0x000fc80000000005 */
/*0620*/ FFMA R3, R12, R5, R11 ; /* 0x000000050c037223 */
/* 0x000fca000000000b */
/*0630*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0640*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0650*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0660*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0670*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0680*/ @!P0 BRA 0x890 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0690*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*06a0*/ @P0 BRA 0x860 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*06b0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*06c0*/ @P0 BRA 0x8a0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*06d0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*06e0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*06f0*/ @!P0 BRA 0x8a0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0700*/ FFMA.RZ R4, R12, R5.reuse, R11.reuse ; /* 0x000000050c047223 */
/* 0x180fe2000000c00b */
/*0710*/ IADD3 R7, R8.reuse, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x040fe40007ffe0ff */
/*0720*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*0730*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0740*/ FFMA.RP R4, R12, R5.reuse, R11.reuse ; /* 0x000000050c047223 */
/* 0x180fe2000000800b */
/*0750*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*0760*/ FFMA.RM R5, R12, R5, R11 ; /* 0x000000050c057223 */
/* 0x000fe2000000400b */
/*0770*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe200078efcff */
/*0780*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0a08 */
/*0790*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*07a0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fe40003f1d000 */
/*07b0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*07c0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*07d0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*07e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*07f0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fe40000011605 */
/*0800*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0810*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0820*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0830*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0840*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0850*/ BRA 0x8a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0860*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0870*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0880*/ BRA 0x8a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0890*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*08a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x940 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*08c0*/ LOP3.LUT R3, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fc800078e4805 */
/*08d0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*08e0*/ BRA 0x940 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08f0*/ LOP3.LUT R3, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fe200078e4805 */
/*0900*/ BRA 0x940 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0910*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0920*/ BRA 0x940 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0930*/ FADD.FTZ R3, R8, R11 ; /* 0x0000000b08037221 */
/* 0x000fe40000010000 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*0960*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0970*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff68002007950 */
/* 0x000fea0003c3ffff */
/*0980*/ BRA 0x980; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8fwd_percPfS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e680000002500 */
/*0050*/ STS [0x320], RZ ; /* 0x000320ffff007388 */
/* 0x000fe60000000800 */
/*0060*/ IMAD.WIDE R2, R13, R7, c[0x0][0x160] ; /* 0x000058000d027625 */
/* 0x001fe200078e0207 */
/*0070*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0080*/ IMAD R0, R8, 0xc8, R13 ; /* 0x000000c808007824 */
/* 0x002fc800078e020d */
/*0090*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000eaa000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*00d0*/ BSSY B0, 0x160 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*00e0*/ FMUL R6, R4, R3 ; /* 0x0000000304067220 */
/* 0x004fca0000400000 */
/*00f0*/ STS [R13.X4], R6 ; /* 0x000000060d007388 */
/* 0x0001e80000004800 */
/*0100*/ LDS R2, [0x320] ; /* 0x00032000ff027984 */
/* 0x000e640000000800 */
/*0110*/ FADD R3, R6, R2 ; /* 0x0000000206037221 */
/* 0x002fcc0000000000 */
/*0120*/ ATOMS.CAST.SPIN R3, [0x320], R2, R3 ; /* 0x00032002ff03738d */
/* 0x000e640001800003 */
/*0130*/ ISETP.EQ.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x002fda0003f02070 */
/*0140*/ @!P0 BRA 0x100 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0170*/ IMAD.WIDE R2, R8, R7, c[0x0][0x180] ; /* 0x0000600008027625 */
/* 0x000fc800078e0207 */
/*0180*/ IMAD.WIDE R4, R0, R7, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fc800078e0207 */
/*0190*/ IMAD.WIDE R6, R8, R7, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x001fe200078e0207 */
/*01a0*/ LDS R11, [0x320] ; /* 0x00032000ff0b7984 */
/* 0x000e280000000800 */
/*01b0*/ LDS R13, [R13.X4] ; /* 0x000000000d0d7984 */
/* 0x000e620000004800 */
/*01c0*/ FSETP.GEU.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x001fc60003f0e000 */
/*01d0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*01e0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x002fec000c101904 */
/*01f0*/ @P0 MOV R9, R11 ; /* 0x0000000b00090202 */
/* 0x000fca0000000f00 */
/*0200*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8fwd_percPfS_S_S_S_
.globl _Z8fwd_percPfS_S_S_S_
.p2align 8
.type _Z8fwd_percPfS_S_S_S_,@function
_Z8fwd_percPfS_S_S_S_:
s_mov_b32 s2, s15
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s2, 0xc8, v[0:1]
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_mov_b32 s3, exec_lo
ds_store_b32 v5, v5 offset:800
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v5, v0, s[6:7]
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v5, v3
v_bfrev_b32_e32 v3, 1
ds_store_b32 v0, v4
.LBB0_1:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v4, s4
s_lshl_b32 s4, 1, s4
s_and_not1_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_add_f32_e32 v3, s5, v3
s_cbranch_scc1 .LBB0_1
v_mbcnt_lo_u32_b32 v4, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v4
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v4, 0
ds_add_f32 v4, v3 offset:800
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v3, 0
s_load_b128 s[4:7], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v3 offset:800
ds_load_b32 v5, v0
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[2:3], s[2:3], 2
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, 0, v4
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_cndmask_b32_e32 v2, 0, v4, vcc_lo
global_store_b32 v3, v4, s[6:7]
global_store_b32 v[0:1], v5, off
global_store_b32 v3, v2, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8fwd_percPfS_S_S_S_
.amdhsa_group_segment_fixed_size 804
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8fwd_percPfS_S_S_S_, .Lfunc_end0-_Z8fwd_percPfS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8lrp_percPfS_S_S_
.globl _Z8lrp_percPfS_S_S_
.p2align 8
.type _Z8lrp_percPfS_S_S_,@function
_Z8lrp_percPfS_S_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x0
s_mov_b32 s2, s15
v_lshlrev_b32_e32 v3, 2, v0
v_mad_u32_u24 v1, v0, 0xc8, s2
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo
s_clause 0x1
global_load_b32 v2, v3, s[6:7]
global_load_b32 v4, v3, s[8:9]
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
ds_store_b32 v1, v1 offset:40
s_waitcnt vmcnt(2)
ds_store_b32 v3, v2 offset:96
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v3, v0, v4 offset1:12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[0:1], v3 offset1:12
ds_load_b32 v2, v3 offset:96
s_waitcnt lgkmcnt(1)
v_mul_f32_e32 v0, v0, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v1, null, v2, v2, v0
v_div_scale_f32 v5, vcc_lo, v0, v2, v0
v_rcp_f32_e32 v3, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v1, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v3
v_mul_f32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v1, v4, v5
v_fmac_f32_e32 v4, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, -v1, v4, v5
v_div_fmas_f32 v1, v1, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v1, v1, v2, v0
v_bfrev_b32_e32 v0, 1
.LBB1_1:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v1, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s3, s3, s4
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, s5, v0
s_cbranch_scc1 .LBB1_1
v_mbcnt_lo_u32_b32 v1, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB1_4
v_mov_b32_e32 v1, 0
ds_add_f32 v1, v0 offset:40
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v0 offset:40
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8lrp_percPfS_S_S_
.amdhsa_group_segment_fixed_size 136
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8lrp_percPfS_S_S_, .Lfunc_end1-_Z8lrp_percPfS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 804
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8fwd_percPfS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8fwd_percPfS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 136
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8lrp_percPfS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8lrp_percPfS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00008c99_00000000-6_dense_relu_lrp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21getTimeMicroseconds64v
.type _Z21getTimeMicroseconds64v, @function
_Z21getTimeMicroseconds64v:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
movl $0, %edi
call clock_gettime@PLT
movq 8(%rsp), %rdx
shrq $3, %rdx
movabsq $2361183241434822607, %rcx
movq %rdx, %rax
mulq %rcx
movq %rdx, %rax
shrq $4, %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z21getTimeMicroseconds64v, .-_Z21getTimeMicroseconds64v
.globl _Z11lrp_perc_gmPfS_S_S_S_S_ii
.type _Z11lrp_perc_gmPfS_S_S_S_S_ii, @function
_Z11lrp_perc_gmPfS_S_S_S_S_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdx, %r15
movl 56(%rsp), %r11d
movl 64(%rsp), %r13d
testl %r13d, %r13d
jle .L8
movq %rcx, %r12
movq %rsi, %rbx
movq %r9, %rdx
movslq %r13d, %rax
leaq (%r9,%rax,4), %r14
movslq %r11d, %r10
salq $2, %r10
movl $0, %ebp
pxor %xmm1, %xmm1
movq %rsi, -8(%rsp)
jmp .L9
.L28:
movl $0x00000000, (%rbx)
.L13:
addq $4, %rbx
addq $4, %rdx
addl %r11d, %ebp
cmpq %r14, %rdx
je .L26
.L9:
testl %r11d, %r11d
jle .L15
movslq %ebp, %rcx
salq $2, %rcx
leaq (%r12,%rcx), %rsi
addq %r8, %rcx
movl $0, %eax
.L10:
movss (%rdi,%rax), %xmm0
mulss (%rsi,%rax), %xmm0
movss %xmm0, (%rcx,%rax)
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
cmpq %r10, %rax
jne .L10
.L15:
movss (%rdx), %xmm0
comiss %xmm0, %xmm1
ja .L28
movss %xmm0, (%rbx)
jmp .L13
.L26:
movq -8(%rsp), %rsi
.L8:
testl %r11d, %r11d
jle .L7
movq %r15, %rcx
movslq %r11d, %r10
salq $2, %r10
movslq %r13d, %rdi
salq $2, %rdi
movl $0, %ebx
jmp .L17
.L18:
movss (%rdx), %xmm0
mulss (%rsi,%rax), %xmm0
divss (%r9,%rax), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq %r10, %rdx
addq $4, %rax
cmpq %rdi, %rax
jne .L18
.L19:
addl $1, %ebx
addq $4, %r8
addq $4, %rcx
cmpl %ebx, %r11d
je .L7
.L17:
movq %r8, %rdx
movl $0, %eax
testl %r13d, %r13d
jg .L18
jmp .L19
.L7:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11lrp_perc_gmPfS_S_S_S_S_ii, .-_Z11lrp_perc_gmPfS_S_S_S_S_ii
.globl _Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_
.type _Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_, @function
_Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8fwd_percPfS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_, .-_Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_
.globl _Z8fwd_percPfS_S_S_S_
.type _Z8fwd_percPfS_S_S_S_, @function
_Z8fwd_percPfS_S_S_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8fwd_percPfS_S_S_S_, .-_Z8fwd_percPfS_S_S_S_
.globl _Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_
.type _Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_, @function
_Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8lrp_percPfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_, .-_Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_
.globl _Z8lrp_percPfS_S_S_
.type _Z8lrp_percPfS_S_S_, @function
_Z8lrp_percPfS_S_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z8lrp_percPfS_S_S_, .-_Z8lrp_percPfS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s\n"
.LC2:
.string "### RELEVANCE ###\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Error: golden_relevance[%d]!=cuda_relevance[%d] (%f, %f)\n"
.section .rodata.str1.1
.LC4:
.string "### OUT ###\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "Error: golden_out[%d]!=cuda_out[%d] (%f, %f)\n"
.section .rodata.str1.1
.LC6:
.string "### ACTIVATIONS ###\n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Error: golden_activations[%d]!=cuda_activations[%d] (%f, %f)\n"
.section .rodata.str1.1
.LC8:
.string "### ASUM ###\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Error: golden_asum[%d]!=cuda_asum[%d] (%f, %f)\n"
.align 8
.LC10:
.string "GPU time: %lu, \tCPU time: %lu\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -24576(%rsp), %r11
.cfi_def_cfa 11, 24632
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2120, %rsp
.cfi_def_cfa_offset 26752
movq %fs:40, %rax
movq %rax, 26680(%rsp)
xorl %eax, %eax
movl $8000, %ebp
movl $0, %r12d
leaq -7728(%rsp), %r13
jmp .L47
.L77:
addl $1, %r12d
addq $4, %rbp
cmpl $200, %r12d
je .L76
.L47:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rbp)
movl $0x00000000, -6928(%rsp,%rbp)
movl $0x00000000, -6128(%rsp,%rbp)
leaq -8000(%rbp), %rbx
.L46:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 2672(%rsp,%rbx)
movl $0x00000000, 10672(%rsp,%rbx)
movl $0x00000000, 18672(%rsp,%rbx)
addq $800, %rbx
cmpq %rbp, %rbx
jne .L46
jmp .L77
.L76:
movl $0, %eax
.L48:
movl $0x00000000, 80(%rsp,%rax)
movl $0x00000000, 128(%rsp,%rax)
movl $0x00000000, 176(%rsp,%rax)
movl $0x00000000, 224(%rsp,%rax)
addq $4, %rax
cmpq $40, %rax
jne .L48
leaq 8(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 272(%rsp), %rbx
movl $1, %ecx
movl $800, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 2672(%rsp), %rbp
movl $1, %ecx
movl $8000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $40, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $800, %edx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
movl $8000, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl $40, %edx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
call _Z21getTimeMicroseconds64v
movq %rax, %r15
leaq 1072(%rsp), %rdx
leaq 80(%rsp), %rsi
pushq $10
.cfi_def_cfa_offset 26760
pushq $200
.cfi_def_cfa_offset 26768
leaq 192(%rsp), %r9
leaq 10688(%rsp), %r8
movq %rbp, %rcx
movq %rbx, %rdi
call _Z11lrp_perc_gmPfS_S_S_S_S_ii
call _Z21getTimeMicroseconds64v
movq %rax, %r12
call _Z21getTimeMicroseconds64v
movq %rax, %r13
movl $200, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $10, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 26752
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L78
.L49:
movl $10, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $200, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L79
.L50:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
call _Z21getTimeMicroseconds64v
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1872(%rsp), %rdi
movl $0, %r8d
movl $2, %ecx
movl $800, %edx
movq 32(%rsp), %rsi
call cudaMemcpyAsync@PLT
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %r14
jmp .L53
.L78:
movq 48(%rsp), %r8
movq 40(%rsp), %rcx
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z8fwd_percPfS_S_S_S_PfS_S_S_S_
jmp .L49
.L79:
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z8lrp_percPfS_S_S_PfS_S_S_
jmp .L50
.L64:
movl %ebx, %edx
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L51:
addq $1, %rbx
cmpq $200, %rbx
je .L80
.L53:
movss 1072(%rsp,%rbx,4), %xmm0
movss 1872(%rsp,%rbx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L64
je .L51
jmp .L64
.L80:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 128(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC5(%rip), %r14
jmp .L56
.L65:
movl %ebx, %edx
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L54:
addq $1, %rbx
cmpq $10, %rbx
je .L81
.L56:
movss 80(%rsp,%rbx,4), %xmm0
movss 128(%rsp,%rbx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L65
je .L54
jmp .L65
.L81:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 18672(%rsp), %rdi
movl $2, %ecx
movl $8000, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC7(%rip), %r14
jmp .L59
.L66:
movl %ebx, %edx
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L57:
addq $1, %rbx
cmpq $2000, %rbx
je .L82
.L59:
movss 10672(%rsp,%rbx,4), %xmm0
movss 18672(%rsp,%rbx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L66
je .L57
jmp .L66
.L82:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 224(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC9(%rip), %r14
jmp .L62
.L67:
movl %ebx, %edx
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %ebx, %ecx
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L60:
addq $1, %rbx
cmpq $10, %rbx
je .L83
.L62:
movss 176(%rsp,%rbx,4), %xmm0
movss 224(%rsp,%rbx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L67
je .L60
jmp .L67
.L83:
movq %r12, %rcx
subq %r15, %rcx
salq $16, %rcx
movq %rbp, %rdx
subq %r13, %rdx
salq $16, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 26680(%rsp), %rax
subq %fs:40, %rax
jne .L84
movl $0, %eax
addq $26696, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z8lrp_percPfS_S_S_"
.LC12:
.string "_Z8fwd_percPfS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z8lrp_percPfS_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z8fwd_percPfS_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dense_relu_lrp.hip"
.globl _Z21getTimeMicroseconds64v # -- Begin function _Z21getTimeMicroseconds64v
.p2align 4, 0x90
.type _Z21getTimeMicroseconds64v,@function
_Z21getTimeMicroseconds64v: # @_Z21getTimeMicroseconds64v
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 16(%rsp), %rax
shrq $3, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
mulq %rcx
movq %rdx, %rax
shrq $4, %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z21getTimeMicroseconds64v, .Lfunc_end0-_Z21getTimeMicroseconds64v
.cfi_endproc
# -- End function
.globl _Z23__device_stub__fwd_percPfS_S_S_S_ # -- Begin function _Z23__device_stub__fwd_percPfS_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__fwd_percPfS_S_S_S_,@function
_Z23__device_stub__fwd_percPfS_S_S_S_: # @_Z23__device_stub__fwd_percPfS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8fwd_percPfS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z23__device_stub__fwd_percPfS_S_S_S_, .Lfunc_end1-_Z23__device_stub__fwd_percPfS_S_S_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__lrp_percPfS_S_S_ # -- Begin function _Z23__device_stub__lrp_percPfS_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__lrp_percPfS_S_S_,@function
_Z23__device_stub__lrp_percPfS_S_S_: # @_Z23__device_stub__lrp_percPfS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8lrp_percPfS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z23__device_stub__lrp_percPfS_S_S_, .Lfunc_end2-_Z23__device_stub__lrp_percPfS_S_S_
.cfi_endproc
# -- End function
.globl _Z11lrp_perc_gmPfS_S_S_S_S_ii # -- Begin function _Z11lrp_perc_gmPfS_S_S_S_S_ii
.p2align 4, 0x90
.type _Z11lrp_perc_gmPfS_S_S_S_S_ii,@function
_Z11lrp_perc_gmPfS_S_S_S_S_ii: # @_Z11lrp_perc_gmPfS_S_S_S_S_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl 64(%rsp), %eax
movl 56(%rsp), %ebx
movl %eax, %r10d
movl %ebx, %r11d
testl %eax, %eax
jle .LBB3_6
# %bb.1: # %.preheader52.lr.ph
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
xorps %xmm0, %xmm0
maxss (%r9,%r15,4), %xmm0
movss %xmm0, (%rsi,%r15,4)
incq %r15
addl %ebx, %r14d
cmpq %r10, %r15
je .LBB3_6
.LBB3_2: # %.preheader52
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ebx, %ebx
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r14d, %r13d
leaq (%r8,%r13,4), %r12
leaq (%rcx,%r13,4), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r13,%rbp,4), %xmm0
movss %xmm0, (%r12,%rbp,4)
addss (%r9,%r15,4), %xmm0
movss %xmm0, (%r9,%r15,4)
incq %rbp
cmpq %rbp, %r11
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %.preheader51
testl %ebx, %ebx
jle .LBB3_12
# %bb.7: # %.preheader.lr.ph
leaq (,%r11,4), %rcx
xorl %edi, %edi
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_11: # %._crit_edge57
# in Loop: Header=BB3_8 Depth=1
incq %rdi
addq $4, %r8
cmpq %r11, %rdi
je .LBB3_12
.LBB3_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
testl %eax, %eax
jle .LBB3_11
# %bb.9: # %.lr.ph56
# in Loop: Header=BB3_8 Depth=1
movss (%rdx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r8, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rsi,%r14,4), %xmm1
divss (%r9,%r14,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rdx,%rdi,4)
incq %r14
addq %rcx, %rbx
cmpq %r14, %r10
jne .LBB3_10
jmp .LBB3_11
.LBB3_12: # %._crit_edge59
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11lrp_perc_gmPfS_S_S_S_S_ii, .Lfunc_end3-_Z11lrp_perc_gmPfS_S_S_S_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $26776, %rsp # imm = 0x6898
.cfi_def_cfa_offset 26832
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 10768(%rsp), %rbx
leaq 2768(%rsp), %r14
leaq 18768(%rsp), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_1: # =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 1968(%rsp,%r12,4)
movl $0, 368(%rsp,%r12,4)
movl $0, 1168(%rsp,%r12,4)
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r13)
movl $0, (%r14,%r13)
movl $0, (%rbx,%r13)
addq $800, %r13 # imm = 0x320
cmpq $8000, %r13 # imm = 0x1F40
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %r12
addq $4, %rbx
addq $4, %r14
addq $4, %r15
cmpq $200, %r12
jne .LBB4_1
# %bb.4: # %.preheader.preheader
xorps %xmm0, %xmm0
movaps %xmm0, 240(%rsp)
movaps %xmm0, 224(%rsp)
movq $0, 256(%rsp)
movaps %xmm0, 320(%rsp)
movaps %xmm0, 336(%rsp)
movq $0, 352(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 192(%rsp)
movq $0, 208(%rsp)
movaps %xmm0, 272(%rsp)
movaps %xmm0, 288(%rsp)
movq $0, 304(%rsp)
leaq 40(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
leaq 32(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 40(%rsp), %rdi
leaq 1968(%rsp), %rsi
movl $800, %edx # imm = 0x320
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
leaq 18768(%rsp), %r14
movl $8000, %edx # imm = 0x1F40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %r15d, %r15d
movl $40, %edx
xorl %esi, %esi
callq hipMemset
movq 24(%rsp), %rdi
movl $800, %edx # imm = 0x320
xorl %esi, %esi
callq hipMemset
movq 8(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
xorl %esi, %esi
callq hipMemset
movq (%rsp), %rdi
movl $40, %edx
xorl %esi, %esi
callq hipMemset
leaq 128(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 136(%rsp), %rbx
leaq 2768(%rsp), %rax
.p2align 4, 0x90
.LBB4_5: # %.preheader52.i
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
movss 176(%rsp,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movss 1968(%rsp,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r14,%rcx,4), %xmm1
movss %xmm1, (%rax,%rcx,4)
addss %xmm1, %xmm0
incq %rcx
cmpq $200, %rcx
jne .LBB4_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB4_5 Depth=1
movss %xmm0, 176(%rsp,%r15,4)
xorps %xmm1, %xmm1
maxss %xmm0, %xmm1
movss %xmm1, 224(%rsp,%r15,4)
incq %r15
addq $800, %rax # imm = 0x320
addq $800, %r14 # imm = 0x320
cmpq $10, %r15
jne .LBB4_5
# %bb.8: # %.preheader.i.preheader
leaq 2768(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_9: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_10 Depth 2
movss 368(%rsp,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_10: # Parent Loop BB4_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss 224(%rsp,%rsi,4), %xmm1
divss 176(%rsp,%rsi,4), %xmm1
addss %xmm1, %xmm0
incq %rsi
addq $800, %rdx # imm = 0x320
cmpq $10, %rsi
jne .LBB4_10
# %bb.11: # %._crit_edge57.i
# in Loop: Header=BB4_9 Depth=1
movss %xmm0, 368(%rsp,%rcx,4)
incq %rcx
addq $4, %rax
cmpq $200, %rcx
jne .LBB4_9
# %bb.12: # %_Z11lrp_perc_gmPfS_S_S_S_S_ii.exit
movabsq $4294967306, %r12 # imm = 0x10000000A
leaq 128(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 136(%rsp), %r14
leaq 128(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 136(%rsp), %r15
leaq 190(%r12), %r13
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_14
# %bb.13:
movq 40(%rsp), %rax
movq 16(%rsp), %rcx
movq 32(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdi, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 168(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8fwd_percPfS_S_S_S_, %edi
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_14:
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_16
# %bb.15:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8lrp_percPfS_S_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_16:
callq hipDeviceSynchronize
movl %eax, %ebp
xorl %r13d, %r13d
leaq 128(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 136(%rsp), %r12
movl %ebp, %edi
callq hipGetErrorName
movq %rax, %rdi
callq puts@PLT
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rsi
leaq 1168(%rsp), %rdi
movl $800, %edx # imm = 0x320
movl $2, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
movl %eax, %edi
callq hipGetErrorName
movq %rax, %rdi
callq puts@PLT
jmp .LBB4_17
.p2align 4, 0x90
.LBB4_19: # in Loop: Header=BB4_17 Depth=1
incq %r13
cmpq $200, %r13
je .LBB4_20
.LBB4_17: # =>This Inner Loop Header: Depth=1
movss 368(%rsp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 1168(%rsp,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_18
jnp .LBB4_19
.LBB4_18: # in Loop: Header=BB4_17 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.2, %edi
movl %r13d, %esi
movl %r13d, %edx
movb $2, %al
callq printf
jmp .LBB4_19
.LBB4_20:
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %rsi
leaq 320(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorName
movq %rax, %rdi
callq puts@PLT
xorl %r13d, %r13d
jmp .LBB4_21
.p2align 4, 0x90
.LBB4_23: # in Loop: Header=BB4_21 Depth=1
incq %r13
cmpq $10, %r13
je .LBB4_24
.LBB4_21: # =>This Inner Loop Header: Depth=1
movss 224(%rsp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 320(%rsp,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_22
jnp .LBB4_23
.LBB4_22: # in Loop: Header=BB4_21 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %edi
movl %r13d, %esi
movl %r13d, %edx
movb $2, %al
callq printf
jmp .LBB4_23
.LBB4_24:
movl $.Lstr.2, %edi
callq puts@PLT
movq 8(%rsp), %rsi
leaq 10768(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorName
movq %rax, %rdi
callq puts@PLT
xorl %r13d, %r13d
jmp .LBB4_25
.p2align 4, 0x90
.LBB4_27: # in Loop: Header=BB4_25 Depth=1
incq %r13
cmpq $2000, %r13 # imm = 0x7D0
je .LBB4_28
.LBB4_25: # =>This Inner Loop Header: Depth=1
movss 2768(%rsp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 10768(%rsp,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_26
jnp .LBB4_27
.LBB4_26: # in Loop: Header=BB4_25 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.6, %edi
movl %r13d, %esi
movl %r13d, %edx
movb $2, %al
callq printf
jmp .LBB4_27
.LBB4_28:
movl $.Lstr.3, %edi
callq puts@PLT
movq (%rsp), %rsi
leaq 272(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorName
movq %rax, %rdi
callq puts@PLT
xorl %r13d, %r13d
jmp .LBB4_29
.p2align 4, 0x90
.LBB4_31: # in Loop: Header=BB4_29 Depth=1
incq %r13
cmpq $10, %r13
je .LBB4_32
.LBB4_29: # =>This Inner Loop Header: Depth=1
movss 176(%rsp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 272(%rsp,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_30
jnp .LBB4_31
.LBB4_30: # in Loop: Header=BB4_29 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.8, %edi
movl %r13d, %esi
movl %r13d, %edx
movb $2, %al
callq printf
jmp .LBB4_31
.LBB4_32:
shrq $3, %r12
movabsq $2361183241434822607, %rdi # imm = 0x20C49BA5E353F7CF
movq %r12, %rax
mulq %rdi
movq %rdx, %rsi
shrq $4, %rsi
shrq $3, %r15
movq %r15, %rax
mulq %rdi
movq %rdx, %rcx
shrq $4, %rcx
shrq $3, %r14
movq %r14, %rax
mulq %rdi
movq %rdx, %r8
subq %rcx, %rsi
shrq $4, %r8
shrq $3, %rbx
movq %rbx, %rax
mulq %rdi
shrq $4, %rdx
subq %rdx, %r8
shlq $16, %rsi
shlq $16, %r8
movl $.L.str.9, %edi
movq %r8, %rdx
xorl %eax, %eax
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $26776, %rsp # imm = 0x6898
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8fwd_percPfS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8lrp_percPfS_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8fwd_percPfS_S_S_S_,@object # @_Z8fwd_percPfS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z8fwd_percPfS_S_S_S_
.p2align 3, 0x0
_Z8fwd_percPfS_S_S_S_:
.quad _Z23__device_stub__fwd_percPfS_S_S_S_
.size _Z8fwd_percPfS_S_S_S_, 8
.type _Z8lrp_percPfS_S_S_,@object # @_Z8lrp_percPfS_S_S_
.globl _Z8lrp_percPfS_S_S_
.p2align 3, 0x0
_Z8lrp_percPfS_S_S_:
.quad _Z23__device_stub__lrp_percPfS_S_S_
.size _Z8lrp_percPfS_S_S_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Error: golden_relevance[%d]!=cuda_relevance[%d] (%f, %f)\n"
.size .L.str.2, 58
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error: golden_out[%d]!=cuda_out[%d] (%f, %f)\n"
.size .L.str.4, 46
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error: golden_activations[%d]!=cuda_activations[%d] (%f, %f)\n"
.size .L.str.6, 62
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error: golden_asum[%d]!=cuda_asum[%d] (%f, %f)\n"
.size .L.str.8, 48
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "GPU time: %lu, \tCPU time: %lu\n"
.size .L.str.9, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8fwd_percPfS_S_S_S_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8lrp_percPfS_S_S_"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "### RELEVANCE ###"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "### OUT ###"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "### ACTIVATIONS ###"
.size .Lstr.2, 20
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "### ASUM ###"
.size .Lstr.3, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__fwd_percPfS_S_S_S_
.addrsig_sym _Z23__device_stub__lrp_percPfS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8fwd_percPfS_S_S_S_
.addrsig_sym _Z8lrp_percPfS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define DIM 2048
#define N (DIM*DIM)
#define THREAD_PER_BLOCK 512
__global__ void add(int* a, int* b, int* c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
void randomInts(int* a, int size)
{
std::random_device random;
for (int i = 0 ; i < size ; ++i)
a[i] = random() % 1000;
}
void printMatrix(int* m, int dim)
{
printf("matrix %p :\n", m);
for(int i = 0 ; i < 3 ; ++i)
{
for(int j = 0 ; j < 2 ; ++j)
printf("%d\t", m[i+j*dim]);
printf("%d...\n", m[i+2*dim]);
}
printf("...\n\n");
}
// nvcc -o bin/exo2 src/exo2.cu
int main(void)
{
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
a = (int*)malloc(size); randomInts(a, N);
b = (int*)malloc(size); randomInts(b, N);
c = (int*)malloc(size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
auto t1 = std::chrono::high_resolution_clock::now();
add<<<N/THREAD_PER_BLOCK,THREAD_PER_BLOCK>>>(d_a, d_b, d_c);
auto t2 = std::chrono::high_resolution_clock::now();
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// j'affiche les 3 premières lignes/col de la mat1, mat2
// et mat résultat
printMatrix(a, DIM); printMatrix(b, DIM); printMatrix(c, DIM);
auto int_us = std::chrono::duration_cast<std::chrono::microseconds>(t2 - t1);
std::cout<<"done in "<<int_us.count()<<" μs"<<std::endl;
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define DIM 2048
#define N (DIM*DIM)
#define THREAD_PER_BLOCK 512
__global__ void add(int* a, int* b, int* c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
void randomInts(int* a, int size)
{
std::random_device random;
for (int i = 0 ; i < size ; ++i)
a[i] = random() % 1000;
}
void printMatrix(int* m, int dim)
{
printf("matrix %p :\n", m);
for(int i = 0 ; i < 3 ; ++i)
{
for(int j = 0 ; j < 2 ; ++j)
printf("%d\t", m[i+j*dim]);
printf("%d...\n", m[i+2*dim]);
}
printf("...\n\n");
}
// nvcc -o bin/exo2 src/exo2.cu
int main(void)
{
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
a = (int*)malloc(size); randomInts(a, N);
b = (int*)malloc(size); randomInts(b, N);
c = (int*)malloc(size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
auto t1 = std::chrono::high_resolution_clock::now();
add<<<N/THREAD_PER_BLOCK,THREAD_PER_BLOCK>>>(d_a, d_b, d_c);
auto t2 = std::chrono::high_resolution_clock::now();
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// j'affiche les 3 premières lignes/col de la mat1, mat2
// et mat résultat
printMatrix(a, DIM); printMatrix(b, DIM); printMatrix(c, DIM);
auto int_us = std::chrono::duration_cast<std::chrono::microseconds>(t2 - t1);
std::cout<<"done in "<<int_us.count()<<" μs"<<std::endl;
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | .file "tmpxft_0001f00d_00000000-6_exo2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4860:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4860:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10randomIntsPii
.type _Z10randomIntsPii, @function
_Z10randomIntsPii:
.LFB4852:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4852
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $944, %rsp
.cfi_def_cfa_offset 5072
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 5032(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movl $1634100580, 16(%rsp)
movl $1953264993, 19(%rsp)
movq $7, 8(%rsp)
movb $0, 23(%rsp)
leaq 32(%rsp), %rdi
.LEHB0:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE0:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L4
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L4:
testl %ebp, %ebp
jle .L6
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r12
leaq 32(%rsp), %rbp
jmp .L9
.L14:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 5032(%rsp), %rax
subq %fs:40, %rax
je .L8
call __stack_chk_fail@PLT
.L8:
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L18:
movl %eax, %edx
imulq $274877907, %rdx, %rdx
shrq $38, %rdx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbx, %r12
je .L6
.L9:
movq %rbp, %rdi
.LEHB2:
call _ZNSt13random_device9_M_getvalEv@PLT
.LEHE2:
jmp .L18
.L6:
leaq 32(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 5032(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $5040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 5032(%rsp), %rax
subq %fs:40, %rax
je .L11
call __stack_chk_fail@PLT
.L11:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4852:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4852:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4852-.LLSDACSB4852
.LLSDACSB4852:
.uleb128 .LEHB0-.LFB4852
.uleb128 .LEHE0-.LEHB0
.uleb128 .L14-.LFB4852
.uleb128 0
.uleb128 .LEHB1-.LFB4852
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.uleb128 .LEHB2-.LFB4852
.uleb128 .LEHE2-.LEHB2
.uleb128 .L13-.LFB4852
.uleb128 0
.uleb128 .LEHB3-.LFB4852
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4852:
.text
.size _Z10randomIntsPii, .-_Z10randomIntsPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "matrix %p :\n"
.LC1:
.string "%d\t"
.LC2:
.string "%d...\n"
.LC3:
.string "...\n\n"
.text
.globl _Z11printMatrixPii
.type _Z11printMatrixPii, @function
_Z11printMatrixPii:
.LFB4853:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl %esi, %r12d
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $12, %rbp
leal (%r12,%r12), %r14d
movslq %r14d, %r14
leaq .LC1(%rip), %r13
movslq %r12d, %r12
leaq .LC2(%rip), %r15
.L21:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rbx,%r12,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rbx,%r14,4), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L21
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4853:
.size _Z11printMatrixPii, .-_Z11printMatrixPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB4882:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4882:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB4883:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4883:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1
.LC4:
.string "done in "
.LC5:
.string " \316\274s"
.text
.globl main
.type main, @function
main:
.LFB4854:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %esi
movq %rax, %rdi
call _Z10randomIntsPii
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %esi
movq %rax, %rdi
call _Z10randomIntsPii
movl $16777216, %edi
call malloc@PLT
movq %rax, %r13
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r14
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L33:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2048, %esi
movq %r12, %rdi
call _Z11printMatrixPii
movl $2048, %esi
movq %rbp, %rdi
call _Z11printMatrixPii
movl $2048, %esi
movq %r13, %rdi
call _Z11printMatrixPii
subq %r14, %rbx
movq %rbx, %rcx
movabsq $2361183241434822607, %rdx
movq %rbx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rbx
subq %rcx, %rbx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L33
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4854:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4885:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4885:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define DIM 2048
#define N (DIM*DIM)
#define THREAD_PER_BLOCK 512
__global__ void add(int* a, int* b, int* c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
void randomInts(int* a, int size)
{
std::random_device random;
for (int i = 0 ; i < size ; ++i)
a[i] = random() % 1000;
}
void printMatrix(int* m, int dim)
{
printf("matrix %p :\n", m);
for(int i = 0 ; i < 3 ; ++i)
{
for(int j = 0 ; j < 2 ; ++j)
printf("%d\t", m[i+j*dim]);
printf("%d...\n", m[i+2*dim]);
}
printf("...\n\n");
}
// nvcc -o bin/exo2 src/exo2.cu
int main(void)
{
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
a = (int*)malloc(size); randomInts(a, N);
b = (int*)malloc(size); randomInts(b, N);
c = (int*)malloc(size);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
auto t1 = std::chrono::high_resolution_clock::now();
add<<<N/THREAD_PER_BLOCK,THREAD_PER_BLOCK>>>(d_a, d_b, d_c);
auto t2 = std::chrono::high_resolution_clock::now();
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
// j'affiche les 3 premières lignes/col de la mat1, mat2
// et mat résultat
printMatrix(a, DIM); printMatrix(b, DIM); printMatrix(c, DIM);
auto int_us = std::chrono::duration_cast<std::chrono::microseconds>(t2 - t1);
std::cout<<"done in "<<int_us.count()<<" μs"<<std::endl;
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define DIM 2048
#define N (DIM*DIM)
#define THREAD_PER_BLOCK 512
__global__ void add(int* a, int* b, int* c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
void randomInts(int* a, int size)
{
std::random_device random;
for (int i = 0 ; i < size ; ++i)
a[i] = random() % 1000;
}
void printMatrix(int* m, int dim)
{
printf("matrix %p :\n", m);
for(int i = 0 ; i < 3 ; ++i)
{
for(int j = 0 ; j < 2 ; ++j)
printf("%d\t", m[i+j*dim]);
printf("%d...\n", m[i+2*dim]);
}
printf("...\n\n");
}
// nvcc -o bin/exo2 src/exo2.cu
int main(void)
{
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
a = (int*)malloc(size); randomInts(a, N);
b = (int*)malloc(size); randomInts(b, N);
c = (int*)malloc(size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
auto t1 = std::chrono::high_resolution_clock::now();
add<<<N/THREAD_PER_BLOCK,THREAD_PER_BLOCK>>>(d_a, d_b, d_c);
auto t2 = std::chrono::high_resolution_clock::now();
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// j'affiche les 3 premières lignes/col de la mat1, mat2
// et mat résultat
printMatrix(a, DIM); printMatrix(b, DIM); printMatrix(c, DIM);
auto int_us = std::chrono::duration_cast<std::chrono::microseconds>(t2 - t1);
std::cout<<"done in "<<int_us.count()<<" μs"<<std::endl;
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define DIM 2048
#define N (DIM*DIM)
#define THREAD_PER_BLOCK 512
__global__ void add(int* a, int* b, int* c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
void randomInts(int* a, int size)
{
std::random_device random;
for (int i = 0 ; i < size ; ++i)
a[i] = random() % 1000;
}
void printMatrix(int* m, int dim)
{
printf("matrix %p :\n", m);
for(int i = 0 ; i < 3 ; ++i)
{
for(int j = 0 ; j < 2 ; ++j)
printf("%d\t", m[i+j*dim]);
printf("%d...\n", m[i+2*dim]);
}
printf("...\n\n");
}
// nvcc -o bin/exo2 src/exo2.cu
int main(void)
{
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
a = (int*)malloc(size); randomInts(a, N);
b = (int*)malloc(size); randomInts(b, N);
c = (int*)malloc(size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
auto t1 = std::chrono::high_resolution_clock::now();
add<<<N/THREAD_PER_BLOCK,THREAD_PER_BLOCK>>>(d_a, d_b, d_c);
auto t2 = std::chrono::high_resolution_clock::now();
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// j'affiche les 3 premières lignes/col de la mat1, mat2
// et mat résultat
printMatrix(a, DIM); printMatrix(b, DIM); printMatrix(c, DIM);
auto int_us = std::chrono::duration_cast<std::chrono::microseconds>(t2 - t1);
std::cout<<"done in "<<int_us.count()<<" μs"<<std::endl;
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// #include <cuda.h>
#include <iostream>
#include <random>
#include <chrono>
#define DIM 2048
#define N (DIM*DIM)
#define THREAD_PER_BLOCK 512
__global__ void add(int* a, int* b, int* c)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
c[index] = a[index] + b[index];
}
void randomInts(int* a, int size)
{
std::random_device random;
for (int i = 0 ; i < size ; ++i)
a[i] = random() % 1000;
}
void printMatrix(int* m, int dim)
{
printf("matrix %p :\n", m);
for(int i = 0 ; i < 3 ; ++i)
{
for(int j = 0 ; j < 2 ; ++j)
printf("%d\t", m[i+j*dim]);
printf("%d...\n", m[i+2*dim]);
}
printf("...\n\n");
}
// nvcc -o bin/exo2 src/exo2.cu
int main(void)
{
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
a = (int*)malloc(size); randomInts(a, N);
b = (int*)malloc(size); randomInts(b, N);
c = (int*)malloc(size);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
auto t1 = std::chrono::high_resolution_clock::now();
add<<<N/THREAD_PER_BLOCK,THREAD_PER_BLOCK>>>(d_a, d_b, d_c);
auto t2 = std::chrono::high_resolution_clock::now();
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
// j'affiche les 3 premières lignes/col de la mat1, mat2
// et mat résultat
printMatrix(a, DIM); printMatrix(b, DIM); printMatrix(c, DIM);
auto int_us = std::chrono::duration_cast<std::chrono::microseconds>(t2 - t1);
std::cout<<"done in "<<int_us.count()<<" μs"<<std::endl;
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.file "exo2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z10randomIntsPii # -- Begin function _Z10randomIntsPii
.p2align 4, 0x90
.type _Z10randomIntsPii,@function
_Z10randomIntsPii: # @_Z10randomIntsPii
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $5040, %rsp # imm = 0x13B0
.cfi_def_cfa_offset 5088
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
leaq 24(%rsp), %r14
movq %r14, 8(%rsp)
movl $1634100580, 24(%rsp) # imm = 0x61666564
movl $1953264993, 27(%rsp) # imm = 0x746C7561
movq $7, 16(%rsp)
movb $0, 31(%rsp)
.Ltmp0:
leaq 40(%rsp), %rdi
leaq 8(%rsp), %rsi
callq _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq 8(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_3
# %bb.2: # %.critedge.i.i.i
callq _ZdlPv
.LBB1_3: # %_ZNSt13random_deviceC2Ev.exit
testl %ebp, %ebp
jle .LBB1_7
# %bb.4: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %r12d, %r12d
leaq 40(%rsp), %r14
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp3:
movq %r14, %rdi
callq _ZNSt13random_device9_M_getvalEv
.Ltmp4:
# %bb.6: # %_ZNSt13random_deviceclEv.exit
# in Loop: Header=BB1_5 Depth=1
movl %eax, %ecx
imulq $274877907, %rcx, %rcx # imm = 0x10624DD3
shrq $38, %rcx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB1_5
.LBB1_7: # %._crit_edge
.Ltmp9:
leaq 40(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp10:
# %bb.8: # %_ZNSt13random_deviceD2Ev.exit
addq $5040, %rsp # imm = 0x13B0
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 5088
.Ltmp11:
movq %rax, %rdi
callq __clang_call_terminate
.LBB1_9:
.Ltmp2:
movq %rax, %rbx
movq 8(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_11
# %bb.10: # %.critedge.i.i6.i
callq _ZdlPv
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB1_14:
.Ltmp5:
movq %rax, %rbx
.Ltmp6:
leaq 40(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp7:
.LBB1_11: # %common.resume
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB1_13:
.Ltmp8:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end1:
.size _Z10randomIntsPii, .Lfunc_end1-_Z10randomIntsPii
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 1 # On action: 1
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp10 # Call between .Ltmp10 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 1 # On action: 1
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end1-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z11printMatrixPii # -- Begin function _Z11printMatrixPii
.p2align 4, 0x90
.type _Z11printMatrixPii,@function
_Z11printMatrixPii: # @_Z11printMatrixPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movslq %ebp, %r14
addl %ebp, %ebp
movslq %ebp, %rax
leaq (%rbx,%rax,4), %r15
shlq $2, %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movl $1, %r13d
movq %rbx, %rbp
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
addq %r14, %rbp
decq %r13
je .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
addq $4, %rbx
cmpq $3, %r12
jne .LBB2_1
# %bb.4:
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end2:
.size _Z11printMatrixPii, .Lfunc_end2-_Z11printMatrixPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movl $4194304, %esi # imm = 0x400000
callq _Z10randomIntsPii
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
movq %rax, %rdi
movl $4194304, %esi # imm = 0x400000
callq _Z10randomIntsPii
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 32(%rsp) # 8-byte Spill
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 7680(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 24(%rsp) # 8-byte Spill
movq (%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq %rbx, %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r13), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
addq $8192, %r13 # imm = 0x2000
cmpq $8192, %r13 # imm = 0x2000
je .LBB3_4
# %bb.5: # in Loop: Header=BB3_3 Depth=1
movl 16384(%rbx,%r12,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
addq $4, %rbp
cmpq $3, %r12
jne .LBB3_3
# %bb.6: # %_Z11printMatrixPii.exit
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movq %r14, %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # %.preheader.i21
# =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_8: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r13), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
addq $8192, %r13 # imm = 0x2000
cmpq $8192, %r13 # imm = 0x2000
je .LBB3_8
# %bb.9: # in Loop: Header=BB3_7 Depth=1
movl 16384(%r14,%r12,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
addq $4, %rbp
cmpq $3, %r12
jne .LBB3_7
# %bb.10: # %_Z11printMatrixPii.exit28
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movq %r15, %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_11: # %.preheader.i29
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_12: # Parent Loop BB3_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r13), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
addq $8192, %r13 # imm = 0x2000
cmpq $8192, %r13 # imm = 0x2000
je .LBB3_12
# %bb.13: # in Loop: Header=BB3_11 Depth=1
movl 16384(%r15,%r12,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
addq $4, %rbp
cmpq $3, %r12
jne .LBB3_11
# %bb.14: # %_Z11printMatrixPii.exit36
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rax # 8-byte Reload
subq 32(%rsp), %rax # 8-byte Folded Reload
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r12
shrq $63, %r12
sarq $7, %rdx
addq %rdx, %r12
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r12, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r12
movl $.L.str.5, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB3_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB3_17
# %bb.16:
movzbl 67(%r13), %eax
jmp .LBB3_18
.LBB3_17:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_19:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end4:
.size __clang_call_terminate, .Lfunc_end4-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "matrix %p :\n"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\t"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d...\n"
.size .L.str.2, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "done in "
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " \316\274s"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "default"
.size .L.str.6, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "...\n"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001f00d_00000000-6_exo2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4860:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4860:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10randomIntsPii
.type _Z10randomIntsPii, @function
_Z10randomIntsPii:
.LFB4852:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4852
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $944, %rsp
.cfi_def_cfa_offset 5072
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 5032(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movl $1634100580, 16(%rsp)
movl $1953264993, 19(%rsp)
movq $7, 8(%rsp)
movb $0, 23(%rsp)
leaq 32(%rsp), %rdi
.LEHB0:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE0:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L4
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L4:
testl %ebp, %ebp
jle .L6
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r12
leaq 32(%rsp), %rbp
jmp .L9
.L14:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 5032(%rsp), %rax
subq %fs:40, %rax
je .L8
call __stack_chk_fail@PLT
.L8:
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L18:
movl %eax, %edx
imulq $274877907, %rdx, %rdx
shrq $38, %rdx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbx, %r12
je .L6
.L9:
movq %rbp, %rdi
.LEHB2:
call _ZNSt13random_device9_M_getvalEv@PLT
.LEHE2:
jmp .L18
.L6:
leaq 32(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 5032(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $5040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 5032(%rsp), %rax
subq %fs:40, %rax
je .L11
call __stack_chk_fail@PLT
.L11:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4852:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4852:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4852-.LLSDACSB4852
.LLSDACSB4852:
.uleb128 .LEHB0-.LFB4852
.uleb128 .LEHE0-.LEHB0
.uleb128 .L14-.LFB4852
.uleb128 0
.uleb128 .LEHB1-.LFB4852
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.uleb128 .LEHB2-.LFB4852
.uleb128 .LEHE2-.LEHB2
.uleb128 .L13-.LFB4852
.uleb128 0
.uleb128 .LEHB3-.LFB4852
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4852:
.text
.size _Z10randomIntsPii, .-_Z10randomIntsPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "matrix %p :\n"
.LC1:
.string "%d\t"
.LC2:
.string "%d...\n"
.LC3:
.string "...\n\n"
.text
.globl _Z11printMatrixPii
.type _Z11printMatrixPii, @function
_Z11printMatrixPii:
.LFB4853:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl %esi, %r12d
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $12, %rbp
leal (%r12,%r12), %r14d
movslq %r14d, %r14
leaq .LC1(%rip), %r13
movslq %r12d, %r12
leaq .LC2(%rip), %r15
.L21:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rbx,%r12,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rbx,%r14,4), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L21
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4853:
.size _Z11printMatrixPii, .-_Z11printMatrixPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB4882:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4882:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB4883:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4883:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1
.LC4:
.string "done in "
.LC5:
.string " \316\274s"
.text
.globl main
.type main, @function
main:
.LFB4854:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %esi
movq %rax, %rdi
call _Z10randomIntsPii
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %esi
movq %rax, %rdi
call _Z10randomIntsPii
movl $16777216, %edi
call malloc@PLT
movq %rax, %r13
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r14
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L33:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2048, %esi
movq %r12, %rdi
call _Z11printMatrixPii
movl $2048, %esi
movq %rbp, %rdi
call _Z11printMatrixPii
movl $2048, %esi
movq %r13, %rdi
call _Z11printMatrixPii
subq %r14, %rbx
movq %rbx, %rcx
movabsq $2361183241434822607, %rdx
movq %rbx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rbx
subq %rcx, %rbx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L33
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4854:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4885:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4885:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exo2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z10randomIntsPii # -- Begin function _Z10randomIntsPii
.p2align 4, 0x90
.type _Z10randomIntsPii,@function
_Z10randomIntsPii: # @_Z10randomIntsPii
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $5040, %rsp # imm = 0x13B0
.cfi_def_cfa_offset 5088
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
leaq 24(%rsp), %r14
movq %r14, 8(%rsp)
movl $1634100580, 24(%rsp) # imm = 0x61666564
movl $1953264993, 27(%rsp) # imm = 0x746C7561
movq $7, 16(%rsp)
movb $0, 31(%rsp)
.Ltmp0:
leaq 40(%rsp), %rdi
leaq 8(%rsp), %rsi
callq _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq 8(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_3
# %bb.2: # %.critedge.i.i.i
callq _ZdlPv
.LBB1_3: # %_ZNSt13random_deviceC2Ev.exit
testl %ebp, %ebp
jle .LBB1_7
# %bb.4: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %r12d, %r12d
leaq 40(%rsp), %r14
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp3:
movq %r14, %rdi
callq _ZNSt13random_device9_M_getvalEv
.Ltmp4:
# %bb.6: # %_ZNSt13random_deviceclEv.exit
# in Loop: Header=BB1_5 Depth=1
movl %eax, %ecx
imulq $274877907, %rcx, %rcx # imm = 0x10624DD3
shrq $38, %rcx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB1_5
.LBB1_7: # %._crit_edge
.Ltmp9:
leaq 40(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp10:
# %bb.8: # %_ZNSt13random_deviceD2Ev.exit
addq $5040, %rsp # imm = 0x13B0
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 5088
.Ltmp11:
movq %rax, %rdi
callq __clang_call_terminate
.LBB1_9:
.Ltmp2:
movq %rax, %rbx
movq 8(%rsp), %rdi
cmpq %r14, %rdi
je .LBB1_11
# %bb.10: # %.critedge.i.i6.i
callq _ZdlPv
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB1_14:
.Ltmp5:
movq %rax, %rbx
.Ltmp6:
leaq 40(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp7:
.LBB1_11: # %common.resume
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB1_13:
.Ltmp8:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end1:
.size _Z10randomIntsPii, .Lfunc_end1-_Z10randomIntsPii
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 1 # On action: 1
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp10 # Call between .Ltmp10 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 1 # On action: 1
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end1-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z11printMatrixPii # -- Begin function _Z11printMatrixPii
.p2align 4, 0x90
.type _Z11printMatrixPii,@function
_Z11printMatrixPii: # @_Z11printMatrixPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movslq %ebp, %r14
addl %ebp, %ebp
movslq %ebp, %rax
leaq (%rbx,%rax,4), %r15
shlq $2, %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movl $1, %r13d
movq %rbx, %rbp
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
addq %r14, %rbp
decq %r13
je .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
addq $4, %rbx
cmpq $3, %r12
jne .LBB2_1
# %bb.4:
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end2:
.size _Z11printMatrixPii, .Lfunc_end2-_Z11printMatrixPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movl $4194304, %esi # imm = 0x400000
callq _Z10randomIntsPii
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
movq %rax, %rdi
movl $4194304, %esi # imm = 0x400000
callq _Z10randomIntsPii
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 32(%rsp) # 8-byte Spill
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 7680(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 24(%rsp) # 8-byte Spill
movq (%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq %rbx, %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r13), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
addq $8192, %r13 # imm = 0x2000
cmpq $8192, %r13 # imm = 0x2000
je .LBB3_4
# %bb.5: # in Loop: Header=BB3_3 Depth=1
movl 16384(%rbx,%r12,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
addq $4, %rbp
cmpq $3, %r12
jne .LBB3_3
# %bb.6: # %_Z11printMatrixPii.exit
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movq %r14, %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # %.preheader.i21
# =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_8: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r13), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
addq $8192, %r13 # imm = 0x2000
cmpq $8192, %r13 # imm = 0x2000
je .LBB3_8
# %bb.9: # in Loop: Header=BB3_7 Depth=1
movl 16384(%r14,%r12,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
addq $4, %rbp
cmpq $3, %r12
jne .LBB3_7
# %bb.10: # %_Z11printMatrixPii.exit28
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movq %r15, %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_11: # %.preheader.i29
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_12: # Parent Loop BB3_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r13), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
addq $8192, %r13 # imm = 0x2000
cmpq $8192, %r13 # imm = 0x2000
je .LBB3_12
# %bb.13: # in Loop: Header=BB3_11 Depth=1
movl 16384(%r15,%r12,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
addq $4, %rbp
cmpq $3, %r12
jne .LBB3_11
# %bb.14: # %_Z11printMatrixPii.exit36
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rax # 8-byte Reload
subq 32(%rsp), %rax # 8-byte Folded Reload
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r12
shrq $63, %r12
sarq $7, %rdx
addq %rdx, %r12
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r12, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r12
movl $.L.str.5, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB3_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB3_17
# %bb.16:
movzbl 67(%r13), %eax
jmp .LBB3_18
.LBB3_17:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_19:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end4:
.size __clang_call_terminate, .Lfunc_end4-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "matrix %p :\n"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\t"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d...\n"
.size .L.str.2, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "done in "
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " \316\274s"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "default"
.size .L.str.6, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "...\n"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void UpdateVelocitiesKernel (double *VthetaInt, double *VradInt, double *invRmed, double *Rmed, double *Rsup, double *Rinf, double *invdiffRmed, double *invdiffRsup, double *Dens, double *invRinf, double *TAURR, double *TAURP, double *TAUPP, double DeltaT, int nrad, int nsec)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dphi, invdphi;
/* Now we can update velocities
with the viscous source term
of Navier-Stokes equation */
/* vtheta first */
if (i > 0 && i<nrad-1 && j<nsec){
dphi = 2.0*M_PI/(double)nsec;
invdphi = 1.0/dphi;
VthetaInt[i*nsec +j] += DeltaT*invRmed[i]*((Rsup[i]*TAURP[(i+1)*nsec+ j] - Rinf[i]*TAURP[i*nsec +j])*invdiffRsup[i] + \
(TAUPP[i*nsec +j] - TAUPP[i*nsec + ((j-1)+nsec)%nsec])*invdphi + 0.5*(TAURP[i*nsec + j] + TAURP[(i+1)*nsec +j]))/ \
(0.5*(Dens[i*nsec +j]+Dens[i*nsec + ((j-1)+nsec)%nsec]));
}
/* now vrad */
if (i > 0 && i<nrad && j<nsec){
dphi = 2.0*M_PI/(double)nsec;
invdphi = 1.0/dphi;
VradInt[i*nsec +j] += DeltaT*invRinf[i]*((Rmed[i]*TAURR[i*nsec +j] - Rmed[i-1]*TAURR[(i-1)*nsec + j])*invdiffRmed[i] + \
(TAURP[i*nsec + (j+1)%nsec] - TAURP[i*nsec + j])*invdphi - 0.5*(TAUPP[i*nsec +j] + TAUPP[(i-1)*nsec + j]))/ \
(0.5*(Dens[i*nsec +j] + Dens[(i-1)*nsec + j]));
}
} | .file "tmpxft_000d2c9b_00000000-6_UpdateVelocitiesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z69__device_stub__Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_diiPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.type _Z69__device_stub__Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_diiPdS_S_S_S_S_S_S_S_S_S_S_S_dii, @function
_Z69__device_stub__Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_diiPdS_S_S_S_S_S_S_S_S_S_S_S_dii:
.LFB2051:
.cfi_startproc
endbr64
subq $328, %rsp
.cfi_def_cfa_offset 336
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movsd %xmm0, (%rsp)
movq 336(%rsp), %rax
movq %rax, 56(%rsp)
movq 344(%rsp), %rax
movq %rax, 48(%rsp)
movq 352(%rsp), %rax
movq %rax, 40(%rsp)
movq 360(%rsp), %rax
movq %rax, 32(%rsp)
movq 368(%rsp), %rax
movq %rax, 24(%rsp)
movq 376(%rsp), %rax
movq %rax, 16(%rsp)
movq 384(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 32(%rsp), %rax
movq %rax, 248(%rsp)
leaq 24(%rsp), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rax
movq %rax, 264(%rsp)
leaq 8(%rsp), %rax
movq %rax, 272(%rsp)
movq %rsp, %rax
movq %rax, 280(%rsp)
leaq 392(%rsp), %rax
movq %rax, 288(%rsp)
leaq 400(%rsp), %rax
movq %rax, 296(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 344
pushq 120(%rsp)
.cfi_def_cfa_offset 352
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z69__device_stub__Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_diiPdS_S_S_S_S_S_S_S_S_S_S_S_dii, .-_Z69__device_stub__Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_diiPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.globl _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.type _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, @function
_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z69__device_stub__Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_diiPdS_S_S_S_S_S_S_S_S_S_S_S_dii
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, .-_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void UpdateVelocitiesKernel (double *VthetaInt, double *VradInt, double *invRmed, double *Rmed, double *Rsup, double *Rinf, double *invdiffRmed, double *invdiffRsup, double *Dens, double *invRinf, double *TAURR, double *TAURP, double *TAUPP, double DeltaT, int nrad, int nsec)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dphi, invdphi;
/* Now we can update velocities
with the viscous source term
of Navier-Stokes equation */
/* vtheta first */
if (i > 0 && i<nrad-1 && j<nsec){
dphi = 2.0*M_PI/(double)nsec;
invdphi = 1.0/dphi;
VthetaInt[i*nsec +j] += DeltaT*invRmed[i]*((Rsup[i]*TAURP[(i+1)*nsec+ j] - Rinf[i]*TAURP[i*nsec +j])*invdiffRsup[i] + \
(TAUPP[i*nsec +j] - TAUPP[i*nsec + ((j-1)+nsec)%nsec])*invdphi + 0.5*(TAURP[i*nsec + j] + TAURP[(i+1)*nsec +j]))/ \
(0.5*(Dens[i*nsec +j]+Dens[i*nsec + ((j-1)+nsec)%nsec]));
}
/* now vrad */
if (i > 0 && i<nrad && j<nsec){
dphi = 2.0*M_PI/(double)nsec;
invdphi = 1.0/dphi;
VradInt[i*nsec +j] += DeltaT*invRinf[i]*((Rmed[i]*TAURR[i*nsec +j] - Rmed[i-1]*TAURR[(i-1)*nsec + j])*invdiffRmed[i] + \
(TAURP[i*nsec + (j+1)%nsec] - TAURP[i*nsec + j])*invdphi - 0.5*(TAUPP[i*nsec +j] + TAUPP[(i-1)*nsec + j]))/ \
(0.5*(Dens[i*nsec +j] + Dens[(i-1)*nsec + j]));
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UpdateVelocitiesKernel (double *VthetaInt, double *VradInt, double *invRmed, double *Rmed, double *Rsup, double *Rinf, double *invdiffRmed, double *invdiffRsup, double *Dens, double *invRinf, double *TAURR, double *TAURP, double *TAUPP, double DeltaT, int nrad, int nsec)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dphi, invdphi;
/* Now we can update velocities
with the viscous source term
of Navier-Stokes equation */
/* vtheta first */
if (i > 0 && i<nrad-1 && j<nsec){
dphi = 2.0*M_PI/(double)nsec;
invdphi = 1.0/dphi;
VthetaInt[i*nsec +j] += DeltaT*invRmed[i]*((Rsup[i]*TAURP[(i+1)*nsec+ j] - Rinf[i]*TAURP[i*nsec +j])*invdiffRsup[i] + \
(TAUPP[i*nsec +j] - TAUPP[i*nsec + ((j-1)+nsec)%nsec])*invdphi + 0.5*(TAURP[i*nsec + j] + TAURP[(i+1)*nsec +j]))/ \
(0.5*(Dens[i*nsec +j]+Dens[i*nsec + ((j-1)+nsec)%nsec]));
}
/* now vrad */
if (i > 0 && i<nrad && j<nsec){
dphi = 2.0*M_PI/(double)nsec;
invdphi = 1.0/dphi;
VradInt[i*nsec +j] += DeltaT*invRinf[i]*((Rmed[i]*TAURR[i*nsec +j] - Rmed[i-1]*TAURR[(i-1)*nsec + j])*invdiffRmed[i] + \
(TAURP[i*nsec + (j+1)%nsec] - TAURP[i*nsec + j])*invdphi - 0.5*(TAUPP[i*nsec +j] + TAUPP[(i-1)*nsec + j]))/ \
(0.5*(Dens[i*nsec +j] + Dens[(i-1)*nsec + j]));
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UpdateVelocitiesKernel (double *VthetaInt, double *VradInt, double *invRmed, double *Rmed, double *Rsup, double *Rinf, double *invdiffRmed, double *invdiffRsup, double *Dens, double *invRinf, double *TAURR, double *TAURP, double *TAUPP, double DeltaT, int nrad, int nsec)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dphi, invdphi;
/* Now we can update velocities
with the viscous source term
of Navier-Stokes equation */
/* vtheta first */
if (i > 0 && i<nrad-1 && j<nsec){
dphi = 2.0*M_PI/(double)nsec;
invdphi = 1.0/dphi;
VthetaInt[i*nsec +j] += DeltaT*invRmed[i]*((Rsup[i]*TAURP[(i+1)*nsec+ j] - Rinf[i]*TAURP[i*nsec +j])*invdiffRsup[i] + \
(TAUPP[i*nsec +j] - TAUPP[i*nsec + ((j-1)+nsec)%nsec])*invdphi + 0.5*(TAURP[i*nsec + j] + TAURP[(i+1)*nsec +j]))/ \
(0.5*(Dens[i*nsec +j]+Dens[i*nsec + ((j-1)+nsec)%nsec]));
}
/* now vrad */
if (i > 0 && i<nrad && j<nsec){
dphi = 2.0*M_PI/(double)nsec;
invdphi = 1.0/dphi;
VradInt[i*nsec +j] += DeltaT*invRinf[i]*((Rmed[i]*TAURR[i*nsec +j] - Rmed[i-1]*TAURR[(i-1)*nsec + j])*invdiffRmed[i] + \
(TAURP[i*nsec + (j+1)%nsec] - TAURP[i*nsec + j])*invdphi - 0.5*(TAUPP[i*nsec +j] + TAUPP[(i-1)*nsec + j]))/ \
(0.5*(Dens[i*nsec +j] + Dens[(i-1)*nsec + j]));
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.globl _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.p2align 8
.type _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii,@function
_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x58
s_load_b32 s2, s[0:1], 0x84
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v6, 0x3ff, v0
s_load_b64 s[16:17], s[0:1], 0x40
s_waitcnt lgkmcnt(0)
v_cvt_f64_i32_e32 v[4:5], s11
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s3, v[6:7]
s_add_i32 s2, s10, -1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_mul_lo_u32 v3, v0, s11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s11, v2
v_cmp_lt_i32_e64 s3, 0, v0
s_and_b32 s12, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s12, s12, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s12
s_cbranch_execz .LBB0_2
s_mov_b32 s13, 0x401921fb
s_mov_b32 s12, 0x54442d18
s_ashr_i32 s15, s11, 31
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], s[12:13]
v_div_scale_f64 v[12:13], vcc_lo, s[12:13], v[4:5], s[12:13]
s_add_i32 s18, s11, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s15, s18, s15
v_cvt_f32_u32_e32 v1, s15
s_sub_i32 s18, 0, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rcp_iflag_f32_e32 v1, v1
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_add3_u32 v8, s11, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v8
v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_add_nc_u32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v1, v1
v_xor_b32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, s18, v1
v_mul_hi_u32 v9, v1, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v9
v_mul_hi_u32 v1, v8, v1
v_div_fixup_f64 v[6:7], v[6:7], v[4:5], s[12:13]
s_clause 0x1
s_load_b128 s[20:23], s[0:1], 0x20
s_load_b64 s[12:13], s[0:1], 0x38
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s15
v_sub_nc_u32_e32 v1, v8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, s15, v1
v_cmp_le_u32_e32 vcc_lo, s15, v1
v_cndmask_b32_e32 v1, v1, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, s15, v1
v_cmp_le_u32_e32 vcc_lo, s15, v1
v_dual_cndmask_b32 v9, v1, v8 :: v_dual_add_nc_u32 v8, v3, v2
v_div_scale_f64 v[13:14], null, v[6:7], v[6:7], 1.0
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v11, v9, v10
v_ashrrev_i32_e32 v9, 31, v8
v_add_nc_u32_e32 v27, s11, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v15, v11, v10
v_lshlrev_b64 v[9:10], 3, v[8:9]
v_lshlrev_b64 v[11:12], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v28, 31, v27
v_add_nc_u32_e32 v15, v15, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v17, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v10, vcc_lo
v_ashrrev_i32_e32 v16, 31, v15
v_add_co_u32 v19, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v20, vcc_lo, s7, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[15:16], 3, v[15:16]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v21, vcc_lo, s22, v11
v_add_co_ci_u32_e32 v22, vcc_lo, s23, v12, vcc_lo
v_lshlrev_b64 v[27:28], 3, v[27:28]
v_add_co_u32 v23, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v24, vcc_lo, s7, v16, vcc_lo
global_load_b64 v[17:18], v[17:18], off
global_load_b64 v[21:22], v[21:22], off
s_clause 0x1
global_load_b64 v[19:20], v[19:20], off
global_load_b64 v[23:24], v[23:24], off
v_add_co_u32 v29, vcc_lo, s20, v11
v_add_co_ci_u32_e32 v30, vcc_lo, s21, v12, vcc_lo
v_rcp_f64_e32 v[25:26], v[13:14]
v_add_co_u32 v27, vcc_lo, s4, v27
v_add_co_ci_u32_e32 v28, vcc_lo, s5, v28, vcc_lo
global_load_b64 v[29:30], v[29:30], off
global_load_b64 v[27:28], v[27:28], off
v_add_co_u32 v33, vcc_lo, s12, v11
v_add_co_ci_u32_e32 v34, vcc_lo, s13, v12, vcc_lo
s_load_b64 s[12:13], s[0:1], 0x10
global_load_b64 v[33:34], v[33:34], off
v_fma_f64 v[31:32], -v[13:14], v[25:26], 1.0
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[25:26], v[25:26], v[31:32], v[25:26]
v_add_co_u32 v31, vcc_lo, s16, v9
v_add_co_ci_u32_e32 v32, vcc_lo, s17, v10, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, vcc_lo, s12, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
v_add_co_u32 v15, vcc_lo, s16, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s17, v16, vcc_lo
global_load_b64 v[11:12], v[11:12], off
s_clause 0x1
global_load_b64 v[31:32], v[31:32], off
global_load_b64 v[15:16], v[15:16], off
v_div_scale_f64 v[37:38], vcc_lo, 1.0, v[6:7], 1.0
s_load_b64 s[12:13], s[0:1], 0x0
v_fma_f64 v[35:36], -v[13:14], v[25:26], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[25:26], v[25:26], v[35:36], v[25:26]
v_mul_f64 v[35:36], v[37:38], v[25:26]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], -v[13:14], v[35:36], v[37:38]
v_div_fmas_f64 v[13:14], v[13:14], v[25:26], v[35:36]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s12, v9
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f64 v[6:7], v[13:14], v[6:7], 1.0
s_waitcnt vmcnt(8)
v_mul_f64 v[21:22], v[21:22], v[17:18]
s_waitcnt vmcnt(6)
v_add_f64 v[19:20], v[19:20], -v[23:24]
s_waitcnt vmcnt(4)
v_add_f64 v[17:18], v[27:28], v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[13:14], v[29:30], v[27:28], -v[21:22]
v_mul_f64 v[6:7], v[6:7], v[19:20]
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[6:7], v[33:34], v[13:14], v[6:7]
s_waitcnt vmcnt(2)
v_mul_f64 v[11:12], v[11:12], s[8:9]
s_waitcnt vmcnt(0)
v_add_f64 v[13:14], v[31:32], v[15:16]
v_fma_f64 v[6:7], v[17:18], 0.5, v[6:7]
global_load_b64 v[17:18], v[8:9], off
v_mul_f64 v[13:14], v[13:14], 0.5
v_mul_f64 v[6:7], v[11:12], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[11:12], null, v[13:14], v[13:14], v[6:7]
v_rcp_f64_e32 v[15:16], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[19:20], -v[11:12], v[15:16], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
v_fma_f64 v[19:20], -v[11:12], v[15:16], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
v_div_scale_f64 v[19:20], vcc_lo, v[6:7], v[13:14], v[6:7]
v_mul_f64 v[21:22], v[19:20], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[11:12], v[21:22], v[19:20]
v_div_fmas_f64 v[10:11], v[10:11], v[15:16], v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[6:7], v[10:11], v[13:14], v[6:7]
s_waitcnt vmcnt(0)
v_add_f64 v[6:7], v[17:18], v[6:7]
global_store_b64 v[8:9], v[6:7], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s14
v_cmp_gt_i32_e32 vcc_lo, s10, v0
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_mov_b32 s3, 0x401921fb
s_mov_b32 s2, 0x54442d18
s_ashr_i32 s10, s11, 31
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], s[2:3]
v_div_scale_f64 v[12:13], vcc_lo, s[2:3], v[4:5], s[2:3]
s_add_i32 s12, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s10, s12, s10
v_cvt_f32_u32_e32 v1, s10
s_sub_i32 s12, 0, s10
s_delay_alu instid0(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
v_add_nc_u32_e32 v12, 1, v2
v_cvt_u32_f32_e32 v1, v1
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_mul_lo_u32 v8, s12, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v12, v13
s_load_b128 s[12:15], s[0:1], 0x48
v_xor_b32_e32 v9, v9, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v8, v1, v8
v_add_nc_u32_e32 v1, v1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v9, v1
v_mul_lo_u32 v1, v1, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v9, v1
v_div_fixup_f64 v[4:5], v[6:7], v[4:5], s[2:3]
s_load_b64 s[2:3], s[0:1], 0x18
v_subrev_nc_u32_e32 v6, s10, v1
v_cmp_le_u32_e32 vcc_lo, s10, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v8, v1, v6 :: v_dual_mov_b32 v1, 0
v_subrev_nc_u32_e32 v9, s10, v8
v_cmp_le_u32_e32 vcc_lo, s10, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 3, v[0:1]
v_dual_cndmask_b32 v9, v8, v9 :: v_dual_add_nc_u32 v0, -1, v0
v_add_nc_u32_e32 v8, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[10:11], null, v0, s11, v[2:3]
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_xor_b32_e32 v2, v9, v13
s_delay_alu instid0(VALU_DEP_4)
v_ashrrev_i32_e32 v9, 31, v8
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x30
s_load_b64 s[0:1], s[0:1], 0x8
v_sub_nc_u32_e32 v2, v2, v13
v_ashrrev_i32_e32 v11, 31, v10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_nc_u32_e32 v2, v2, v3
v_div_scale_f64 v[12:13], null, v[4:5], v[4:5], 1.0
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_lshlrev_b64 v[8:9], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v14, vcc_lo, s14, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_add_co_ci_u32_e32 v15, vcc_lo, s15, v11, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v16, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v9, vcc_lo
global_load_b64 v[0:1], v[0:1], off
global_load_b64 v[14:15], v[14:15], off
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[16:17], v[16:17], off
v_add_co_u32 v20, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v22, vcc_lo, s14, v8
v_add_co_ci_u32_e32 v23, vcc_lo, s15, v9, vcc_lo
global_load_b64 v[20:21], v[20:21], off
global_load_b64 v[22:23], v[22:23], off
v_add_co_u32 v26, vcc_lo, s6, v8
v_rcp_f64_e32 v[18:19], v[12:13]
v_add_co_ci_u32_e32 v27, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v28, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v29, vcc_lo, s7, v11, vcc_lo
v_add_co_u32 v30, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v31, vcc_lo, s11, v7, vcc_lo
s_clause 0x1
global_load_b64 v[26:27], v[26:27], off
global_load_b64 v[28:29], v[28:29], off
global_load_b64 v[30:31], v[30:31], off
v_fma_f64 v[24:25], -v[12:13], v[18:19], 1.0
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[18:19], v[18:19], v[24:25], v[18:19]
v_add_co_u32 v24, vcc_lo, s16, v8
v_add_co_ci_u32_e32 v25, vcc_lo, s17, v9, vcc_lo
v_add_co_u32 v6, vcc_lo, s12, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v7, vcc_lo
v_add_co_u32 v10, vcc_lo, s16, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s17, v11, vcc_lo
global_load_b64 v[6:7], v[6:7], off
s_clause 0x1
global_load_b64 v[24:25], v[24:25], off
global_load_b64 v[10:11], v[10:11], off
v_div_scale_f64 v[34:35], vcc_lo, 1.0, v[4:5], 1.0
v_fma_f64 v[32:33], -v[12:13], v[18:19], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[18:19], v[18:19], v[32:33], v[18:19]
v_mul_f64 v[32:33], v[34:35], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[12:13], v[32:33], v[34:35]
v_div_fmas_f64 v[12:13], v[12:13], v[18:19], v[32:33]
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
s_waitcnt vmcnt(10)
v_mul_f64 v[0:1], v[0:1], v[14:15]
s_waitcnt vmcnt(8)
v_add_f64 v[2:3], v[2:3], -v[16:17]
v_div_fixup_f64 v[4:5], v[12:13], v[4:5], 1.0
s_waitcnt vmcnt(6)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[0:1], v[20:21], v[22:23], -v[0:1]
v_mul_f64 v[2:3], v[4:5], v[2:3]
s_waitcnt vmcnt(4)
v_add_f64 v[4:5], v[26:27], v[28:29]
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[0:1], v[30:31], v[0:1], v[2:3]
s_waitcnt vmcnt(2)
v_mul_f64 v[2:3], v[6:7], s[8:9]
s_waitcnt vmcnt(0)
v_add_f64 v[6:7], v[24:25], v[10:11]
global_load_b64 v[10:11], v[8:9], off
v_fma_f64 v[0:1], v[4:5], -0.5, v[0:1]
v_mul_f64 v[4:5], v[6:7], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[2:3], v[0:1]
v_div_scale_f64 v[2:3], null, v[4:5], v[4:5], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[2:3], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[2:3], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7]
v_div_scale_f64 v[12:13], vcc_lo, v[0:1], v[4:5], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[14:15], v[12:13], v[6:7]
v_fma_f64 v[2:3], -v[2:3], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[14:15]
v_div_fixup_f64 v[0:1], v[2:3], v[4:5], v[0:1]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[0:1], v[10:11], v[0:1]
global_store_b64 v[8:9], v[0:1], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 376
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 39
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, .Lfunc_end0-_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .offset: 104
.size: 8
.value_kind: by_value
- .offset: 112
.size: 4
.value_kind: by_value
- .offset: 116
.size: 4
.value_kind: by_value
- .offset: 120
.size: 4
.value_kind: hidden_block_count_x
- .offset: 124
.size: 4
.value_kind: hidden_block_count_y
- .offset: 128
.size: 4
.value_kind: hidden_block_count_z
- .offset: 132
.size: 2
.value_kind: hidden_group_size_x
- .offset: 134
.size: 2
.value_kind: hidden_group_size_y
- .offset: 136
.size: 2
.value_kind: hidden_group_size_z
- .offset: 138
.size: 2
.value_kind: hidden_remainder_x
- .offset: 140
.size: 2
.value_kind: hidden_remainder_y
- .offset: 142
.size: 2
.value_kind: hidden_remainder_z
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 168
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 176
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 184
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 376
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 39
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UpdateVelocitiesKernel (double *VthetaInt, double *VradInt, double *invRmed, double *Rmed, double *Rsup, double *Rinf, double *invdiffRmed, double *invdiffRsup, double *Dens, double *invRinf, double *TAURR, double *TAURP, double *TAUPP, double DeltaT, int nrad, int nsec)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
double dphi, invdphi;
/* Now we can update velocities
with the viscous source term
of Navier-Stokes equation */
/* vtheta first */
if (i > 0 && i<nrad-1 && j<nsec){
dphi = 2.0*M_PI/(double)nsec;
invdphi = 1.0/dphi;
VthetaInt[i*nsec +j] += DeltaT*invRmed[i]*((Rsup[i]*TAURP[(i+1)*nsec+ j] - Rinf[i]*TAURP[i*nsec +j])*invdiffRsup[i] + \
(TAUPP[i*nsec +j] - TAUPP[i*nsec + ((j-1)+nsec)%nsec])*invdphi + 0.5*(TAURP[i*nsec + j] + TAURP[(i+1)*nsec +j]))/ \
(0.5*(Dens[i*nsec +j]+Dens[i*nsec + ((j-1)+nsec)%nsec]));
}
/* now vrad */
if (i > 0 && i<nrad && j<nsec){
dphi = 2.0*M_PI/(double)nsec;
invdphi = 1.0/dphi;
VradInt[i*nsec +j] += DeltaT*invRinf[i]*((Rmed[i]*TAURR[i*nsec +j] - Rmed[i-1]*TAURR[(i-1)*nsec + j])*invdiffRmed[i] + \
(TAURP[i*nsec + (j+1)%nsec] - TAURP[i*nsec + j])*invdphi - 0.5*(TAUPP[i*nsec +j] + TAUPP[(i-1)*nsec + j]))/ \
(0.5*(Dens[i*nsec +j] + Dens[(i-1)*nsec + j]));
}
} | .text
.file "UpdateVelocitiesKernel.hip"
.globl _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii # -- Begin function _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.p2align 4, 0x90
.type _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii,@function
_Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii: # @_Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 56(%rsp), %rax
movq %rax, 216(%rsp)
leaq 312(%rsp), %rax
movq %rax, 224(%rsp)
leaq 320(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, .Lfunc_end0-_Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii,@object # @_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.section .rodata,"a",@progbits
.globl _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.p2align 3, 0x0
_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii:
.quad _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.size _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii"
.size .L__unnamed_1, 56
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d2c9b_00000000-6_UpdateVelocitiesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z69__device_stub__Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_diiPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.type _Z69__device_stub__Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_diiPdS_S_S_S_S_S_S_S_S_S_S_S_dii, @function
_Z69__device_stub__Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_diiPdS_S_S_S_S_S_S_S_S_S_S_S_dii:
.LFB2051:
.cfi_startproc
endbr64
subq $328, %rsp
.cfi_def_cfa_offset 336
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movsd %xmm0, (%rsp)
movq 336(%rsp), %rax
movq %rax, 56(%rsp)
movq 344(%rsp), %rax
movq %rax, 48(%rsp)
movq 352(%rsp), %rax
movq %rax, 40(%rsp)
movq 360(%rsp), %rax
movq %rax, 32(%rsp)
movq 368(%rsp), %rax
movq %rax, 24(%rsp)
movq 376(%rsp), %rax
movq %rax, 16(%rsp)
movq 384(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 32(%rsp), %rax
movq %rax, 248(%rsp)
leaq 24(%rsp), %rax
movq %rax, 256(%rsp)
leaq 16(%rsp), %rax
movq %rax, 264(%rsp)
leaq 8(%rsp), %rax
movq %rax, 272(%rsp)
movq %rsp, %rax
movq %rax, 280(%rsp)
leaq 392(%rsp), %rax
movq %rax, 288(%rsp)
leaq 400(%rsp), %rax
movq %rax, 296(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 344
pushq 120(%rsp)
.cfi_def_cfa_offset 352
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z69__device_stub__Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_diiPdS_S_S_S_S_S_S_S_S_S_S_S_dii, .-_Z69__device_stub__Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_diiPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.globl _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.type _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, @function
_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z69__device_stub__Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_diiPdS_S_S_S_S_S_S_S_S_S_S_S_dii
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, .-_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "UpdateVelocitiesKernel.hip"
.globl _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii # -- Begin function _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.p2align 4, 0x90
.type _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii,@function
_Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii: # @_Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movsd %xmm0, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 56(%rsp), %rax
movq %rax, 216(%rsp)
leaq 312(%rsp), %rax
movq %rax, 224(%rsp)
leaq 320(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, .Lfunc_end0-_Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii,@object # @_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.section .rodata,"a",@progbits
.globl _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.p2align 3, 0x0
_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii:
.quad _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.size _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii"
.size .L__unnamed_1, 56
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22UpdateVelocitiesKernelPdS_S_S_S_S_S_S_S_S_S_S_S_dii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ int addem( int a, int b ) {
return a + b;
}
__global__ void add( int a, int b, int *c ) {
*c = addem( a, b );
} | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ int addem( int a, int b ) {
return a + b;
}
__global__ void add( int a, int b, int *c ) {
*c = addem( a, b );
} | .file "tmpxft_000b9381_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5addemii
.type _Z5addemii, @function
_Z5addemii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z5addemii, .-_Z5addemii
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ int addem( int a, int b ) {
return a + b;
}
__global__ void add( int a, int b, int *c ) {
*c = addem( a, b );
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int addem( int a, int b ) {
return a + b;
}
__global__ void add( int a, int b, int *c ) {
*c = addem( a, b );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int addem( int a, int b ) {
return a + b;
}
__global__ void add( int a, int b, int *c ) {
*c = addem( a, b );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int addem( int a, int b ) {
return a + b;
}
__global__ void add( int a, int b, int *c ) {
*c = addem( a, b );
} | .text
.file "add.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b9381_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5addemii
.type _Z5addemii, @function
_Z5addemii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z5addemii, .-_Z5addemii
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cassert>
#include <stdio.h>
#include <cuda_runtime.h>
#include <math.h>
#include <float.h>
#include "raytraceCuda.cuh"
// flags as to whether or not reflection and refraction are included in the
// raytracing
#define REFLECTION 1
#define REFRACTION 1
#define SINGLETHREADMODE 0
#define RECURSIONDEPTH 3
#define gpuErrChk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code,
const char *file,
int line,
bool abort=true) {
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s %s %d\n",
cudaGetErrorString(code), file, line);
exit(code);
}
}
struct Point_Light
{
double position[3]; //3-vector
double color[3]; //3-vector
double attenuation_k;
};
struct Material
{
double diffuse[3]; //3-vector
double ambient[3]; //3-vector
double specular[3]; //3-vector
double shine;
double snell;
double opacity;
double reflectivity;
};
struct Object
{
double e;
double n;
Material mat;
double scale[9]; //3x3-matrix
double unScale[9]; //3x3-matrix
double rotate[9]; //3x3-matrix
double unRotate[9]; //3x3-matrix
double translate[3]; //3-vector
double unTranslate[3]; //3-vector
};
/********** Helper Functions **************************************************/
/* Stores the component-wise product of a and b into c. */
__device__
void cProduct(double *a, double *b, double *c)
{
c[0] = a[0] * b[0];
c[1] = a[1] * b[1];
c[2] = a[2] * b[2];
}
/* Stores the component-wise minimum of a and b into out. */
__device__
void cWiseMin(double *a, double *b, double *out)
{
out[0] = min(a[0], b[0]);
out[1] = min(a[1], b[1]);
out[2] = min(a[2], b[2]);
}
/* Returns -1 for negative numbers, 1 for positive numbers, and 0 for zero. */
__device__
int sign(double s)
{
if(s > 0) return 1;
if(s < 0) return -1;
return 0;
}
/* Returns the norm of the given vector. */
__device__
double d_norm(double *vec)
{
return sqrt((vec[0] * vec[0]) + (vec[1] * vec[1]) + (vec[2] * vec[2]));
}
/* Normalizes the given vector. */
__device__
void d_normalize(double *vec)
{
double n = d_norm(vec);
vec[0] = vec[0] / (double) n;
vec[1] = vec[1] / (double) n;
vec[2] = vec[2] / (double) n;
}
/* Returns the dot product of the given vectors. */
__device__
double d_dot(double *a, double *b)
{
return (a[0] * b[0]) + (a[1] * b[1]) + (a[2] * b[2]);
}
/* Implicit Superquadric function. */
// vec is a 3-vector
__device__
double isq(double *vec, double *e, double *n)
{
// Test for n = 0 now to prevent divide-by-zero errors.
if (n == 0)
return FLT_MAX;
double zTerm = pow(pow(vec[2], 2.0), 1.0 / (double) *n);
// Test for e = 0 now to prevent divide-by-zero errors.
if (e == 0)
return zTerm;
double xTerm = pow(pow(vec[0], 2.0), 1.0 / (double) *e);
double yTerm = pow(pow(vec[1], 2.0), 1.0 / (double) *e);
double xyTerm = pow(xTerm + yTerm, *e / (double) *n);
return xyTerm + zTerm - 1.0;
}
/* Ray Equation */
// a and b are both 3-vectors
__device__
void findRay(double *a, double *b, double *c, double t)
{
c[0] = (a[0] * t) + b[0];
c[1] = (a[1] * t) + b[1];
c[2] = (a[2] * t) + b[2];
}
/* Apply the Inverse Transform to a to get a new, usable a. */
// unScale and unRotate are 3x3 matrices. a and newA are 3-vectors
__device__
void newa(double *unScale, double *unRotate, double *a, double *newA)
{
double a0 = (unRotate[0] * a[0]) + (unRotate[1] * a[1]) + (unRotate[2] * a[2]);
double a1 = (unRotate[3] * a[0]) + (unRotate[4] * a[1]) + (unRotate[5] * a[2]);
double a2 = (unRotate[6] * a[0]) + (unRotate[7] * a[1]) + (unRotate[8] * a[2]);
newA[0] = (unScale[0] * a0) + (unScale[1] * a1) + (unScale[2] * a2);
newA[1] = (unScale[3] * a0) + (unScale[4] * a1) + (unScale[5] * a2);
newA[2] = (unScale[6] * a0) + (unScale[7] * a1) + (unScale[8] * a2);
}
/* Apply the Inverse Transform to b to get a new, usable b. */
// unScale and unRotate are 3x3 matrices. unTranslate, b, and newB are 3-vectors
__device__
void newb(double *unScale, double *unRotate, double *unTranslate, double *b,
double *newB)
{
// b + unTranslate
double b0 = b[0] + unTranslate[0];
double b1 = b[1] + unTranslate[1];
double b2 = b[2] + unTranslate[2];
// unRotate * (b + unTranslate)
newB[0] = (unRotate[0] * b0) + (unRotate[1] * b1) + (unRotate[2] * b2);
newB[1] = (unRotate[3] * b0) + (unRotate[4] * b1) + (unRotate[5] * b2);
newB[2] = (unRotate[6] * b0) + (unRotate[7] * b1) + (unRotate[8] * b2);
b0 = newB[0];
b1 = newB[1];
b2 = newB[2];
// unScale * (unRotate * (b + unTranslate))
newB[0] = (unScale[0] * b0) + (unScale[1] * b1) + (unScale[2] * b2);
newB[1] = (unScale[3] * b0) + (unScale[4] * b1) + (unScale[5] * b2);
newB[2] = (unScale[6] * b0) + (unScale[7] * b1) + (unScale[8] * b2);
}
/* Finds the scalar coefficients of the quadratic equation with the two given
* vectors. If positiveb is true then the returned coeffs will all be multiplied
* by -1 if b is negative, to ensure that b is positive. */
// a, b, and c are 3-vectors
__device__
void findCoeffs(double *a, double *b, double *c, bool positiveb)
{
c[0] = d_dot(a, a);
c[1] = 2 * d_dot(a, b);
c[2] = d_dot(b, b) - 3;
if (positiveb && c[1] < 0){
c[0] *= -1;
c[1] *= -1;
c[2] *= -1;
}
}
/* Finds the roots of the quadratic with the coefficients specified by the input
* Vector3d. If one of the roots is complex then FLT_MAX is returned instead. */
// coeffs is a 3-vector, roots is a 2-vector
__device__
void findRoots(double *coeffs, double *roots)
{
double interior = pow(coeffs[1], 2) - (4 * coeffs[0] * coeffs[2]);
if (interior < 0)
{
roots[0] = FLT_MAX;
roots[1] = FLT_MAX;
}
else
{
roots[0] = (-coeffs[1] - sqrt(interior)) / (double) (2 * coeffs[0]);
roots[1] = (2 * coeffs[2]) / (double) (-coeffs[1] - sqrt(interior));
}
}
/* Gradient of the isq function. */
// vec and grad are 3-vectors
__device__
void isqGradient(double *vec, double *grad, double e, double n)
{
double xval = 0.0, yval = 0.0, zval = 0.0;
// Check for n = 0 to prevent divide-by-zero errors
if (n == 0)
{
xval = yval = zval = FLT_MAX;
}
// Check for e = 0 to prevent divide-by-zero errors
else if (e == 0)
{
xval = yval = FLT_MAX;
zval = (2 * vec[2] * pow(pow(vec[2], 2), ((double) 1 / n) - 1)) / (double) n;
}
else
{
double xterm = pow(pow(vec[0], 2.0), (double) 1 / e);
double yterm = pow(pow(vec[1], 2.0), (double) 1 / e);
double xyterm = pow(xterm + yterm, ((double) e / n) - 1);
double x2term = (2 * vec[0] * pow(pow(vec[0], 2.0), ((double) 1 / e) - 1));
double y2term = (2 * vec[1] * pow(pow(vec[1], 2.0), ((double) 1 / e) - 1));
xval = x2term * xyterm / (double) n;
yval = y2term * xyterm / (double) n;
zval = (2 * vec[2] * pow(pow(vec[2], 2.0), ((double) 1 / n) - 1)) / (double) n;
}
grad[0] = xval;
grad[1] = yval;
grad[2] = zval;
}
/* Derivative of the isq function. */
// vec and a are 3-vectors
__device__
double gPrime(double *vec, double *a, double e, double n)
{
double tmp[3];
isqGradient(vec, &tmp[0], e, n);
double val = d_dot(a, &tmp[0]);
return val;
}
/* Uses Newton's method to find the t value at which a ray hits the superquadric.
* If the ray actually misses the superquadric then FLT_MAX is returned instead.*/
// a and b are 3-vectors
__device__
double updateRule(double *a, double *b, double *e, double *n, double t, double epsilon)
{
double vec[3];
findRay(a, b, &vec[0], t);
double gP = gPrime(&vec[0], a, *e, *n);
double gPPrevious = gP;
double g = 0.0;
double tnew = t, told = t;
bool stopPoint = false;
while (!stopPoint)
{
told = tnew;
findRay(a, b, &vec[0], told);
gP = gPrime(&vec[0], a, *e, *n);
g = isq(&vec[0], e, n);
if ((g - epsilon) <= 0)
{
stopPoint = true;
}
else if (sign(gP) != sign(gPPrevious) || gP == 0)
{
stopPoint = true;
tnew = FLT_MAX;
}
else
{
tnew = told - (g / gP);
gPPrevious = gP;
}
}
return tnew;
}
/* Unit normal vector at a point on the superquadric */
// r is a 3x3 matrix
// vec1, vec2, and un are 3-vectors
__device__
void unitNormal(double *r, double *vec1, double *vec2, double *un, double tt, double e, double n)
{
findRay(vec1, vec2, un, tt);
isqGradient(un, un, e, n);
double un0 = un[0];
double un1 = un[1];
double un2 = un[2];
un[0] = (r[0] * un0) + (r[1] * un1) + (r[2] * un2);
un[1] = (r[3] * un0) + (r[4] * un1) + (r[5] * un2);
un[2] = (r[6] * un0) + (r[7] * un1) + (r[8] * un2);
d_normalize(un);
}
// Returns the angle between two vectors.
// Both a and b are 3-vectors.
__device__
double vectorAngle(double *a, double *b)
{
double d = d_dot(a, b);
double mag = d_norm(a) * d_norm(b);
return acos(d / (double) mag);
}
// Calculates the refracted ray from an input ray and normal and a snell ratio
// If there is total internal reflection, then a vector of FLT_MAX is returned
// instead.
// a, n, and ref are 3-vectors
__device__
void refractedRay(double *a, double *n, double *ref, double snell)
{
double tmp = d_dot(n, a);
n[0] *= -1;
n[1] *= -1;
n[2] *= -1;
double cos1 = d_dot(n, a);
if (cos1 < 0)
{
cos1 = tmp;
}
else {
n[0] *= -1;
n[1] *= -1;
n[2] *= -1;
}
double radicand = 1 - (pow(snell, 2) * (1 - pow(cos1,2)));
if (radicand < 0)
{
ref[0] = FLT_MAX;
ref[1] = FLT_MAX;
ref[2] = FLT_MAX;
}
else
{
double cos2 = sqrt(radicand);
ref[0] = (snell * a[0]) + (((snell * cos1) - cos2) * n[0]);
ref[1] = (snell * a[1]) + (((snell * cos1) - cos2) * n[1]);
ref[2] = (snell * a[2]) + (((snell * cos1) - cos2) * n[2]);
}
}
/* debugging purposes */
__device__
void print_objects(Object *p_objects, int numObjects)
{
for (int i = 0; i < numObjects; i++) {
Object *o = &p_objects[i];
printf("\nObject %d\n", i);
printf("e: %f\t n: %f\n", o->e, o->n);
printf("scale: [%f, %f, %f] unScale: [%f, %f, %f]\n", o->scale[0],
o->scale[1], o->scale[2], o->unScale[0], o->unScale[1], o->unScale[2]);
printf(" [%f, %f, %f] [%f, %f, %f]\n", o->scale[3],
o->scale[4], o->scale[5], o->unScale[3], o->unScale[4], o->unScale[5]);
printf(" [%f, %f, %f] [%f, %f, %f]\n", o->scale[6],
o->scale[7], o->scale[8], o->unScale[6], o->unScale[7], o->unScale[8]);
printf("rotate: [%f, %f, %f] unRotate: [%f, %f, %f]\n", o->rotate[0],
o->rotate[1], o->rotate[2], o->unRotate[0], o->unRotate[1], o->unRotate[2]);
printf(" [%f, %f, %f] [%f, %f, %f]\n", o->rotate[3],
o->rotate[4], o->rotate[5], o->unRotate[3], o->unRotate[4], o->unRotate[5]);
printf(" [%f, %f, %f] [%f, %f, %f]\n", o->rotate[6],
o->rotate[7], o->rotate[8], o->unRotate[6], o->unRotate[7], o->unRotate[8]);
printf("translate: (%f, %f, %f) unTranslate: (%f, %f, %f)\n",
o->translate[0], o->translate[1], o->translate[2], o->unTranslate[0],
o->unTranslate[1], o->unTranslate[2]);
printf("Material-\n");
printf("Diffuse: (%f, %f, %f)\n", o->mat.diffuse[0], o->mat.diffuse[1],
o->mat.diffuse[2]);
printf("Ambient: (%f, %f, %f)\n", o->mat.ambient[0], o->mat.ambient[1],
o->mat.ambient[2]);
printf("Specular: (%f, %f, %f)\n", o->mat.specular[0], o->mat.specular[1],
o->mat.specular[2]);
printf("shine: %f\t snell: %f\t opacity: %f\n", o->mat.shine, o->mat.snell, o->mat.opacity);
}
}
__device__
void print_lights(Point_Light *p_lights, int numLights)
{
for (int i = 0; i < numLights; i++) {
Point_Light *l = &p_lights[i];
printf("\nLight %d\n", i);
printf("Position: (%f, %f, %f)\n", l->position[0], l->position[1], l->position[2]);
printf("Color: (%f, %f, %f)\n", l->color[0], l->color[1], l->color[2]);
printf("Attenuation Factor: %f\n", l->attenuation_k);
}
}
/********** Actual Raytracing Functions ***************************************/
__device__
// n is the normal. e is the eye. ind is the index of the object we're lighting.
void lighting(double *point, double *n, double *e, Material *mat,
Point_Light *l, int numLights,
Object *objects, int numObjects,
double epsilon, int ind, int generation, double *res,
double *lightDoubles)
{
double diffuseSum[3] = {0.0, 0.0, 0.0};
double specularSum[3] = {0.0, 0.0, 0.0};
double refractedLight[3] = {0.0, 0.0, 0.0};
double reflectedLight[3] = {0.0, 0.0, 0.0};
double* dif = &mat->diffuse[0];
double* spec = &mat->specular[0];
double shine = mat->shine;
double *newA = &lightDoubles[0];
double *newB = &lightDoubles[3];
double *coeffs = &lightDoubles[6];
double *roots = &lightDoubles[30];
// Get the unit direction from the point to the camera
double eDirection[3];
for (int i = 0; i < 3; i++)
eDirection[i] = e[i] - point[i];
d_normalize(&eDirection[0]);
for (int i = 0; i < numLights && generation > 0; i++)
{
// Retrieve the light's postion, color, and attenuation factor
double attenuation = l[i].attenuation_k;
// Get the unit direction and the distance between the light and the
// point
double lDirection[3];
lDirection[0] = l[i].position[0] - point[0];
lDirection[1] = l[i].position[1] - point[1];
lDirection[2] = l[i].position[2] - point[2];
double lightDist = d_norm(&lDirection[0]);
d_normalize(&lDirection[0]);
// Check to see that the light isn't blocked before considering it
// further.
// The i > 0 condition is present to prevent the program from blocking
// anything from the eyelight, for the obvious reason that anything we
// can see will be illuminated by the eyelight.
bool useLight = true;
for (int k = 0; k < numObjects && useLight && i > 0; k++)
{
if (k != ind)
{
// Find the ray equation transformations
newa(&objects[k].unScale[0], &objects[k].unRotate[0],
&lDirection[0], &newA[0]);
newb(&objects[k].unScale[0], &objects[k].unRotate[0],
&objects[k].unTranslate[0], point, &newB[0]);
// Find the quadratic equation coefficients
findCoeffs(&newA[0], &newB[0], &coeffs[0], true);
// Using the coefficients, find the roots
findRoots(&coeffs[0], &roots[0]);
// Check to see if the roots are FLT_MAX - if they are then the
// ray missed the superquadric. If they haven't missed then we
// can continue with the calculations.
if (roots[0] != FLT_MAX)
{
// Use the update rule to find tfinal
double tini = min(roots[0], roots[1]);
double tfinal = updateRule(&newA[0], &newB[0], &objects[k].e,
&objects[k].n, tini, epsilon);
/* Check to see if tfinal is FLT_MAX - if it is then the ray
* missed the superquadric. Additionally, if tfinal is
* negative then either the ray has started inside the
* object or is pointing away from the object; in both cases
* the ray has "missed". Also check to see if the object is
* farther away than the light - if it is then it isn't
* actually blocking the light. */
double ray[3];
findRay(&lDirection[0], point, &ray[0], tfinal);
double objDist = d_norm(&ray[0]);
if (tfinal != FLT_MAX && tfinal >= 0 && objDist < lightDist)
useLight = false;
}
}
}
if (useLight)
{
// Find tthe attenuation term
double atten = 1 / (double) (1 + (attenuation * pow(lightDist, 2)));
// Add the attenuation factor to the light's color
// Add the diffuse factor to the diffuse sum
double nDotl = d_dot(n, &lDirection[0]);
//Vector3d lDiffuse = lC * atten * ((0 < nDotl) ? nDotl : 0);
//diffuseSum = diffuseSum + lDiffuse;
if (0 < nDotl) {
diffuseSum[0] += l[i].color[0] * atten * nDotl;
diffuseSum[1] += l[i].color[1] * atten * nDotl;
diffuseSum[2] += l[i].color[2] * atten * nDotl;
}
// Add the specular factor to the specular sum
double dirDif[3];
dirDif[0] = eDirection[0] + lDirection[0];
dirDif[1] = eDirection[1] + lDirection[1];
dirDif[2] = eDirection[2] + lDirection[2];
d_normalize(&dirDif[0]);
double nDotDir = d_dot(n, &dirDif[0]);
//Vector3d lSpecular = lC * atten *
// pow(((0 < nDotDir && 0 < nDotl) ? nDotDir : 0), shine);
//specularSum = specularSum + lSpecular;
if (0 < nDotDir && 0 < nDotl) {
specularSum[0] += l[i].color[0] * atten * pow(nDotDir, shine);
specularSum[1] += l[i].color[1] * atten * pow(nDotDir, shine);
specularSum[2] += l[i].color[2] * atten * pow(nDotDir, shine);
}
}
}
/* Find the light contribution from reflection */
// Find the reflected ray
#if REFLECTION
double ttrueFinal = 0.0;
int finalObj = 0;
bool hitObject = false;
double *finalNewA = &lightDoubles[12];
double *finalNewB = &lightDoubles[15];
// If the object's reflectivity is 0 then just don't bother
if (objects[ind].mat.reflectivity != 0) {
double eDotN = d_dot(n, &eDirection[0]);
double *reflected = &lightDoubles[9];
reflected[0] = (2 * n[0] * eDotN) - eDirection[0];
reflected[1] = (2 * n[1] * eDotN) - eDirection[1];
reflected[2] = (2 * n[2] * eDotN) - eDirection[2];
d_normalize(&reflected[0]);
for (int k = 0; k < numObjects && generation > 0 ; k++)
{
if (k != ind)
{
// Find the ray equation transformations
newa(objects[k].unScale, objects[k].unRotate, &reflected[0],
&newA[0]);
newb(objects[k].unScale, objects[k].unRotate,
objects[k].unTranslate, point, &newB[0]);
// Find the quadratic equation coefficients
findCoeffs(&newA[0], &newB[0], &coeffs[0], true);
// Using the coefficients, find the roots
findRoots(&coeffs[0], &roots[0]);
// Check to see if the roots are FLT_MAX - if they are then the
// ray missed the superquadric. If they haven't missed then we
// can continue with the calculations.
if (roots[0] != FLT_MAX)
{
// Use the update rule to find tfinal
double tini = min(roots[0], roots[1]);
double tfinal = updateRule(&newA[0], &newB[0], &objects[k].e,
&objects[k].n, tini, epsilon);
/* Check to see if tfinal is FLT_MAX - if it is then the ray
* missed the superquadric. Additionally, if tfinal is negative
* then either the ray has started inside the object or is
* pointing away from the object; in both cases the ray has
* "missed". */
if (tfinal != FLT_MAX && tfinal >= 0)
{
if(hitObject && tfinal < ttrueFinal)
{
ttrueFinal = tfinal;
finalObj = k;
finalNewA[0] = newA[0];
finalNewA[1] = newA[1];
finalNewA[2] = newA[2];
finalNewB[0] = newB[0];
finalNewB[1] = newB[1];
finalNewB[2] = newB[2];
}
else if (!hitObject)
{
hitObject = true;
ttrueFinal = tfinal;
finalObj = k;
finalNewA[0] = newA[0];
finalNewA[1] = newA[1];
finalNewA[2] = newA[2];
finalNewB[0] = newB[0];
finalNewB[1] = newB[1];
finalNewB[2] = newB[2];
}
}
}
}
}
if (hitObject)
{
double intersectR[3];
double intersectRNormal[3];
findRay(&reflected[0], point, &intersectR[0], ttrueFinal);
unitNormal(objects[finalObj].rotate, &finalNewA[0], &finalNewB[0],
&intersectRNormal[0], ttrueFinal, objects[finalObj].e,
objects[finalObj].n);
lighting(&intersectR[0], &intersectRNormal[0], e,
&objects[finalObj].mat,
l, numLights, objects, numObjects, epsilon,
finalObj, generation-1, &reflectedLight[0], lightDoubles);
// Multiply by the object's reflectivity
reflectedLight[0] *= objects[ind].mat.reflectivity;
reflectedLight[1] *= objects[ind].mat.reflectivity;
reflectedLight[2] *= objects[ind].mat.reflectivity;
}
}
#endif
#if REFRACTION
/* Find the refraction contribution. */
// If the object's opacity is zero then just don't bother
if (objects[ind].mat.opacity != 0) {
// Change the eye-direction vector so that it points at the surface instead
// of at the eye
eDirection[0] *= -1;
eDirection[1] *= -1;
eDirection[2] *= -1;
// Find the refracted ray
double *refracted1 = &lightDoubles[9];
refractedRay(&eDirection[0], n, &refracted1[0], objects[ind].mat.snell);
d_normalize(&refracted1[0]);
ttrueFinal = 0.0;
finalObj = 0;
hitObject = false;
for (int k = 0; k < numObjects && generation > 0; k++)
{
if (k != ind)
{
// Find the ray equation transformations
newa(objects[k].unScale, objects[k].unRotate, &refracted1[0], &newA[0]);
newb(objects[k].unScale, objects[k].unRotate,
objects[k].unTranslate, point, &newB[0]);
// Find the quadratic equation coefficients
findCoeffs(&newA[0], &newB[0], &coeffs[0], true);
// Using the coefficients, find the roots
findRoots(&coeffs[0], &roots[0]);
// Check to see if the roots are FLT_MAX - if they are then the
// ray missed the superquadric. If they haven't missed then we
// can continue with the calculations.
if (roots[0] != FLT_MAX)
{
// Use the update rule to find tfinal
double tini = min(roots[0], roots[1]);
double tfinal = updateRule(&newA[0], &newB[0], &objects[k].e,
&objects[k].n, tini, epsilon);
/* Check to see if tfinal is FLT_MAX - if it is then the ray
* missed the superquadric. Additionally, if tfinal is negative
* then either the ray has started inside the object or is
* pointing away from the object; in both cases the ray has
* "missed". */
if (tfinal != FLT_MAX && tfinal >= 0)
{
if(hitObject && tfinal < ttrueFinal)
{
ttrueFinal = tfinal;
finalObj = k;
finalNewA[0] = newA[0];
finalNewA[1] = newA[1];
finalNewA[2] = newA[2];
finalNewB[0] = newB[0];
finalNewB[1] = newB[1];
finalNewB[2] = newB[2];
}
else if (!hitObject)
{
hitObject = true;
ttrueFinal = tfinal;
finalObj = k;
finalNewA[0] = newA[0];
finalNewA[1] = newA[1];
finalNewA[2] = newA[2];
finalNewB[0] = newB[0];
finalNewB[1] = newB[1];
finalNewB[2] = newB[2];
}
}
}
}
}
if (hitObject)
{
double intersectR[3];
double intersectRNormal[3];
findRay(&refracted1[0], point, &intersectR[0], ttrueFinal);
unitNormal(objects[finalObj].rotate, &finalNewA[0], &finalNewB[0],
&intersectRNormal[0], ttrueFinal, objects[finalObj].e,
objects[finalObj].n);
lighting(&intersectR[0], &intersectRNormal[0], e,
&objects[finalObj].mat,
l, numLights, objects, numObjects, epsilon,
finalObj, generation-1, &refractedLight[0], lightDoubles);
refractedLight[0] *= objects[ind].mat.opacity;
refractedLight[1] *= objects[ind].mat.opacity;
refractedLight[2] *= objects[ind].mat.opacity;
}
else
{
double *refA = &lightDoubles[18];
double *refB = &lightDoubles[21];
double *refCoeffs = &lightDoubles[24];
double *refRoots = &lightDoubles[27];
newa(objects[ind].unScale, objects[ind].unRotate, &refracted1[0], &refA[0]);
newb(objects[ind].unScale, objects[ind].unRotate,
objects[ind].unTranslate, point, &refB[0]);
findCoeffs(&refA[0], &refB[0], &refCoeffs[0], true);
findRoots(&refCoeffs[0], &refRoots[0]);
double tini = max(refRoots[0], refRoots[1]);
double tfinalRef = updateRule(&refA[0], &refB[0], &objects[ind].e,
&objects[ind].n, tini, epsilon);
bool isRefracted = true;
double outNormal[3];
double *outPoint = &lightDoubles[24];
double *outRay = &lightDoubles[27];
if (isRefracted) // the fuck is the point of this?
{
findRay(&refracted1[0], point, &outPoint[0], tfinalRef);
unitNormal(objects[ind].rotate, &refA[0], &refB[0], &outNormal[0], tfinalRef,
objects[ind].e, objects[ind].n);
refractedRay(&refracted1[0], &outNormal[0], &outRay[0],
(double) 1 / objects[ind].mat.snell);
// If the point has total internal reflection, then don't bother
// with the rest of the refraction calculations.
if(outRay[0] == FLT_MAX)
isRefracted = false;
}
// Now that we've found where the ray exits, check to see if it hits any
// objects; if it does, find the color contribution from that object
ttrueFinal = 0.0;
finalObj = 0;
hitObject = false;
for (int k = 0; k < numObjects && generation > 0 && isRefracted; k++)
{
if (k != ind)
{
// Find the ray equation transformations
newa(objects[k].unScale, objects[k].unRotate,
&outRay[0], &newA[0]);
newb(objects[k].unScale, objects[k].unRotate,
objects[k].unTranslate, &outPoint[0], &newB[0]);
// Find the quadratic equation coefficients
findCoeffs(&newA[0], &newB[0], &coeffs[0], true);
// Using the coefficients, find the roots
findRoots(&coeffs[0], &roots[0]);
// Check to see if the roots are FLT_MAX - if they are then the
// ray missed the superquadric. If they haven't missed then we
// can continue with the calculations.
if (roots[0] != FLT_MAX)
{
// Use the update rule to find tfinal
double tini = min(roots[0], roots[1]);
double tfinal = updateRule(&newA[0], &newB[0], &objects[k].e,
&objects[k].n, tini, epsilon);
/* Check to see if tfinal is FLT_MAX - if it is then the ray
* missed the superquadric. Additionally, if tfinal is negative
* then either the ray has started inside the object or is
* pointing away from the object; in both cases the ray has
* "missed". */
if (tfinal != FLT_MAX && tfinal >= 0)
{
if(hitObject && tfinal < ttrueFinal)
{
ttrueFinal = tfinal;
finalObj = k;
finalNewA[0] = newA[0];
finalNewA[1] = newA[1];
finalNewA[2] = newA[2];
finalNewB[0] = newB[0];
finalNewB[1] = newB[1];
finalNewB[2] = newB[2];
}
else if (!hitObject)
{
hitObject = true;
ttrueFinal = tfinal;
finalObj = k;
finalNewA[0] = newA[0];
finalNewA[1] = newA[1];
finalNewA[2] = newA[2];
finalNewB[0] = newB[0];
finalNewB[1] = newB[1];
finalNewB[2] = newB[2];
}
}
}
}
}
if (hitObject)
{
double intersectR[3];
double intersectRNormal[3];
findRay(&outRay[0], &outPoint[0], &intersectR[0], ttrueFinal);
unitNormal(objects[finalObj].rotate, &finalNewA[0], &finalNewB[0],
&intersectRNormal[0], ttrueFinal, objects[finalObj].e,
objects[finalObj].n);
lighting(&intersectR[0], &intersectRNormal[0], e,
&objects[finalObj].mat,
l, numLights, objects, numObjects, epsilon,
finalObj, generation - 1, &refractedLight[0], lightDoubles);
refractedLight[0] *= objects[ind].mat.opacity;
refractedLight[1] *= objects[ind].mat.opacity;
refractedLight[2] *= objects[ind].mat.opacity;
}
}
}
#endif
double *minVec = &lightDoubles[0];
double *maxVec = &lightDoubles[3];
minVec[0] = 1;
minVec[1] = 1;
minVec[2] = 1;
cProduct(&diffuseSum[0], dif, &diffuseSum[0]);
cProduct(&specularSum[0], spec, &specularSum[0]);
maxVec[0] = diffuseSum[0] + specularSum[0] + reflectedLight[0] + refractedLight[0];
maxVec[1] = diffuseSum[1] + specularSum[1] + reflectedLight[1] + refractedLight[1];
maxVec[2] = diffuseSum[2] + specularSum[2] + reflectedLight[2] + refractedLight[2];
cWiseMin(&minVec[0], &maxVec[0], res);
}
__global__
void raytraceKernel(double *grid, Object *objects, Point_Light *lightsPPM,
double *data, double *bgColor, double *e1, double *e2,
double *e3, double *lookFrom, double *rayDoubles,
double *lightDoubles,
int Nx, int Ny, bool antiAliased)
{
/* data[0] = numObjects
* data[1] = numLights
* data[2] = filmX
* data[3] = filmY
* data[4] = epsilon
* data[5] = filmDepth
*/
// Parallize by screen pixel
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
// Debugging
/*if (i == 0 && j == 0) {
print_objects(objects, data[0]);
print_lights(lightsPPM, data[1]);
}
__syncthreads();*/
#if SINGLETHREADMODE
if (i == 0 && j == 0) {
for(i = 0; i < Nx; i++)
{
for(j = 0; j < Ny; j++)
#else
while (i < Nx)
{
j = threadIdx.y + blockDim.y * blockIdx.y;
while (j < Ny)
#endif
{
/* Do all of this within the while loop to prevent threads with i's
* and j's outside of the image boundaris from accessing rayDoubles.
*/
double dx = data[2] / (double) Nx;
double dy = data[3] / (double) Ny;
double ttrueFinal = 0.0;
int finalObj = 0;
bool hitObject = false;
int rayInd = (j * Nx + i) * 26;
double *finalNewA = &rayDoubles[rayInd];
double *finalNewB = &rayDoubles[rayInd + 3];
double *pointA = &rayDoubles[rayInd + 6];
double *newA = &rayDoubles[rayInd + 9];
double *newB = &rayDoubles[rayInd + 12];
double *coeffs = &rayDoubles[rayInd + 15];
double *intersect = &rayDoubles[rayInd + 18];
double *intersectNormal = &rayDoubles[rayInd + 21];
double *roots = &rayDoubles[rayInd + 24];
double *lDoubles = &lightDoubles[(j * Nx + i) * 32];
// The positions are subtracted by a Nx/2 or Ny/2 term to center
// the film plane
double px = (i * dx) - (data[2] / (double) 2);
double py = (j * dy) - (data[3] / (double) 2);
double pxColor[] = {bgColor[0], bgColor[1], bgColor[2]};
if (!antiAliased)
{
// Transform point A into film coordinates
pointA[0] = (data[5] * e3[0]) + (px * e1[0]) + (py * e2[0]);
pointA[1] = (data[5] * e3[1]) + (px * e1[1]) + (py * e2[1]);
pointA[2] = (data[5] * e3[2]) + (px * e1[2]) + (py * e2[2]);
hitObject = false;
finalObj = 0, ttrueFinal = 0;
for (int k = 0; k < data[0]; k++)
{
// Find the ray equation transformations
newa(objects[k].unScale, objects[k].unRotate, pointA, newA);
newb(objects[k].unScale, objects[k].unRotate,
objects[k].unTranslate, lookFrom, newB);
// Find the quadratic equation coefficients
findCoeffs(newA, newB, coeffs, true);
// Using the coefficients, find the roots
findRoots(coeffs, roots);
// Check to see if the roots are FLT_MAX - if they are then the
// ray missed the superquadric. If they haven't missed then we
// can continue with the calculations.
if (roots[0] != FLT_MAX)
{
// Use the update rule to find tfinal
double tini = min(roots[0], roots[1]);
double tfinal = updateRule(newA, newB, &objects[k].e,
&objects[k].n, tini, data[4]);
/* Check to see if tfinal is FLT_MAX - if it is then the ray
* missed the superquadric. Additionally, if tfinal is negative
* then either the ray has started inside the object or is
* pointing away from the object; in both cases the ray has
* "missed". */
if (tfinal != FLT_MAX && tfinal >= 0)
{
if(hitObject && tfinal < ttrueFinal)
{
ttrueFinal = tfinal;
finalObj = k;
finalNewA[0] = newA[0];
finalNewA[1] = newA[1];
finalNewA[2] = newA[2];
finalNewB[0] = newB[0];
finalNewB[1] = newB[1];
finalNewB[2] = newB[2];
}
else if (!hitObject)
{
hitObject = true;
ttrueFinal = tfinal;
finalObj = k;
finalNewA[0] = newA[0];
finalNewA[1] = newA[1];
finalNewA[2] = newA[2];
finalNewB[0] = newB[0];
finalNewB[1] = newB[1];
finalNewB[2] = newB[2];
}
}
}
}
if(hitObject)
{
findRay(pointA, lookFrom, intersect, ttrueFinal);
unitNormal(objects[finalObj].rotate, finalNewA, finalNewB,
intersectNormal, ttrueFinal, objects[finalObj].e,
objects[finalObj].n);
lighting(intersect, intersectNormal, lookFrom,
&objects[finalObj].mat,
lightsPPM, data[1], objects, data[0], data[4],
finalObj, RECURSIONDEPTH,
&pxColor[0], lDoubles);
}
}
else
{
double denom = 3 + (2 / sqrt((double) 2));
double pxCoeffs[] = {(1 / (2 * sqrt((double) 2))) / denom,
(1 / (double) 2) / denom,
(1 / (2 * sqrt((double) 2))) / denom,
(1 / (double) 2) / denom,
1 / denom,
(1 / (double) 2) / denom,
(1 / (2 * sqrt((double) 2))) / denom,
(1 / (double) 2) / denom,
(1 / (2 * sqrt((double) 2))) / denom};
int counter = 0;
for (int g = -1; g <= 1; g++)
{
for (int h = -1; h <= 1; h++)
{
double thisPx = px + (g * (dx / (double) 2));
double thisPy = py + (h * (dy / (double) 2));
// Transform point A into film Coordinates
pointA[0] = (data[5] * e3[0]) + (thisPx * e1[0]) + (thisPy * e2[0]);
pointA[1] = (data[5] * e3[1]) + (thisPx * e1[1]) + (thisPy * e2[1]);
pointA[2] = (data[5] * e3[2]) + (thisPx * e1[2]) + (thisPy * e2[2]);
hitObject = false;
finalObj = 0, ttrueFinal = 0;
for (int k = 0; k < data[0]; k++)
{
// Find the ray equation transformations
newa(objects[k].unScale, objects[k].unRotate,
pointA, newA);
newb(objects[k].unScale, objects[k].unRotate,
objects[k].unTranslate, lookFrom, newB);
// Find the quadratic equation coefficients
findCoeffs(newA, newB, coeffs, true);
// Using the coefficients, find the roots
findRoots(coeffs, roots);
// Check to see if the roots are FLT_MAX - if they are then the
// ray missed the superquadric. If they haven't missed then we
// can continue with the calculations.
if (roots[0] != FLT_MAX)
{
// Use the update rule to find tfinal
double tini = min(roots[0], roots[1]);
double tfinal = updateRule(newA, newB, &objects[k].e,
&objects[k].n, tini, data[4]);
/* Check to see if tfinal is FLT_MAX - if it is then the ray
* missed the superquadric. Additionally, if tfinal is negative
* then either the ray has started inside the object or is
* pointing away from the object; in both cases the ray has
* "missed". */
if (tfinal != FLT_MAX && tfinal >= 0)
{
if(hitObject && tfinal < ttrueFinal)
{
ttrueFinal = tfinal;
finalObj = k;
finalNewA[0] = newA[0];
finalNewA[1] = newA[1];
finalNewA[2] = newA[2];
finalNewB[0] = newB[0];
finalNewB[1] = newB[1];
finalNewB[2] = newB[2];
}
else if (!hitObject)
{
hitObject = true;
ttrueFinal = tfinal;
finalObj = k;
finalNewA[0] = newA[0];
finalNewA[1] = newA[1];
finalNewA[2] = newA[2];
finalNewB[0] = newB[0];
finalNewB[1] = newB[1];
finalNewB[2] = newB[2];
}
}
}
}
if(hitObject)
{
findRay(pointA, lookFrom, intersect, ttrueFinal);
unitNormal(objects[finalObj].rotate, finalNewA,
finalNewB, intersectNormal, ttrueFinal,
objects[finalObj].e, objects[finalObj].n);
double color[] = {0, 0, 0};
lighting(intersect, intersectNormal, lookFrom,
&objects[finalObj].mat,
lightsPPM, data[1], objects, data[0],
data[4],
finalObj, RECURSIONDEPTH,
&color[0], lDoubles);
pxColor[0] += color[0] * pxCoeffs[counter];
pxColor[1] += color[1] * pxCoeffs[counter];
pxColor[2] += color[2] * pxCoeffs[counter];
}
counter++;
}
}
}
int index = (j * Nx + i) * 3;
grid[index] = pxColor[0];
grid[index + 1] = pxColor[1];
grid[index + 2] = pxColor[2];
#if SINGLETHREADMODE
}
}
}
}
#else
j += blockDim.y * gridDim.y;
}
i += blockDim.x * gridDim.x;
}
}
#endif
void callRaytraceKernel(double *grid, Object *objects, Point_Light *lightsPPM,
double *data, double *bgColor, double *e1, double *e2,
double *e3, double *lookFrom, int Nx, int Ny,
bool antiAliased, int blockPower)
{
int blockSize = pow(2, blockPower);
dim3 blocks;
blocks.x = blockSize;
blocks.y = blockSize;
int gx = (Nx / blockSize);
int gy = (Ny / blockSize);
if (gx < 1) gx = 1;
if (gy < 1) gy = 1;
dim3 gridSize;
gridSize.x = gx;
gridSize.y = gy;
// Mostly debug info, but possibly interesting
int numThreads = (blockSize * gx) * (blockSize * gy);
printf("Image size: %d x %d (%d Pixels)\n", Nx, Ny, Nx * Ny);
printf("Total number of threads: %d\n", (blockSize * gx) * (blockSize * gy));
float factor = numThreads / (float) (1024 * 1024);
size_t deviceLimit;
gpuErrChk(cudaDeviceGetLimit(&deviceLimit, cudaLimitStackSize));
printf("Original Device stack size: %d\n", (int) deviceLimit);
printf("Total Device stack memory: %0.2f MB\n", (int) deviceLimit * factor);
// Recursion's a bitch, gotta increase that stack size
// (Also relevant for images larger than 400 x 400 or so, I suppose)
gpuErrChk(cudaDeviceSetLimit(cudaLimitStackSize, 4096));
gpuErrChk(cudaDeviceGetLimit(&deviceLimit, cudaLimitStackSize));
printf("New Device stack size: %d\n", (int) deviceLimit);
printf("Total Device stack memory: %0.2f MB\n", (int) deviceLimit * factor);
// Allocate space on the gpu for the double arrays in the kernel
double *rayDoubles;
gpuErrChk(cudaMalloc(&rayDoubles, sizeof(double) * Nx * Ny * 26));
gpuErrChk(cudaMemset(rayDoubles, 0, sizeof(double) * Nx * Ny * 26));
double *lightDoubles;
gpuErrChk(cudaMalloc(&lightDoubles, sizeof(double) * Nx * Ny * 32));
gpuErrChk(cudaMemset(lightDoubles, 0, sizeof(double) * Nx * Ny * 32));
raytraceKernel<<<gridSize, blocks>>>(grid, objects, lightsPPM, data,
bgColor, e1, e2, e3, lookFrom,
rayDoubles, lightDoubles, Nx, Ny,
antiAliased);
gpuErrChk(cudaPeekAtLastError());
gpuErrChk(cudaDeviceSynchronize());
gpuErrChk(cudaFree(rayDoubles));
gpuErrChk(cudaFree(lightDoubles));
} | #include <cstdio>
#include <math.h>
#include <hip/hip_runtime.h>
struct Point_Light;
struct Material;
struct Object;
void callRaytraceKernel(double *grid, Object *objects, Point_Light *lightsPPM,
double *data, double *bgColor, double *e1, double *e2,
double *e3, double *lookFrom, int Nx, int Ny,
bool antiAliased, int blockPower); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <cstdio>
#include <math.h>
#include <hip/hip_runtime.h>
struct Point_Light;
struct Material;
struct Object;
void callRaytraceKernel(double *grid, Object *objects, Point_Light *lightsPPM,
double *data, double *bgColor, double *e1, double *e2,
double *e3, double *lookFrom, int Nx, int Ny,
bool antiAliased, int blockPower); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <cstdio>
#include <math.h>
#include <hip/hip_runtime.h>
struct Point_Light;
struct Material;
struct Object;
void callRaytraceKernel(double *grid, Object *objects, Point_Light *lightsPPM,
double *data, double *bgColor, double *e1, double *e2,
double *e3, double *lookFrom, int Nx, int Ny,
bool antiAliased, int blockPower); | .text
.file "raytraceCuda.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012eb29_00000000-6_raytraceCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8cProductPdS_S_
.type _Z8cProductPdS_S_, @function
_Z8cProductPdS_S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8cProductPdS_S_, .-_Z8cProductPdS_S_
.globl _Z8cWiseMinPdS_S_
.type _Z8cWiseMinPdS_S_, @function
_Z8cWiseMinPdS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z8cWiseMinPdS_S_, .-_Z8cWiseMinPdS_S_
.globl _Z4signd
.type _Z4signd, @function
_Z4signd:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z4signd, .-_Z4signd
.globl _Z6d_normPd
.type _Z6d_normPd, @function
_Z6d_normPd:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z6d_normPd, .-_Z6d_normPd
.globl _Z11d_normalizePd
.type _Z11d_normalizePd, @function
_Z11d_normalizePd:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z11d_normalizePd, .-_Z11d_normalizePd
.globl _Z5d_dotPdS_
.type _Z5d_dotPdS_, @function
_Z5d_dotPdS_:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z5d_dotPdS_, .-_Z5d_dotPdS_
.globl _Z3isqPdS_S_
.type _Z3isqPdS_S_, @function
_Z3isqPdS_S_:
.LFB2064:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z3isqPdS_S_, .-_Z3isqPdS_S_
.globl _Z7findRayPdS_S_d
.type _Z7findRayPdS_S_d, @function
_Z7findRayPdS_S_d:
.LFB2065:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z7findRayPdS_S_d, .-_Z7findRayPdS_S_d
.globl _Z4newaPdS_S_S_
.type _Z4newaPdS_S_S_, @function
_Z4newaPdS_S_S_:
.LFB2066:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size _Z4newaPdS_S_S_, .-_Z4newaPdS_S_S_
.globl _Z4newbPdS_S_S_S_
.type _Z4newbPdS_S_S_S_, @function
_Z4newbPdS_S_S_S_:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z4newbPdS_S_S_S_, .-_Z4newbPdS_S_S_S_
.globl _Z10findCoeffsPdS_S_b
.type _Z10findCoeffsPdS_S_b, @function
_Z10findCoeffsPdS_S_b:
.LFB2068:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2068:
.size _Z10findCoeffsPdS_S_b, .-_Z10findCoeffsPdS_S_b
.globl _Z9findRootsPdS_
.type _Z9findRootsPdS_, @function
_Z9findRootsPdS_:
.LFB2069:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2069:
.size _Z9findRootsPdS_, .-_Z9findRootsPdS_
.globl _Z11isqGradientPdS_dd
.type _Z11isqGradientPdS_dd, @function
_Z11isqGradientPdS_dd:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z11isqGradientPdS_dd, .-_Z11isqGradientPdS_dd
.globl _Z6gPrimePdS_dd
.type _Z6gPrimePdS_dd, @function
_Z6gPrimePdS_dd:
.LFB2071:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2071:
.size _Z6gPrimePdS_dd, .-_Z6gPrimePdS_dd
.globl _Z10updateRulePdS_S_S_dd
.type _Z10updateRulePdS_S_S_dd, @function
_Z10updateRulePdS_S_S_dd:
.LFB2072:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2072:
.size _Z10updateRulePdS_S_S_dd, .-_Z10updateRulePdS_S_S_dd
.globl _Z10unitNormalPdS_S_S_ddd
.type _Z10unitNormalPdS_S_S_ddd, @function
_Z10unitNormalPdS_S_S_ddd:
.LFB2073:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2073:
.size _Z10unitNormalPdS_S_S_ddd, .-_Z10unitNormalPdS_S_S_ddd
.globl _Z11vectorAnglePdS_
.type _Z11vectorAnglePdS_, @function
_Z11vectorAnglePdS_:
.LFB2074:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2074:
.size _Z11vectorAnglePdS_, .-_Z11vectorAnglePdS_
.globl _Z12refractedRayPdS_S_d
.type _Z12refractedRayPdS_S_d, @function
_Z12refractedRayPdS_S_d:
.LFB2075:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2075:
.size _Z12refractedRayPdS_S_d, .-_Z12refractedRayPdS_S_d
.globl _Z13print_objectsP6Objecti
.type _Z13print_objectsP6Objecti, @function
_Z13print_objectsP6Objecti:
.LFB2076:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2076:
.size _Z13print_objectsP6Objecti, .-_Z13print_objectsP6Objecti
.globl _Z12print_lightsP11Point_Lighti
.type _Z12print_lightsP11Point_Lighti, @function
_Z12print_lightsP11Point_Lighti:
.LFB2077:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2077:
.size _Z12print_lightsP11Point_Lighti, .-_Z12print_lightsP11Point_Lighti
.globl _Z8lightingPdS_S_P8MaterialP11Point_LightiP6ObjectidiiS_S_
.type _Z8lightingPdS_S_P8MaterialP11Point_LightiP6ObjectidiiS_S_, @function
_Z8lightingPdS_S_P8MaterialP11Point_LightiP6ObjectidiiS_S_:
.LFB2078:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2078:
.size _Z8lightingPdS_S_P8MaterialP11Point_LightiP6ObjectidiiS_S_, .-_Z8lightingPdS_S_P8MaterialP11Point_LightiP6ObjectidiiS_S_
.globl _Z75__device_stub__Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iibPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib
.type _Z75__device_stub__Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iibPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib, @function
_Z75__device_stub__Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iibPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib:
.LFB2104:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
movq 304(%rsp), %rax
movq %rax, 40(%rsp)
movq 312(%rsp), %rax
movq %rax, 32(%rsp)
movq 320(%rsp), %rax
movq %rax, 24(%rsp)
movq 328(%rsp), %rax
movq %rax, 16(%rsp)
movq 336(%rsp), %rax
movq %rax, 8(%rsp)
movl 360(%rsp), %eax
movb %al, 4(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 8(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
leaq 352(%rsp), %rax
movq %rax, 256(%rsp)
leaq 4(%rsp), %rax
movq %rax, 264(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 312
pushq 104(%rsp)
.cfi_def_cfa_offset 320
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z75__device_stub__Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iibPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib, .-_Z75__device_stub__Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iibPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib
.globl _Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib
.type _Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib, @function
_Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib:
.LFB2105:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z75__device_stub__Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iibPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib, .-_Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Image size: %d x %d (%d Pixels)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Total number of threads: %d\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/matathias/Raytracer/master/Multi-threaded/raytraceCuda.cu"
.section .rodata.str1.1
.LC5:
.string "GPUassert: %s %s %d\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Original Device stack size: %d\n"
.align 8
.LC7:
.string "Total Device stack memory: %0.2f MB\n"
.section .rodata.str1.1
.LC8:
.string "New Device stack size: %d\n"
.text
.globl _Z18callRaytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_iibi
.type _Z18callRaytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_iibi, @function
_Z18callRaytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_iibi:
.LFB2079:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movq 192(%rsp), %r14
movq 200(%rsp), %rax
movq %rax, 48(%rsp)
movq 208(%rsp), %r15
movl 216(%rsp), %ebp
movl 224(%rsp), %r12d
movl 232(%rsp), %eax
movl %eax, 60(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
pxor %xmm1, %xmm1
cvtsi2sdl 240(%rsp), %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %ecx
movl $1, 104(%rsp)
movl %ecx, 96(%rsp)
movl %ecx, 100(%rsp)
movl %ebp, %eax
cltd
idivl %ecx
testl %eax, %eax
movl $1, %edx
cmovg %eax, %edx
movl %edx, %ebx
movl %r12d, %eax
cltd
idivl %ecx
testl %eax, %eax
movl $1, %edx
cmovle %edx, %eax
movl $1, 116(%rsp)
movl %ebx, 108(%rsp)
movl %eax, 112(%rsp)
imull %ecx, %ebx
imull %eax, %ecx
imull %ecx, %ebx
movl %ebp, %r8d
imull %r12d, %r8d
movl %r12d, %ecx
movl %ebp, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss .LC3(%rip), %xmm0
movss %xmm0, 56(%rsp)
leaq 72(%rsp), %rdi
movl $0, %esi
call cudaDeviceGetLimit@PLT
testl %eax, %eax
jne .L68
movl 72(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 72(%rsp), %xmm0
mulss 56(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $4096, %esi
movl $0, %edi
call cudaDeviceSetLimit@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L69
leaq 72(%rsp), %rdi
movl $0, %esi
call cudaDeviceGetLimit@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L70
movl 72(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 72(%rsp), %xmm0
mulss 56(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebp, %rbx
movslq %r12d, %rax
imulq %rax, %rbx
leaq (%rbx,%rbx,2), %rax
leaq (%rbx,%rax,4), %r13
salq $4, %r13
leaq 80(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L71
movq %r13, %rdx
movl $0, %esi
movq 80(%rsp), %rdi
call cudaMemset@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L72
salq $8, %rbx
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L73
movq %rbx, %rdx
movl $0, %esi
movq 88(%rsp), %rdi
call cudaMemset@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L74
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L61:
call cudaPeekAtLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L76
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L77
movq 80(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L78
movq 88(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L79
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L80
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $1179, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L69:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $1185, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L70:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $1186, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L71:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $1192, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L72:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $1193, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r13d, %edi
call exit@PLT
.L73:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $1196, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r13d, %edi
call exit@PLT
.L74:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $1197, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L75:
movzbl 60(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 200
pushq %r12
.cfi_def_cfa_offset 208
pushq %rbp
.cfi_def_cfa_offset 216
pushq 112(%rsp)
.cfi_def_cfa_offset 224
pushq 112(%rsp)
.cfi_def_cfa_offset 232
pushq %r15
.cfi_def_cfa_offset 240
pushq 96(%rsp)
.cfi_def_cfa_offset 248
pushq %r14
.cfi_def_cfa_offset 256
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movq 88(%rsp), %rcx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z75__device_stub__Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iibPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib
addq $64, %rsp
.cfi_def_cfa_offset 192
jmp .L61
.L76:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $1203, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L77:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $1204, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L78:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $1205, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L79:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $1206, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2079:
.size _Z18callRaytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_iibi, .-_Z18callRaytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_iibi
.section .rodata.str1.8
.align 8
.LC9:
.string "_Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z14raytraceKernelPdP6ObjectP11Point_LightS_S_S_S_S_S_S_S_iib(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1073741824
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 897581056
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "raytraceCuda.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Date March 28 2029
//Programer: Hemanta Bhattarai
// Progarm : To add two arrays and compare computation time in host and device
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h> //for random numbers
#include <time.h>
#include <sys/time.h>
#define gpuErrchk(ans){ gpuAssert((ans),__FILE__, __LINE__);}
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
if(code != cudaSuccess)
{
fprintf(stderr, "GPUassert : %s %s %d\n", cudaGetErrorString(code), file, line);
if(abort) exit(code);
}
}
// device kernal
__global__ void vecAdd(float *A, float *B, float *C, float *D, int array_size)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
while(i < array_size)
{
D[i] = A[i] + B[i] + C[i];
i += blockDim.x * gridDim.x; // each iteration will move the block-grid to access other element in matrix
}
}
int main()
{
// host function definition
float get_random();
//variable definition
float *hA, *hB, *hC, *hD, *dA, *dB, *dC;
float *dD, *hE;
float size_of_array;
//define size of array
printf("Enter the size of array");
scanf("%f",&size_of_array);
float size = sizeof(int) * size_of_array;
//memory allocation in host
hA = (float*)malloc(size);
hB = (float*)malloc(size);
hC = (float*)malloc(size);
hD = (float*)malloc(size);
hE = (float*)malloc(size);
//memory allocation in device
gpuErrchk(cudaMalloc((void**)&dA,size));
gpuErrchk(cudaMalloc((void**)&dB,size));
gpuErrchk(cudaMalloc((void**)&dC,size));
gpuErrchk(cudaMalloc((void**)&dD,size));
//array initilization
for(int i=0; i<size_of_array; ++i) hA[i] = get_random();
for(int i=0; i<size_of_array; ++i) hB[i] = get_random();
for(int i=0; i<size_of_array; ++i) hC[i] = get_random();
clock_t host_begin, host_end;
//record begin of host computation
host_begin = clock();
//add vectors in host
for(int i=0; i<size_of_array; ++i) hE[i] = hA[i] + hB[i] + hC[i];
//record end of host computation
host_end = clock();
clock_t device_begin, device_end;
//record of device computation
device_begin = clock();
//copy host data to memory
gpuErrchk(cudaMemcpy(dA, hA, size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(dB, hB, size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(dC, hC, size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(dD, hD, size, cudaMemcpyHostToDevice));
//record start of device computation
// add array in device
vecAdd<<<128,128>>>(dA, dB, dC, dD, size_of_array);
gpuErrchk(cudaDeviceSynchronize());
//record end of device computation
device_end = clock();
//copy data from device to host
gpuErrchk(cudaMemcpy(hD, dD, size, cudaMemcpyDeviceToHost));
double host_time, device_time;
host_time = (double)((double)(host_end - host_begin)/(CLOCKS_PER_SEC));
device_time = (double)((double)(device_end - device_begin)/(CLOCKS_PER_SEC));
//print the time of host and device computation
printf("Host computation time: %f\n",host_time);
printf("Device computation time: %f\n",device_time);
//display the devation of device and host result
float sum = 0;
for(int i=0; i< size_of_array; ++i)
{
sum += hE[i] - hD[i];
}
printf("The deviation of host and device result is %f\n",sum);
//free host memory
free(hA);
free(hB);
free(hC);
free(hD);
free(hE);
//free device memory
gpuErrchk(cudaFree(dA));
gpuErrchk(cudaFree(dB));
gpuErrchk(cudaFree(dC));
gpuErrchk(cudaFree(dD));
}
//random number generator
float get_random()
{
return rand() % 100 + 1;
} | code for sm_80
Function : _Z6vecAddPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IMAD.WIDE R6, R0.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x0c0fe400078e0209 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fe200078e0209 */
/*00f0*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */
/* 0x000fca0000000f00 */
/*0100*/ IMAD R0, R13, c[0x0][0xc], R0 ; /* 0x000003000d007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0120*/ FADD R10, R4, R3 ; /* 0x00000003040a7221 */
/* 0x004fc80000000000 */
/*0130*/ FADD R11, R10, R7 ; /* 0x000000070a0b7221 */
/* 0x008fca0000000000 */
/*0140*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e6000c101904 */
/*0150*/ @!P0 BRA 0x70 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Date March 28 2029
//Programer: Hemanta Bhattarai
// Progarm : To add two arrays and compare computation time in host and device
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h> //for random numbers
#include <time.h>
#include <sys/time.h>
#define gpuErrchk(ans){ gpuAssert((ans),__FILE__, __LINE__);}
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
if(code != cudaSuccess)
{
fprintf(stderr, "GPUassert : %s %s %d\n", cudaGetErrorString(code), file, line);
if(abort) exit(code);
}
}
// device kernal
__global__ void vecAdd(float *A, float *B, float *C, float *D, int array_size)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
while(i < array_size)
{
D[i] = A[i] + B[i] + C[i];
i += blockDim.x * gridDim.x; // each iteration will move the block-grid to access other element in matrix
}
}
int main()
{
// host function definition
float get_random();
//variable definition
float *hA, *hB, *hC, *hD, *dA, *dB, *dC;
float *dD, *hE;
float size_of_array;
//define size of array
printf("Enter the size of array");
scanf("%f",&size_of_array);
float size = sizeof(int) * size_of_array;
//memory allocation in host
hA = (float*)malloc(size);
hB = (float*)malloc(size);
hC = (float*)malloc(size);
hD = (float*)malloc(size);
hE = (float*)malloc(size);
//memory allocation in device
gpuErrchk(cudaMalloc((void**)&dA,size));
gpuErrchk(cudaMalloc((void**)&dB,size));
gpuErrchk(cudaMalloc((void**)&dC,size));
gpuErrchk(cudaMalloc((void**)&dD,size));
//array initilization
for(int i=0; i<size_of_array; ++i) hA[i] = get_random();
for(int i=0; i<size_of_array; ++i) hB[i] = get_random();
for(int i=0; i<size_of_array; ++i) hC[i] = get_random();
clock_t host_begin, host_end;
//record begin of host computation
host_begin = clock();
//add vectors in host
for(int i=0; i<size_of_array; ++i) hE[i] = hA[i] + hB[i] + hC[i];
//record end of host computation
host_end = clock();
clock_t device_begin, device_end;
//record of device computation
device_begin = clock();
//copy host data to memory
gpuErrchk(cudaMemcpy(dA, hA, size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(dB, hB, size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(dC, hC, size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(dD, hD, size, cudaMemcpyHostToDevice));
//record start of device computation
// add array in device
vecAdd<<<128,128>>>(dA, dB, dC, dD, size_of_array);
gpuErrchk(cudaDeviceSynchronize());
//record end of device computation
device_end = clock();
//copy data from device to host
gpuErrchk(cudaMemcpy(hD, dD, size, cudaMemcpyDeviceToHost));
double host_time, device_time;
host_time = (double)((double)(host_end - host_begin)/(CLOCKS_PER_SEC));
device_time = (double)((double)(device_end - device_begin)/(CLOCKS_PER_SEC));
//print the time of host and device computation
printf("Host computation time: %f\n",host_time);
printf("Device computation time: %f\n",device_time);
//display the devation of device and host result
float sum = 0;
for(int i=0; i< size_of_array; ++i)
{
sum += hE[i] - hD[i];
}
printf("The deviation of host and device result is %f\n",sum);
//free host memory
free(hA);
free(hB);
free(hC);
free(hD);
free(hE);
//free device memory
gpuErrchk(cudaFree(dA));
gpuErrchk(cudaFree(dB));
gpuErrchk(cudaFree(dC));
gpuErrchk(cudaFree(dD));
}
//random number generator
float get_random()
{
return rand() % 100 + 1;
} | .file "tmpxft_001173c7_00000000-6_add_vector_very_large.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert : %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z10get_randomv
.type _Z10get_randomv, @function
_Z10get_randomv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10get_randomv, .-_Z10get_randomv
.globl _Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i
.type _Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i, @function
_Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6vecAddPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i, .-_Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i
.globl _Z6vecAddPfS_S_S_i
.type _Z6vecAddPfS_S_S_i, @function
_Z6vecAddPfS_S_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6vecAddPfS_S_S_i, .-_Z6vecAddPfS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Enter the size of array"
.LC3:
.string "%f"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Hemanta-Bhattarai/Self_Learning/master/CUDA/vector_operations/add_vector_very_large.cu"
.section .rodata.str1.1
.LC8:
.string "Host computation time: %f\n"
.LC9:
.string "Device computation time: %f\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "The deviation of host and device result is %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 60(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movss .LC4(%rip), %xmm0
mulss 60(%rsp), %xmm0
comiss .LC5(%rip), %xmm0
jnb .L22
cvttss2siq %xmm0, %r15
.L23:
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r15, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
leaq 64(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $70, %edx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 72(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $71, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 80(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $72, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 88(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $73, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ebx
movss 60(%rsp), %xmm1
pxor %xmm0, %xmm0
comiss %xmm0, %xmm1
jbe .L29
.L26:
call _Z10get_randomv
movss %xmm0, -4(%r13,%rbx,4)
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
movss 60(%rsp), %xmm0
addq $1, %rbx
comiss %xmm1, %xmm0
ja .L26
pxor %xmm1, %xmm1
comiss %xmm1, %xmm0
jbe .L29
movl $1, %ebx
.L28:
call _Z10get_randomv
movss %xmm0, -4(%r12,%rbx,4)
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
movss 60(%rsp), %xmm0
addq $1, %rbx
comiss %xmm1, %xmm0
ja .L28
pxor %xmm1, %xmm1
comiss %xmm1, %xmm0
jbe .L29
movl $1, %ebx
.L31:
call _Z10get_randomv
movss %xmm0, -4(%rbp,%rbx,4)
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
addq $1, %rbx
movss 60(%rsp), %xmm1
comiss %xmm0, %xmm1
ja .L31
.L29:
call clock@PLT
movq %rax, 16(%rsp)
movss 60(%rsp), %xmm1
movl $1, %eax
pxor %xmm0, %xmm0
comiss %xmm0, %xmm1
jbe .L32
.L34:
movss -4(%r13,%rax,4), %xmm0
addss -4(%r12,%rax,4), %xmm0
addss -4(%rbp,%rax,4), %xmm0
movss %xmm0, -4(%r14,%rax,4)
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addq $1, %rax
comiss %xmm0, %xmm1
ja .L34
.L32:
call clock@PLT
movq %rax, 24(%rsp)
call clock@PLT
movq %rax, 32(%rsp)
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $102, %edx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $103, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $104, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $105, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $128, 108(%rsp)
movl $1, 112(%rsp)
movl $128, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L35:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $111, %edx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call clock@PLT
movq %rax, 40(%rsp)
movl $2, %ecx
movq %r15, %rdx
movq 88(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $118, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC7(%rip), %xmm1
divsd %xmm1, %xmm0
movq %xmm0, %rbx
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd %xmm1, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 60(%rsp), %xmm2
movl $1, %eax
pxor %xmm0, %xmm0
comiss %xmm0, %xmm2
jbe .L54
.L38:
movss -4(%r14,%rax,4), %xmm1
movq 8(%rsp), %rdx
subss -4(%rdx,%rax,4), %xmm1
addss %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
addq $1, %rax
comiss %xmm1, %xmm2
ja .L38
.L36:
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $144, %edx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $145, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 80(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $146, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 88(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $147, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L57
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
subss .LC5(%rip), %xmm0
cvttss2siq %xmm0, %r15
btcq $63, %r15
jmp .L23
.L56:
cvttss2sil 60(%rsp), %r8d
movq 88(%rsp), %rcx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i
jmp .L35
.L54:
pxor %xmm0, %xmm0
jmp .L36
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z6vecAddPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1082130432
.align 4
.LC5:
.long 1593835520
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Date March 28 2029
//Programer: Hemanta Bhattarai
// Progarm : To add two arrays and compare computation time in host and device
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h> //for random numbers
#include <time.h>
#include <sys/time.h>
#define gpuErrchk(ans){ gpuAssert((ans),__FILE__, __LINE__);}
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
if(code != cudaSuccess)
{
fprintf(stderr, "GPUassert : %s %s %d\n", cudaGetErrorString(code), file, line);
if(abort) exit(code);
}
}
// device kernal
__global__ void vecAdd(float *A, float *B, float *C, float *D, int array_size)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
while(i < array_size)
{
D[i] = A[i] + B[i] + C[i];
i += blockDim.x * gridDim.x; // each iteration will move the block-grid to access other element in matrix
}
}
int main()
{
// host function definition
float get_random();
//variable definition
float *hA, *hB, *hC, *hD, *dA, *dB, *dC;
float *dD, *hE;
float size_of_array;
//define size of array
printf("Enter the size of array");
scanf("%f",&size_of_array);
float size = sizeof(int) * size_of_array;
//memory allocation in host
hA = (float*)malloc(size);
hB = (float*)malloc(size);
hC = (float*)malloc(size);
hD = (float*)malloc(size);
hE = (float*)malloc(size);
//memory allocation in device
gpuErrchk(cudaMalloc((void**)&dA,size));
gpuErrchk(cudaMalloc((void**)&dB,size));
gpuErrchk(cudaMalloc((void**)&dC,size));
gpuErrchk(cudaMalloc((void**)&dD,size));
//array initilization
for(int i=0; i<size_of_array; ++i) hA[i] = get_random();
for(int i=0; i<size_of_array; ++i) hB[i] = get_random();
for(int i=0; i<size_of_array; ++i) hC[i] = get_random();
clock_t host_begin, host_end;
//record begin of host computation
host_begin = clock();
//add vectors in host
for(int i=0; i<size_of_array; ++i) hE[i] = hA[i] + hB[i] + hC[i];
//record end of host computation
host_end = clock();
clock_t device_begin, device_end;
//record of device computation
device_begin = clock();
//copy host data to memory
gpuErrchk(cudaMemcpy(dA, hA, size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(dB, hB, size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(dC, hC, size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(dD, hD, size, cudaMemcpyHostToDevice));
//record start of device computation
// add array in device
vecAdd<<<128,128>>>(dA, dB, dC, dD, size_of_array);
gpuErrchk(cudaDeviceSynchronize());
//record end of device computation
device_end = clock();
//copy data from device to host
gpuErrchk(cudaMemcpy(hD, dD, size, cudaMemcpyDeviceToHost));
double host_time, device_time;
host_time = (double)((double)(host_end - host_begin)/(CLOCKS_PER_SEC));
device_time = (double)((double)(device_end - device_begin)/(CLOCKS_PER_SEC));
//print the time of host and device computation
printf("Host computation time: %f\n",host_time);
printf("Device computation time: %f\n",device_time);
//display the devation of device and host result
float sum = 0;
for(int i=0; i< size_of_array; ++i)
{
sum += hE[i] - hD[i];
}
printf("The deviation of host and device result is %f\n",sum);
//free host memory
free(hA);
free(hB);
free(hC);
free(hD);
free(hE);
//free device memory
gpuErrchk(cudaFree(dA));
gpuErrchk(cudaFree(dB));
gpuErrchk(cudaFree(dC));
gpuErrchk(cudaFree(dD));
}
//random number generator
float get_random()
{
return rand() % 100 + 1;
} | // Date March 28 2029
//Programer: Hemanta Bhattarai
// Progarm : To add two arrays and compare computation time in host and device
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h> //for random numbers
#include <time.h>
#include <sys/time.h>
#define gpuErrchk(ans){ gpuAssert((ans),__FILE__, __LINE__);}
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
if(code != hipSuccess)
{
fprintf(stderr, "GPUassert : %s %s %d\n", hipGetErrorString(code), file, line);
if(abort) exit(code);
}
}
// device kernal
__global__ void vecAdd(float *A, float *B, float *C, float *D, int array_size)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
while(i < array_size)
{
D[i] = A[i] + B[i] + C[i];
i += blockDim.x * gridDim.x; // each iteration will move the block-grid to access other element in matrix
}
}
int main()
{
// host function definition
float get_random();
//variable definition
float *hA, *hB, *hC, *hD, *dA, *dB, *dC;
float *dD, *hE;
float size_of_array;
//define size of array
printf("Enter the size of array");
scanf("%f",&size_of_array);
float size = sizeof(int) * size_of_array;
//memory allocation in host
hA = (float*)malloc(size);
hB = (float*)malloc(size);
hC = (float*)malloc(size);
hD = (float*)malloc(size);
hE = (float*)malloc(size);
//memory allocation in device
gpuErrchk(hipMalloc((void**)&dA,size));
gpuErrchk(hipMalloc((void**)&dB,size));
gpuErrchk(hipMalloc((void**)&dC,size));
gpuErrchk(hipMalloc((void**)&dD,size));
//array initilization
for(int i=0; i<size_of_array; ++i) hA[i] = get_random();
for(int i=0; i<size_of_array; ++i) hB[i] = get_random();
for(int i=0; i<size_of_array; ++i) hC[i] = get_random();
clock_t host_begin, host_end;
//record begin of host computation
host_begin = clock();
//add vectors in host
for(int i=0; i<size_of_array; ++i) hE[i] = hA[i] + hB[i] + hC[i];
//record end of host computation
host_end = clock();
clock_t device_begin, device_end;
//record of device computation
device_begin = clock();
//copy host data to memory
gpuErrchk(hipMemcpy(dA, hA, size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(dB, hB, size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(dC, hC, size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(dD, hD, size, hipMemcpyHostToDevice));
//record start of device computation
// add array in device
vecAdd<<<128,128>>>(dA, dB, dC, dD, size_of_array);
gpuErrchk(hipDeviceSynchronize());
//record end of device computation
device_end = clock();
//copy data from device to host
gpuErrchk(hipMemcpy(hD, dD, size, hipMemcpyDeviceToHost));
double host_time, device_time;
host_time = (double)((double)(host_end - host_begin)/(CLOCKS_PER_SEC));
device_time = (double)((double)(device_end - device_begin)/(CLOCKS_PER_SEC));
//print the time of host and device computation
printf("Host computation time: %f\n",host_time);
printf("Device computation time: %f\n",device_time);
//display the devation of device and host result
float sum = 0;
for(int i=0; i< size_of_array; ++i)
{
sum += hE[i] - hD[i];
}
printf("The deviation of host and device result is %f\n",sum);
//free host memory
free(hA);
free(hB);
free(hC);
free(hD);
free(hE);
//free device memory
gpuErrchk(hipFree(dA));
gpuErrchk(hipFree(dB));
gpuErrchk(hipFree(dC));
gpuErrchk(hipFree(dD));
}
//random number generator
float get_random()
{
return rand() % 100 + 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Date March 28 2029
//Programer: Hemanta Bhattarai
// Progarm : To add two arrays and compare computation time in host and device
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h> //for random numbers
#include <time.h>
#include <sys/time.h>
#define gpuErrchk(ans){ gpuAssert((ans),__FILE__, __LINE__);}
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
if(code != hipSuccess)
{
fprintf(stderr, "GPUassert : %s %s %d\n", hipGetErrorString(code), file, line);
if(abort) exit(code);
}
}
// device kernal
__global__ void vecAdd(float *A, float *B, float *C, float *D, int array_size)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
while(i < array_size)
{
D[i] = A[i] + B[i] + C[i];
i += blockDim.x * gridDim.x; // each iteration will move the block-grid to access other element in matrix
}
}
int main()
{
// host function definition
float get_random();
//variable definition
float *hA, *hB, *hC, *hD, *dA, *dB, *dC;
float *dD, *hE;
float size_of_array;
//define size of array
printf("Enter the size of array");
scanf("%f",&size_of_array);
float size = sizeof(int) * size_of_array;
//memory allocation in host
hA = (float*)malloc(size);
hB = (float*)malloc(size);
hC = (float*)malloc(size);
hD = (float*)malloc(size);
hE = (float*)malloc(size);
//memory allocation in device
gpuErrchk(hipMalloc((void**)&dA,size));
gpuErrchk(hipMalloc((void**)&dB,size));
gpuErrchk(hipMalloc((void**)&dC,size));
gpuErrchk(hipMalloc((void**)&dD,size));
//array initilization
for(int i=0; i<size_of_array; ++i) hA[i] = get_random();
for(int i=0; i<size_of_array; ++i) hB[i] = get_random();
for(int i=0; i<size_of_array; ++i) hC[i] = get_random();
clock_t host_begin, host_end;
//record begin of host computation
host_begin = clock();
//add vectors in host
for(int i=0; i<size_of_array; ++i) hE[i] = hA[i] + hB[i] + hC[i];
//record end of host computation
host_end = clock();
clock_t device_begin, device_end;
//record of device computation
device_begin = clock();
//copy host data to memory
gpuErrchk(hipMemcpy(dA, hA, size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(dB, hB, size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(dC, hC, size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(dD, hD, size, hipMemcpyHostToDevice));
//record start of device computation
// add array in device
vecAdd<<<128,128>>>(dA, dB, dC, dD, size_of_array);
gpuErrchk(hipDeviceSynchronize());
//record end of device computation
device_end = clock();
//copy data from device to host
gpuErrchk(hipMemcpy(hD, dD, size, hipMemcpyDeviceToHost));
double host_time, device_time;
host_time = (double)((double)(host_end - host_begin)/(CLOCKS_PER_SEC));
device_time = (double)((double)(device_end - device_begin)/(CLOCKS_PER_SEC));
//print the time of host and device computation
printf("Host computation time: %f\n",host_time);
printf("Device computation time: %f\n",device_time);
//display the devation of device and host result
float sum = 0;
for(int i=0; i< size_of_array; ++i)
{
sum += hE[i] - hD[i];
}
printf("The deviation of host and device result is %f\n",sum);
//free host memory
free(hA);
free(hB);
free(hC);
free(hD);
free(hE);
//free device memory
gpuErrchk(hipFree(dA));
gpuErrchk(hipFree(dB));
gpuErrchk(hipFree(dC));
gpuErrchk(hipFree(dD));
}
//random number generator
float get_random()
{
return rand() % 100 + 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_S_i
.globl _Z6vecAddPfS_S_S_i
.p2align 8
.type _Z6vecAddPfS_S_S_i,@function
_Z6vecAddPfS_S_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s12, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s13
s_mov_b32 s2, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
global_load_b32 v5, v[8:9], off
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v2, s0, s10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v4
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v5
s_or_b32 s2, vcc_lo, s2
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_S_i, .Lfunc_end0-_Z6vecAddPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Date March 28 2029
//Programer: Hemanta Bhattarai
// Progarm : To add two arrays and compare computation time in host and device
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h> //for random numbers
#include <time.h>
#include <sys/time.h>
#define gpuErrchk(ans){ gpuAssert((ans),__FILE__, __LINE__);}
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
if(code != hipSuccess)
{
fprintf(stderr, "GPUassert : %s %s %d\n", hipGetErrorString(code), file, line);
if(abort) exit(code);
}
}
// device kernal
__global__ void vecAdd(float *A, float *B, float *C, float *D, int array_size)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
while(i < array_size)
{
D[i] = A[i] + B[i] + C[i];
i += blockDim.x * gridDim.x; // each iteration will move the block-grid to access other element in matrix
}
}
int main()
{
// host function definition
float get_random();
//variable definition
float *hA, *hB, *hC, *hD, *dA, *dB, *dC;
float *dD, *hE;
float size_of_array;
//define size of array
printf("Enter the size of array");
scanf("%f",&size_of_array);
float size = sizeof(int) * size_of_array;
//memory allocation in host
hA = (float*)malloc(size);
hB = (float*)malloc(size);
hC = (float*)malloc(size);
hD = (float*)malloc(size);
hE = (float*)malloc(size);
//memory allocation in device
gpuErrchk(hipMalloc((void**)&dA,size));
gpuErrchk(hipMalloc((void**)&dB,size));
gpuErrchk(hipMalloc((void**)&dC,size));
gpuErrchk(hipMalloc((void**)&dD,size));
//array initilization
for(int i=0; i<size_of_array; ++i) hA[i] = get_random();
for(int i=0; i<size_of_array; ++i) hB[i] = get_random();
for(int i=0; i<size_of_array; ++i) hC[i] = get_random();
clock_t host_begin, host_end;
//record begin of host computation
host_begin = clock();
//add vectors in host
for(int i=0; i<size_of_array; ++i) hE[i] = hA[i] + hB[i] + hC[i];
//record end of host computation
host_end = clock();
clock_t device_begin, device_end;
//record of device computation
device_begin = clock();
//copy host data to memory
gpuErrchk(hipMemcpy(dA, hA, size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(dB, hB, size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(dC, hC, size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(dD, hD, size, hipMemcpyHostToDevice));
//record start of device computation
// add array in device
vecAdd<<<128,128>>>(dA, dB, dC, dD, size_of_array);
gpuErrchk(hipDeviceSynchronize());
//record end of device computation
device_end = clock();
//copy data from device to host
gpuErrchk(hipMemcpy(hD, dD, size, hipMemcpyDeviceToHost));
double host_time, device_time;
host_time = (double)((double)(host_end - host_begin)/(CLOCKS_PER_SEC));
device_time = (double)((double)(device_end - device_begin)/(CLOCKS_PER_SEC));
//print the time of host and device computation
printf("Host computation time: %f\n",host_time);
printf("Device computation time: %f\n",device_time);
//display the devation of device and host result
float sum = 0;
for(int i=0; i< size_of_array; ++i)
{
sum += hE[i] - hD[i];
}
printf("The deviation of host and device result is %f\n",sum);
//free host memory
free(hA);
free(hB);
free(hC);
free(hD);
free(hE);
//free device memory
gpuErrchk(hipFree(dA));
gpuErrchk(hipFree(dB));
gpuErrchk(hipFree(dC));
gpuErrchk(hipFree(dD));
}
//random number generator
float get_random()
{
return rand() % 100 + 1;
} | .text
.file "add_vector_very_large.hip"
.globl _Z21__device_stub__vecAddPfS_S_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_S_i,@function
_Z21__device_stub__vecAddPfS_S_S_i: # @_Z21__device_stub__vecAddPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecAddPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x40800000 # float 4
.LCPI1_1:
.long 0x5f000000 # float 9.22337203E+18
.LCPI1_3:
.long 0x00000000 # float 0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss .LCPI1_0(%rip), %xmm0
cvttss2si %xmm0, %rax
movq %rax, %rcx
sarq $63, %rcx
subss .LCPI1_1(%rip), %xmm0
cvttss2si %xmm0, %rbp
andq %rcx, %rbp
orq %rax, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %rbp, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %rbp, %rdi
callq malloc
movq %rax, %r12
movq %rbp, %rdi
callq malloc
movq %rax, %r13
leaq 48(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit68
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit70
movq %r12, 24(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_47
# %bb.8: # %_Z9gpuAssert10hipError_tPKcib.exit72.preheader
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jbe .LBB1_11
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit72.preheader126
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_10: # %_Z9gpuAssert10hipError_tPKcib.exit72
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss 4(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
ja .LBB1_10
.LBB1_11: # %.preheader96
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI1_3(%rip), %xmm0
jbe .LBB1_14
# %bb.12: # %.lr.ph99.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_13: # %.lr.ph99
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss 4(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
ja .LBB1_13
.LBB1_14: # %.preheader
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jbe .LBB1_17
# %bb.15: # %.lr.ph101.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_16: # %.lr.ph101
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss 4(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
ja .LBB1_16
.LBB1_17: # %._crit_edge
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI1_3(%rip), %xmm0
jbe .LBB1_20
# %bb.18: # %.lr.ph104.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_19: # %.lr.ph104
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm1
addss (%r15,%rax,4), %xmm1
movss %xmm1, (%r13,%rax,4)
incq %rax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
ucomiss %xmm1, %xmm0
ja .LBB1_19
.LBB1_20: # %._crit_edge105
callq clock
movq %rax, 64(%rsp) # 8-byte Spill
callq clock
movq %rax, 72(%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
movq 24(%rsp), %r12 # 8-byte Reload
jne .LBB1_21
# %bb.22: # %_Z9gpuAssert10hipError_tPKcib.exit74
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_23
# %bb.24: # %_Z9gpuAssert10hipError_tPKcib.exit76
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_25
# %bb.26: # %_Z9gpuAssert10hipError_tPKcib.exit78
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_27
# %bb.28: # %_Z9gpuAssert10hipError_tPKcib.exit80
movabsq $4294967424, %rdi # imm = 0x100000080
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_30
# %bb.29:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
cvttss2si 4(%rsp), %esi
movq 8(%rsp), %rdi
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq %rdi, 128(%rsp)
movl %esi, 60(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 60(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z6vecAddPfS_S_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_30:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_31
# %bb.32: # %_Z9gpuAssert10hipError_tPKcib.exit82
callq clock
movq %rax, %r12
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_33
# %bb.34: # %_Z9gpuAssert10hipError_tPKcib.exit84
movq 64(%rsp), %rax # 8-byte Reload
subq 16(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd .LCPI1_2(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
subq 72(%rsp), %r12 # 8-byte Folded Reload
cvtsi2sd %r12, %xmm2
divsd %xmm1, %xmm2
movsd %xmm2, 16(%rsp) # 8-byte Spill
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.L.str.4, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movss 4(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
xorpd %xmm2, %xmm2
ucomiss %xmm2, %xmm1
movq 24(%rsp), %r12 # 8-byte Reload
jbe .LBB1_38
# %bb.35: # %.lr.ph108.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_36: # %.lr.ph108
# =>This Inner Loop Header: Depth=1
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%r12,%rax,4), %xmm0
incq %rax
xorps %xmm3, %xmm3
cvtsi2ss %eax, %xmm3
addss %xmm0, %xmm2
ucomiss %xmm3, %xmm1
ja .LBB1_36
# %bb.37: # %._crit_edge109.loopexit
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
.LBB1_38: # %._crit_edge109
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_39
# %bb.40: # %_Z9gpuAssert10hipError_tPKcib.exit86
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_41
# %bb.42: # %_Z9gpuAssert10hipError_tPKcib.exit88
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_43
# %bb.44: # %_Z9gpuAssert10hipError_tPKcib.exit90
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_45
# %bb.46: # %_Z9gpuAssert10hipError_tPKcib.exit92
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $70, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $71, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %r8d
jmp .LBB1_2
.LBB1_47:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $73, %r8d
jmp .LBB1_2
.LBB1_21:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $102, %r8d
jmp .LBB1_2
.LBB1_23:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $103, %r8d
jmp .LBB1_2
.LBB1_25:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $104, %r8d
jmp .LBB1_2
.LBB1_27:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $105, %r8d
jmp .LBB1_2
.LBB1_31:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $111, %r8d
jmp .LBB1_2
.LBB1_33:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $118, %r8d
jmp .LBB1_2
.LBB1_39:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $144, %r8d
jmp .LBB1_2
.LBB1_41:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $145, %r8d
jmp .LBB1_2
.LBB1_43:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $146, %r8d
jmp .LBB1_2
.LBB1_45:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $147, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z10get_randomv # -- Begin function _Z10get_randomv
.p2align 4, 0x90
.type _Z10get_randomv,@function
_Z10get_randomv: # @_Z10get_randomv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
cvtsi2ss %eax, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10get_randomv, .Lfunc_end2-_Z10get_randomv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_S_i,@object # @_Z6vecAddPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_S_i
.p2align 3, 0x0
_Z6vecAddPfS_S_S_i:
.quad _Z21__device_stub__vecAddPfS_S_S_i
.size _Z6vecAddPfS_S_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the size of array"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Hemanta-Bhattarai/Self_Learning/master/CUDA/vector_operations/add_vector_very_large.hip"
.size .L.str.2, 145
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Host computation time: %f\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device computation time: %f\n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "The deviation of host and device result is %f\n"
.size .L.str.5, 47
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPUassert : %s %s %d\n"
.size .L.str.6, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IMAD.WIDE R6, R0.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x0c0fe400078e0209 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fe200078e0209 */
/*00f0*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */
/* 0x000fca0000000f00 */
/*0100*/ IMAD R0, R13, c[0x0][0xc], R0 ; /* 0x000003000d007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0120*/ FADD R10, R4, R3 ; /* 0x00000003040a7221 */
/* 0x004fc80000000000 */
/*0130*/ FADD R11, R10, R7 ; /* 0x000000070a0b7221 */
/* 0x008fca0000000000 */
/*0140*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e6000c101904 */
/*0150*/ @!P0 BRA 0x70 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_S_i
.globl _Z6vecAddPfS_S_S_i
.p2align 8
.type _Z6vecAddPfS_S_S_i,@function
_Z6vecAddPfS_S_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s12, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s13
s_mov_b32 s2, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
global_load_b32 v5, v[8:9], off
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v2, s0, s10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v4
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v5
s_or_b32 s2, vcc_lo, s2
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_S_i, .Lfunc_end0-_Z6vecAddPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001173c7_00000000-6_add_vector_very_large.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert : %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z10get_randomv
.type _Z10get_randomv, @function
_Z10get_randomv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10get_randomv, .-_Z10get_randomv
.globl _Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i
.type _Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i, @function
_Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6vecAddPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i, .-_Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i
.globl _Z6vecAddPfS_S_S_i
.type _Z6vecAddPfS_S_S_i, @function
_Z6vecAddPfS_S_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6vecAddPfS_S_S_i, .-_Z6vecAddPfS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Enter the size of array"
.LC3:
.string "%f"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Hemanta-Bhattarai/Self_Learning/master/CUDA/vector_operations/add_vector_very_large.cu"
.section .rodata.str1.1
.LC8:
.string "Host computation time: %f\n"
.LC9:
.string "Device computation time: %f\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "The deviation of host and device result is %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 60(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movss .LC4(%rip), %xmm0
mulss 60(%rsp), %xmm0
comiss .LC5(%rip), %xmm0
jnb .L22
cvttss2siq %xmm0, %r15
.L23:
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r15, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
leaq 64(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $70, %edx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 72(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $71, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 80(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $72, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 88(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $73, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ebx
movss 60(%rsp), %xmm1
pxor %xmm0, %xmm0
comiss %xmm0, %xmm1
jbe .L29
.L26:
call _Z10get_randomv
movss %xmm0, -4(%r13,%rbx,4)
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
movss 60(%rsp), %xmm0
addq $1, %rbx
comiss %xmm1, %xmm0
ja .L26
pxor %xmm1, %xmm1
comiss %xmm1, %xmm0
jbe .L29
movl $1, %ebx
.L28:
call _Z10get_randomv
movss %xmm0, -4(%r12,%rbx,4)
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
movss 60(%rsp), %xmm0
addq $1, %rbx
comiss %xmm1, %xmm0
ja .L28
pxor %xmm1, %xmm1
comiss %xmm1, %xmm0
jbe .L29
movl $1, %ebx
.L31:
call _Z10get_randomv
movss %xmm0, -4(%rbp,%rbx,4)
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
addq $1, %rbx
movss 60(%rsp), %xmm1
comiss %xmm0, %xmm1
ja .L31
.L29:
call clock@PLT
movq %rax, 16(%rsp)
movss 60(%rsp), %xmm1
movl $1, %eax
pxor %xmm0, %xmm0
comiss %xmm0, %xmm1
jbe .L32
.L34:
movss -4(%r13,%rax,4), %xmm0
addss -4(%r12,%rax,4), %xmm0
addss -4(%rbp,%rax,4), %xmm0
movss %xmm0, -4(%r14,%rax,4)
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addq $1, %rax
comiss %xmm0, %xmm1
ja .L34
.L32:
call clock@PLT
movq %rax, 24(%rsp)
call clock@PLT
movq %rax, 32(%rsp)
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $102, %edx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $103, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $104, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $105, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $128, 108(%rsp)
movl $1, 112(%rsp)
movl $128, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L35:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $111, %edx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call clock@PLT
movq %rax, 40(%rsp)
movl $2, %ecx
movq %r15, %rdx
movq 88(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $118, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC7(%rip), %xmm1
divsd %xmm1, %xmm0
movq %xmm0, %rbx
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd %xmm1, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 60(%rsp), %xmm2
movl $1, %eax
pxor %xmm0, %xmm0
comiss %xmm0, %xmm2
jbe .L54
.L38:
movss -4(%r14,%rax,4), %xmm1
movq 8(%rsp), %rdx
subss -4(%rdx,%rax,4), %xmm1
addss %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
addq $1, %rax
comiss %xmm1, %xmm2
ja .L38
.L36:
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $144, %edx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $145, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 80(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $146, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 88(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $147, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L57
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
subss .LC5(%rip), %xmm0
cvttss2siq %xmm0, %r15
btcq $63, %r15
jmp .L23
.L56:
cvttss2sil 60(%rsp), %r8d
movq 88(%rsp), %rcx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z32__device_stub__Z6vecAddPfS_S_S_iPfS_S_S_i
jmp .L35
.L54:
pxor %xmm0, %xmm0
jmp .L36
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z6vecAddPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1082130432
.align 4
.LC5:
.long 1593835520
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_vector_very_large.hip"
.globl _Z21__device_stub__vecAddPfS_S_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_S_i,@function
_Z21__device_stub__vecAddPfS_S_S_i: # @_Z21__device_stub__vecAddPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecAddPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x40800000 # float 4
.LCPI1_1:
.long 0x5f000000 # float 9.22337203E+18
.LCPI1_3:
.long 0x00000000 # float 0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss .LCPI1_0(%rip), %xmm0
cvttss2si %xmm0, %rax
movq %rax, %rcx
sarq $63, %rcx
subss .LCPI1_1(%rip), %xmm0
cvttss2si %xmm0, %rbp
andq %rcx, %rbp
orq %rax, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %rbp, %rdi
callq malloc
movq %rax, %r14
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %rbp, %rdi
callq malloc
movq %rax, %r12
movq %rbp, %rdi
callq malloc
movq %rax, %r13
leaq 48(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit68
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit70
movq %r12, 24(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_47
# %bb.8: # %_Z9gpuAssert10hipError_tPKcib.exit72.preheader
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jbe .LBB1_11
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit72.preheader126
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_10: # %_Z9gpuAssert10hipError_tPKcib.exit72
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss 4(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
ja .LBB1_10
.LBB1_11: # %.preheader96
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI1_3(%rip), %xmm0
jbe .LBB1_14
# %bb.12: # %.lr.ph99.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_13: # %.lr.ph99
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss 4(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
ja .LBB1_13
.LBB1_14: # %.preheader
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jbe .LBB1_17
# %bb.15: # %.lr.ph101.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_16: # %.lr.ph101
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss 4(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
ja .LBB1_16
.LBB1_17: # %._crit_edge
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI1_3(%rip), %xmm0
jbe .LBB1_20
# %bb.18: # %.lr.ph104.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_19: # %.lr.ph104
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm1
addss (%r15,%rax,4), %xmm1
movss %xmm1, (%r13,%rax,4)
incq %rax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
ucomiss %xmm1, %xmm0
ja .LBB1_19
.LBB1_20: # %._crit_edge105
callq clock
movq %rax, 64(%rsp) # 8-byte Spill
callq clock
movq %rax, 72(%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
movq 24(%rsp), %r12 # 8-byte Reload
jne .LBB1_21
# %bb.22: # %_Z9gpuAssert10hipError_tPKcib.exit74
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_23
# %bb.24: # %_Z9gpuAssert10hipError_tPKcib.exit76
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_25
# %bb.26: # %_Z9gpuAssert10hipError_tPKcib.exit78
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_27
# %bb.28: # %_Z9gpuAssert10hipError_tPKcib.exit80
movabsq $4294967424, %rdi # imm = 0x100000080
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_30
# %bb.29:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
cvttss2si 4(%rsp), %esi
movq 8(%rsp), %rdi
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq %rdi, 128(%rsp)
movl %esi, 60(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 60(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z6vecAddPfS_S_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_30:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_31
# %bb.32: # %_Z9gpuAssert10hipError_tPKcib.exit82
callq clock
movq %rax, %r12
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_33
# %bb.34: # %_Z9gpuAssert10hipError_tPKcib.exit84
movq 64(%rsp), %rax # 8-byte Reload
subq 16(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd .LCPI1_2(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
subq 72(%rsp), %r12 # 8-byte Folded Reload
cvtsi2sd %r12, %xmm2
divsd %xmm1, %xmm2
movsd %xmm2, 16(%rsp) # 8-byte Spill
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.L.str.4, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movss 4(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
xorpd %xmm2, %xmm2
ucomiss %xmm2, %xmm1
movq 24(%rsp), %r12 # 8-byte Reload
jbe .LBB1_38
# %bb.35: # %.lr.ph108.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_36: # %.lr.ph108
# =>This Inner Loop Header: Depth=1
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%r12,%rax,4), %xmm0
incq %rax
xorps %xmm3, %xmm3
cvtsi2ss %eax, %xmm3
addss %xmm0, %xmm2
ucomiss %xmm3, %xmm1
ja .LBB1_36
# %bb.37: # %._crit_edge109.loopexit
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
.LBB1_38: # %._crit_edge109
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_39
# %bb.40: # %_Z9gpuAssert10hipError_tPKcib.exit86
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_41
# %bb.42: # %_Z9gpuAssert10hipError_tPKcib.exit88
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_43
# %bb.44: # %_Z9gpuAssert10hipError_tPKcib.exit90
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_45
# %bb.46: # %_Z9gpuAssert10hipError_tPKcib.exit92
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $70, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $71, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %r8d
jmp .LBB1_2
.LBB1_47:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $73, %r8d
jmp .LBB1_2
.LBB1_21:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $102, %r8d
jmp .LBB1_2
.LBB1_23:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $103, %r8d
jmp .LBB1_2
.LBB1_25:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $104, %r8d
jmp .LBB1_2
.LBB1_27:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $105, %r8d
jmp .LBB1_2
.LBB1_31:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $111, %r8d
jmp .LBB1_2
.LBB1_33:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $118, %r8d
jmp .LBB1_2
.LBB1_39:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $144, %r8d
jmp .LBB1_2
.LBB1_41:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $145, %r8d
jmp .LBB1_2
.LBB1_43:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $146, %r8d
jmp .LBB1_2
.LBB1_45:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $147, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z10get_randomv # -- Begin function _Z10get_randomv
.p2align 4, 0x90
.type _Z10get_randomv,@function
_Z10get_randomv: # @_Z10get_randomv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
cvtsi2ss %eax, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10get_randomv, .Lfunc_end2-_Z10get_randomv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_S_i,@object # @_Z6vecAddPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_S_i
.p2align 3, 0x0
_Z6vecAddPfS_S_S_i:
.quad _Z21__device_stub__vecAddPfS_S_S_i
.size _Z6vecAddPfS_S_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the size of array"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Hemanta-Bhattarai/Self_Learning/master/CUDA/vector_operations/add_vector_very_large.hip"
.size .L.str.2, 145
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Host computation time: %f\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device computation time: %f\n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "The deviation of host and device result is %f\n"
.size .L.str.5, 47
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPUassert : %s %s %d\n"
.size .L.str.6, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <time.h>
#define LENGTH 10000
using namespace std;
struct aos{
int a;
int b;
int c;
};
__global__ void vector_add(aos *arr){
int i = threadIdx.x ;
if (i < LENGTH)
arr[i].c = arr[i].a + arr[i].b; // read
}
__host__ void vector_add_cpu(float a[], float b[], float *c){
for(int i=0 ; i< LENGTH ; i++){
c[i] = a[i] + b[i];
// std::cout << c[i] << std::endl;
}
}
int main(){
aos *h_aos;
aos *d_aos;
h_aos = new aos [LENGTH];
for(int i=0 ; i< LENGTH; i++){
h_aos[i].a = i;
h_aos[i].b = i;
}
cudaMalloc((void**)&d_aos, LENGTH*sizeof(aos));
cudaMemcpy(d_aos, h_aos, LENGTH*sizeof(aos), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
float total_time = 0.0;
// for(int k=0 ; k< 1000 ; k++){
// cudaEventRecord(start);
vector_add<<<LENGTH/128, 128>>>(d_aos);
cudaDeviceSynchronize();
// cudaEventRecord(stop);
cudaMemcpy(h_aos, d_aos, LENGTH*sizeof(aos), cudaMemcpyDeviceToHost);
// cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
total_time += milliseconds;
// }
std::cout << "Time taken : " << milliseconds << " Avg time : " << total_time << std::endl;
for(int i=0; i<10 ;i++){
cout << h_aos[i].c << endl;
}
} | code for sm_80
Function : _Z10vector_addP3aos
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R2, 0x270f, PT ; /* 0x0000270f0200780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R3, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff037435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*0090*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R2.64+0x8], R5 ; /* 0x0000080502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <time.h>
#define LENGTH 10000
using namespace std;
struct aos{
int a;
int b;
int c;
};
__global__ void vector_add(aos *arr){
int i = threadIdx.x ;
if (i < LENGTH)
arr[i].c = arr[i].a + arr[i].b; // read
}
__host__ void vector_add_cpu(float a[], float b[], float *c){
for(int i=0 ; i< LENGTH ; i++){
c[i] = a[i] + b[i];
// std::cout << c[i] << std::endl;
}
}
int main(){
aos *h_aos;
aos *d_aos;
h_aos = new aos [LENGTH];
for(int i=0 ; i< LENGTH; i++){
h_aos[i].a = i;
h_aos[i].b = i;
}
cudaMalloc((void**)&d_aos, LENGTH*sizeof(aos));
cudaMemcpy(d_aos, h_aos, LENGTH*sizeof(aos), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
float total_time = 0.0;
// for(int k=0 ; k< 1000 ; k++){
// cudaEventRecord(start);
vector_add<<<LENGTH/128, 128>>>(d_aos);
cudaDeviceSynchronize();
// cudaEventRecord(stop);
cudaMemcpy(h_aos, d_aos, LENGTH*sizeof(aos), cudaMemcpyDeviceToHost);
// cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
total_time += milliseconds;
// }
std::cout << "Time taken : " << milliseconds << " Avg time : " << total_time << std::endl;
for(int i=0; i<10 ;i++){
cout << h_aos[i].c << endl;
}
} | .file "tmpxft_00023d51_00000000-6_aos.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14vector_add_cpuPfS_S_
.type _Z14vector_add_cpuPfS_S_, @function
_Z14vector_add_cpuPfS_S_:
.LFB3669:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $40000, %rax
jne .L4
ret
.cfi_endproc
.LFE3669:
.size _Z14vector_add_cpuPfS_S_, .-_Z14vector_add_cpuPfS_S_
.globl _Z33__device_stub__Z10vector_addP3aosP3aos
.type _Z33__device_stub__Z10vector_addP3aosP3aos, @function
_Z33__device_stub__Z10vector_addP3aosP3aos:
.LFB3695:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10vector_addP3aos(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z33__device_stub__Z10vector_addP3aosP3aos, .-_Z33__device_stub__Z10vector_addP3aosP3aos
.globl _Z10vector_addP3aos
.type _Z10vector_addP3aos, @function
_Z10vector_addP3aos:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10vector_addP3aosP3aos
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z10vector_addP3aos, .-_Z10vector_addP3aos
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Time taken : "
.LC2:
.string " Avg time : "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $120000, %edi
call _Znam@PLT
movq %rax, %r12
movq %rax, %rdx
movl $0, %eax
.L15:
movl %eax, (%rdx)
movl %eax, 4(%rdx)
addl $1, %eax
addq $12, %rdx
cmpl $10000, %eax
jne .L15
leaq 24(%rsp), %rdi
movl $120000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $120000, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 20(%rsp)
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $78, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L16:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $120000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 20(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
addss 20(%rsp), %xmm0
movss %xmm0, 12(%rsp)
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%r12), %rbp
subq $-128, %r12
leaq _ZSt4cout(%rip), %r13
jmp .L21
.L26:
movq 24(%rsp), %rdi
call _Z33__device_stub__Z10vector_addP3aosP3aos
jmp .L16
.L29:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L27
call _ZSt16__throw_bad_castv@PLT
.L27:
call __stack_chk_fail@PLT
.L19:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
.L20:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $12, %rbp
cmpq %r12, %rbp
je .L28
.L21:
movl 0(%rbp), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L29
cmpb $0, 56(%r14)
je .L19
movzbl 67(%r14), %esi
jmp .L20
.L28:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10vector_addP3aos"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addP3aos(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <time.h>
#define LENGTH 10000
using namespace std;
struct aos{
int a;
int b;
int c;
};
__global__ void vector_add(aos *arr){
int i = threadIdx.x ;
if (i < LENGTH)
arr[i].c = arr[i].a + arr[i].b; // read
}
__host__ void vector_add_cpu(float a[], float b[], float *c){
for(int i=0 ; i< LENGTH ; i++){
c[i] = a[i] + b[i];
// std::cout << c[i] << std::endl;
}
}
int main(){
aos *h_aos;
aos *d_aos;
h_aos = new aos [LENGTH];
for(int i=0 ; i< LENGTH; i++){
h_aos[i].a = i;
h_aos[i].b = i;
}
cudaMalloc((void**)&d_aos, LENGTH*sizeof(aos));
cudaMemcpy(d_aos, h_aos, LENGTH*sizeof(aos), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
float total_time = 0.0;
// for(int k=0 ; k< 1000 ; k++){
// cudaEventRecord(start);
vector_add<<<LENGTH/128, 128>>>(d_aos);
cudaDeviceSynchronize();
// cudaEventRecord(stop);
cudaMemcpy(h_aos, d_aos, LENGTH*sizeof(aos), cudaMemcpyDeviceToHost);
// cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
total_time += milliseconds;
// }
std::cout << "Time taken : " << milliseconds << " Avg time : " << total_time << std::endl;
for(int i=0; i<10 ;i++){
cout << h_aos[i].c << endl;
}
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <time.h>
#define LENGTH 10000
using namespace std;
struct aos{
int a;
int b;
int c;
};
__global__ void vector_add(aos *arr){
int i = threadIdx.x ;
if (i < LENGTH)
arr[i].c = arr[i].a + arr[i].b; // read
}
__host__ void vector_add_cpu(float a[], float b[], float *c){
for(int i=0 ; i< LENGTH ; i++){
c[i] = a[i] + b[i];
// std::cout << c[i] << std::endl;
}
}
int main(){
aos *h_aos;
aos *d_aos;
h_aos = new aos [LENGTH];
for(int i=0 ; i< LENGTH; i++){
h_aos[i].a = i;
h_aos[i].b = i;
}
hipMalloc((void**)&d_aos, LENGTH*sizeof(aos));
hipMemcpy(d_aos, h_aos, LENGTH*sizeof(aos), hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
float total_time = 0.0;
// for(int k=0 ; k< 1000 ; k++){
// cudaEventRecord(start);
vector_add<<<LENGTH/128, 128>>>(d_aos);
hipDeviceSynchronize();
// cudaEventRecord(stop);
hipMemcpy(h_aos, d_aos, LENGTH*sizeof(aos), hipMemcpyDeviceToHost);
// cudaEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
total_time += milliseconds;
// }
std::cout << "Time taken : " << milliseconds << " Avg time : " << total_time << std::endl;
for(int i=0; i<10 ;i++){
cout << h_aos[i].c << endl;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <time.h>
#define LENGTH 10000
using namespace std;
struct aos{
int a;
int b;
int c;
};
__global__ void vector_add(aos *arr){
int i = threadIdx.x ;
if (i < LENGTH)
arr[i].c = arr[i].a + arr[i].b; // read
}
__host__ void vector_add_cpu(float a[], float b[], float *c){
for(int i=0 ; i< LENGTH ; i++){
c[i] = a[i] + b[i];
// std::cout << c[i] << std::endl;
}
}
int main(){
aos *h_aos;
aos *d_aos;
h_aos = new aos [LENGTH];
for(int i=0 ; i< LENGTH; i++){
h_aos[i].a = i;
h_aos[i].b = i;
}
hipMalloc((void**)&d_aos, LENGTH*sizeof(aos));
hipMemcpy(d_aos, h_aos, LENGTH*sizeof(aos), hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
float total_time = 0.0;
// for(int k=0 ; k< 1000 ; k++){
// cudaEventRecord(start);
vector_add<<<LENGTH/128, 128>>>(d_aos);
hipDeviceSynchronize();
// cudaEventRecord(stop);
hipMemcpy(h_aos, d_aos, LENGTH*sizeof(aos), hipMemcpyDeviceToHost);
// cudaEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
total_time += milliseconds;
// }
std::cout << "Time taken : " << milliseconds << " Avg time : " << total_time << std::endl;
for(int i=0; i<10 ;i++){
cout << h_aos[i].c << endl;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addP3aos
.globl _Z10vector_addP3aos
.p2align 8
.type _Z10vector_addP3aos,@function
_Z10vector_addP3aos:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, 12, s[0:1]
global_load_b64 v[3:4], v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v3
global_store_b32 v[1:2], v0, off offset:8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addP3aos
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addP3aos, .Lfunc_end0-_Z10vector_addP3aos
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addP3aos
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z10vector_addP3aos.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <time.h>
#define LENGTH 10000
using namespace std;
struct aos{
int a;
int b;
int c;
};
__global__ void vector_add(aos *arr){
int i = threadIdx.x ;
if (i < LENGTH)
arr[i].c = arr[i].a + arr[i].b; // read
}
__host__ void vector_add_cpu(float a[], float b[], float *c){
for(int i=0 ; i< LENGTH ; i++){
c[i] = a[i] + b[i];
// std::cout << c[i] << std::endl;
}
}
int main(){
aos *h_aos;
aos *d_aos;
h_aos = new aos [LENGTH];
for(int i=0 ; i< LENGTH; i++){
h_aos[i].a = i;
h_aos[i].b = i;
}
hipMalloc((void**)&d_aos, LENGTH*sizeof(aos));
hipMemcpy(d_aos, h_aos, LENGTH*sizeof(aos), hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
float total_time = 0.0;
// for(int k=0 ; k< 1000 ; k++){
// cudaEventRecord(start);
vector_add<<<LENGTH/128, 128>>>(d_aos);
hipDeviceSynchronize();
// cudaEventRecord(stop);
hipMemcpy(h_aos, d_aos, LENGTH*sizeof(aos), hipMemcpyDeviceToHost);
// cudaEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
total_time += milliseconds;
// }
std::cout << "Time taken : " << milliseconds << " Avg time : " << total_time << std::endl;
for(int i=0; i<10 ;i++){
cout << h_aos[i].c << endl;
}
} | .text
.file "aos.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__vector_addP3aos # -- Begin function _Z25__device_stub__vector_addP3aos
.p2align 4, 0x90
.type _Z25__device_stub__vector_addP3aos,@function
_Z25__device_stub__vector_addP3aos: # @_Z25__device_stub__vector_addP3aos
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10vector_addP3aos, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addP3aos, .Lfunc_end0-_Z25__device_stub__vector_addP3aos
.cfi_endproc
# -- End function
.globl _Z14vector_add_cpuPfS_S_ # -- Begin function _Z14vector_add_cpuPfS_S_
.p2align 4, 0x90
.type _Z14vector_add_cpuPfS_S_,@function
_Z14vector_add_cpuPfS_S_: # @_Z14vector_add_cpuPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z14vector_add_cpuPfS_S_, .Lfunc_end1-_Z14vector_add_cpuPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $120000, %edi # imm = 0x1D4C0
callq _Znam
movq %rax, %rbx
addq $4, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %ecx, -4(%rax)
movl %ecx, (%rax)
incq %rcx
addq $12, %rax
cmpq $10000, %rcx # imm = 0x2710
jne .LBB2_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $120000, %esi # imm = 0x1D4C0
callq hipMalloc
movq 16(%rsp), %rdi
movl $120000, %edx # imm = 0x1D4C0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
movl $0, 12(%rsp)
movabsq $4294967374, %rdi # imm = 0x10000004E
leaq 50(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10vector_addP3aos, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $120000, %edx # imm = 0x1D4C0
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 56(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
xorps %xmm0, %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 28(%rsp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r14, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_15
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_7
# %bb.6:
movzbl 67(%r14), %ecx
jmp .LBB2_8
.LBB2_7:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $8, %r15d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_9 Depth=1
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
# in Loop: Header=BB2_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $12, %r15
cmpq $128, %r15
je .LBB2_14
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_15
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
# in Loop: Header=BB2_9 Depth=1
cmpb $0, 56(%r14)
je .LBB2_12
# %bb.11: # in Loop: Header=BB2_9 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB2_13
.LBB2_14:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_15:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addP3aos, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addP3aos,@object # @_Z10vector_addP3aos
.section .rodata,"a",@progbits
.globl _Z10vector_addP3aos
.p2align 3, 0x0
_Z10vector_addP3aos:
.quad _Z25__device_stub__vector_addP3aos
.size _Z10vector_addP3aos, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time taken : "
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Avg time : "
.size .L.str.1, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addP3aos"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addP3aos
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addP3aos
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10vector_addP3aos
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R2, 0x270f, PT ; /* 0x0000270f0200780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R3, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff037435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*0090*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R2.64+0x8], R5 ; /* 0x0000080502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addP3aos
.globl _Z10vector_addP3aos
.p2align 8
.type _Z10vector_addP3aos,@function
_Z10vector_addP3aos:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v0, 12, s[0:1]
global_load_b64 v[3:4], v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v3
global_store_b32 v[1:2], v0, off offset:8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addP3aos
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addP3aos, .Lfunc_end0-_Z10vector_addP3aos
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addP3aos
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z10vector_addP3aos.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00023d51_00000000-6_aos.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14vector_add_cpuPfS_S_
.type _Z14vector_add_cpuPfS_S_, @function
_Z14vector_add_cpuPfS_S_:
.LFB3669:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $40000, %rax
jne .L4
ret
.cfi_endproc
.LFE3669:
.size _Z14vector_add_cpuPfS_S_, .-_Z14vector_add_cpuPfS_S_
.globl _Z33__device_stub__Z10vector_addP3aosP3aos
.type _Z33__device_stub__Z10vector_addP3aosP3aos, @function
_Z33__device_stub__Z10vector_addP3aosP3aos:
.LFB3695:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10vector_addP3aos(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z33__device_stub__Z10vector_addP3aosP3aos, .-_Z33__device_stub__Z10vector_addP3aosP3aos
.globl _Z10vector_addP3aos
.type _Z10vector_addP3aos, @function
_Z10vector_addP3aos:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10vector_addP3aosP3aos
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z10vector_addP3aos, .-_Z10vector_addP3aos
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Time taken : "
.LC2:
.string " Avg time : "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $120000, %edi
call _Znam@PLT
movq %rax, %r12
movq %rax, %rdx
movl $0, %eax
.L15:
movl %eax, (%rdx)
movl %eax, 4(%rdx)
addl $1, %eax
addq $12, %rdx
cmpl $10000, %eax
jne .L15
leaq 24(%rsp), %rdi
movl $120000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $120000, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 20(%rsp)
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $78, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L16:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $120000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 20(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
addss 20(%rsp), %xmm0
movss %xmm0, 12(%rsp)
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%r12), %rbp
subq $-128, %r12
leaq _ZSt4cout(%rip), %r13
jmp .L21
.L26:
movq 24(%rsp), %rdi
call _Z33__device_stub__Z10vector_addP3aosP3aos
jmp .L16
.L29:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L27
call _ZSt16__throw_bad_castv@PLT
.L27:
call __stack_chk_fail@PLT
.L19:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
.L20:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $12, %rbp
cmpq %r12, %rbp
je .L28
.L21:
movl 0(%rbp), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L29
cmpb $0, 56(%r14)
je .L19
movzbl 67(%r14), %esi
jmp .L20
.L28:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10vector_addP3aos"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addP3aos(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "aos.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__vector_addP3aos # -- Begin function _Z25__device_stub__vector_addP3aos
.p2align 4, 0x90
.type _Z25__device_stub__vector_addP3aos,@function
_Z25__device_stub__vector_addP3aos: # @_Z25__device_stub__vector_addP3aos
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10vector_addP3aos, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addP3aos, .Lfunc_end0-_Z25__device_stub__vector_addP3aos
.cfi_endproc
# -- End function
.globl _Z14vector_add_cpuPfS_S_ # -- Begin function _Z14vector_add_cpuPfS_S_
.p2align 4, 0x90
.type _Z14vector_add_cpuPfS_S_,@function
_Z14vector_add_cpuPfS_S_: # @_Z14vector_add_cpuPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z14vector_add_cpuPfS_S_, .Lfunc_end1-_Z14vector_add_cpuPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $120000, %edi # imm = 0x1D4C0
callq _Znam
movq %rax, %rbx
addq $4, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %ecx, -4(%rax)
movl %ecx, (%rax)
incq %rcx
addq $12, %rax
cmpq $10000, %rcx # imm = 0x2710
jne .LBB2_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $120000, %esi # imm = 0x1D4C0
callq hipMalloc
movq 16(%rsp), %rdi
movl $120000, %edx # imm = 0x1D4C0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
movl $0, 12(%rsp)
movabsq $4294967374, %rdi # imm = 0x10000004E
leaq 50(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10vector_addP3aos, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $120000, %edx # imm = 0x1D4C0
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 56(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
xorps %xmm0, %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 28(%rsp) # 4-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r14, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_15
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_7
# %bb.6:
movzbl 67(%r14), %ecx
jmp .LBB2_8
.LBB2_7:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $8, %r15d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_9 Depth=1
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
# in Loop: Header=BB2_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $12, %r15
cmpq $128, %r15
je .LBB2_14
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_15
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
# in Loop: Header=BB2_9 Depth=1
cmpb $0, 56(%r14)
je .LBB2_12
# %bb.11: # in Loop: Header=BB2_9 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB2_13
.LBB2_14:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_15:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addP3aos, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addP3aos,@object # @_Z10vector_addP3aos
.section .rodata,"a",@progbits
.globl _Z10vector_addP3aos
.p2align 3, 0x0
_Z10vector_addP3aos:
.quad _Z25__device_stub__vector_addP3aos
.size _Z10vector_addP3aos, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time taken : "
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Avg time : "
.size .L.str.1, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addP3aos"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addP3aos
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addP3aos
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void addSubArray1 (int *A, int *B, int w, int h) {
for (int i = 0; i < w; i++) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
B[2 * j * w + i] += A[i];
B[(2 * j + 1) * w + i] -= A[i];
}
} | code for sm_80
Function : _Z12addSubArray1PiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0050*/ IADD3 R3, R4.reuse, -0x1, RZ ; /* 0xffffffff04037810 */
/* 0x040fe20007ffe0ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304007812 */
/* 0x000fe200078ec0ff */
/*0080*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0090*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*00a0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00c0*/ IMAD R11, R11, c[0x0][0x0], R2 ; /* 0x000000000b0b7a24 */
/* 0x001fca00078e0202 */
/*00d0*/ SHF.L.U32 R13, R11, 0x1, RZ ; /* 0x000000010b0d7819 */
/* 0x000fca00000006ff */
/*00e0*/ IMAD R13, R13, R4, c[0x0][0x170] ; /* 0x00005c000d0d7624 */
/* 0x000fe200078e0204 */
/*00f0*/ @!P1 BRA 0x430 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD R15, R11, c[0x0][0x170], RZ ; /* 0x00005c000b0f7a24 */
/* 0x000fe200078e02ff */
/*0110*/ IADD3 R12, -R0, c[0x0][0x170], RZ ; /* 0x00005c00000c7a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0130*/ MOV R14, c[0x0][0x160] ; /* 0x00005800000e7a02 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0150*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.SHL.U32 R15, R15, 0x2, RZ ; /* 0x000000020f0f7824 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.WIDE R6, R15, 0x4, R4 ; /* 0x000000040f067825 */
/* 0x001fc800078e0204 */
/*0190*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000e */
/*01a0*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ IADD3 R17, R8, R9, RZ ; /* 0x0000000908117210 */
/* 0x004fe20007ffe0ff */
/*01d0*/ IMAD.WIDE R8, R13, 0x4, R4 ; /* 0x000000040d087825 */
/* 0x000fc800078e0204 */
/*01e0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x000ea4000c1e1900 */
/*0210*/ IMAD.IADD R19, R14, 0x1, -R19 ; /* 0x000000010e137824 */
/* 0x004fca00078e0a13 */
/*0220*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0003e8000c101904 */
/*0230*/ LDG.E R14, [R6.64+0x4] ; /* 0x00000404060e7981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R21, [R2.64+0x4] ; /* 0x0000040402157981 */
/* 0x000ea4000c1e1900 */
/*0250*/ IADD3 R21, R14, R21, RZ ; /* 0x000000150e157210 */
/* 0x004fca0007ffe0ff */
/*0260*/ STG.E [R6.64+0x4], R21 ; /* 0x0000041506007986 */
/* 0x0005e8000c101904 */
/*0270*/ LDG.E R14, [R8.64+0x4] ; /* 0x00000404080e7981 */
/* 0x000ee8000c1e1900 */
/*0280*/ LDG.E R23, [R2.64+0x4] ; /* 0x0000040402177981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.IADD R23, R14, 0x1, -R23 ; /* 0x000000010e177824 */
/* 0x008fca00078e0a17 */
/*02a0*/ STG.E [R8.64+0x4], R23 ; /* 0x0000041708007986 */
/* 0x0007e8000c101904 */
/*02b0*/ LDG.E R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x001f24000c1e1900 */
/*02d0*/ IADD3 R17, R14, R17, RZ ; /* 0x000000110e117210 */
/* 0x010fca0007ffe0ff */
/*02e0*/ STG.E [R6.64+0x8], R17 ; /* 0x0000081106007986 */
/* 0x0001e8000c101904 */
/*02f0*/ LDG.E R14, [R8.64+0x8] ; /* 0x00000804080e7981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R2.64+0x8] ; /* 0x0000080402137981 */
/* 0x002f24000c1e1900 */
/*0310*/ IMAD.IADD R19, R14, 0x1, -R19 ; /* 0x000000010e137824 */
/* 0x010fca00078e0a13 */
/*0320*/ STG.E [R8.64+0x8], R19 ; /* 0x0000081308007986 */
/* 0x0001e8000c101904 */
/*0330*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c04060e7981 */
/* 0x000f28000c1e1900 */
/*0340*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x004f22000c1e1900 */
/*0350*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fe40007ffe0ff */
/*0360*/ IADD3 R21, R14, R21, RZ ; /* 0x000000150e157210 */
/* 0x010fca0007ffe0ff */
/*0370*/ STG.E [R6.64+0xc], R21 ; /* 0x00000c1506007986 */
/* 0x0001e8000c101904 */
/*0380*/ LDG.E R14, [R8.64+0xc] ; /* 0x00000c04080e7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R23, [R2.64+0xc] ; /* 0x00000c0402177981 */
/* 0x008ea2000c1e1900 */
/*03a0*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f25270 */
/*03b0*/ IADD3 R4, P2, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc40007f5e0ff */
/*03c0*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200017fe4ff */
/*03e0*/ IMAD.IADD R23, R14, 0x1, -R23 ; /* 0x000000010e177824 */
/* 0x004fe200078e0a17 */
/*03f0*/ IADD3 R14, P3, R2, 0x10, RZ ; /* 0x00000010020e7810 */
/* 0x000fc80007f7e0ff */
/*0400*/ STG.E [R8.64+0xc], R23 ; /* 0x00000c1708007986 */
/* 0x0001e2000c101904 */
/*0410*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe200018e0603 */
/*0420*/ @P1 BRA 0x180 ; /* 0xfffffd5000001947 */
/* 0x000fea000383ffff */
/*0430*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0440*/ IMAD R11, R11, c[0x0][0x170], RZ ; /* 0x00005c000b0b7a24 */
/* 0x000fe200078e02ff */
/*0450*/ IADD3 R2, R13, R10, RZ ; /* 0x0000000a0d027210 */
/* 0x000fe20007ffe0ff */
/*0460*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0470*/ LEA R4, R11, R10, 0x1 ; /* 0x0000000a0b047211 */
/* 0x000fe200078e08ff */
/*0480*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0205 */
/*0490*/ IMAD.WIDE R10, R10, R5, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe200078e0205 */
/*04a0*/ MOV R13, R3 ; /* 0x00000003000d7202 */
/* 0x000fc60000000f00 */
/*04b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*04c0*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0002 */
/*04d0*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x000fe20000000f00 */
/*04e0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x001fc800078e0004 */
/*04f0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0500*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe20000000f00 */
/*0510*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fc600078e000b */
/*0520*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1900 */
/*0530*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0540*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0550*/ IADD3 R9, R6, R7, RZ ; /* 0x0000000706097210 */
/* 0x004fe20007ffe0ff */
/*0560*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000c */
/*0570*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fc60000000f00 */
/*0580*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0590*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*05c0*/ IADD3 R12, P1, R6, 0x4, RZ ; /* 0x00000004060c7810 */
/* 0x000fc40007f3e0ff */
/*05d0*/ IADD3 R10, P3, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fe40007f7e0ff */
/*05e0*/ IADD3.X R13, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff0d7210 */
/* 0x000fe20000ffe4ff */
/*05f0*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x004fe200078e0a0b */
/*0600*/ IADD3 R8, P2, R2, 0x4, RZ ; /* 0x0000000402087810 */
/* 0x000fc80007f5e0ff */
/*0610*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0003e2000c101904 */
/*0620*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*0630*/ IADD3.X R11, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0b7210 */
/* 0x002fe20001ffe4ff */
/*0640*/ @P0 BRA 0x4f0 ; /* 0xfffffea000000947 */
/* 0x000fea000383ffff */
/*0650*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0660*/ BRA 0x660; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void addSubArray1 (int *A, int *B, int w, int h) {
for (int i = 0; i < w; i++) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
B[2 * j * w + i] += A[i];
B[(2 * j + 1) * w + i] -= A[i];
}
} | .file "tmpxft_0011aae5_00000000-6_addSub1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12addSubArray1PiS_iiPiS_ii
.type _Z36__device_stub__Z12addSubArray1PiS_iiPiS_ii, @function
_Z36__device_stub__Z12addSubArray1PiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12addSubArray1PiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12addSubArray1PiS_iiPiS_ii, .-_Z36__device_stub__Z12addSubArray1PiS_iiPiS_ii
.globl _Z12addSubArray1PiS_ii
.type _Z12addSubArray1PiS_ii, @function
_Z12addSubArray1PiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12addSubArray1PiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12addSubArray1PiS_ii, .-_Z12addSubArray1PiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12addSubArray1PiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12addSubArray1PiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void addSubArray1 (int *A, int *B, int w, int h) {
for (int i = 0; i < w; i++) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
B[2 * j * w + i] += A[i];
B[(2 * j + 1) * w + i] -= A[i];
}
} | #include <hip/hip_runtime.h>
__global__ void addSubArray1 (int *A, int *B, int w, int h) {
for (int i = 0; i < w; i++) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
B[2 * j * w + i] += A[i];
B[(2 * j + 1) * w + i] -= A[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void addSubArray1 (int *A, int *B, int w, int h) {
for (int i = 0; i < w; i++) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
B[2 * j * w + i] += A[i];
B[(2 * j + 1) * w + i] -= A[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12addSubArray1PiS_ii
.globl _Z12addSubArray1PiS_ii
.p2align 8
.type _Z12addSubArray1PiS_ii,@function
_Z12addSubArray1PiS_ii:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s2, s[0:1], 0x24
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_load_b128 s[0:3], s[0:1], 0x0
v_add_lshl_u32 v0, s15, v0, 1
v_or_b32_e32 v1, 1, v0
v_mul_lo_u32 v0, v0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
.p2align 6
.LBB0_2:
global_load_b32 v5, v4, s[0:1]
global_load_b32 v6, v[0:1], off
s_add_i32 s4, s4, -1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
global_store_b32 v[0:1], v5, off
global_load_b32 v5, v4, s[0:1]
global_load_b32 v6, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v5, v6, v5
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12addSubArray1PiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12addSubArray1PiS_ii, .Lfunc_end0-_Z12addSubArray1PiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12addSubArray1PiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12addSubArray1PiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void addSubArray1 (int *A, int *B, int w, int h) {
for (int i = 0; i < w; i++) {
int j = blockIdx.x * blockDim.x + threadIdx.x;
B[2 * j * w + i] += A[i];
B[(2 * j + 1) * w + i] -= A[i];
}
} | .text
.file "addSub1.hip"
.globl _Z27__device_stub__addSubArray1PiS_ii # -- Begin function _Z27__device_stub__addSubArray1PiS_ii
.p2align 4, 0x90
.type _Z27__device_stub__addSubArray1PiS_ii,@function
_Z27__device_stub__addSubArray1PiS_ii: # @_Z27__device_stub__addSubArray1PiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12addSubArray1PiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__addSubArray1PiS_ii, .Lfunc_end0-_Z27__device_stub__addSubArray1PiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12addSubArray1PiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12addSubArray1PiS_ii,@object # @_Z12addSubArray1PiS_ii
.section .rodata,"a",@progbits
.globl _Z12addSubArray1PiS_ii
.p2align 3, 0x0
_Z12addSubArray1PiS_ii:
.quad _Z27__device_stub__addSubArray1PiS_ii
.size _Z12addSubArray1PiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12addSubArray1PiS_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__addSubArray1PiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12addSubArray1PiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12addSubArray1PiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0050*/ IADD3 R3, R4.reuse, -0x1, RZ ; /* 0xffffffff04037810 */
/* 0x040fe20007ffe0ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304007812 */
/* 0x000fe200078ec0ff */
/*0080*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0090*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*00a0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00c0*/ IMAD R11, R11, c[0x0][0x0], R2 ; /* 0x000000000b0b7a24 */
/* 0x001fca00078e0202 */
/*00d0*/ SHF.L.U32 R13, R11, 0x1, RZ ; /* 0x000000010b0d7819 */
/* 0x000fca00000006ff */
/*00e0*/ IMAD R13, R13, R4, c[0x0][0x170] ; /* 0x00005c000d0d7624 */
/* 0x000fe200078e0204 */
/*00f0*/ @!P1 BRA 0x430 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD R15, R11, c[0x0][0x170], RZ ; /* 0x00005c000b0f7a24 */
/* 0x000fe200078e02ff */
/*0110*/ IADD3 R12, -R0, c[0x0][0x170], RZ ; /* 0x00005c00000c7a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0130*/ MOV R14, c[0x0][0x160] ; /* 0x00005800000e7a02 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0150*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.SHL.U32 R15, R15, 0x2, RZ ; /* 0x000000020f0f7824 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.WIDE R6, R15, 0x4, R4 ; /* 0x000000040f067825 */
/* 0x001fc800078e0204 */
/*0190*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000e */
/*01a0*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ IADD3 R17, R8, R9, RZ ; /* 0x0000000908117210 */
/* 0x004fe20007ffe0ff */
/*01d0*/ IMAD.WIDE R8, R13, 0x4, R4 ; /* 0x000000040d087825 */
/* 0x000fc800078e0204 */
/*01e0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x000ea4000c1e1900 */
/*0210*/ IMAD.IADD R19, R14, 0x1, -R19 ; /* 0x000000010e137824 */
/* 0x004fca00078e0a13 */
/*0220*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0003e8000c101904 */
/*0230*/ LDG.E R14, [R6.64+0x4] ; /* 0x00000404060e7981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R21, [R2.64+0x4] ; /* 0x0000040402157981 */
/* 0x000ea4000c1e1900 */
/*0250*/ IADD3 R21, R14, R21, RZ ; /* 0x000000150e157210 */
/* 0x004fca0007ffe0ff */
/*0260*/ STG.E [R6.64+0x4], R21 ; /* 0x0000041506007986 */
/* 0x0005e8000c101904 */
/*0270*/ LDG.E R14, [R8.64+0x4] ; /* 0x00000404080e7981 */
/* 0x000ee8000c1e1900 */
/*0280*/ LDG.E R23, [R2.64+0x4] ; /* 0x0000040402177981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.IADD R23, R14, 0x1, -R23 ; /* 0x000000010e177824 */
/* 0x008fca00078e0a17 */
/*02a0*/ STG.E [R8.64+0x4], R23 ; /* 0x0000041708007986 */
/* 0x0007e8000c101904 */
/*02b0*/ LDG.E R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x001f24000c1e1900 */
/*02d0*/ IADD3 R17, R14, R17, RZ ; /* 0x000000110e117210 */
/* 0x010fca0007ffe0ff */
/*02e0*/ STG.E [R6.64+0x8], R17 ; /* 0x0000081106007986 */
/* 0x0001e8000c101904 */
/*02f0*/ LDG.E R14, [R8.64+0x8] ; /* 0x00000804080e7981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R2.64+0x8] ; /* 0x0000080402137981 */
/* 0x002f24000c1e1900 */
/*0310*/ IMAD.IADD R19, R14, 0x1, -R19 ; /* 0x000000010e137824 */
/* 0x010fca00078e0a13 */
/*0320*/ STG.E [R8.64+0x8], R19 ; /* 0x0000081308007986 */
/* 0x0001e8000c101904 */
/*0330*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c04060e7981 */
/* 0x000f28000c1e1900 */
/*0340*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x004f22000c1e1900 */
/*0350*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fe40007ffe0ff */
/*0360*/ IADD3 R21, R14, R21, RZ ; /* 0x000000150e157210 */
/* 0x010fca0007ffe0ff */
/*0370*/ STG.E [R6.64+0xc], R21 ; /* 0x00000c1506007986 */
/* 0x0001e8000c101904 */
/*0380*/ LDG.E R14, [R8.64+0xc] ; /* 0x00000c04080e7981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R23, [R2.64+0xc] ; /* 0x00000c0402177981 */
/* 0x008ea2000c1e1900 */
/*03a0*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f25270 */
/*03b0*/ IADD3 R4, P2, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc40007f5e0ff */
/*03c0*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x000fe200017fe4ff */
/*03e0*/ IMAD.IADD R23, R14, 0x1, -R23 ; /* 0x000000010e177824 */
/* 0x004fe200078e0a17 */
/*03f0*/ IADD3 R14, P3, R2, 0x10, RZ ; /* 0x00000010020e7810 */
/* 0x000fc80007f7e0ff */
/*0400*/ STG.E [R8.64+0xc], R23 ; /* 0x00000c1708007986 */
/* 0x0001e2000c101904 */
/*0410*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe200018e0603 */
/*0420*/ @P1 BRA 0x180 ; /* 0xfffffd5000001947 */
/* 0x000fea000383ffff */
/*0430*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0440*/ IMAD R11, R11, c[0x0][0x170], RZ ; /* 0x00005c000b0b7a24 */
/* 0x000fe200078e02ff */
/*0450*/ IADD3 R2, R13, R10, RZ ; /* 0x0000000a0d027210 */
/* 0x000fe20007ffe0ff */
/*0460*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0470*/ LEA R4, R11, R10, 0x1 ; /* 0x0000000a0b047211 */
/* 0x000fe200078e08ff */
/*0480*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0205 */
/*0490*/ IMAD.WIDE R10, R10, R5, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe200078e0205 */
/*04a0*/ MOV R13, R3 ; /* 0x00000003000d7202 */
/* 0x000fc60000000f00 */
/*04b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*04c0*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0002 */
/*04d0*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x000fe20000000f00 */
/*04e0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x001fc800078e0004 */
/*04f0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0500*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe20000000f00 */
/*0510*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fc600078e000b */
/*0520*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1900 */
/*0530*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0540*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0550*/ IADD3 R9, R6, R7, RZ ; /* 0x0000000706097210 */
/* 0x004fe20007ffe0ff */
/*0560*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000c */
/*0570*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fc60000000f00 */
/*0580*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0590*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*05c0*/ IADD3 R12, P1, R6, 0x4, RZ ; /* 0x00000004060c7810 */
/* 0x000fc40007f3e0ff */
/*05d0*/ IADD3 R10, P3, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fe40007f7e0ff */
/*05e0*/ IADD3.X R13, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff0d7210 */
/* 0x000fe20000ffe4ff */
/*05f0*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x004fe200078e0a0b */
/*0600*/ IADD3 R8, P2, R2, 0x4, RZ ; /* 0x0000000402087810 */
/* 0x000fc80007f5e0ff */
/*0610*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0003e2000c101904 */
/*0620*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*0630*/ IADD3.X R11, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0b7210 */
/* 0x002fe20001ffe4ff */
/*0640*/ @P0 BRA 0x4f0 ; /* 0xfffffea000000947 */
/* 0x000fea000383ffff */
/*0650*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0660*/ BRA 0x660; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12addSubArray1PiS_ii
.globl _Z12addSubArray1PiS_ii
.p2align 8
.type _Z12addSubArray1PiS_ii,@function
_Z12addSubArray1PiS_ii:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s2, s[0:1], 0x24
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_load_b128 s[0:3], s[0:1], 0x0
v_add_lshl_u32 v0, s15, v0, 1
v_or_b32_e32 v1, 1, v0
v_mul_lo_u32 v0, v0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
.p2align 6
.LBB0_2:
global_load_b32 v5, v4, s[0:1]
global_load_b32 v6, v[0:1], off
s_add_i32 s4, s4, -1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
global_store_b32 v[0:1], v5, off
global_load_b32 v5, v4, s[0:1]
global_load_b32 v6, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v5, v6, v5
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12addSubArray1PiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12addSubArray1PiS_ii, .Lfunc_end0-_Z12addSubArray1PiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12addSubArray1PiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12addSubArray1PiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011aae5_00000000-6_addSub1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12addSubArray1PiS_iiPiS_ii
.type _Z36__device_stub__Z12addSubArray1PiS_iiPiS_ii, @function
_Z36__device_stub__Z12addSubArray1PiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12addSubArray1PiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12addSubArray1PiS_iiPiS_ii, .-_Z36__device_stub__Z12addSubArray1PiS_iiPiS_ii
.globl _Z12addSubArray1PiS_ii
.type _Z12addSubArray1PiS_ii, @function
_Z12addSubArray1PiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12addSubArray1PiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12addSubArray1PiS_ii, .-_Z12addSubArray1PiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12addSubArray1PiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12addSubArray1PiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addSub1.hip"
.globl _Z27__device_stub__addSubArray1PiS_ii # -- Begin function _Z27__device_stub__addSubArray1PiS_ii
.p2align 4, 0x90
.type _Z27__device_stub__addSubArray1PiS_ii,@function
_Z27__device_stub__addSubArray1PiS_ii: # @_Z27__device_stub__addSubArray1PiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12addSubArray1PiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__addSubArray1PiS_ii, .Lfunc_end0-_Z27__device_stub__addSubArray1PiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12addSubArray1PiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12addSubArray1PiS_ii,@object # @_Z12addSubArray1PiS_ii
.section .rodata,"a",@progbits
.globl _Z12addSubArray1PiS_ii
.p2align 3, 0x0
_Z12addSubArray1PiS_ii:
.quad _Z27__device_stub__addSubArray1PiS_ii
.size _Z12addSubArray1PiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12addSubArray1PiS_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__addSubArray1PiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12addSubArray1PiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Exercise: Implement matrix transpose using CUDA
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/time.h>
#include<assert.h>
// #define NUM_BLOCKS 8192
#define NUM_THREADS 512
double cclock()
/* Returns elepsed seconds past from the last call to timer rest */
{
struct timeval tmp;
double sec;
gettimeofday( &tmp, (struct timezone *)0 );
sec = tmp.tv_sec + ((double)tmp.tv_usec)/1000000.0;
return sec;
}
// print the matrix
void print_matrix(int size, double * M)
{
int i, j;
for (i=0; i<size; i++)
{
for(j=0; j<size; j++)
{
fprintf(stdout, "%f ", M[ i*size + j ]);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\n");
}
// transpose the matrix
__global__ void trasp_mat(int MATRIXDIM, double * d_A, double * d_AT)
{
int idx = ( blockIdx.x * blockDim.x ) + threadIdx.x;
// here I am writing i and j as functions of idx,
// knowing that idx = i*MATRIXDIM+j
int i = idx / MATRIXDIM;
int j = idx % MATRIXDIM;
if ( idx < MATRIXDIM * MATRIXDIM )
{
d_AT[ ( j * MATRIXDIM ) + i ] = d_A[ ( i * MATRIXDIM ) + j ];
}
}
int main( int argc, char * argv [] )
{
double * h_A, * h_AT; // host pointers
double * d_A, * d_AT; // device pointers
int i;
int MATRIXDIM;
int size_in_bytes;
double t_start, t_end;
if( argc < 2 ){
fprintf( stderr, "Error. The program runs as following: %s [MATRIXDIM].\nProgram exit ...\n", argv[0]);
exit(1);
}
MATRIXDIM = atoi(argv[1]);
size_in_bytes = MATRIXDIM * MATRIXDIM * sizeof( double );
if( MATRIXDIM < 1 ){
fprintf( stderr, "Error. Inconsistent parameters.\nProgram exit ...\n", argv[0]);
exit(1);
}
// allocate the pointers
h_A = ( double * ) malloc( size_in_bytes );
h_AT = ( double * ) malloc( size_in_bytes );
//cudaMalloc( (void **) &my_ptr, sizeinbytes );
cudaMalloc( (void**) &d_A, size_in_bytes );
cudaMalloc( (void**) &d_AT, size_in_bytes );
// initialize the matrix A
for( i = 0; i < MATRIXDIM * MATRIXDIM; i++ ){
h_A[i] = (double) i;
}
print_matrix( MATRIXDIM, h_A);
// copy from cpu to gpu
//cudaMemcpy( dest, source, sizeinbytes, cudaMemcpyHostToDevice | cudaMemcpyDeviceToHost );
cudaMemcpy( d_A, h_A, size_in_bytes, cudaMemcpyHostToDevice );
// (MATRIXDIM * MATRIXDIM + NUM_THREADS) makes sure that we create enough threads
t_start=cclock();
trasp_mat<<< (MATRIXDIM * MATRIXDIM + NUM_THREADS) / NUM_THREADS, NUM_THREADS >>>( MATRIXDIM, d_A, d_AT );
t_end=cclock();
// copying from gpu to cpu
cudaMemcpy( h_AT, d_AT, size_in_bytes, cudaMemcpyDeviceToHost );
print_matrix(MATRIXDIM, h_AT);
fprintf( stdout, " Matrix transpose executed. Time Elapsed %9.4f secs\n", t_end-t_start );
// free the memory
free( h_A );
free( h_AT );
cudaFree( d_A );
cudaFree( d_AT );
return 0;
} | code for sm_80
Function : _Z9trasp_matiPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x160] ; /* 0x0000580000057a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00f0*/ IADD3 R6, RZ, -R3, RZ ; /* 0x80000003ff067210 */
/* 0x002fca0007ffe0ff */
/*0100*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0110*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0120*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0130*/ LOP3.LUT R2, R0, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580000027a12 */
/* 0x000fc600078e3cff */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0160*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R3, RZ, RZ ; /* 0x000000ff03047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*0190*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01a0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*01b0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f45270 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fc80007ffe0ff */
/*01f0*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fca0000000f00 */
/*0200*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0210*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff04aa12 */
/* 0x000fc800078e33ff */
/*0220*/ IADD3 R5, -R4, RZ, RZ ; /* 0x000000ff04057210 */
/* 0x000fca0007ffe1ff */
/*0230*/ IMAD R5, R5, c[0x0][0x160], R0 ; /* 0x0000580005057a24 */
/* 0x000fc800078e0200 */
/*0240*/ IMAD R2, R4, c[0x0][0x160], R5 ; /* 0x0000580004027a24 */
/* 0x000fc800078e0205 */
/*0250*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0207 */
/*0260*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD R4, R5, c[0x0][0x160], R4 ; /* 0x0000580005047a24 */
/* 0x000fc800078e0204 */
/*0280*/ IMAD.WIDE R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0207 */
/*0290*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Exercise: Implement matrix transpose using CUDA
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/time.h>
#include<assert.h>
// #define NUM_BLOCKS 8192
#define NUM_THREADS 512
double cclock()
/* Returns elepsed seconds past from the last call to timer rest */
{
struct timeval tmp;
double sec;
gettimeofday( &tmp, (struct timezone *)0 );
sec = tmp.tv_sec + ((double)tmp.tv_usec)/1000000.0;
return sec;
}
// print the matrix
void print_matrix(int size, double * M)
{
int i, j;
for (i=0; i<size; i++)
{
for(j=0; j<size; j++)
{
fprintf(stdout, "%f ", M[ i*size + j ]);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\n");
}
// transpose the matrix
__global__ void trasp_mat(int MATRIXDIM, double * d_A, double * d_AT)
{
int idx = ( blockIdx.x * blockDim.x ) + threadIdx.x;
// here I am writing i and j as functions of idx,
// knowing that idx = i*MATRIXDIM+j
int i = idx / MATRIXDIM;
int j = idx % MATRIXDIM;
if ( idx < MATRIXDIM * MATRIXDIM )
{
d_AT[ ( j * MATRIXDIM ) + i ] = d_A[ ( i * MATRIXDIM ) + j ];
}
}
int main( int argc, char * argv [] )
{
double * h_A, * h_AT; // host pointers
double * d_A, * d_AT; // device pointers
int i;
int MATRIXDIM;
int size_in_bytes;
double t_start, t_end;
if( argc < 2 ){
fprintf( stderr, "Error. The program runs as following: %s [MATRIXDIM].\nProgram exit ...\n", argv[0]);
exit(1);
}
MATRIXDIM = atoi(argv[1]);
size_in_bytes = MATRIXDIM * MATRIXDIM * sizeof( double );
if( MATRIXDIM < 1 ){
fprintf( stderr, "Error. Inconsistent parameters.\nProgram exit ...\n", argv[0]);
exit(1);
}
// allocate the pointers
h_A = ( double * ) malloc( size_in_bytes );
h_AT = ( double * ) malloc( size_in_bytes );
//cudaMalloc( (void **) &my_ptr, sizeinbytes );
cudaMalloc( (void**) &d_A, size_in_bytes );
cudaMalloc( (void**) &d_AT, size_in_bytes );
// initialize the matrix A
for( i = 0; i < MATRIXDIM * MATRIXDIM; i++ ){
h_A[i] = (double) i;
}
print_matrix( MATRIXDIM, h_A);
// copy from cpu to gpu
//cudaMemcpy( dest, source, sizeinbytes, cudaMemcpyHostToDevice | cudaMemcpyDeviceToHost );
cudaMemcpy( d_A, h_A, size_in_bytes, cudaMemcpyHostToDevice );
// (MATRIXDIM * MATRIXDIM + NUM_THREADS) makes sure that we create enough threads
t_start=cclock();
trasp_mat<<< (MATRIXDIM * MATRIXDIM + NUM_THREADS) / NUM_THREADS, NUM_THREADS >>>( MATRIXDIM, d_A, d_AT );
t_end=cclock();
// copying from gpu to cpu
cudaMemcpy( h_AT, d_AT, size_in_bytes, cudaMemcpyDeviceToHost );
print_matrix(MATRIXDIM, h_AT);
fprintf( stdout, " Matrix transpose executed. Time Elapsed %9.4f secs\n", t_end-t_start );
// free the memory
free( h_A );
free( h_AT );
cudaFree( d_A );
cudaFree( d_AT );
return 0;
} | .file "tmpxft_0004c58f_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6cclockv
.type _Z6cclockv, @function
_Z6cclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6cclockv, .-_Z6cclockv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f "
.LC2:
.string "\n"
.text
.globl _Z12print_matrixiPd
.type _Z12print_matrixiPd, @function
_Z12print_matrixiPd:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
testl %edi, %edi
jle .L8
movslq %edi, %r14
leaq 0(,%r14,8), %r15
leaq (%rsi,%r15), %rbp
negq %r14
salq $3, %r14
movl $0, %r13d
leaq .LC1(%rip), %r12
.L9:
leaq 0(%rbp,%r14), %rbx
.L10:
movsd (%rbx), %xmm0
movq %r12, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L10
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L9
.L8:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12print_matrixiPd, .-_Z12print_matrixiPd
.globl _Z31__device_stub__Z9trasp_matiPdS_iPdS_
.type _Z31__device_stub__Z9trasp_matiPdS_iPdS_, @function
_Z31__device_stub__Z9trasp_matiPdS_iPdS_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9trasp_matiPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z9trasp_matiPdS_iPdS_, .-_Z31__device_stub__Z9trasp_matiPdS_iPdS_
.globl _Z9trasp_matiPdS_
.type _Z9trasp_matiPdS_, @function
_Z9trasp_matiPdS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9trasp_matiPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9trasp_matiPdS_, .-_Z9trasp_matiPdS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Error. The program runs as following: %s [MATRIXDIM].\nProgram exit ...\n"
.align 8
.LC4:
.string "Error. Inconsistent parameters.\nProgram exit ...\n"
.align 8
.LC5:
.string " Matrix transpose executed. Time Elapsed %9.4f secs\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L29
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r14d
movl %eax, %ebx
imull %eax, %ebx
leal 0(,%rbx,8), %r12d
testl %eax, %eax
jle .L30
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $0, %eax
.L24:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
addq $1, %rax
cmpl %eax, %ebx
jg .L24
movq %rbp, %rsi
movl %r14d, %edi
call _Z12print_matrixiPd
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _Z6cclockv
movsd %xmm0, (%rsp)
movl $512, 44(%rsp)
movl $1, 48(%rsp)
leal 1023(%rbx), %eax
addl $512, %ebx
cmovns %ebx, %eax
sarl $9, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L25:
call _Z6cclockv
movsd %xmm0, 8(%rsp)
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rsi
movl %r14d, %edi
call _Z12print_matrixiPd
movsd 8(%rsp), %xmm0
subsd (%rsp), %xmm0
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movq 0(%rbp), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl %r14d, %edi
call _Z31__device_stub__Z9trasp_matiPdS_iPdS_
jmp .L25
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9trasp_matiPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9trasp_matiPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Exercise: Implement matrix transpose using CUDA
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/time.h>
#include<assert.h>
// #define NUM_BLOCKS 8192
#define NUM_THREADS 512
double cclock()
/* Returns elepsed seconds past from the last call to timer rest */
{
struct timeval tmp;
double sec;
gettimeofday( &tmp, (struct timezone *)0 );
sec = tmp.tv_sec + ((double)tmp.tv_usec)/1000000.0;
return sec;
}
// print the matrix
void print_matrix(int size, double * M)
{
int i, j;
for (i=0; i<size; i++)
{
for(j=0; j<size; j++)
{
fprintf(stdout, "%f ", M[ i*size + j ]);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\n");
}
// transpose the matrix
__global__ void trasp_mat(int MATRIXDIM, double * d_A, double * d_AT)
{
int idx = ( blockIdx.x * blockDim.x ) + threadIdx.x;
// here I am writing i and j as functions of idx,
// knowing that idx = i*MATRIXDIM+j
int i = idx / MATRIXDIM;
int j = idx % MATRIXDIM;
if ( idx < MATRIXDIM * MATRIXDIM )
{
d_AT[ ( j * MATRIXDIM ) + i ] = d_A[ ( i * MATRIXDIM ) + j ];
}
}
int main( int argc, char * argv [] )
{
double * h_A, * h_AT; // host pointers
double * d_A, * d_AT; // device pointers
int i;
int MATRIXDIM;
int size_in_bytes;
double t_start, t_end;
if( argc < 2 ){
fprintf( stderr, "Error. The program runs as following: %s [MATRIXDIM].\nProgram exit ...\n", argv[0]);
exit(1);
}
MATRIXDIM = atoi(argv[1]);
size_in_bytes = MATRIXDIM * MATRIXDIM * sizeof( double );
if( MATRIXDIM < 1 ){
fprintf( stderr, "Error. Inconsistent parameters.\nProgram exit ...\n", argv[0]);
exit(1);
}
// allocate the pointers
h_A = ( double * ) malloc( size_in_bytes );
h_AT = ( double * ) malloc( size_in_bytes );
//cudaMalloc( (void **) &my_ptr, sizeinbytes );
cudaMalloc( (void**) &d_A, size_in_bytes );
cudaMalloc( (void**) &d_AT, size_in_bytes );
// initialize the matrix A
for( i = 0; i < MATRIXDIM * MATRIXDIM; i++ ){
h_A[i] = (double) i;
}
print_matrix( MATRIXDIM, h_A);
// copy from cpu to gpu
//cudaMemcpy( dest, source, sizeinbytes, cudaMemcpyHostToDevice | cudaMemcpyDeviceToHost );
cudaMemcpy( d_A, h_A, size_in_bytes, cudaMemcpyHostToDevice );
// (MATRIXDIM * MATRIXDIM + NUM_THREADS) makes sure that we create enough threads
t_start=cclock();
trasp_mat<<< (MATRIXDIM * MATRIXDIM + NUM_THREADS) / NUM_THREADS, NUM_THREADS >>>( MATRIXDIM, d_A, d_AT );
t_end=cclock();
// copying from gpu to cpu
cudaMemcpy( h_AT, d_AT, size_in_bytes, cudaMemcpyDeviceToHost );
print_matrix(MATRIXDIM, h_AT);
fprintf( stdout, " Matrix transpose executed. Time Elapsed %9.4f secs\n", t_end-t_start );
// free the memory
free( h_A );
free( h_AT );
cudaFree( d_A );
cudaFree( d_AT );
return 0;
} | // Exercise: Implement matrix transpose using CUDA
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/time.h>
#include<assert.h>
// #define NUM_BLOCKS 8192
#define NUM_THREADS 512
double cclock()
/* Returns elepsed seconds past from the last call to timer rest */
{
struct timeval tmp;
double sec;
gettimeofday( &tmp, (struct timezone *)0 );
sec = tmp.tv_sec + ((double)tmp.tv_usec)/1000000.0;
return sec;
}
// print the matrix
void print_matrix(int size, double * M)
{
int i, j;
for (i=0; i<size; i++)
{
for(j=0; j<size; j++)
{
fprintf(stdout, "%f ", M[ i*size + j ]);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\n");
}
// transpose the matrix
__global__ void trasp_mat(int MATRIXDIM, double * d_A, double * d_AT)
{
int idx = ( blockIdx.x * blockDim.x ) + threadIdx.x;
// here I am writing i and j as functions of idx,
// knowing that idx = i*MATRIXDIM+j
int i = idx / MATRIXDIM;
int j = idx % MATRIXDIM;
if ( idx < MATRIXDIM * MATRIXDIM )
{
d_AT[ ( j * MATRIXDIM ) + i ] = d_A[ ( i * MATRIXDIM ) + j ];
}
}
int main( int argc, char * argv [] )
{
double * h_A, * h_AT; // host pointers
double * d_A, * d_AT; // device pointers
int i;
int MATRIXDIM;
int size_in_bytes;
double t_start, t_end;
if( argc < 2 ){
fprintf( stderr, "Error. The program runs as following: %s [MATRIXDIM].\nProgram exit ...\n", argv[0]);
exit(1);
}
MATRIXDIM = atoi(argv[1]);
size_in_bytes = MATRIXDIM * MATRIXDIM * sizeof( double );
if( MATRIXDIM < 1 ){
fprintf( stderr, "Error. Inconsistent parameters.\nProgram exit ...\n", argv[0]);
exit(1);
}
// allocate the pointers
h_A = ( double * ) malloc( size_in_bytes );
h_AT = ( double * ) malloc( size_in_bytes );
//cudaMalloc( (void **) &my_ptr, sizeinbytes );
hipMalloc( (void**) &d_A, size_in_bytes );
hipMalloc( (void**) &d_AT, size_in_bytes );
// initialize the matrix A
for( i = 0; i < MATRIXDIM * MATRIXDIM; i++ ){
h_A[i] = (double) i;
}
print_matrix( MATRIXDIM, h_A);
// copy from cpu to gpu
//cudaMemcpy( dest, source, sizeinbytes, cudaMemcpyHostToDevice | cudaMemcpyDeviceToHost );
hipMemcpy( d_A, h_A, size_in_bytes, hipMemcpyHostToDevice );
// (MATRIXDIM * MATRIXDIM + NUM_THREADS) makes sure that we create enough threads
t_start=cclock();
trasp_mat<<< (MATRIXDIM * MATRIXDIM + NUM_THREADS) / NUM_THREADS, NUM_THREADS >>>( MATRIXDIM, d_A, d_AT );
t_end=cclock();
// copying from gpu to cpu
hipMemcpy( h_AT, d_AT, size_in_bytes, hipMemcpyDeviceToHost );
print_matrix(MATRIXDIM, h_AT);
fprintf( stdout, " Matrix transpose executed. Time Elapsed %9.4f secs\n", t_end-t_start );
// free the memory
free( h_A );
free( h_AT );
hipFree( d_A );
hipFree( d_AT );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Exercise: Implement matrix transpose using CUDA
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/time.h>
#include<assert.h>
// #define NUM_BLOCKS 8192
#define NUM_THREADS 512
double cclock()
/* Returns elepsed seconds past from the last call to timer rest */
{
struct timeval tmp;
double sec;
gettimeofday( &tmp, (struct timezone *)0 );
sec = tmp.tv_sec + ((double)tmp.tv_usec)/1000000.0;
return sec;
}
// print the matrix
void print_matrix(int size, double * M)
{
int i, j;
for (i=0; i<size; i++)
{
for(j=0; j<size; j++)
{
fprintf(stdout, "%f ", M[ i*size + j ]);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\n");
}
// transpose the matrix
__global__ void trasp_mat(int MATRIXDIM, double * d_A, double * d_AT)
{
int idx = ( blockIdx.x * blockDim.x ) + threadIdx.x;
// here I am writing i and j as functions of idx,
// knowing that idx = i*MATRIXDIM+j
int i = idx / MATRIXDIM;
int j = idx % MATRIXDIM;
if ( idx < MATRIXDIM * MATRIXDIM )
{
d_AT[ ( j * MATRIXDIM ) + i ] = d_A[ ( i * MATRIXDIM ) + j ];
}
}
int main( int argc, char * argv [] )
{
double * h_A, * h_AT; // host pointers
double * d_A, * d_AT; // device pointers
int i;
int MATRIXDIM;
int size_in_bytes;
double t_start, t_end;
if( argc < 2 ){
fprintf( stderr, "Error. The program runs as following: %s [MATRIXDIM].\nProgram exit ...\n", argv[0]);
exit(1);
}
MATRIXDIM = atoi(argv[1]);
size_in_bytes = MATRIXDIM * MATRIXDIM * sizeof( double );
if( MATRIXDIM < 1 ){
fprintf( stderr, "Error. Inconsistent parameters.\nProgram exit ...\n", argv[0]);
exit(1);
}
// allocate the pointers
h_A = ( double * ) malloc( size_in_bytes );
h_AT = ( double * ) malloc( size_in_bytes );
//cudaMalloc( (void **) &my_ptr, sizeinbytes );
hipMalloc( (void**) &d_A, size_in_bytes );
hipMalloc( (void**) &d_AT, size_in_bytes );
// initialize the matrix A
for( i = 0; i < MATRIXDIM * MATRIXDIM; i++ ){
h_A[i] = (double) i;
}
print_matrix( MATRIXDIM, h_A);
// copy from cpu to gpu
//cudaMemcpy( dest, source, sizeinbytes, cudaMemcpyHostToDevice | cudaMemcpyDeviceToHost );
hipMemcpy( d_A, h_A, size_in_bytes, hipMemcpyHostToDevice );
// (MATRIXDIM * MATRIXDIM + NUM_THREADS) makes sure that we create enough threads
t_start=cclock();
trasp_mat<<< (MATRIXDIM * MATRIXDIM + NUM_THREADS) / NUM_THREADS, NUM_THREADS >>>( MATRIXDIM, d_A, d_AT );
t_end=cclock();
// copying from gpu to cpu
hipMemcpy( h_AT, d_AT, size_in_bytes, hipMemcpyDeviceToHost );
print_matrix(MATRIXDIM, h_AT);
fprintf( stdout, " Matrix transpose executed. Time Elapsed %9.4f secs\n", t_end-t_start );
// free the memory
free( h_A );
free( h_AT );
hipFree( d_A );
hipFree( d_AT );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9trasp_matiPdS_
.globl _Z9trasp_matiPdS_
.p2align 8
.type _Z9trasp_matiPdS_,@function
_Z9trasp_matiPdS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s4, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v5, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v6, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v6, v6, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_ashr_i32 s0, s4, 31
s_add_i32 s1, s4, s0
global_load_b64 v[2:3], v[2:3], off
s_xor_b32 s1, s1, s0
v_xor_b32_e32 v5, s0, v5
v_cvt_f32_u32_e32 v0, s1
s_sub_i32 s5, 0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s5, v0
v_mul_hi_u32 v4, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v4
v_mul_hi_u32 v0, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v0, s1
v_sub_nc_u32_e32 v4, v6, v4
v_add_nc_u32_e32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s1, v4
v_cmp_le_u32_e32 vcc_lo, s1, v4
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_add_nc_u32_e32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s1, v4
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v5
v_sub_nc_u32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v0, s4
v_sub_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v1, s4, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9trasp_matiPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9trasp_matiPdS_, .Lfunc_end0-_Z9trasp_matiPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9trasp_matiPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9trasp_matiPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Exercise: Implement matrix transpose using CUDA
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <ctype.h>
#include <sys/types.h>
#include <sys/time.h>
#include<assert.h>
// #define NUM_BLOCKS 8192
#define NUM_THREADS 512
double cclock()
/* Returns elepsed seconds past from the last call to timer rest */
{
struct timeval tmp;
double sec;
gettimeofday( &tmp, (struct timezone *)0 );
sec = tmp.tv_sec + ((double)tmp.tv_usec)/1000000.0;
return sec;
}
// print the matrix
void print_matrix(int size, double * M)
{
int i, j;
for (i=0; i<size; i++)
{
for(j=0; j<size; j++)
{
fprintf(stdout, "%f ", M[ i*size + j ]);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\n");
}
// transpose the matrix
__global__ void trasp_mat(int MATRIXDIM, double * d_A, double * d_AT)
{
int idx = ( blockIdx.x * blockDim.x ) + threadIdx.x;
// here I am writing i and j as functions of idx,
// knowing that idx = i*MATRIXDIM+j
int i = idx / MATRIXDIM;
int j = idx % MATRIXDIM;
if ( idx < MATRIXDIM * MATRIXDIM )
{
d_AT[ ( j * MATRIXDIM ) + i ] = d_A[ ( i * MATRIXDIM ) + j ];
}
}
int main( int argc, char * argv [] )
{
double * h_A, * h_AT; // host pointers
double * d_A, * d_AT; // device pointers
int i;
int MATRIXDIM;
int size_in_bytes;
double t_start, t_end;
if( argc < 2 ){
fprintf( stderr, "Error. The program runs as following: %s [MATRIXDIM].\nProgram exit ...\n", argv[0]);
exit(1);
}
MATRIXDIM = atoi(argv[1]);
size_in_bytes = MATRIXDIM * MATRIXDIM * sizeof( double );
if( MATRIXDIM < 1 ){
fprintf( stderr, "Error. Inconsistent parameters.\nProgram exit ...\n", argv[0]);
exit(1);
}
// allocate the pointers
h_A = ( double * ) malloc( size_in_bytes );
h_AT = ( double * ) malloc( size_in_bytes );
//cudaMalloc( (void **) &my_ptr, sizeinbytes );
hipMalloc( (void**) &d_A, size_in_bytes );
hipMalloc( (void**) &d_AT, size_in_bytes );
// initialize the matrix A
for( i = 0; i < MATRIXDIM * MATRIXDIM; i++ ){
h_A[i] = (double) i;
}
print_matrix( MATRIXDIM, h_A);
// copy from cpu to gpu
//cudaMemcpy( dest, source, sizeinbytes, cudaMemcpyHostToDevice | cudaMemcpyDeviceToHost );
hipMemcpy( d_A, h_A, size_in_bytes, hipMemcpyHostToDevice );
// (MATRIXDIM * MATRIXDIM + NUM_THREADS) makes sure that we create enough threads
t_start=cclock();
trasp_mat<<< (MATRIXDIM * MATRIXDIM + NUM_THREADS) / NUM_THREADS, NUM_THREADS >>>( MATRIXDIM, d_A, d_AT );
t_end=cclock();
// copying from gpu to cpu
hipMemcpy( h_AT, d_AT, size_in_bytes, hipMemcpyDeviceToHost );
print_matrix(MATRIXDIM, h_AT);
fprintf( stdout, " Matrix transpose executed. Time Elapsed %9.4f secs\n", t_end-t_start );
// free the memory
free( h_A );
free( h_AT );
hipFree( d_A );
hipFree( d_AT );
return 0;
} | .text
.file "transpose.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6cclockv
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z6cclockv
.p2align 4, 0x90
.type _Z6cclockv,@function
_Z6cclockv: # @_Z6cclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6cclockv, .Lfunc_end0-_Z6cclockv
.cfi_endproc
# -- End function
.globl _Z12print_matrixiPd # -- Begin function _Z12print_matrixiPd
.p2align 4, 0x90
.type _Z12print_matrixiPd,@function
_Z12print_matrixiPd: # @_Z12print_matrixiPd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, (%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %edi, %ebp
movl %edi, %r14d
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r15d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movq stdout(%rip), %rdi
movsd (%r13,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %esi
movb $1, %al
callq fprintf
incq %rbx
cmpq %rbx, %r14
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incq %r12
addl %ebp, %r15d
cmpq %r14, %r12
jne .LBB1_2
.LBB1_5: # %._crit_edge14
movq stdout(%rip), %rsi
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fputc@PLT # TAILCALL
.Lfunc_end1:
.size _Z12print_matrixiPd, .Lfunc_end1-_Z12print_matrixiPd
.cfi_endproc
# -- End function
.globl _Z24__device_stub__trasp_matiPdS_ # -- Begin function _Z24__device_stub__trasp_matiPdS_
.p2align 4, 0x90
.type _Z24__device_stub__trasp_matiPdS_,@function
_Z24__device_stub__trasp_matiPdS_: # @_Z24__device_stub__trasp_matiPdS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9trasp_matiPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z24__device_stub__trasp_matiPdS_, .Lfunc_end2-_Z24__device_stub__trasp_matiPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $1, %edi
jle .LBB3_1
# %bb.3:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
testl %r14d, %r14d
jle .LBB3_4
# %bb.5:
movl %r14d, %r12d
imull %r12d, %r12d
leal (,%r12,8), %eax
movslq %eax, %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, 8(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
cmpl $1, %r12d
movq %r12, (%rsp) # 8-byte Spill
movl %r12d, %eax
adcl $0, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_6: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
movsd %xmm0, (%rbx,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_6
# %bb.7: # %.preheader.lr.ph.i
movl %r14d, %ebp
xorl %r12d, %r12d
xorl %r13d, %r13d
movq %rbx, 72(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB3_8: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_9 Depth 2
movq %r14, %r15
movl %r12d, %eax
leaq (%rbx,%rax,8), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_9: # Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
movq stdout(%rip), %rdi
movsd (%r14,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %esi
movb $1, %al
callq fprintf
incq %rbx
cmpq %rbx, %rbp
jne .LBB3_9
# %bb.10: # %._crit_edge.i
# in Loop: Header=BB3_8 Depth=1
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incq %r13
movq %r15, %r14
addl %r14d, %r12d
cmpq %rbp, %r13
movq 72(%rsp), %rbx # 8-byte Reload
jne .LBB3_8
# %bb.11: # %_Z12print_matrixiPd.exit
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq 8(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
xorl %ebp, %ebp
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
movq %rax, 96(%rsp) # 8-byte Spill
movq 56(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movq (%rsp), %rdi # 8-byte Reload
addl $512, %edi # imm = 0x200
shrl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movl %r14d, 44(%rsp)
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 48(%rsp)
leaq 160(%rsp), %rax
movq %rax, 56(%rsp)
leaq 152(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9trasp_matiPdS_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13: # %.preheader.lr.ph.i37
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
movq %rax, (%rsp) # 8-byte Spill
movq 56(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movl %r14d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_14: # %.preheader.i39
# =>This Loop Header: Depth=1
# Child Loop BB3_15 Depth 2
movl %ebp, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_15: # Parent Loop BB3_14 Depth=1
# => This Inner Loop Header: Depth=2
movq stdout(%rip), %rdi
movsd (%r14,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %esi
movb $1, %al
callq fprintf
incq %rbx
cmpq %rbx, %r12
jne .LBB3_15
# %bb.16: # %._crit_edge.i45
# in Loop: Header=BB3_14 Depth=1
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incq %r13
movq %r15, %rax
addl %eax, %ebp
cmpq %r12, %r13
jne .LBB3_14
# %bb.17: # %_Z12print_matrixiPd.exit49
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0 # 8-byte Folded Reload
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
cvtsi2sdq (%rsp), %xmm3 # 8-byte Folded Reload
addsd %xmm0, %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0 # 8-byte Folded Reload
cvtsi2sdq 96(%rsp), %xmm2 # 8-byte Folded Reload
divsd %xmm1, %xmm0
addsd %xmm0, %xmm2
subsd %xmm2, %xmm3
movsd %xmm3, 8(%rsp) # 8-byte Spill
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
movq 72(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rdi
movq (%rbx), %rdx
movl $.L.str.2, %esi
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rdi
movq (%rbx), %rdx
movl $.L.str.3, %esi
.LBB3_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9trasp_matiPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 8
.type _Z9trasp_matiPdS_,@object # @_Z9trasp_matiPdS_
.section .rodata,"a",@progbits
.globl _Z9trasp_matiPdS_
.p2align 3, 0x0
_Z9trasp_matiPdS_:
.quad _Z24__device_stub__trasp_matiPdS_
.size _Z9trasp_matiPdS_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Error. The program runs as following: %s [MATRIXDIM].\nProgram exit ...\n"
.size .L.str.2, 72
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error. Inconsistent parameters.\nProgram exit ...\n"
.size .L.str.3, 50
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Matrix transpose executed. Time Elapsed %9.4f secs\n"
.size .L.str.4, 53
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9trasp_matiPdS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__trasp_matiPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9trasp_matiPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9trasp_matiPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x160] ; /* 0x0000580000057a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00f0*/ IADD3 R6, RZ, -R3, RZ ; /* 0x80000003ff067210 */
/* 0x002fca0007ffe0ff */
/*0100*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0110*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0120*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0130*/ LOP3.LUT R2, R0, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580000027a12 */
/* 0x000fc600078e3cff */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0160*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R3, RZ, RZ ; /* 0x000000ff03047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*0190*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01a0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*01b0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f45270 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fc80007ffe0ff */
/*01f0*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fca0000000f00 */
/*0200*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0210*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff04aa12 */
/* 0x000fc800078e33ff */
/*0220*/ IADD3 R5, -R4, RZ, RZ ; /* 0x000000ff04057210 */
/* 0x000fca0007ffe1ff */
/*0230*/ IMAD R5, R5, c[0x0][0x160], R0 ; /* 0x0000580005057a24 */
/* 0x000fc800078e0200 */
/*0240*/ IMAD R2, R4, c[0x0][0x160], R5 ; /* 0x0000580004027a24 */
/* 0x000fc800078e0205 */
/*0250*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0207 */
/*0260*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD R4, R5, c[0x0][0x160], R4 ; /* 0x0000580005047a24 */
/* 0x000fc800078e0204 */
/*0280*/ IMAD.WIDE R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0207 */
/*0290*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9trasp_matiPdS_
.globl _Z9trasp_matiPdS_
.p2align 8
.type _Z9trasp_matiPdS_,@function
_Z9trasp_matiPdS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s4, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v5, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v6, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v6, v6, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_ashr_i32 s0, s4, 31
s_add_i32 s1, s4, s0
global_load_b64 v[2:3], v[2:3], off
s_xor_b32 s1, s1, s0
v_xor_b32_e32 v5, s0, v5
v_cvt_f32_u32_e32 v0, s1
s_sub_i32 s5, 0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s5, v0
v_mul_hi_u32 v4, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v4
v_mul_hi_u32 v0, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v0, s1
v_sub_nc_u32_e32 v4, v6, v4
v_add_nc_u32_e32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s1, v4
v_cmp_le_u32_e32 vcc_lo, s1, v4
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_add_nc_u32_e32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s1, v4
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v5
v_sub_nc_u32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v0, s4
v_sub_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v1, s4, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9trasp_matiPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9trasp_matiPdS_, .Lfunc_end0-_Z9trasp_matiPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9trasp_matiPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9trasp_matiPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004c58f_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6cclockv
.type _Z6cclockv, @function
_Z6cclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6cclockv, .-_Z6cclockv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f "
.LC2:
.string "\n"
.text
.globl _Z12print_matrixiPd
.type _Z12print_matrixiPd, @function
_Z12print_matrixiPd:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
testl %edi, %edi
jle .L8
movslq %edi, %r14
leaq 0(,%r14,8), %r15
leaq (%rsi,%r15), %rbp
negq %r14
salq $3, %r14
movl $0, %r13d
leaq .LC1(%rip), %r12
.L9:
leaq 0(%rbp,%r14), %rbx
.L10:
movsd (%rbx), %xmm0
movq %r12, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L10
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L9
.L8:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12print_matrixiPd, .-_Z12print_matrixiPd
.globl _Z31__device_stub__Z9trasp_matiPdS_iPdS_
.type _Z31__device_stub__Z9trasp_matiPdS_iPdS_, @function
_Z31__device_stub__Z9trasp_matiPdS_iPdS_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9trasp_matiPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z9trasp_matiPdS_iPdS_, .-_Z31__device_stub__Z9trasp_matiPdS_iPdS_
.globl _Z9trasp_matiPdS_
.type _Z9trasp_matiPdS_, @function
_Z9trasp_matiPdS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9trasp_matiPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9trasp_matiPdS_, .-_Z9trasp_matiPdS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Error. The program runs as following: %s [MATRIXDIM].\nProgram exit ...\n"
.align 8
.LC4:
.string "Error. Inconsistent parameters.\nProgram exit ...\n"
.align 8
.LC5:
.string " Matrix transpose executed. Time Elapsed %9.4f secs\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L29
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r14d
movl %eax, %ebx
imull %eax, %ebx
leal 0(,%rbx,8), %r12d
testl %eax, %eax
jle .L30
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $0, %eax
.L24:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
addq $1, %rax
cmpl %eax, %ebx
jg .L24
movq %rbp, %rsi
movl %r14d, %edi
call _Z12print_matrixiPd
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _Z6cclockv
movsd %xmm0, (%rsp)
movl $512, 44(%rsp)
movl $1, 48(%rsp)
leal 1023(%rbx), %eax
addl $512, %ebx
cmovns %ebx, %eax
sarl $9, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L25:
call _Z6cclockv
movsd %xmm0, 8(%rsp)
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rsi
movl %r14d, %edi
call _Z12print_matrixiPd
movsd 8(%rsp), %xmm0
subsd (%rsp), %xmm0
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movq 0(%rbp), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl %r14d, %edi
call _Z31__device_stub__Z9trasp_matiPdS_iPdS_
jmp .L25
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9trasp_matiPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9trasp_matiPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transpose.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6cclockv
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z6cclockv
.p2align 4, 0x90
.type _Z6cclockv,@function
_Z6cclockv: # @_Z6cclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6cclockv, .Lfunc_end0-_Z6cclockv
.cfi_endproc
# -- End function
.globl _Z12print_matrixiPd # -- Begin function _Z12print_matrixiPd
.p2align 4, 0x90
.type _Z12print_matrixiPd,@function
_Z12print_matrixiPd: # @_Z12print_matrixiPd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, (%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %edi, %ebp
movl %edi, %r14d
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r15d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movq stdout(%rip), %rdi
movsd (%r13,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %esi
movb $1, %al
callq fprintf
incq %rbx
cmpq %rbx, %r14
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incq %r12
addl %ebp, %r15d
cmpq %r14, %r12
jne .LBB1_2
.LBB1_5: # %._crit_edge14
movq stdout(%rip), %rsi
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fputc@PLT # TAILCALL
.Lfunc_end1:
.size _Z12print_matrixiPd, .Lfunc_end1-_Z12print_matrixiPd
.cfi_endproc
# -- End function
.globl _Z24__device_stub__trasp_matiPdS_ # -- Begin function _Z24__device_stub__trasp_matiPdS_
.p2align 4, 0x90
.type _Z24__device_stub__trasp_matiPdS_,@function
_Z24__device_stub__trasp_matiPdS_: # @_Z24__device_stub__trasp_matiPdS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9trasp_matiPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z24__device_stub__trasp_matiPdS_, .Lfunc_end2-_Z24__device_stub__trasp_matiPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $1, %edi
jle .LBB3_1
# %bb.3:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
testl %r14d, %r14d
jle .LBB3_4
# %bb.5:
movl %r14d, %r12d
imull %r12d, %r12d
leal (,%r12,8), %eax
movslq %eax, %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, 8(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
cmpl $1, %r12d
movq %r12, (%rsp) # 8-byte Spill
movl %r12d, %eax
adcl $0, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_6: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
movsd %xmm0, (%rbx,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_6
# %bb.7: # %.preheader.lr.ph.i
movl %r14d, %ebp
xorl %r12d, %r12d
xorl %r13d, %r13d
movq %rbx, 72(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB3_8: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_9 Depth 2
movq %r14, %r15
movl %r12d, %eax
leaq (%rbx,%rax,8), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_9: # Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
movq stdout(%rip), %rdi
movsd (%r14,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %esi
movb $1, %al
callq fprintf
incq %rbx
cmpq %rbx, %rbp
jne .LBB3_9
# %bb.10: # %._crit_edge.i
# in Loop: Header=BB3_8 Depth=1
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incq %r13
movq %r15, %r14
addl %r14d, %r12d
cmpq %rbp, %r13
movq 72(%rsp), %rbx # 8-byte Reload
jne .LBB3_8
# %bb.11: # %_Z12print_matrixiPd.exit
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq 8(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
xorl %ebp, %ebp
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
movq %rax, 96(%rsp) # 8-byte Spill
movq 56(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movq (%rsp), %rdi # 8-byte Reload
addl $512, %edi # imm = 0x200
shrl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movl %r14d, 44(%rsp)
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 48(%rsp)
leaq 160(%rsp), %rax
movq %rax, 56(%rsp)
leaq 152(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9trasp_matiPdS_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13: # %.preheader.lr.ph.i37
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
movq %rax, (%rsp) # 8-byte Spill
movq 56(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movl %r14d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_14: # %.preheader.i39
# =>This Loop Header: Depth=1
# Child Loop BB3_15 Depth 2
movl %ebp, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_15: # Parent Loop BB3_14 Depth=1
# => This Inner Loop Header: Depth=2
movq stdout(%rip), %rdi
movsd (%r14,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %esi
movb $1, %al
callq fprintf
incq %rbx
cmpq %rbx, %r12
jne .LBB3_15
# %bb.16: # %._crit_edge.i45
# in Loop: Header=BB3_14 Depth=1
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incq %r13
movq %r15, %rax
addl %eax, %ebp
cmpq %r12, %r13
jne .LBB3_14
# %bb.17: # %_Z12print_matrixiPd.exit49
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0 # 8-byte Folded Reload
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
cvtsi2sdq (%rsp), %xmm3 # 8-byte Folded Reload
addsd %xmm0, %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0 # 8-byte Folded Reload
cvtsi2sdq 96(%rsp), %xmm2 # 8-byte Folded Reload
divsd %xmm1, %xmm0
addsd %xmm0, %xmm2
subsd %xmm2, %xmm3
movsd %xmm3, 8(%rsp) # 8-byte Spill
movq stdout(%rip), %rsi
movl $10, %edi
callq fputc@PLT
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
movq 72(%rsp), %rdi # 8-byte Reload
callq free
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rdi
movq (%rbx), %rdx
movl $.L.str.2, %esi
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rdi
movq (%rbx), %rdx
movl $.L.str.3, %esi
.LBB3_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9trasp_matiPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 8
.type _Z9trasp_matiPdS_,@object # @_Z9trasp_matiPdS_
.section .rodata,"a",@progbits
.globl _Z9trasp_matiPdS_
.p2align 3, 0x0
_Z9trasp_matiPdS_:
.quad _Z24__device_stub__trasp_matiPdS_
.size _Z9trasp_matiPdS_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Error. The program runs as following: %s [MATRIXDIM].\nProgram exit ...\n"
.size .L.str.2, 72
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error. Inconsistent parameters.\nProgram exit ...\n"
.size .L.str.3, 50
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Matrix transpose executed. Time Elapsed %9.4f secs\n"
.size .L.str.4, 53
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9trasp_matiPdS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__trasp_matiPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9trasp_matiPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Detect the number of CUDA capable devices.
*/
#include <iostream>
int main()
{
int count = 0;
cudaGetDeviceCount( &count );
std::cout << count << " device(s) found.\n";
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Detect the number of CUDA capable devices.
*/
#include <iostream>
int main()
{
int count = 0;
cudaGetDeviceCount( &count );
std::cout << count << " device(s) found.\n";
return 0;
} | .file "tmpxft_00056019_00000000-6_01-query.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " device(s) found.\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Detect the number of CUDA capable devices.
*/
#include <iostream>
int main()
{
int count = 0;
cudaGetDeviceCount( &count );
std::cout << count << " device(s) found.\n";
return 0;
} | /**
* Detect the number of CUDA capable devices.
*/
#include <hip/hip_runtime.h>
#include <iostream>
int main()
{
int count = 0;
hipGetDeviceCount( &count );
std::cout << count << " device(s) found.\n";
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Detect the number of CUDA capable devices.
*/
#include <hip/hip_runtime.h>
#include <iostream>
int main()
{
int count = 0;
hipGetDeviceCount( &count );
std::cout << count << " device(s) found.\n";
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Detect the number of CUDA capable devices.
*/
#include <hip/hip_runtime.h>
#include <iostream>
int main()
{
int count = 0;
hipGetDeviceCount( &count );
std::cout << count << " device(s) found.\n";
return 0;
} | .text
.file "01-query.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $18, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " device(s) found.\n"
.size .L.str, 19
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00056019_00000000-6_01-query.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " device(s) found.\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "01-query.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $18, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " device(s) found.\n"
.size .L.str, 19
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <math.h>
using namespace std;
// Blocksize
#define BLOCKSIZE 1024
//*************************************************
// GLOBAL MEMORY VERSION OF THE ALGORITHM
// ************************************************
__global__ void vectorNS(float *in, float *out, int n, int ex) {
int i = threadIdx.x + blockDim.x * blockIdx.x + 2;
int iB = i - 2;
if (iB < n) {
float Aim2 = in[i - 2];
float Aim1 = in[i - 1];
float Ai = in[i];
float Aip1 = in[i + 1];
float Aip2 = in[i + 2];
out[iB] = (pow(Aim2, ex) + 2.0 * pow(Aim1, ex) + pow(Ai, ex) - 3.0 * pow(Aip1, ex) + 5.0 * pow(Aip2, ex)) / 24.0;
}
}
//*************************************************
// TILING VERSION (USES SHARED MEMORY) OF THE ALGORITHM
// ************************************************
__global__ void vectorS(float *in, float *out, int n, int ex) {
int li = threadIdx.x + 2; //local index in shared memory vector
int gi = blockDim.x * blockIdx.x + threadIdx.x + 2; // global memory index
int lstart = 0;
__shared__ float s_in[BLOCKSIZE + 4]; //shared mem. vector
// Load Tile in shared memory
if (gi < n + 3) {
s_in[li] = in[gi];
}
if (threadIdx.x == 0) { // First Thread (in the current block)
s_in[lstart] = in[gi - 2];
s_in[lstart + 1] = in[gi - 1];
}
if ((gi >= n + 1) || (threadIdx.x == BLOCKSIZE - 1)) { // Last Block || Last Thread
s_in[li + 1] = in[gi + 1];
s_in[li + 2] = in[gi + 2];
}
__syncthreads();
int iB = gi - 2;
if (iB < n) {
float Aim2 = s_in[li - 2];
float Aim1 = s_in[li - 1];
float Ai = s_in[li];
float Aip1 = s_in[li + 1];
float Aip2 = s_in[li + 2];
out[iB] = (pow(Aim2, ex) + 2.0 * pow(Aim1, ex) + pow(Ai, ex) - 3.0 * pow(Aip1, ex) + 5.0 * pow(Aip2, ex)) / 24.0;
}
}
//**************************************************************************
// FIND MAX IN VECTOR
__global__ void reduceMax(float * V_in, float * V_out, const int N) {
extern __shared__ float sdata[];
int tid = threadIdx.x;
int mid = blockDim.x/2;
int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
sdata[tid] = ((i < N) ? V_in[i] : -1);
sdata[tid + blockDim.x] = ((i + blockDim.x) < N ? V_in[i + blockDim.x] : -1);
__syncthreads();
for(int s = mid; s > 0; s >>= 1) {
if (tid < s) {
if(sdata[tid] < sdata[tid + s]) {
sdata[tid] = sdata[tid + s];
}
} else if((i + blockDim.x + s) < N) {
if(sdata[tid + mid] < sdata[tid + mid + s]) {
sdata[tid + mid] = sdata[tid + mid + s];
}
}
__syncthreads();
}
if (tid == 0) {
V_out[blockIdx.x * 2] = sdata[0];
} else if (tid == mid) {
V_out[(blockIdx.x * 2) + 1] = sdata[tid + mid];
}
}
//**************************************************************************
int main(int argc, char *argv[]) {
//******************************
//Get GPU information
int devID;
cudaDeviceProp props;
cudaError_t err;
err = cudaGetDevice(&devID);
if (err != cudaSuccess) {
cout << "ERRORRR" << endl;
}
cudaGetDeviceProperties(&props, devID);
printf("Device %d: \"%s\" with Compute %d.%d capability\n", devID, props.name, props.major, props.minor);
int N;
int ex;
if (argc != 3) {
cout << "Uso: transformacion Num_elementos Potencia " << endl;
return (0);
}
else {
N = atoi(argv[1]);
ex = atoi(argv[2]);
}
//* pointers to host memory */
float *A, *B;
//* Allocate arrays a, b and c on host*/
A = new float[N + 4];
B = new float[N];
float mx; // maximum of B
//* Initialize array A */
for (int i = 2; i < N + 2; i++)
A[i] = (float)(1 - (i % 100) * 0.001);
// Impose Boundary Conditions
A[0] = 0.0;
A[1] = 0.0;
A[N + 2] = 0.0;
A[N + 3] = 0.0;
//**************************
// GPU phase
//**************************
float *B_GPU_global = new float[N];
float *B_GPU_shared = new float[N];
int Nsize = N * sizeof(float);
int NsizeWithBound = (N + 4) * sizeof(float);
// Allocation in device mem
float *A_GPU = NULL;
err = cudaMalloc((void **)&A_GPU, NsizeWithBound);
if (err != cudaSuccess) {
cout << "ALLOCATION ERROR" << endl;
}
float *out = NULL;
err = cudaMalloc((void **)&out, Nsize);
if (err != cudaSuccess) {
cout << "ALLOCATION ERROR" << endl;
}
// Copy A values to device memory
err = cudaMemcpy(A_GPU, A, NsizeWithBound, cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
cout << "GPU COPY ERROR" << endl;
}
int blocksPerGrid = (int)ceil((float)(N) / BLOCKSIZE);
// Shared memory
// Take initial time
cout << "Start GPU Shared" << endl;
cudaDeviceSynchronize();
double gst1 = clock();
int smemSizeVec = (BLOCKSIZE + 4)*sizeof(float);
cout << endl;
// ********* Kernel Launch ************************************
vectorS<<<blocksPerGrid, BLOCKSIZE, smemSizeVec>>>(A_GPU, out, N, ex);
// ************************************************************
cudaDeviceSynchronize();
double TgpuS = clock();
TgpuS = (TgpuS - gst1) / CLOCKS_PER_SEC;
cout << "End GPU shared" << endl;
err = cudaGetLastError();
if (err != cudaSuccess) {
fprintf(stderr, "Failed to launch kernel! %d \n", err);
exit(EXIT_FAILURE);
}
cudaMemcpy(B_GPU_shared, out, Nsize, cudaMemcpyDeviceToHost);
// Global memory
// Take initial time
cout << "Start GPU Global" << endl;
cudaDeviceSynchronize();
double ggt1 = clock();
cout << endl;
// ********* Kernel Launch ************************************
vectorNS<<<blocksPerGrid, BLOCKSIZE>>>(A_GPU, out, N, ex);
// ************************************************************
cudaDeviceSynchronize();
double TgpuG = clock();
TgpuG = (TgpuG - ggt1) / CLOCKS_PER_SEC;
cout << "End GPU global" << endl;
err = cudaGetLastError();
if (err != cudaSuccess) {
fprintf(stderr, "Failed to launch kernel! %d \n", err);
exit(EXIT_FAILURE);
}
cudaMemcpy(B_GPU_global, out, Nsize, cudaMemcpyDeviceToHost);
//**************************
// CPU phase
//**************************
cout << "Start CPU" << endl;
// Time measurement
double ct1 = clock();
float Ai, Aim1, Aim2, Aip1, Aip2;
// Compute B[i] and mx
for (int i = 2; i < N + 2; i++) {
const int iB = i - 2;
Aim2 = A[i - 2];
Aim1 = A[i - 1];
Ai = A[i];
Aip1 = A[i + 1];
Aip2 = A[i + 2];
B[iB] = (pow(Aim2, ex) + 2.0 * pow(Aim1, ex) + pow(Ai, ex) - 3.0 * pow(Aip1, ex) + 5.0 * pow(Aip2, ex)) / 24.0;
mx = (iB == 0) ? B[0] : max(B[iB], mx);
}
double Tcpu = clock();
Tcpu = (Tcpu - ct1) / CLOCKS_PER_SEC;
cout << "End CPU" << endl;
//**************************
// CPU-GPU comparison and error checking
//**************************
int passed = 1;
int i = 0;
while (passed && i < N) {
float diff = fabs(B[i] - B_GPU_global[i]);
if (diff > 0) {
passed = 0;
cout << endl << i << endl;
cout << "DIFF= " << diff << endl;
}
i++;
}
if (passed) {
cout << "PASSED TEST GLOBAL MEMORY!!!" << endl;
}
else {
cout << "ERROR IN TEST GLOBAL MEMORY!!!" << endl;
}
passed = 1;
i = 0;
while (passed && i < N) {
float diff = fabs(B[i] - B_GPU_shared[i]);
if (diff > 0) {
passed = 0;
cout << endl << i << endl;
cout << "DIFF= " << diff << endl;
}
i++;
}
if (passed) {
cout << "PASSED TEST SHARED MEMORY!!!" << endl;
}
else {
cout << "ERROR IN TEST SHARED MEMORY!!!" << endl;
}
// c_d Maximum computation on GPU
dim3 threadsPerBlock(BLOCKSIZE);
dim3 numBlocks( ceil ((float)(N / 2)/threadsPerBlock.x));
// Maximum vector on CPU
float * vmax;
vmax = (float*) malloc(2*numBlocks.x*sizeof(float));
// Maximum vector to be computed on GPU
float *vmax_d;
cudaMalloc ((void **) &vmax_d, sizeof(float)*2*numBlocks.x);
float smemSize = 2*threadsPerBlock.x*sizeof(float);
// Kernel launch to compute Minimum Vector
reduceMax<<<numBlocks, threadsPerBlock, smemSize>>>(out,vmax_d, N);
/* Copy data from device memory to host memory */
cudaMemcpy(vmax, vmax_d, 2*numBlocks.x*sizeof(float),cudaMemcpyDeviceToHost);
// Perform final reduction in CPU
float max_gpu = -1;
for (int i=0; i<numBlocks.x; i++) {
max_gpu =max(max_gpu,vmax[i]);
}
if (N < 16) {
for (int i = 0; i < N; i++) {
cout << "CPU[" << i << "] = " << B[i] << ", GPU[" << i << "] = " << B_GPU_global[i] << endl;
}
}
cout << "................................." << endl;
cout << "................................." << endl
<< "El valor máximo en B es (CPU): " << mx << endl;
cout << "................................." << endl
<< "El valor máximo en B es (GPU): " << max_gpu << endl;
cout << endl
<< "Tiempo gastado CPU= " << Tcpu << endl
<< endl;
cout << endl
<< "Tiempo gastado GPU (SHARED MEMORY)= " << TgpuS << endl
<< endl;
cout << endl
<< "Speedup GPU (SHARED MEMORY)= " << Tcpu / TgpuS << endl
<< endl;
cout << endl
<< "Tiempo gastado GPU (GLOBAL MEMORY)= " << TgpuG << endl
<< endl;
cout << endl
<< "Speedup GPU (GLOBAL MEMORY)= " << Tcpu / TgpuG << endl
<< endl;
//* Free the memory */
delete (A);
delete (B);
cudaFree(A_GPU);
cudaFree(B_GPU_global);
cudaFree(out);
} | .file "tmpxft_00184ff9_00000000-6_vector.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8vectorNSPfS_iiPfS_ii
.type _Z31__device_stub__Z8vectorNSPfS_iiPfS_ii, @function
_Z31__device_stub__Z8vectorNSPfS_iiPfS_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8vectorNSPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z31__device_stub__Z8vectorNSPfS_iiPfS_ii, .-_Z31__device_stub__Z8vectorNSPfS_iiPfS_ii
.globl _Z8vectorNSPfS_ii
.type _Z8vectorNSPfS_ii, @function
_Z8vectorNSPfS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8vectorNSPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8vectorNSPfS_ii, .-_Z8vectorNSPfS_ii
.globl _Z30__device_stub__Z7vectorSPfS_iiPfS_ii
.type _Z30__device_stub__Z7vectorSPfS_iiPfS_ii, @function
_Z30__device_stub__Z7vectorSPfS_iiPfS_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7vectorSPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z30__device_stub__Z7vectorSPfS_iiPfS_ii, .-_Z30__device_stub__Z7vectorSPfS_iiPfS_ii
.globl _Z7vectorSPfS_ii
.type _Z7vectorSPfS_ii, @function
_Z7vectorSPfS_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7vectorSPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z7vectorSPfS_ii, .-_Z7vectorSPfS_ii
.globl _Z31__device_stub__Z9reduceMaxPfS_iPfS_i
.type _Z31__device_stub__Z9reduceMaxPfS_iPfS_i, @function
_Z31__device_stub__Z9reduceMaxPfS_iPfS_i:
.LFB3698:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reduceMaxPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z31__device_stub__Z9reduceMaxPfS_iPfS_i, .-_Z31__device_stub__Z9reduceMaxPfS_iPfS_i
.globl _Z9reduceMaxPfS_i
.type _Z9reduceMaxPfS_i, @function
_Z9reduceMaxPfS_i:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reduceMaxPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z9reduceMaxPfS_i, .-_Z9reduceMaxPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "ERRORRR"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Device %d: \"%s\" with Compute %d.%d capability\n"
.align 8
.LC3:
.string "Uso: transformacion Num_elementos Potencia "
.section .rodata.str1.1
.LC7:
.string "ALLOCATION ERROR"
.LC8:
.string "GPU COPY ERROR"
.LC10:
.string "Start GPU Shared"
.LC12:
.string "End GPU shared"
.LC13:
.string "Failed to launch kernel! %d \n"
.LC14:
.string "Start GPU Global"
.LC15:
.string "End GPU global"
.LC16:
.string "Start CPU"
.LC21:
.string "DIFF= "
.section .rodata.str1.8
.align 8
.LC22:
.string "ERROR IN TEST GLOBAL MEMORY!!!"
.section .rodata.str1.1
.LC23:
.string "PASSED TEST GLOBAL MEMORY!!!"
.section .rodata.str1.8
.align 8
.LC24:
.string "ERROR IN TEST SHARED MEMORY!!!"
.section .rodata.str1.1
.LC25:
.string "PASSED TEST SHARED MEMORY!!!"
.LC26:
.string "CPU["
.LC27:
.string "] = "
.LC28:
.string ", GPU["
.section .rodata.str1.8
.align 8
.LC29:
.string "................................."
.align 8
.LC30:
.string "El valor m\303\241ximo en B es (CPU): "
.align 8
.LC31:
.string "El valor m\303\241ximo en B es (GPU): "
.section .rodata.str1.1
.LC32:
.string "Tiempo gastado CPU= "
.section .rodata.str1.8
.align 8
.LC33:
.string "Tiempo gastado GPU (SHARED MEMORY)= "
.section .rodata.str1.1
.LC34:
.string "Speedup GPU (SHARED MEMORY)= "
.section .rodata.str1.8
.align 8
.LC35:
.string "Tiempo gastado GPU (GLOBAL MEMORY)= "
.section .rodata.str1.1
.LC36:
.string "Speedup GPU (GLOBAL MEMORY)= "
.LC37:
.string "End CPU"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1208, %rsp
.cfi_def_cfa_offset 1264
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1192(%rsp)
xorl %eax, %eax
leaq 108(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
jne .L110
.L28:
leaq 160(%rsp), %r12
movl 108(%rsp), %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 524(%rsp), %r9d
movl 520(%rsp), %r8d
movq %r12, %rcx
movl 108(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $3, %ebp
je .L29
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L30:
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L111
movl $0, %eax
addq $1208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L110:
.cfi_restore_state
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L28
.L29:
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq %rax, 48(%rsp)
movl %eax, 60(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, (%rsp)
leal 4(%r14), %r12d
movslq %r12d, %r15
movabsq $2305843009213693950, %rax
cmpq %r15, %rax
jb .L31
salq $2, %r15
movq %r15, %rdi
call _Znam@PLT
movq %rax, %rbx
movslq %r14d, %r13
movabsq $2305843009213693950, %rax
cmpq %r13, %rax
jb .L112
leaq -16(%r15), %r14
movq %r14, %rdi
call _Znam@PLT
movq %rax, %rbp
movl 48(%rsp), %eax
addl $1, %eax
movl %eax, 28(%rsp)
cmpl $1, %eax
jle .L36
movq 48(%rsp), %rax
leal -1(%rax), %ecx
addq $3, %rcx
movl $2, %edx
movsd .LC4(%rip), %xmm3
movsd .LC5(%rip), %xmm2
.L38:
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %edx, %esi
sarl $31, %esi
subl %esi, %eax
imull $100, %eax, %eax
movl %edx, %esi
subl %eax, %esi
pxor %xmm1, %xmm1
cvtsi2sdl %esi, %xmm1
mulsd %xmm3, %xmm1
movapd %xmm2, %xmm0
subsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%rdx,4)
addq $1, %rdx
cmpq %rcx, %rdx
jne .L38
.L36:
movl $0x00000000, (%rbx)
movl $0x00000000, 4(%rbx)
movl $0x00000000, -8(%rbx,%r15)
movl $0x00000000, -4(%rbx,%r15)
movq %r14, %rdi
call _Znam@PLT
movq %rax, 64(%rsp)
movq %r14, %rdi
call _Znam@PLT
movq %rax, %r14
sall $2, %r13d
movq $0, 112(%rsp)
sall $2, %r12d
movslq %r12d, %r12
leaq 112(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L113
.L39:
movq $0, 120(%rsp)
movslq %r13d, %r15
leaq 120(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L114
.L40:
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L115
.L41:
pxor %xmm0, %xmm0
cvtsi2ssl 48(%rsp), %xmm0
mulss .LC9(%rip), %xmm0
call ceilf@PLT
movss %xmm0, 16(%rsp)
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaDeviceSynchronize@PLT
call clock@PLT
pxor %xmm7, %xmm7
cvtsi2sdq %rax, %xmm7
movsd %xmm7, 8(%rsp)
movq %r12, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1024, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
cvttss2sil 16(%rsp), %r13d
movl %r13d, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $0, %r9d
movl $4112, %r8d
movq 148(%rsp), %rdx
movl $1, %ecx
movq 136(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L116
.L42:
call cudaDeviceSynchronize@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd 8(%rsp), %xmm0
divsd .LC11(%rip), %xmm0
movsd %xmm0, 72(%rsp)
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L117
movl $2, %ecx
movq %r15, %rdx
movq 120(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaDeviceSynchronize@PLT
call clock@PLT
pxor %xmm6, %xmm6
cvtsi2sdq %rax, %xmm6
movsd %xmm6, 8(%rsp)
movq %r12, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1024, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl %r13d, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 148(%rsp), %rdx
movl $1, %ecx
movq 136(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L118
.L44:
call cudaDeviceSynchronize@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd 8(%rsp), %xmm0
divsd .LC11(%rip), %xmm0
movsd %xmm0, 80(%rsp)
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L119
movl $2, %ecx
movq %r15, %rdx
movq 120(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
pxor %xmm5, %xmm5
cvtsi2sdq %rax, %xmm5
movsd %xmm5, 88(%rsp)
cmpl $1, 28(%rsp)
jle .L46
movq 48(%rsp), %rax
leal -1(%rax), %r15d
movl $0, %r12d
pxor %xmm6, %xmm6
cvtsi2sdl (%rsp), %xmm6
movq %xmm6, %r13
jmp .L49
.L31:
movq 1192(%rsp), %rax
subq %fs:40, %rax
je .L34
call __stack_chk_fail@PLT
.L34:
call __cxa_throw_bad_array_new_length@PLT
.L112:
movq 1192(%rsp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L37:
call __cxa_throw_bad_array_new_length@PLT
.L113:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L39
.L114:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L40
.L115:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L41
.L116:
movl (%rsp), %ecx
movl 60(%rsp), %edx
movq 120(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z30__device_stub__Z7vectorSPfS_iiPfS_ii
jmp .L42
.L117:
movl %eax, %ecx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L118:
movl (%rsp), %ecx
movl 60(%rsp), %edx
movq 120(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z31__device_stub__Z8vectorNSPfS_iiPfS_ii
jmp .L44
.L119:
movl %eax, %ecx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movss 56(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 56(%rsp)
.L48:
leaq 1(%r12), %rax
cmpq %r15, %r12
je .L120
movq %rax, %r12
.L49:
movss 4(%rbx,%r12,4), %xmm5
movss %xmm5, (%rsp)
movss 8(%rbx,%r12,4), %xmm6
movss %xmm6, 8(%rsp)
movss 12(%rbx,%r12,4), %xmm7
movss %xmm7, 16(%rsp)
movss 16(%rbx,%r12,4), %xmm3
movss %xmm3, 28(%rsp)
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12,4), %xmm0
movq %r13, %xmm1
call pow@PLT
movsd %xmm0, 40(%rsp)
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
movq %r13, %xmm1
call pow@PLT
movsd %xmm0, 32(%rsp)
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
movq %r13, %xmm1
call pow@PLT
movsd %xmm0, 8(%rsp)
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
movq %r13, %xmm1
call pow@PLT
movsd %xmm0, (%rsp)
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
movq %r13, %xmm1
call pow@PLT
movapd %xmm0, %xmm1
movsd 32(%rsp), %xmm4
addsd %xmm4, %xmm4
movapd %xmm4, %xmm0
addsd 40(%rsp), %xmm0
addsd 8(%rsp), %xmm0
movsd .LC17(%rip), %xmm2
mulsd (%rsp), %xmm2
subsd %xmm2, %xmm0
mulsd .LC18(%rip), %xmm1
addsd %xmm1, %xmm0
divsd .LC19(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%r12,4)
testl %r12d, %r12d
jne .L47
movss 0(%rbp), %xmm3
movss %xmm3, 56(%rsp)
jmp .L48
.L124:
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L121
call _ZSt16__throw_bad_castv@PLT
.L121:
call __stack_chk_fail@PLT
.L55:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L56
.L125:
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L122
call _ZSt16__throw_bad_castv@PLT
.L122:
call __stack_chk_fail@PLT
.L59:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L60
.L126:
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L123
call _ZSt16__throw_bad_castv@PLT
.L123:
call __stack_chk_fail@PLT
.L63:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L64
.L106:
leaq 1(%r12), %rax
cmpq %rdx, %r12
je .L93
movq %rax, %r12
.L66:
movss 0(%rbp,%r12,4), %xmm0
subss (%rcx,%r12,4), %xmm0
andps %xmm2, %xmm0
movss %xmm0, (%rsp)
comiss %xmm1, %xmm0
jbe .L106
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %r13
testq %r13, %r13
je .L124
cmpb $0, 56(%r13)
je .L55
movzbl 67(%r13), %esi
.L56:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L125
cmpb $0, 56(%r13)
je .L59
movzbl 67(%r13), %esi
.L60:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $6, %edx
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L126
cmpb $0, 56(%r13)
je .L63
movzbl 67(%r13), %esi
.L64:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L65:
movq 48(%rsp), %rax
leal -1(%rax), %edx
movl $0, %r12d
movss .LC20(%rip), %xmm2
pxor %xmm1, %xmm1
jmp .L83
.L130:
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L127
call _ZSt16__throw_bad_castv@PLT
.L127:
call __stack_chk_fail@PLT
.L72:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L73
.L131:
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L128
call _ZSt16__throw_bad_castv@PLT
.L128:
call __stack_chk_fail@PLT
.L76:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L77
.L132:
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L129
call _ZSt16__throw_bad_castv@PLT
.L129:
call __stack_chk_fail@PLT
.L80:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L81
.L107:
leaq 1(%r12), %rax
cmpq %r12, %rdx
je .L67
movq %rax, %r12
.L83:
movss 0(%rbp,%r12,4), %xmm0
subss (%r14,%r12,4), %xmm0
andps %xmm2, %xmm0
movss %xmm0, (%rsp)
comiss %xmm1, %xmm0
jbe .L107
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %r13
testq %r13, %r13
je .L130
cmpb $0, 56(%r13)
je .L72
movzbl 67(%r13), %esi
.L73:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L131
cmpb $0, 56(%r13)
je .L76
movzbl 67(%r13), %esi
.L77:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $6, %edx
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L132
cmpb $0, 56(%r13)
je .L80
movzbl 67(%r13), %esi
.L81:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq .LC24(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L82:
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $2, %ecx
movl 60(%rsp), %eax
cltd
idivl %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC9(%rip), %xmm0
call ceilf@PLT
cvttss2siq %xmm0, %r12
movl $1, 152(%rsp)
movl $1, 156(%rsp)
leal (%r12,%r12), %eax
movl %eax, %eax
leaq 0(,%rax,4), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movl %r12d, %r13d
leaq 0(,%r13,8), %rsi
leaq 128(%rsp), %rdi
call cudaMalloc@PLT
movl %r12d, 148(%rsp)
movl $1024, 136(%rsp)
movl 144(%rsp), %ecx
movl $0, %r9d
movl $8192, %r8d
movq 136(%rsp), %rdx
movq 148(%rsp), %rdi
movl 156(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L133
.L84:
movl $2, %ecx
movq %r15, %rdx
movq 128(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %r12d, %r12d
je .L98
movq %r14, %r12
leaq (%r14,%r13,4), %r13
movss .LC0(%rip), %xmm7
movss %xmm7, (%rsp)
.L86:
movss (%r12), %xmm0
movss (%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, (%rsp)
addq $4, %r12
cmpq %r13, %r12
jne .L86
.L85:
movl 48(%rsp), %eax
subl $1, %eax
cmpl $14, %eax
ja .L87
movl $0, %r12d
leaq _ZSt4cout(%rip), %r14
movq %rbx, 16(%rsp)
movq 64(%rsp), %r13
jmp .L92
.L133:
movl 60(%rsp), %edx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call _Z31__device_stub__Z9reduceMaxPfS_iPfS_i
jmp .L84
.L98:
movss .LC0(%rip), %xmm6
movss %xmm6, (%rsp)
jmp .L85
.L136:
movq 1192(%rsp), %rax
subq %fs:40, %rax
jne .L134
call _ZSt16__throw_bad_castv@PLT
.L134:
call __stack_chk_fail@PLT
.L90:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L91:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %r12
cmpl %r12d, 60(%rsp)
jle .L135
.L92:
movl $4, %edx
leaq .LC26(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $4, %edx
leaq .LC27(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r12,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $6, %edx
leaq .LC28(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $4, %edx
leaq .LC27(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%r12,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L136
cmpb $0, 56(%r15)
je .L90
movzbl 67(%r15), %esi
jmp .L91
.L135:
movq 16(%rsp), %rbx
.L87:
leaq .LC29(%rip), %r13
movq %r13, %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC30(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 56(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC31(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC32(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC33(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 72(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC34(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm3
divsd 72(%rsp), %xmm3
movapd %xmm3, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC35(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 80(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC36(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm3
divsd 80(%rsp), %xmm3
movapd %xmm3, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
jmp .L30
.L46:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd 88(%rsp), %xmm0
divsd .LC11(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC37(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L93:
leaq .LC23(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 48(%rsp)
jg .L65
.L67:
leaq .LC25(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L82
.L120:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd 88(%rsp), %xmm0
divsd .LC11(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC37(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 48(%rsp), %rax
leal -1(%rax), %edx
movl $0, %r12d
movss .LC20(%rip), %xmm2
pxor %xmm1, %xmm1
movq 64(%rsp), %rcx
jmp .L66
.L111:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC38:
.string "_Z9reduceMaxPfS_i"
.LC39:
.string "_Z7vectorSPfS_ii"
.LC40:
.string "_Z8vectorNSPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC38(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reduceMaxPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC39(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vectorSPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC40(%rip), %rdx
movq %rdx, %rcx
leaq _Z8vectorNSPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long -1082130432
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long -755914244
.long 1062232653
.align 8
.LC5:
.long 0
.long 1072693248
.section .rodata.cst4
.align 4
.LC9:
.long 981467136
.section .rodata.cst8
.align 8
.LC11:
.long 0
.long 1093567616
.align 8
.LC17:
.long 0
.long 1074266112
.align 8
.LC18:
.long 0
.long 1075052544
.align 8
.LC19:
.long 0
.long 1077411840
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC20:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <math.h>
using namespace std;
// Blocksize
#define BLOCKSIZE 1024
//*************************************************
// GLOBAL MEMORY VERSION OF THE ALGORITHM
// ************************************************
__global__ void vectorNS(float *in, float *out, int n, int ex) {
int i = threadIdx.x + blockDim.x * blockIdx.x + 2;
int iB = i - 2;
if (iB < n) {
float Aim2 = in[i - 2];
float Aim1 = in[i - 1];
float Ai = in[i];
float Aip1 = in[i + 1];
float Aip2 = in[i + 2];
out[iB] = (pow(Aim2, ex) + 2.0 * pow(Aim1, ex) + pow(Ai, ex) - 3.0 * pow(Aip1, ex) + 5.0 * pow(Aip2, ex)) / 24.0;
}
}
//*************************************************
// TILING VERSION (USES SHARED MEMORY) OF THE ALGORITHM
// ************************************************
__global__ void vectorS(float *in, float *out, int n, int ex) {
int li = threadIdx.x + 2; //local index in shared memory vector
int gi = blockDim.x * blockIdx.x + threadIdx.x + 2; // global memory index
int lstart = 0;
__shared__ float s_in[BLOCKSIZE + 4]; //shared mem. vector
// Load Tile in shared memory
if (gi < n + 3) {
s_in[li] = in[gi];
}
if (threadIdx.x == 0) { // First Thread (in the current block)
s_in[lstart] = in[gi - 2];
s_in[lstart + 1] = in[gi - 1];
}
if ((gi >= n + 1) || (threadIdx.x == BLOCKSIZE - 1)) { // Last Block || Last Thread
s_in[li + 1] = in[gi + 1];
s_in[li + 2] = in[gi + 2];
}
__syncthreads();
int iB = gi - 2;
if (iB < n) {
float Aim2 = s_in[li - 2];
float Aim1 = s_in[li - 1];
float Ai = s_in[li];
float Aip1 = s_in[li + 1];
float Aip2 = s_in[li + 2];
out[iB] = (pow(Aim2, ex) + 2.0 * pow(Aim1, ex) + pow(Ai, ex) - 3.0 * pow(Aip1, ex) + 5.0 * pow(Aip2, ex)) / 24.0;
}
}
//**************************************************************************
// FIND MAX IN VECTOR
__global__ void reduceMax(float * V_in, float * V_out, const int N) {
extern __shared__ float sdata[];
int tid = threadIdx.x;
int mid = blockDim.x/2;
int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
sdata[tid] = ((i < N) ? V_in[i] : -1);
sdata[tid + blockDim.x] = ((i + blockDim.x) < N ? V_in[i + blockDim.x] : -1);
__syncthreads();
for(int s = mid; s > 0; s >>= 1) {
if (tid < s) {
if(sdata[tid] < sdata[tid + s]) {
sdata[tid] = sdata[tid + s];
}
} else if((i + blockDim.x + s) < N) {
if(sdata[tid + mid] < sdata[tid + mid + s]) {
sdata[tid + mid] = sdata[tid + mid + s];
}
}
__syncthreads();
}
if (tid == 0) {
V_out[blockIdx.x * 2] = sdata[0];
} else if (tid == mid) {
V_out[(blockIdx.x * 2) + 1] = sdata[tid + mid];
}
}
//**************************************************************************
int main(int argc, char *argv[]) {
//******************************
//Get GPU information
int devID;
cudaDeviceProp props;
cudaError_t err;
err = cudaGetDevice(&devID);
if (err != cudaSuccess) {
cout << "ERRORRR" << endl;
}
cudaGetDeviceProperties(&props, devID);
printf("Device %d: \"%s\" with Compute %d.%d capability\n", devID, props.name, props.major, props.minor);
int N;
int ex;
if (argc != 3) {
cout << "Uso: transformacion Num_elementos Potencia " << endl;
return (0);
}
else {
N = atoi(argv[1]);
ex = atoi(argv[2]);
}
//* pointers to host memory */
float *A, *B;
//* Allocate arrays a, b and c on host*/
A = new float[N + 4];
B = new float[N];
float mx; // maximum of B
//* Initialize array A */
for (int i = 2; i < N + 2; i++)
A[i] = (float)(1 - (i % 100) * 0.001);
// Impose Boundary Conditions
A[0] = 0.0;
A[1] = 0.0;
A[N + 2] = 0.0;
A[N + 3] = 0.0;
//**************************
// GPU phase
//**************************
float *B_GPU_global = new float[N];
float *B_GPU_shared = new float[N];
int Nsize = N * sizeof(float);
int NsizeWithBound = (N + 4) * sizeof(float);
// Allocation in device mem
float *A_GPU = NULL;
err = cudaMalloc((void **)&A_GPU, NsizeWithBound);
if (err != cudaSuccess) {
cout << "ALLOCATION ERROR" << endl;
}
float *out = NULL;
err = cudaMalloc((void **)&out, Nsize);
if (err != cudaSuccess) {
cout << "ALLOCATION ERROR" << endl;
}
// Copy A values to device memory
err = cudaMemcpy(A_GPU, A, NsizeWithBound, cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
cout << "GPU COPY ERROR" << endl;
}
int blocksPerGrid = (int)ceil((float)(N) / BLOCKSIZE);
// Shared memory
// Take initial time
cout << "Start GPU Shared" << endl;
cudaDeviceSynchronize();
double gst1 = clock();
int smemSizeVec = (BLOCKSIZE + 4)*sizeof(float);
cout << endl;
// ********* Kernel Launch ************************************
vectorS<<<blocksPerGrid, BLOCKSIZE, smemSizeVec>>>(A_GPU, out, N, ex);
// ************************************************************
cudaDeviceSynchronize();
double TgpuS = clock();
TgpuS = (TgpuS - gst1) / CLOCKS_PER_SEC;
cout << "End GPU shared" << endl;
err = cudaGetLastError();
if (err != cudaSuccess) {
fprintf(stderr, "Failed to launch kernel! %d \n", err);
exit(EXIT_FAILURE);
}
cudaMemcpy(B_GPU_shared, out, Nsize, cudaMemcpyDeviceToHost);
// Global memory
// Take initial time
cout << "Start GPU Global" << endl;
cudaDeviceSynchronize();
double ggt1 = clock();
cout << endl;
// ********* Kernel Launch ************************************
vectorNS<<<blocksPerGrid, BLOCKSIZE>>>(A_GPU, out, N, ex);
// ************************************************************
cudaDeviceSynchronize();
double TgpuG = clock();
TgpuG = (TgpuG - ggt1) / CLOCKS_PER_SEC;
cout << "End GPU global" << endl;
err = cudaGetLastError();
if (err != cudaSuccess) {
fprintf(stderr, "Failed to launch kernel! %d \n", err);
exit(EXIT_FAILURE);
}
cudaMemcpy(B_GPU_global, out, Nsize, cudaMemcpyDeviceToHost);
//**************************
// CPU phase
//**************************
cout << "Start CPU" << endl;
// Time measurement
double ct1 = clock();
float Ai, Aim1, Aim2, Aip1, Aip2;
// Compute B[i] and mx
for (int i = 2; i < N + 2; i++) {
const int iB = i - 2;
Aim2 = A[i - 2];
Aim1 = A[i - 1];
Ai = A[i];
Aip1 = A[i + 1];
Aip2 = A[i + 2];
B[iB] = (pow(Aim2, ex) + 2.0 * pow(Aim1, ex) + pow(Ai, ex) - 3.0 * pow(Aip1, ex) + 5.0 * pow(Aip2, ex)) / 24.0;
mx = (iB == 0) ? B[0] : max(B[iB], mx);
}
double Tcpu = clock();
Tcpu = (Tcpu - ct1) / CLOCKS_PER_SEC;
cout << "End CPU" << endl;
//**************************
// CPU-GPU comparison and error checking
//**************************
int passed = 1;
int i = 0;
while (passed && i < N) {
float diff = fabs(B[i] - B_GPU_global[i]);
if (diff > 0) {
passed = 0;
cout << endl << i << endl;
cout << "DIFF= " << diff << endl;
}
i++;
}
if (passed) {
cout << "PASSED TEST GLOBAL MEMORY!!!" << endl;
}
else {
cout << "ERROR IN TEST GLOBAL MEMORY!!!" << endl;
}
passed = 1;
i = 0;
while (passed && i < N) {
float diff = fabs(B[i] - B_GPU_shared[i]);
if (diff > 0) {
passed = 0;
cout << endl << i << endl;
cout << "DIFF= " << diff << endl;
}
i++;
}
if (passed) {
cout << "PASSED TEST SHARED MEMORY!!!" << endl;
}
else {
cout << "ERROR IN TEST SHARED MEMORY!!!" << endl;
}
// c_d Maximum computation on GPU
dim3 threadsPerBlock(BLOCKSIZE);
dim3 numBlocks( ceil ((float)(N / 2)/threadsPerBlock.x));
// Maximum vector on CPU
float * vmax;
vmax = (float*) malloc(2*numBlocks.x*sizeof(float));
// Maximum vector to be computed on GPU
float *vmax_d;
cudaMalloc ((void **) &vmax_d, sizeof(float)*2*numBlocks.x);
float smemSize = 2*threadsPerBlock.x*sizeof(float);
// Kernel launch to compute Minimum Vector
reduceMax<<<numBlocks, threadsPerBlock, smemSize>>>(out,vmax_d, N);
/* Copy data from device memory to host memory */
cudaMemcpy(vmax, vmax_d, 2*numBlocks.x*sizeof(float),cudaMemcpyDeviceToHost);
// Perform final reduction in CPU
float max_gpu = -1;
for (int i=0; i<numBlocks.x; i++) {
max_gpu =max(max_gpu,vmax[i]);
}
if (N < 16) {
for (int i = 0; i < N; i++) {
cout << "CPU[" << i << "] = " << B[i] << ", GPU[" << i << "] = " << B_GPU_global[i] << endl;
}
}
cout << "................................." << endl;
cout << "................................." << endl
<< "El valor máximo en B es (CPU): " << mx << endl;
cout << "................................." << endl
<< "El valor máximo en B es (GPU): " << max_gpu << endl;
cout << endl
<< "Tiempo gastado CPU= " << Tcpu << endl
<< endl;
cout << endl
<< "Tiempo gastado GPU (SHARED MEMORY)= " << TgpuS << endl
<< endl;
cout << endl
<< "Speedup GPU (SHARED MEMORY)= " << Tcpu / TgpuS << endl
<< endl;
cout << endl
<< "Tiempo gastado GPU (GLOBAL MEMORY)= " << TgpuG << endl
<< endl;
cout << endl
<< "Speedup GPU (GLOBAL MEMORY)= " << Tcpu / TgpuG << endl
<< endl;
//* Free the memory */
delete (A);
delete (B);
cudaFree(A_GPU);
cudaFree(B_GPU_global);
cudaFree(out);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <math.h>
using namespace std;
// Blocksize
#define BLOCKSIZE 1024
//*************************************************
// GLOBAL MEMORY VERSION OF THE ALGORITHM
// ************************************************
__global__ void vectorNS(float *in, float *out, int n, int ex) {
int i = threadIdx.x + blockDim.x * blockIdx.x + 2;
int iB = i - 2;
if (iB < n) {
float Aim2 = in[i - 2];
float Aim1 = in[i - 1];
float Ai = in[i];
float Aip1 = in[i + 1];
float Aip2 = in[i + 2];
out[iB] = (pow(Aim2, ex) + 2.0 * pow(Aim1, ex) + pow(Ai, ex) - 3.0 * pow(Aip1, ex) + 5.0 * pow(Aip2, ex)) / 24.0;
}
}
//*************************************************
// TILING VERSION (USES SHARED MEMORY) OF THE ALGORITHM
// ************************************************
__global__ void vectorS(float *in, float *out, int n, int ex) {
int li = threadIdx.x + 2; //local index in shared memory vector
int gi = blockDim.x * blockIdx.x + threadIdx.x + 2; // global memory index
int lstart = 0;
__shared__ float s_in[BLOCKSIZE + 4]; //shared mem. vector
// Load Tile in shared memory
if (gi < n + 3) {
s_in[li] = in[gi];
}
if (threadIdx.x == 0) { // First Thread (in the current block)
s_in[lstart] = in[gi - 2];
s_in[lstart + 1] = in[gi - 1];
}
if ((gi >= n + 1) || (threadIdx.x == BLOCKSIZE - 1)) { // Last Block || Last Thread
s_in[li + 1] = in[gi + 1];
s_in[li + 2] = in[gi + 2];
}
__syncthreads();
int iB = gi - 2;
if (iB < n) {
float Aim2 = s_in[li - 2];
float Aim1 = s_in[li - 1];
float Ai = s_in[li];
float Aip1 = s_in[li + 1];
float Aip2 = s_in[li + 2];
out[iB] = (pow(Aim2, ex) + 2.0 * pow(Aim1, ex) + pow(Ai, ex) - 3.0 * pow(Aip1, ex) + 5.0 * pow(Aip2, ex)) / 24.0;
}
}
//**************************************************************************
// FIND MAX IN VECTOR
__global__ void reduceMax(float * V_in, float * V_out, const int N) {
extern __shared__ float sdata[];
int tid = threadIdx.x;
int mid = blockDim.x/2;
int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
sdata[tid] = ((i < N) ? V_in[i] : -1);
sdata[tid + blockDim.x] = ((i + blockDim.x) < N ? V_in[i + blockDim.x] : -1);
__syncthreads();
for(int s = mid; s > 0; s >>= 1) {
if (tid < s) {
if(sdata[tid] < sdata[tid + s]) {
sdata[tid] = sdata[tid + s];
}
} else if((i + blockDim.x + s) < N) {
if(sdata[tid + mid] < sdata[tid + mid + s]) {
sdata[tid + mid] = sdata[tid + mid + s];
}
}
__syncthreads();
}
if (tid == 0) {
V_out[blockIdx.x * 2] = sdata[0];
} else if (tid == mid) {
V_out[(blockIdx.x * 2) + 1] = sdata[tid + mid];
}
}
//**************************************************************************
int main(int argc, char *argv[]) {
//******************************
//Get GPU information
int devID;
hipDeviceProp_t props;
hipError_t err;
err = hipGetDevice(&devID);
if (err != hipSuccess) {
cout << "ERRORRR" << endl;
}
hipGetDeviceProperties(&props, devID);
printf("Device %d: \"%s\" with Compute %d.%d capability\n", devID, props.name, props.major, props.minor);
int N;
int ex;
if (argc != 3) {
cout << "Uso: transformacion Num_elementos Potencia " << endl;
return (0);
}
else {
N = atoi(argv[1]);
ex = atoi(argv[2]);
}
//* pointers to host memory */
float *A, *B;
//* Allocate arrays a, b and c on host*/
A = new float[N + 4];
B = new float[N];
float mx; // maximum of B
//* Initialize array A */
for (int i = 2; i < N + 2; i++)
A[i] = (float)(1 - (i % 100) * 0.001);
// Impose Boundary Conditions
A[0] = 0.0;
A[1] = 0.0;
A[N + 2] = 0.0;
A[N + 3] = 0.0;
//**************************
// GPU phase
//**************************
float *B_GPU_global = new float[N];
float *B_GPU_shared = new float[N];
int Nsize = N * sizeof(float);
int NsizeWithBound = (N + 4) * sizeof(float);
// Allocation in device mem
float *A_GPU = NULL;
err = hipMalloc((void **)&A_GPU, NsizeWithBound);
if (err != hipSuccess) {
cout << "ALLOCATION ERROR" << endl;
}
float *out = NULL;
err = hipMalloc((void **)&out, Nsize);
if (err != hipSuccess) {
cout << "ALLOCATION ERROR" << endl;
}
// Copy A values to device memory
err = hipMemcpy(A_GPU, A, NsizeWithBound, hipMemcpyHostToDevice);
if (err != hipSuccess) {
cout << "GPU COPY ERROR" << endl;
}
int blocksPerGrid = (int)ceil((float)(N) / BLOCKSIZE);
// Shared memory
// Take initial time
cout << "Start GPU Shared" << endl;
hipDeviceSynchronize();
double gst1 = clock();
int smemSizeVec = (BLOCKSIZE + 4)*sizeof(float);
cout << endl;
// ********* Kernel Launch ************************************
vectorS<<<blocksPerGrid, BLOCKSIZE, smemSizeVec>>>(A_GPU, out, N, ex);
// ************************************************************
hipDeviceSynchronize();
double TgpuS = clock();
TgpuS = (TgpuS - gst1) / CLOCKS_PER_SEC;
cout << "End GPU shared" << endl;
err = hipGetLastError();
if (err != hipSuccess) {
fprintf(stderr, "Failed to launch kernel! %d \n", err);
exit(EXIT_FAILURE);
}
hipMemcpy(B_GPU_shared, out, Nsize, hipMemcpyDeviceToHost);
// Global memory
// Take initial time
cout << "Start GPU Global" << endl;
hipDeviceSynchronize();
double ggt1 = clock();
cout << endl;
// ********* Kernel Launch ************************************
vectorNS<<<blocksPerGrid, BLOCKSIZE>>>(A_GPU, out, N, ex);
// ************************************************************
hipDeviceSynchronize();
double TgpuG = clock();
TgpuG = (TgpuG - ggt1) / CLOCKS_PER_SEC;
cout << "End GPU global" << endl;
err = hipGetLastError();
if (err != hipSuccess) {
fprintf(stderr, "Failed to launch kernel! %d \n", err);
exit(EXIT_FAILURE);
}
hipMemcpy(B_GPU_global, out, Nsize, hipMemcpyDeviceToHost);
//**************************
// CPU phase
//**************************
cout << "Start CPU" << endl;
// Time measurement
double ct1 = clock();
float Ai, Aim1, Aim2, Aip1, Aip2;
// Compute B[i] and mx
for (int i = 2; i < N + 2; i++) {
const int iB = i - 2;
Aim2 = A[i - 2];
Aim1 = A[i - 1];
Ai = A[i];
Aip1 = A[i + 1];
Aip2 = A[i + 2];
B[iB] = (pow(Aim2, ex) + 2.0 * pow(Aim1, ex) + pow(Ai, ex) - 3.0 * pow(Aip1, ex) + 5.0 * pow(Aip2, ex)) / 24.0;
mx = (iB == 0) ? B[0] : max(B[iB], mx);
}
double Tcpu = clock();
Tcpu = (Tcpu - ct1) / CLOCKS_PER_SEC;
cout << "End CPU" << endl;
//**************************
// CPU-GPU comparison and error checking
//**************************
int passed = 1;
int i = 0;
while (passed && i < N) {
float diff = fabs(B[i] - B_GPU_global[i]);
if (diff > 0) {
passed = 0;
cout << endl << i << endl;
cout << "DIFF= " << diff << endl;
}
i++;
}
if (passed) {
cout << "PASSED TEST GLOBAL MEMORY!!!" << endl;
}
else {
cout << "ERROR IN TEST GLOBAL MEMORY!!!" << endl;
}
passed = 1;
i = 0;
while (passed && i < N) {
float diff = fabs(B[i] - B_GPU_shared[i]);
if (diff > 0) {
passed = 0;
cout << endl << i << endl;
cout << "DIFF= " << diff << endl;
}
i++;
}
if (passed) {
cout << "PASSED TEST SHARED MEMORY!!!" << endl;
}
else {
cout << "ERROR IN TEST SHARED MEMORY!!!" << endl;
}
// c_d Maximum computation on GPU
dim3 threadsPerBlock(BLOCKSIZE);
dim3 numBlocks( ceil ((float)(N / 2)/threadsPerBlock.x));
// Maximum vector on CPU
float * vmax;
vmax = (float*) malloc(2*numBlocks.x*sizeof(float));
// Maximum vector to be computed on GPU
float *vmax_d;
hipMalloc ((void **) &vmax_d, sizeof(float)*2*numBlocks.x);
float smemSize = 2*threadsPerBlock.x*sizeof(float);
// Kernel launch to compute Minimum Vector
reduceMax<<<numBlocks, threadsPerBlock, smemSize>>>(out,vmax_d, N);
/* Copy data from device memory to host memory */
hipMemcpy(vmax, vmax_d, 2*numBlocks.x*sizeof(float),hipMemcpyDeviceToHost);
// Perform final reduction in CPU
float max_gpu = -1;
for (int i=0; i<numBlocks.x; i++) {
max_gpu =max(max_gpu,vmax[i]);
}
if (N < 16) {
for (int i = 0; i < N; i++) {
cout << "CPU[" << i << "] = " << B[i] << ", GPU[" << i << "] = " << B_GPU_global[i] << endl;
}
}
cout << "................................." << endl;
cout << "................................." << endl
<< "El valor máximo en B es (CPU): " << mx << endl;
cout << "................................." << endl
<< "El valor máximo en B es (GPU): " << max_gpu << endl;
cout << endl
<< "Tiempo gastado CPU= " << Tcpu << endl
<< endl;
cout << endl
<< "Tiempo gastado GPU (SHARED MEMORY)= " << TgpuS << endl
<< endl;
cout << endl
<< "Speedup GPU (SHARED MEMORY)= " << Tcpu / TgpuS << endl
<< endl;
cout << endl
<< "Tiempo gastado GPU (GLOBAL MEMORY)= " << TgpuG << endl
<< endl;
cout << endl
<< "Speedup GPU (GLOBAL MEMORY)= " << Tcpu / TgpuG << endl
<< endl;
//* Free the memory */
delete (A);
delete (B);
hipFree(A_GPU);
hipFree(B_GPU_global);
hipFree(out);
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
//#define __OUTPUT_PIX__
#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];
__global__ void convert_to_luv_gpu_kernel(unsigned char *in_img, float *out_img, int cols, int rows, bool use_rgb)
{
float r, g, b, l, u, v, x, y, z, lt;
unsigned int x_pos = threadIdx.x + (blockDim.x * blockIdx.x);
unsigned int y_pos = threadIdx.y + (blockDim.y * blockIdx.y);
if ((x_pos < cols) && (y_pos < rows)) {
unsigned int pos = (y_pos * cols) + x_pos;
if (use_rgb) {
r = (float)in_img[(3 * pos)];
g = (float)in_img[(3 * pos) + 1];
b = (float)in_img[(3 * pos) + 2];
} else {
b = (float)in_img[(3 * pos)];
g = (float)in_img[(3 * pos) + 1];
r = (float)in_img[(3 * pos) + 2];
}
x = (mr_const[0] * r) + (mg_const[0] * g) + (mb_const[0] * b);
y = (mr_const[1] * r) + (mg_const[1] * g) + (mb_const[1] * b);
z = (mr_const[2] * r) + (mg_const[2] * g) + (mb_const[2] * b);
float maxi = 1.0f / 270;
float minu = -88.0f * maxi;
float minv = -134.0f * maxi;
float un = 0.197833f;
float vn = 0.468331f;
lt = lTable_const[static_cast<int>((y*1024))];
l = lt; z = 1/(x + (15 * y) + (3 * z) + (float)1e-35);
u = lt * (13 * 4 * x * z - 13 * un) - minu;
v = lt * (13 * 9 * y * z - 13 * vn) - minv;
out_img[(3 * pos)] = l;
out_img[(3 * pos) + 1] = u;
out_img[(3 * pos) + 2] = v;
}
} | code for sm_80
Function : _Z25convert_to_luv_gpu_kernelPhPfiib
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD R3, R3, 0x3, RZ ; /* 0x0000000303037824 */
/* 0x000fca00078e02ff */
/*00d0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ IADD3 R0, R3.reuse, 0x2, RZ ; /* 0x0000000203007810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ IADD3 R4, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fe40007f1e0ff */
/*0100*/ IADD3 R6, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */
/* 0x000fe40007f3e0ff */
/*0110*/ IADD3 R8, P2, R0, c[0x0][0x160], RZ ; /* 0x0000580000087a10 */
/* 0x000fe40007f5e0ff */
/*0120*/ IADD3.X R5, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff057a10 */
/* 0x000fe200007fe4ff */
/*0130*/ IMAD.X R7, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff077624 */
/* 0x000fe200008e06ff */
/*0140*/ IADD3.X R9, RZ, c[0x0][0x164], RZ, P2, !PT ; /* 0x00005900ff097a10 */
/* 0x000fc600017fe4ff */
/*0150*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1100 */
/*0160*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ee8000c1e1100 */
/*0170*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000f22000c1e1100 */
/*0180*/ ULDC.S8 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000200 */
/*0190*/ BSSY B0, 0x3b0 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*01a0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*01b0*/ I2F.U16 R10, R4 ; /* 0x00000004000a7306 */
/* 0x004ff00000101000 */
/*01c0*/ I2F.U16 R13, R8 ; /* 0x00000008000d7306 */
/* 0x008e300000101000 */
/*01d0*/ I2F.U16 R11, R6 ; /* 0x00000006000b7306 */
/* 0x010e620000101000 */
/*01e0*/ FSEL R12, R10, R13, P0 ; /* 0x0000000d0a0c7208 */
/* 0x001fc40000000000 */
/*01f0*/ FSEL R10, R13, R10, P0 ; /* 0x0000000a0d0a7208 */
/* 0x000fe20000000000 */
/*0200*/ FMUL R15, R11.reuse, c[0x3][0x10ac] ; /* 0x00c42b000b0f7a20 */
/* 0x042fe40000400000 */
/*0210*/ FMUL R5, R11.reuse, c[0x3][0x10b0] ; /* 0x00c42c000b057a20 */
/* 0x040fe40000400000 */
/*0220*/ FMUL R11, R11, c[0x3][0x10b4] ; /* 0x00c42d000b0b7a20 */
/* 0x000fe40000400000 */
/*0230*/ FFMA R15, R12.reuse, c[0x3][0x10a0], R15 ; /* 0x00c428000c0f7a23 */
/* 0x040fe4000000000f */
/*0240*/ FFMA R5, R12.reuse, c[0x3][0x10a4], R5 ; /* 0x00c429000c057a23 */
/* 0x040fe40000000005 */
/*0250*/ FFMA R11, R12, c[0x3][0x10a8], R11 ; /* 0x00c42a000c0b7a23 */
/* 0x000fc4000000000b */
/*0260*/ FFMA R4, R10.reuse, c[0x3][0x10b8], R15 ; /* 0x00c42e000a047a23 */
/* 0x040fe4000000000f */
/*0270*/ FFMA R5, R10.reuse, c[0x3][0x10bc], R5 ; /* 0x00c42f000a057a23 */
/* 0x040fe40000000005 */
/*0280*/ FFMA R11, R10, c[0x3][0x10c0], R11 ; /* 0x00c430000a0b7a23 */
/* 0x000fe4000000000b */
/*0290*/ FFMA R6, R5.reuse, 15, R4 ; /* 0x4170000005067823 */
/* 0x040fe40000000004 */
/*02a0*/ FMUL R7, R5, 1024 ; /* 0x4480000005077820 */
/* 0x000fe40000400000 */
/*02b0*/ FFMA R6, R11, 3, R6 ; /* 0x404000000b067823 */
/* 0x000fc80000000006 */
/*02c0*/ FADD R9, R6, 1.0000000180025094805e-35 ; /* 0x0554ad2e06097421 */
/* 0x000fe40000000000 */
/*02d0*/ F2I.TRUNC.NTZ R6, R7 ; /* 0x0000000700067305 */
/* 0x000e26000020f100 */
/*02e0*/ IADD3 R8, R9, 0x1800000, RZ ; /* 0x0180000009087810 */
/* 0x000fc80007ffe0ff */
/*02f0*/ LOP3.LUT R8, R8, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000008087812 */
/* 0x000fc800078ec0ff */
/*0300*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ffffff, PT ; /* 0x01ffffff0800780c */
/* 0x000fe20003f04070 */
/*0310*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x001fd800078e00ff */
/*0320*/ @P0 BRA 0x360 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0330*/ MOV R8, 0x350 ; /* 0x0000035000087802 */
/* 0x000fe40000000f00 */
/*0340*/ CALL.REL.NOINC 0x4a0 ; /* 0x0000015000007944 */
/* 0x000fea0003c00000 */
/*0350*/ BRA 0x3a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0360*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e240000001000 */
/*0370*/ FFMA R7, R9, R8, -1 ; /* 0xbf80000009077423 */
/* 0x001fc80000000008 */
/*0380*/ FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07077221 */
/* 0x000fc80000010100 */
/*0390*/ FFMA R7, R8, R7, R8 ; /* 0x0000000708077223 */
/* 0x000fe40000000008 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03b0*/ LDC R11, c[0x3][R6] ; /* 0x00c00000060b7b82 */
/* 0x000e220000000800 */
/*03c0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*03d0*/ FMUL R4, R4, 52 ; /* 0x4250000004047820 */
/* 0x000fe40000400000 */
/*03e0*/ FMUL R8, R5, 117 ; /* 0x42ea000005087820 */
/* 0x000fe40000400000 */
/*03f0*/ FFMA R10, R4, R7.reuse, -2.5718290805816650391 ; /* 0xc02498d9040a7423 */
/* 0x080fe40000000007 */
/*0400*/ FFMA R12, R8, R7, -6.0883030891418457031 ; /* 0xc0c2d361080c7423 */
/* 0x000fc60000000007 */
/*0410*/ IMAD.WIDE.U32 R4, R3, R9, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0009 */
/*0420*/ IMAD.WIDE.U32 R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0009 */
/*0430*/ IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fc800078e0009 */
/*0440*/ FFMA R7, R10, R11, 0.32592591643333435059 ; /* 0x3ea6dfc30a077423 */
/* 0x001fe2000000000b */
/*0450*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe2000c101906 */
/*0460*/ FFMA R13, R11, R12, 0.49629628658294677734 ; /* 0x3efe1a8c0b0d7423 */
/* 0x000fc6000000000c */
/*0470*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101906 */
/*0480*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x000fe2000c101906 */
/*0490*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04a0*/ IMAD.SHL.U32 R7, R9, 0x2, RZ ; /* 0x0000000209077824 */
/* 0x000fe200078e00ff */
/*04b0*/ BSSY B1, 0x7d0 ; /* 0x0000031000017945 */
/* 0x000fe80003800000 */
/*04c0*/ SHF.R.U32.HI R10, RZ, 0x18, R7 ; /* 0x00000018ff0a7819 */
/* 0x000fc40000011607 */
/*04d0*/ MOV R7, R9 ; /* 0x0000000900077202 */
/* 0x000fe40000000f00 */
/*04e0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05070 */
/*04f0*/ @P0 BRA 0x5a0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0500*/ IMAD.SHL.U32 R9, R7, 0x2, RZ ; /* 0x0000000207097824 */
/* 0x000fca00078e00ff */
/*0510*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0520*/ @P0 FFMA R10, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f800000070a0823 */
/* 0x000fe200000000ff */
/*0530*/ @!P0 MUFU.RCP R9, R7 ; /* 0x0000000700098308 */
/* 0x000ff00000001000 */
/*0540*/ @P0 MUFU.RCP R11, R10 ; /* 0x0000000a000b0308 */
/* 0x000e240000001000 */
/*0550*/ @P0 FFMA R12, R10, R11, -1 ; /* 0xbf8000000a0c0423 */
/* 0x001fc8000000000b */
/*0560*/ @P0 FADD.FTZ R12, -R12, -RZ ; /* 0x800000ff0c0c0221 */
/* 0x000fc80000010100 */
/*0570*/ @P0 FFMA R12, R11, R12, R11 ; /* 0x0000000c0b0c0223 */
/* 0x000fc8000000000b */
/*0580*/ @P0 FFMA R9, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c090823 */
/* 0x000fe200000000ff */
/*0590*/ BRA 0x7c0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*05a0*/ IADD3 R9, R10, -0xfd, RZ ; /* 0xffffff030a097810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.GT.U32.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f04070 */
/*05c0*/ @P0 BRA 0x7b0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*05d0*/ LOP3.LUT R11, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff070b7812 */
/* 0x000fe200078ec0ff */
/*05e0*/ HFMA2.MMA R16, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff107435 */
/* 0x000fc600000001ff */
/*05f0*/ LOP3.LUT R11, R11, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f8000000b0b7812 */
/* 0x000fc800078efcff */
/*0600*/ MUFU.RCP R12, R11 ; /* 0x0000000b000c7308 */
/* 0x000e260000001000 */
/*0610*/ SHF.L.U32 R15, R16, R9, RZ ; /* 0x00000009100f7219 */
/* 0x000fe200000006ff */
/*0620*/ FFMA R13, R11, R12, -1 ; /* 0xbf8000000b0d7423 */
/* 0x001fc8000000000c */
/*0630*/ FADD.FTZ R13, -R13, -RZ ; /* 0x800000ff0d0d7221 */
/* 0x000fc80000010100 */
/*0640*/ FFMA.RM R14, R12.reuse, R13.reuse, R12.reuse ; /* 0x0000000d0c0e7223 */
/* 0x1c0fe4000000400c */
/*0650*/ FFMA.RP R13, R12, R13, R12 ; /* 0x0000000d0c0d7223 */
/* 0x000fc6000000800c */
/*0660*/ LOP3.LUT R12, R14.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0e0c7812 */
/* 0x040fe400078ec0ff */
/*0670*/ FSETP.NEU.FTZ.AND P0, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x000fe40003f1d000 */
/*0680*/ LOP3.LUT R12, R12, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000c0c7812 */
/* 0x000fe400078efcff */
/*0690*/ SEL R13, RZ, 0xffffffff, !P0 ; /* 0xffffffffff0d7807 */
/* 0x000fe40004000000 */
/*06a0*/ LOP3.LUT R14, R15, R12, RZ, 0xc0, !PT ; /* 0x0000000c0f0e7212 */
/* 0x000fc600078ec0ff */
/*06b0*/ IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0d */
/*06c0*/ SHF.R.U32.HI R14, RZ, R9, R14 ; /* 0x00000009ff0e7219 */
/* 0x000fc8000001160e */
/*06d0*/ LOP3.LUT P1, RZ, R13, R9, R12, 0xf8, !PT ; /* 0x000000090dff7212 */
/* 0x000fe4000782f80c */
/*06e0*/ LOP3.LUT P0, RZ, R14.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x000000010eff7812 */
/* 0x040fe4000780c0ff */
/*06f0*/ LOP3.LUT P2, RZ, R14, 0x2, RZ, 0xc0, !PT ; /* 0x000000020eff7812 */
/* 0x000fc8000784c0ff */
/*0700*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0710*/ LOP3.LUT P1, RZ, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07ff7812 */
/* 0x000fe4000782c0ff */
/*0720*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0730*/ IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09097210 */
/* 0x000fc80007ffe1ff */
/*0740*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*0750*/ IADD3 R9, R10, -0xfc, RZ ; /* 0xffffff040a097810 */
/* 0x000fc80007ffe0ff */
/*0760*/ SHF.R.U32.HI R12, RZ, R9, R12 ; /* 0x00000009ff0c7219 */
/* 0x000fce000001160c */
/*0770*/ @!P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c8810 */
/* 0x000fca0007ffe0ff */
/*0780*/ @!P1 IMAD.SHL.U32 R12, R12, 0x2, RZ ; /* 0x000000020c0c9824 */
/* 0x000fca00078e00ff */
/*0790*/ LOP3.LUT R9, R12, 0x80000000, R7, 0xf8, !PT ; /* 0x800000000c097812 */
/* 0x000fe200078ef807 */
/*07a0*/ BRA 0x7c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07b0*/ MUFU.RCP R9, R7 ; /* 0x0000000700097308 */
/* 0x0000640000001000 */
/*07c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07d0*/ MOV R7, R9 ; /* 0x0000000900077202 */
/* 0x003fe20000000f00 */
/*07e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*07f0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff80008007950 */
/* 0x000fea0003c3ffff */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
//#define __OUTPUT_PIX__
#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];
__global__ void convert_to_luv_gpu_kernel(unsigned char *in_img, float *out_img, int cols, int rows, bool use_rgb)
{
float r, g, b, l, u, v, x, y, z, lt;
unsigned int x_pos = threadIdx.x + (blockDim.x * blockIdx.x);
unsigned int y_pos = threadIdx.y + (blockDim.y * blockIdx.y);
if ((x_pos < cols) && (y_pos < rows)) {
unsigned int pos = (y_pos * cols) + x_pos;
if (use_rgb) {
r = (float)in_img[(3 * pos)];
g = (float)in_img[(3 * pos) + 1];
b = (float)in_img[(3 * pos) + 2];
} else {
b = (float)in_img[(3 * pos)];
g = (float)in_img[(3 * pos) + 1];
r = (float)in_img[(3 * pos) + 2];
}
x = (mr_const[0] * r) + (mg_const[0] * g) + (mb_const[0] * b);
y = (mr_const[1] * r) + (mg_const[1] * g) + (mb_const[1] * b);
z = (mr_const[2] * r) + (mg_const[2] * g) + (mb_const[2] * b);
float maxi = 1.0f / 270;
float minu = -88.0f * maxi;
float minv = -134.0f * maxi;
float un = 0.197833f;
float vn = 0.468331f;
lt = lTable_const[static_cast<int>((y*1024))];
l = lt; z = 1/(x + (15 * y) + (3 * z) + (float)1e-35);
u = lt * (13 * 4 * x * z - 13 * un) - minu;
v = lt * (13 * 9 * y * z - 13 * vn) - minv;
out_img[(3 * pos)] = l;
out_img[(3 * pos) + 1] = u;
out_img[(3 * pos) + 2] = v;
}
} | .file "tmpxft_00172874_00000000-6_convert_to_luv_gpu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z25convert_to_luv_gpu_kernelPhPfiibPhPfiib
.type _Z50__device_stub__Z25convert_to_luv_gpu_kernelPhPfiibPhPfiib, @function
_Z50__device_stub__Z25convert_to_luv_gpu_kernelPhPfiibPhPfiib:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movb %r8b, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25convert_to_luv_gpu_kernelPhPfiib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z25convert_to_luv_gpu_kernelPhPfiibPhPfiib, .-_Z50__device_stub__Z25convert_to_luv_gpu_kernelPhPfiibPhPfiib
.globl _Z25convert_to_luv_gpu_kernelPhPfiib
.type _Z25convert_to_luv_gpu_kernelPhPfiib, @function
_Z25convert_to_luv_gpu_kernelPhPfiib:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r8b, %r8d
call _Z50__device_stub__Z25convert_to_luv_gpu_kernelPhPfiibPhPfiib
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25convert_to_luv_gpu_kernelPhPfiib, .-_Z25convert_to_luv_gpu_kernelPhPfiib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25convert_to_luv_gpu_kernelPhPfiib"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "lTable_const"
.LC2:
.string "mr_const"
.LC3:
.string "mg_const"
.LC4:
.string "mb_const"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25convert_to_luv_gpu_kernelPhPfiib(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4256, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12lTable_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $12, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8mr_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $12, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8mg_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $12, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8mb_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8mb_const
.comm _ZL8mb_const,12,8
.local _ZL8mg_const
.comm _ZL8mg_const,12,8
.local _ZL8mr_const
.comm _ZL8mr_const,12,8
.local _ZL12lTable_const
.comm _ZL12lTable_const,4256,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
//#define __OUTPUT_PIX__
#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];
__global__ void convert_to_luv_gpu_kernel(unsigned char *in_img, float *out_img, int cols, int rows, bool use_rgb)
{
float r, g, b, l, u, v, x, y, z, lt;
unsigned int x_pos = threadIdx.x + (blockDim.x * blockIdx.x);
unsigned int y_pos = threadIdx.y + (blockDim.y * blockIdx.y);
if ((x_pos < cols) && (y_pos < rows)) {
unsigned int pos = (y_pos * cols) + x_pos;
if (use_rgb) {
r = (float)in_img[(3 * pos)];
g = (float)in_img[(3 * pos) + 1];
b = (float)in_img[(3 * pos) + 2];
} else {
b = (float)in_img[(3 * pos)];
g = (float)in_img[(3 * pos) + 1];
r = (float)in_img[(3 * pos) + 2];
}
x = (mr_const[0] * r) + (mg_const[0] * g) + (mb_const[0] * b);
y = (mr_const[1] * r) + (mg_const[1] * g) + (mb_const[1] * b);
z = (mr_const[2] * r) + (mg_const[2] * g) + (mb_const[2] * b);
float maxi = 1.0f / 270;
float minu = -88.0f * maxi;
float minv = -134.0f * maxi;
float un = 0.197833f;
float vn = 0.468331f;
lt = lTable_const[static_cast<int>((y*1024))];
l = lt; z = 1/(x + (15 * y) + (3 * z) + (float)1e-35);
u = lt * (13 * 4 * x * z - 13 * un) - minu;
v = lt * (13 * 9 * y * z - 13 * vn) - minv;
out_img[(3 * pos)] = l;
out_img[(3 * pos) + 1] = u;
out_img[(3 * pos) + 2] = v;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
//#define __OUTPUT_PIX__
#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];
__global__ void convert_to_luv_gpu_kernel(unsigned char *in_img, float *out_img, int cols, int rows, bool use_rgb)
{
float r, g, b, l, u, v, x, y, z, lt;
unsigned int x_pos = threadIdx.x + (blockDim.x * blockIdx.x);
unsigned int y_pos = threadIdx.y + (blockDim.y * blockIdx.y);
if ((x_pos < cols) && (y_pos < rows)) {
unsigned int pos = (y_pos * cols) + x_pos;
if (use_rgb) {
r = (float)in_img[(3 * pos)];
g = (float)in_img[(3 * pos) + 1];
b = (float)in_img[(3 * pos) + 2];
} else {
b = (float)in_img[(3 * pos)];
g = (float)in_img[(3 * pos) + 1];
r = (float)in_img[(3 * pos) + 2];
}
x = (mr_const[0] * r) + (mg_const[0] * g) + (mb_const[0] * b);
y = (mr_const[1] * r) + (mg_const[1] * g) + (mb_const[1] * b);
z = (mr_const[2] * r) + (mg_const[2] * g) + (mb_const[2] * b);
float maxi = 1.0f / 270;
float minu = -88.0f * maxi;
float minv = -134.0f * maxi;
float un = 0.197833f;
float vn = 0.468331f;
lt = lTable_const[static_cast<int>((y*1024))];
l = lt; z = 1/(x + (15 * y) + (3 * z) + (float)1e-35);
u = lt * (13 * 4 * x * z - 13 * un) - minu;
v = lt * (13 * 9 * y * z - 13 * vn) - minv;
out_img[(3 * pos)] = l;
out_img[(3 * pos) + 1] = u;
out_img[(3 * pos) + 2] = v;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//#define __OUTPUT_PIX__
#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];
__global__ void convert_to_luv_gpu_kernel(unsigned char *in_img, float *out_img, int cols, int rows, bool use_rgb)
{
float r, g, b, l, u, v, x, y, z, lt;
unsigned int x_pos = threadIdx.x + (blockDim.x * blockIdx.x);
unsigned int y_pos = threadIdx.y + (blockDim.y * blockIdx.y);
if ((x_pos < cols) && (y_pos < rows)) {
unsigned int pos = (y_pos * cols) + x_pos;
if (use_rgb) {
r = (float)in_img[(3 * pos)];
g = (float)in_img[(3 * pos) + 1];
b = (float)in_img[(3 * pos) + 2];
} else {
b = (float)in_img[(3 * pos)];
g = (float)in_img[(3 * pos) + 1];
r = (float)in_img[(3 * pos) + 2];
}
x = (mr_const[0] * r) + (mg_const[0] * g) + (mb_const[0] * b);
y = (mr_const[1] * r) + (mg_const[1] * g) + (mb_const[1] * b);
z = (mr_const[2] * r) + (mg_const[2] * g) + (mb_const[2] * b);
float maxi = 1.0f / 270;
float minu = -88.0f * maxi;
float minv = -134.0f * maxi;
float un = 0.197833f;
float vn = 0.468331f;
lt = lTable_const[static_cast<int>((y*1024))];
l = lt; z = 1/(x + (15 * y) + (3 * z) + (float)1e-35);
u = lt * (13 * 4 * x * z - 13 * un) - minu;
v = lt * (13 * 9 * y * z - 13 * vn) - minv;
out_img[(3 * pos)] = l;
out_img[(3 * pos) + 1] = u;
out_img[(3 * pos) + 2] = v;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25convert_to_luv_gpu_kernelPhPfiib
.globl _Z25convert_to_luv_gpu_kernelPhPfiib
.p2align 8
.type _Z25convert_to_luv_gpu_kernelPhPfiib,@function
_Z25convert_to_luv_gpu_kernelPhPfiib:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s5, s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, v2
v_add_nc_u32_e32 v2, 1, v0
v_add_nc_u32_e32 v4, 2, v0
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s5, 0
global_load_u8 v1, v2, s[0:1]
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v5, v4, v0, vcc_lo
v_cndmask_b32_e32 v3, v0, v4, vcc_lo
s_clause 0x1
global_load_u8 v5, v5, s[0:1]
global_load_u8 v3, v3, s[0:1]
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, mg_const@rel32@lo+8
s_addc_u32 s1, s1, mg_const@rel32@hi+16
s_load_b32 s6, s[0:1], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, mr_const@rel32@lo+8
s_addc_u32 s1, s1, mr_const@rel32@hi+16
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, mb_const@rel32@lo+8
s_addc_u32 s5, s5, mb_const@rel32@hi+16
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[4:5], 0x0
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v1, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mul_f32_e32 v7, s6, v1
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v8, v5
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v3, v3
v_fmac_f32_e32 v7, s0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, s1, v3
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, lTable_const@rel32@lo+4
s_addc_u32 s1, s1, lTable_const@rel32@hi+12
v_mul_f32_e32 v5, 0x44800000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v5, v5
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, v5, s0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, mg_const@rel32@lo+4
s_addc_u32 s1, s1, mg_const@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, mr_const@rel32@lo+4
s_addc_u32 s5, s5, mr_const@rel32@hi+12
s_load_b32 s10, s[0:1], 0x0
global_load_b32 v6, v[5:6], off
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, mg_const@rel32@lo+12
s_addc_u32 s7, s7, mg_const@rel32@hi+20
s_load_b32 s6, s[6:7], 0x0
s_load_b32 s7, s[4:5], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, mb_const@rel32@lo+4
s_addc_u32 s1, s1, mb_const@rel32@hi+12
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, mr_const@rel32@lo+12
s_addc_u32 s9, s9, mr_const@rel32@hi+20
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, mb_const@rel32@lo+12
s_addc_u32 s5, s5, mb_const@rel32@hi+20
s_load_b32 s8, s[8:9], 0x0
s_clause 0x1
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v9, s10, v1
v_mul_f32_e32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, s7, v8
v_fmac_f32_e32 v1, s8, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, s0, v3
v_fmac_f32_e32 v1, s1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fmamk_f32 v3, v7, 0x41700000, v9
v_mul_f32_e32 v9, 0x42500000, v9
v_mul_f32_e32 v7, 0x42ea0000, v7
v_fmamk_f32 v1, v1, 0x40400000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_add_f32 v8, 0x554ad2e, v1
v_div_scale_f32 v10, null, v8, v8, 1.0
v_div_scale_f32 v12, vcc_lo, 1.0, v8, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v11, v10
s_waitcnt_depctr 0xfff
v_fma_f32 v1, -v10, v11, 1.0
v_fmac_f32_e32 v11, v1, v11
v_mov_b32_e32 v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v13, v12, v11
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v10, v13, v12
v_fmac_f32_e32 v13, v5, v11
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v10, -v10, v13, v12
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v10, v10, v11, v13
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_div_fixup_f32 v8, v10, v8, 1.0
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_fmaak_f32 v9, v9, v8, 0xc02498d9
v_fmaak_f32 v7, v7, v8, 0xc0c2d361
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmaak_f32 v8, v6, v9, 0x3ea6dfc3
v_fmaak_f32 v7, v6, v7, 0x3efe1a8c
s_clause 0x2
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v8, off
global_store_b32 v[4:5], v7, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25convert_to_luv_gpu_kernelPhPfiib
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25convert_to_luv_gpu_kernelPhPfiib, .Lfunc_end0-_Z25convert_to_luv_gpu_kernelPhPfiib
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected lTable_const
.type lTable_const,@object
.section .bss,"aw",@nobits
.globl lTable_const
.p2align 4, 0x0
lTable_const:
.zero 4256
.size lTable_const, 4256
.protected mr_const
.type mr_const,@object
.globl mr_const
.p2align 2, 0x0
mr_const:
.zero 12
.size mr_const, 12
.protected mg_const
.type mg_const,@object
.globl mg_const
.p2align 2, 0x0
mg_const:
.zero 12
.size mg_const, 12
.protected mb_const
.type mb_const,@object
.globl mb_const
.p2align 2, 0x0
mb_const:
.zero 12
.size mb_const, 12
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym lTable_const
.addrsig_sym mr_const
.addrsig_sym mg_const
.addrsig_sym mb_const
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 1
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25convert_to_luv_gpu_kernelPhPfiib
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25convert_to_luv_gpu_kernelPhPfiib.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//#define __OUTPUT_PIX__
#define BLOCK_SIZE 32
__constant__ __device__ float lTable_const[1064];
__constant__ __device__ float mr_const[3];
__constant__ __device__ float mg_const[3];
__constant__ __device__ float mb_const[3];
__global__ void convert_to_luv_gpu_kernel(unsigned char *in_img, float *out_img, int cols, int rows, bool use_rgb)
{
float r, g, b, l, u, v, x, y, z, lt;
unsigned int x_pos = threadIdx.x + (blockDim.x * blockIdx.x);
unsigned int y_pos = threadIdx.y + (blockDim.y * blockIdx.y);
if ((x_pos < cols) && (y_pos < rows)) {
unsigned int pos = (y_pos * cols) + x_pos;
if (use_rgb) {
r = (float)in_img[(3 * pos)];
g = (float)in_img[(3 * pos) + 1];
b = (float)in_img[(3 * pos) + 2];
} else {
b = (float)in_img[(3 * pos)];
g = (float)in_img[(3 * pos) + 1];
r = (float)in_img[(3 * pos) + 2];
}
x = (mr_const[0] * r) + (mg_const[0] * g) + (mb_const[0] * b);
y = (mr_const[1] * r) + (mg_const[1] * g) + (mb_const[1] * b);
z = (mr_const[2] * r) + (mg_const[2] * g) + (mb_const[2] * b);
float maxi = 1.0f / 270;
float minu = -88.0f * maxi;
float minv = -134.0f * maxi;
float un = 0.197833f;
float vn = 0.468331f;
lt = lTable_const[static_cast<int>((y*1024))];
l = lt; z = 1/(x + (15 * y) + (3 * z) + (float)1e-35);
u = lt * (13 * 4 * x * z - 13 * un) - minu;
v = lt * (13 * 9 * y * z - 13 * vn) - minv;
out_img[(3 * pos)] = l;
out_img[(3 * pos) + 1] = u;
out_img[(3 * pos) + 2] = v;
}
} | .text
.file "convert_to_luv_gpu_kernel.hip"
.globl _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib # -- Begin function _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib
.p2align 4, 0x90
.type _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib,@function
_Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib: # @_Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movb %r8b, 7(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 7(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25convert_to_luv_gpu_kernelPhPfiib, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib, .Lfunc_end0-_Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25convert_to_luv_gpu_kernelPhPfiib, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $lTable_const, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4256, %r9d # imm = 0x10A0
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $mr_const, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $12, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $mg_const, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $12, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $mb_const, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $12, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type lTable_const,@object # @lTable_const
.local lTable_const
.comm lTable_const,4256,16
.type mr_const,@object # @mr_const
.local mr_const
.comm mr_const,12,4
.type mg_const,@object # @mg_const
.local mg_const
.comm mg_const,12,4
.type mb_const,@object # @mb_const
.local mb_const
.comm mb_const,12,4
.type _Z25convert_to_luv_gpu_kernelPhPfiib,@object # @_Z25convert_to_luv_gpu_kernelPhPfiib
.section .rodata,"a",@progbits
.globl _Z25convert_to_luv_gpu_kernelPhPfiib
.p2align 3, 0x0
_Z25convert_to_luv_gpu_kernelPhPfiib:
.quad _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib
.size _Z25convert_to_luv_gpu_kernelPhPfiib, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25convert_to_luv_gpu_kernelPhPfiib"
.size .L__unnamed_1, 37
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "lTable_const"
.size .L__unnamed_2, 13
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "mr_const"
.size .L__unnamed_3, 9
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "mg_const"
.size .L__unnamed_4, 9
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "mb_const"
.size .L__unnamed_5, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym lTable_const
.addrsig_sym mr_const
.addrsig_sym mg_const
.addrsig_sym mb_const
.addrsig_sym _Z25convert_to_luv_gpu_kernelPhPfiib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25convert_to_luv_gpu_kernelPhPfiib
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IMAD R3, R3, 0x3, RZ ; /* 0x0000000303037824 */
/* 0x000fca00078e02ff */
/*00d0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ IADD3 R0, R3.reuse, 0x2, RZ ; /* 0x0000000203007810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ IADD3 R4, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fe40007f1e0ff */
/*0100*/ IADD3 R6, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */
/* 0x000fe40007f3e0ff */
/*0110*/ IADD3 R8, P2, R0, c[0x0][0x160], RZ ; /* 0x0000580000087a10 */
/* 0x000fe40007f5e0ff */
/*0120*/ IADD3.X R5, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff057a10 */
/* 0x000fe200007fe4ff */
/*0130*/ IMAD.X R7, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff077624 */
/* 0x000fe200008e06ff */
/*0140*/ IADD3.X R9, RZ, c[0x0][0x164], RZ, P2, !PT ; /* 0x00005900ff097a10 */
/* 0x000fc600017fe4ff */
/*0150*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1100 */
/*0160*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ee8000c1e1100 */
/*0170*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000f22000c1e1100 */
/*0180*/ ULDC.S8 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000200 */
/*0190*/ BSSY B0, 0x3b0 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*01a0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*01b0*/ I2F.U16 R10, R4 ; /* 0x00000004000a7306 */
/* 0x004ff00000101000 */
/*01c0*/ I2F.U16 R13, R8 ; /* 0x00000008000d7306 */
/* 0x008e300000101000 */
/*01d0*/ I2F.U16 R11, R6 ; /* 0x00000006000b7306 */
/* 0x010e620000101000 */
/*01e0*/ FSEL R12, R10, R13, P0 ; /* 0x0000000d0a0c7208 */
/* 0x001fc40000000000 */
/*01f0*/ FSEL R10, R13, R10, P0 ; /* 0x0000000a0d0a7208 */
/* 0x000fe20000000000 */
/*0200*/ FMUL R15, R11.reuse, c[0x3][0x10ac] ; /* 0x00c42b000b0f7a20 */
/* 0x042fe40000400000 */
/*0210*/ FMUL R5, R11.reuse, c[0x3][0x10b0] ; /* 0x00c42c000b057a20 */
/* 0x040fe40000400000 */
/*0220*/ FMUL R11, R11, c[0x3][0x10b4] ; /* 0x00c42d000b0b7a20 */
/* 0x000fe40000400000 */
/*0230*/ FFMA R15, R12.reuse, c[0x3][0x10a0], R15 ; /* 0x00c428000c0f7a23 */
/* 0x040fe4000000000f */
/*0240*/ FFMA R5, R12.reuse, c[0x3][0x10a4], R5 ; /* 0x00c429000c057a23 */
/* 0x040fe40000000005 */
/*0250*/ FFMA R11, R12, c[0x3][0x10a8], R11 ; /* 0x00c42a000c0b7a23 */
/* 0x000fc4000000000b */
/*0260*/ FFMA R4, R10.reuse, c[0x3][0x10b8], R15 ; /* 0x00c42e000a047a23 */
/* 0x040fe4000000000f */
/*0270*/ FFMA R5, R10.reuse, c[0x3][0x10bc], R5 ; /* 0x00c42f000a057a23 */
/* 0x040fe40000000005 */
/*0280*/ FFMA R11, R10, c[0x3][0x10c0], R11 ; /* 0x00c430000a0b7a23 */
/* 0x000fe4000000000b */
/*0290*/ FFMA R6, R5.reuse, 15, R4 ; /* 0x4170000005067823 */
/* 0x040fe40000000004 */
/*02a0*/ FMUL R7, R5, 1024 ; /* 0x4480000005077820 */
/* 0x000fe40000400000 */
/*02b0*/ FFMA R6, R11, 3, R6 ; /* 0x404000000b067823 */
/* 0x000fc80000000006 */
/*02c0*/ FADD R9, R6, 1.0000000180025094805e-35 ; /* 0x0554ad2e06097421 */
/* 0x000fe40000000000 */
/*02d0*/ F2I.TRUNC.NTZ R6, R7 ; /* 0x0000000700067305 */
/* 0x000e26000020f100 */
/*02e0*/ IADD3 R8, R9, 0x1800000, RZ ; /* 0x0180000009087810 */
/* 0x000fc80007ffe0ff */
/*02f0*/ LOP3.LUT R8, R8, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000008087812 */
/* 0x000fc800078ec0ff */
/*0300*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ffffff, PT ; /* 0x01ffffff0800780c */
/* 0x000fe20003f04070 */
/*0310*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x001fd800078e00ff */
/*0320*/ @P0 BRA 0x360 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0330*/ MOV R8, 0x350 ; /* 0x0000035000087802 */
/* 0x000fe40000000f00 */
/*0340*/ CALL.REL.NOINC 0x4a0 ; /* 0x0000015000007944 */
/* 0x000fea0003c00000 */
/*0350*/ BRA 0x3a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0360*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e240000001000 */
/*0370*/ FFMA R7, R9, R8, -1 ; /* 0xbf80000009077423 */
/* 0x001fc80000000008 */
/*0380*/ FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07077221 */
/* 0x000fc80000010100 */
/*0390*/ FFMA R7, R8, R7, R8 ; /* 0x0000000708077223 */
/* 0x000fe40000000008 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03b0*/ LDC R11, c[0x3][R6] ; /* 0x00c00000060b7b82 */
/* 0x000e220000000800 */
/*03c0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*03d0*/ FMUL R4, R4, 52 ; /* 0x4250000004047820 */
/* 0x000fe40000400000 */
/*03e0*/ FMUL R8, R5, 117 ; /* 0x42ea000005087820 */
/* 0x000fe40000400000 */
/*03f0*/ FFMA R10, R4, R7.reuse, -2.5718290805816650391 ; /* 0xc02498d9040a7423 */
/* 0x080fe40000000007 */
/*0400*/ FFMA R12, R8, R7, -6.0883030891418457031 ; /* 0xc0c2d361080c7423 */
/* 0x000fc60000000007 */
/*0410*/ IMAD.WIDE.U32 R4, R3, R9, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0009 */
/*0420*/ IMAD.WIDE.U32 R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0009 */
/*0430*/ IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fc800078e0009 */
/*0440*/ FFMA R7, R10, R11, 0.32592591643333435059 ; /* 0x3ea6dfc30a077423 */
/* 0x001fe2000000000b */
/*0450*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe2000c101906 */
/*0460*/ FFMA R13, R11, R12, 0.49629628658294677734 ; /* 0x3efe1a8c0b0d7423 */
/* 0x000fc6000000000c */
/*0470*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101906 */
/*0480*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x000fe2000c101906 */
/*0490*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04a0*/ IMAD.SHL.U32 R7, R9, 0x2, RZ ; /* 0x0000000209077824 */
/* 0x000fe200078e00ff */
/*04b0*/ BSSY B1, 0x7d0 ; /* 0x0000031000017945 */
/* 0x000fe80003800000 */
/*04c0*/ SHF.R.U32.HI R10, RZ, 0x18, R7 ; /* 0x00000018ff0a7819 */
/* 0x000fc40000011607 */
/*04d0*/ MOV R7, R9 ; /* 0x0000000900077202 */
/* 0x000fe40000000f00 */
/*04e0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05070 */
/*04f0*/ @P0 BRA 0x5a0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0500*/ IMAD.SHL.U32 R9, R7, 0x2, RZ ; /* 0x0000000207097824 */
/* 0x000fca00078e00ff */
/*0510*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0520*/ @P0 FFMA R10, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f800000070a0823 */
/* 0x000fe200000000ff */
/*0530*/ @!P0 MUFU.RCP R9, R7 ; /* 0x0000000700098308 */
/* 0x000ff00000001000 */
/*0540*/ @P0 MUFU.RCP R11, R10 ; /* 0x0000000a000b0308 */
/* 0x000e240000001000 */
/*0550*/ @P0 FFMA R12, R10, R11, -1 ; /* 0xbf8000000a0c0423 */
/* 0x001fc8000000000b */
/*0560*/ @P0 FADD.FTZ R12, -R12, -RZ ; /* 0x800000ff0c0c0221 */
/* 0x000fc80000010100 */
/*0570*/ @P0 FFMA R12, R11, R12, R11 ; /* 0x0000000c0b0c0223 */
/* 0x000fc8000000000b */
/*0580*/ @P0 FFMA R9, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c090823 */
/* 0x000fe200000000ff */
/*0590*/ BRA 0x7c0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*05a0*/ IADD3 R9, R10, -0xfd, RZ ; /* 0xffffff030a097810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.GT.U32.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f04070 */
/*05c0*/ @P0 BRA 0x7b0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*05d0*/ LOP3.LUT R11, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff070b7812 */
/* 0x000fe200078ec0ff */
/*05e0*/ HFMA2.MMA R16, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff107435 */
/* 0x000fc600000001ff */
/*05f0*/ LOP3.LUT R11, R11, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f8000000b0b7812 */
/* 0x000fc800078efcff */
/*0600*/ MUFU.RCP R12, R11 ; /* 0x0000000b000c7308 */
/* 0x000e260000001000 */
/*0610*/ SHF.L.U32 R15, R16, R9, RZ ; /* 0x00000009100f7219 */
/* 0x000fe200000006ff */
/*0620*/ FFMA R13, R11, R12, -1 ; /* 0xbf8000000b0d7423 */
/* 0x001fc8000000000c */
/*0630*/ FADD.FTZ R13, -R13, -RZ ; /* 0x800000ff0d0d7221 */
/* 0x000fc80000010100 */
/*0640*/ FFMA.RM R14, R12.reuse, R13.reuse, R12.reuse ; /* 0x0000000d0c0e7223 */
/* 0x1c0fe4000000400c */
/*0650*/ FFMA.RP R13, R12, R13, R12 ; /* 0x0000000d0c0d7223 */
/* 0x000fc6000000800c */
/*0660*/ LOP3.LUT R12, R14.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0e0c7812 */
/* 0x040fe400078ec0ff */
/*0670*/ FSETP.NEU.FTZ.AND P0, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x000fe40003f1d000 */
/*0680*/ LOP3.LUT R12, R12, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000c0c7812 */
/* 0x000fe400078efcff */
/*0690*/ SEL R13, RZ, 0xffffffff, !P0 ; /* 0xffffffffff0d7807 */
/* 0x000fe40004000000 */
/*06a0*/ LOP3.LUT R14, R15, R12, RZ, 0xc0, !PT ; /* 0x0000000c0f0e7212 */
/* 0x000fc600078ec0ff */
/*06b0*/ IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0d */
/*06c0*/ SHF.R.U32.HI R14, RZ, R9, R14 ; /* 0x00000009ff0e7219 */
/* 0x000fc8000001160e */
/*06d0*/ LOP3.LUT P1, RZ, R13, R9, R12, 0xf8, !PT ; /* 0x000000090dff7212 */
/* 0x000fe4000782f80c */
/*06e0*/ LOP3.LUT P0, RZ, R14.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x000000010eff7812 */
/* 0x040fe4000780c0ff */
/*06f0*/ LOP3.LUT P2, RZ, R14, 0x2, RZ, 0xc0, !PT ; /* 0x000000020eff7812 */
/* 0x000fc8000784c0ff */
/*0700*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0710*/ LOP3.LUT P1, RZ, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07ff7812 */
/* 0x000fe4000782c0ff */
/*0720*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0730*/ IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09097210 */
/* 0x000fc80007ffe1ff */
/*0740*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*0750*/ IADD3 R9, R10, -0xfc, RZ ; /* 0xffffff040a097810 */
/* 0x000fc80007ffe0ff */
/*0760*/ SHF.R.U32.HI R12, RZ, R9, R12 ; /* 0x00000009ff0c7219 */
/* 0x000fce000001160c */
/*0770*/ @!P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c8810 */
/* 0x000fca0007ffe0ff */
/*0780*/ @!P1 IMAD.SHL.U32 R12, R12, 0x2, RZ ; /* 0x000000020c0c9824 */
/* 0x000fca00078e00ff */
/*0790*/ LOP3.LUT R9, R12, 0x80000000, R7, 0xf8, !PT ; /* 0x800000000c097812 */
/* 0x000fe200078ef807 */
/*07a0*/ BRA 0x7c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07b0*/ MUFU.RCP R9, R7 ; /* 0x0000000700097308 */
/* 0x0000640000001000 */
/*07c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*07d0*/ MOV R7, R9 ; /* 0x0000000900077202 */
/* 0x003fe20000000f00 */
/*07e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*07f0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff80008007950 */
/* 0x000fea0003c3ffff */
/*0800*/ BRA 0x800; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25convert_to_luv_gpu_kernelPhPfiib
.globl _Z25convert_to_luv_gpu_kernelPhPfiib
.p2align 8
.type _Z25convert_to_luv_gpu_kernelPhPfiib,@function
_Z25convert_to_luv_gpu_kernelPhPfiib:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s5, s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, v2
v_add_nc_u32_e32 v2, 1, v0
v_add_nc_u32_e32 v4, 2, v0
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s5, 0
global_load_u8 v1, v2, s[0:1]
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v5, v4, v0, vcc_lo
v_cndmask_b32_e32 v3, v0, v4, vcc_lo
s_clause 0x1
global_load_u8 v5, v5, s[0:1]
global_load_u8 v3, v3, s[0:1]
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, mg_const@rel32@lo+8
s_addc_u32 s1, s1, mg_const@rel32@hi+16
s_load_b32 s6, s[0:1], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, mr_const@rel32@lo+8
s_addc_u32 s1, s1, mr_const@rel32@hi+16
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, mb_const@rel32@lo+8
s_addc_u32 s5, s5, mb_const@rel32@hi+16
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[4:5], 0x0
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v1, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mul_f32_e32 v7, s6, v1
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v8, v5
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v3, v3
v_fmac_f32_e32 v7, s0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, s1, v3
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, lTable_const@rel32@lo+4
s_addc_u32 s1, s1, lTable_const@rel32@hi+12
v_mul_f32_e32 v5, 0x44800000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v5, v5
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, v5, s0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, mg_const@rel32@lo+4
s_addc_u32 s1, s1, mg_const@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, mr_const@rel32@lo+4
s_addc_u32 s5, s5, mr_const@rel32@hi+12
s_load_b32 s10, s[0:1], 0x0
global_load_b32 v6, v[5:6], off
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, mg_const@rel32@lo+12
s_addc_u32 s7, s7, mg_const@rel32@hi+20
s_load_b32 s6, s[6:7], 0x0
s_load_b32 s7, s[4:5], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, mb_const@rel32@lo+4
s_addc_u32 s1, s1, mb_const@rel32@hi+12
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, mr_const@rel32@lo+12
s_addc_u32 s9, s9, mr_const@rel32@hi+20
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, mb_const@rel32@lo+12
s_addc_u32 s5, s5, mb_const@rel32@hi+20
s_load_b32 s8, s[8:9], 0x0
s_clause 0x1
s_load_b32 s0, s[0:1], 0x0
s_load_b32 s1, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v9, s10, v1
v_mul_f32_e32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, s7, v8
v_fmac_f32_e32 v1, s8, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, s0, v3
v_fmac_f32_e32 v1, s1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fmamk_f32 v3, v7, 0x41700000, v9
v_mul_f32_e32 v9, 0x42500000, v9
v_mul_f32_e32 v7, 0x42ea0000, v7
v_fmamk_f32 v1, v1, 0x40400000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_add_f32 v8, 0x554ad2e, v1
v_div_scale_f32 v10, null, v8, v8, 1.0
v_div_scale_f32 v12, vcc_lo, 1.0, v8, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v11, v10
s_waitcnt_depctr 0xfff
v_fma_f32 v1, -v10, v11, 1.0
v_fmac_f32_e32 v11, v1, v11
v_mov_b32_e32 v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v13, v12, v11
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v10, v13, v12
v_fmac_f32_e32 v13, v5, v11
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v10, -v10, v13, v12
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v10, v10, v11, v13
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_div_fixup_f32 v8, v10, v8, 1.0
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_fmaak_f32 v9, v9, v8, 0xc02498d9
v_fmaak_f32 v7, v7, v8, 0xc0c2d361
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmaak_f32 v8, v6, v9, 0x3ea6dfc3
v_fmaak_f32 v7, v6, v7, 0x3efe1a8c
s_clause 0x2
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v8, off
global_store_b32 v[4:5], v7, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25convert_to_luv_gpu_kernelPhPfiib
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25convert_to_luv_gpu_kernelPhPfiib, .Lfunc_end0-_Z25convert_to_luv_gpu_kernelPhPfiib
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected lTable_const
.type lTable_const,@object
.section .bss,"aw",@nobits
.globl lTable_const
.p2align 4, 0x0
lTable_const:
.zero 4256
.size lTable_const, 4256
.protected mr_const
.type mr_const,@object
.globl mr_const
.p2align 2, 0x0
mr_const:
.zero 12
.size mr_const, 12
.protected mg_const
.type mg_const,@object
.globl mg_const
.p2align 2, 0x0
mg_const:
.zero 12
.size mg_const, 12
.protected mb_const
.type mb_const,@object
.globl mb_const
.p2align 2, 0x0
mb_const:
.zero 12
.size mb_const, 12
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym lTable_const
.addrsig_sym mr_const
.addrsig_sym mg_const
.addrsig_sym mb_const
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 1
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25convert_to_luv_gpu_kernelPhPfiib
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25convert_to_luv_gpu_kernelPhPfiib.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00172874_00000000-6_convert_to_luv_gpu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z25convert_to_luv_gpu_kernelPhPfiibPhPfiib
.type _Z50__device_stub__Z25convert_to_luv_gpu_kernelPhPfiibPhPfiib, @function
_Z50__device_stub__Z25convert_to_luv_gpu_kernelPhPfiibPhPfiib:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movb %r8b, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25convert_to_luv_gpu_kernelPhPfiib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z25convert_to_luv_gpu_kernelPhPfiibPhPfiib, .-_Z50__device_stub__Z25convert_to_luv_gpu_kernelPhPfiibPhPfiib
.globl _Z25convert_to_luv_gpu_kernelPhPfiib
.type _Z25convert_to_luv_gpu_kernelPhPfiib, @function
_Z25convert_to_luv_gpu_kernelPhPfiib:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %r8b, %r8d
call _Z50__device_stub__Z25convert_to_luv_gpu_kernelPhPfiibPhPfiib
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25convert_to_luv_gpu_kernelPhPfiib, .-_Z25convert_to_luv_gpu_kernelPhPfiib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25convert_to_luv_gpu_kernelPhPfiib"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "lTable_const"
.LC2:
.string "mr_const"
.LC3:
.string "mg_const"
.LC4:
.string "mb_const"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25convert_to_luv_gpu_kernelPhPfiib(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4256, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12lTable_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $12, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8mr_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $12, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8mg_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $12, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8mb_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8mb_const
.comm _ZL8mb_const,12,8
.local _ZL8mg_const
.comm _ZL8mg_const,12,8
.local _ZL8mr_const
.comm _ZL8mr_const,12,8
.local _ZL12lTable_const
.comm _ZL12lTable_const,4256,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convert_to_luv_gpu_kernel.hip"
.globl _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib # -- Begin function _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib
.p2align 4, 0x90
.type _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib,@function
_Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib: # @_Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movb %r8b, 7(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 7(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25convert_to_luv_gpu_kernelPhPfiib, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib, .Lfunc_end0-_Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25convert_to_luv_gpu_kernelPhPfiib, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $lTable_const, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4256, %r9d # imm = 0x10A0
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $mr_const, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $12, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $mg_const, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $12, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $mb_const, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $12, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type lTable_const,@object # @lTable_const
.local lTable_const
.comm lTable_const,4256,16
.type mr_const,@object # @mr_const
.local mr_const
.comm mr_const,12,4
.type mg_const,@object # @mg_const
.local mg_const
.comm mg_const,12,4
.type mb_const,@object # @mb_const
.local mb_const
.comm mb_const,12,4
.type _Z25convert_to_luv_gpu_kernelPhPfiib,@object # @_Z25convert_to_luv_gpu_kernelPhPfiib
.section .rodata,"a",@progbits
.globl _Z25convert_to_luv_gpu_kernelPhPfiib
.p2align 3, 0x0
_Z25convert_to_luv_gpu_kernelPhPfiib:
.quad _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib
.size _Z25convert_to_luv_gpu_kernelPhPfiib, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25convert_to_luv_gpu_kernelPhPfiib"
.size .L__unnamed_1, 37
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "lTable_const"
.size .L__unnamed_2, 13
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "mr_const"
.size .L__unnamed_3, 9
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "mg_const"
.size .L__unnamed_4, 9
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "mb_const"
.size .L__unnamed_5, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__convert_to_luv_gpu_kernelPhPfiib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym lTable_const
.addrsig_sym mr_const
.addrsig_sym mg_const
.addrsig_sym mb_const
.addrsig_sym _Z25convert_to_luv_gpu_kernelPhPfiib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <string>
/*
struct PointCloud {
utility::device_vector<Eigen::Vector3f> points_;
};
namespace ply_pointcloud_reader {
struct PLYReaderState {
utility::ConsoleProgressBar *progress_bar;
HostPointCloud *pointcloud_ptr;
long vertex_index;
long vertex_num;
long normal_index;
long normal_num;
long color_index;
long color_num;
};
int ReadVertexCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->vertex_index >= state_ptr->vertex_num) {
return 0; // some sanity check
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->points_[state_ptr->vertex_index](index) = value;
if (index == 2) { // reading 'z'
state_ptr->vertex_index++;
++(*state_ptr->progress_bar);
}
return 1;
}
int ReadNormalCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->normal_index >= state_ptr->normal_num) {
return 0;
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->normals_[state_ptr->normal_index](index) = value;
if (index == 2) { // reading 'nz'
state_ptr->normal_index++;
}
return 1;
}
int ReadColorCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->color_index >= state_ptr->color_num) {
return 0;
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->colors_[state_ptr->color_index](index) =
value / 255.0;
if (index == 2) { // reading 'blue'
state_ptr->color_index++;
}
return 1;
}
} // namespace ply_pointcloud_reader
bool ReadPointCloudFromPLY(const std::string &filename,
PointCloud &pointcloud,
bool print_progress = false);
bool ReadPointCloudFromPLY(const std::string &filename,
geometry::PointCloud &pointcloud,
bool print_progress) {
using namespace ply_pointcloud_reader;
p_ply ply_file = ply_open(filename.c_str(), NULL, 0, NULL);
if (!ply_file) {
utility::LogWarning("Read PLY failed: unable to open file: %s",
filename.c_str());
return false;
}
if (!ply_read_header(ply_file)) {
utility::LogWarning("Read PLY failed: unable to parse header.");
ply_close(ply_file);
return false;
}
PLYReaderState state;
HostPointCloud host_pc;
state.pointcloud_ptr = &host_pc;
state.vertex_num = ply_set_read_cb(ply_file, "vertex", "x",
ReadVertexCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "y", ReadVertexCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "z", ReadVertexCallback, &state, 2);
state.normal_num = ply_set_read_cb(ply_file, "vertex", "nx",
ReadNormalCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "ny", ReadNormalCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "nz", ReadNormalCallback, &state, 2);
state.color_num = ply_set_read_cb(ply_file, "vertex", "red",
ReadColorCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "green", ReadColorCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "blue", ReadColorCallback, &state, 2);
if (state.vertex_num <= 0) {
utility::LogWarning("Read PLY failed: number of vertex <= 0.");
ply_close(ply_file);
return false;
}
state.vertex_index = 0;
state.normal_index = 0;
state.color_index = 0;
host_pc.Clear();
host_pc.points_.resize(state.vertex_num);
host_pc.normals_.resize(state.normal_num);
host_pc.colors_.resize(state.color_num);
utility::ConsoleProgressBar progress_bar(state.vertex_num + 1,
"Reading PLY: ", print_progress);
state.progress_bar = &progress_bar;
if (!ply_read(ply_file)) {
utility::LogWarning("Read PLY failed: unable to read file: {}",
filename);
ply_close(ply_file);
return false;
}
ply_close(ply_file);
++progress_bar;
host_pc.ToDevice(pointcloud);
return true;
}
*/
int main() {
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <string>
/*
struct PointCloud {
utility::device_vector<Eigen::Vector3f> points_;
};
namespace ply_pointcloud_reader {
struct PLYReaderState {
utility::ConsoleProgressBar *progress_bar;
HostPointCloud *pointcloud_ptr;
long vertex_index;
long vertex_num;
long normal_index;
long normal_num;
long color_index;
long color_num;
};
int ReadVertexCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->vertex_index >= state_ptr->vertex_num) {
return 0; // some sanity check
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->points_[state_ptr->vertex_index](index) = value;
if (index == 2) { // reading 'z'
state_ptr->vertex_index++;
++(*state_ptr->progress_bar);
}
return 1;
}
int ReadNormalCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->normal_index >= state_ptr->normal_num) {
return 0;
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->normals_[state_ptr->normal_index](index) = value;
if (index == 2) { // reading 'nz'
state_ptr->normal_index++;
}
return 1;
}
int ReadColorCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->color_index >= state_ptr->color_num) {
return 0;
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->colors_[state_ptr->color_index](index) =
value / 255.0;
if (index == 2) { // reading 'blue'
state_ptr->color_index++;
}
return 1;
}
} // namespace ply_pointcloud_reader
bool ReadPointCloudFromPLY(const std::string &filename,
PointCloud &pointcloud,
bool print_progress = false);
bool ReadPointCloudFromPLY(const std::string &filename,
geometry::PointCloud &pointcloud,
bool print_progress) {
using namespace ply_pointcloud_reader;
p_ply ply_file = ply_open(filename.c_str(), NULL, 0, NULL);
if (!ply_file) {
utility::LogWarning("Read PLY failed: unable to open file: %s",
filename.c_str());
return false;
}
if (!ply_read_header(ply_file)) {
utility::LogWarning("Read PLY failed: unable to parse header.");
ply_close(ply_file);
return false;
}
PLYReaderState state;
HostPointCloud host_pc;
state.pointcloud_ptr = &host_pc;
state.vertex_num = ply_set_read_cb(ply_file, "vertex", "x",
ReadVertexCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "y", ReadVertexCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "z", ReadVertexCallback, &state, 2);
state.normal_num = ply_set_read_cb(ply_file, "vertex", "nx",
ReadNormalCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "ny", ReadNormalCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "nz", ReadNormalCallback, &state, 2);
state.color_num = ply_set_read_cb(ply_file, "vertex", "red",
ReadColorCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "green", ReadColorCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "blue", ReadColorCallback, &state, 2);
if (state.vertex_num <= 0) {
utility::LogWarning("Read PLY failed: number of vertex <= 0.");
ply_close(ply_file);
return false;
}
state.vertex_index = 0;
state.normal_index = 0;
state.color_index = 0;
host_pc.Clear();
host_pc.points_.resize(state.vertex_num);
host_pc.normals_.resize(state.normal_num);
host_pc.colors_.resize(state.color_num);
utility::ConsoleProgressBar progress_bar(state.vertex_num + 1,
"Reading PLY: ", print_progress);
state.progress_bar = &progress_bar;
if (!ply_read(ply_file)) {
utility::LogWarning("Read PLY failed: unable to read file: {}",
filename);
ply_close(ply_file);
return false;
}
ply_close(ply_file);
++progress_bar;
host_pc.ToDevice(pointcloud);
return true;
}
*/
int main() {
} | .file "tmpxft_000d2302_00000000-6_01_read_ply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB3056:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE3056:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3082:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <string>
/*
struct PointCloud {
utility::device_vector<Eigen::Vector3f> points_;
};
namespace ply_pointcloud_reader {
struct PLYReaderState {
utility::ConsoleProgressBar *progress_bar;
HostPointCloud *pointcloud_ptr;
long vertex_index;
long vertex_num;
long normal_index;
long normal_num;
long color_index;
long color_num;
};
int ReadVertexCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->vertex_index >= state_ptr->vertex_num) {
return 0; // some sanity check
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->points_[state_ptr->vertex_index](index) = value;
if (index == 2) { // reading 'z'
state_ptr->vertex_index++;
++(*state_ptr->progress_bar);
}
return 1;
}
int ReadNormalCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->normal_index >= state_ptr->normal_num) {
return 0;
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->normals_[state_ptr->normal_index](index) = value;
if (index == 2) { // reading 'nz'
state_ptr->normal_index++;
}
return 1;
}
int ReadColorCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->color_index >= state_ptr->color_num) {
return 0;
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->colors_[state_ptr->color_index](index) =
value / 255.0;
if (index == 2) { // reading 'blue'
state_ptr->color_index++;
}
return 1;
}
} // namespace ply_pointcloud_reader
bool ReadPointCloudFromPLY(const std::string &filename,
PointCloud &pointcloud,
bool print_progress = false);
bool ReadPointCloudFromPLY(const std::string &filename,
geometry::PointCloud &pointcloud,
bool print_progress) {
using namespace ply_pointcloud_reader;
p_ply ply_file = ply_open(filename.c_str(), NULL, 0, NULL);
if (!ply_file) {
utility::LogWarning("Read PLY failed: unable to open file: %s",
filename.c_str());
return false;
}
if (!ply_read_header(ply_file)) {
utility::LogWarning("Read PLY failed: unable to parse header.");
ply_close(ply_file);
return false;
}
PLYReaderState state;
HostPointCloud host_pc;
state.pointcloud_ptr = &host_pc;
state.vertex_num = ply_set_read_cb(ply_file, "vertex", "x",
ReadVertexCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "y", ReadVertexCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "z", ReadVertexCallback, &state, 2);
state.normal_num = ply_set_read_cb(ply_file, "vertex", "nx",
ReadNormalCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "ny", ReadNormalCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "nz", ReadNormalCallback, &state, 2);
state.color_num = ply_set_read_cb(ply_file, "vertex", "red",
ReadColorCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "green", ReadColorCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "blue", ReadColorCallback, &state, 2);
if (state.vertex_num <= 0) {
utility::LogWarning("Read PLY failed: number of vertex <= 0.");
ply_close(ply_file);
return false;
}
state.vertex_index = 0;
state.normal_index = 0;
state.color_index = 0;
host_pc.Clear();
host_pc.points_.resize(state.vertex_num);
host_pc.normals_.resize(state.normal_num);
host_pc.colors_.resize(state.color_num);
utility::ConsoleProgressBar progress_bar(state.vertex_num + 1,
"Reading PLY: ", print_progress);
state.progress_bar = &progress_bar;
if (!ply_read(ply_file)) {
utility::LogWarning("Read PLY failed: unable to read file: {}",
filename);
ply_close(ply_file);
return false;
}
ply_close(ply_file);
++progress_bar;
host_pc.ToDevice(pointcloud);
return true;
}
*/
int main() {
} | #include <hip/hip_runtime.h>
#include <string>
/*
struct PointCloud {
utility::device_vector<Eigen::Vector3f> points_;
};
namespace ply_pointcloud_reader {
struct PLYReaderState {
utility::ConsoleProgressBar *progress_bar;
HostPointCloud *pointcloud_ptr;
long vertex_index;
long vertex_num;
long normal_index;
long normal_num;
long color_index;
long color_num;
};
int ReadVertexCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->vertex_index >= state_ptr->vertex_num) {
return 0; // some sanity check
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->points_[state_ptr->vertex_index](index) = value;
if (index == 2) { // reading 'z'
state_ptr->vertex_index++;
++(*state_ptr->progress_bar);
}
return 1;
}
int ReadNormalCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->normal_index >= state_ptr->normal_num) {
return 0;
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->normals_[state_ptr->normal_index](index) = value;
if (index == 2) { // reading 'nz'
state_ptr->normal_index++;
}
return 1;
}
int ReadColorCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->color_index >= state_ptr->color_num) {
return 0;
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->colors_[state_ptr->color_index](index) =
value / 255.0;
if (index == 2) { // reading 'blue'
state_ptr->color_index++;
}
return 1;
}
} // namespace ply_pointcloud_reader
bool ReadPointCloudFromPLY(const std::string &filename,
PointCloud &pointcloud,
bool print_progress = false);
bool ReadPointCloudFromPLY(const std::string &filename,
geometry::PointCloud &pointcloud,
bool print_progress) {
using namespace ply_pointcloud_reader;
p_ply ply_file = ply_open(filename.c_str(), NULL, 0, NULL);
if (!ply_file) {
utility::LogWarning("Read PLY failed: unable to open file: %s",
filename.c_str());
return false;
}
if (!ply_read_header(ply_file)) {
utility::LogWarning("Read PLY failed: unable to parse header.");
ply_close(ply_file);
return false;
}
PLYReaderState state;
HostPointCloud host_pc;
state.pointcloud_ptr = &host_pc;
state.vertex_num = ply_set_read_cb(ply_file, "vertex", "x",
ReadVertexCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "y", ReadVertexCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "z", ReadVertexCallback, &state, 2);
state.normal_num = ply_set_read_cb(ply_file, "vertex", "nx",
ReadNormalCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "ny", ReadNormalCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "nz", ReadNormalCallback, &state, 2);
state.color_num = ply_set_read_cb(ply_file, "vertex", "red",
ReadColorCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "green", ReadColorCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "blue", ReadColorCallback, &state, 2);
if (state.vertex_num <= 0) {
utility::LogWarning("Read PLY failed: number of vertex <= 0.");
ply_close(ply_file);
return false;
}
state.vertex_index = 0;
state.normal_index = 0;
state.color_index = 0;
host_pc.Clear();
host_pc.points_.resize(state.vertex_num);
host_pc.normals_.resize(state.normal_num);
host_pc.colors_.resize(state.color_num);
utility::ConsoleProgressBar progress_bar(state.vertex_num + 1,
"Reading PLY: ", print_progress);
state.progress_bar = &progress_bar;
if (!ply_read(ply_file)) {
utility::LogWarning("Read PLY failed: unable to read file: {}",
filename);
ply_close(ply_file);
return false;
}
ply_close(ply_file);
++progress_bar;
host_pc.ToDevice(pointcloud);
return true;
}
*/
int main() {
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <string>
/*
struct PointCloud {
utility::device_vector<Eigen::Vector3f> points_;
};
namespace ply_pointcloud_reader {
struct PLYReaderState {
utility::ConsoleProgressBar *progress_bar;
HostPointCloud *pointcloud_ptr;
long vertex_index;
long vertex_num;
long normal_index;
long normal_num;
long color_index;
long color_num;
};
int ReadVertexCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->vertex_index >= state_ptr->vertex_num) {
return 0; // some sanity check
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->points_[state_ptr->vertex_index](index) = value;
if (index == 2) { // reading 'z'
state_ptr->vertex_index++;
++(*state_ptr->progress_bar);
}
return 1;
}
int ReadNormalCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->normal_index >= state_ptr->normal_num) {
return 0;
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->normals_[state_ptr->normal_index](index) = value;
if (index == 2) { // reading 'nz'
state_ptr->normal_index++;
}
return 1;
}
int ReadColorCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->color_index >= state_ptr->color_num) {
return 0;
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->colors_[state_ptr->color_index](index) =
value / 255.0;
if (index == 2) { // reading 'blue'
state_ptr->color_index++;
}
return 1;
}
} // namespace ply_pointcloud_reader
bool ReadPointCloudFromPLY(const std::string &filename,
PointCloud &pointcloud,
bool print_progress = false);
bool ReadPointCloudFromPLY(const std::string &filename,
geometry::PointCloud &pointcloud,
bool print_progress) {
using namespace ply_pointcloud_reader;
p_ply ply_file = ply_open(filename.c_str(), NULL, 0, NULL);
if (!ply_file) {
utility::LogWarning("Read PLY failed: unable to open file: %s",
filename.c_str());
return false;
}
if (!ply_read_header(ply_file)) {
utility::LogWarning("Read PLY failed: unable to parse header.");
ply_close(ply_file);
return false;
}
PLYReaderState state;
HostPointCloud host_pc;
state.pointcloud_ptr = &host_pc;
state.vertex_num = ply_set_read_cb(ply_file, "vertex", "x",
ReadVertexCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "y", ReadVertexCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "z", ReadVertexCallback, &state, 2);
state.normal_num = ply_set_read_cb(ply_file, "vertex", "nx",
ReadNormalCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "ny", ReadNormalCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "nz", ReadNormalCallback, &state, 2);
state.color_num = ply_set_read_cb(ply_file, "vertex", "red",
ReadColorCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "green", ReadColorCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "blue", ReadColorCallback, &state, 2);
if (state.vertex_num <= 0) {
utility::LogWarning("Read PLY failed: number of vertex <= 0.");
ply_close(ply_file);
return false;
}
state.vertex_index = 0;
state.normal_index = 0;
state.color_index = 0;
host_pc.Clear();
host_pc.points_.resize(state.vertex_num);
host_pc.normals_.resize(state.normal_num);
host_pc.colors_.resize(state.color_num);
utility::ConsoleProgressBar progress_bar(state.vertex_num + 1,
"Reading PLY: ", print_progress);
state.progress_bar = &progress_bar;
if (!ply_read(ply_file)) {
utility::LogWarning("Read PLY failed: unable to read file: {}",
filename);
ply_close(ply_file);
return false;
}
ply_close(ply_file);
++progress_bar;
host_pc.ToDevice(pointcloud);
return true;
}
*/
int main() {
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <string>
/*
struct PointCloud {
utility::device_vector<Eigen::Vector3f> points_;
};
namespace ply_pointcloud_reader {
struct PLYReaderState {
utility::ConsoleProgressBar *progress_bar;
HostPointCloud *pointcloud_ptr;
long vertex_index;
long vertex_num;
long normal_index;
long normal_num;
long color_index;
long color_num;
};
int ReadVertexCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->vertex_index >= state_ptr->vertex_num) {
return 0; // some sanity check
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->points_[state_ptr->vertex_index](index) = value;
if (index == 2) { // reading 'z'
state_ptr->vertex_index++;
++(*state_ptr->progress_bar);
}
return 1;
}
int ReadNormalCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->normal_index >= state_ptr->normal_num) {
return 0;
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->normals_[state_ptr->normal_index](index) = value;
if (index == 2) { // reading 'nz'
state_ptr->normal_index++;
}
return 1;
}
int ReadColorCallback(p_ply_argument argument) {
PLYReaderState *state_ptr;
long index;
ply_get_argument_user_data(argument, reinterpret_cast<void **>(&state_ptr),
&index);
if (state_ptr->color_index >= state_ptr->color_num) {
return 0;
}
float value = ply_get_argument_value(argument);
state_ptr->pointcloud_ptr->colors_[state_ptr->color_index](index) =
value / 255.0;
if (index == 2) { // reading 'blue'
state_ptr->color_index++;
}
return 1;
}
} // namespace ply_pointcloud_reader
bool ReadPointCloudFromPLY(const std::string &filename,
PointCloud &pointcloud,
bool print_progress = false);
bool ReadPointCloudFromPLY(const std::string &filename,
geometry::PointCloud &pointcloud,
bool print_progress) {
using namespace ply_pointcloud_reader;
p_ply ply_file = ply_open(filename.c_str(), NULL, 0, NULL);
if (!ply_file) {
utility::LogWarning("Read PLY failed: unable to open file: %s",
filename.c_str());
return false;
}
if (!ply_read_header(ply_file)) {
utility::LogWarning("Read PLY failed: unable to parse header.");
ply_close(ply_file);
return false;
}
PLYReaderState state;
HostPointCloud host_pc;
state.pointcloud_ptr = &host_pc;
state.vertex_num = ply_set_read_cb(ply_file, "vertex", "x",
ReadVertexCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "y", ReadVertexCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "z", ReadVertexCallback, &state, 2);
state.normal_num = ply_set_read_cb(ply_file, "vertex", "nx",
ReadNormalCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "ny", ReadNormalCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "nz", ReadNormalCallback, &state, 2);
state.color_num = ply_set_read_cb(ply_file, "vertex", "red",
ReadColorCallback, &state, 0);
ply_set_read_cb(ply_file, "vertex", "green", ReadColorCallback, &state, 1);
ply_set_read_cb(ply_file, "vertex", "blue", ReadColorCallback, &state, 2);
if (state.vertex_num <= 0) {
utility::LogWarning("Read PLY failed: number of vertex <= 0.");
ply_close(ply_file);
return false;
}
state.vertex_index = 0;
state.normal_index = 0;
state.color_index = 0;
host_pc.Clear();
host_pc.points_.resize(state.vertex_num);
host_pc.normals_.resize(state.normal_num);
host_pc.colors_.resize(state.color_num);
utility::ConsoleProgressBar progress_bar(state.vertex_num + 1,
"Reading PLY: ", print_progress);
state.progress_bar = &progress_bar;
if (!ply_read(ply_file)) {
utility::LogWarning("Read PLY failed: unable to read file: {}",
filename);
ply_close(ply_file);
return false;
}
ply_close(ply_file);
++progress_bar;
host_pc.ToDevice(pointcloud);
return true;
}
*/
int main() {
} | .text
.file "01_read_ply.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d2302_00000000-6_01_read_ply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB3056:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE3056:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3082:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "01_read_ply.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gradientRowsKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[ROWS_GRAD_BLOCKDIM_Z][ROWS_GRAD_BLOCKDIM_Y][(ROWS_GRAD_RESULT_STEPS + 2 * ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X];
//Offset to the left halo edge
const int baseX = (blockIdx.x * ROWS_GRAD_RESULT_STEPS - ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * ROWS_GRAD_BLOCKDIM_Y + threadIdx.y;
const int baseZ = blockIdx.z * ROWS_GRAD_BLOCKDIM_Z + threadIdx.z;
d_Src += (baseZ * imageH + baseY) * imageW + baseX;
d_Dst += (baseZ * imageH + baseY) * imageW + baseX;
//Load main data
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = d_Src[i * ROWS_GRAD_BLOCKDIM_X];
}
//Load left halo
#pragma unroll
for (int i = 0; i < ROWS_GRAD_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = (baseX + i * ROWS_GRAD_BLOCKDIM_X >= 0) ? d_Src[i * ROWS_GRAD_BLOCKDIM_X] : 0;
}
//Load right halo
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS + ROWS_GRAD_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = (baseX + i * ROWS_GRAD_BLOCKDIM_X < imageW) ? d_Src[i * ROWS_GRAD_BLOCKDIM_X] : 0;
}
//Compute and store results
__syncthreads();
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i++)
{
float sum = 0;
sum += s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X + 1];
sum -= s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X - 1];
sum *= 0.5f;
d_Dst[i * ROWS_GRAD_BLOCKDIM_X] = sum;
}
} | code for sm_80
Function : _Z18gradientRowsKernelPfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R17, SR_TID.Y ; /* 0x0000000000117919 */
/* 0x000e280000002200 */
/*0050*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000e680000002700 */
/*0060*/ S2R R12, SR_TID.Z ; /* 0x00000000000c7919 */
/* 0x000e680000002300 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000ea80000002500 */
/*0080*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000ea20000002100 */
/*0090*/ LEA R0, R0, R17, 0x2 ; /* 0x0000001100007211 */
/* 0x001fc400078e10ff */
/*00a0*/ LEA R5, R5, R12, 0x2 ; /* 0x0000000c05057211 */
/* 0x002fca00078e10ff */
/*00b0*/ IMAD R0, R5, c[0x0][0x174], R0 ; /* 0x00005d0005007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ LEA R2, R2, R13, 0x7 ; /* 0x0000000d02027211 */
/* 0x004fc800078e38ff */
/*00e0*/ IADD3 R3, R2.reuse, -0x10, RZ ; /* 0xfffffff002037810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ IADD3 R4, R2, 0x80, RZ ; /* 0x0000008002047810 */
/* 0x000fe40007ffe0ff */
/*0100*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f06270 */
/*0110*/ IMAD R0, R0, c[0x0][0x170], R3 ; /* 0x00005c0000007a24 */
/* 0x000fe200078e0203 */
/*0120*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc60003f26270 */
/*0130*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0205 */
/*0140*/ LDG.E R4, [R2.64+0x40] ; /* 0x0000400402047981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R5, [R2.64+0x80] ; /* 0x0000800402057981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R6, [R2.64+0xc0] ; /* 0x0000c00402067981 */
/* 0x000f28000c1e1900 */
/*0170*/ LDG.E R7, [R2.64+0x100] ; /* 0x0001000402077981 */
/* 0x000f68000c1e1900 */
/*0180*/ LDG.E R8, [R2.64+0x140] ; /* 0x0001400402087981 */
/* 0x000f68000c1e1900 */
/*0190*/ LDG.E R9, [R2.64+0x180] ; /* 0x0001800402097981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R10, [R2.64+0x1c0] ; /* 0x0001c004020a7981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R11, [R2.64+0x200] ; /* 0x00020004020b7981 */
/* 0x000f68000c1e1900 */
/*01c0*/ @P0 LDG.E R15, [R2.64] ; /* 0x00000004020f0981 */
/* 0x000f68000c1e1900 */
/*01d0*/ @!P1 LDG.E R14, [R2.64+0x240] ; /* 0x00024004020e9981 */
/* 0x000f62000c1e1900 */
/*01e0*/ LEA R12, R12, R17, 0x2 ; /* 0x000000110c0c7211 */
/* 0x000fca00078e10ff */
/*01f0*/ IMAD R20, R12, 0xa0, R13 ; /* 0x000000a00c147824 */
/* 0x000fca00078e020d */
/*0200*/ STS [R20.X4+0x40], R4 ; /* 0x0000400414007388 */
/* 0x004fe80000004800 */
/*0210*/ STS [R20.X4+0x80], R5 ; /* 0x0000800514007388 */
/* 0x008fe80000004800 */
/*0220*/ STS [R20.X4+0xc0], R6 ; /* 0x0000c00614007388 */
/* 0x010fe80000004800 */
/*0230*/ STS [R20.X4+0x100], R7 ; /* 0x0001000714007388 */
/* 0x020fe80000004800 */
/*0240*/ STS [R20.X4+0x140], R8 ; /* 0x0001400814007388 */
/* 0x000fe80000004800 */
/*0250*/ STS [R20.X4+0x180], R9 ; /* 0x0001800914007388 */
/* 0x000fe80000004800 */
/*0260*/ STS [R20.X4+0x1c0], R10 ; /* 0x0001c00a14007388 */
/* 0x000fe80000004800 */
/*0270*/ STS [R20.X4+0x200], R11 ; /* 0x0002000b14007388 */
/* 0x000fe80000004800 */
/*0280*/ STS [R20.X4], R15 ; /* 0x0000000f14007388 */
/* 0x000fe80000004800 */
/*0290*/ STS [R20.X4+0x240], R14 ; /* 0x0002400e14007388 */
/* 0x0001e80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02b0*/ IADD3 R14, P0, R0, 0x10, RZ ; /* 0x00000010000e7810 */
/* 0x001fc80007f1e0ff */
/*02c0*/ LEA.HI.X.SX32 R15, R0, RZ, 0x1, P0 ; /* 0x000000ff000f7211 */
/* 0x000fe400000f0eff */
/*02d0*/ LEA R2, P0, R14.reuse, c[0x0][0x160], 0x2 ; /* 0x000058000e027a11 */
/* 0x040fe200078010ff */
/*02e0*/ LDS R3, [R20.X4+0x44] ; /* 0x0000440014037984 */
/* 0x000e280000004800 */
/*02f0*/ LDS R17, [R20.X4+0x3c] ; /* 0x00003c0014117984 */
/* 0x000e680000004800 */
/*0300*/ LDS R11, [R20.X4+0x144] ; /* 0x00014400140b7984 */
/* 0x000ea80000004800 */
/*0310*/ LDS R16, [R20.X4+0x84] ; /* 0x0000840014107984 */
/* 0x000ee80000004800 */
/*0320*/ LDS R18, [R20.X4+0xc4] ; /* 0x0000c40014127984 */
/* 0x000f280000004800 */
/*0330*/ LDS R13, [R20.X4+0x104] ; /* 0x00010400140d7984 */
/* 0x000f680000004800 */
/*0340*/ LDS R10, [R20.X4+0x184] ; /* 0x00018400140a7984 */
/* 0x000f680000004800 */
/*0350*/ LDS R9, [R20.X4+0x1c4] ; /* 0x0001c40014097984 */
/* 0x000f680000004800 */
/*0360*/ LDS R8, [R20.X4+0x204] ; /* 0x0002040014087984 */
/* 0x000f680000004800 */
/*0370*/ LDS R19, [R20.X4+0x7c] ; /* 0x00007c0014137984 */
/* 0x000f680000004800 */
/*0380*/ LDS R21, [R20.X4+0xbc] ; /* 0x0000bc0014157984 */
/* 0x000f620000004800 */
/*0390*/ FADD R0, RZ, R3 ; /* 0x00000003ff007221 */
/* 0x001fe20000000000 */
/*03a0*/ LEA.HI.X R3, R14, c[0x0][0x164], R15, 0x2, P0 ; /* 0x000059000e037a11 */
/* 0x000fc400000f140f */
/*03b0*/ LDS R12, [R20.X4+0xfc] ; /* 0x0000fc00140c7984 */
/* 0x000e220000004800 */
/*03c0*/ FADD R0, R0, -R17 ; /* 0x8000001100007221 */
/* 0x002fc60000000000 */
/*03d0*/ LDS R7, [R20.X4+0x13c] ; /* 0x00013c0014077984 */
/* 0x000e620000004800 */
/*03e0*/ FMUL R15, R0, 0.5 ; /* 0x3f000000000f7820 */
/* 0x000fe40000400000 */
/*03f0*/ FADD R0, RZ, R11 ; /* 0x0000000bff007221 */
/* 0x004fe20000000000 */
/*0400*/ LDS R4, [R20.X4+0x17c] ; /* 0x00017c0014047984 */
/* 0x000ea20000004800 */
/*0410*/ FADD R16, RZ, R16 ; /* 0x00000010ff107221 */
/* 0x008fc60000000000 */
/*0420*/ LDS R6, [R20.X4+0x1bc] ; /* 0x0001bc0014067984 */
/* 0x000ee20000004800 */
/*0430*/ FADD R18, RZ, R18 ; /* 0x00000012ff127221 */
/* 0x010fc60000000000 */
/*0440*/ LDS R5, [R20.X4+0x1fc] ; /* 0x0001fc0014057984 */
/* 0x000f220000004800 */
/*0450*/ FADD R13, RZ, R13 ; /* 0x0000000dff0d7221 */
/* 0x020fe40000000000 */
/*0460*/ FADD R11, RZ, R10 ; /* 0x0000000aff0b7221 */
/* 0x000fe20000000000 */
/*0470*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*0480*/ FADD R9, RZ, R9 ; /* 0x00000009ff097221 */
/* 0x000fe40000000000 */
/*0490*/ FADD R8, RZ, R8 ; /* 0x00000008ff087221 */
/* 0x000fe40000000000 */
/*04a0*/ FADD R16, R16, -R19 ; /* 0x8000001310107221 */
/* 0x000fe40000000000 */
/*04b0*/ FADD R18, R18, -R21 ; /* 0x8000001512127221 */
/* 0x000fc40000000000 */
/*04c0*/ FMUL R17, R16, 0.5 ; /* 0x3f00000010117820 */
/* 0x000fe40000400000 */
/*04d0*/ FADD R12, R13, -R12 ; /* 0x8000000c0d0c7221 */
/* 0x001fe40000000000 */
/*04e0*/ FMUL R19, R18, 0.5 ; /* 0x3f00000012137820 */
/* 0x000fe20000400000 */
/*04f0*/ STG.E [R2.64+0x40], R17 ; /* 0x0000401102007986 */
/* 0x000fe2000c101904 */
/*0500*/ FADD R0, R0, -R7 ; /* 0x8000000700007221 */
/* 0x002fc60000000000 */
/*0510*/ STG.E [R2.64+0x80], R19 ; /* 0x0000801302007986 */
/* 0x000fe2000c101904 */
/*0520*/ FADD R4, R11, -R4 ; /* 0x800000040b047221 */
/* 0x004fe40000000000 */
/*0530*/ FMUL R7, R0, 0.5 ; /* 0x3f00000000077820 */
/* 0x000fe40000400000 */
/*0540*/ FADD R6, R9, -R6 ; /* 0x8000000609067221 */
/* 0x008fe40000000000 */
/*0550*/ FMUL R9, R4, 0.5 ; /* 0x3f00000004097820 */
/* 0x000fe20000400000 */
/*0560*/ STG.E [R2.64+0x100], R7 ; /* 0x0001000702007986 */
/* 0x000fe2000c101904 */
/*0570*/ FADD R8, R8, -R5 ; /* 0x8000000508087221 */
/* 0x010fe40000000000 */
/*0580*/ FMUL R5, R12, 0.5 ; /* 0x3f0000000c057820 */
/* 0x000fe20000400000 */
/*0590*/ STG.E [R2.64+0x140], R9 ; /* 0x0001400902007986 */
/* 0x000fe2000c101904 */
/*05a0*/ FMUL R11, R6, 0.5 ; /* 0x3f000000060b7820 */
/* 0x000fc40000400000 */
/*05b0*/ FMUL R13, R8, 0.5 ; /* 0x3f000000080d7820 */
/* 0x000fe20000400000 */
/*05c0*/ STG.E [R2.64+0xc0], R5 ; /* 0x0000c00502007986 */
/* 0x000fe8000c101904 */
/*05d0*/ STG.E [R2.64+0x180], R11 ; /* 0x0001800b02007986 */
/* 0x000fe8000c101904 */
/*05e0*/ STG.E [R2.64+0x1c0], R13 ; /* 0x0001c00d02007986 */
/* 0x000fe2000c101904 */
/*05f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gradientRowsKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[ROWS_GRAD_BLOCKDIM_Z][ROWS_GRAD_BLOCKDIM_Y][(ROWS_GRAD_RESULT_STEPS + 2 * ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X];
//Offset to the left halo edge
const int baseX = (blockIdx.x * ROWS_GRAD_RESULT_STEPS - ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * ROWS_GRAD_BLOCKDIM_Y + threadIdx.y;
const int baseZ = blockIdx.z * ROWS_GRAD_BLOCKDIM_Z + threadIdx.z;
d_Src += (baseZ * imageH + baseY) * imageW + baseX;
d_Dst += (baseZ * imageH + baseY) * imageW + baseX;
//Load main data
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = d_Src[i * ROWS_GRAD_BLOCKDIM_X];
}
//Load left halo
#pragma unroll
for (int i = 0; i < ROWS_GRAD_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = (baseX + i * ROWS_GRAD_BLOCKDIM_X >= 0) ? d_Src[i * ROWS_GRAD_BLOCKDIM_X] : 0;
}
//Load right halo
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS + ROWS_GRAD_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = (baseX + i * ROWS_GRAD_BLOCKDIM_X < imageW) ? d_Src[i * ROWS_GRAD_BLOCKDIM_X] : 0;
}
//Compute and store results
__syncthreads();
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i++)
{
float sum = 0;
sum += s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X + 1];
sum -= s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X - 1];
sum *= 0.5f;
d_Dst[i * ROWS_GRAD_BLOCKDIM_X] = sum;
}
} | .file "tmpxft_00033b4f_00000000-6_gradientRowsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z18gradientRowsKernelPfS_iiiPfS_iii
.type _Z43__device_stub__Z18gradientRowsKernelPfS_iiiPfS_iii, @function
_Z43__device_stub__Z18gradientRowsKernelPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18gradientRowsKernelPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z18gradientRowsKernelPfS_iiiPfS_iii, .-_Z43__device_stub__Z18gradientRowsKernelPfS_iiiPfS_iii
.globl _Z18gradientRowsKernelPfS_iii
.type _Z18gradientRowsKernelPfS_iii, @function
_Z18gradientRowsKernelPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18gradientRowsKernelPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18gradientRowsKernelPfS_iii, .-_Z18gradientRowsKernelPfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18gradientRowsKernelPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18gradientRowsKernelPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gradientRowsKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[ROWS_GRAD_BLOCKDIM_Z][ROWS_GRAD_BLOCKDIM_Y][(ROWS_GRAD_RESULT_STEPS + 2 * ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X];
//Offset to the left halo edge
const int baseX = (blockIdx.x * ROWS_GRAD_RESULT_STEPS - ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * ROWS_GRAD_BLOCKDIM_Y + threadIdx.y;
const int baseZ = blockIdx.z * ROWS_GRAD_BLOCKDIM_Z + threadIdx.z;
d_Src += (baseZ * imageH + baseY) * imageW + baseX;
d_Dst += (baseZ * imageH + baseY) * imageW + baseX;
//Load main data
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = d_Src[i * ROWS_GRAD_BLOCKDIM_X];
}
//Load left halo
#pragma unroll
for (int i = 0; i < ROWS_GRAD_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = (baseX + i * ROWS_GRAD_BLOCKDIM_X >= 0) ? d_Src[i * ROWS_GRAD_BLOCKDIM_X] : 0;
}
//Load right halo
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS + ROWS_GRAD_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = (baseX + i * ROWS_GRAD_BLOCKDIM_X < imageW) ? d_Src[i * ROWS_GRAD_BLOCKDIM_X] : 0;
}
//Compute and store results
__syncthreads();
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i++)
{
float sum = 0;
sum += s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X + 1];
sum -= s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X - 1];
sum *= 0.5f;
d_Dst[i * ROWS_GRAD_BLOCKDIM_X] = sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gradientRowsKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[ROWS_GRAD_BLOCKDIM_Z][ROWS_GRAD_BLOCKDIM_Y][(ROWS_GRAD_RESULT_STEPS + 2 * ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X];
//Offset to the left halo edge
const int baseX = (blockIdx.x * ROWS_GRAD_RESULT_STEPS - ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * ROWS_GRAD_BLOCKDIM_Y + threadIdx.y;
const int baseZ = blockIdx.z * ROWS_GRAD_BLOCKDIM_Z + threadIdx.z;
d_Src += (baseZ * imageH + baseY) * imageW + baseX;
d_Dst += (baseZ * imageH + baseY) * imageW + baseX;
//Load main data
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = d_Src[i * ROWS_GRAD_BLOCKDIM_X];
}
//Load left halo
#pragma unroll
for (int i = 0; i < ROWS_GRAD_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = (baseX + i * ROWS_GRAD_BLOCKDIM_X >= 0) ? d_Src[i * ROWS_GRAD_BLOCKDIM_X] : 0;
}
//Load right halo
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS + ROWS_GRAD_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = (baseX + i * ROWS_GRAD_BLOCKDIM_X < imageW) ? d_Src[i * ROWS_GRAD_BLOCKDIM_X] : 0;
}
//Compute and store results
__syncthreads();
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i++)
{
float sum = 0;
sum += s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X + 1];
sum -= s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X - 1];
sum *= 0.5f;
d_Dst[i * ROWS_GRAD_BLOCKDIM_X] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gradientRowsKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[ROWS_GRAD_BLOCKDIM_Z][ROWS_GRAD_BLOCKDIM_Y][(ROWS_GRAD_RESULT_STEPS + 2 * ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X];
//Offset to the left halo edge
const int baseX = (blockIdx.x * ROWS_GRAD_RESULT_STEPS - ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * ROWS_GRAD_BLOCKDIM_Y + threadIdx.y;
const int baseZ = blockIdx.z * ROWS_GRAD_BLOCKDIM_Z + threadIdx.z;
d_Src += (baseZ * imageH + baseY) * imageW + baseX;
d_Dst += (baseZ * imageH + baseY) * imageW + baseX;
//Load main data
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = d_Src[i * ROWS_GRAD_BLOCKDIM_X];
}
//Load left halo
#pragma unroll
for (int i = 0; i < ROWS_GRAD_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = (baseX + i * ROWS_GRAD_BLOCKDIM_X >= 0) ? d_Src[i * ROWS_GRAD_BLOCKDIM_X] : 0;
}
//Load right halo
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS + ROWS_GRAD_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = (baseX + i * ROWS_GRAD_BLOCKDIM_X < imageW) ? d_Src[i * ROWS_GRAD_BLOCKDIM_X] : 0;
}
//Compute and store results
__syncthreads();
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i++)
{
float sum = 0;
sum += s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X + 1];
sum -= s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X - 1];
sum *= 0.5f;
d_Dst[i * ROWS_GRAD_BLOCKDIM_X] = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18gradientRowsKernelPfS_iii
.globl _Z18gradientRowsKernelPfS_iii
.p2align 8
.type _Z18gradientRowsKernelPfS_iii,@function
_Z18gradientRowsKernelPfS_iii:
s_load_b128 s[4:7], s[0:1], 0x8
v_bfe_u32 v5, v0, 20, 10
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u32 v7, v0, 10, 10
s_lshl_b32 s2, s13, 7
s_lshl_b32 s3, s14, 2
v_lshl_add_u32 v1, s15, 2, v5
v_add3_u32 v4, v6, s2, -16
v_mul_u32_u24_e32 v9, 0x280, v7
v_mov_b32_e32 v10, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u32_u24 v8, v5, 0xa00, v9
v_lshl_add_u32 v19, v6, 2, v8
v_mov_b32_e32 v8, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v1, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, s3, v7, v1
v_mad_u64_u32 v[0:1], null, v2, s6, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_clause 0x7
global_load_b32 v11, v[2:3], off offset:64
global_load_b32 v12, v[2:3], off offset:128
global_load_b32 v13, v[2:3], off offset:192
global_load_b32 v14, v[2:3], off offset:256
global_load_b32 v15, v[2:3], off offset:320
global_load_b32 v16, v[2:3], off offset:384
global_load_b32 v17, v[2:3], off offset:448
global_load_b32 v18, v[2:3], off offset:512
s_waitcnt vmcnt(6)
ds_store_2addr_b32 v19, v11, v12 offset0:16 offset1:32
s_waitcnt vmcnt(4)
ds_store_2addr_b32 v19, v13, v14 offset0:48 offset1:64
s_waitcnt vmcnt(2)
ds_store_2addr_b32 v19, v15, v16 offset0:80 offset1:96
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v19, v17, v18 offset0:112 offset1:128
v_cmpx_lt_i32_e32 -1, v4
s_cbranch_execz .LBB0_2
global_load_b32 v10, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v11, 2, v6
v_mul_u32_u24_e32 v12, 0xa00, v5
v_add_nc_u32_e32 v4, 0x90, v4
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v9, v12, v9, v11
s_waitcnt vmcnt(0)
ds_store_b32 v9, v10
v_cmpx_gt_i32_e64 s6, v4
s_cbranch_execz .LBB0_4
global_load_b32 v8, v[2:3], off offset:576
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
v_mul_u32_u24_e32 v2, 0x280, v7
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u32_u24 v2, v5, 0xa00, v2
v_lshl_add_u32 v16, v6, 2, v2
s_waitcnt vmcnt(0)
ds_store_b32 v16, v8 offset:576
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v16 offset0:15 offset1:17
ds_load_2addr_b32 v[4:5], v16 offset0:31 offset1:33
ds_load_2addr_b32 v[6:7], v16 offset0:47 offset1:49
ds_load_2addr_b32 v[8:9], v16 offset0:63 offset1:65
ds_load_2addr_b32 v[10:11], v16 offset0:79 offset1:81
ds_load_2addr_b32 v[12:13], v16 offset0:95 offset1:97
ds_load_2addr_b32 v[14:15], v16 offset0:111 offset1:113
ds_load_2addr_b32 v[16:17], v16 offset0:127 offset1:129
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(3)
v_add_f32_e32 v11, 0, v11
v_add_f32_e32 v7, 0, v7
v_add_f32_e32 v3, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v5, 0, v5 :: v_dual_sub_f32 v2, v3, v2
v_dual_sub_f32 v3, v5, v4 :: v_dual_sub_f32 v4, v7, v6
s_waitcnt lgkmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_dual_add_f32 v13, 0, v13 :: v_dual_mul_f32 v2, 0.5, v2
v_sub_f32_e32 v6, v11, v10
s_waitcnt lgkmcnt(1)
v_dual_mul_f32 v4, 0.5, v4 :: v_dual_add_f32 v15, 0, v15
v_sub_f32_e32 v7, v13, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_mul_f32 v3, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v6
v_add_f32_e32 v9, 0, v9
v_mul_f32_e32 v7, 0.5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_sub_f32 v5, v9, v8 :: v_dual_sub_f32 v8, v15, v14
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v17, 0, v17
v_dual_mul_f32 v5, 0.5, v5 :: v_dual_mul_f32 v8, 0.5, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v17, v16
v_mul_f32_e32 v9, 0.5, v9
s_clause 0x7
global_store_b32 v[0:1], v2, off offset:64
global_store_b32 v[0:1], v3, off offset:128
global_store_b32 v[0:1], v4, off offset:192
global_store_b32 v[0:1], v5, off offset:256
global_store_b32 v[0:1], v6, off offset:320
global_store_b32 v[0:1], v7, off offset:384
global_store_b32 v[0:1], v8, off offset:448
global_store_b32 v[0:1], v9, off offset:512
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18gradientRowsKernelPfS_iii
.amdhsa_group_segment_fixed_size 10240
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18gradientRowsKernelPfS_iii, .Lfunc_end0-_Z18gradientRowsKernelPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 10240
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18gradientRowsKernelPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18gradientRowsKernelPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gradientRowsKernel( float *d_Dst, float *d_Src, int imageW, int imageH, int imageD )
{
__shared__ float s_Data[ROWS_GRAD_BLOCKDIM_Z][ROWS_GRAD_BLOCKDIM_Y][(ROWS_GRAD_RESULT_STEPS + 2 * ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X];
//Offset to the left halo edge
const int baseX = (blockIdx.x * ROWS_GRAD_RESULT_STEPS - ROWS_GRAD_HALO_STEPS) * ROWS_GRAD_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * ROWS_GRAD_BLOCKDIM_Y + threadIdx.y;
const int baseZ = blockIdx.z * ROWS_GRAD_BLOCKDIM_Z + threadIdx.z;
d_Src += (baseZ * imageH + baseY) * imageW + baseX;
d_Dst += (baseZ * imageH + baseY) * imageW + baseX;
//Load main data
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = d_Src[i * ROWS_GRAD_BLOCKDIM_X];
}
//Load left halo
#pragma unroll
for (int i = 0; i < ROWS_GRAD_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = (baseX + i * ROWS_GRAD_BLOCKDIM_X >= 0) ? d_Src[i * ROWS_GRAD_BLOCKDIM_X] : 0;
}
//Load right halo
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS + ROWS_GRAD_HALO_STEPS; i++) {
s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X] = (baseX + i * ROWS_GRAD_BLOCKDIM_X < imageW) ? d_Src[i * ROWS_GRAD_BLOCKDIM_X] : 0;
}
//Compute and store results
__syncthreads();
#pragma unroll
for (int i = ROWS_GRAD_HALO_STEPS; i < ROWS_GRAD_HALO_STEPS + ROWS_GRAD_RESULT_STEPS; i++)
{
float sum = 0;
sum += s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X + 1];
sum -= s_Data[threadIdx.z][threadIdx.y][threadIdx.x + i * ROWS_GRAD_BLOCKDIM_X - 1];
sum *= 0.5f;
d_Dst[i * ROWS_GRAD_BLOCKDIM_X] = sum;
}
} | .text
.file "gradientRowsKernel.hip"
.globl _Z33__device_stub__gradientRowsKernelPfS_iii # -- Begin function _Z33__device_stub__gradientRowsKernelPfS_iii
.p2align 4, 0x90
.type _Z33__device_stub__gradientRowsKernelPfS_iii,@function
_Z33__device_stub__gradientRowsKernelPfS_iii: # @_Z33__device_stub__gradientRowsKernelPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18gradientRowsKernelPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__gradientRowsKernelPfS_iii, .Lfunc_end0-_Z33__device_stub__gradientRowsKernelPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18gradientRowsKernelPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18gradientRowsKernelPfS_iii,@object # @_Z18gradientRowsKernelPfS_iii
.section .rodata,"a",@progbits
.globl _Z18gradientRowsKernelPfS_iii
.p2align 3, 0x0
_Z18gradientRowsKernelPfS_iii:
.quad _Z33__device_stub__gradientRowsKernelPfS_iii
.size _Z18gradientRowsKernelPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18gradientRowsKernelPfS_iii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__gradientRowsKernelPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18gradientRowsKernelPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18gradientRowsKernelPfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R17, SR_TID.Y ; /* 0x0000000000117919 */
/* 0x000e280000002200 */
/*0050*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000e680000002700 */
/*0060*/ S2R R12, SR_TID.Z ; /* 0x00000000000c7919 */
/* 0x000e680000002300 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000ea80000002500 */
/*0080*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000ea20000002100 */
/*0090*/ LEA R0, R0, R17, 0x2 ; /* 0x0000001100007211 */
/* 0x001fc400078e10ff */
/*00a0*/ LEA R5, R5, R12, 0x2 ; /* 0x0000000c05057211 */
/* 0x002fca00078e10ff */
/*00b0*/ IMAD R0, R5, c[0x0][0x174], R0 ; /* 0x00005d0005007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ LEA R2, R2, R13, 0x7 ; /* 0x0000000d02027211 */
/* 0x004fc800078e38ff */
/*00e0*/ IADD3 R3, R2.reuse, -0x10, RZ ; /* 0xfffffff002037810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ IADD3 R4, R2, 0x80, RZ ; /* 0x0000008002047810 */
/* 0x000fe40007ffe0ff */
/*0100*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f06270 */
/*0110*/ IMAD R0, R0, c[0x0][0x170], R3 ; /* 0x00005c0000007a24 */
/* 0x000fe200078e0203 */
/*0120*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc60003f26270 */
/*0130*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0205 */
/*0140*/ LDG.E R4, [R2.64+0x40] ; /* 0x0000400402047981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R5, [R2.64+0x80] ; /* 0x0000800402057981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R6, [R2.64+0xc0] ; /* 0x0000c00402067981 */
/* 0x000f28000c1e1900 */
/*0170*/ LDG.E R7, [R2.64+0x100] ; /* 0x0001000402077981 */
/* 0x000f68000c1e1900 */
/*0180*/ LDG.E R8, [R2.64+0x140] ; /* 0x0001400402087981 */
/* 0x000f68000c1e1900 */
/*0190*/ LDG.E R9, [R2.64+0x180] ; /* 0x0001800402097981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R10, [R2.64+0x1c0] ; /* 0x0001c004020a7981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R11, [R2.64+0x200] ; /* 0x00020004020b7981 */
/* 0x000f68000c1e1900 */
/*01c0*/ @P0 LDG.E R15, [R2.64] ; /* 0x00000004020f0981 */
/* 0x000f68000c1e1900 */
/*01d0*/ @!P1 LDG.E R14, [R2.64+0x240] ; /* 0x00024004020e9981 */
/* 0x000f62000c1e1900 */
/*01e0*/ LEA R12, R12, R17, 0x2 ; /* 0x000000110c0c7211 */
/* 0x000fca00078e10ff */
/*01f0*/ IMAD R20, R12, 0xa0, R13 ; /* 0x000000a00c147824 */
/* 0x000fca00078e020d */
/*0200*/ STS [R20.X4+0x40], R4 ; /* 0x0000400414007388 */
/* 0x004fe80000004800 */
/*0210*/ STS [R20.X4+0x80], R5 ; /* 0x0000800514007388 */
/* 0x008fe80000004800 */
/*0220*/ STS [R20.X4+0xc0], R6 ; /* 0x0000c00614007388 */
/* 0x010fe80000004800 */
/*0230*/ STS [R20.X4+0x100], R7 ; /* 0x0001000714007388 */
/* 0x020fe80000004800 */
/*0240*/ STS [R20.X4+0x140], R8 ; /* 0x0001400814007388 */
/* 0x000fe80000004800 */
/*0250*/ STS [R20.X4+0x180], R9 ; /* 0x0001800914007388 */
/* 0x000fe80000004800 */
/*0260*/ STS [R20.X4+0x1c0], R10 ; /* 0x0001c00a14007388 */
/* 0x000fe80000004800 */
/*0270*/ STS [R20.X4+0x200], R11 ; /* 0x0002000b14007388 */
/* 0x000fe80000004800 */
/*0280*/ STS [R20.X4], R15 ; /* 0x0000000f14007388 */
/* 0x000fe80000004800 */
/*0290*/ STS [R20.X4+0x240], R14 ; /* 0x0002400e14007388 */
/* 0x0001e80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02b0*/ IADD3 R14, P0, R0, 0x10, RZ ; /* 0x00000010000e7810 */
/* 0x001fc80007f1e0ff */
/*02c0*/ LEA.HI.X.SX32 R15, R0, RZ, 0x1, P0 ; /* 0x000000ff000f7211 */
/* 0x000fe400000f0eff */
/*02d0*/ LEA R2, P0, R14.reuse, c[0x0][0x160], 0x2 ; /* 0x000058000e027a11 */
/* 0x040fe200078010ff */
/*02e0*/ LDS R3, [R20.X4+0x44] ; /* 0x0000440014037984 */
/* 0x000e280000004800 */
/*02f0*/ LDS R17, [R20.X4+0x3c] ; /* 0x00003c0014117984 */
/* 0x000e680000004800 */
/*0300*/ LDS R11, [R20.X4+0x144] ; /* 0x00014400140b7984 */
/* 0x000ea80000004800 */
/*0310*/ LDS R16, [R20.X4+0x84] ; /* 0x0000840014107984 */
/* 0x000ee80000004800 */
/*0320*/ LDS R18, [R20.X4+0xc4] ; /* 0x0000c40014127984 */
/* 0x000f280000004800 */
/*0330*/ LDS R13, [R20.X4+0x104] ; /* 0x00010400140d7984 */
/* 0x000f680000004800 */
/*0340*/ LDS R10, [R20.X4+0x184] ; /* 0x00018400140a7984 */
/* 0x000f680000004800 */
/*0350*/ LDS R9, [R20.X4+0x1c4] ; /* 0x0001c40014097984 */
/* 0x000f680000004800 */
/*0360*/ LDS R8, [R20.X4+0x204] ; /* 0x0002040014087984 */
/* 0x000f680000004800 */
/*0370*/ LDS R19, [R20.X4+0x7c] ; /* 0x00007c0014137984 */
/* 0x000f680000004800 */
/*0380*/ LDS R21, [R20.X4+0xbc] ; /* 0x0000bc0014157984 */
/* 0x000f620000004800 */
/*0390*/ FADD R0, RZ, R3 ; /* 0x00000003ff007221 */
/* 0x001fe20000000000 */
/*03a0*/ LEA.HI.X R3, R14, c[0x0][0x164], R15, 0x2, P0 ; /* 0x000059000e037a11 */
/* 0x000fc400000f140f */
/*03b0*/ LDS R12, [R20.X4+0xfc] ; /* 0x0000fc00140c7984 */
/* 0x000e220000004800 */
/*03c0*/ FADD R0, R0, -R17 ; /* 0x8000001100007221 */
/* 0x002fc60000000000 */
/*03d0*/ LDS R7, [R20.X4+0x13c] ; /* 0x00013c0014077984 */
/* 0x000e620000004800 */
/*03e0*/ FMUL R15, R0, 0.5 ; /* 0x3f000000000f7820 */
/* 0x000fe40000400000 */
/*03f0*/ FADD R0, RZ, R11 ; /* 0x0000000bff007221 */
/* 0x004fe20000000000 */
/*0400*/ LDS R4, [R20.X4+0x17c] ; /* 0x00017c0014047984 */
/* 0x000ea20000004800 */
/*0410*/ FADD R16, RZ, R16 ; /* 0x00000010ff107221 */
/* 0x008fc60000000000 */
/*0420*/ LDS R6, [R20.X4+0x1bc] ; /* 0x0001bc0014067984 */
/* 0x000ee20000004800 */
/*0430*/ FADD R18, RZ, R18 ; /* 0x00000012ff127221 */
/* 0x010fc60000000000 */
/*0440*/ LDS R5, [R20.X4+0x1fc] ; /* 0x0001fc0014057984 */
/* 0x000f220000004800 */
/*0450*/ FADD R13, RZ, R13 ; /* 0x0000000dff0d7221 */
/* 0x020fe40000000000 */
/*0460*/ FADD R11, RZ, R10 ; /* 0x0000000aff0b7221 */
/* 0x000fe20000000000 */
/*0470*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c101904 */
/*0480*/ FADD R9, RZ, R9 ; /* 0x00000009ff097221 */
/* 0x000fe40000000000 */
/*0490*/ FADD R8, RZ, R8 ; /* 0x00000008ff087221 */
/* 0x000fe40000000000 */
/*04a0*/ FADD R16, R16, -R19 ; /* 0x8000001310107221 */
/* 0x000fe40000000000 */
/*04b0*/ FADD R18, R18, -R21 ; /* 0x8000001512127221 */
/* 0x000fc40000000000 */
/*04c0*/ FMUL R17, R16, 0.5 ; /* 0x3f00000010117820 */
/* 0x000fe40000400000 */
/*04d0*/ FADD R12, R13, -R12 ; /* 0x8000000c0d0c7221 */
/* 0x001fe40000000000 */
/*04e0*/ FMUL R19, R18, 0.5 ; /* 0x3f00000012137820 */
/* 0x000fe20000400000 */
/*04f0*/ STG.E [R2.64+0x40], R17 ; /* 0x0000401102007986 */
/* 0x000fe2000c101904 */
/*0500*/ FADD R0, R0, -R7 ; /* 0x8000000700007221 */
/* 0x002fc60000000000 */
/*0510*/ STG.E [R2.64+0x80], R19 ; /* 0x0000801302007986 */
/* 0x000fe2000c101904 */
/*0520*/ FADD R4, R11, -R4 ; /* 0x800000040b047221 */
/* 0x004fe40000000000 */
/*0530*/ FMUL R7, R0, 0.5 ; /* 0x3f00000000077820 */
/* 0x000fe40000400000 */
/*0540*/ FADD R6, R9, -R6 ; /* 0x8000000609067221 */
/* 0x008fe40000000000 */
/*0550*/ FMUL R9, R4, 0.5 ; /* 0x3f00000004097820 */
/* 0x000fe20000400000 */
/*0560*/ STG.E [R2.64+0x100], R7 ; /* 0x0001000702007986 */
/* 0x000fe2000c101904 */
/*0570*/ FADD R8, R8, -R5 ; /* 0x8000000508087221 */
/* 0x010fe40000000000 */
/*0580*/ FMUL R5, R12, 0.5 ; /* 0x3f0000000c057820 */
/* 0x000fe20000400000 */
/*0590*/ STG.E [R2.64+0x140], R9 ; /* 0x0001400902007986 */
/* 0x000fe2000c101904 */
/*05a0*/ FMUL R11, R6, 0.5 ; /* 0x3f000000060b7820 */
/* 0x000fc40000400000 */
/*05b0*/ FMUL R13, R8, 0.5 ; /* 0x3f000000080d7820 */
/* 0x000fe20000400000 */
/*05c0*/ STG.E [R2.64+0xc0], R5 ; /* 0x0000c00502007986 */
/* 0x000fe8000c101904 */
/*05d0*/ STG.E [R2.64+0x180], R11 ; /* 0x0001800b02007986 */
/* 0x000fe8000c101904 */
/*05e0*/ STG.E [R2.64+0x1c0], R13 ; /* 0x0001c00d02007986 */
/* 0x000fe2000c101904 */
/*05f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18gradientRowsKernelPfS_iii
.globl _Z18gradientRowsKernelPfS_iii
.p2align 8
.type _Z18gradientRowsKernelPfS_iii,@function
_Z18gradientRowsKernelPfS_iii:
s_load_b128 s[4:7], s[0:1], 0x8
v_bfe_u32 v5, v0, 20, 10
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u32 v7, v0, 10, 10
s_lshl_b32 s2, s13, 7
s_lshl_b32 s3, s14, 2
v_lshl_add_u32 v1, s15, 2, v5
v_add3_u32 v4, v6, s2, -16
v_mul_u32_u24_e32 v9, 0x280, v7
v_mov_b32_e32 v10, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u32_u24 v8, v5, 0xa00, v9
v_lshl_add_u32 v19, v6, 2, v8
v_mov_b32_e32 v8, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v1, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, s3, v7, v1
v_mad_u64_u32 v[0:1], null, v2, s6, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_clause 0x7
global_load_b32 v11, v[2:3], off offset:64
global_load_b32 v12, v[2:3], off offset:128
global_load_b32 v13, v[2:3], off offset:192
global_load_b32 v14, v[2:3], off offset:256
global_load_b32 v15, v[2:3], off offset:320
global_load_b32 v16, v[2:3], off offset:384
global_load_b32 v17, v[2:3], off offset:448
global_load_b32 v18, v[2:3], off offset:512
s_waitcnt vmcnt(6)
ds_store_2addr_b32 v19, v11, v12 offset0:16 offset1:32
s_waitcnt vmcnt(4)
ds_store_2addr_b32 v19, v13, v14 offset0:48 offset1:64
s_waitcnt vmcnt(2)
ds_store_2addr_b32 v19, v15, v16 offset0:80 offset1:96
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v19, v17, v18 offset0:112 offset1:128
v_cmpx_lt_i32_e32 -1, v4
s_cbranch_execz .LBB0_2
global_load_b32 v10, v[2:3], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v11, 2, v6
v_mul_u32_u24_e32 v12, 0xa00, v5
v_add_nc_u32_e32 v4, 0x90, v4
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v9, v12, v9, v11
s_waitcnt vmcnt(0)
ds_store_b32 v9, v10
v_cmpx_gt_i32_e64 s6, v4
s_cbranch_execz .LBB0_4
global_load_b32 v8, v[2:3], off offset:576
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
v_mul_u32_u24_e32 v2, 0x280, v7
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u32_u24 v2, v5, 0xa00, v2
v_lshl_add_u32 v16, v6, 2, v2
s_waitcnt vmcnt(0)
ds_store_b32 v16, v8 offset:576
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[2:3], v16 offset0:15 offset1:17
ds_load_2addr_b32 v[4:5], v16 offset0:31 offset1:33
ds_load_2addr_b32 v[6:7], v16 offset0:47 offset1:49
ds_load_2addr_b32 v[8:9], v16 offset0:63 offset1:65
ds_load_2addr_b32 v[10:11], v16 offset0:79 offset1:81
ds_load_2addr_b32 v[12:13], v16 offset0:95 offset1:97
ds_load_2addr_b32 v[14:15], v16 offset0:111 offset1:113
ds_load_2addr_b32 v[16:17], v16 offset0:127 offset1:129
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(3)
v_add_f32_e32 v11, 0, v11
v_add_f32_e32 v7, 0, v7
v_add_f32_e32 v3, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v5, 0, v5 :: v_dual_sub_f32 v2, v3, v2
v_dual_sub_f32 v3, v5, v4 :: v_dual_sub_f32 v4, v7, v6
s_waitcnt lgkmcnt(2)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_dual_add_f32 v13, 0, v13 :: v_dual_mul_f32 v2, 0.5, v2
v_sub_f32_e32 v6, v11, v10
s_waitcnt lgkmcnt(1)
v_dual_mul_f32 v4, 0.5, v4 :: v_dual_add_f32 v15, 0, v15
v_sub_f32_e32 v7, v13, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_mul_f32 v3, 0.5, v3 :: v_dual_mul_f32 v6, 0.5, v6
v_add_f32_e32 v9, 0, v9
v_mul_f32_e32 v7, 0.5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_sub_f32 v5, v9, v8 :: v_dual_sub_f32 v8, v15, v14
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v17, 0, v17
v_dual_mul_f32 v5, 0.5, v5 :: v_dual_mul_f32 v8, 0.5, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v17, v16
v_mul_f32_e32 v9, 0.5, v9
s_clause 0x7
global_store_b32 v[0:1], v2, off offset:64
global_store_b32 v[0:1], v3, off offset:128
global_store_b32 v[0:1], v4, off offset:192
global_store_b32 v[0:1], v5, off offset:256
global_store_b32 v[0:1], v6, off offset:320
global_store_b32 v[0:1], v7, off offset:384
global_store_b32 v[0:1], v8, off offset:448
global_store_b32 v[0:1], v9, off offset:512
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18gradientRowsKernelPfS_iii
.amdhsa_group_segment_fixed_size 10240
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18gradientRowsKernelPfS_iii, .Lfunc_end0-_Z18gradientRowsKernelPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 10240
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18gradientRowsKernelPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18gradientRowsKernelPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00033b4f_00000000-6_gradientRowsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z18gradientRowsKernelPfS_iiiPfS_iii
.type _Z43__device_stub__Z18gradientRowsKernelPfS_iiiPfS_iii, @function
_Z43__device_stub__Z18gradientRowsKernelPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18gradientRowsKernelPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z18gradientRowsKernelPfS_iiiPfS_iii, .-_Z43__device_stub__Z18gradientRowsKernelPfS_iiiPfS_iii
.globl _Z18gradientRowsKernelPfS_iii
.type _Z18gradientRowsKernelPfS_iii, @function
_Z18gradientRowsKernelPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18gradientRowsKernelPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18gradientRowsKernelPfS_iii, .-_Z18gradientRowsKernelPfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18gradientRowsKernelPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18gradientRowsKernelPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gradientRowsKernel.hip"
.globl _Z33__device_stub__gradientRowsKernelPfS_iii # -- Begin function _Z33__device_stub__gradientRowsKernelPfS_iii
.p2align 4, 0x90
.type _Z33__device_stub__gradientRowsKernelPfS_iii,@function
_Z33__device_stub__gradientRowsKernelPfS_iii: # @_Z33__device_stub__gradientRowsKernelPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18gradientRowsKernelPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__gradientRowsKernelPfS_iii, .Lfunc_end0-_Z33__device_stub__gradientRowsKernelPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18gradientRowsKernelPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18gradientRowsKernelPfS_iii,@object # @_Z18gradientRowsKernelPfS_iii
.section .rodata,"a",@progbits
.globl _Z18gradientRowsKernelPfS_iii
.p2align 3, 0x0
_Z18gradientRowsKernelPfS_iii:
.quad _Z33__device_stub__gradientRowsKernelPfS_iii
.size _Z18gradientRowsKernelPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18gradientRowsKernelPfS_iii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__gradientRowsKernelPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18gradientRowsKernelPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.