system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <sys/time.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <math.h>
#include <cuda.h>
__device__ int endLoop=0;
__device__ __host__ int get_keypair(char* tab, int length, int first_char, int last_char){
int sum=0;
int pow=1;
int i=0;
for(i=0; i<length; i++){
sum+=tab[i]*pow;
pow*=(last_char - first_char);
}
return sum;
}
__host__ __device__ int check_keypairs(int crypt, int test)
{
if(crypt == test){
return 1;
}
else{
return 0;
}
}
__global__ void kernel( int *crypted, int length, int first_char, int last_char, double max_iter){
int loop_size = last_char - first_char;
int i =blockIdx.x * blockDim.x + threadIdx.x;
int total = (blockDim.x * gridDim.x);
char *tab = (char*)malloc(sizeof(char)*(length+1));
tab[length]='\0';
int j;
for(j=0; j<length; j++) tab[j] = first_char;
int current_keypair;
int pow=0;
for(int j=i; j<max_iter; j+=total){
pow=1;
for(int x=0; x<length; x++){
tab[x] = ((j/pow) % loop_size) + first_char;
pow*=loop_size;
}
current_keypair = get_keypair(tab, length, first_char, last_char);
if( check_keypairs(*crypted, current_keypair) ) {
printf( "password found: %s\n", tab );
endLoop=1;
}
if(endLoop==1){
j=max_iter;
}
}
}
int main( int argc, char** argv ) {
char* password;
int first_char, last_char;
float t1, t2;
//unsigned long cmp;
if( argc == 1 ) {
password = "A$4c";
first_char = 32;
last_char = 126;
/* ---ASCII values---
* special characters: 32 to 47
* numbers: 48 to 57
* special characters: 58 to 64
* letters uppercase: 65 to 90
* special characters: 91 to 96
* letters lowercase: 97 to 122
* special characters: 123 to 126
* */
} else if( argc == 4 ) {
password = argv[1];
first_char = atoi( argv[2] );
last_char = atoi( argv[3] );
} else {
printf("usage: breaker <password> <first_ch> <last_ch>\n");
printf("default: breaker A$4c 32 126\n");
printf("exemple to break the binary password 1101000:\n");
printf( "breaker 1101000 48 49\n" );
exit( 0 );
}
int length = strlen(password);
int sz_in_bytes = sizeof(int);
int *h_crypted = (int *)malloc(sizeof(int));
int crypted_to_break= get_keypair(password, length, first_char, last_char);
h_crypted = &crypted_to_break;
int *d_crypted=(int *)malloc(sizeof(int));
printf( "*running parameters*\n" );
printf( " -password length:\t%lu digits\n", strlen(password) );
printf( " -password length:\t%s digits\n", password);
printf( " -digits:\t\tfrom -%c- to -%c-\n", first_char, last_char );
printf( " -crypted to break:\t%d\n", crypted_to_break);
t1 = clock();
cudaMalloc((void**)&d_crypted, sz_in_bytes);
cudaMemcpy(d_crypted, h_crypted, sz_in_bytes, cudaMemcpyHostToDevice);
dim3 nBlocks;
dim3 nThperBlock;
nBlocks.x = 16;
nThperBlock.x = 1024;
int loop_size = last_char - first_char;
double max_iter = powl(loop_size, length);
kernel<<< nBlocks , nThperBlock >>>(d_crypted, length, first_char, last_char, max_iter);
cudaDeviceSynchronize();
t2 = clock();
cudaMemcpy(h_crypted, d_crypted, sz_in_bytes, cudaMemcpyDeviceToHost);
cudaFree(d_crypted);
float period = (t2-t1)/CLOCKS_PER_SEC;
if( period < 60 ){
printf( "time: %.1fs \n", period );
}else{
printf( "time: %.1fmin \n", period/60 );
}
return EXIT_SUCCESS;
} | .file "tmpxft_00117789_00000000-6_Breaker_for.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11get_keypairPciii
.type _Z11get_keypairPciii, @function
_Z11get_keypairPciii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L6
movq %rdi, %rax
movslq %esi, %rsi
addq %rsi, %rdi
movl $1, %esi
movl $0, %r8d
subl %edx, %ecx
.L5:
movsbl (%rax), %edx
imull %esi, %edx
addl %edx, %r8d
imull %ecx, %esi
addq $1, %rax
cmpq %rdi, %rax
jne .L5
.L3:
movl %r8d, %eax
ret
.L6:
movl $0, %r8d
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z11get_keypairPciii, .-_Z11get_keypairPciii
.globl _Z14check_keypairsii
.type _Z14check_keypairsii, @function
_Z14check_keypairsii:
.LFB2058:
.cfi_startproc
endbr64
cmpl %esi, %edi
sete %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z14check_keypairsii, .-_Z14check_keypairsii
.globl _Z29__device_stub__Z6kernelPiiiidPiiiid
.type _Z29__device_stub__Z6kernelPiiiidPiiiid, @function
_Z29__device_stub__Z6kernelPiiiidPiiiid:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPiiiid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z6kernelPiiiidPiiiid, .-_Z29__device_stub__Z6kernelPiiiidPiiiid
.globl _Z6kernelPiiiid
.type _Z6kernelPiiiid, @function
_Z6kernelPiiiid:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPiiiidPiiiid
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6kernelPiiiid, .-_Z6kernelPiiiid
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "A$4c"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "usage: breaker <password> <first_ch> <last_ch>\n"
.section .rodata.str1.1
.LC2:
.string "default: breaker A$4c 32 126\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "exemple to break the binary password 1101000:\n"
.section .rodata.str1.1
.LC4:
.string "breaker 1101000 48 49\n"
.LC5:
.string "*running parameters*\n"
.section .rodata.str1.8
.align 8
.LC6:
.string " -password length:\t%lu digits\n"
.section .rodata.str1.1
.LC7:
.string " -password length:\t%s digits\n"
.LC8:
.string " -digits:\t\tfrom -%c- to -%c-\n"
.LC9:
.string " -crypted to break:\t%d\n"
.LC12:
.string "time: %.1fs \n"
.LC13:
.string "time: %.1fmin \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $1, %edi
je .L25
movq %rsi, %rbx
cmpl $4, %edi
je .L29
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L29:
movq 8(%rsi), %r12
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
.L18:
movq %r12, %rdi
call strlen@PLT
movq %rax, (%rsp)
movl (%rsp), %r13d
movl %ebx, %ecx
movl %ebp, %edx
movl %r13d, %esi
movq %r12, %rdi
call _Z11get_keypairPciii
movl %eax, 36(%rsp)
movl $4, %edi
call malloc@PLT
movq %rax, 40(%rsp)
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call strlen@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movl %ebp, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 36(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
pxor %xmm2, %xmm2
cvtsi2ssq %rax, %xmm2
movss %xmm2, 28(%rsp)
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 36(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $16, 48(%rsp)
movl $1024, 60(%rsp)
fildl (%rsp)
leaq -32(%rsp), %rsp
.cfi_def_cfa_offset 160
fstpt 16(%rsp)
movl %ebx, %eax
subl %ebp, %eax
movl %eax, 32(%rsp)
fildl 32(%rsp)
fstpt (%rsp)
call powl@PLT
fstpt 32(%rsp)
addq $32, %rsp
.cfi_def_cfa_offset 128
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L20:
call cudaDeviceSynchronize@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
movss %xmm0, (%rsp)
leaq 36(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movss (%rsp), %xmm0
subss 28(%rsp), %xmm0
divss .LC10(%rip), %xmm0
movss .LC11(%rip), %xmm1
comiss %xmm0, %xmm1
jbe .L27
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L23:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $126, %ebx
movl $32, %ebp
leaq .LC0(%rip), %r12
jmp .L18
.L30:
fldt (%rsp)
fstpl (%rsp)
movsd (%rsp), %xmm0
movl %ebx, %ecx
movl %ebp, %edx
movl %r13d, %esi
movq 40(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiiiidPiiiid
jmp .L20
.L27:
divss .LC11(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L23
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z6kernelPiiiid"
.LC16:
.string "endLoop"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiiiid(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7endLoop(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7endLoop
.comm _ZL7endLoop,4,4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 1232348160
.align 4
.LC11:
.long 1114636288
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <sys/time.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <math.h>
#include <cuda.h>
__device__ int endLoop=0;
__device__ __host__ int get_keypair(char* tab, int length, int first_char, int last_char){
int sum=0;
int pow=1;
int i=0;
for(i=0; i<length; i++){
sum+=tab[i]*pow;
pow*=(last_char - first_char);
}
return sum;
}
__host__ __device__ int check_keypairs(int crypt, int test)
{
if(crypt == test){
return 1;
}
else{
return 0;
}
}
__global__ void kernel( int *crypted, int length, int first_char, int last_char, double max_iter){
int loop_size = last_char - first_char;
int i =blockIdx.x * blockDim.x + threadIdx.x;
int total = (blockDim.x * gridDim.x);
char *tab = (char*)malloc(sizeof(char)*(length+1));
tab[length]='\0';
int j;
for(j=0; j<length; j++) tab[j] = first_char;
int current_keypair;
int pow=0;
for(int j=i; j<max_iter; j+=total){
pow=1;
for(int x=0; x<length; x++){
tab[x] = ((j/pow) % loop_size) + first_char;
pow*=loop_size;
}
current_keypair = get_keypair(tab, length, first_char, last_char);
if( check_keypairs(*crypted, current_keypair) ) {
printf( "password found: %s\n", tab );
endLoop=1;
}
if(endLoop==1){
j=max_iter;
}
}
}
int main( int argc, char** argv ) {
char* password;
int first_char, last_char;
float t1, t2;
//unsigned long cmp;
if( argc == 1 ) {
password = "A$4c";
first_char = 32;
last_char = 126;
/* ---ASCII values---
* special characters: 32 to 47
* numbers: 48 to 57
* special characters: 58 to 64
* letters uppercase: 65 to 90
* special characters: 91 to 96
* letters lowercase: 97 to 122
* special characters: 123 to 126
* */
} else if( argc == 4 ) {
password = argv[1];
first_char = atoi( argv[2] );
last_char = atoi( argv[3] );
} else {
printf("usage: breaker <password> <first_ch> <last_ch>\n");
printf("default: breaker A$4c 32 126\n");
printf("exemple to break the binary password 1101000:\n");
printf( "breaker 1101000 48 49\n" );
exit( 0 );
}
int length = strlen(password);
int sz_in_bytes = sizeof(int);
int *h_crypted = (int *)malloc(sizeof(int));
int crypted_to_break= get_keypair(password, length, first_char, last_char);
h_crypted = &crypted_to_break;
int *d_crypted=(int *)malloc(sizeof(int));
printf( "*running parameters*\n" );
printf( " -password length:\t%lu digits\n", strlen(password) );
printf( " -password length:\t%s digits\n", password);
printf( " -digits:\t\tfrom -%c- to -%c-\n", first_char, last_char );
printf( " -crypted to break:\t%d\n", crypted_to_break);
t1 = clock();
cudaMalloc((void**)&d_crypted, sz_in_bytes);
cudaMemcpy(d_crypted, h_crypted, sz_in_bytes, cudaMemcpyHostToDevice);
dim3 nBlocks;
dim3 nThperBlock;
nBlocks.x = 16;
nThperBlock.x = 1024;
int loop_size = last_char - first_char;
double max_iter = powl(loop_size, length);
kernel<<< nBlocks , nThperBlock >>>(d_crypted, length, first_char, last_char, max_iter);
cudaDeviceSynchronize();
t2 = clock();
cudaMemcpy(h_crypted, d_crypted, sz_in_bytes, cudaMemcpyDeviceToHost);
cudaFree(d_crypted);
float period = (t2-t1)/CLOCKS_PER_SEC;
if( period < 60 ){
printf( "time: %.1fs \n", period );
}else{
printf( "time: %.1fmin \n", period/60 );
}
return EXIT_SUCCESS;
} | #include <stdlib.h>
#include <sys/time.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <math.h>
#include <hip/hip_runtime.h>
__device__ int endLoop=0;
__device__ __host__ int get_keypair(char* tab, int length, int first_char, int last_char){
int sum=0;
int pow=1;
int i=0;
for(i=0; i<length; i++){
sum+=tab[i]*pow;
pow*=(last_char - first_char);
}
return sum;
}
__host__ __device__ int check_keypairs(int crypt, int test)
{
if(crypt == test){
return 1;
}
else{
return 0;
}
}
__global__ void kernel( int *crypted, int length, int first_char, int last_char, double max_iter){
int loop_size = last_char - first_char;
int i =blockIdx.x * blockDim.x + threadIdx.x;
int total = (blockDim.x * gridDim.x);
char *tab = (char*)malloc(sizeof(char)*(length+1));
tab[length]='\0';
int j;
for(j=0; j<length; j++) tab[j] = first_char;
int current_keypair;
int pow=0;
for(int j=i; j<max_iter; j+=total){
pow=1;
for(int x=0; x<length; x++){
tab[x] = ((j/pow) % loop_size) + first_char;
pow*=loop_size;
}
current_keypair = get_keypair(tab, length, first_char, last_char);
if( check_keypairs(*crypted, current_keypair) ) {
printf( "password found: %s\n", tab );
endLoop=1;
}
if(endLoop==1){
j=max_iter;
}
}
}
int main( int argc, char** argv ) {
char* password;
int first_char, last_char;
float t1, t2;
//unsigned long cmp;
if( argc == 1 ) {
password = "A$4c";
first_char = 32;
last_char = 126;
/* ---ASCII values---
* special characters: 32 to 47
* numbers: 48 to 57
* special characters: 58 to 64
* letters uppercase: 65 to 90
* special characters: 91 to 96
* letters lowercase: 97 to 122
* special characters: 123 to 126
* */
} else if( argc == 4 ) {
password = argv[1];
first_char = atoi( argv[2] );
last_char = atoi( argv[3] );
} else {
printf("usage: breaker <password> <first_ch> <last_ch>\n");
printf("default: breaker A$4c 32 126\n");
printf("exemple to break the binary password 1101000:\n");
printf( "breaker 1101000 48 49\n" );
exit( 0 );
}
int length = strlen(password);
int sz_in_bytes = sizeof(int);
int *h_crypted = (int *)malloc(sizeof(int));
int crypted_to_break= get_keypair(password, length, first_char, last_char);
h_crypted = &crypted_to_break;
int *d_crypted=(int *)malloc(sizeof(int));
printf( "*running parameters*\n" );
printf( " -password length:\t%lu digits\n", strlen(password) );
printf( " -password length:\t%s digits\n", password);
printf( " -digits:\t\tfrom -%c- to -%c-\n", first_char, last_char );
printf( " -crypted to break:\t%d\n", crypted_to_break);
t1 = clock();
hipMalloc((void**)&d_crypted, sz_in_bytes);
hipMemcpy(d_crypted, h_crypted, sz_in_bytes, hipMemcpyHostToDevice);
dim3 nBlocks;
dim3 nThperBlock;
nBlocks.x = 16;
nThperBlock.x = 1024;
int loop_size = last_char - first_char;
double max_iter = powl(loop_size, length);
kernel<<< nBlocks , nThperBlock >>>(d_crypted, length, first_char, last_char, max_iter);
hipDeviceSynchronize();
t2 = clock();
hipMemcpy(h_crypted, d_crypted, sz_in_bytes, hipMemcpyDeviceToHost);
hipFree(d_crypted);
float period = (t2-t1)/CLOCKS_PER_SEC;
if( period < 60 ){
printf( "time: %.1fs \n", period );
}else{
printf( "time: %.1fmin \n", period/60 );
}
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <sys/time.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <math.h>
#include <hip/hip_runtime.h>
__device__ int endLoop=0;
__device__ __host__ int get_keypair(char* tab, int length, int first_char, int last_char){
int sum=0;
int pow=1;
int i=0;
for(i=0; i<length; i++){
sum+=tab[i]*pow;
pow*=(last_char - first_char);
}
return sum;
}
__host__ __device__ int check_keypairs(int crypt, int test)
{
if(crypt == test){
return 1;
}
else{
return 0;
}
}
__global__ void kernel( int *crypted, int length, int first_char, int last_char, double max_iter){
int loop_size = last_char - first_char;
int i =blockIdx.x * blockDim.x + threadIdx.x;
int total = (blockDim.x * gridDim.x);
char *tab = (char*)malloc(sizeof(char)*(length+1));
tab[length]='\0';
int j;
for(j=0; j<length; j++) tab[j] = first_char;
int current_keypair;
int pow=0;
for(int j=i; j<max_iter; j+=total){
pow=1;
for(int x=0; x<length; x++){
tab[x] = ((j/pow) % loop_size) + first_char;
pow*=loop_size;
}
current_keypair = get_keypair(tab, length, first_char, last_char);
if( check_keypairs(*crypted, current_keypair) ) {
printf( "password found: %s\n", tab );
endLoop=1;
}
if(endLoop==1){
j=max_iter;
}
}
}
int main( int argc, char** argv ) {
char* password;
int first_char, last_char;
float t1, t2;
//unsigned long cmp;
if( argc == 1 ) {
password = "A$4c";
first_char = 32;
last_char = 126;
/* ---ASCII values---
* special characters: 32 to 47
* numbers: 48 to 57
* special characters: 58 to 64
* letters uppercase: 65 to 90
* special characters: 91 to 96
* letters lowercase: 97 to 122
* special characters: 123 to 126
* */
} else if( argc == 4 ) {
password = argv[1];
first_char = atoi( argv[2] );
last_char = atoi( argv[3] );
} else {
printf("usage: breaker <password> <first_ch> <last_ch>\n");
printf("default: breaker A$4c 32 126\n");
printf("exemple to break the binary password 1101000:\n");
printf( "breaker 1101000 48 49\n" );
exit( 0 );
}
int length = strlen(password);
int sz_in_bytes = sizeof(int);
int *h_crypted = (int *)malloc(sizeof(int));
int crypted_to_break= get_keypair(password, length, first_char, last_char);
h_crypted = &crypted_to_break;
int *d_crypted=(int *)malloc(sizeof(int));
printf( "*running parameters*\n" );
printf( " -password length:\t%lu digits\n", strlen(password) );
printf( " -password length:\t%s digits\n", password);
printf( " -digits:\t\tfrom -%c- to -%c-\n", first_char, last_char );
printf( " -crypted to break:\t%d\n", crypted_to_break);
t1 = clock();
hipMalloc((void**)&d_crypted, sz_in_bytes);
hipMemcpy(d_crypted, h_crypted, sz_in_bytes, hipMemcpyHostToDevice);
dim3 nBlocks;
dim3 nThperBlock;
nBlocks.x = 16;
nThperBlock.x = 1024;
int loop_size = last_char - first_char;
double max_iter = powl(loop_size, length);
kernel<<< nBlocks , nThperBlock >>>(d_crypted, length, first_char, last_char, max_iter);
hipDeviceSynchronize();
t2 = clock();
hipMemcpy(h_crypted, d_crypted, sz_in_bytes, hipMemcpyDeviceToHost);
hipFree(d_crypted);
float period = (t2-t1)/CLOCKS_PER_SEC;
if( period < 60 ){
printf( "time: %.1fs \n", period );
}else{
printf( "time: %.1fmin \n", period/60 );
}
return EXIT_SUCCESS;
} | .text
.file "Breaker_for.hip"
.globl _Z11get_keypairPciii # -- Begin function _Z11get_keypairPciii
.p2align 4, 0x90
.type _Z11get_keypairPciii,@function
_Z11get_keypairPciii: # @_Z11get_keypairPciii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_1
# %bb.2: # %.lr.ph
subl %edx, %ecx
movl %esi, %edx
xorl %esi, %esi
movl $1, %r8d
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movsbl (%rdi,%rsi), %r9d
imull %r8d, %r9d
addl %r9d, %eax
imull %ecx, %r8d
incq %rsi
cmpq %rsi, %rdx
jne .LBB0_3
# %bb.4: # %._crit_edge
retq
.LBB0_1:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z11get_keypairPciii, .Lfunc_end0-_Z11get_keypairPciii
.cfi_endproc
# -- End function
.globl _Z14check_keypairsii # -- Begin function _Z14check_keypairsii
.p2align 4, 0x90
.type _Z14check_keypairsii,@function
_Z14check_keypairsii: # @_Z14check_keypairsii
.cfi_startproc
# %bb.0:
xorl %eax, %eax
cmpl %esi, %edi
sete %al
retq
.Lfunc_end1:
.size _Z14check_keypairsii, .Lfunc_end1-_Z14check_keypairsii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__kernelPiiiid # -- Begin function _Z21__device_stub__kernelPiiiid
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiiiid,@function
_Z21__device_stub__kernelPiiiid: # @_Z21__device_stub__kernelPiiiid
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movsd %xmm0, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPiiiid, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z21__device_stub__kernelPiiiid, .Lfunc_end2-_Z21__device_stub__kernelPiiiid
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x49742400 # float 1.0E+6
.LCPI3_1:
.long 0x42700000 # float 60
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $184, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
je .LBB3_1
# %bb.2:
cmpl $4, %edi
jne .LBB3_13
# %bb.3:
movq 8(%rsi), %r12
movq 16(%rsi), %rdi
movq %rsi, %r14
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB3_4
.LBB3_1:
movl $.L.str, %r12d
movl $32, %ebx
movl $126, %r14d
.LBB3_4:
movq %r12, %rdi
callq strlen
movq %rax, %r15
testl %r15d, %r15d
jle .LBB3_5
# %bb.6: # %.lr.ph.i
movl %r14d, %eax
subl %ebx, %eax
movl %r15d, %ecx
xorl %edx, %edx
movl $1, %edi
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
movsbl (%r12,%rdx), %r8d
imull %edi, %r8d
addl %r8d, %esi
imull %eax, %edi
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_7
jmp .LBB3_8
.LBB3_5:
xorl %esi, %esi
.LBB3_8: # %_Z11get_keypairPciii.exit
movl %esi, 36(%rsp)
movl $4, %edi
callq malloc
movq %rax, 40(%rsp)
movl $.Lstr.4, %edi
callq puts@PLT
movq %r12, %rdi
callq strlen
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
movq %r12, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.8, %edi
movl %ebx, %esi
movl %r14d, %edx
xorl %eax, %eax
callq printf
movl 36(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
callq clock
movq %rax, %r12
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 40(%rsp), %rdi
leaq 36(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl %r14d, %eax
subl %ebx, %eax
movl %eax, 64(%rsp)
fildl 64(%rsp)
movl %r15d, 60(%rsp)
fildl 60(%rsp)
fstpt 16(%rsp)
fstpt (%rsp)
callq powl
fstpt 48(%rsp) # 10-byte Folded Spill
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 1008(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 40(%rsp), %rax
movq %rax, 136(%rsp)
movl %r15d, 76(%rsp)
movl %ebx, 72(%rsp)
movl %r14d, 68(%rsp)
fldt 48(%rsp) # 10-byte Folded Reload
fstpl 128(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 76(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 68(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rax
movq 80(%rsp), %rdi
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 144(%rsp), %r9
movl $_Z6kernelPiiiid, %edi
callq hipLaunchKernel
.LBB3_10:
cvtsi2ss %r12, %xmm0
movss %xmm0, 48(%rsp) # 4-byte Spill
callq hipDeviceSynchronize
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
subss 48(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 48(%rsp) # 4-byte Spill
movq 40(%rsp), %rsi
leaq 36(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movss 48(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
divss .LCPI3_0(%rip), %xmm1
movss .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
ja .LBB3_12
# %bb.11:
divss %xmm0, %xmm1
.LBB3_12:
movl $.L.str.10, %eax
movl $.L.str.11, %edi
cmovaq %rax, %rdi
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movb $1, %al
callq printf
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_13:
.cfi_def_cfa_offset 224
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiiiid, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $endLoop, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type endLoop,@object # @endLoop
.local endLoop
.comm endLoop,4,4
.type _Z6kernelPiiiid,@object # @_Z6kernelPiiiid
.section .rodata,"a",@progbits
.globl _Z6kernelPiiiid
.p2align 3, 0x0
_Z6kernelPiiiid:
.quad _Z21__device_stub__kernelPiiiid
.size _Z6kernelPiiiid, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A$4c"
.size .L.str, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " -password length:\t%lu digits\n"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " -password length:\t%s digits\n"
.size .L.str.7, 30
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " -digits:\t\tfrom -%c- to -%c-\n"
.size .L.str.8, 30
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " -crypted to break:\t%d\n"
.size .L.str.9, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "time: %.1fs \n"
.size .L.str.10, 14
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "time: %.1fmin \n"
.size .L.str.11, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiiiid"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "endLoop"
.size .L__unnamed_2, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: breaker <password> <first_ch> <last_ch>"
.size .Lstr, 47
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "default: breaker A$4c 32 126"
.size .Lstr.1, 29
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "exemple to break the binary password 1101000:"
.size .Lstr.2, 46
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "breaker 1101000 48 49"
.size .Lstr.3, 22
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "*running parameters*"
.size .Lstr.4, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiiiid
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym endLoop
.addrsig_sym _Z6kernelPiiiid
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00117789_00000000-6_Breaker_for.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11get_keypairPciii
.type _Z11get_keypairPciii, @function
_Z11get_keypairPciii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L6
movq %rdi, %rax
movslq %esi, %rsi
addq %rsi, %rdi
movl $1, %esi
movl $0, %r8d
subl %edx, %ecx
.L5:
movsbl (%rax), %edx
imull %esi, %edx
addl %edx, %r8d
imull %ecx, %esi
addq $1, %rax
cmpq %rdi, %rax
jne .L5
.L3:
movl %r8d, %eax
ret
.L6:
movl $0, %r8d
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z11get_keypairPciii, .-_Z11get_keypairPciii
.globl _Z14check_keypairsii
.type _Z14check_keypairsii, @function
_Z14check_keypairsii:
.LFB2058:
.cfi_startproc
endbr64
cmpl %esi, %edi
sete %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z14check_keypairsii, .-_Z14check_keypairsii
.globl _Z29__device_stub__Z6kernelPiiiidPiiiid
.type _Z29__device_stub__Z6kernelPiiiidPiiiid, @function
_Z29__device_stub__Z6kernelPiiiidPiiiid:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPiiiid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z6kernelPiiiidPiiiid, .-_Z29__device_stub__Z6kernelPiiiidPiiiid
.globl _Z6kernelPiiiid
.type _Z6kernelPiiiid, @function
_Z6kernelPiiiid:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPiiiidPiiiid
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6kernelPiiiid, .-_Z6kernelPiiiid
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "A$4c"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "usage: breaker <password> <first_ch> <last_ch>\n"
.section .rodata.str1.1
.LC2:
.string "default: breaker A$4c 32 126\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "exemple to break the binary password 1101000:\n"
.section .rodata.str1.1
.LC4:
.string "breaker 1101000 48 49\n"
.LC5:
.string "*running parameters*\n"
.section .rodata.str1.8
.align 8
.LC6:
.string " -password length:\t%lu digits\n"
.section .rodata.str1.1
.LC7:
.string " -password length:\t%s digits\n"
.LC8:
.string " -digits:\t\tfrom -%c- to -%c-\n"
.LC9:
.string " -crypted to break:\t%d\n"
.LC12:
.string "time: %.1fs \n"
.LC13:
.string "time: %.1fmin \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $1, %edi
je .L25
movq %rsi, %rbx
cmpl $4, %edi
je .L29
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L29:
movq 8(%rsi), %r12
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
.L18:
movq %r12, %rdi
call strlen@PLT
movq %rax, (%rsp)
movl (%rsp), %r13d
movl %ebx, %ecx
movl %ebp, %edx
movl %r13d, %esi
movq %r12, %rdi
call _Z11get_keypairPciii
movl %eax, 36(%rsp)
movl $4, %edi
call malloc@PLT
movq %rax, 40(%rsp)
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call strlen@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movl %ebp, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 36(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
pxor %xmm2, %xmm2
cvtsi2ssq %rax, %xmm2
movss %xmm2, 28(%rsp)
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 36(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $16, 48(%rsp)
movl $1024, 60(%rsp)
fildl (%rsp)
leaq -32(%rsp), %rsp
.cfi_def_cfa_offset 160
fstpt 16(%rsp)
movl %ebx, %eax
subl %ebp, %eax
movl %eax, 32(%rsp)
fildl 32(%rsp)
fstpt (%rsp)
call powl@PLT
fstpt 32(%rsp)
addq $32, %rsp
.cfi_def_cfa_offset 128
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L20:
call cudaDeviceSynchronize@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
movss %xmm0, (%rsp)
leaq 36(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movss (%rsp), %xmm0
subss 28(%rsp), %xmm0
divss .LC10(%rip), %xmm0
movss .LC11(%rip), %xmm1
comiss %xmm0, %xmm1
jbe .L27
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L23:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl $126, %ebx
movl $32, %ebp
leaq .LC0(%rip), %r12
jmp .L18
.L30:
fldt (%rsp)
fstpl (%rsp)
movsd (%rsp), %xmm0
movl %ebx, %ecx
movl %ebp, %edx
movl %r13d, %esi
movq 40(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiiiidPiiiid
jmp .L20
.L27:
divss .LC11(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L23
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z6kernelPiiiid"
.LC16:
.string "endLoop"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiiiid(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7endLoop(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7endLoop
.comm _ZL7endLoop,4,4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 1232348160
.align 4
.LC11:
.long 1114636288
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Breaker_for.hip"
.globl _Z11get_keypairPciii # -- Begin function _Z11get_keypairPciii
.p2align 4, 0x90
.type _Z11get_keypairPciii,@function
_Z11get_keypairPciii: # @_Z11get_keypairPciii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_1
# %bb.2: # %.lr.ph
subl %edx, %ecx
movl %esi, %edx
xorl %esi, %esi
movl $1, %r8d
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movsbl (%rdi,%rsi), %r9d
imull %r8d, %r9d
addl %r9d, %eax
imull %ecx, %r8d
incq %rsi
cmpq %rsi, %rdx
jne .LBB0_3
# %bb.4: # %._crit_edge
retq
.LBB0_1:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z11get_keypairPciii, .Lfunc_end0-_Z11get_keypairPciii
.cfi_endproc
# -- End function
.globl _Z14check_keypairsii # -- Begin function _Z14check_keypairsii
.p2align 4, 0x90
.type _Z14check_keypairsii,@function
_Z14check_keypairsii: # @_Z14check_keypairsii
.cfi_startproc
# %bb.0:
xorl %eax, %eax
cmpl %esi, %edi
sete %al
retq
.Lfunc_end1:
.size _Z14check_keypairsii, .Lfunc_end1-_Z14check_keypairsii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__kernelPiiiid # -- Begin function _Z21__device_stub__kernelPiiiid
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiiiid,@function
_Z21__device_stub__kernelPiiiid: # @_Z21__device_stub__kernelPiiiid
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movsd %xmm0, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPiiiid, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z21__device_stub__kernelPiiiid, .Lfunc_end2-_Z21__device_stub__kernelPiiiid
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x49742400 # float 1.0E+6
.LCPI3_1:
.long 0x42700000 # float 60
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $184, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
je .LBB3_1
# %bb.2:
cmpl $4, %edi
jne .LBB3_13
# %bb.3:
movq 8(%rsi), %r12
movq 16(%rsi), %rdi
movq %rsi, %r14
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB3_4
.LBB3_1:
movl $.L.str, %r12d
movl $32, %ebx
movl $126, %r14d
.LBB3_4:
movq %r12, %rdi
callq strlen
movq %rax, %r15
testl %r15d, %r15d
jle .LBB3_5
# %bb.6: # %.lr.ph.i
movl %r14d, %eax
subl %ebx, %eax
movl %r15d, %ecx
xorl %edx, %edx
movl $1, %edi
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
movsbl (%r12,%rdx), %r8d
imull %edi, %r8d
addl %r8d, %esi
imull %eax, %edi
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_7
jmp .LBB3_8
.LBB3_5:
xorl %esi, %esi
.LBB3_8: # %_Z11get_keypairPciii.exit
movl %esi, 36(%rsp)
movl $4, %edi
callq malloc
movq %rax, 40(%rsp)
movl $.Lstr.4, %edi
callq puts@PLT
movq %r12, %rdi
callq strlen
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
movq %r12, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.8, %edi
movl %ebx, %esi
movl %r14d, %edx
xorl %eax, %eax
callq printf
movl 36(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
callq clock
movq %rax, %r12
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 40(%rsp), %rdi
leaq 36(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl %r14d, %eax
subl %ebx, %eax
movl %eax, 64(%rsp)
fildl 64(%rsp)
movl %r15d, 60(%rsp)
fildl 60(%rsp)
fstpt 16(%rsp)
fstpt (%rsp)
callq powl
fstpt 48(%rsp) # 10-byte Folded Spill
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 1008(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 40(%rsp), %rax
movq %rax, 136(%rsp)
movl %r15d, 76(%rsp)
movl %ebx, 72(%rsp)
movl %r14d, 68(%rsp)
fldt 48(%rsp) # 10-byte Folded Reload
fstpl 128(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 76(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 68(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rax
movq 80(%rsp), %rdi
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 144(%rsp), %r9
movl $_Z6kernelPiiiid, %edi
callq hipLaunchKernel
.LBB3_10:
cvtsi2ss %r12, %xmm0
movss %xmm0, 48(%rsp) # 4-byte Spill
callq hipDeviceSynchronize
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
subss 48(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 48(%rsp) # 4-byte Spill
movq 40(%rsp), %rsi
leaq 36(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movss 48(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
divss .LCPI3_0(%rip), %xmm1
movss .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
ja .LBB3_12
# %bb.11:
divss %xmm0, %xmm1
.LBB3_12:
movl $.L.str.10, %eax
movl $.L.str.11, %edi
cmovaq %rax, %rdi
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movb $1, %al
callq printf
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_13:
.cfi_def_cfa_offset 224
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiiiid, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $endLoop, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type endLoop,@object # @endLoop
.local endLoop
.comm endLoop,4,4
.type _Z6kernelPiiiid,@object # @_Z6kernelPiiiid
.section .rodata,"a",@progbits
.globl _Z6kernelPiiiid
.p2align 3, 0x0
_Z6kernelPiiiid:
.quad _Z21__device_stub__kernelPiiiid
.size _Z6kernelPiiiid, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A$4c"
.size .L.str, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " -password length:\t%lu digits\n"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " -password length:\t%s digits\n"
.size .L.str.7, 30
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " -digits:\t\tfrom -%c- to -%c-\n"
.size .L.str.8, 30
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " -crypted to break:\t%d\n"
.size .L.str.9, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "time: %.1fs \n"
.size .L.str.10, 14
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "time: %.1fmin \n"
.size .L.str.11, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiiiid"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "endLoop"
.size .L__unnamed_2, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: breaker <password> <first_ch> <last_ch>"
.size .Lstr, 47
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "default: breaker A$4c 32 126"
.size .Lstr.1, 29
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "exemple to break the binary password 1101000:"
.size .Lstr.2, 46
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "breaker 1101000 48 49"
.size .Lstr.3, 22
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "*running parameters*"
.size .Lstr.4, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiiiid
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym endLoop
.addrsig_sym _Z6kernelPiiiid
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<cuda.h>
#include <sys/time.h>
#include <thrust/sort.h>
#include <thrust/execution_policy.h>
#include <algorithm>
using namespace std;
#define BLOCKSIZE 1024
__global__ void initialize(pair<float, int> * gputimes, unsigned n){
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
if(id < n)
gputimes[id].first = 0;
gputimes[id].second = id;
}
__global__ void add_time(pair<float, int> * gputimes, unsigned vectorSize, int* gpuspeed, int i, int dis){
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
if(id < vectorSize)
gputimes[id].first += 60* float(dis)/gpuspeed[i*vectorSize + gputimes[id].second];
}
__global__ void queue(pair<float, int> * gputimes, unsigned vectorSize, int x){
unsigned id = threadIdx.x;
for (int i =0; i < ceil(float(vectorSize)/blockDim.x); ++i){
if(id + (i+1)* blockDim.x < vectorSize){
if(gputimes[id + (i+1) * blockDim.x].first < gputimes[id + i * blockDim.x].first + x){
gputimes[id + (i+1) * blockDim.x].first = gputimes[id + i * blockDim.x].first + x;
}
}
gputimes[id + i * blockDim.x].first = gputimes[id + i * blockDim.x].first + x;
}
}
//Complete the following function
void operations ( int n, int k, int m, int x, int dis, int *speed, int **results ) {
pair<float, int> *times = (pair<float, int> *) malloc ( n * sizeof (pair<float, int>) );
pair<float, int> *gputimes;
int *gpuspeed;
cudaMalloc(&gputimes, n * sizeof (pair<float, int>));
cudaMalloc(&gpuspeed, n*( k+1 ) * sizeof (int));
cudaMemcpy(gpuspeed, speed, n*( k+1 ) * sizeof (int), cudaMemcpyHostToDevice);
unsigned nblocks = ceil(float(n) / BLOCKSIZE);
//initialization
cudaMemcpy(gputimes, times, n * sizeof (pair<float, int>), cudaMemcpyHostToDevice);
initialize<<<nblocks, BLOCKSIZE>>>(gputimes, n);
cudaDeviceSynchronize();
cudaMemcpy(times, gputimes, n * sizeof (pair<float, int>), cudaMemcpyDeviceToHost);
for (int i = 0; i < k+1; ++i){
/*
cudaMemcpy(gputimes, times, n * sizeof (pair<float, int>), cudaMemcpyHostToDevice);
add_time<<<nblocks, BLOCKSIZE>>>(gputimes, n, gpuspeed, i, dis);
cudaMemcpy(times, gputimes, n * sizeof (pair<float, int>), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
*/
for(int j = 0; j< n; j++){
times[j].first += 60* float(dis)/speed[i*n + times[j].second];
}
thrust::sort(thrust::host, times, times + n);
//sort(times, times+ n);
results[0][i] = times[0].second+1;
results[1][i] = times[n-1].second+1;
cudaMemcpy(gputimes, times, n * sizeof (pair<float, int>), cudaMemcpyHostToDevice);
queue<<<1, m>>>(gputimes, n, x);
cudaDeviceSynchronize();
cudaMemcpy(times, gputimes, n * sizeof (pair<float, int>), cudaMemcpyDeviceToHost);
}
for(int i = 0; i< n; ++i){
results[2][times[i].second] = int(times[i].first) - x;
}
}
int main(int argc,char **argv){
//variable declarations
int n,k,m,x;
int dis;
//Input file pointer declaration
FILE *inputfilepointer;
//File Opening for read
char *inputfilename = argv[1];
inputfilepointer = fopen( inputfilename , "r");
//Checking if file ptr is NULL
if ( inputfilepointer == NULL ) {
printf( "input.txt file failed to open." );
return 0;
}
fscanf( inputfilepointer, "%d", &n ); //scaning for number of vehicles
fscanf( inputfilepointer, "%d", &k ); //scaning for number of toll tax zones
fscanf( inputfilepointer, "%d", &m ); //scaning for number of toll tax points
fscanf( inputfilepointer, "%d", &x ); //scaning for toll tax zone passing time
fscanf( inputfilepointer, "%d", &dis ); //scaning for distance between two consecutive toll tax zones
// scanning for speeds of each vehicles for every subsequent toll tax combinations
int *speed = (int *) malloc ( n*( k+1 ) * sizeof (int) );
for ( int i=0; i<=k; i++ ) {
for ( int j=0; j<n; j++ ) {
fscanf( inputfilepointer, "%d", &speed[i*n+j] );
}
}
// results is in the format of first crossing vehicles list, last crossing vehicles list
// and total time taken by each vehicles to pass the highway
int **results = (int **) malloc ( 3 * sizeof (int *) );
results[0] = (int *) malloc ( (k+1) * sizeof (int) );
results[1] = (int *) malloc ( (k+1) * sizeof (int) );
results[2] = (int *) malloc ( (n) * sizeof (int) );
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
cudaEventRecord(start,0);
// Function given to implement
operations ( n, k, m, x, dis, speed, results );
cudaDeviceSynchronize();
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Time taken by function to execute is: %.6f ms\n", milliseconds);
// Output file pointer declaration
char *outputfilename = argv[2];
FILE *outputfilepointer;
outputfilepointer = fopen(outputfilename,"w");
// First crossing vehicles list
for ( int i=0; i<=k; i++ ) {
fprintf( outputfilepointer, "%d ", results[0][i]);
}
fprintf( outputfilepointer, "\n");
//Last crossing vehicles list
for ( int i=0; i<=k; i++ ) {
fprintf( outputfilepointer, "%d ", results[1][i]);
}
fprintf( outputfilepointer, "\n");
//Total time taken by each vehicles to pass the highway
for ( int i=0; i<n; i++ ) {
fprintf( outputfilepointer, "%d ", results[2][i]);
}
fprintf( outputfilepointer, "\n");
fclose( outputfilepointer );
fclose( inputfilepointer );
return 0;
} | #include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#include <sys/time.h>
#include <thrust/sort.h>
#include <thrust/execution_policy.h>
#include <algorithm>
using namespace std;
#define BLOCKSIZE 1024
__global__ void initialize(pair<float, int> * gputimes, unsigned n){
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
if(id < n)
gputimes[id].first = 0;
gputimes[id].second = id;
}
__global__ void add_time(pair<float, int> * gputimes, unsigned vectorSize, int* gpuspeed, int i, int dis){
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
if(id < vectorSize)
gputimes[id].first += 60* float(dis)/gpuspeed[i*vectorSize + gputimes[id].second];
}
__global__ void queue(pair<float, int> * gputimes, unsigned vectorSize, int x){
unsigned id = threadIdx.x;
for (int i =0; i < ceil(float(vectorSize)/blockDim.x); ++i){
if(id + (i+1)* blockDim.x < vectorSize){
if(gputimes[id + (i+1) * blockDim.x].first < gputimes[id + i * blockDim.x].first + x){
gputimes[id + (i+1) * blockDim.x].first = gputimes[id + i * blockDim.x].first + x;
}
}
gputimes[id + i * blockDim.x].first = gputimes[id + i * blockDim.x].first + x;
}
}
//Complete the following function
void operations ( int n, int k, int m, int x, int dis, int *speed, int **results ) {
pair<float, int> *times = (pair<float, int> *) malloc ( n * sizeof (pair<float, int>) );
pair<float, int> *gputimes;
int *gpuspeed;
hipMalloc(&gputimes, n * sizeof (pair<float, int>));
hipMalloc(&gpuspeed, n*( k+1 ) * sizeof (int));
hipMemcpy(gpuspeed, speed, n*( k+1 ) * sizeof (int), hipMemcpyHostToDevice);
unsigned nblocks = ceil(float(n) / BLOCKSIZE);
//initialization
hipMemcpy(gputimes, times, n * sizeof (pair<float, int>), hipMemcpyHostToDevice);
initialize<<<nblocks, BLOCKSIZE>>>(gputimes, n);
hipDeviceSynchronize();
hipMemcpy(times, gputimes, n * sizeof (pair<float, int>), hipMemcpyDeviceToHost);
for (int i = 0; i < k+1; ++i){
/*
cudaMemcpy(gputimes, times, n * sizeof (pair<float, int>), cudaMemcpyHostToDevice);
add_time<<<nblocks, BLOCKSIZE>>>(gputimes, n, gpuspeed, i, dis);
cudaMemcpy(times, gputimes, n * sizeof (pair<float, int>), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
*/
for(int j = 0; j< n; j++){
times[j].first += 60* float(dis)/speed[i*n + times[j].second];
}
thrust::sort(thrust::host, times, times + n);
//sort(times, times+ n);
results[0][i] = times[0].second+1;
results[1][i] = times[n-1].second+1;
hipMemcpy(gputimes, times, n * sizeof (pair<float, int>), hipMemcpyHostToDevice);
queue<<<1, m>>>(gputimes, n, x);
hipDeviceSynchronize();
hipMemcpy(times, gputimes, n * sizeof (pair<float, int>), hipMemcpyDeviceToHost);
}
for(int i = 0; i< n; ++i){
results[2][times[i].second] = int(times[i].first) - x;
}
}
int main(int argc,char **argv){
//variable declarations
int n,k,m,x;
int dis;
//Input file pointer declaration
FILE *inputfilepointer;
//File Opening for read
char *inputfilename = argv[1];
inputfilepointer = fopen( inputfilename , "r");
//Checking if file ptr is NULL
if ( inputfilepointer == NULL ) {
printf( "input.txt file failed to open." );
return 0;
}
fscanf( inputfilepointer, "%d", &n ); //scaning for number of vehicles
fscanf( inputfilepointer, "%d", &k ); //scaning for number of toll tax zones
fscanf( inputfilepointer, "%d", &m ); //scaning for number of toll tax points
fscanf( inputfilepointer, "%d", &x ); //scaning for toll tax zone passing time
fscanf( inputfilepointer, "%d", &dis ); //scaning for distance between two consecutive toll tax zones
// scanning for speeds of each vehicles for every subsequent toll tax combinations
int *speed = (int *) malloc ( n*( k+1 ) * sizeof (int) );
for ( int i=0; i<=k; i++ ) {
for ( int j=0; j<n; j++ ) {
fscanf( inputfilepointer, "%d", &speed[i*n+j] );
}
}
// results is in the format of first crossing vehicles list, last crossing vehicles list
// and total time taken by each vehicles to pass the highway
int **results = (int **) malloc ( 3 * sizeof (int *) );
results[0] = (int *) malloc ( (k+1) * sizeof (int) );
results[1] = (int *) malloc ( (k+1) * sizeof (int) );
results[2] = (int *) malloc ( (n) * sizeof (int) );
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
hipEventRecord(start,0);
// Function given to implement
operations ( n, k, m, x, dis, speed, results );
hipDeviceSynchronize();
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
printf("Time taken by function to execute is: %.6f ms\n", milliseconds);
// Output file pointer declaration
char *outputfilename = argv[2];
FILE *outputfilepointer;
outputfilepointer = fopen(outputfilename,"w");
// First crossing vehicles list
for ( int i=0; i<=k; i++ ) {
fprintf( outputfilepointer, "%d ", results[0][i]);
}
fprintf( outputfilepointer, "\n");
//Last crossing vehicles list
for ( int i=0; i<=k; i++ ) {
fprintf( outputfilepointer, "%d ", results[1][i]);
}
fprintf( outputfilepointer, "\n");
//Total time taken by each vehicles to pass the highway
for ( int i=0; i<n; i++ ) {
fprintf( outputfilepointer, "%d ", results[2][i]);
}
fprintf( outputfilepointer, "\n");
fclose( outputfilepointer );
fclose( inputfilepointer );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#include <sys/time.h>
#include <thrust/sort.h>
#include <thrust/execution_policy.h>
#include <algorithm>
using namespace std;
#define BLOCKSIZE 1024
__global__ void initialize(pair<float, int> * gputimes, unsigned n){
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
if(id < n)
gputimes[id].first = 0;
gputimes[id].second = id;
}
__global__ void add_time(pair<float, int> * gputimes, unsigned vectorSize, int* gpuspeed, int i, int dis){
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
if(id < vectorSize)
gputimes[id].first += 60* float(dis)/gpuspeed[i*vectorSize + gputimes[id].second];
}
__global__ void queue(pair<float, int> * gputimes, unsigned vectorSize, int x){
unsigned id = threadIdx.x;
for (int i =0; i < ceil(float(vectorSize)/blockDim.x); ++i){
if(id + (i+1)* blockDim.x < vectorSize){
if(gputimes[id + (i+1) * blockDim.x].first < gputimes[id + i * blockDim.x].first + x){
gputimes[id + (i+1) * blockDim.x].first = gputimes[id + i * blockDim.x].first + x;
}
}
gputimes[id + i * blockDim.x].first = gputimes[id + i * blockDim.x].first + x;
}
}
//Complete the following function
void operations ( int n, int k, int m, int x, int dis, int *speed, int **results ) {
pair<float, int> *times = (pair<float, int> *) malloc ( n * sizeof (pair<float, int>) );
pair<float, int> *gputimes;
int *gpuspeed;
hipMalloc(&gputimes, n * sizeof (pair<float, int>));
hipMalloc(&gpuspeed, n*( k+1 ) * sizeof (int));
hipMemcpy(gpuspeed, speed, n*( k+1 ) * sizeof (int), hipMemcpyHostToDevice);
unsigned nblocks = ceil(float(n) / BLOCKSIZE);
//initialization
hipMemcpy(gputimes, times, n * sizeof (pair<float, int>), hipMemcpyHostToDevice);
initialize<<<nblocks, BLOCKSIZE>>>(gputimes, n);
hipDeviceSynchronize();
hipMemcpy(times, gputimes, n * sizeof (pair<float, int>), hipMemcpyDeviceToHost);
for (int i = 0; i < k+1; ++i){
/*
cudaMemcpy(gputimes, times, n * sizeof (pair<float, int>), cudaMemcpyHostToDevice);
add_time<<<nblocks, BLOCKSIZE>>>(gputimes, n, gpuspeed, i, dis);
cudaMemcpy(times, gputimes, n * sizeof (pair<float, int>), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
*/
for(int j = 0; j< n; j++){
times[j].first += 60* float(dis)/speed[i*n + times[j].second];
}
thrust::sort(thrust::host, times, times + n);
//sort(times, times+ n);
results[0][i] = times[0].second+1;
results[1][i] = times[n-1].second+1;
hipMemcpy(gputimes, times, n * sizeof (pair<float, int>), hipMemcpyHostToDevice);
queue<<<1, m>>>(gputimes, n, x);
hipDeviceSynchronize();
hipMemcpy(times, gputimes, n * sizeof (pair<float, int>), hipMemcpyDeviceToHost);
}
for(int i = 0; i< n; ++i){
results[2][times[i].second] = int(times[i].first) - x;
}
}
int main(int argc,char **argv){
//variable declarations
int n,k,m,x;
int dis;
//Input file pointer declaration
FILE *inputfilepointer;
//File Opening for read
char *inputfilename = argv[1];
inputfilepointer = fopen( inputfilename , "r");
//Checking if file ptr is NULL
if ( inputfilepointer == NULL ) {
printf( "input.txt file failed to open." );
return 0;
}
fscanf( inputfilepointer, "%d", &n ); //scaning for number of vehicles
fscanf( inputfilepointer, "%d", &k ); //scaning for number of toll tax zones
fscanf( inputfilepointer, "%d", &m ); //scaning for number of toll tax points
fscanf( inputfilepointer, "%d", &x ); //scaning for toll tax zone passing time
fscanf( inputfilepointer, "%d", &dis ); //scaning for distance between two consecutive toll tax zones
// scanning for speeds of each vehicles for every subsequent toll tax combinations
int *speed = (int *) malloc ( n*( k+1 ) * sizeof (int) );
for ( int i=0; i<=k; i++ ) {
for ( int j=0; j<n; j++ ) {
fscanf( inputfilepointer, "%d", &speed[i*n+j] );
}
}
// results is in the format of first crossing vehicles list, last crossing vehicles list
// and total time taken by each vehicles to pass the highway
int **results = (int **) malloc ( 3 * sizeof (int *) );
results[0] = (int *) malloc ( (k+1) * sizeof (int) );
results[1] = (int *) malloc ( (k+1) * sizeof (int) );
results[2] = (int *) malloc ( (n) * sizeof (int) );
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
hipEventRecord(start,0);
// Function given to implement
operations ( n, k, m, x, dis, speed, results );
hipDeviceSynchronize();
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
printf("Time taken by function to execute is: %.6f ms\n", milliseconds);
// Output file pointer declaration
char *outputfilename = argv[2];
FILE *outputfilepointer;
outputfilepointer = fopen(outputfilename,"w");
// First crossing vehicles list
for ( int i=0; i<=k; i++ ) {
fprintf( outputfilepointer, "%d ", results[0][i]);
}
fprintf( outputfilepointer, "\n");
//Last crossing vehicles list
for ( int i=0; i<=k; i++ ) {
fprintf( outputfilepointer, "%d ", results[1][i]);
}
fprintf( outputfilepointer, "\n");
//Total time taken by each vehicles to pass the highway
for ( int i=0; i<n; i++ ) {
fprintf( outputfilepointer, "%d ", results[2][i]);
}
fprintf( outputfilepointer, "\n");
fclose( outputfilepointer );
fclose( inputfilepointer );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializePSt4pairIfiEj
.globl _Z10initializePSt4pairIfiEj
.p2align 8
.type _Z10initializePSt4pairIfiEj,@function
_Z10initializePSt4pairIfiEj:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[3:4], v2, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off offset:4
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializePSt4pairIfiEj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10initializePSt4pairIfiEj, .Lfunc_end0-_Z10initializePSt4pairIfiEj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8add_timePSt4pairIfiEjPiii
.globl _Z8add_timePSt4pairIfiEjPiii
.p2align 8
.type _Z8add_timePSt4pairIfiEjPiii,@function
_Z8add_timePSt4pairIfiEjPiii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_load_b64 v[3:4], v[0:1], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, s6, s2, v[4:5]
v_mov_b32_e32 v6, v2
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
v_cvt_f32_i32_e32 v4, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x42700000, v4
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v2, v2
v_div_scale_f32 v5, null, v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v7, vcc_lo, v4, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v7, v6
v_fma_f32 v9, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v6
v_fma_f32 v5, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v6, v8
v_div_fixup_f32 v2, v5, v2, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8add_timePSt4pairIfiEjPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8add_timePSt4pairIfiEjPiii, .Lfunc_end1-_Z8add_timePSt4pairIfiEjPiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5queuePSt4pairIfiEji
.globl _Z5queuePSt4pairIfiEji
.p2align 8
.type _Z5queuePSt4pairIfiEji,@function
_Z5queuePSt4pairIfiEji:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
v_cvt_f32_u32_e32 v1, s2
v_cvt_f32_u32_e32 v2, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v3, null, v2, v2, v1
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v1, v2, v1
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v6, v5
v_fmac_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v5
v_div_fmas_f32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v1, v3, v2, v1
v_ceil_f32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 0, v6
s_cbranch_vccnz .LBB2_6
s_clause 0x1
s_load_b32 s4, s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v7, s4
s_mov_b32 s4, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_3
.p2align 6
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b64 v[1:2], 3, v[2:3]
v_cvt_f32_i32_e32 v5, s4
s_add_i32 s4, s4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ngt_f32_e32 vcc_lo, v6, v5
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v7
global_store_b32 v[1:2], v4, off
s_cbranch_vccnz .LBB2_6
.LBB2_3:
v_mov_b32_e32 v2, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s3, v2
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB2_2
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v1
v_lshlrev_b64 v[8:9], 3, v[0:1]
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v9, vcc_lo
s_clause 0x1
global_load_b32 v1, v[10:11], off
global_load_b32 v8, v[4:5], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v1, v1, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, v8, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_2
global_store_b32 v[4:5], v1, off
s_branch .LBB2_2
.LBB2_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5queuePSt4pairIfiEji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z5queuePSt4pairIfiEji, .Lfunc_end2-_Z5queuePSt4pairIfiEji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializePSt4pairIfiEj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10initializePSt4pairIfiEj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8add_timePSt4pairIfiEjPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8add_timePSt4pairIfiEjPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5queuePSt4pairIfiEji
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z5queuePSt4pairIfiEji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void vecAdd(unsigned int *A_d, unsigned int *B_d, unsigned int *C_d, int WORK_SIZE) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate vecADD kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < WORK_SIZE)
C_d[id] = A_d[id] + B_d[id];
} | code for sm_80
Function : _Z6vecAddPjS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void vecAdd(unsigned int *A_d, unsigned int *B_d, unsigned int *C_d, int WORK_SIZE) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate vecADD kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < WORK_SIZE)
C_d[id] = A_d[id] + B_d[id];
} | .file "tmpxft_000b256c_00000000-6_vecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPjS_S_iPjS_S_i
.type _Z30__device_stub__Z6vecAddPjS_S_iPjS_S_i, @function
_Z30__device_stub__Z6vecAddPjS_S_iPjS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPjS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6vecAddPjS_S_iPjS_S_i, .-_Z30__device_stub__Z6vecAddPjS_S_iPjS_S_i
.globl _Z6vecAddPjS_S_i
.type _Z6vecAddPjS_S_i, @function
_Z6vecAddPjS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPjS_S_iPjS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecAddPjS_S_i, .-_Z6vecAddPjS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecAddPjS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPjS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void vecAdd(unsigned int *A_d, unsigned int *B_d, unsigned int *C_d, int WORK_SIZE) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate vecADD kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < WORK_SIZE)
C_d[id] = A_d[id] + B_d[id];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecAdd(unsigned int *A_d, unsigned int *B_d, unsigned int *C_d, int WORK_SIZE) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate vecADD kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < WORK_SIZE)
C_d[id] = A_d[id] + B_d[id];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecAdd(unsigned int *A_d, unsigned int *B_d, unsigned int *C_d, int WORK_SIZE) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate vecADD kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < WORK_SIZE)
C_d[id] = A_d[id] + B_d[id];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPjS_S_i
.globl _Z6vecAddPjS_S_i
.p2align 8
.type _Z6vecAddPjS_S_i,@function
_Z6vecAddPjS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPjS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPjS_S_i, .Lfunc_end0-_Z6vecAddPjS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPjS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPjS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecAdd(unsigned int *A_d, unsigned int *B_d, unsigned int *C_d, int WORK_SIZE) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate vecADD kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// Get our global thread ID
int id = blockIdx.x*blockDim.x+threadIdx.x;
// Make sure we do not go out of bounds
if (id < WORK_SIZE)
C_d[id] = A_d[id] + B_d[id];
} | .text
.file "vecAdd.hip"
.globl _Z21__device_stub__vecAddPjS_S_i # -- Begin function _Z21__device_stub__vecAddPjS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPjS_S_i,@function
_Z21__device_stub__vecAddPjS_S_i: # @_Z21__device_stub__vecAddPjS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPjS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPjS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPjS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPjS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPjS_S_i,@object # @_Z6vecAddPjS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPjS_S_i
.p2align 3, 0x0
_Z6vecAddPjS_S_i:
.quad _Z21__device_stub__vecAddPjS_S_i
.size _Z6vecAddPjS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecAddPjS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPjS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPjS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPjS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPjS_S_i
.globl _Z6vecAddPjS_S_i
.p2align 8
.type _Z6vecAddPjS_S_i,@function
_Z6vecAddPjS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPjS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPjS_S_i, .Lfunc_end0-_Z6vecAddPjS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPjS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPjS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b256c_00000000-6_vecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPjS_S_iPjS_S_i
.type _Z30__device_stub__Z6vecAddPjS_S_iPjS_S_i, @function
_Z30__device_stub__Z6vecAddPjS_S_iPjS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPjS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6vecAddPjS_S_iPjS_S_i, .-_Z30__device_stub__Z6vecAddPjS_S_iPjS_S_i
.globl _Z6vecAddPjS_S_i
.type _Z6vecAddPjS_S_i, @function
_Z6vecAddPjS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPjS_S_iPjS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecAddPjS_S_i, .-_Z6vecAddPjS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecAddPjS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPjS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecAdd.hip"
.globl _Z21__device_stub__vecAddPjS_S_i # -- Begin function _Z21__device_stub__vecAddPjS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPjS_S_i,@function
_Z21__device_stub__vecAddPjS_S_i: # @_Z21__device_stub__vecAddPjS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPjS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPjS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPjS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPjS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPjS_S_i,@object # @_Z6vecAddPjS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPjS_S_i
.p2align 3, 0x0
_Z6vecAddPjS_S_i:
.quad _Z21__device_stub__vecAddPjS_S_i
.size _Z6vecAddPjS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecAddPjS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPjS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPjS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright 2014. All rights reserved.
*
* CUDA Kernel Device code
* Rowan Hughes
*/
#define SDATA(index) sdata[index]
#define SMEM(X, Y) sdata[(Y)*bw+(X)]
extern "C" __global__ void
copyReductionKernel(float4* g_idata, float* g_odata, int chanels, int sizeData, int offset)
{
// shared memory
// the size is determined by the host application
extern __shared__ float sdata[];
const int dId = (blockDim.x * blockIdx.x + threadIdx.x);
if(dId >= sizeData) return;
const unsigned int tIdC = chanels * threadIdx.x;
const int pixelIdIn = offset + dId;
const int tIdMax = sizeData - blockDim.x*blockIdx.x;
// load data from global to shared memory
float4 ldata = g_idata[pixelIdIn]; //[thetaDot1, thetaDot2, ttc, first]
if(ldata.z >= 0 && ldata.x != 0 )
{
// it is a pixel belonging to an object
SDATA(tIdC ) = ldata.x; // thetaDot1
SDATA(tIdC+1) = ldata.y; // thetaDot2
SDATA(tIdC+2) = ldata.z; // ttc
SDATA(tIdC+3) = 1; // go first if taking thetaDot1
SDATA(tIdC+4) = 1; // go first if taking thetaDot2
if(ldata.z < 3 && ldata.w <= 0) // ttc < 3s and giving a way
{
if(abs(ldata.x) < abs(ldata.y))
{
SDATA(tIdC+3) = -1; // go second if taking thetaDot1 => slow down
}
else
{
SDATA(tIdC+4) = -1; // go second if taking thetaDot2 => slow down
}
}
}
else
{
// it is a background pixel
SDATA(tIdC+2) = -1;
}
__syncthreads();
// perform reduction
for (unsigned int i=blockDim.x*0.5; i>0; i>>=1)
{
if(threadIdx.x < i && (threadIdx.x + i < tIdMax))
{
int ic = chanels*i+tIdC;
if(SDATA(ic+2) >= 0) // if ttc2 >= 0
{
if(SDATA(tIdC+2) >= 0) // if ttc1 >= 0
{
SDATA(tIdC ) = min(SDATA(tIdC ), SDATA(ic ));
SDATA(tIdC+1) = max(SDATA(tIdC+1), SDATA(ic+1));
SDATA(tIdC+2) = min(SDATA(tIdC+2), SDATA(ic+2));
SDATA(tIdC+3) = min(SDATA(tIdC+3), SDATA(ic+3));
SDATA(tIdC+4) = min(SDATA(tIdC+4), SDATA(ic+4));
}
else
{
SDATA(tIdC ) = SDATA(ic);
SDATA(tIdC+1) = SDATA(ic+1);
SDATA(tIdC+2) = SDATA(ic+2);
SDATA(tIdC+3) = SDATA(ic+3);
SDATA(tIdC+4) = SDATA(ic+4);
}
}
}
__syncthreads();
}
// write data to global memory
if(threadIdx.x==0)
{
int bc = chanels*blockIdx.x;
g_odata[bc] = SDATA(0);
g_odata[bc+1] = SDATA(1);
g_odata[bc+2] = SDATA(2);
g_odata[bc+3] = SDATA(3);
g_odata[bc+4] = SDATA(4);
}
} | code for sm_80
Function : copyReductionKernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R0, c[0x0][0x0], R3 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R4, R2, c[0x0][0x178], RZ ; /* 0x00005e0002047a10 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0205 */
/*00a0*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1d00 */
/*00b0*/ I2F.F64.U32 R8, c[0x0][0x0] ; /* 0x0000000000087b12 */
/* 0x000e220000201800 */
/*00c0*/ BSSY B0, 0x230 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*00d0*/ DMUL R10, R8, 0.5 ; /* 0x3fe00000080a7828 */
/* 0x0010640000000000 */
/*00e0*/ IMAD R9, R3, c[0x0][0x170], RZ ; /* 0x00005c0003097a24 */
/* 0x001fd000078e02ff */
/*00f0*/ F2I.U32.F64.TRUNC R10, R10 ; /* 0x0000000a000a7311 */
/* 0x002062000030d000 */
/*0100*/ FSETP.NEU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x004fc80003f0d000 */
/*0110*/ FSETP.GE.AND P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720b */
/* 0x000fda0000706000 */
/*0120*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, -0x40800000 ; /* 0xbf800000ff028424 */
/* 0x000fca00078e00ff */
/*0130*/ @!P0 STS [R9.X4+0x8], R2 ; /* 0x0000080209008388 */
/* 0x0001e20000004800 */
/*0140*/ @!P0 BRA 0x220 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff027424 */
/* 0x003fe200078e00ff */
/*0160*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0001e20000004800 */
/*0170*/ FSETP.GTU.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fc60003f0c000 */
/*0180*/ STS [R9.X4+0xc], R2 ; /* 0x00000c0209007388 */
/* 0x0001e20000004800 */
/*0190*/ FSETP.GEU.OR P0, PT, R6, 3, P0 ; /* 0x404000000600780b */
/* 0x000fc6000070e400 */
/*01a0*/ STS [R9.X4+0x10], R2 ; /* 0x0000100209007388 */
/* 0x0001e80000004800 */
/*01b0*/ STS [R9.X4+0x4], R5 ; /* 0x0000040509007388 */
/* 0x0001e80000004800 */
/*01c0*/ STS [R9.X4+0x8], R6 ; /* 0x0000080609007388 */
/* 0x0001e40000004800 */
/*01d0*/ @P0 BRA 0x220 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*01e0*/ FSETP.GEU.AND P0, PT, |R4|, |R5|, PT ; /* 0x400000050400720b */
/* 0x000fe20003f0e200 */
/*01f0*/ IMAD.MOV.U32 R2, RZ, RZ, -0x40800000 ; /* 0xbf800000ff027424 */
/* 0x001fd800078e00ff */
/*0200*/ @P0 STS [R9.X4+0x10], R2 ; /* 0x0000100209000388 */
/* 0x0001e80000004800 */
/*0210*/ @!P0 STS [R9.X4+0xc], R2 ; /* 0x00000c0209008388 */
/* 0x0001e40000004800 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0250*/ IMAD.SHL.U32 R2, R9, 0x4, RZ ; /* 0x0000000409027824 */
/* 0x001fd800078e00ff */
/*0260*/ @!P0 BRA 0x5b0 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.MOV R5, RZ, RZ, -R0 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0a00 */
/*0280*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000a */
/*02a0*/ IMAD R5, R5, R6, c[0x0][0x174] ; /* 0x00005d0005057624 */
/* 0x000fe400078e0206 */
/*02b0*/ IMAD.IADD R6, R3, 0x1, R4 ; /* 0x0000000103067824 */
/* 0x000fe200078e0204 */
/*02c0*/ BSSY B0, 0x570 ; /* 0x000002a000007945 */
/* 0x000fe80003800000 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fc80003f06070 */
/*02e0*/ ISETP.GE.U32.OR P0, PT, R3, R4, P0 ; /* 0x000000040300720c */
/* 0x000fda0000706470 */
/*02f0*/ @P0 BRA 0x560 ; /* 0x0000026000000947 */
/* 0x001fea0003800000 */
/*0300*/ IMAD R7, R4, c[0x0][0x170], RZ ; /* 0x00005c0004077a24 */
/* 0x000fc800078e02ff */
/*0310*/ IMAD R11, R7, 0x4, R2 ; /* 0x00000004070b7824 */
/* 0x000fca00078e0202 */
/*0320*/ LDS R6, [R11+0x8] ; /* 0x000008000b067984 */
/* 0x000e240000000800 */
/*0330*/ FSETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x001fda0003f06000 */
/*0340*/ @!P0 BRA 0x560 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0350*/ LDS R6, [R9.X4+0x8] ; /* 0x0000080009067984 */
/* 0x000e240000004800 */
/*0360*/ FSETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x001fda0003f06000 */
/*0370*/ @!P0 BRA 0x4c0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0380*/ LDS R7, [R9.X4] ; /* 0x0000000009077984 */
/* 0x000fe80000004800 */
/*0390*/ LDS R8, [R11] ; /* 0x000000000b087984 */
/* 0x000e280000000800 */
/*03a0*/ LDS R10, [R9.X4+0x4] ; /* 0x00000400090a7984 */
/* 0x000fe80000004800 */
/*03b0*/ LDS R12, [R9.X4+0xc] ; /* 0x00000c00090c7984 */
/* 0x000fe80000004800 */
/*03c0*/ LDS R14, [R9.X4+0x10] ; /* 0x00001000090e7984 */
/* 0x000fe20000004800 */
/*03d0*/ FMNMX R8, R7, R8, PT ; /* 0x0000000807087209 */
/* 0x001fca0003800000 */
/*03e0*/ STS [R9.X4], R8 ; /* 0x0000000809007388 */
/* 0x000fe80000004800 */
/*03f0*/ LDS R7, [R11+0x4] ; /* 0x000004000b077984 */
/* 0x000e240000000800 */
/*0400*/ FMNMX R10, R7, R10, !PT ; /* 0x0000000a070a7209 */
/* 0x001fca0007800000 */
/*0410*/ STS [R9.X4+0x4], R10 ; /* 0x0000040a09007388 */
/* 0x000fe80000004800 */
/*0420*/ LDS R7, [R11+0x8] ; /* 0x000008000b077984 */
/* 0x000e240000000800 */
/*0430*/ FMNMX R6, R6, R7, PT ; /* 0x0000000706067209 */
/* 0x001fca0003800000 */
/*0440*/ STS [R9.X4+0x8], R6 ; /* 0x0000080609007388 */
/* 0x000fe80000004800 */
/*0450*/ LDS R7, [R11+0xc] ; /* 0x00000c000b077984 */
/* 0x000e240000000800 */
/*0460*/ FMNMX R12, R7, R12, PT ; /* 0x0000000c070c7209 */
/* 0x001fca0003800000 */
/*0470*/ STS [R9.X4+0xc], R12 ; /* 0x00000c0c09007388 */
/* 0x000fe80000004800 */
/*0480*/ LDS R7, [R11+0x10] ; /* 0x000010000b077984 */
/* 0x000e240000000800 */
/*0490*/ FMNMX R14, R7, R14, PT ; /* 0x0000000e070e7209 */
/* 0x001fca0003800000 */
/*04a0*/ STS [R9.X4+0x10], R14 ; /* 0x0000100e09007388 */
/* 0x0001e20000004800 */
/*04b0*/ BRA 0x560 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*04c0*/ LDS R6, [R11] ; /* 0x000000000b067984 */
/* 0x000e280000000800 */
/*04d0*/ STS [R9.X4], R6 ; /* 0x0000000609007388 */
/* 0x001fe80000004800 */
/*04e0*/ LDS R8, [R11+0x4] ; /* 0x000004000b087984 */
/* 0x000e280000000800 */
/*04f0*/ STS [R9.X4+0x4], R8 ; /* 0x0000040809007388 */
/* 0x001fe80000004800 */
/*0500*/ LDS R10, [R11+0x8] ; /* 0x000008000b0a7984 */
/* 0x000e280000000800 */
/*0510*/ STS [R9.X4+0x8], R10 ; /* 0x0000080a09007388 */
/* 0x001fe80000004800 */
/*0520*/ LDS R12, [R11+0xc] ; /* 0x00000c000b0c7984 */
/* 0x000e280000000800 */
/*0530*/ STS [R9.X4+0xc], R12 ; /* 0x00000c0c09007388 */
/* 0x001fe80000004800 */
/*0540*/ LDS R14, [R11+0x10] ; /* 0x000010000b0e7984 */
/* 0x000e280000000800 */
/*0550*/ STS [R9.X4+0x10], R14 ; /* 0x0000100e09007388 */
/* 0x0011e40000004800 */
/*0560*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0570*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fe20000011604 */
/*0580*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0590*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*05a0*/ @P0 BRA 0x2b0 ; /* 0xfffffd0000000947 */
/* 0x000fea000383ffff */
/*05b0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*05c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05d0*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e620000000c00 */
/*05e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*05f0*/ IMAD R2, R0, c[0x0][0x170], RZ ; /* 0x00005c0000027a24 */
/* 0x000fe200078e02ff */
/*0600*/ LDS R9, [0x10] ; /* 0x00001000ff097984 */
/* 0x001e260000000800 */
/*0610*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0620*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x002fe8000c101904 */
/*0630*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*0640*/ STG.E [R2.64+0x8], R6 ; /* 0x0000080602007986 */
/* 0x000fe8000c101904 */
/*0650*/ STG.E [R2.64+0xc], R7 ; /* 0x00000c0702007986 */
/* 0x000fe8000c101904 */
/*0660*/ STG.E [R2.64+0x10], R9 ; /* 0x0000100902007986 */
/* 0x001fe2000c101904 */
/*0670*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0680*/ BRA 0x680; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 2014. All rights reserved.
*
* CUDA Kernel Device code
* Rowan Hughes
*/
#define SDATA(index) sdata[index]
#define SMEM(X, Y) sdata[(Y)*bw+(X)]
extern "C" __global__ void
copyReductionKernel(float4* g_idata, float* g_odata, int chanels, int sizeData, int offset)
{
// shared memory
// the size is determined by the host application
extern __shared__ float sdata[];
const int dId = (blockDim.x * blockIdx.x + threadIdx.x);
if(dId >= sizeData) return;
const unsigned int tIdC = chanels * threadIdx.x;
const int pixelIdIn = offset + dId;
const int tIdMax = sizeData - blockDim.x*blockIdx.x;
// load data from global to shared memory
float4 ldata = g_idata[pixelIdIn]; //[thetaDot1, thetaDot2, ttc, first]
if(ldata.z >= 0 && ldata.x != 0 )
{
// it is a pixel belonging to an object
SDATA(tIdC ) = ldata.x; // thetaDot1
SDATA(tIdC+1) = ldata.y; // thetaDot2
SDATA(tIdC+2) = ldata.z; // ttc
SDATA(tIdC+3) = 1; // go first if taking thetaDot1
SDATA(tIdC+4) = 1; // go first if taking thetaDot2
if(ldata.z < 3 && ldata.w <= 0) // ttc < 3s and giving a way
{
if(abs(ldata.x) < abs(ldata.y))
{
SDATA(tIdC+3) = -1; // go second if taking thetaDot1 => slow down
}
else
{
SDATA(tIdC+4) = -1; // go second if taking thetaDot2 => slow down
}
}
}
else
{
// it is a background pixel
SDATA(tIdC+2) = -1;
}
__syncthreads();
// perform reduction
for (unsigned int i=blockDim.x*0.5; i>0; i>>=1)
{
if(threadIdx.x < i && (threadIdx.x + i < tIdMax))
{
int ic = chanels*i+tIdC;
if(SDATA(ic+2) >= 0) // if ttc2 >= 0
{
if(SDATA(tIdC+2) >= 0) // if ttc1 >= 0
{
SDATA(tIdC ) = min(SDATA(tIdC ), SDATA(ic ));
SDATA(tIdC+1) = max(SDATA(tIdC+1), SDATA(ic+1));
SDATA(tIdC+2) = min(SDATA(tIdC+2), SDATA(ic+2));
SDATA(tIdC+3) = min(SDATA(tIdC+3), SDATA(ic+3));
SDATA(tIdC+4) = min(SDATA(tIdC+4), SDATA(ic+4));
}
else
{
SDATA(tIdC ) = SDATA(ic);
SDATA(tIdC+1) = SDATA(ic+1);
SDATA(tIdC+2) = SDATA(ic+2);
SDATA(tIdC+3) = SDATA(ic+3);
SDATA(tIdC+4) = SDATA(ic+4);
}
}
}
__syncthreads();
}
// write data to global memory
if(threadIdx.x==0)
{
int bc = chanels*blockIdx.x;
g_odata[bc] = SDATA(0);
g_odata[bc+1] = SDATA(1);
g_odata[bc+2] = SDATA(2);
g_odata[bc+3] = SDATA(3);
g_odata[bc+4] = SDATA(4);
}
} | .file "tmpxft_0018e927_00000000-6_copyReductionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z19copyReductionKernelP6float4PfiiiP6float4Pfiii
.type _Z50__device_stub__Z19copyReductionKernelP6float4PfiiiP6float4Pfiii, @function
_Z50__device_stub__Z19copyReductionKernelP6float4PfiiiP6float4Pfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq copyReductionKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z19copyReductionKernelP6float4PfiiiP6float4Pfiii, .-_Z50__device_stub__Z19copyReductionKernelP6float4PfiiiP6float4Pfiii
.globl copyReductionKernel
.type copyReductionKernel, @function
copyReductionKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z19copyReductionKernelP6float4PfiiiP6float4Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size copyReductionKernel, .-copyReductionKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "copyReductionKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq copyReductionKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 2014. All rights reserved.
*
* CUDA Kernel Device code
* Rowan Hughes
*/
#define SDATA(index) sdata[index]
#define SMEM(X, Y) sdata[(Y)*bw+(X)]
extern "C" __global__ void
copyReductionKernel(float4* g_idata, float* g_odata, int chanels, int sizeData, int offset)
{
// shared memory
// the size is determined by the host application
extern __shared__ float sdata[];
const int dId = (blockDim.x * blockIdx.x + threadIdx.x);
if(dId >= sizeData) return;
const unsigned int tIdC = chanels * threadIdx.x;
const int pixelIdIn = offset + dId;
const int tIdMax = sizeData - blockDim.x*blockIdx.x;
// load data from global to shared memory
float4 ldata = g_idata[pixelIdIn]; //[thetaDot1, thetaDot2, ttc, first]
if(ldata.z >= 0 && ldata.x != 0 )
{
// it is a pixel belonging to an object
SDATA(tIdC ) = ldata.x; // thetaDot1
SDATA(tIdC+1) = ldata.y; // thetaDot2
SDATA(tIdC+2) = ldata.z; // ttc
SDATA(tIdC+3) = 1; // go first if taking thetaDot1
SDATA(tIdC+4) = 1; // go first if taking thetaDot2
if(ldata.z < 3 && ldata.w <= 0) // ttc < 3s and giving a way
{
if(abs(ldata.x) < abs(ldata.y))
{
SDATA(tIdC+3) = -1; // go second if taking thetaDot1 => slow down
}
else
{
SDATA(tIdC+4) = -1; // go second if taking thetaDot2 => slow down
}
}
}
else
{
// it is a background pixel
SDATA(tIdC+2) = -1;
}
__syncthreads();
// perform reduction
for (unsigned int i=blockDim.x*0.5; i>0; i>>=1)
{
if(threadIdx.x < i && (threadIdx.x + i < tIdMax))
{
int ic = chanels*i+tIdC;
if(SDATA(ic+2) >= 0) // if ttc2 >= 0
{
if(SDATA(tIdC+2) >= 0) // if ttc1 >= 0
{
SDATA(tIdC ) = min(SDATA(tIdC ), SDATA(ic ));
SDATA(tIdC+1) = max(SDATA(tIdC+1), SDATA(ic+1));
SDATA(tIdC+2) = min(SDATA(tIdC+2), SDATA(ic+2));
SDATA(tIdC+3) = min(SDATA(tIdC+3), SDATA(ic+3));
SDATA(tIdC+4) = min(SDATA(tIdC+4), SDATA(ic+4));
}
else
{
SDATA(tIdC ) = SDATA(ic);
SDATA(tIdC+1) = SDATA(ic+1);
SDATA(tIdC+2) = SDATA(ic+2);
SDATA(tIdC+3) = SDATA(ic+3);
SDATA(tIdC+4) = SDATA(ic+4);
}
}
}
__syncthreads();
}
// write data to global memory
if(threadIdx.x==0)
{
int bc = chanels*blockIdx.x;
g_odata[bc] = SDATA(0);
g_odata[bc+1] = SDATA(1);
g_odata[bc+2] = SDATA(2);
g_odata[bc+3] = SDATA(3);
g_odata[bc+4] = SDATA(4);
}
} | #include <hip/hip_runtime.h>
/*
* Copyright 2014. All rights reserved.
*
* CUDA Kernel Device code
* Rowan Hughes
*/
#define SDATA(index) sdata[index]
#define SMEM(X, Y) sdata[(Y)*bw+(X)]
extern "C" __global__ void
copyReductionKernel(float4* g_idata, float* g_odata, int chanels, int sizeData, int offset)
{
// shared memory
// the size is determined by the host application
extern __shared__ float sdata[];
const int dId = (blockDim.x * blockIdx.x + threadIdx.x);
if(dId >= sizeData) return;
const unsigned int tIdC = chanels * threadIdx.x;
const int pixelIdIn = offset + dId;
const int tIdMax = sizeData - blockDim.x*blockIdx.x;
// load data from global to shared memory
float4 ldata = g_idata[pixelIdIn]; //[thetaDot1, thetaDot2, ttc, first]
if(ldata.z >= 0 && ldata.x != 0 )
{
// it is a pixel belonging to an object
SDATA(tIdC ) = ldata.x; // thetaDot1
SDATA(tIdC+1) = ldata.y; // thetaDot2
SDATA(tIdC+2) = ldata.z; // ttc
SDATA(tIdC+3) = 1; // go first if taking thetaDot1
SDATA(tIdC+4) = 1; // go first if taking thetaDot2
if(ldata.z < 3 && ldata.w <= 0) // ttc < 3s and giving a way
{
if(abs(ldata.x) < abs(ldata.y))
{
SDATA(tIdC+3) = -1; // go second if taking thetaDot1 => slow down
}
else
{
SDATA(tIdC+4) = -1; // go second if taking thetaDot2 => slow down
}
}
}
else
{
// it is a background pixel
SDATA(tIdC+2) = -1;
}
__syncthreads();
// perform reduction
for (unsigned int i=blockDim.x*0.5; i>0; i>>=1)
{
if(threadIdx.x < i && (threadIdx.x + i < tIdMax))
{
int ic = chanels*i+tIdC;
if(SDATA(ic+2) >= 0) // if ttc2 >= 0
{
if(SDATA(tIdC+2) >= 0) // if ttc1 >= 0
{
SDATA(tIdC ) = min(SDATA(tIdC ), SDATA(ic ));
SDATA(tIdC+1) = max(SDATA(tIdC+1), SDATA(ic+1));
SDATA(tIdC+2) = min(SDATA(tIdC+2), SDATA(ic+2));
SDATA(tIdC+3) = min(SDATA(tIdC+3), SDATA(ic+3));
SDATA(tIdC+4) = min(SDATA(tIdC+4), SDATA(ic+4));
}
else
{
SDATA(tIdC ) = SDATA(ic);
SDATA(tIdC+1) = SDATA(ic+1);
SDATA(tIdC+2) = SDATA(ic+2);
SDATA(tIdC+3) = SDATA(ic+3);
SDATA(tIdC+4) = SDATA(ic+4);
}
}
}
__syncthreads();
}
// write data to global memory
if(threadIdx.x==0)
{
int bc = chanels*blockIdx.x;
g_odata[bc] = SDATA(0);
g_odata[bc+1] = SDATA(1);
g_odata[bc+2] = SDATA(2);
g_odata[bc+3] = SDATA(3);
g_odata[bc+4] = SDATA(4);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* Copyright 2014. All rights reserved.
*
* CUDA Kernel Device code
* Rowan Hughes
*/
#define SDATA(index) sdata[index]
#define SMEM(X, Y) sdata[(Y)*bw+(X)]
extern "C" __global__ void
copyReductionKernel(float4* g_idata, float* g_odata, int chanels, int sizeData, int offset)
{
// shared memory
// the size is determined by the host application
extern __shared__ float sdata[];
const int dId = (blockDim.x * blockIdx.x + threadIdx.x);
if(dId >= sizeData) return;
const unsigned int tIdC = chanels * threadIdx.x;
const int pixelIdIn = offset + dId;
const int tIdMax = sizeData - blockDim.x*blockIdx.x;
// load data from global to shared memory
float4 ldata = g_idata[pixelIdIn]; //[thetaDot1, thetaDot2, ttc, first]
if(ldata.z >= 0 && ldata.x != 0 )
{
// it is a pixel belonging to an object
SDATA(tIdC ) = ldata.x; // thetaDot1
SDATA(tIdC+1) = ldata.y; // thetaDot2
SDATA(tIdC+2) = ldata.z; // ttc
SDATA(tIdC+3) = 1; // go first if taking thetaDot1
SDATA(tIdC+4) = 1; // go first if taking thetaDot2
if(ldata.z < 3 && ldata.w <= 0) // ttc < 3s and giving a way
{
if(abs(ldata.x) < abs(ldata.y))
{
SDATA(tIdC+3) = -1; // go second if taking thetaDot1 => slow down
}
else
{
SDATA(tIdC+4) = -1; // go second if taking thetaDot2 => slow down
}
}
}
else
{
// it is a background pixel
SDATA(tIdC+2) = -1;
}
__syncthreads();
// perform reduction
for (unsigned int i=blockDim.x*0.5; i>0; i>>=1)
{
if(threadIdx.x < i && (threadIdx.x + i < tIdMax))
{
int ic = chanels*i+tIdC;
if(SDATA(ic+2) >= 0) // if ttc2 >= 0
{
if(SDATA(tIdC+2) >= 0) // if ttc1 >= 0
{
SDATA(tIdC ) = min(SDATA(tIdC ), SDATA(ic ));
SDATA(tIdC+1) = max(SDATA(tIdC+1), SDATA(ic+1));
SDATA(tIdC+2) = min(SDATA(tIdC+2), SDATA(ic+2));
SDATA(tIdC+3) = min(SDATA(tIdC+3), SDATA(ic+3));
SDATA(tIdC+4) = min(SDATA(tIdC+4), SDATA(ic+4));
}
else
{
SDATA(tIdC ) = SDATA(ic);
SDATA(tIdC+1) = SDATA(ic+1);
SDATA(tIdC+2) = SDATA(ic+2);
SDATA(tIdC+3) = SDATA(ic+3);
SDATA(tIdC+4) = SDATA(ic+4);
}
}
}
__syncthreads();
}
// write data to global memory
if(threadIdx.x==0)
{
int bc = chanels*blockIdx.x;
g_odata[bc] = SDATA(0);
g_odata[bc+1] = SDATA(1);
g_odata[bc+2] = SDATA(2);
g_odata[bc+3] = SDATA(3);
g_odata[bc+4] = SDATA(4);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected copyReductionKernel
.globl copyReductionKernel
.p2align 8
.type copyReductionKernel,@function
copyReductionKernel:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s5, s15, s2
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v1, s5, v0
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_21
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s2, v1
v_mul_lo_u32 v3, v0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
s_clause 0x1
global_load_b32 v6, v[1:2], off offset:8
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(1)
v_cmp_nle_f32_e32 vcc_lo, 0, v6
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e64 s2, 0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s8, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v3
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v5, v1, 0, 8
s_and_not1_saveexec_b32 s8, s2
s_cbranch_execz .LBB0_7
s_clause 0x1
global_load_b32 v5, v[1:2], off offset:12
global_load_b32 v1, v[1:2], off offset:4
v_cmp_gt_f32_e32 vcc_lo, 0x40400000, v6
v_lshl_add_u32 v2, v3, 2, 0
v_mov_b32_e32 v7, 1.0
s_mov_b32 s9, s7
s_waitcnt vmcnt(1)
v_cmp_ge_f32_e64 s2, 0, v5
v_mov_b32_e32 v5, 1.0
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v2, v4, v1 offset1:1
ds_store_b32 v2, v6 offset:8
ds_store_2addr_b32 v2, v5, v7 offset0:3 offset1:4
s_and_b32 s10, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s10
v_add_nc_u32_e32 v5, 12, v2
v_add_nc_u32_e32 v2, 16, v2
v_cmp_lt_f32_e64 vcc_lo, |v4|, |v1|
s_or_b32 s9, s7, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v5, v2, v5, vcc_lo
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s7, exec_lo
s_and_b32 s7, s9, exec_lo
s_or_b32 s7, s2, s7
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s2, s7
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v1, -1.0
ds_store_b32 v5, v1
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s2
s_and_b32 s2, 0xffff, s6
s_waitcnt lgkmcnt(0)
v_cvt_f64_u32_e32 v[1:2], s2
s_barrier
buffer_gl0_inv
v_mul_f64 v[1:2], v[1:2], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f64_e32 v1, v[1:2]
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_cbranch_vccnz .LBB0_19
v_lshl_add_u32 v2, v3, 2, 0
s_sub_i32 s2, s4, s5
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v3, 8, v2
v_add_nc_u32_e32 v4, 4, v2
v_add_nc_u32_e32 v5, 12, v2
v_add_nc_u32_e32 v6, 16, v2
s_branch .LBB0_12
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s4
v_lshrrev_b32_e32 v7, 1, v1
v_cmp_gt_u32_e32 vcc_lo, 2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v1, v7
s_cbranch_vccnz .LBB0_19
.LBB0_12:
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u32_e64 v0, v1
s_cbranch_execz .LBB0_11
v_add_nc_u32_e32 v7, v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v7
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_11
v_mul_lo_u32 v7, v7, s3
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v7, v7, 2, 0
ds_load_b32 v8, v7 offset:8
s_waitcnt lgkmcnt(0)
v_cmp_le_f32_e32 vcc_lo, 0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_11
ds_load_b32 v9, v3
v_add_nc_u32_e32 v8, 8, v7
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_le_f32_e32 0, v9
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_17
ds_load_b32 v10, v7
ds_load_b32 v11, v2
ds_load_b32 v12, v6
s_waitcnt lgkmcnt(2)
v_dual_max_f32 v9, v9, v9 :: v_dual_max_f32 v10, v10, v10
s_waitcnt lgkmcnt(1)
v_max_f32_e32 v11, v11, v11
s_delay_alu instid0(VALU_DEP_1)
v_min_f32_e32 v10, v11, v10
ds_store_b32 v2, v10
ds_load_b32 v10, v4
ds_load_b32 v11, v7 offset:4
ds_load_b32 v13, v5
s_waitcnt lgkmcnt(1)
v_dual_max_f32 v10, v10, v10 :: v_dual_max_f32 v11, v11, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_max_f32_e32 v10, v10, v11
ds_store_b32 v4, v10
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(0)
v_max_f32_e32 v8, v8, v8
v_min_f32_e32 v8, v9, v8
v_max_f32_e32 v9, v13, v13
ds_store_b32 v3, v8
ds_load_b32 v8, v7 offset:12
s_waitcnt lgkmcnt(0)
v_max_f32_e32 v8, v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_min_f32_e32 v8, v9, v8
ds_store_b32 v5, v8
ds_load_b32 v7, v7 offset:16
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v8, v12, v12 :: v_dual_max_f32 v7, v7, v7
v_min_f32_e32 v7, v8, v7
ds_store_b32 v6, v7
.LBB0_17:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_11
ds_load_b32 v9, v7
s_waitcnt lgkmcnt(0)
ds_store_b32 v2, v9
ds_load_b32 v9, v7 offset:4
s_waitcnt lgkmcnt(0)
ds_store_b32 v4, v9
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(0)
ds_store_b32 v3, v8
ds_load_b32 v8, v7 offset:12
s_waitcnt lgkmcnt(0)
ds_store_b32 v5, v8
ds_load_b32 v7, v7 offset:16
s_waitcnt lgkmcnt(0)
ds_store_b32 v6, v7
s_branch .LBB0_11
.LBB0_19:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_21
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mul_i32 s2, s15, s3
ds_load_b32 v4, v0
ds_load_2addr_b32 v[2:3], v0 offset0:3 offset1:4
ds_load_2addr_b32 v[0:1], v0 offset0:1 offset1:2
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_clause 0x1
global_store_b32 v5, v4, s[0:1]
global_store_b128 v5, v[0:3], s[0:1] offset:4
.LBB0_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel copyReductionKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size copyReductionKernel, .Lfunc_end0-copyReductionKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: copyReductionKernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: copyReductionKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* Copyright 2014. All rights reserved.
*
* CUDA Kernel Device code
* Rowan Hughes
*/
#define SDATA(index) sdata[index]
#define SMEM(X, Y) sdata[(Y)*bw+(X)]
extern "C" __global__ void
copyReductionKernel(float4* g_idata, float* g_odata, int chanels, int sizeData, int offset)
{
// shared memory
// the size is determined by the host application
extern __shared__ float sdata[];
const int dId = (blockDim.x * blockIdx.x + threadIdx.x);
if(dId >= sizeData) return;
const unsigned int tIdC = chanels * threadIdx.x;
const int pixelIdIn = offset + dId;
const int tIdMax = sizeData - blockDim.x*blockIdx.x;
// load data from global to shared memory
float4 ldata = g_idata[pixelIdIn]; //[thetaDot1, thetaDot2, ttc, first]
if(ldata.z >= 0 && ldata.x != 0 )
{
// it is a pixel belonging to an object
SDATA(tIdC ) = ldata.x; // thetaDot1
SDATA(tIdC+1) = ldata.y; // thetaDot2
SDATA(tIdC+2) = ldata.z; // ttc
SDATA(tIdC+3) = 1; // go first if taking thetaDot1
SDATA(tIdC+4) = 1; // go first if taking thetaDot2
if(ldata.z < 3 && ldata.w <= 0) // ttc < 3s and giving a way
{
if(abs(ldata.x) < abs(ldata.y))
{
SDATA(tIdC+3) = -1; // go second if taking thetaDot1 => slow down
}
else
{
SDATA(tIdC+4) = -1; // go second if taking thetaDot2 => slow down
}
}
}
else
{
// it is a background pixel
SDATA(tIdC+2) = -1;
}
__syncthreads();
// perform reduction
for (unsigned int i=blockDim.x*0.5; i>0; i>>=1)
{
if(threadIdx.x < i && (threadIdx.x + i < tIdMax))
{
int ic = chanels*i+tIdC;
if(SDATA(ic+2) >= 0) // if ttc2 >= 0
{
if(SDATA(tIdC+2) >= 0) // if ttc1 >= 0
{
SDATA(tIdC ) = min(SDATA(tIdC ), SDATA(ic ));
SDATA(tIdC+1) = max(SDATA(tIdC+1), SDATA(ic+1));
SDATA(tIdC+2) = min(SDATA(tIdC+2), SDATA(ic+2));
SDATA(tIdC+3) = min(SDATA(tIdC+3), SDATA(ic+3));
SDATA(tIdC+4) = min(SDATA(tIdC+4), SDATA(ic+4));
}
else
{
SDATA(tIdC ) = SDATA(ic);
SDATA(tIdC+1) = SDATA(ic+1);
SDATA(tIdC+2) = SDATA(ic+2);
SDATA(tIdC+3) = SDATA(ic+3);
SDATA(tIdC+4) = SDATA(ic+4);
}
}
}
__syncthreads();
}
// write data to global memory
if(threadIdx.x==0)
{
int bc = chanels*blockIdx.x;
g_odata[bc] = SDATA(0);
g_odata[bc+1] = SDATA(1);
g_odata[bc+2] = SDATA(2);
g_odata[bc+3] = SDATA(3);
g_odata[bc+4] = SDATA(4);
}
} | .text
.file "copyReductionKernel.hip"
.globl __device_stub__copyReductionKernel # -- Begin function __device_stub__copyReductionKernel
.p2align 4, 0x90
.type __device_stub__copyReductionKernel,@function
__device_stub__copyReductionKernel: # @__device_stub__copyReductionKernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $copyReductionKernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__copyReductionKernel, .Lfunc_end0-__device_stub__copyReductionKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $copyReductionKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type copyReductionKernel,@object # @copyReductionKernel
.section .rodata,"a",@progbits
.globl copyReductionKernel
.p2align 3, 0x0
copyReductionKernel:
.quad __device_stub__copyReductionKernel
.size copyReductionKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "copyReductionKernel"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__copyReductionKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym copyReductionKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : copyReductionKernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R0, c[0x0][0x0], R3 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R4, R2, c[0x0][0x178], RZ ; /* 0x00005e0002047a10 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0205 */
/*00a0*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1d00 */
/*00b0*/ I2F.F64.U32 R8, c[0x0][0x0] ; /* 0x0000000000087b12 */
/* 0x000e220000201800 */
/*00c0*/ BSSY B0, 0x230 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*00d0*/ DMUL R10, R8, 0.5 ; /* 0x3fe00000080a7828 */
/* 0x0010640000000000 */
/*00e0*/ IMAD R9, R3, c[0x0][0x170], RZ ; /* 0x00005c0003097a24 */
/* 0x001fd000078e02ff */
/*00f0*/ F2I.U32.F64.TRUNC R10, R10 ; /* 0x0000000a000a7311 */
/* 0x002062000030d000 */
/*0100*/ FSETP.NEU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x004fc80003f0d000 */
/*0110*/ FSETP.GE.AND P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720b */
/* 0x000fda0000706000 */
/*0120*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, -0x40800000 ; /* 0xbf800000ff028424 */
/* 0x000fca00078e00ff */
/*0130*/ @!P0 STS [R9.X4+0x8], R2 ; /* 0x0000080209008388 */
/* 0x0001e20000004800 */
/*0140*/ @!P0 BRA 0x220 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff027424 */
/* 0x003fe200078e00ff */
/*0160*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0001e20000004800 */
/*0170*/ FSETP.GTU.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fc60003f0c000 */
/*0180*/ STS [R9.X4+0xc], R2 ; /* 0x00000c0209007388 */
/* 0x0001e20000004800 */
/*0190*/ FSETP.GEU.OR P0, PT, R6, 3, P0 ; /* 0x404000000600780b */
/* 0x000fc6000070e400 */
/*01a0*/ STS [R9.X4+0x10], R2 ; /* 0x0000100209007388 */
/* 0x0001e80000004800 */
/*01b0*/ STS [R9.X4+0x4], R5 ; /* 0x0000040509007388 */
/* 0x0001e80000004800 */
/*01c0*/ STS [R9.X4+0x8], R6 ; /* 0x0000080609007388 */
/* 0x0001e40000004800 */
/*01d0*/ @P0 BRA 0x220 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*01e0*/ FSETP.GEU.AND P0, PT, |R4|, |R5|, PT ; /* 0x400000050400720b */
/* 0x000fe20003f0e200 */
/*01f0*/ IMAD.MOV.U32 R2, RZ, RZ, -0x40800000 ; /* 0xbf800000ff027424 */
/* 0x001fd800078e00ff */
/*0200*/ @P0 STS [R9.X4+0x10], R2 ; /* 0x0000100209000388 */
/* 0x0001e80000004800 */
/*0210*/ @!P0 STS [R9.X4+0xc], R2 ; /* 0x00000c0209008388 */
/* 0x0001e40000004800 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0250*/ IMAD.SHL.U32 R2, R9, 0x4, RZ ; /* 0x0000000409027824 */
/* 0x001fd800078e00ff */
/*0260*/ @!P0 BRA 0x5b0 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.MOV R5, RZ, RZ, -R0 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0a00 */
/*0280*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000a */
/*02a0*/ IMAD R5, R5, R6, c[0x0][0x174] ; /* 0x00005d0005057624 */
/* 0x000fe400078e0206 */
/*02b0*/ IMAD.IADD R6, R3, 0x1, R4 ; /* 0x0000000103067824 */
/* 0x000fe200078e0204 */
/*02c0*/ BSSY B0, 0x570 ; /* 0x000002a000007945 */
/* 0x000fe80003800000 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fc80003f06070 */
/*02e0*/ ISETP.GE.U32.OR P0, PT, R3, R4, P0 ; /* 0x000000040300720c */
/* 0x000fda0000706470 */
/*02f0*/ @P0 BRA 0x560 ; /* 0x0000026000000947 */
/* 0x001fea0003800000 */
/*0300*/ IMAD R7, R4, c[0x0][0x170], RZ ; /* 0x00005c0004077a24 */
/* 0x000fc800078e02ff */
/*0310*/ IMAD R11, R7, 0x4, R2 ; /* 0x00000004070b7824 */
/* 0x000fca00078e0202 */
/*0320*/ LDS R6, [R11+0x8] ; /* 0x000008000b067984 */
/* 0x000e240000000800 */
/*0330*/ FSETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x001fda0003f06000 */
/*0340*/ @!P0 BRA 0x560 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0350*/ LDS R6, [R9.X4+0x8] ; /* 0x0000080009067984 */
/* 0x000e240000004800 */
/*0360*/ FSETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x001fda0003f06000 */
/*0370*/ @!P0 BRA 0x4c0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0380*/ LDS R7, [R9.X4] ; /* 0x0000000009077984 */
/* 0x000fe80000004800 */
/*0390*/ LDS R8, [R11] ; /* 0x000000000b087984 */
/* 0x000e280000000800 */
/*03a0*/ LDS R10, [R9.X4+0x4] ; /* 0x00000400090a7984 */
/* 0x000fe80000004800 */
/*03b0*/ LDS R12, [R9.X4+0xc] ; /* 0x00000c00090c7984 */
/* 0x000fe80000004800 */
/*03c0*/ LDS R14, [R9.X4+0x10] ; /* 0x00001000090e7984 */
/* 0x000fe20000004800 */
/*03d0*/ FMNMX R8, R7, R8, PT ; /* 0x0000000807087209 */
/* 0x001fca0003800000 */
/*03e0*/ STS [R9.X4], R8 ; /* 0x0000000809007388 */
/* 0x000fe80000004800 */
/*03f0*/ LDS R7, [R11+0x4] ; /* 0x000004000b077984 */
/* 0x000e240000000800 */
/*0400*/ FMNMX R10, R7, R10, !PT ; /* 0x0000000a070a7209 */
/* 0x001fca0007800000 */
/*0410*/ STS [R9.X4+0x4], R10 ; /* 0x0000040a09007388 */
/* 0x000fe80000004800 */
/*0420*/ LDS R7, [R11+0x8] ; /* 0x000008000b077984 */
/* 0x000e240000000800 */
/*0430*/ FMNMX R6, R6, R7, PT ; /* 0x0000000706067209 */
/* 0x001fca0003800000 */
/*0440*/ STS [R9.X4+0x8], R6 ; /* 0x0000080609007388 */
/* 0x000fe80000004800 */
/*0450*/ LDS R7, [R11+0xc] ; /* 0x00000c000b077984 */
/* 0x000e240000000800 */
/*0460*/ FMNMX R12, R7, R12, PT ; /* 0x0000000c070c7209 */
/* 0x001fca0003800000 */
/*0470*/ STS [R9.X4+0xc], R12 ; /* 0x00000c0c09007388 */
/* 0x000fe80000004800 */
/*0480*/ LDS R7, [R11+0x10] ; /* 0x000010000b077984 */
/* 0x000e240000000800 */
/*0490*/ FMNMX R14, R7, R14, PT ; /* 0x0000000e070e7209 */
/* 0x001fca0003800000 */
/*04a0*/ STS [R9.X4+0x10], R14 ; /* 0x0000100e09007388 */
/* 0x0001e20000004800 */
/*04b0*/ BRA 0x560 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*04c0*/ LDS R6, [R11] ; /* 0x000000000b067984 */
/* 0x000e280000000800 */
/*04d0*/ STS [R9.X4], R6 ; /* 0x0000000609007388 */
/* 0x001fe80000004800 */
/*04e0*/ LDS R8, [R11+0x4] ; /* 0x000004000b087984 */
/* 0x000e280000000800 */
/*04f0*/ STS [R9.X4+0x4], R8 ; /* 0x0000040809007388 */
/* 0x001fe80000004800 */
/*0500*/ LDS R10, [R11+0x8] ; /* 0x000008000b0a7984 */
/* 0x000e280000000800 */
/*0510*/ STS [R9.X4+0x8], R10 ; /* 0x0000080a09007388 */
/* 0x001fe80000004800 */
/*0520*/ LDS R12, [R11+0xc] ; /* 0x00000c000b0c7984 */
/* 0x000e280000000800 */
/*0530*/ STS [R9.X4+0xc], R12 ; /* 0x00000c0c09007388 */
/* 0x001fe80000004800 */
/*0540*/ LDS R14, [R11+0x10] ; /* 0x000010000b0e7984 */
/* 0x000e280000000800 */
/*0550*/ STS [R9.X4+0x10], R14 ; /* 0x0000100e09007388 */
/* 0x0011e40000004800 */
/*0560*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0570*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fe20000011604 */
/*0580*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0590*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*05a0*/ @P0 BRA 0x2b0 ; /* 0xfffffd0000000947 */
/* 0x000fea000383ffff */
/*05b0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*05c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05d0*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e620000000c00 */
/*05e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*05f0*/ IMAD R2, R0, c[0x0][0x170], RZ ; /* 0x00005c0000027a24 */
/* 0x000fe200078e02ff */
/*0600*/ LDS R9, [0x10] ; /* 0x00001000ff097984 */
/* 0x001e260000000800 */
/*0610*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0620*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x002fe8000c101904 */
/*0630*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*0640*/ STG.E [R2.64+0x8], R6 ; /* 0x0000080602007986 */
/* 0x000fe8000c101904 */
/*0650*/ STG.E [R2.64+0xc], R7 ; /* 0x00000c0702007986 */
/* 0x000fe8000c101904 */
/*0660*/ STG.E [R2.64+0x10], R9 ; /* 0x0000100902007986 */
/* 0x001fe2000c101904 */
/*0670*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0680*/ BRA 0x680; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected copyReductionKernel
.globl copyReductionKernel
.p2align 8
.type copyReductionKernel,@function
copyReductionKernel:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s5, s15, s2
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v1, s5, v0
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_21
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s2, v1
v_mul_lo_u32 v3, v0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
s_clause 0x1
global_load_b32 v6, v[1:2], off offset:8
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(1)
v_cmp_nle_f32_e32 vcc_lo, 0, v6
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e64 s2, 0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s8, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s8
v_lshlrev_b32_e32 v1, 2, v3
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v5, v1, 0, 8
s_and_not1_saveexec_b32 s8, s2
s_cbranch_execz .LBB0_7
s_clause 0x1
global_load_b32 v5, v[1:2], off offset:12
global_load_b32 v1, v[1:2], off offset:4
v_cmp_gt_f32_e32 vcc_lo, 0x40400000, v6
v_lshl_add_u32 v2, v3, 2, 0
v_mov_b32_e32 v7, 1.0
s_mov_b32 s9, s7
s_waitcnt vmcnt(1)
v_cmp_ge_f32_e64 s2, 0, v5
v_mov_b32_e32 v5, 1.0
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v2, v4, v1 offset1:1
ds_store_b32 v2, v6 offset:8
ds_store_2addr_b32 v2, v5, v7 offset0:3 offset1:4
s_and_b32 s10, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s10
v_add_nc_u32_e32 v5, 12, v2
v_add_nc_u32_e32 v2, 16, v2
v_cmp_lt_f32_e64 vcc_lo, |v4|, |v1|
s_or_b32 s9, s7, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v5, v2, v5, vcc_lo
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s7, exec_lo
s_and_b32 s7, s9, exec_lo
s_or_b32 s7, s2, s7
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s2, s7
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v1, -1.0
ds_store_b32 v5, v1
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s2
s_and_b32 s2, 0xffff, s6
s_waitcnt lgkmcnt(0)
v_cvt_f64_u32_e32 v[1:2], s2
s_barrier
buffer_gl0_inv
v_mul_f64 v[1:2], v[1:2], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f64_e32 v1, v[1:2]
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_cbranch_vccnz .LBB0_19
v_lshl_add_u32 v2, v3, 2, 0
s_sub_i32 s2, s4, s5
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v3, 8, v2
v_add_nc_u32_e32 v4, 4, v2
v_add_nc_u32_e32 v5, 12, v2
v_add_nc_u32_e32 v6, 16, v2
s_branch .LBB0_12
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s4
v_lshrrev_b32_e32 v7, 1, v1
v_cmp_gt_u32_e32 vcc_lo, 2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v1, v7
s_cbranch_vccnz .LBB0_19
.LBB0_12:
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u32_e64 v0, v1
s_cbranch_execz .LBB0_11
v_add_nc_u32_e32 v7, v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v7
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_11
v_mul_lo_u32 v7, v7, s3
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v7, v7, 2, 0
ds_load_b32 v8, v7 offset:8
s_waitcnt lgkmcnt(0)
v_cmp_le_f32_e32 vcc_lo, 0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_11
ds_load_b32 v9, v3
v_add_nc_u32_e32 v8, 8, v7
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_le_f32_e32 0, v9
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_17
ds_load_b32 v10, v7
ds_load_b32 v11, v2
ds_load_b32 v12, v6
s_waitcnt lgkmcnt(2)
v_dual_max_f32 v9, v9, v9 :: v_dual_max_f32 v10, v10, v10
s_waitcnt lgkmcnt(1)
v_max_f32_e32 v11, v11, v11
s_delay_alu instid0(VALU_DEP_1)
v_min_f32_e32 v10, v11, v10
ds_store_b32 v2, v10
ds_load_b32 v10, v4
ds_load_b32 v11, v7 offset:4
ds_load_b32 v13, v5
s_waitcnt lgkmcnt(1)
v_dual_max_f32 v10, v10, v10 :: v_dual_max_f32 v11, v11, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_max_f32_e32 v10, v10, v11
ds_store_b32 v4, v10
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(0)
v_max_f32_e32 v8, v8, v8
v_min_f32_e32 v8, v9, v8
v_max_f32_e32 v9, v13, v13
ds_store_b32 v3, v8
ds_load_b32 v8, v7 offset:12
s_waitcnt lgkmcnt(0)
v_max_f32_e32 v8, v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_min_f32_e32 v8, v9, v8
ds_store_b32 v5, v8
ds_load_b32 v7, v7 offset:16
s_waitcnt lgkmcnt(0)
v_dual_max_f32 v8, v12, v12 :: v_dual_max_f32 v7, v7, v7
v_min_f32_e32 v7, v8, v7
ds_store_b32 v6, v7
.LBB0_17:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_11
ds_load_b32 v9, v7
s_waitcnt lgkmcnt(0)
ds_store_b32 v2, v9
ds_load_b32 v9, v7 offset:4
s_waitcnt lgkmcnt(0)
ds_store_b32 v4, v9
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(0)
ds_store_b32 v3, v8
ds_load_b32 v8, v7 offset:12
s_waitcnt lgkmcnt(0)
ds_store_b32 v5, v8
ds_load_b32 v7, v7 offset:16
s_waitcnt lgkmcnt(0)
ds_store_b32 v6, v7
s_branch .LBB0_11
.LBB0_19:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_21
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mul_i32 s2, s15, s3
ds_load_b32 v4, v0
ds_load_2addr_b32 v[2:3], v0 offset0:3 offset1:4
ds_load_2addr_b32 v[0:1], v0 offset0:1 offset1:2
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_clause 0x1
global_store_b32 v5, v4, s[0:1]
global_store_b128 v5, v[0:3], s[0:1] offset:4
.LBB0_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel copyReductionKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size copyReductionKernel, .Lfunc_end0-copyReductionKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: copyReductionKernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: copyReductionKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018e927_00000000-6_copyReductionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z19copyReductionKernelP6float4PfiiiP6float4Pfiii
.type _Z50__device_stub__Z19copyReductionKernelP6float4PfiiiP6float4Pfiii, @function
_Z50__device_stub__Z19copyReductionKernelP6float4PfiiiP6float4Pfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq copyReductionKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z19copyReductionKernelP6float4PfiiiP6float4Pfiii, .-_Z50__device_stub__Z19copyReductionKernelP6float4PfiiiP6float4Pfiii
.globl copyReductionKernel
.type copyReductionKernel, @function
copyReductionKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z19copyReductionKernelP6float4PfiiiP6float4Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size copyReductionKernel, .-copyReductionKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "copyReductionKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq copyReductionKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "copyReductionKernel.hip"
.globl __device_stub__copyReductionKernel # -- Begin function __device_stub__copyReductionKernel
.p2align 4, 0x90
.type __device_stub__copyReductionKernel,@function
__device_stub__copyReductionKernel: # @__device_stub__copyReductionKernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $copyReductionKernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__copyReductionKernel, .Lfunc_end0-__device_stub__copyReductionKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $copyReductionKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type copyReductionKernel,@object # @copyReductionKernel
.section .rodata,"a",@progbits
.globl copyReductionKernel
.p2align 3, 0x0
copyReductionKernel:
.quad __device_stub__copyReductionKernel
.size copyReductionKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "copyReductionKernel"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__copyReductionKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym copyReductionKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void decryptKernel(char* deviceDataIn, char* deviceDataOut, int n) {
unsigned index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n)
deviceDataOut[index] = deviceDataIn[index]-1;
} | code for sm_80
Function : _Z13decryptKernelPcS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0080*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0090*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00a0*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fca0007f1e0ff */
/*00b0*/ IMAD.X R5, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff057624 */
/* 0x000fe200000e06ff */
/*00c0*/ IADD3 R7, R2, -0x1, RZ ; /* 0xffffffff02077810 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void decryptKernel(char* deviceDataIn, char* deviceDataOut, int n) {
unsigned index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n)
deviceDataOut[index] = deviceDataIn[index]-1;
} | .file "tmpxft_00096fcf_00000000-6_decryptKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13decryptKernelPcS_iPcS_i
.type _Z36__device_stub__Z13decryptKernelPcS_iPcS_i, @function
_Z36__device_stub__Z13decryptKernelPcS_iPcS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13decryptKernelPcS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13decryptKernelPcS_iPcS_i, .-_Z36__device_stub__Z13decryptKernelPcS_iPcS_i
.globl _Z13decryptKernelPcS_i
.type _Z13decryptKernelPcS_i, @function
_Z13decryptKernelPcS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13decryptKernelPcS_iPcS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13decryptKernelPcS_i, .-_Z13decryptKernelPcS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13decryptKernelPcS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13decryptKernelPcS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void decryptKernel(char* deviceDataIn, char* deviceDataOut, int n) {
unsigned index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n)
deviceDataOut[index] = deviceDataIn[index]-1;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void decryptKernel(char* deviceDataIn, char* deviceDataOut, int n) {
unsigned index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n)
deviceDataOut[index] = deviceDataIn[index]-1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void decryptKernel(char* deviceDataIn, char* deviceDataOut, int n) {
unsigned index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n)
deviceDataOut[index] = deviceDataIn[index]-1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13decryptKernelPcS_i
.globl _Z13decryptKernelPcS_i
.p2align 8
.type _Z13decryptKernelPcS_i,@function
_Z13decryptKernelPcS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v0, v1, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v0, v0, -1
global_store_b8 v1, v0, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13decryptKernelPcS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13decryptKernelPcS_i, .Lfunc_end0-_Z13decryptKernelPcS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13decryptKernelPcS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z13decryptKernelPcS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void decryptKernel(char* deviceDataIn, char* deviceDataOut, int n) {
unsigned index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n)
deviceDataOut[index] = deviceDataIn[index]-1;
} | .text
.file "decryptKernel.hip"
.globl _Z28__device_stub__decryptKernelPcS_i # -- Begin function _Z28__device_stub__decryptKernelPcS_i
.p2align 4, 0x90
.type _Z28__device_stub__decryptKernelPcS_i,@function
_Z28__device_stub__decryptKernelPcS_i: # @_Z28__device_stub__decryptKernelPcS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13decryptKernelPcS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__decryptKernelPcS_i, .Lfunc_end0-_Z28__device_stub__decryptKernelPcS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13decryptKernelPcS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13decryptKernelPcS_i,@object # @_Z13decryptKernelPcS_i
.section .rodata,"a",@progbits
.globl _Z13decryptKernelPcS_i
.p2align 3, 0x0
_Z13decryptKernelPcS_i:
.quad _Z28__device_stub__decryptKernelPcS_i
.size _Z13decryptKernelPcS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13decryptKernelPcS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__decryptKernelPcS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13decryptKernelPcS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13decryptKernelPcS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0080*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0090*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00a0*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fca0007f1e0ff */
/*00b0*/ IMAD.X R5, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff057624 */
/* 0x000fe200000e06ff */
/*00c0*/ IADD3 R7, R2, -0x1, RZ ; /* 0xffffffff02077810 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13decryptKernelPcS_i
.globl _Z13decryptKernelPcS_i
.p2align 8
.type _Z13decryptKernelPcS_i,@function
_Z13decryptKernelPcS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v0, v1, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v0, v0, -1
global_store_b8 v1, v0, s[2:3]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13decryptKernelPcS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13decryptKernelPcS_i, .Lfunc_end0-_Z13decryptKernelPcS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13decryptKernelPcS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z13decryptKernelPcS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00096fcf_00000000-6_decryptKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13decryptKernelPcS_iPcS_i
.type _Z36__device_stub__Z13decryptKernelPcS_iPcS_i, @function
_Z36__device_stub__Z13decryptKernelPcS_iPcS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13decryptKernelPcS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13decryptKernelPcS_iPcS_i, .-_Z36__device_stub__Z13decryptKernelPcS_iPcS_i
.globl _Z13decryptKernelPcS_i
.type _Z13decryptKernelPcS_i, @function
_Z13decryptKernelPcS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13decryptKernelPcS_iPcS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13decryptKernelPcS_i, .-_Z13decryptKernelPcS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13decryptKernelPcS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13decryptKernelPcS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "decryptKernel.hip"
.globl _Z28__device_stub__decryptKernelPcS_i # -- Begin function _Z28__device_stub__decryptKernelPcS_i
.p2align 4, 0x90
.type _Z28__device_stub__decryptKernelPcS_i,@function
_Z28__device_stub__decryptKernelPcS_i: # @_Z28__device_stub__decryptKernelPcS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13decryptKernelPcS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__decryptKernelPcS_i, .Lfunc_end0-_Z28__device_stub__decryptKernelPcS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13decryptKernelPcS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13decryptKernelPcS_i,@object # @_Z13decryptKernelPcS_i
.section .rodata,"a",@progbits
.globl _Z13decryptKernelPcS_i
.p2align 3, 0x0
_Z13decryptKernelPcS_i:
.quad _Z28__device_stub__decryptKernelPcS_i
.size _Z13decryptKernelPcS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13decryptKernelPcS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__decryptKernelPcS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13decryptKernelPcS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define NUM 10
__global__ void averagePx(int * a, int * c)
{
int width = blockIdx.x;
printf("w: %d\n", width);
if(width < NUM*NUM) {
c[width] = a[width] / 2;
}
}
int main ()
{
int a[NUM][NUM], c[NUM*NUM];
int change_a[NUM*NUM];
int *de_a, *de_c;
// 이미지의 값을 넣어 준다. 지금은 내 임의로 넣는다.
int gap = 0;
for (int i = 0; i < NUM; ++i) {
for (int j = 0; j < NUM; ++j) {
a[i][j] = 5 * 10;
change_a[gap] = a[i][j];
printf("a[%d][%d] = %d\n", i, j, a[i][j]);
printf("gap[%d] = %d\n", gap, change_a[gap]);
++gap;
}
}
// 이미지를 일차원으로 바꿔준다.
cudaMalloc((void**)&de_a, sizeof(int) * NUM*NUM);
cudaMalloc((void**)&de_c, sizeof(int) * NUM*NUM);
cudaMemcpy(de_a, change_a, sizeof(int) * NUM*NUM, cudaMemcpyHostToDevice);
averagePx <<<100, 1>>> (de_a, de_c);
cudaMemcpy(c, de_c, sizeof(int) * NUM*NUM, cudaMemcpyDeviceToHost);
for (int i = 0; i < NUM*NUM; ++i) {
printf("a(%d) = c(%d)\n", change_a[i], c[i]);
}
cudaFree(de_a);
cudaFree(de_c);
getchar();
return 0;
} | code for sm_80
Function : _Z9averagePxPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fc60000000000 */
/*00b0*/ MOV R3, 0x120 ; /* 0x0000012000037802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0100*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0110*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x004fea0003c00000 */
/*0120*/ ISETP.GT.AND P0, PT, R2, 0x63, PT ; /* 0x000000630200780c */
/* 0x000fda0003f04270 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0150*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0160*/ IMAD.WIDE R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fcc00078e0203 */
/*0170*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0203 */
/*0190*/ LEA.HI R0, R4, R4, RZ, 0x1 ; /* 0x0000000404007211 */
/* 0x004fc800078f08ff */
/*01a0*/ SHF.R.S32.HI R7, RZ, 0x1, R0 ; /* 0x00000001ff077819 */
/* 0x000fca0000011400 */
/*01b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define NUM 10
__global__ void averagePx(int * a, int * c)
{
int width = blockIdx.x;
printf("w: %d\n", width);
if(width < NUM*NUM) {
c[width] = a[width] / 2;
}
}
int main ()
{
int a[NUM][NUM], c[NUM*NUM];
int change_a[NUM*NUM];
int *de_a, *de_c;
// 이미지의 값을 넣어 준다. 지금은 내 임의로 넣는다.
int gap = 0;
for (int i = 0; i < NUM; ++i) {
for (int j = 0; j < NUM; ++j) {
a[i][j] = 5 * 10;
change_a[gap] = a[i][j];
printf("a[%d][%d] = %d\n", i, j, a[i][j]);
printf("gap[%d] = %d\n", gap, change_a[gap]);
++gap;
}
}
// 이미지를 일차원으로 바꿔준다.
cudaMalloc((void**)&de_a, sizeof(int) * NUM*NUM);
cudaMalloc((void**)&de_c, sizeof(int) * NUM*NUM);
cudaMemcpy(de_a, change_a, sizeof(int) * NUM*NUM, cudaMemcpyHostToDevice);
averagePx <<<100, 1>>> (de_a, de_c);
cudaMemcpy(c, de_c, sizeof(int) * NUM*NUM, cudaMemcpyDeviceToHost);
for (int i = 0; i < NUM*NUM; ++i) {
printf("a(%d) = c(%d)\n", change_a[i], c[i]);
}
cudaFree(de_a);
cudaFree(de_c);
getchar();
return 0;
} | .file "tmpxft_001b95b9_00000000-6_ImageConverter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9averagePxPiS_PiS_
.type _Z30__device_stub__Z9averagePxPiS_PiS_, @function
_Z30__device_stub__Z9averagePxPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9averagePxPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9averagePxPiS_PiS_, .-_Z30__device_stub__Z9averagePxPiS_PiS_
.globl _Z9averagePxPiS_
.type _Z9averagePxPiS_, @function
_Z9averagePxPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9averagePxPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9averagePxPiS_, .-_Z9averagePxPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "a[%d][%d] = %d\n"
.LC1:
.string "gap[%d] = %d\n"
.LC2:
.string "a(%d) = c(%d)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $872, %rsp
.cfi_def_cfa_offset 928
movq %fs:40, %rax
movq %rax, 856(%rsp)
xorl %eax, %eax
leaq 448(%rsp), %rbp
movl $0, %r14d
movl $0, %r13d
leaq .LC0(%rip), %r15
.L12:
movl $0, %ebx
.L13:
leal 0(%r13,%rbx), %r12d
movl $50, 0(%rbp,%rbx,4)
movl $50, %r8d
movl %ebx, %ecx
movl %r14d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 0(%rbp,%rbx,4), %ecx
movl %r12d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L13
addl $10, %r13d
addl $1, %r14d
addq $40, %rbp
cmpl $100, %r13d
jne .L12
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 448(%rsp), %rsi
movl $1, %ecx
movl $400, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $100, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $400, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L16:
movl 48(%rsp,%rbx), %ecx
movl 448(%rsp,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $400, %rbx
jne .L16
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 856(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $872, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9averagePxPiS_PiS_
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9averagePxPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9averagePxPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define NUM 10
__global__ void averagePx(int * a, int * c)
{
int width = blockIdx.x;
printf("w: %d\n", width);
if(width < NUM*NUM) {
c[width] = a[width] / 2;
}
}
int main ()
{
int a[NUM][NUM], c[NUM*NUM];
int change_a[NUM*NUM];
int *de_a, *de_c;
// 이미지의 값을 넣어 준다. 지금은 내 임의로 넣는다.
int gap = 0;
for (int i = 0; i < NUM; ++i) {
for (int j = 0; j < NUM; ++j) {
a[i][j] = 5 * 10;
change_a[gap] = a[i][j];
printf("a[%d][%d] = %d\n", i, j, a[i][j]);
printf("gap[%d] = %d\n", gap, change_a[gap]);
++gap;
}
}
// 이미지를 일차원으로 바꿔준다.
cudaMalloc((void**)&de_a, sizeof(int) * NUM*NUM);
cudaMalloc((void**)&de_c, sizeof(int) * NUM*NUM);
cudaMemcpy(de_a, change_a, sizeof(int) * NUM*NUM, cudaMemcpyHostToDevice);
averagePx <<<100, 1>>> (de_a, de_c);
cudaMemcpy(c, de_c, sizeof(int) * NUM*NUM, cudaMemcpyDeviceToHost);
for (int i = 0; i < NUM*NUM; ++i) {
printf("a(%d) = c(%d)\n", change_a[i], c[i]);
}
cudaFree(de_a);
cudaFree(de_c);
getchar();
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define NUM 10
__global__ void averagePx(int * a, int * c)
{
int width = blockIdx.x;
printf("w: %d\n", width);
if(width < NUM*NUM) {
c[width] = a[width] / 2;
}
}
int main ()
{
int a[NUM][NUM], c[NUM*NUM];
int change_a[NUM*NUM];
int *de_a, *de_c;
// 이미지의 값을 넣어 준다. 지금은 내 임의로 넣는다.
int gap = 0;
for (int i = 0; i < NUM; ++i) {
for (int j = 0; j < NUM; ++j) {
a[i][j] = 5 * 10;
change_a[gap] = a[i][j];
printf("a[%d][%d] = %d\n", i, j, a[i][j]);
printf("gap[%d] = %d\n", gap, change_a[gap]);
++gap;
}
}
// 이미지를 일차원으로 바꿔준다.
hipMalloc((void**)&de_a, sizeof(int) * NUM*NUM);
hipMalloc((void**)&de_c, sizeof(int) * NUM*NUM);
hipMemcpy(de_a, change_a, sizeof(int) * NUM*NUM, hipMemcpyHostToDevice);
averagePx <<<100, 1>>> (de_a, de_c);
hipMemcpy(c, de_c, sizeof(int) * NUM*NUM, hipMemcpyDeviceToHost);
for (int i = 0; i < NUM*NUM; ++i) {
printf("a(%d) = c(%d)\n", change_a[i], c[i]);
}
hipFree(de_a);
hipFree(de_c);
getchar();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define NUM 10
__global__ void averagePx(int * a, int * c)
{
int width = blockIdx.x;
printf("w: %d\n", width);
if(width < NUM*NUM) {
c[width] = a[width] / 2;
}
}
int main ()
{
int a[NUM][NUM], c[NUM*NUM];
int change_a[NUM*NUM];
int *de_a, *de_c;
// 이미지의 값을 넣어 준다. 지금은 내 임의로 넣는다.
int gap = 0;
for (int i = 0; i < NUM; ++i) {
for (int j = 0; j < NUM; ++j) {
a[i][j] = 5 * 10;
change_a[gap] = a[i][j];
printf("a[%d][%d] = %d\n", i, j, a[i][j]);
printf("gap[%d] = %d\n", gap, change_a[gap]);
++gap;
}
}
// 이미지를 일차원으로 바꿔준다.
hipMalloc((void**)&de_a, sizeof(int) * NUM*NUM);
hipMalloc((void**)&de_c, sizeof(int) * NUM*NUM);
hipMemcpy(de_a, change_a, sizeof(int) * NUM*NUM, hipMemcpyHostToDevice);
averagePx <<<100, 1>>> (de_a, de_c);
hipMemcpy(c, de_c, sizeof(int) * NUM*NUM, hipMemcpyDeviceToHost);
for (int i = 0; i < NUM*NUM; ++i) {
printf("a(%d) = c(%d)\n", change_a[i], c[i]);
}
hipFree(de_a);
hipFree(de_c);
getchar();
return 0;
} | .text
.file "ImageConverter.hip"
.globl _Z24__device_stub__averagePxPiS_ # -- Begin function _Z24__device_stub__averagePxPiS_
.p2align 4, 0x90
.type _Z24__device_stub__averagePxPiS_,@function
_Z24__device_stub__averagePxPiS_: # @_Z24__device_stub__averagePxPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9averagePxPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__averagePxPiS_, .Lfunc_end0-_Z24__device_stub__averagePxPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $888, %rsp # imm = 0x378
.cfi_def_cfa_offset 928
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r15d, %r15d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl %r15d, %r12d
movslq %r15d, %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $50, 480(%rsp,%r15,4)
movl $.L.str, %edi
movl %ebx, %esi
movl %r14d, %edx
movl $50, %ecx
xorl %eax, %eax
callq printf
movl 480(%rsp,%r15,4), %edx
leal (%r12,%r14), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
incl %r14d
cmpl $10, %r14d
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incl %ebx
cmpl $10, %ebx
jne .LBB1_1
# %bb.4:
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq %rsp, %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 8(%rsp), %rdi
leaq 480(%rsp), %rsi
movl $400, %edx # imm = 0x190
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 99(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9averagePxPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $400, %edx # imm = 0x190
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 480(%rsp,%rbx,4), %esi
movl 80(%rsp,%rbx,4), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $100, %rbx
jne .LBB1_7
# %bb.8:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $888, %rsp # imm = 0x378
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9averagePxPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9averagePxPiS_,@object # @_Z9averagePxPiS_
.section .rodata,"a",@progbits
.globl _Z9averagePxPiS_
.p2align 3, 0x0
_Z9averagePxPiS_:
.quad _Z24__device_stub__averagePxPiS_
.size _Z9averagePxPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a[%d][%d] = %d\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "gap[%d] = %d\n"
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "a(%d) = c(%d)\n"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9averagePxPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__averagePxPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9averagePxPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b95b9_00000000-6_ImageConverter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9averagePxPiS_PiS_
.type _Z30__device_stub__Z9averagePxPiS_PiS_, @function
_Z30__device_stub__Z9averagePxPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9averagePxPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9averagePxPiS_PiS_, .-_Z30__device_stub__Z9averagePxPiS_PiS_
.globl _Z9averagePxPiS_
.type _Z9averagePxPiS_, @function
_Z9averagePxPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9averagePxPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9averagePxPiS_, .-_Z9averagePxPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "a[%d][%d] = %d\n"
.LC1:
.string "gap[%d] = %d\n"
.LC2:
.string "a(%d) = c(%d)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $872, %rsp
.cfi_def_cfa_offset 928
movq %fs:40, %rax
movq %rax, 856(%rsp)
xorl %eax, %eax
leaq 448(%rsp), %rbp
movl $0, %r14d
movl $0, %r13d
leaq .LC0(%rip), %r15
.L12:
movl $0, %ebx
.L13:
leal 0(%r13,%rbx), %r12d
movl $50, 0(%rbp,%rbx,4)
movl $50, %r8d
movl %ebx, %ecx
movl %r14d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 0(%rbp,%rbx,4), %ecx
movl %r12d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L13
addl $10, %r13d
addl $1, %r14d
addq $40, %rbp
cmpl $100, %r13d
jne .L12
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 448(%rsp), %rsi
movl $1, %ecx
movl $400, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $100, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $400, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L16:
movl 48(%rsp,%rbx), %ecx
movl 448(%rsp,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $400, %rbx
jne .L16
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 856(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $872, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9averagePxPiS_PiS_
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9averagePxPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9averagePxPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ImageConverter.hip"
.globl _Z24__device_stub__averagePxPiS_ # -- Begin function _Z24__device_stub__averagePxPiS_
.p2align 4, 0x90
.type _Z24__device_stub__averagePxPiS_,@function
_Z24__device_stub__averagePxPiS_: # @_Z24__device_stub__averagePxPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9averagePxPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__averagePxPiS_, .Lfunc_end0-_Z24__device_stub__averagePxPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $888, %rsp # imm = 0x378
.cfi_def_cfa_offset 928
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r15d, %r15d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl %r15d, %r12d
movslq %r15d, %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $50, 480(%rsp,%r15,4)
movl $.L.str, %edi
movl %ebx, %esi
movl %r14d, %edx
movl $50, %ecx
xorl %eax, %eax
callq printf
movl 480(%rsp,%r15,4), %edx
leal (%r12,%r14), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
incl %r14d
cmpl $10, %r14d
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incl %ebx
cmpl $10, %ebx
jne .LBB1_1
# %bb.4:
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq %rsp, %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 8(%rsp), %rdi
leaq 480(%rsp), %rsi
movl $400, %edx # imm = 0x190
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 99(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9averagePxPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $400, %edx # imm = 0x190
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 480(%rsp,%rbx,4), %esi
movl 80(%rsp,%rbx,4), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $100, %rbx
jne .LBB1_7
# %bb.8:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $888, %rsp # imm = 0x378
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9averagePxPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9averagePxPiS_,@object # @_Z9averagePxPiS_
.section .rodata,"a",@progbits
.globl _Z9averagePxPiS_
.p2align 3, 0x0
_Z9averagePxPiS_:
.quad _Z24__device_stub__averagePxPiS_
.size _Z9averagePxPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a[%d][%d] = %d\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "gap[%d] = %d\n"
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "a(%d) = c(%d)\n"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9averagePxPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__averagePxPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9averagePxPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <string>
#include <sstream>
#include <vector>
#include <utility>
#include <cstdlib>
__constant__ unsigned int d_lookup[256];
int get_one(unsigned int value);
struct MyBitMap {
unsigned int *bits;
int x,y;
unsigned long long int size;
MyBitMap(int row, int col) {
int intCols = (col+31)/32;
size = (unsigned long long int)row*(unsigned long long int)intCols;
//printf("Need size: %llu, row: %d, cols: %d \n", size, row, intCols);
bits = new unsigned int[size];
x = row;
y = intCols;
for(int i=0; i<row*intCols; i++)
bits[i] = 0;
}
~MyBitMap() {
delete [] bits;
}
int getSize(){
return x*y;
}
unsigned int *getPointer() {
return bits;
}
int getRow() {
return x;
}
int getCol() {
return y;
}
void setRow(int row1, unsigned int *second, int row2) {
for(int i=0; i<y; i++) {
bits[row1*y+i] = second[row2*y+i];
}
}
void resize(int row, int col) {
delete [] bits;
int intCols = (col+31)/32;
size = (unsigned long long int)row*(unsigned long long int)intCols;
//printf("Need size: %llu \n", size);
bits = new unsigned int[size];
x = row;
y = intCols;
for(int i=0; i<row*intCols; i++)
bits[i] = 0;
}
unsigned int getInt(int row, int colInt) {
return bits[row*y+colInt];
}
void setInt(int row, int colInt, unsigned int value) {
bits[row*y+colInt] = value;
}
void setBit(int row, int col) {
int i = row*y+col/32;
unsigned int flag = 1;
flag = flag<<(31-col%32);
bits[i] = bits[i] | flag;
}
void clearBit(int row, int col) {
int i = row*y+col/32;
unsigned int flag = 1;
flag = flag<<(31-col%32);
if((bits[i]&flag) != 0)
bits[i] = bits[i] - flag;
}
unsigned int getBit(int row, int col) {
int i = row*y+col/32;
unsigned int flag = 1;
flag = flag<<(31-col%32);
if((flag&bits[i]) == 0)
return 0;
else
return 1;
}
void print(int row) {
for(int i=0; i<y; i++)
std::cout<<bits[row*y+i]<<" ";
}
};
__global__ void count_ones(unsigned int *d_itemBitmap, unsigned int *d_bitmap, int numItem, int numTxn, int support)
{
int idx = blockIdx.x*blockDim.x+threadIdx.x;
for (int i=idx; i<numItem; i += blockDim.x*gridDim.x) {
int count = 0;
int colInt = (numTxn+31)/32;
for(int j=0; j<colInt; ++j){
unsigned int temp = d_bitmap[i*colInt+j];
unsigned int one = 255;
one = one&temp;
temp=temp>>8;
unsigned int two = 255;
two = two&temp;
temp=temp>>8;
unsigned int three = 255;
three = three&temp;
unsigned int four = temp>>8;
count += d_lookup[one]+d_lookup[two]+d_lookup[three]+d_lookup[four];
}
if(count >= support){
int itemMapCol = (numItem+1+32)/32;
int index = itemMapCol*i+itemMapCol-1;
unsigned int flag = 1;
flag = flag<<(31-numItem%32);
d_itemBitmap[index] = d_itemBitmap[index] | flag;
}
}
}
__global__ void testSupport(unsigned int *pairs, unsigned int *d_parent_transactions, unsigned int *d_child_transactions, unsigned int *d_child_items, int numItem, int support, int numTxn, int numChild)
{
int idx = blockIdx.x*blockDim.x+threadIdx.x;
for (int i=idx; i<numChild; i += blockDim.x*gridDim.x) {
int count = 0;
int colTxn = (numTxn+31)/32;
int colItem = (numItem+32)/32;
for(int j=0; j<colTxn; ++j) {
int a = pairs[2*i];
int b = pairs[2*i+1];
unsigned int temp = d_parent_transactions[a*colTxn+j] & d_parent_transactions[b*colTxn+j];
d_child_transactions[i*colTxn+j]=temp;
unsigned int one = 255;
one = one&temp;
temp=temp>>8;
unsigned int two = 255;
two = two&temp;
temp=temp>>8;
unsigned int three = 255;
three = three&temp;
unsigned int four = temp>>8;
count += d_lookup[one]+d_lookup[two]+d_lookup[three]+d_lookup[four];
}
if(count >= support) {
int indexHere = colItem*(i+1)-1;
unsigned int flag=1;
flag = flag<<(31-numItem%32);
d_child_items[indexHere] = d_child_items[indexHere] | flag;
}
}
}
__global__ void generateNext(unsigned int *pairs, unsigned int *d_parent, unsigned int *d_child, int itemSize, int itemNum, int size, int rowsItem)
{
int idx = blockIdx.x*blockDim.x+threadIdx.x;
for (int i=idx; i<size; i += blockDim.x*gridDim.x) {
int a=0;
int b;
int newI = i+1;
int temp = rowsItem-1;
while(newI>temp) {
a++;
newI -= temp;
temp--;
}
b=a+newI;
int colInt = (itemNum+32)/32;
int equal = itemSize-2;
for(int p=0; p<colInt; p++) {
unsigned int aParent = d_parent[a*colInt+p];
unsigned int bParent = d_parent[b*colInt+p];
//printf("a: %d, b: %d, avalue: %u, bvalue: %u, p: %d, equal: %d\n",a,b, aParent, bParent, p, equal);
unsigned int flag = 1;
flag = flag<<31;
int satisfy=1;
for(int q=0; q<32; q++) {
if(equal==0) {
satisfy = 2;
break;
}
if((aParent&flag) != (bParent&flag)){
satisfy = 0;
break;
}
else {
if((aParent&flag)!=0)
--equal;
}
flag = flag>>1;
}
if(satisfy==2) {
for(int m=0; m<colInt; m++){
unsigned int aNewParent = d_parent[a*colInt+m];
unsigned int bNewParent = d_parent[b*colInt+m];
d_child[i*colInt+m] = aNewParent | bNewParent;
}
int indexHere = (i+1)*colInt-1;
unsigned int flag=1;
flag = flag<<(31-itemNum%32);
d_child[indexHere] = d_child[indexHere] | flag;
pairs[i*2] = a;
pairs[i*2+1] = b;
//printf("satisfied a: %d, b: %d , d_childlast: %u \n",a, b, d_child[indexHere]);
break;
}
if(satisfy==0){
int indexHere = (i+1)*colInt-1;
d_child[indexHere] = 0;
break;
}
}
}
}
int main(int argc, char *argv[])
{
std::ifstream input_file(argv[1]);
int numBlock = atoi(argv[2]);
int numThreads = atoi(argv[3]);
float support_ratio=0.01;
int tnx, numItem;
input_file>>tnx>>numItem;
float totalTime = 0;
MyBitMap bitmap(numItem, tnx);
int support = tnx*support_ratio;
std::string tempLine;
std::getline(input_file, tempLine);
for(int i=0; i<tnx; i++) {
std::string oneline;
std::getline(input_file, oneline);
std::istringstream items(oneline);
int item;
while(items>>item){
if (item<=numItem && item >0)
bitmap.setBit(item-1, i);
}
items.clear();
}
MyBitMap itemBitmap(numItem, numItem+1);
for(int i=0; i<numItem; i++) {
itemBitmap.setBit(i, i);
}
int lookup[256];
for(unsigned int i=0; i<256; i++) {
lookup[i]=get_one(i);
}
cudaMemcpyToSymbol(d_lookup, lookup, sizeof(int)*256);
unsigned int *d_bitmap, *d_itemBitmap;
cudaMalloc(&d_bitmap, bitmap.getSize()*sizeof(unsigned int));
cudaMalloc(&d_itemBitmap, itemBitmap.getSize()*sizeof(unsigned int));
cudaMemcpy(d_bitmap, bitmap.getPointer(), bitmap.getSize()*sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaMemcpy(d_itemBitmap, itemBitmap.getPointer(), itemBitmap.getSize()*sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
count_ones<<<numBlock, numThreads>>>(d_itemBitmap, d_bitmap, numItem, tnx, support);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
totalTime+=milliseconds;
std::cout<<"Init time: "<<milliseconds<<"--------------------------"<<std::endl;
cudaMemcpy(bitmap.getPointer(),d_bitmap, bitmap.getSize()*sizeof(unsigned int), cudaMemcpyDeviceToHost);
cudaMemcpy(itemBitmap.getPointer(), d_itemBitmap, itemBitmap.getSize()*sizeof(unsigned int), cudaMemcpyDeviceToHost);
cudaFree(d_bitmap);
cudaFree(d_itemBitmap);
int oldCount = numItem;
int newCount = 0;
for(int i=0; i<numItem; i++) {
if(itemBitmap.getBit(i, numItem) == 1)
newCount++;
}
int tnxCol = (tnx+31)/32;
int itemCol = (numItem+32)/32;
int itemSize = 1;
while(newCount > 1) {
std::cout<<std::endl<<"new itemSize: "<<itemSize<<" newCount: "<<newCount<<std::endl<<std::endl;
itemSize++;
MyBitMap newBitmap(newCount, tnx);
MyBitMap newItemmap(newCount, numItem+1);
int j=0;
for(int i=0; i<oldCount; i++) {
if(itemBitmap.getBit(i, numItem) == 1) {
newBitmap.setRow(j, bitmap.getPointer(), i);
newItemmap.setRow(j, itemBitmap.getPointer(), i);
newItemmap.clearBit(j, numItem);
j++;
}
}
int possibleNextChild = (newCount)*(newCount-1)/2;
unsigned int *d_pairs, *d_parent, *d_child;
cudaMalloc(&d_pairs, 2*possibleNextChild*sizeof(unsigned int));
cudaMalloc(&d_parent, newCount*sizeof(unsigned int)*itemCol);
cudaMalloc(&d_child, possibleNextChild*itemCol*sizeof(unsigned int));
printf("Device Variable alloc:\t%s\n", cudaGetErrorString(cudaGetLastError()));
cudaMemcpy(d_parent, newItemmap.getPointer(), newItemmap.getSize()*sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaEventRecord(start);
generateNext<<<numBlock, numThreads>>> (d_pairs, d_parent, d_child, itemSize, numItem, possibleNextChild, newCount);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
totalTime+=milliseconds;
std::cout<<"generate time: "<<milliseconds<<"--------------------------"<<std::endl;
unsigned int *pairs = new unsigned int[2*possibleNextChild];
MyBitMap child(possibleNextChild, numItem+1);
cudaError_t error1 = cudaMemcpy(pairs, d_pairs, 2*possibleNextChild*sizeof(unsigned int), cudaMemcpyDeviceToHost);
cudaError_t error2 = cudaMemcpy(child.getPointer(), d_child, itemCol*possibleNextChild*sizeof(unsigned int), cudaMemcpyDeviceToHost);
//printf("Error1: %s\n", cudaGetErrorString(error1));
//printf("Error2: %s\n", cudaGetErrorString(error2));
printf("Device Variable Copying:\t%s\n", cudaGetErrorString(cudaGetLastError()));
cudaFree(d_child);
cudaFree(d_pairs);
cudaFree(d_parent);
int usefulChild=0;
for(int m=0; m<possibleNextChild; m++) {
if(child.getBit(m,numItem) == 1)
usefulChild++;
}
unsigned int *pairsGen = new unsigned int[2*usefulChild];
std::cout<<std::endl<<"usefulChild:"<<usefulChild<<std::endl<<std::endl;
itemBitmap.resize(usefulChild, numItem+1);
j=0;
for(int m=0; m<possibleNextChild; m++) {
if(child.getBit(m, numItem) == 1) {
itemBitmap.setRow(j, child.getPointer(), m);
itemBitmap.clearBit(j, numItem);
pairsGen[j*2]=pairs[2*m];
pairsGen[j*2+1]=pairs[2*m+1];
++j;
}
}
delete []pairs;
unsigned int *d_parent_tnx, *d_child_tnx, *d_child_item;
cudaMalloc(&d_pairs, 2*usefulChild*sizeof(unsigned int));
cudaMalloc(&d_parent_tnx, newCount*sizeof(unsigned int)*tnxCol);
cudaMalloc(&d_child_tnx, usefulChild*sizeof(unsigned int)*tnxCol);
cudaMalloc(&d_child_item, usefulChild*sizeof(unsigned int)*itemCol);
cudaMemcpy(d_pairs, pairsGen, 2*usefulChild*sizeof(unsigned int),cudaMemcpyHostToDevice);
cudaMemcpy(d_parent_tnx,newBitmap.getPointer() , newCount*sizeof(unsigned int)*tnxCol,cudaMemcpyHostToDevice);
cudaMemcpy(d_child_item,itemBitmap.getPointer() , usefulChild*sizeof(unsigned int)*itemCol,cudaMemcpyHostToDevice);
cudaEventRecord(start);
testSupport<<<numBlock, numThreads>>> (d_pairs, d_parent_tnx, d_child_tnx, d_child_item, numItem, support, tnx, usefulChild);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
totalTime+=milliseconds;
std::cout<<"test time: "<<milliseconds<<"--------------------------"<<std::endl;
bitmap.resize(usefulChild, tnx);
cudaMemcpy(itemBitmap.getPointer(), d_child_item, usefulChild*sizeof(unsigned int)*itemCol, cudaMemcpyDeviceToHost);
cudaMemcpy(bitmap.getPointer(), d_child_tnx, usefulChild*sizeof(unsigned int)*tnxCol, cudaMemcpyDeviceToHost);
newCount = 0;
for(int m=0; m<usefulChild; m++) {
if(itemBitmap.getBit(m, numItem) == 1)
newCount++;
}
oldCount = usefulChild;
cudaFree(d_pairs);
cudaFree(d_parent_tnx);
cudaFree(d_child_tnx);
cudaFree(d_child_item);
delete[] pairsGen;
}
std::cout<<"total time: "<<totalTime<<" milliseconds--------------------------"<<std::endl;
return 0;
}
int get_one(unsigned int value){
int count = 0;
unsigned int flag = 1;
for(int i=0; i<8; i++) {
if((value&flag) == flag)
++count;
value = value>>1;
}
return count;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <string>
#include <sstream>
#include <vector>
#include <utility>
#include <cstdlib>
__constant__ unsigned int d_lookup[256];
int get_one(unsigned int value);
struct MyBitMap {
unsigned int *bits;
int x,y;
unsigned long long int size;
MyBitMap(int row, int col) {
int intCols = (col+31)/32;
size = (unsigned long long int)row*(unsigned long long int)intCols;
//printf("Need size: %llu, row: %d, cols: %d \n", size, row, intCols);
bits = new unsigned int[size];
x = row;
y = intCols;
for(int i=0; i<row*intCols; i++)
bits[i] = 0;
}
~MyBitMap() {
delete [] bits;
}
int getSize(){
return x*y;
}
unsigned int *getPointer() {
return bits;
}
int getRow() {
return x;
}
int getCol() {
return y;
}
void setRow(int row1, unsigned int *second, int row2) {
for(int i=0; i<y; i++) {
bits[row1*y+i] = second[row2*y+i];
}
}
void resize(int row, int col) {
delete [] bits;
int intCols = (col+31)/32;
size = (unsigned long long int)row*(unsigned long long int)intCols;
//printf("Need size: %llu \n", size);
bits = new unsigned int[size];
x = row;
y = intCols;
for(int i=0; i<row*intCols; i++)
bits[i] = 0;
}
unsigned int getInt(int row, int colInt) {
return bits[row*y+colInt];
}
void setInt(int row, int colInt, unsigned int value) {
bits[row*y+colInt] = value;
}
void setBit(int row, int col) {
int i = row*y+col/32;
unsigned int flag = 1;
flag = flag<<(31-col%32);
bits[i] = bits[i] | flag;
}
void clearBit(int row, int col) {
int i = row*y+col/32;
unsigned int flag = 1;
flag = flag<<(31-col%32);
if((bits[i]&flag) != 0)
bits[i] = bits[i] - flag;
}
unsigned int getBit(int row, int col) {
int i = row*y+col/32;
unsigned int flag = 1;
flag = flag<<(31-col%32);
if((flag&bits[i]) == 0)
return 0;
else
return 1;
}
void print(int row) {
for(int i=0; i<y; i++)
std::cout<<bits[row*y+i]<<" ";
}
};
__global__ void count_ones(unsigned int *d_itemBitmap, unsigned int *d_bitmap, int numItem, int numTxn, int support)
{
int idx = blockIdx.x*blockDim.x+threadIdx.x;
for (int i=idx; i<numItem; i += blockDim.x*gridDim.x) {
int count = 0;
int colInt = (numTxn+31)/32;
for(int j=0; j<colInt; ++j){
unsigned int temp = d_bitmap[i*colInt+j];
unsigned int one = 255;
one = one&temp;
temp=temp>>8;
unsigned int two = 255;
two = two&temp;
temp=temp>>8;
unsigned int three = 255;
three = three&temp;
unsigned int four = temp>>8;
count += d_lookup[one]+d_lookup[two]+d_lookup[three]+d_lookup[four];
}
if(count >= support){
int itemMapCol = (numItem+1+32)/32;
int index = itemMapCol*i+itemMapCol-1;
unsigned int flag = 1;
flag = flag<<(31-numItem%32);
d_itemBitmap[index] = d_itemBitmap[index] | flag;
}
}
}
__global__ void testSupport(unsigned int *pairs, unsigned int *d_parent_transactions, unsigned int *d_child_transactions, unsigned int *d_child_items, int numItem, int support, int numTxn, int numChild)
{
int idx = blockIdx.x*blockDim.x+threadIdx.x;
for (int i=idx; i<numChild; i += blockDim.x*gridDim.x) {
int count = 0;
int colTxn = (numTxn+31)/32;
int colItem = (numItem+32)/32;
for(int j=0; j<colTxn; ++j) {
int a = pairs[2*i];
int b = pairs[2*i+1];
unsigned int temp = d_parent_transactions[a*colTxn+j] & d_parent_transactions[b*colTxn+j];
d_child_transactions[i*colTxn+j]=temp;
unsigned int one = 255;
one = one&temp;
temp=temp>>8;
unsigned int two = 255;
two = two&temp;
temp=temp>>8;
unsigned int three = 255;
three = three&temp;
unsigned int four = temp>>8;
count += d_lookup[one]+d_lookup[two]+d_lookup[three]+d_lookup[four];
}
if(count >= support) {
int indexHere = colItem*(i+1)-1;
unsigned int flag=1;
flag = flag<<(31-numItem%32);
d_child_items[indexHere] = d_child_items[indexHere] | flag;
}
}
}
__global__ void generateNext(unsigned int *pairs, unsigned int *d_parent, unsigned int *d_child, int itemSize, int itemNum, int size, int rowsItem)
{
int idx = blockIdx.x*blockDim.x+threadIdx.x;
for (int i=idx; i<size; i += blockDim.x*gridDim.x) {
int a=0;
int b;
int newI = i+1;
int temp = rowsItem-1;
while(newI>temp) {
a++;
newI -= temp;
temp--;
}
b=a+newI;
int colInt = (itemNum+32)/32;
int equal = itemSize-2;
for(int p=0; p<colInt; p++) {
unsigned int aParent = d_parent[a*colInt+p];
unsigned int bParent = d_parent[b*colInt+p];
//printf("a: %d, b: %d, avalue: %u, bvalue: %u, p: %d, equal: %d\n",a,b, aParent, bParent, p, equal);
unsigned int flag = 1;
flag = flag<<31;
int satisfy=1;
for(int q=0; q<32; q++) {
if(equal==0) {
satisfy = 2;
break;
}
if((aParent&flag) != (bParent&flag)){
satisfy = 0;
break;
}
else {
if((aParent&flag)!=0)
--equal;
}
flag = flag>>1;
}
if(satisfy==2) {
for(int m=0; m<colInt; m++){
unsigned int aNewParent = d_parent[a*colInt+m];
unsigned int bNewParent = d_parent[b*colInt+m];
d_child[i*colInt+m] = aNewParent | bNewParent;
}
int indexHere = (i+1)*colInt-1;
unsigned int flag=1;
flag = flag<<(31-itemNum%32);
d_child[indexHere] = d_child[indexHere] | flag;
pairs[i*2] = a;
pairs[i*2+1] = b;
//printf("satisfied a: %d, b: %d , d_childlast: %u \n",a, b, d_child[indexHere]);
break;
}
if(satisfy==0){
int indexHere = (i+1)*colInt-1;
d_child[indexHere] = 0;
break;
}
}
}
}
int main(int argc, char *argv[])
{
std::ifstream input_file(argv[1]);
int numBlock = atoi(argv[2]);
int numThreads = atoi(argv[3]);
float support_ratio=0.01;
int tnx, numItem;
input_file>>tnx>>numItem;
float totalTime = 0;
MyBitMap bitmap(numItem, tnx);
int support = tnx*support_ratio;
std::string tempLine;
std::getline(input_file, tempLine);
for(int i=0; i<tnx; i++) {
std::string oneline;
std::getline(input_file, oneline);
std::istringstream items(oneline);
int item;
while(items>>item){
if (item<=numItem && item >0)
bitmap.setBit(item-1, i);
}
items.clear();
}
MyBitMap itemBitmap(numItem, numItem+1);
for(int i=0; i<numItem; i++) {
itemBitmap.setBit(i, i);
}
int lookup[256];
for(unsigned int i=0; i<256; i++) {
lookup[i]=get_one(i);
}
hipMemcpyToSymbol(HIP_SYMBOL(d_lookup), lookup, sizeof(int)*256);
unsigned int *d_bitmap, *d_itemBitmap;
hipMalloc(&d_bitmap, bitmap.getSize()*sizeof(unsigned int));
hipMalloc(&d_itemBitmap, itemBitmap.getSize()*sizeof(unsigned int));
hipMemcpy(d_bitmap, bitmap.getPointer(), bitmap.getSize()*sizeof(unsigned int), hipMemcpyHostToDevice);
hipMemcpy(d_itemBitmap, itemBitmap.getPointer(), itemBitmap.getSize()*sizeof(unsigned int), hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
count_ones<<<numBlock, numThreads>>>(d_itemBitmap, d_bitmap, numItem, tnx, support);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
totalTime+=milliseconds;
std::cout<<"Init time: "<<milliseconds<<"--------------------------"<<std::endl;
hipMemcpy(bitmap.getPointer(),d_bitmap, bitmap.getSize()*sizeof(unsigned int), hipMemcpyDeviceToHost);
hipMemcpy(itemBitmap.getPointer(), d_itemBitmap, itemBitmap.getSize()*sizeof(unsigned int), hipMemcpyDeviceToHost);
hipFree(d_bitmap);
hipFree(d_itemBitmap);
int oldCount = numItem;
int newCount = 0;
for(int i=0; i<numItem; i++) {
if(itemBitmap.getBit(i, numItem) == 1)
newCount++;
}
int tnxCol = (tnx+31)/32;
int itemCol = (numItem+32)/32;
int itemSize = 1;
while(newCount > 1) {
std::cout<<std::endl<<"new itemSize: "<<itemSize<<" newCount: "<<newCount<<std::endl<<std::endl;
itemSize++;
MyBitMap newBitmap(newCount, tnx);
MyBitMap newItemmap(newCount, numItem+1);
int j=0;
for(int i=0; i<oldCount; i++) {
if(itemBitmap.getBit(i, numItem) == 1) {
newBitmap.setRow(j, bitmap.getPointer(), i);
newItemmap.setRow(j, itemBitmap.getPointer(), i);
newItemmap.clearBit(j, numItem);
j++;
}
}
int possibleNextChild = (newCount)*(newCount-1)/2;
unsigned int *d_pairs, *d_parent, *d_child;
hipMalloc(&d_pairs, 2*possibleNextChild*sizeof(unsigned int));
hipMalloc(&d_parent, newCount*sizeof(unsigned int)*itemCol);
hipMalloc(&d_child, possibleNextChild*itemCol*sizeof(unsigned int));
printf("Device Variable alloc:\t%s\n", hipGetErrorString(hipGetLastError()));
hipMemcpy(d_parent, newItemmap.getPointer(), newItemmap.getSize()*sizeof(unsigned int), hipMemcpyHostToDevice);
hipEventRecord(start);
generateNext<<<numBlock, numThreads>>> (d_pairs, d_parent, d_child, itemSize, numItem, possibleNextChild, newCount);
hipEventRecord(stop);
hipEventSynchronize(stop);
milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
totalTime+=milliseconds;
std::cout<<"generate time: "<<milliseconds<<"--------------------------"<<std::endl;
unsigned int *pairs = new unsigned int[2*possibleNextChild];
MyBitMap child(possibleNextChild, numItem+1);
hipError_t error1 = hipMemcpy(pairs, d_pairs, 2*possibleNextChild*sizeof(unsigned int), hipMemcpyDeviceToHost);
hipError_t error2 = hipMemcpy(child.getPointer(), d_child, itemCol*possibleNextChild*sizeof(unsigned int), hipMemcpyDeviceToHost);
//printf("Error1: %s\n", cudaGetErrorString(error1));
//printf("Error2: %s\n", cudaGetErrorString(error2));
printf("Device Variable Copying:\t%s\n", hipGetErrorString(hipGetLastError()));
hipFree(d_child);
hipFree(d_pairs);
hipFree(d_parent);
int usefulChild=0;
for(int m=0; m<possibleNextChild; m++) {
if(child.getBit(m,numItem) == 1)
usefulChild++;
}
unsigned int *pairsGen = new unsigned int[2*usefulChild];
std::cout<<std::endl<<"usefulChild:"<<usefulChild<<std::endl<<std::endl;
itemBitmap.resize(usefulChild, numItem+1);
j=0;
for(int m=0; m<possibleNextChild; m++) {
if(child.getBit(m, numItem) == 1) {
itemBitmap.setRow(j, child.getPointer(), m);
itemBitmap.clearBit(j, numItem);
pairsGen[j*2]=pairs[2*m];
pairsGen[j*2+1]=pairs[2*m+1];
++j;
}
}
delete []pairs;
unsigned int *d_parent_tnx, *d_child_tnx, *d_child_item;
hipMalloc(&d_pairs, 2*usefulChild*sizeof(unsigned int));
hipMalloc(&d_parent_tnx, newCount*sizeof(unsigned int)*tnxCol);
hipMalloc(&d_child_tnx, usefulChild*sizeof(unsigned int)*tnxCol);
hipMalloc(&d_child_item, usefulChild*sizeof(unsigned int)*itemCol);
hipMemcpy(d_pairs, pairsGen, 2*usefulChild*sizeof(unsigned int),hipMemcpyHostToDevice);
hipMemcpy(d_parent_tnx,newBitmap.getPointer() , newCount*sizeof(unsigned int)*tnxCol,hipMemcpyHostToDevice);
hipMemcpy(d_child_item,itemBitmap.getPointer() , usefulChild*sizeof(unsigned int)*itemCol,hipMemcpyHostToDevice);
hipEventRecord(start);
testSupport<<<numBlock, numThreads>>> (d_pairs, d_parent_tnx, d_child_tnx, d_child_item, numItem, support, tnx, usefulChild);
hipEventRecord(stop);
hipEventSynchronize(stop);
milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
totalTime+=milliseconds;
std::cout<<"test time: "<<milliseconds<<"--------------------------"<<std::endl;
bitmap.resize(usefulChild, tnx);
hipMemcpy(itemBitmap.getPointer(), d_child_item, usefulChild*sizeof(unsigned int)*itemCol, hipMemcpyDeviceToHost);
hipMemcpy(bitmap.getPointer(), d_child_tnx, usefulChild*sizeof(unsigned int)*tnxCol, hipMemcpyDeviceToHost);
newCount = 0;
for(int m=0; m<usefulChild; m++) {
if(itemBitmap.getBit(m, numItem) == 1)
newCount++;
}
oldCount = usefulChild;
hipFree(d_pairs);
hipFree(d_parent_tnx);
hipFree(d_child_tnx);
hipFree(d_child_item);
delete[] pairsGen;
}
std::cout<<"total time: "<<totalTime<<" milliseconds--------------------------"<<std::endl;
return 0;
}
int get_one(unsigned int value){
int count = 0;
unsigned int flag = 1;
for(int i=0; i<8; i++) {
if((value&flag) == flag)
++count;
value = value>>1;
}
return count;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <string>
#include <sstream>
#include <vector>
#include <utility>
#include <cstdlib>
__constant__ unsigned int d_lookup[256];
int get_one(unsigned int value);
struct MyBitMap {
unsigned int *bits;
int x,y;
unsigned long long int size;
MyBitMap(int row, int col) {
int intCols = (col+31)/32;
size = (unsigned long long int)row*(unsigned long long int)intCols;
//printf("Need size: %llu, row: %d, cols: %d \n", size, row, intCols);
bits = new unsigned int[size];
x = row;
y = intCols;
for(int i=0; i<row*intCols; i++)
bits[i] = 0;
}
~MyBitMap() {
delete [] bits;
}
int getSize(){
return x*y;
}
unsigned int *getPointer() {
return bits;
}
int getRow() {
return x;
}
int getCol() {
return y;
}
void setRow(int row1, unsigned int *second, int row2) {
for(int i=0; i<y; i++) {
bits[row1*y+i] = second[row2*y+i];
}
}
void resize(int row, int col) {
delete [] bits;
int intCols = (col+31)/32;
size = (unsigned long long int)row*(unsigned long long int)intCols;
//printf("Need size: %llu \n", size);
bits = new unsigned int[size];
x = row;
y = intCols;
for(int i=0; i<row*intCols; i++)
bits[i] = 0;
}
unsigned int getInt(int row, int colInt) {
return bits[row*y+colInt];
}
void setInt(int row, int colInt, unsigned int value) {
bits[row*y+colInt] = value;
}
void setBit(int row, int col) {
int i = row*y+col/32;
unsigned int flag = 1;
flag = flag<<(31-col%32);
bits[i] = bits[i] | flag;
}
void clearBit(int row, int col) {
int i = row*y+col/32;
unsigned int flag = 1;
flag = flag<<(31-col%32);
if((bits[i]&flag) != 0)
bits[i] = bits[i] - flag;
}
unsigned int getBit(int row, int col) {
int i = row*y+col/32;
unsigned int flag = 1;
flag = flag<<(31-col%32);
if((flag&bits[i]) == 0)
return 0;
else
return 1;
}
void print(int row) {
for(int i=0; i<y; i++)
std::cout<<bits[row*y+i]<<" ";
}
};
__global__ void count_ones(unsigned int *d_itemBitmap, unsigned int *d_bitmap, int numItem, int numTxn, int support)
{
int idx = blockIdx.x*blockDim.x+threadIdx.x;
for (int i=idx; i<numItem; i += blockDim.x*gridDim.x) {
int count = 0;
int colInt = (numTxn+31)/32;
for(int j=0; j<colInt; ++j){
unsigned int temp = d_bitmap[i*colInt+j];
unsigned int one = 255;
one = one&temp;
temp=temp>>8;
unsigned int two = 255;
two = two&temp;
temp=temp>>8;
unsigned int three = 255;
three = three&temp;
unsigned int four = temp>>8;
count += d_lookup[one]+d_lookup[two]+d_lookup[three]+d_lookup[four];
}
if(count >= support){
int itemMapCol = (numItem+1+32)/32;
int index = itemMapCol*i+itemMapCol-1;
unsigned int flag = 1;
flag = flag<<(31-numItem%32);
d_itemBitmap[index] = d_itemBitmap[index] | flag;
}
}
}
__global__ void testSupport(unsigned int *pairs, unsigned int *d_parent_transactions, unsigned int *d_child_transactions, unsigned int *d_child_items, int numItem, int support, int numTxn, int numChild)
{
int idx = blockIdx.x*blockDim.x+threadIdx.x;
for (int i=idx; i<numChild; i += blockDim.x*gridDim.x) {
int count = 0;
int colTxn = (numTxn+31)/32;
int colItem = (numItem+32)/32;
for(int j=0; j<colTxn; ++j) {
int a = pairs[2*i];
int b = pairs[2*i+1];
unsigned int temp = d_parent_transactions[a*colTxn+j] & d_parent_transactions[b*colTxn+j];
d_child_transactions[i*colTxn+j]=temp;
unsigned int one = 255;
one = one&temp;
temp=temp>>8;
unsigned int two = 255;
two = two&temp;
temp=temp>>8;
unsigned int three = 255;
three = three&temp;
unsigned int four = temp>>8;
count += d_lookup[one]+d_lookup[two]+d_lookup[three]+d_lookup[four];
}
if(count >= support) {
int indexHere = colItem*(i+1)-1;
unsigned int flag=1;
flag = flag<<(31-numItem%32);
d_child_items[indexHere] = d_child_items[indexHere] | flag;
}
}
}
__global__ void generateNext(unsigned int *pairs, unsigned int *d_parent, unsigned int *d_child, int itemSize, int itemNum, int size, int rowsItem)
{
int idx = blockIdx.x*blockDim.x+threadIdx.x;
for (int i=idx; i<size; i += blockDim.x*gridDim.x) {
int a=0;
int b;
int newI = i+1;
int temp = rowsItem-1;
while(newI>temp) {
a++;
newI -= temp;
temp--;
}
b=a+newI;
int colInt = (itemNum+32)/32;
int equal = itemSize-2;
for(int p=0; p<colInt; p++) {
unsigned int aParent = d_parent[a*colInt+p];
unsigned int bParent = d_parent[b*colInt+p];
//printf("a: %d, b: %d, avalue: %u, bvalue: %u, p: %d, equal: %d\n",a,b, aParent, bParent, p, equal);
unsigned int flag = 1;
flag = flag<<31;
int satisfy=1;
for(int q=0; q<32; q++) {
if(equal==0) {
satisfy = 2;
break;
}
if((aParent&flag) != (bParent&flag)){
satisfy = 0;
break;
}
else {
if((aParent&flag)!=0)
--equal;
}
flag = flag>>1;
}
if(satisfy==2) {
for(int m=0; m<colInt; m++){
unsigned int aNewParent = d_parent[a*colInt+m];
unsigned int bNewParent = d_parent[b*colInt+m];
d_child[i*colInt+m] = aNewParent | bNewParent;
}
int indexHere = (i+1)*colInt-1;
unsigned int flag=1;
flag = flag<<(31-itemNum%32);
d_child[indexHere] = d_child[indexHere] | flag;
pairs[i*2] = a;
pairs[i*2+1] = b;
//printf("satisfied a: %d, b: %d , d_childlast: %u \n",a, b, d_child[indexHere]);
break;
}
if(satisfy==0){
int indexHere = (i+1)*colInt-1;
d_child[indexHere] = 0;
break;
}
}
}
}
int main(int argc, char *argv[])
{
std::ifstream input_file(argv[1]);
int numBlock = atoi(argv[2]);
int numThreads = atoi(argv[3]);
float support_ratio=0.01;
int tnx, numItem;
input_file>>tnx>>numItem;
float totalTime = 0;
MyBitMap bitmap(numItem, tnx);
int support = tnx*support_ratio;
std::string tempLine;
std::getline(input_file, tempLine);
for(int i=0; i<tnx; i++) {
std::string oneline;
std::getline(input_file, oneline);
std::istringstream items(oneline);
int item;
while(items>>item){
if (item<=numItem && item >0)
bitmap.setBit(item-1, i);
}
items.clear();
}
MyBitMap itemBitmap(numItem, numItem+1);
for(int i=0; i<numItem; i++) {
itemBitmap.setBit(i, i);
}
int lookup[256];
for(unsigned int i=0; i<256; i++) {
lookup[i]=get_one(i);
}
hipMemcpyToSymbol(HIP_SYMBOL(d_lookup), lookup, sizeof(int)*256);
unsigned int *d_bitmap, *d_itemBitmap;
hipMalloc(&d_bitmap, bitmap.getSize()*sizeof(unsigned int));
hipMalloc(&d_itemBitmap, itemBitmap.getSize()*sizeof(unsigned int));
hipMemcpy(d_bitmap, bitmap.getPointer(), bitmap.getSize()*sizeof(unsigned int), hipMemcpyHostToDevice);
hipMemcpy(d_itemBitmap, itemBitmap.getPointer(), itemBitmap.getSize()*sizeof(unsigned int), hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
count_ones<<<numBlock, numThreads>>>(d_itemBitmap, d_bitmap, numItem, tnx, support);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
totalTime+=milliseconds;
std::cout<<"Init time: "<<milliseconds<<"--------------------------"<<std::endl;
hipMemcpy(bitmap.getPointer(),d_bitmap, bitmap.getSize()*sizeof(unsigned int), hipMemcpyDeviceToHost);
hipMemcpy(itemBitmap.getPointer(), d_itemBitmap, itemBitmap.getSize()*sizeof(unsigned int), hipMemcpyDeviceToHost);
hipFree(d_bitmap);
hipFree(d_itemBitmap);
int oldCount = numItem;
int newCount = 0;
for(int i=0; i<numItem; i++) {
if(itemBitmap.getBit(i, numItem) == 1)
newCount++;
}
int tnxCol = (tnx+31)/32;
int itemCol = (numItem+32)/32;
int itemSize = 1;
while(newCount > 1) {
std::cout<<std::endl<<"new itemSize: "<<itemSize<<" newCount: "<<newCount<<std::endl<<std::endl;
itemSize++;
MyBitMap newBitmap(newCount, tnx);
MyBitMap newItemmap(newCount, numItem+1);
int j=0;
for(int i=0; i<oldCount; i++) {
if(itemBitmap.getBit(i, numItem) == 1) {
newBitmap.setRow(j, bitmap.getPointer(), i);
newItemmap.setRow(j, itemBitmap.getPointer(), i);
newItemmap.clearBit(j, numItem);
j++;
}
}
int possibleNextChild = (newCount)*(newCount-1)/2;
unsigned int *d_pairs, *d_parent, *d_child;
hipMalloc(&d_pairs, 2*possibleNextChild*sizeof(unsigned int));
hipMalloc(&d_parent, newCount*sizeof(unsigned int)*itemCol);
hipMalloc(&d_child, possibleNextChild*itemCol*sizeof(unsigned int));
printf("Device Variable alloc:\t%s\n", hipGetErrorString(hipGetLastError()));
hipMemcpy(d_parent, newItemmap.getPointer(), newItemmap.getSize()*sizeof(unsigned int), hipMemcpyHostToDevice);
hipEventRecord(start);
generateNext<<<numBlock, numThreads>>> (d_pairs, d_parent, d_child, itemSize, numItem, possibleNextChild, newCount);
hipEventRecord(stop);
hipEventSynchronize(stop);
milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
totalTime+=milliseconds;
std::cout<<"generate time: "<<milliseconds<<"--------------------------"<<std::endl;
unsigned int *pairs = new unsigned int[2*possibleNextChild];
MyBitMap child(possibleNextChild, numItem+1);
hipError_t error1 = hipMemcpy(pairs, d_pairs, 2*possibleNextChild*sizeof(unsigned int), hipMemcpyDeviceToHost);
hipError_t error2 = hipMemcpy(child.getPointer(), d_child, itemCol*possibleNextChild*sizeof(unsigned int), hipMemcpyDeviceToHost);
//printf("Error1: %s\n", cudaGetErrorString(error1));
//printf("Error2: %s\n", cudaGetErrorString(error2));
printf("Device Variable Copying:\t%s\n", hipGetErrorString(hipGetLastError()));
hipFree(d_child);
hipFree(d_pairs);
hipFree(d_parent);
int usefulChild=0;
for(int m=0; m<possibleNextChild; m++) {
if(child.getBit(m,numItem) == 1)
usefulChild++;
}
unsigned int *pairsGen = new unsigned int[2*usefulChild];
std::cout<<std::endl<<"usefulChild:"<<usefulChild<<std::endl<<std::endl;
itemBitmap.resize(usefulChild, numItem+1);
j=0;
for(int m=0; m<possibleNextChild; m++) {
if(child.getBit(m, numItem) == 1) {
itemBitmap.setRow(j, child.getPointer(), m);
itemBitmap.clearBit(j, numItem);
pairsGen[j*2]=pairs[2*m];
pairsGen[j*2+1]=pairs[2*m+1];
++j;
}
}
delete []pairs;
unsigned int *d_parent_tnx, *d_child_tnx, *d_child_item;
hipMalloc(&d_pairs, 2*usefulChild*sizeof(unsigned int));
hipMalloc(&d_parent_tnx, newCount*sizeof(unsigned int)*tnxCol);
hipMalloc(&d_child_tnx, usefulChild*sizeof(unsigned int)*tnxCol);
hipMalloc(&d_child_item, usefulChild*sizeof(unsigned int)*itemCol);
hipMemcpy(d_pairs, pairsGen, 2*usefulChild*sizeof(unsigned int),hipMemcpyHostToDevice);
hipMemcpy(d_parent_tnx,newBitmap.getPointer() , newCount*sizeof(unsigned int)*tnxCol,hipMemcpyHostToDevice);
hipMemcpy(d_child_item,itemBitmap.getPointer() , usefulChild*sizeof(unsigned int)*itemCol,hipMemcpyHostToDevice);
hipEventRecord(start);
testSupport<<<numBlock, numThreads>>> (d_pairs, d_parent_tnx, d_child_tnx, d_child_item, numItem, support, tnx, usefulChild);
hipEventRecord(stop);
hipEventSynchronize(stop);
milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
totalTime+=milliseconds;
std::cout<<"test time: "<<milliseconds<<"--------------------------"<<std::endl;
bitmap.resize(usefulChild, tnx);
hipMemcpy(itemBitmap.getPointer(), d_child_item, usefulChild*sizeof(unsigned int)*itemCol, hipMemcpyDeviceToHost);
hipMemcpy(bitmap.getPointer(), d_child_tnx, usefulChild*sizeof(unsigned int)*tnxCol, hipMemcpyDeviceToHost);
newCount = 0;
for(int m=0; m<usefulChild; m++) {
if(itemBitmap.getBit(m, numItem) == 1)
newCount++;
}
oldCount = usefulChild;
hipFree(d_pairs);
hipFree(d_parent_tnx);
hipFree(d_child_tnx);
hipFree(d_child_item);
delete[] pairsGen;
}
std::cout<<"total time: "<<totalTime<<" milliseconds--------------------------"<<std::endl;
return 0;
}
int get_one(unsigned int value){
int count = 0;
unsigned int flag = 1;
for(int i=0; i<8; i++) {
if((value&flag) == flag)
++count;
value = value>>1;
}
return count;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10count_onesPjS_iii
.globl _Z10count_onesPjS_iii
.p2align 8
.type _Z10count_onesPjS_iii,@function
_Z10count_onesPjS_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_9
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x14
s_load_b32 s10, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, -4
s_addc_u32 s3, s5, -1
s_add_i32 s4, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s5, s4, 31
s_lshr_b32 s5, s5, 27
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s5, s4, s5
s_mov_b32 s4, 0
s_ashr_i32 s12, s5, 5
s_cmp_gt_i32 s0, 0
s_mul_i32 s5, s10, s9
s_cselect_b32 s9, -1, 0
s_add_i32 s0, s8, 33
v_mul_lo_u32 v2, s12, v1
s_ashr_i32 s11, s0, 31
s_lshr_b32 s10, 0x80000000, s8
s_lshr_b32 s11, s11, 27
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s0, s0, s11
s_max_i32 s11, s12, 1
s_ashr_i32 s0, s0, 5
s_mul_i32 s12, s5, s12
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v1, s5, v1
v_add_nc_u32_e32 v2, s12, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s4, vcc_lo, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_9
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_6
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v0, 0
s_mov_b32 s13, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_5:
global_load_b32 v5, v[3:4], off
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, d_lookup@rel32@lo+4
s_addc_u32 s15, s15, d_lookup@rel32@hi+12
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_add_i32 s13, s13, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v6, 0xff, v5
v_lshrrev_b32_e32 v7, 6, v5
v_lshrrev_b32_e32 v8, 14, v5
v_lshrrev_b32_e32 v5, 22, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b32_e32 v6, 2, v6
v_and_b32_e32 v7, 0x3fc, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_and_b32_e32 v8, 0x3fc, v8
v_and_b32_e32 v5, 0x3fc, v5
s_clause 0x3
global_load_b32 v6, v6, s[14:15]
global_load_b32 v7, v7, s[14:15]
global_load_b32 v8, v8, s[14:15]
global_load_b32 v5, v5, s[14:15]
s_waitcnt vmcnt(2)
v_add3_u32 v0, v6, v0, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v0, v8, v5
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v0, 0
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 s1, v0
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[3:4], null, s0, v1, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_or_b32_e32 v0, s10, v0
global_store_b32 v[3:4], v0, off
s_branch .LBB0_2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10count_onesPjS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10count_onesPjS_iii, .Lfunc_end0-_Z10count_onesPjS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11testSupportPjS_S_S_iiii
.globl _Z11testSupportPjS_S_S_iiii
.p2align 8
.type _Z11testSupportPjS_S_S_iiii,@function
_Z11testSupportPjS_S_S_iiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x2c
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s18, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s18, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB1_9
s_clause 0x2
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s16, s[0:1], 0x28
s_load_b64 s[0:1], s[0:1], 0x20
s_load_b32 s19, s[2:3], 0x0
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s10, -4
s_addc_u32 s13, s11, -1
s_add_i32 s2, s16, 31
s_add_i32 s10, s0, 32
s_ashr_i32 s11, s2, 31
s_ashr_i32 s14, s10, 31
s_lshr_b32 s11, s11, 27
s_lshr_b32 s14, s14, 27
s_add_i32 s2, s2, s11
s_add_i32 s10, s10, s14
s_ashr_i32 s14, s2, 5
s_ashr_i32 s2, s10, 5
v_mul_lo_u32 v2, s14, v1
s_cmp_gt_i32 s16, 0
s_mul_i32 s18, s19, s18
s_cselect_b32 s16, -1, 0
s_lshr_b32 s17, 0x80000000, s0
s_max_i32 s19, s14, 1
s_mul_i32 s20, s18, s14
s_getpc_b64 s[22:23]
s_add_u32 s22, s22, d_lookup@rel32@lo+4
s_addc_u32 s23, s23, d_lookup@rel32@hi+12
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, s18, v1
v_add_nc_u32_e32 v2, s20, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s15, vcc_lo, s15
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB1_9
.LBB1_3:
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB1_6
v_lshlrev_b32_e32 v4, 1, v1
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v0, 0
s_mov_b64 s[10:11], 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_or_b32_e32 v6, 1, v4
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[4:5]
v_add_co_u32 v3, vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[7:8], 2, v[6:7]
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v9, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
.LBB1_5:
s_clause 0x1
global_load_b32 v9, v[5:6], off
global_load_b32 v10, v[7:8], off
s_waitcnt vmcnt(1)
v_mul_lo_u32 v11, v9, s14
s_waitcnt vmcnt(0)
v_mul_lo_u32 v9, v10, s14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v10, 31, v11
v_ashrrev_i32_e32 v13, 31, v9
v_add_co_u32 v11, s0, s10, v11
v_add_co_u32 v9, vcc_lo, s10, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v12, s0, s11, v10, s0
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v13, vcc_lo
s_add_u32 s10, s10, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_addc_u32 s11, s11, 0
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_cmp_eq_u32 s19, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_clause 0x1
global_load_b32 v11, v[11:12], off
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v10, 0xff, v9
v_lshrrev_b32_e32 v11, 6, v9
v_lshrrev_b32_e32 v12, 14, v9
v_lshrrev_b32_e32 v13, 22, v9
global_store_b32 v[3:4], v9, off
v_lshlrev_b32_e32 v10, 2, v10
v_and_b32_e32 v11, 0x3fc, v11
v_and_b32_e32 v9, 0x3fc, v12
v_and_b32_e32 v12, 0x3fc, v13
s_clause 0x3
global_load_b32 v10, v10, s[22:23]
global_load_b32 v11, v11, s[22:23]
global_load_b32 v9, v9, s[22:23]
global_load_b32 v12, v12, s[22:23]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(2)
v_add3_u32 v0, v10, v0, v11
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v0, v9, v12
s_cbranch_scc0 .LBB1_5
s_branch .LBB1_7
.LBB1_6:
v_mov_b32_e32 v0, 0
.LBB1_7:
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 s1, v0
s_cbranch_execz .LBB1_2
v_mad_u64_u32 v[3:4], null, s2, v1, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s3, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_or_b32_e32 v0, s17, v0
global_store_b32 v[3:4], v0, off
s_branch .LBB1_2
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11testSupportPjS_S_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11testSupportPjS_S_S_iiii, .Lfunc_end1-_Z11testSupportPjS_S_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12generateNextPjS_S_iiii
.globl _Z12generateNextPjS_S_iiii
.p2align 8
.type _Z12generateNextPjS_S_iiii,@function
_Z12generateNextPjS_S_iiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s12, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s16, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s16, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB2_32
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b32 s15, s[2:3], 0x0
s_load_b32 s1, s[0:1], 0x24
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s8, -4
s_addc_u32 s3, s9, -1
s_add_i32 s0, s11, 32
s_add_i32 s10, s10, -2
s_ashr_i32 s13, s0, 31
s_mul_i32 s15, s15, s16
s_lshr_b32 s13, s13, 27
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s13
s_ashr_i32 s13, s0, 5
s_cmp_gt_i32 s11, -1
v_mul_lo_u32 v2, s13, v1
s_cselect_b32 s14, -1, 0
s_lshr_b32 s11, 0x80000000, s11
s_max_i32 s16, s13, 1
s_mul_i32 s17, s15, s13
s_branch .LBB2_4
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s19
.LBB2_3:
v_add_nc_u32_e32 v1, s15, v1
v_add_nc_u32_e32 v2, s17, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s18, vcc_lo, s18
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB2_32
.LBB2_4:
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v0, 1, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v0
v_cmpx_le_i32_e64 s1, v0
s_cbranch_execz .LBB2_8
v_mov_b32_e32 v3, v0
s_mov_b32 s19, 0
s_mov_b32 s20, 0
.LBB2_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_add_i32 s21, s1, s20
s_add_i32 s20, s20, -1
v_subrev_nc_u32_e32 v3, s21, v3
s_add_i32 s21, s1, s20
v_dual_mov_b32 v4, s20 :: v_dual_add_nc_u32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s21, v3
s_or_b32 s19, vcc_lo, s19
s_and_not1_b32 exec_lo, exec_lo, s19
s_cbranch_execnz .LBB2_6
s_or_b32 exec_lo, exec_lo, s19
v_sub_nc_u32_e32 v9, 0, v4
.LBB2_8:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB2_3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v3, s10 :: v_dual_add_nc_u32 v10, v9, v3
v_mul_lo_u32 v4, v9, s13
s_mov_b32 s20, 0
s_mov_b32 s21, 0
v_mul_lo_u32 v6, v10, s13
s_branch .LBB2_12
.LBB2_10:
s_or_b32 exec_lo, exec_lo, s28
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s24, s24, exec_lo
s_and_b32 s25, s27, exec_lo
s_and_not1_b32 s23, s23, exec_lo
s_or_b32 s24, s24, s25
s_or_not1_b32 s27, s26, exec_lo
.LBB2_11:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s27
s_or_b32 s20, s0, s20
s_and_not1_b32 s0, s19, exec_lo
s_and_b32 s19, s24, exec_lo
s_and_not1_b32 s22, s22, exec_lo
s_and_b32 s25, s23, exec_lo
s_or_b32 s19, s0, s19
s_or_b32 s22, s22, s25
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execz .LBB2_21
.LBB2_12:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, s21, v4
v_add_nc_u32_e32 v11, s21, v6
s_brev_b32 s27, 1
s_mov_b32 s28, 32
s_mov_b32 s29, 0
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
s_clause 0x1
global_load_b32 v5, v[7:8], off
global_load_b32 v7, v[11:12], off
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_15
.p2align 6
.LBB2_13:
s_or_b32 exec_lo, exec_lo, s36
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s0, s31, exec_lo
s_and_b32 s31, s35, exec_lo
s_and_not1_b32 s30, s30, exec_lo
s_and_b32 s34, s34, exec_lo
s_or_b32 s31, s0, s31
s_or_b32 s30, s30, s34
.LBB2_14:
s_or_b32 exec_lo, exec_lo, s33
s_xor_b32 s0, s31, -1
s_and_b32 s33, exec_lo, s30
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s29, s33, s29
s_and_not1_b32 s25, s25, exec_lo
s_and_b32 s0, s0, exec_lo
s_and_not1_b32 s26, s26, exec_lo
s_and_b32 s33, vcc_lo, exec_lo
s_or_b32 s25, s25, s0
s_or_b32 s26, s26, s33
s_and_not1_b32 exec_lo, exec_lo, s29
s_cbranch_execz .LBB2_18
.LBB2_15:
v_cmp_ne_u32_e32 vcc_lo, 0, v3
s_and_not1_b32 s31, s31, exec_lo
s_or_b32 s30, s30, exec_lo
s_and_saveexec_b32 s33, vcc_lo
s_cbranch_execz .LBB2_14
s_waitcnt vmcnt(1)
v_and_b32_e32 v8, s27, v5
s_waitcnt vmcnt(0)
v_and_b32_e32 v11, s27, v7
s_mov_b32 s34, -1
s_mov_b32 s35, -1
s_mov_b32 s36, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e64 v8, v11
s_cbranch_execz .LBB2_13
v_cmp_ne_u32_e64 s0, 0, v8
s_add_i32 s28, s28, -1
s_lshr_b32 s27, s27, 1
s_cmp_eq_u32 s28, 0
s_delay_alu instid0(VALU_DEP_1)
v_subrev_co_ci_u32_e64 v3, s0, 0, v3, s0
s_cselect_b32 s0, -1, 0
s_xor_b32 s35, exec_lo, -1
s_or_not1_b32 s34, s0, exec_lo
s_branch .LBB2_13
.LBB2_18:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s29
s_mov_b32 s27, -1
s_and_not1_b32 s24, s24, exec_lo
s_or_b32 s23, s23, exec_lo
s_and_saveexec_b32 s0, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB2_11
s_mov_b32 s26, -1
s_and_saveexec_b32 s28, s25
s_cbranch_execz .LBB2_10
s_add_i32 s21, s21, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s21, s16
s_cselect_b32 s25, -1, 0
s_xor_b32 s27, exec_lo, -1
s_or_not1_b32 s26, s25, exec_lo
s_branch .LBB2_10
.LBB2_21:
s_or_b32 exec_lo, exec_lo, s20
s_xor_b32 s21, s22, -1
s_mov_b32 s0, 0
s_and_saveexec_b32 s22, s21
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s21, exec_lo, s22
s_cbranch_execz .LBB2_25
s_and_saveexec_b32 s22, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s19, exec_lo, s22
v_mul_lo_u32 v3, v0, s13
s_mov_b32 s0, exec_lo
s_mov_b32 s20, 0
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
.LBB2_25:
s_or_saveexec_b32 s19, s21
s_waitcnt vmcnt(0)
v_dual_mov_b32 v5, s20 :: v_dual_mov_b32 v8, s3
v_mov_b32_e32 v7, s2
s_xor_b32 exec_lo, exec_lo, s19
s_cbranch_execz .LBB2_30
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB2_29
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v5, 31, v4
s_mov_b32 s20, s16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[2:3]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 2, v[4:5]
v_add_co_u32 v3, vcc_lo, s8, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v12, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v13
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v14, vcc_lo
.p2align 6
.LBB2_28:
global_load_b32 v11, v[7:8], off
global_load_b32 v12, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_add_i32 s20, s20, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s20, 0
s_waitcnt vmcnt(0)
v_or_b32_e32 v11, v12, v11
global_store_b32 v[3:4], v11, off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_cbranch_scc0 .LBB2_28
.LBB2_29:
v_mul_lo_u32 v3, v0, s13
v_mov_b32_e32 v5, v10
s_or_b32 s0, s0, exec_lo
v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v4, vcc_lo
v_lshlrev_b32_e32 v3, 1, v1
global_load_b32 v0, v[11:12], off
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[13:14], 2, v[3:4]
v_or_b32_e32 v3, 1, v3
v_add_co_u32 v13, vcc_lo, s4, v13
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
s_waitcnt vmcnt(0)
v_or_b32_e32 v0, s11, v0
global_store_b32 v[11:12], v0, off
global_store_b32 v[13:14], v9, off
.LBB2_30:
s_or_b32 exec_lo, exec_lo, s19
s_and_saveexec_b32 s19, s0
s_cbranch_execz .LBB2_2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, v7, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
global_store_b32 v[3:4], v5, off
s_branch .LBB2_2
.LBB2_32:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12generateNextPjS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 37
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z12generateNextPjS_S_iiii, .Lfunc_end2-_Z12generateNextPjS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_lookup
.type d_lookup,@object
.section .bss,"aw",@nobits
.globl d_lookup
.p2align 4, 0x0
d_lookup:
.zero 1024
.size d_lookup, 1024
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_lookup
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10count_onesPjS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10count_onesPjS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11testSupportPjS_S_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z11testSupportPjS_S_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12generateNextPjS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 39
.sgpr_spill_count: 0
.symbol: _Z12generateNextPjS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void LEQ(float * xf, bool * xb, size_t idxf, size_t idxb, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
xb[idxb*N+i] = xf[(idxf-1)*N+i] <= xf[(idxf-2)*N+i];
}
return;
} | code for sm_80
Function : _Z3LEQPfPbmmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R4, RZ, 0x1f, R8 ; /* 0x0000001fff047819 */
/* 0x000fc80000011408 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R4, c[0x0][0x184], PT, P0 ; /* 0x0000610004007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R2, P1, RZ, -c[0x0][0x180], RZ ; /* 0x80006000ff027a10 */
/* 0x000fe20007f3e0ff */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0004 */
/*00d0*/ IADD3 R0, P0, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fe20007f1e1ff */
/*00e0*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0008 */
/*00f0*/ IADD3.X R3, RZ, ~c[0x0][0x184], RZ, P1, !PT ; /* 0x80006100ff037a10 */
/* 0x000fe40000ffe4ff */
/*0100*/ IADD3.X R5, R5, -0x1, RZ, P0, !PT ; /* 0xffffffff05057810 */
/* 0x000fc600007fe4ff */
/*0110*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x180], R2 ; /* 0x0000600000027a25 */
/* 0x000fc800078e0002 */
/*0120*/ IMAD R5, R5, c[0x0][0x180], RZ ; /* 0x0000600005057a24 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD R7, R0, c[0x0][0x184], R5 ; /* 0x0000610000077a24 */
/* 0x000fc800078e0205 */
/*0140*/ IMAD.IADD R6, R3, 0x1, R7 ; /* 0x0000000103067824 */
/* 0x000fe400078e0207 */
/*0150*/ MOV R4, R11 ; /* 0x0000000b00047202 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, R12 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000c */
/*0170*/ IADD3 R9, P0, R11, R2, RZ ; /* 0x000000020b097210 */
/* 0x000fc60007f1e0ff */
/*0180*/ IMAD.WIDE.U32 R10, R0, c[0x0][0x180], R4 ; /* 0x00006000000a7a25 */
/* 0x000fc800078e0004 */
/*0190*/ IMAD.X R16, R12, 0x1, R6, P0 ; /* 0x000000010c107824 */
/* 0x000fe200000e0606 */
/*01a0*/ IADD3 R11, R7, R11, RZ ; /* 0x0000000b070b7210 */
/* 0x000fe40007ffe0ff */
/*01b0*/ LEA R14, P0, R10.reuse, c[0x0][0x160], 0x2 ; /* 0x000058000a0e7a11 */
/* 0x040fe400078010ff */
/*01c0*/ LEA R12, P1, R9.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800090c7a11 */
/* 0x040fe400078210ff */
/*01d0*/ LEA.HI.X R15, R10, c[0x0][0x164], R11, 0x2, P0 ; /* 0x000059000a0f7a11 */
/* 0x000fe400000f140b */
/*01e0*/ LEA.HI.X R13, R9, c[0x0][0x164], R16, 0x2, P1 ; /* 0x00005900090d7a11 */
/* 0x000fc800008f1410 */
/*01f0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1900 */
/*0210*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff097624 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0a7624 */
/* 0x000fe400078e00ff */
/*0230*/ IMAD.WIDE.U32 R4, R9, c[0x0][0x180], R4 ; /* 0x0000600009047a25 */
/* 0x000fc800078e0004 */
/*0240*/ IMAD R9, R9, c[0x0][0x184], RZ ; /* 0x0000610009097a24 */
/* 0x000fe200078e02ff */
/*0250*/ IADD3 R4, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc60007f3e0ff */
/*0260*/ IMAD R9, R10, c[0x0][0x17c], R9 ; /* 0x00005f000a097a24 */
/* 0x000fe200078e0209 */
/*0270*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fc80000000f00 */
/*0280*/ IADD3.X R5, R5, c[0x0][0x16c], R9, P1, !PT ; /* 0x00005b0005057a10 */
/* 0x000fe20000ffe409 */
/*0290*/ IMAD R11, R11, c[0x0][0xc], R8 ; /* 0x000003000b0b7a24 */
/* 0x000fc800078e0208 */
/*02a0*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000b */
/*02b0*/ FSETP.GTU.AND P0, PT, R15, R12, PT ; /* 0x0000000c0f00720b */
/* 0x004fc80003f0c000 */
/*02c0*/ SEL R9, RZ, 0x1, P0 ; /* 0x00000001ff097807 */
/* 0x000fe40000000000 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R11, c[0x0][0x180], PT ; /* 0x000060000b007a0c */
/* 0x000fe40003f06070 */
/*02e0*/ SHF.R.S32.HI R12, RZ, 0x1f, R11 ; /* 0x0000001fff0c7819 */
/* 0x000fe2000001140b */
/*02f0*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e6000c101104 */
/*0300*/ ISETP.GE.U32.AND.EX P0, PT, R12, c[0x0][0x184], PT, P0 ; /* 0x000061000c007a0c */
/* 0x000fda0003f06100 */
/*0310*/ @!P0 BRA 0x150 ; /* 0xfffffe3000008947 */
/* 0x001fea000383ffff */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void LEQ(float * xf, bool * xb, size_t idxf, size_t idxb, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
xb[idxb*N+i] = xf[(idxf-1)*N+i] <= xf[(idxf-2)*N+i];
}
return;
} | .file "tmpxft_0017cb07_00000000-6_LEQ.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3LEQPfPbmmmPfPbmmm
.type _Z27__device_stub__Z3LEQPfPbmmmPfPbmmm, @function
_Z27__device_stub__Z3LEQPfPbmmmPfPbmmm:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3LEQPfPbmmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3LEQPfPbmmmPfPbmmm, .-_Z27__device_stub__Z3LEQPfPbmmmPfPbmmm
.globl _Z3LEQPfPbmmm
.type _Z3LEQPfPbmmm, @function
_Z3LEQPfPbmmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3LEQPfPbmmmPfPbmmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3LEQPfPbmmm, .-_Z3LEQPfPbmmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3LEQPfPbmmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3LEQPfPbmmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void LEQ(float * xf, bool * xb, size_t idxf, size_t idxb, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
xb[idxb*N+i] = xf[(idxf-1)*N+i] <= xf[(idxf-2)*N+i];
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void LEQ(float * xf, bool * xb, size_t idxf, size_t idxb, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
xb[idxb*N+i] = xf[(idxf-1)*N+i] <= xf[(idxf-2)*N+i];
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void LEQ(float * xf, bool * xb, size_t idxf, size_t idxb, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
xb[idxb*N+i] = xf[(idxf-1)*N+i] <= xf[(idxf-2)*N+i];
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3LEQPfPbmmm
.globl _Z3LEQPfPbmmm
.p2align 8
.type _Z3LEQPfPbmmm,@function
_Z3LEQPfPbmmm:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
s_add_u32 s10, s0, 40
s_addc_u32 s11, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_u64_e64 s[8:9], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s13, s4, -1
s_addc_u32 s14, s5, -1
s_mul_i32 s16, s13, s9
s_mul_hi_u32 s17, s13, s8
s_mul_i32 s14, s14, s8
s_add_i32 s17, s17, s16
s_mul_i32 s16, s13, s8
s_add_i32 s17, s17, s14
s_load_b32 s13, s[10:11], 0x0
s_lshl_b64 s[10:11], s[16:17], 2
s_mul_i32 s14, s8, s7
s_add_u32 s7, s0, s10
s_addc_u32 s10, s1, s11
s_add_u32 s4, s4, -2
s_addc_u32 s5, s5, -1
s_mul_i32 s11, s4, s9
s_mul_hi_u32 s16, s4, s8
s_mul_i32 s5, s5, s8
s_add_i32 s11, s16, s11
s_mul_i32 s4, s4, s8
s_add_i32 s5, s11, s5
s_mul_hi_u32 s11, s8, s6
s_lshl_b64 s[4:5], s[4:5], 2
s_mul_i32 s16, s9, s6
s_add_u32 s4, s0, s4
s_addc_u32 s1, s1, s5
s_add_i32 s0, s11, s14
s_mul_i32 s5, s8, s6
s_add_i32 s0, s0, s16
s_add_u32 s2, s2, s5
s_addc_u32 s3, s3, s0
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s13
s_mul_i32 s5, s13, s12
v_mad_u64_u32 v[3:4], null, s15, s12, v[0:1]
s_mov_b32 s6, 0
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s7, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v7, v[4:5], off
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v5, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_u64_e32 vcc_lo, s[8:9], v[3:4]
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_nc_u32_e32 v3, s5, v3
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_cmp_le_f32_e64 s0, v0, v7
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v0, 0, 1, s0
global_store_b8 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3LEQPfPbmmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3LEQPfPbmmm, .Lfunc_end0-_Z3LEQPfPbmmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3LEQPfPbmmm
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z3LEQPfPbmmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void LEQ(float * xf, bool * xb, size_t idxf, size_t idxb, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
xb[idxb*N+i] = xf[(idxf-1)*N+i] <= xf[(idxf-2)*N+i];
}
return;
} | .text
.file "LEQ.hip"
.globl _Z18__device_stub__LEQPfPbmmm # -- Begin function _Z18__device_stub__LEQPfPbmmm
.p2align 4, 0x90
.type _Z18__device_stub__LEQPfPbmmm,@function
_Z18__device_stub__LEQPfPbmmm: # @_Z18__device_stub__LEQPfPbmmm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3LEQPfPbmmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z18__device_stub__LEQPfPbmmm, .Lfunc_end0-_Z18__device_stub__LEQPfPbmmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3LEQPfPbmmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3LEQPfPbmmm,@object # @_Z3LEQPfPbmmm
.section .rodata,"a",@progbits
.globl _Z3LEQPfPbmmm
.p2align 3, 0x0
_Z3LEQPfPbmmm:
.quad _Z18__device_stub__LEQPfPbmmm
.size _Z3LEQPfPbmmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3LEQPfPbmmm"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__LEQPfPbmmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3LEQPfPbmmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3LEQPfPbmmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R4, RZ, 0x1f, R8 ; /* 0x0000001fff047819 */
/* 0x000fc80000011408 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R4, c[0x0][0x184], PT, P0 ; /* 0x0000610004007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R2, P1, RZ, -c[0x0][0x180], RZ ; /* 0x80006000ff027a10 */
/* 0x000fe20007f3e0ff */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0004 */
/*00d0*/ IADD3 R0, P0, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fe20007f1e1ff */
/*00e0*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0008 */
/*00f0*/ IADD3.X R3, RZ, ~c[0x0][0x184], RZ, P1, !PT ; /* 0x80006100ff037a10 */
/* 0x000fe40000ffe4ff */
/*0100*/ IADD3.X R5, R5, -0x1, RZ, P0, !PT ; /* 0xffffffff05057810 */
/* 0x000fc600007fe4ff */
/*0110*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x180], R2 ; /* 0x0000600000027a25 */
/* 0x000fc800078e0002 */
/*0120*/ IMAD R5, R5, c[0x0][0x180], RZ ; /* 0x0000600005057a24 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD R7, R0, c[0x0][0x184], R5 ; /* 0x0000610000077a24 */
/* 0x000fc800078e0205 */
/*0140*/ IMAD.IADD R6, R3, 0x1, R7 ; /* 0x0000000103067824 */
/* 0x000fe400078e0207 */
/*0150*/ MOV R4, R11 ; /* 0x0000000b00047202 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, R12 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000c */
/*0170*/ IADD3 R9, P0, R11, R2, RZ ; /* 0x000000020b097210 */
/* 0x000fc60007f1e0ff */
/*0180*/ IMAD.WIDE.U32 R10, R0, c[0x0][0x180], R4 ; /* 0x00006000000a7a25 */
/* 0x000fc800078e0004 */
/*0190*/ IMAD.X R16, R12, 0x1, R6, P0 ; /* 0x000000010c107824 */
/* 0x000fe200000e0606 */
/*01a0*/ IADD3 R11, R7, R11, RZ ; /* 0x0000000b070b7210 */
/* 0x000fe40007ffe0ff */
/*01b0*/ LEA R14, P0, R10.reuse, c[0x0][0x160], 0x2 ; /* 0x000058000a0e7a11 */
/* 0x040fe400078010ff */
/*01c0*/ LEA R12, P1, R9.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800090c7a11 */
/* 0x040fe400078210ff */
/*01d0*/ LEA.HI.X R15, R10, c[0x0][0x164], R11, 0x2, P0 ; /* 0x000059000a0f7a11 */
/* 0x000fe400000f140b */
/*01e0*/ LEA.HI.X R13, R9, c[0x0][0x164], R16, 0x2, P1 ; /* 0x00005900090d7a11 */
/* 0x000fc800008f1410 */
/*01f0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1900 */
/*0210*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff097624 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0a7624 */
/* 0x000fe400078e00ff */
/*0230*/ IMAD.WIDE.U32 R4, R9, c[0x0][0x180], R4 ; /* 0x0000600009047a25 */
/* 0x000fc800078e0004 */
/*0240*/ IMAD R9, R9, c[0x0][0x184], RZ ; /* 0x0000610009097a24 */
/* 0x000fe200078e02ff */
/*0250*/ IADD3 R4, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc60007f3e0ff */
/*0260*/ IMAD R9, R10, c[0x0][0x17c], R9 ; /* 0x00005f000a097a24 */
/* 0x000fe200078e0209 */
/*0270*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fc80000000f00 */
/*0280*/ IADD3.X R5, R5, c[0x0][0x16c], R9, P1, !PT ; /* 0x00005b0005057a10 */
/* 0x000fe20000ffe409 */
/*0290*/ IMAD R11, R11, c[0x0][0xc], R8 ; /* 0x000003000b0b7a24 */
/* 0x000fc800078e0208 */
/*02a0*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000b */
/*02b0*/ FSETP.GTU.AND P0, PT, R15, R12, PT ; /* 0x0000000c0f00720b */
/* 0x004fc80003f0c000 */
/*02c0*/ SEL R9, RZ, 0x1, P0 ; /* 0x00000001ff097807 */
/* 0x000fe40000000000 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R11, c[0x0][0x180], PT ; /* 0x000060000b007a0c */
/* 0x000fe40003f06070 */
/*02e0*/ SHF.R.S32.HI R12, RZ, 0x1f, R11 ; /* 0x0000001fff0c7819 */
/* 0x000fe2000001140b */
/*02f0*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e6000c101104 */
/*0300*/ ISETP.GE.U32.AND.EX P0, PT, R12, c[0x0][0x184], PT, P0 ; /* 0x000061000c007a0c */
/* 0x000fda0003f06100 */
/*0310*/ @!P0 BRA 0x150 ; /* 0xfffffe3000008947 */
/* 0x001fea000383ffff */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3LEQPfPbmmm
.globl _Z3LEQPfPbmmm
.p2align 8
.type _Z3LEQPfPbmmm,@function
_Z3LEQPfPbmmm:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x20
s_add_u32 s10, s0, 40
s_addc_u32 s11, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_u64_e64 s[8:9], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s13, s4, -1
s_addc_u32 s14, s5, -1
s_mul_i32 s16, s13, s9
s_mul_hi_u32 s17, s13, s8
s_mul_i32 s14, s14, s8
s_add_i32 s17, s17, s16
s_mul_i32 s16, s13, s8
s_add_i32 s17, s17, s14
s_load_b32 s13, s[10:11], 0x0
s_lshl_b64 s[10:11], s[16:17], 2
s_mul_i32 s14, s8, s7
s_add_u32 s7, s0, s10
s_addc_u32 s10, s1, s11
s_add_u32 s4, s4, -2
s_addc_u32 s5, s5, -1
s_mul_i32 s11, s4, s9
s_mul_hi_u32 s16, s4, s8
s_mul_i32 s5, s5, s8
s_add_i32 s11, s16, s11
s_mul_i32 s4, s4, s8
s_add_i32 s5, s11, s5
s_mul_hi_u32 s11, s8, s6
s_lshl_b64 s[4:5], s[4:5], 2
s_mul_i32 s16, s9, s6
s_add_u32 s4, s0, s4
s_addc_u32 s1, s1, s5
s_add_i32 s0, s11, s14
s_mul_i32 s5, s8, s6
s_add_i32 s0, s0, s16
s_add_u32 s2, s2, s5
s_addc_u32 s3, s3, s0
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s13
s_mul_i32 s5, s13, s12
v_mad_u64_u32 v[3:4], null, s15, s12, v[0:1]
s_mov_b32 s6, 0
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s7, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v7, v[4:5], off
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v5, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_u64_e32 vcc_lo, s[8:9], v[3:4]
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_nc_u32_e32 v3, s5, v3
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_cmp_le_f32_e64 s0, v0, v7
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v0, 0, 1, s0
global_store_b8 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3LEQPfPbmmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3LEQPfPbmmm, .Lfunc_end0-_Z3LEQPfPbmmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3LEQPfPbmmm
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z3LEQPfPbmmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017cb07_00000000-6_LEQ.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3LEQPfPbmmmPfPbmmm
.type _Z27__device_stub__Z3LEQPfPbmmmPfPbmmm, @function
_Z27__device_stub__Z3LEQPfPbmmmPfPbmmm:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3LEQPfPbmmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3LEQPfPbmmmPfPbmmm, .-_Z27__device_stub__Z3LEQPfPbmmmPfPbmmm
.globl _Z3LEQPfPbmmm
.type _Z3LEQPfPbmmm, @function
_Z3LEQPfPbmmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3LEQPfPbmmmPfPbmmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3LEQPfPbmmm, .-_Z3LEQPfPbmmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3LEQPfPbmmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3LEQPfPbmmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "LEQ.hip"
.globl _Z18__device_stub__LEQPfPbmmm # -- Begin function _Z18__device_stub__LEQPfPbmmm
.p2align 4, 0x90
.type _Z18__device_stub__LEQPfPbmmm,@function
_Z18__device_stub__LEQPfPbmmm: # @_Z18__device_stub__LEQPfPbmmm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3LEQPfPbmmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z18__device_stub__LEQPfPbmmm, .Lfunc_end0-_Z18__device_stub__LEQPfPbmmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3LEQPfPbmmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3LEQPfPbmmm,@object # @_Z3LEQPfPbmmm
.section .rodata,"a",@progbits
.globl _Z3LEQPfPbmmm
.p2align 3, 0x0
_Z3LEQPfPbmmm:
.quad _Z18__device_stub__LEQPfPbmmm
.size _Z3LEQPfPbmmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3LEQPfPbmmm"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__LEQPfPbmmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3LEQPfPbmmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define TILE 32 // Thread block dimension
#define N 8192 // Side of the matrix
#define MATSIZE N * N // Total size of the matrix
#define MEMSIZE MATSIZE * sizeof(double) // Size of matrix in memory
// Generic function to be called for bandwidth testing on GPUs.
typedef void (*kernelFunc)(double *, double *, int);
/**
* @brief Performs an optimized version of a matrix transposition.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*
* By exploiting GPU shared memory we may decompose the transposition in
* multiple submatrices transpositions, minimizing global memory accesses
* by doing them simultaneously for same-tile threads.
*/
__global__ void transposeOptimized(double *a, double *b, int size)
{
__shared__ double tile[TILE][TILE];
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
tile[threadIdx.x][threadIdx.y] = a[row * size + col];
__syncthreads();
b[col * size + row] = tile[threadIdx.x][threadIdx.y];
}
/**
* @brief Performs a naive version of a matrix transposition on GPU.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*/
__global__ void transposeNaive(double *a, double *b, int size)
{
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
b[col * size + row] = a[row * size + col];
}
/**
* @brief Performs a serial version of a matrix transposition on CPU.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*/
void transposeCpu(double *a, double *b, int size)
{
for (int i = 0; i < size; ++i)
for (int j = 0; j < size; ++j)
b[j * size + i] = a[i * size + j];
}
/**
* @brief Validates the equality of two matrices in input.
* @param a Matrix a.
* @param b Matrix b.
* @param size The size of the matrix side.
*/
int isCorrect(double * a, double * b, int size)
{
for(int i = 0; i < size; ++i)
for(int j = 0; j < size; ++j)
if(b[i * size + j] != a[i * size + j])
return 0;
return 1;
}
/**
* @brief Tests execution time and bandwidth of a transposition kernel on a GPU.
* @param kernel The kernel to be tested.
* @param kernelName The name of the kernel to be tested.
* @param block_x The x-dimension of the block used to perform blocking for cache.
* @param block_y The y-dimension of the block used to perform blocking for cache.
*
* The transposition is performed as specified by the kernel function and then is
* validated against a correctly-transposed matrix. GPU time and bandwidth are
* provided as outputs of the function.
*/
int testCudaBandwidth(kernelFunc kernel, const char * kernelName, int block_x, int block_y)
{
double * h_in, * h_out;
double * dev_in, * dev_out;
double * cpu;
dim3 block(block_x, block_y);
dim3 grid(N / block.x, N / block.y);
h_in = (double *)malloc(MEMSIZE);
h_out = (double *)malloc(MEMSIZE);
cpu = (double *)malloc(MEMSIZE);
cudaMalloc((void **)&dev_in, MEMSIZE);
cudaMalloc((void **)&dev_out, MEMSIZE);
// Fill input matrix with some indices (for validating transposition).
for(int i = 0; i < MATSIZE; ++i)
h_in[i] = i;
// Initial setup of input matrix and timing events.
cudaMemcpy(dev_in, h_in, MEMSIZE, cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float exec_time = 0;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Print some informations about the current task.
printf("\nTransposing matrix on CPU for validation...\n");
transposeCpu(h_in, cpu, N);
printf("\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n", N, N, TILE, TILE, block_x, block_y);
printf("\nKernel: %s\n\n", kernelName);
// Time kernel execution.
cudaEventRecord(start);
kernel<<<grid, block>>>(dev_in, dev_out, N);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&exec_time, start, stop);
cudaMemcpy(h_out, dev_out, MEMSIZE, cudaMemcpyDeviceToHost);
printf("%s: %s\n", kernelName, isCorrect(h_out, cpu, N) ? "CORRECT" : "FAIL");
printf("GPU Time: %f\n", exec_time);
// Bandwidth given by reading and writing a matrix during exec_time,
// converted to GB/s for readability.
printf("Bandwidth (GB/s): %f\n", MEMSIZE * 2 / exec_time / 1000000);
printf("-------------------------------\n");
// Cleanup
free(h_in);
free(h_out);
free(cpu);
cudaFree(dev_in);
cudaFree(dev_out);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
}
int main(int argc, char *argv[])
{
testCudaBandwidth(&transposeNaive, "Naive Transpose", 32, 32);
int a[5] = {2, 4, 8, 16, 32};
for(int i = 0; i < 5; ++i)
for(int j = 0; j < 5; ++j)
testCudaBandwidth(&transposeOptimized, "Optimized Transpose", a[i], a[j]);
return 0;
} | code for sm_80
Function : _Z14transposeNaivePdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0060*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R2, R0, c[0x0][0x170], R5 ; /* 0x00005c0000027a24 */
/* 0x000fc800078e0205 */
/*00a0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*00e0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18transposeOptimizedPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff067435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0050*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0060*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0205 */
/*0080*/ IMAD R7, R7, c[0x0][0x4], R4 ; /* 0x0000010007077a24 */
/* 0x002fc800078e0204 */
/*0090*/ IMAD R2, R7, c[0x0][0x170], R0 ; /* 0x00005c0007027a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R2, R6, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0206 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ LEA R9, R5, R4, 0x5 ; /* 0x0000000405097211 */
/* 0x000fe200078e28ff */
/*00d0*/ IMAD R7, R0, c[0x0][0x170], R7 ; /* 0x00005c0000077a24 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fe200078e0206 */
/*00f0*/ STS.64 [R9.X8], R2 ; /* 0x0000000209007388 */
/* 0x004fe80000008a00 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ LDS.64 R4, [R9.X8] ; /* 0x0000000009047984 */
/* 0x000e280000008a00 */
/*0120*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define TILE 32 // Thread block dimension
#define N 8192 // Side of the matrix
#define MATSIZE N * N // Total size of the matrix
#define MEMSIZE MATSIZE * sizeof(double) // Size of matrix in memory
// Generic function to be called for bandwidth testing on GPUs.
typedef void (*kernelFunc)(double *, double *, int);
/**
* @brief Performs an optimized version of a matrix transposition.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*
* By exploiting GPU shared memory we may decompose the transposition in
* multiple submatrices transpositions, minimizing global memory accesses
* by doing them simultaneously for same-tile threads.
*/
__global__ void transposeOptimized(double *a, double *b, int size)
{
__shared__ double tile[TILE][TILE];
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
tile[threadIdx.x][threadIdx.y] = a[row * size + col];
__syncthreads();
b[col * size + row] = tile[threadIdx.x][threadIdx.y];
}
/**
* @brief Performs a naive version of a matrix transposition on GPU.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*/
__global__ void transposeNaive(double *a, double *b, int size)
{
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
b[col * size + row] = a[row * size + col];
}
/**
* @brief Performs a serial version of a matrix transposition on CPU.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*/
void transposeCpu(double *a, double *b, int size)
{
for (int i = 0; i < size; ++i)
for (int j = 0; j < size; ++j)
b[j * size + i] = a[i * size + j];
}
/**
* @brief Validates the equality of two matrices in input.
* @param a Matrix a.
* @param b Matrix b.
* @param size The size of the matrix side.
*/
int isCorrect(double * a, double * b, int size)
{
for(int i = 0; i < size; ++i)
for(int j = 0; j < size; ++j)
if(b[i * size + j] != a[i * size + j])
return 0;
return 1;
}
/**
* @brief Tests execution time and bandwidth of a transposition kernel on a GPU.
* @param kernel The kernel to be tested.
* @param kernelName The name of the kernel to be tested.
* @param block_x The x-dimension of the block used to perform blocking for cache.
* @param block_y The y-dimension of the block used to perform blocking for cache.
*
* The transposition is performed as specified by the kernel function and then is
* validated against a correctly-transposed matrix. GPU time and bandwidth are
* provided as outputs of the function.
*/
int testCudaBandwidth(kernelFunc kernel, const char * kernelName, int block_x, int block_y)
{
double * h_in, * h_out;
double * dev_in, * dev_out;
double * cpu;
dim3 block(block_x, block_y);
dim3 grid(N / block.x, N / block.y);
h_in = (double *)malloc(MEMSIZE);
h_out = (double *)malloc(MEMSIZE);
cpu = (double *)malloc(MEMSIZE);
cudaMalloc((void **)&dev_in, MEMSIZE);
cudaMalloc((void **)&dev_out, MEMSIZE);
// Fill input matrix with some indices (for validating transposition).
for(int i = 0; i < MATSIZE; ++i)
h_in[i] = i;
// Initial setup of input matrix and timing events.
cudaMemcpy(dev_in, h_in, MEMSIZE, cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float exec_time = 0;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Print some informations about the current task.
printf("\nTransposing matrix on CPU for validation...\n");
transposeCpu(h_in, cpu, N);
printf("\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n", N, N, TILE, TILE, block_x, block_y);
printf("\nKernel: %s\n\n", kernelName);
// Time kernel execution.
cudaEventRecord(start);
kernel<<<grid, block>>>(dev_in, dev_out, N);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&exec_time, start, stop);
cudaMemcpy(h_out, dev_out, MEMSIZE, cudaMemcpyDeviceToHost);
printf("%s: %s\n", kernelName, isCorrect(h_out, cpu, N) ? "CORRECT" : "FAIL");
printf("GPU Time: %f\n", exec_time);
// Bandwidth given by reading and writing a matrix during exec_time,
// converted to GB/s for readability.
printf("Bandwidth (GB/s): %f\n", MEMSIZE * 2 / exec_time / 1000000);
printf("-------------------------------\n");
// Cleanup
free(h_in);
free(h_out);
free(cpu);
cudaFree(dev_in);
cudaFree(dev_out);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
}
int main(int argc, char *argv[])
{
testCudaBandwidth(&transposeNaive, "Naive Transpose", 32, 32);
int a[5] = {2, 4, 8, 16, 32};
for(int i = 0; i < 5; ++i)
for(int j = 0; j < 5; ++j)
testCudaBandwidth(&transposeOptimized, "Optimized Transpose", a[i], a[j]);
return 0;
} | .file "tmpxft_00074943_00000000-6_ex6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12transposeCpuPdS_i
.type _Z12transposeCpuPdS_i, @function
_Z12transposeCpuPdS_i:
.LFB2057:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L3
movslq %edx, %r10
leaq 0(,%r10,8), %r8
addq %r8, %rdi
negq %r10
salq $3, %r10
movl $0, %r9d
.L5:
leaq (%rdi,%r10), %rax
movq %rsi, %rcx
.L6:
movsd (%rax), %xmm0
movsd %xmm0, (%rcx)
addq $8, %rax
addq %r8, %rcx
cmpq %rdi, %rax
jne .L6
addl $1, %r9d
addq $8, %rsi
addq %r8, %rdi
cmpl %r9d, %edx
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z12transposeCpuPdS_i, .-_Z12transposeCpuPdS_i
.globl _Z9isCorrectPdS_i
.type _Z9isCorrectPdS_i, @function
_Z9isCorrectPdS_i:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L13
movslq %edx, %rax
leaq 0(,%rax,8), %r10
negq %rax
leaq 0(,%rax,8), %r8
movq %r10, %rcx
movl $0, %r9d
.L10:
leaq (%rcx,%r8), %rax
.L12:
movsd (%rsi,%rax), %xmm0
ucomisd (%rdi,%rax), %xmm0
jp .L14
jne .L14
addq $8, %rax
cmpq %rcx, %rax
jne .L12
addl $1, %r9d
addq %r10, %rcx
cmpl %r9d, %edx
jne .L10
movl $1, %eax
ret
.L13:
movl $1, %eax
ret
.L14:
movl $0, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z9isCorrectPdS_i, .-_Z9isCorrectPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CORRECT"
.LC1:
.string "FAIL"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\nTransposing matrix on CPU for validation...\n"
.align 8
.LC4:
.string "\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n"
.section .rodata.str1.1
.LC5:
.string "\nKernel: %s\n\n"
.LC6:
.string "%s: %s\n"
.LC7:
.string "GPU Time: %f\n"
.LC10:
.string "Bandwidth (GB/s): %f\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "-------------------------------\n"
.text
.globl _Z17testCudaBandwidthPFvPdS_iEPKcii
.type _Z17testCudaBandwidthPFvPdS_iEPKcii, @function
_Z17testCudaBandwidthPFvPdS_iEPKcii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 8(%rsp)
movq %rsi, %r15
movl %edx, %r12d
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 72(%rsp)
movl $8192, %ecx
movl %ecx, %eax
movl $0, %edx
divl %r12d
movl %eax, 76(%rsp)
movl %ecx, %eax
movl $0, %edx
divl %ebp
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $536870912, %edi
call malloc@PLT
movq %rax, %rbx
movl $536870912, %edi
call malloc@PLT
movq %rax, %r14
movl $536870912, %edi
call malloc@PLT
movq %rax, %r13
leaq 32(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl $0, %eax
.L19:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $67108864, %rax
jne .L19
movl $1, %ecx
movl $536870912, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 28(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8192, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _Z12transposeCpuPdS_i
pushq %rbp
.cfi_def_cfa_offset 168
pushq %r12
.cfi_def_cfa_offset 176
movl $32, %r9d
movl $32, %r8d
movl $8192, %ecx
movl $8192, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq %r15, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %r12d, 64(%rsp)
movl %ebp, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L20
movl $8192, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
movq 8(%rsp), %rax
call *%rax
.L20:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $536870912, %edx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $8192, %edx
movq %r13, %rsi
movq %r14, %rdi
call _Z9isCorrectPdS_i
testl %eax, %eax
leaq .LC1(%rip), %rcx
leaq .LC0(%rip), %rax
cmovne %rax, %rcx
movq %r15, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC8(%rip), %xmm0
divss 28(%rsp), %xmm0
divss .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z17testCudaBandwidthPFvPdS_iEPKcii, .-_Z17testCudaBandwidthPFvPdS_iEPKcii
.section .rodata.str1.1
.LC12:
.string "Naive Transpose"
.LC13:
.string "Optimized Transpose"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $32, %ecx
movl $32, %edx
leaq .LC12(%rip), %rsi
leaq _Z14transposeNaivePdS_i(%rip), %rdi
call _Z17testCudaBandwidthPFvPdS_iEPKcii
movl $2, (%rsp)
movl $4, 4(%rsp)
movl $8, 8(%rsp)
movl $16, 12(%rsp)
movl $32, 16(%rsp)
movq %rsp, %r15
leaq 20(%rsp), %r12
movq %r15, %rbp
leaq .LC13(%rip), %r14
leaq _Z18transposeOptimizedPdS_i(%rip), %r13
.L28:
movq %r15, %rbx
.L29:
movl (%rbx), %ecx
movl 0(%rbp), %edx
movq %r14, %rsi
movq %r13, %rdi
call _Z17testCudaBandwidthPFvPdS_iEPKcii
addq $4, %rbx
cmpq %r12, %rbx
jne .L29
addq $4, %rbp
cmpq %r12, %rbp
jne .L28
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.globl _Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i
.type _Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i, @function
_Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18transposeOptimizedPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i, .-_Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i
.globl _Z18transposeOptimizedPdS_i
.type _Z18transposeOptimizedPdS_i, @function
_Z18transposeOptimizedPdS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z18transposeOptimizedPdS_i, .-_Z18transposeOptimizedPdS_i
.globl _Z37__device_stub__Z14transposeNaivePdS_iPdS_i
.type _Z37__device_stub__Z14transposeNaivePdS_iPdS_i, @function
_Z37__device_stub__Z14transposeNaivePdS_iPdS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14transposeNaivePdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z37__device_stub__Z14transposeNaivePdS_iPdS_i, .-_Z37__device_stub__Z14transposeNaivePdS_iPdS_i
.globl _Z14transposeNaivePdS_i
.type _Z14transposeNaivePdS_i, @function
_Z14transposeNaivePdS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14transposeNaivePdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z14transposeNaivePdS_i, .-_Z14transposeNaivePdS_i
.section .rodata.str1.1
.LC14:
.string "_Z14transposeNaivePdS_i"
.LC15:
.string "_Z18transposeOptimizedPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z14transposeNaivePdS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeOptimizedPdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1317011456
.align 4
.LC9:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define TILE 32 // Thread block dimension
#define N 8192 // Side of the matrix
#define MATSIZE N * N // Total size of the matrix
#define MEMSIZE MATSIZE * sizeof(double) // Size of matrix in memory
// Generic function to be called for bandwidth testing on GPUs.
typedef void (*kernelFunc)(double *, double *, int);
/**
* @brief Performs an optimized version of a matrix transposition.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*
* By exploiting GPU shared memory we may decompose the transposition in
* multiple submatrices transpositions, minimizing global memory accesses
* by doing them simultaneously for same-tile threads.
*/
__global__ void transposeOptimized(double *a, double *b, int size)
{
__shared__ double tile[TILE][TILE];
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
tile[threadIdx.x][threadIdx.y] = a[row * size + col];
__syncthreads();
b[col * size + row] = tile[threadIdx.x][threadIdx.y];
}
/**
* @brief Performs a naive version of a matrix transposition on GPU.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*/
__global__ void transposeNaive(double *a, double *b, int size)
{
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
b[col * size + row] = a[row * size + col];
}
/**
* @brief Performs a serial version of a matrix transposition on CPU.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*/
void transposeCpu(double *a, double *b, int size)
{
for (int i = 0; i < size; ++i)
for (int j = 0; j < size; ++j)
b[j * size + i] = a[i * size + j];
}
/**
* @brief Validates the equality of two matrices in input.
* @param a Matrix a.
* @param b Matrix b.
* @param size The size of the matrix side.
*/
int isCorrect(double * a, double * b, int size)
{
for(int i = 0; i < size; ++i)
for(int j = 0; j < size; ++j)
if(b[i * size + j] != a[i * size + j])
return 0;
return 1;
}
/**
* @brief Tests execution time and bandwidth of a transposition kernel on a GPU.
* @param kernel The kernel to be tested.
* @param kernelName The name of the kernel to be tested.
* @param block_x The x-dimension of the block used to perform blocking for cache.
* @param block_y The y-dimension of the block used to perform blocking for cache.
*
* The transposition is performed as specified by the kernel function and then is
* validated against a correctly-transposed matrix. GPU time and bandwidth are
* provided as outputs of the function.
*/
int testCudaBandwidth(kernelFunc kernel, const char * kernelName, int block_x, int block_y)
{
double * h_in, * h_out;
double * dev_in, * dev_out;
double * cpu;
dim3 block(block_x, block_y);
dim3 grid(N / block.x, N / block.y);
h_in = (double *)malloc(MEMSIZE);
h_out = (double *)malloc(MEMSIZE);
cpu = (double *)malloc(MEMSIZE);
cudaMalloc((void **)&dev_in, MEMSIZE);
cudaMalloc((void **)&dev_out, MEMSIZE);
// Fill input matrix with some indices (for validating transposition).
for(int i = 0; i < MATSIZE; ++i)
h_in[i] = i;
// Initial setup of input matrix and timing events.
cudaMemcpy(dev_in, h_in, MEMSIZE, cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float exec_time = 0;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Print some informations about the current task.
printf("\nTransposing matrix on CPU for validation...\n");
transposeCpu(h_in, cpu, N);
printf("\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n", N, N, TILE, TILE, block_x, block_y);
printf("\nKernel: %s\n\n", kernelName);
// Time kernel execution.
cudaEventRecord(start);
kernel<<<grid, block>>>(dev_in, dev_out, N);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&exec_time, start, stop);
cudaMemcpy(h_out, dev_out, MEMSIZE, cudaMemcpyDeviceToHost);
printf("%s: %s\n", kernelName, isCorrect(h_out, cpu, N) ? "CORRECT" : "FAIL");
printf("GPU Time: %f\n", exec_time);
// Bandwidth given by reading and writing a matrix during exec_time,
// converted to GB/s for readability.
printf("Bandwidth (GB/s): %f\n", MEMSIZE * 2 / exec_time / 1000000);
printf("-------------------------------\n");
// Cleanup
free(h_in);
free(h_out);
free(cpu);
cudaFree(dev_in);
cudaFree(dev_out);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
}
int main(int argc, char *argv[])
{
testCudaBandwidth(&transposeNaive, "Naive Transpose", 32, 32);
int a[5] = {2, 4, 8, 16, 32};
for(int i = 0; i < 5; ++i)
for(int j = 0; j < 5; ++j)
testCudaBandwidth(&transposeOptimized, "Optimized Transpose", a[i], a[j]);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE 32 // Thread block dimension
#define N 8192 // Side of the matrix
#define MATSIZE N * N // Total size of the matrix
#define MEMSIZE MATSIZE * sizeof(double) // Size of matrix in memory
// Generic function to be called for bandwidth testing on GPUs.
typedef void (*kernelFunc)(double *, double *, int);
/**
* @brief Performs an optimized version of a matrix transposition.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*
* By exploiting GPU shared memory we may decompose the transposition in
* multiple submatrices transpositions, minimizing global memory accesses
* by doing them simultaneously for same-tile threads.
*/
__global__ void transposeOptimized(double *a, double *b, int size)
{
__shared__ double tile[TILE][TILE];
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
tile[threadIdx.x][threadIdx.y] = a[row * size + col];
__syncthreads();
b[col * size + row] = tile[threadIdx.x][threadIdx.y];
}
/**
* @brief Performs a naive version of a matrix transposition on GPU.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*/
__global__ void transposeNaive(double *a, double *b, int size)
{
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
b[col * size + row] = a[row * size + col];
}
/**
* @brief Performs a serial version of a matrix transposition on CPU.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*/
void transposeCpu(double *a, double *b, int size)
{
for (int i = 0; i < size; ++i)
for (int j = 0; j < size; ++j)
b[j * size + i] = a[i * size + j];
}
/**
* @brief Validates the equality of two matrices in input.
* @param a Matrix a.
* @param b Matrix b.
* @param size The size of the matrix side.
*/
int isCorrect(double * a, double * b, int size)
{
for(int i = 0; i < size; ++i)
for(int j = 0; j < size; ++j)
if(b[i * size + j] != a[i * size + j])
return 0;
return 1;
}
/**
* @brief Tests execution time and bandwidth of a transposition kernel on a GPU.
* @param kernel The kernel to be tested.
* @param kernelName The name of the kernel to be tested.
* @param block_x The x-dimension of the block used to perform blocking for cache.
* @param block_y The y-dimension of the block used to perform blocking for cache.
*
* The transposition is performed as specified by the kernel function and then is
* validated against a correctly-transposed matrix. GPU time and bandwidth are
* provided as outputs of the function.
*/
int testCudaBandwidth(kernelFunc kernel, const char * kernelName, int block_x, int block_y)
{
double * h_in, * h_out;
double * dev_in, * dev_out;
double * cpu;
dim3 block(block_x, block_y);
dim3 grid(N / block.x, N / block.y);
h_in = (double *)malloc(MEMSIZE);
h_out = (double *)malloc(MEMSIZE);
cpu = (double *)malloc(MEMSIZE);
hipMalloc((void **)&dev_in, MEMSIZE);
hipMalloc((void **)&dev_out, MEMSIZE);
// Fill input matrix with some indices (for validating transposition).
for(int i = 0; i < MATSIZE; ++i)
h_in[i] = i;
// Initial setup of input matrix and timing events.
hipMemcpy(dev_in, h_in, MEMSIZE, hipMemcpyHostToDevice);
hipEvent_t start, stop;
float exec_time = 0;
hipEventCreate(&start);
hipEventCreate(&stop);
// Print some informations about the current task.
printf("\nTransposing matrix on CPU for validation...\n");
transposeCpu(h_in, cpu, N);
printf("\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n", N, N, TILE, TILE, block_x, block_y);
printf("\nKernel: %s\n\n", kernelName);
// Time kernel execution.
hipEventRecord(start);
kernel<<<grid, block>>>(dev_in, dev_out, N);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&exec_time, start, stop);
hipMemcpy(h_out, dev_out, MEMSIZE, hipMemcpyDeviceToHost);
printf("%s: %s\n", kernelName, isCorrect(h_out, cpu, N) ? "CORRECT" : "FAIL");
printf("GPU Time: %f\n", exec_time);
// Bandwidth given by reading and writing a matrix during exec_time,
// converted to GB/s for readability.
printf("Bandwidth (GB/s): %f\n", MEMSIZE * 2 / exec_time / 1000000);
printf("-------------------------------\n");
// Cleanup
free(h_in);
free(h_out);
free(cpu);
hipFree(dev_in);
hipFree(dev_out);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
}
int main(int argc, char *argv[])
{
testCudaBandwidth(&transposeNaive, "Naive Transpose", 32, 32);
int a[5] = {2, 4, 8, 16, 32};
for(int i = 0; i < 5; ++i)
for(int j = 0; j < 5; ++j)
testCudaBandwidth(&transposeOptimized, "Optimized Transpose", a[i], a[j]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE 32 // Thread block dimension
#define N 8192 // Side of the matrix
#define MATSIZE N * N // Total size of the matrix
#define MEMSIZE MATSIZE * sizeof(double) // Size of matrix in memory
// Generic function to be called for bandwidth testing on GPUs.
typedef void (*kernelFunc)(double *, double *, int);
/**
* @brief Performs an optimized version of a matrix transposition.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*
* By exploiting GPU shared memory we may decompose the transposition in
* multiple submatrices transpositions, minimizing global memory accesses
* by doing them simultaneously for same-tile threads.
*/
__global__ void transposeOptimized(double *a, double *b, int size)
{
__shared__ double tile[TILE][TILE];
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
tile[threadIdx.x][threadIdx.y] = a[row * size + col];
__syncthreads();
b[col * size + row] = tile[threadIdx.x][threadIdx.y];
}
/**
* @brief Performs a naive version of a matrix transposition on GPU.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*/
__global__ void transposeNaive(double *a, double *b, int size)
{
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
b[col * size + row] = a[row * size + col];
}
/**
* @brief Performs a serial version of a matrix transposition on CPU.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*/
void transposeCpu(double *a, double *b, int size)
{
for (int i = 0; i < size; ++i)
for (int j = 0; j < size; ++j)
b[j * size + i] = a[i * size + j];
}
/**
* @brief Validates the equality of two matrices in input.
* @param a Matrix a.
* @param b Matrix b.
* @param size The size of the matrix side.
*/
int isCorrect(double * a, double * b, int size)
{
for(int i = 0; i < size; ++i)
for(int j = 0; j < size; ++j)
if(b[i * size + j] != a[i * size + j])
return 0;
return 1;
}
/**
* @brief Tests execution time and bandwidth of a transposition kernel on a GPU.
* @param kernel The kernel to be tested.
* @param kernelName The name of the kernel to be tested.
* @param block_x The x-dimension of the block used to perform blocking for cache.
* @param block_y The y-dimension of the block used to perform blocking for cache.
*
* The transposition is performed as specified by the kernel function and then is
* validated against a correctly-transposed matrix. GPU time and bandwidth are
* provided as outputs of the function.
*/
int testCudaBandwidth(kernelFunc kernel, const char * kernelName, int block_x, int block_y)
{
double * h_in, * h_out;
double * dev_in, * dev_out;
double * cpu;
dim3 block(block_x, block_y);
dim3 grid(N / block.x, N / block.y);
h_in = (double *)malloc(MEMSIZE);
h_out = (double *)malloc(MEMSIZE);
cpu = (double *)malloc(MEMSIZE);
hipMalloc((void **)&dev_in, MEMSIZE);
hipMalloc((void **)&dev_out, MEMSIZE);
// Fill input matrix with some indices (for validating transposition).
for(int i = 0; i < MATSIZE; ++i)
h_in[i] = i;
// Initial setup of input matrix and timing events.
hipMemcpy(dev_in, h_in, MEMSIZE, hipMemcpyHostToDevice);
hipEvent_t start, stop;
float exec_time = 0;
hipEventCreate(&start);
hipEventCreate(&stop);
// Print some informations about the current task.
printf("\nTransposing matrix on CPU for validation...\n");
transposeCpu(h_in, cpu, N);
printf("\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n", N, N, TILE, TILE, block_x, block_y);
printf("\nKernel: %s\n\n", kernelName);
// Time kernel execution.
hipEventRecord(start);
kernel<<<grid, block>>>(dev_in, dev_out, N);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&exec_time, start, stop);
hipMemcpy(h_out, dev_out, MEMSIZE, hipMemcpyDeviceToHost);
printf("%s: %s\n", kernelName, isCorrect(h_out, cpu, N) ? "CORRECT" : "FAIL");
printf("GPU Time: %f\n", exec_time);
// Bandwidth given by reading and writing a matrix during exec_time,
// converted to GB/s for readability.
printf("Bandwidth (GB/s): %f\n", MEMSIZE * 2 / exec_time / 1000000);
printf("-------------------------------\n");
// Cleanup
free(h_in);
free(h_out);
free(cpu);
hipFree(dev_in);
hipFree(dev_out);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
}
int main(int argc, char *argv[])
{
testCudaBandwidth(&transposeNaive, "Naive Transpose", 32, 32);
int a[5] = {2, 4, 8, 16, 32};
for(int i = 0; i < 5; ++i)
for(int j = 0; j < 5; ++j)
testCudaBandwidth(&transposeOptimized, "Optimized Transpose", a[i], a[j]);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18transposeOptimizedPdS_i
.globl _Z18transposeOptimizedPdS_i
.p2align 8
.type _Z18transposeOptimizedPdS_i,@function
_Z18transposeOptimizedPdS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v6, v1, 8, v0
v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
ds_store_b64 v6, v[4:5]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b64 v[2:3], v6
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeOptimizedPdS_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18transposeOptimizedPdS_i, .Lfunc_end0-_Z18transposeOptimizedPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14transposeNaivePdS_i
.globl _Z14transposeNaivePdS_i
.p2align 8
.type _Z14transposeNaivePdS_i,@function
_Z14transposeNaivePdS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14transposeNaivePdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14transposeNaivePdS_i, .Lfunc_end1-_Z14transposeNaivePdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeOptimizedPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeOptimizedPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14transposeNaivePdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14transposeNaivePdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE 32 // Thread block dimension
#define N 8192 // Side of the matrix
#define MATSIZE N * N // Total size of the matrix
#define MEMSIZE MATSIZE * sizeof(double) // Size of matrix in memory
// Generic function to be called for bandwidth testing on GPUs.
typedef void (*kernelFunc)(double *, double *, int);
/**
* @brief Performs an optimized version of a matrix transposition.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*
* By exploiting GPU shared memory we may decompose the transposition in
* multiple submatrices transpositions, minimizing global memory accesses
* by doing them simultaneously for same-tile threads.
*/
__global__ void transposeOptimized(double *a, double *b, int size)
{
__shared__ double tile[TILE][TILE];
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
tile[threadIdx.x][threadIdx.y] = a[row * size + col];
__syncthreads();
b[col * size + row] = tile[threadIdx.x][threadIdx.y];
}
/**
* @brief Performs a naive version of a matrix transposition on GPU.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*/
__global__ void transposeNaive(double *a, double *b, int size)
{
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
b[col * size + row] = a[row * size + col];
}
/**
* @brief Performs a serial version of a matrix transposition on CPU.
* @param a The input matrix.
* @param b The transposed matrix in output.
* @param size The size of the matrix side.
*/
void transposeCpu(double *a, double *b, int size)
{
for (int i = 0; i < size; ++i)
for (int j = 0; j < size; ++j)
b[j * size + i] = a[i * size + j];
}
/**
* @brief Validates the equality of two matrices in input.
* @param a Matrix a.
* @param b Matrix b.
* @param size The size of the matrix side.
*/
int isCorrect(double * a, double * b, int size)
{
for(int i = 0; i < size; ++i)
for(int j = 0; j < size; ++j)
if(b[i * size + j] != a[i * size + j])
return 0;
return 1;
}
/**
* @brief Tests execution time and bandwidth of a transposition kernel on a GPU.
* @param kernel The kernel to be tested.
* @param kernelName The name of the kernel to be tested.
* @param block_x The x-dimension of the block used to perform blocking for cache.
* @param block_y The y-dimension of the block used to perform blocking for cache.
*
* The transposition is performed as specified by the kernel function and then is
* validated against a correctly-transposed matrix. GPU time and bandwidth are
* provided as outputs of the function.
*/
int testCudaBandwidth(kernelFunc kernel, const char * kernelName, int block_x, int block_y)
{
double * h_in, * h_out;
double * dev_in, * dev_out;
double * cpu;
dim3 block(block_x, block_y);
dim3 grid(N / block.x, N / block.y);
h_in = (double *)malloc(MEMSIZE);
h_out = (double *)malloc(MEMSIZE);
cpu = (double *)malloc(MEMSIZE);
hipMalloc((void **)&dev_in, MEMSIZE);
hipMalloc((void **)&dev_out, MEMSIZE);
// Fill input matrix with some indices (for validating transposition).
for(int i = 0; i < MATSIZE; ++i)
h_in[i] = i;
// Initial setup of input matrix and timing events.
hipMemcpy(dev_in, h_in, MEMSIZE, hipMemcpyHostToDevice);
hipEvent_t start, stop;
float exec_time = 0;
hipEventCreate(&start);
hipEventCreate(&stop);
// Print some informations about the current task.
printf("\nTransposing matrix on CPU for validation...\n");
transposeCpu(h_in, cpu, N);
printf("\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n", N, N, TILE, TILE, block_x, block_y);
printf("\nKernel: %s\n\n", kernelName);
// Time kernel execution.
hipEventRecord(start);
kernel<<<grid, block>>>(dev_in, dev_out, N);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&exec_time, start, stop);
hipMemcpy(h_out, dev_out, MEMSIZE, hipMemcpyDeviceToHost);
printf("%s: %s\n", kernelName, isCorrect(h_out, cpu, N) ? "CORRECT" : "FAIL");
printf("GPU Time: %f\n", exec_time);
// Bandwidth given by reading and writing a matrix during exec_time,
// converted to GB/s for readability.
printf("Bandwidth (GB/s): %f\n", MEMSIZE * 2 / exec_time / 1000000);
printf("-------------------------------\n");
// Cleanup
free(h_in);
free(h_out);
free(cpu);
hipFree(dev_in);
hipFree(dev_out);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
}
int main(int argc, char *argv[])
{
testCudaBandwidth(&transposeNaive, "Naive Transpose", 32, 32);
int a[5] = {2, 4, 8, 16, 32};
for(int i = 0; i < 5; ++i)
for(int j = 0; j < 5; ++j)
testCudaBandwidth(&transposeOptimized, "Optimized Transpose", a[i], a[j]);
return 0;
} | .text
.file "ex6.hip"
.globl _Z33__device_stub__transposeOptimizedPdS_i # -- Begin function _Z33__device_stub__transposeOptimizedPdS_i
.p2align 4, 0x90
.type _Z33__device_stub__transposeOptimizedPdS_i,@function
_Z33__device_stub__transposeOptimizedPdS_i: # @_Z33__device_stub__transposeOptimizedPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18transposeOptimizedPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__transposeOptimizedPdS_i, .Lfunc_end0-_Z33__device_stub__transposeOptimizedPdS_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__transposeNaivePdS_i # -- Begin function _Z29__device_stub__transposeNaivePdS_i
.p2align 4, 0x90
.type _Z29__device_stub__transposeNaivePdS_i,@function
_Z29__device_stub__transposeNaivePdS_i: # @_Z29__device_stub__transposeNaivePdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14transposeNaivePdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z29__device_stub__transposeNaivePdS_i, .Lfunc_end1-_Z29__device_stub__transposeNaivePdS_i
.cfi_endproc
# -- End function
.globl _Z12transposeCpuPdS_i # -- Begin function _Z12transposeCpuPdS_i
.p2align 4, 0x90
.type _Z12transposeCpuPdS_i,@function
_Z12transposeCpuPdS_i: # @_Z12transposeCpuPdS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %eax
leaq (,%rax,8), %rcx
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r8d, %r10d
leaq (%rdi,%r10,8), %r10
movq %rsi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r10,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r11)
incq %rbx
addq %rcx, %r11
cmpq %rbx, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r9
addl %edx, %r8d
addq $8, %rsi
cmpq %rax, %r9
jne .LBB2_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB2_6: # %._crit_edge17
retq
.Lfunc_end2:
.size _Z12transposeCpuPdS_i, .Lfunc_end2-_Z12transposeCpuPdS_i
.cfi_endproc
# -- End function
.globl _Z9isCorrectPdS_i # -- Begin function _Z9isCorrectPdS_i
.p2align 4, 0x90
.type _Z9isCorrectPdS_i,@function
_Z9isCorrectPdS_i: # @_Z9isCorrectPdS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
setle %al
jle .LBB3_9
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %ecx
leaq 8(%rsi), %rdx
leaq (,%rcx,8), %r8
leaq 8(%rdi), %r9
leaq -1(%rcx), %r10
xorl %r11d, %r11d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %.critedge
# in Loop: Header=BB3_2 Depth=1
incq %r11
cmpq %rcx, %r11
setae %al
addq %r8, %rdx
addq %r8, %r9
cmpq %rcx, %r11
je .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
movq %r11, %rbx
imulq %rcx, %rbx
movsd (%rsi,%rbx,8), %xmm0 # xmm0 = mem[0],zero
ucomisd (%rdi,%rbx,8), %xmm0
jne .LBB3_8
jp .LBB3_8
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB3_2 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_4: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rbx, %r10
je .LBB3_7
# %bb.5: # in Loop: Header=BB3_4 Depth=2
movsd (%rdx,%rbx,8), %xmm0 # xmm0 = mem[0],zero
leaq 1(%rbx), %r14
ucomisd (%r9,%rbx,8), %xmm0
movq %r14, %rbx
jne .LBB3_6
jnp .LBB3_4
.LBB3_6: # %._crit_edge39
# in Loop: Header=BB3_2 Depth=1
cmpq %rcx, %r14
jae .LBB3_7
.LBB3_8:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB3_9: # %._crit_edge
movzbl %al, %eax
andl $1, %eax
retq
.Lfunc_end3:
.size _Z9isCorrectPdS_i, .Lfunc_end3-_Z9isCorrectPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17testCudaBandwidthPFvPdS_iEPKcii
.LCPI4_0:
.long 0x4e800000 # float 1.07374182E+9
.LCPI4_1:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z17testCudaBandwidthPFvPdS_iEPKcii
.p2align 4, 0x90
.type _Z17testCudaBandwidthPFvPdS_iEPKcii,@function
_Z17testCudaBandwidthPFvPdS_iEPKcii: # @_Z17testCudaBandwidthPFvPdS_iEPKcii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r14d
movl %edx, %r12d
movq %rsi, 48(%rsp) # 8-byte Spill
movq %rdi, 64(%rsp) # 8-byte Spill
movl %edx, %eax
movq %r14, %rbp
shlq $32, %rbp
orq %rax, %rbp
xorl %r15d, %r15d
movl $8192, %eax # imm = 0x2000
xorl %edx, %edx
divl %ecx
movl %eax, %r13d
shlq $32, %r13
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %rbx
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
leaq 40(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq $67108864, %r15 # imm = 0x4000000
jne .LBB4_1
# %bb.2:
xorl %r15d, %r15d
movl $8192, %eax # imm = 0x2000
xorl %edx, %edx
divl %r12d
# kill: def $eax killed $eax def $rax
movq %rax, 72(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 12(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
movq 56(%rsp), %rax # 8-byte Reload
movq %rbx, %rcx
.p2align 4, 0x90
.LBB4_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movq %rax, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rcx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rdx)
incq %rsi
addq $65536, %rdx # imm = 0x10000
cmpq $8192, %rsi # imm = 0x2000
jne .LBB4_4
# %bb.5: # %._crit_edge.i
# in Loop: Header=BB4_3 Depth=1
incq %r15
addq $65536, %rcx # imm = 0x10000
addq $8, %rax
cmpq $8192, %r15 # imm = 0x2000
jne .LBB4_3
# %bb.6: # %_Z12transposeCpuPdS_i.exit
orq 72(%rsp), %r13 # 8-byte Folded Reload
movl %r14d, (%rsp)
movl $.L.str.1, %edi
movl $8192, %esi # imm = 0x2000
movl $8192, %edx # imm = 0x2000
movl $32, %ecx
movl $32, %r8d
movl %r12d, %r9d
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq 48(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 40(%rsp), %rdi
movq 32(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq 64(%rsp), %rax # 8-byte Reload
callq *(%rax)
.LBB4_8:
movq 16(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rsi
movl $536870912, %edx # imm = 0x20000000
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, %rax
addq $8, %rax
movq 56(%rsp), %r12 # 8-byte Reload
movq %r12, %rcx
addq $8, %rcx
xorl %esi, %esi
.LBB4_9: # %.preheader.i28
# =>This Loop Header: Depth=1
# Child Loop BB4_11 Depth 2
movq %r14, %rdx
shlq $16, %rdx
movsd (%r12,%rdx), %xmm0 # xmm0 = mem[0],zero
ucomisd (%r15,%rdx), %xmm0
jne .LBB4_14
jp .LBB4_14
# %bb.10: # %.lr.ph.preheader
# in Loop: Header=BB4_9 Depth=1
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_11: # %.lr.ph
# Parent Loop BB4_9 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $8191, %rdx # imm = 0x1FFF
je .LBB4_13
# %bb.12: # in Loop: Header=BB4_11 Depth=2
movsd (%rcx,%rdx,8), %xmm0 # xmm0 = mem[0],zero
ucomisd (%rax,%rdx,8), %xmm0
leaq 1(%rdx), %rdx
jne .LBB4_14
jnp .LBB4_11
jmp .LBB4_14
.p2align 4, 0x90
.LBB4_13: # %.critedge.i
# in Loop: Header=BB4_9 Depth=1
cmpq $8191, %r14 # imm = 0x1FFF
leaq 1(%r14), %rdx
setae %sil
addq $65536, %rax # imm = 0x10000
addq $65536, %rcx # imm = 0x10000
movq %rdx, %r14
cmpq $8192, %rdx # imm = 0x2000
jne .LBB4_9
.LBB4_14: # %_Z9isCorrectPdS_i.exit
movl $.L.str.4, %eax
movl $.L.str.5, %edx
testb $1, %sil
cmovneq %rax, %rdx
movl $.L.str.3, %edi
movq 48(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
callq printf
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 12(%rsp), %xmm0
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z17testCudaBandwidthPFvPdS_iEPKcii, .Lfunc_end4-_Z17testCudaBandwidthPFvPdS_iEPKcii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI5_0:
.long 2 # 0x2
.long 4 # 0x4
.long 8 # 0x8
.long 16 # 0x10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_Z14transposeNaivePdS_i, %edi
movl $.L.str.9, %esi
movl $32, %edx
movl $32, %ecx
callq _Z17testCudaBandwidthPFvPdS_iEPKcii
movaps .LCPI5_0(%rip), %xmm0 # xmm0 = [2,4,8,16]
movaps %xmm0, (%rsp)
movl $32, 16(%rsp)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
movl (%rsp,%r14,4), %ebx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsp,%r15,4), %ecx
movl $_Z18transposeOptimizedPdS_i, %edi
movl $.L.str.10, %esi
movl %ebx, %edx
callq _Z17testCudaBandwidthPFvPdS_iEPKcii
incq %r15
cmpq $5, %r15
jne .LBB5_2
# %bb.3: # in Loop: Header=BB5_1 Depth=1
incq %r14
cmpq $5, %r14
jne .LBB5_1
# %bb.4:
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeOptimizedPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14transposeNaivePdS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18transposeOptimizedPdS_i,@object # @_Z18transposeOptimizedPdS_i
.section .rodata,"a",@progbits
.globl _Z18transposeOptimizedPdS_i
.p2align 3, 0x0
_Z18transposeOptimizedPdS_i:
.quad _Z33__device_stub__transposeOptimizedPdS_i
.size _Z18transposeOptimizedPdS_i, 8
.type _Z14transposeNaivePdS_i,@object # @_Z14transposeNaivePdS_i
.globl _Z14transposeNaivePdS_i
.p2align 3, 0x0
_Z14transposeNaivePdS_i:
.quad _Z29__device_stub__transposeNaivePdS_i
.size _Z14transposeNaivePdS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n"
.size .L.str.1, 48
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nKernel: %s\n\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s: %s\n"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CORRECT"
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "FAIL"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU Time: %f\n"
.size .L.str.6, 14
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Bandwidth (GB/s): %f\n"
.size .L.str.7, 22
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Naive Transpose"
.size .L.str.9, 16
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Optimized Transpose"
.size .L.str.10, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18transposeOptimizedPdS_i"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14transposeNaivePdS_i"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nTransposing matrix on CPU for validation..."
.size .Lstr, 45
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "-------------------------------"
.size .Lstr.1, 32
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__transposeOptimizedPdS_i
.addrsig_sym _Z29__device_stub__transposeNaivePdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18transposeOptimizedPdS_i
.addrsig_sym _Z14transposeNaivePdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14transposeNaivePdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0060*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R2, R0, c[0x0][0x170], R5 ; /* 0x00005c0000027a24 */
/* 0x000fc800078e0205 */
/*00a0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0204 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0204 */
/*00e0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18transposeOptimizedPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff067435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0050*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0060*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0205 */
/*0080*/ IMAD R7, R7, c[0x0][0x4], R4 ; /* 0x0000010007077a24 */
/* 0x002fc800078e0204 */
/*0090*/ IMAD R2, R7, c[0x0][0x170], R0 ; /* 0x00005c0007027a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R2, R6, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0206 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ LEA R9, R5, R4, 0x5 ; /* 0x0000000405097211 */
/* 0x000fe200078e28ff */
/*00d0*/ IMAD R7, R0, c[0x0][0x170], R7 ; /* 0x00005c0000077a24 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fe200078e0206 */
/*00f0*/ STS.64 [R9.X8], R2 ; /* 0x0000000209007388 */
/* 0x004fe80000008a00 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ LDS.64 R4, [R9.X8] ; /* 0x0000000009047984 */
/* 0x000e280000008a00 */
/*0120*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18transposeOptimizedPdS_i
.globl _Z18transposeOptimizedPdS_i
.p2align 8
.type _Z18transposeOptimizedPdS_i,@function
_Z18transposeOptimizedPdS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v6, v1, 8, v0
v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
ds_store_b64 v6, v[4:5]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b64 v[2:3], v6
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeOptimizedPdS_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18transposeOptimizedPdS_i, .Lfunc_end0-_Z18transposeOptimizedPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14transposeNaivePdS_i
.globl _Z14transposeNaivePdS_i
.p2align 8
.type _Z14transposeNaivePdS_i,@function
_Z14transposeNaivePdS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_mad_u64_u32 v[4:5], null, v3, s4, v[2:3]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14transposeNaivePdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14transposeNaivePdS_i, .Lfunc_end1-_Z14transposeNaivePdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeOptimizedPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeOptimizedPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14transposeNaivePdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14transposeNaivePdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00074943_00000000-6_ex6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12transposeCpuPdS_i
.type _Z12transposeCpuPdS_i, @function
_Z12transposeCpuPdS_i:
.LFB2057:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L3
movslq %edx, %r10
leaq 0(,%r10,8), %r8
addq %r8, %rdi
negq %r10
salq $3, %r10
movl $0, %r9d
.L5:
leaq (%rdi,%r10), %rax
movq %rsi, %rcx
.L6:
movsd (%rax), %xmm0
movsd %xmm0, (%rcx)
addq $8, %rax
addq %r8, %rcx
cmpq %rdi, %rax
jne .L6
addl $1, %r9d
addq $8, %rsi
addq %r8, %rdi
cmpl %r9d, %edx
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z12transposeCpuPdS_i, .-_Z12transposeCpuPdS_i
.globl _Z9isCorrectPdS_i
.type _Z9isCorrectPdS_i, @function
_Z9isCorrectPdS_i:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L13
movslq %edx, %rax
leaq 0(,%rax,8), %r10
negq %rax
leaq 0(,%rax,8), %r8
movq %r10, %rcx
movl $0, %r9d
.L10:
leaq (%rcx,%r8), %rax
.L12:
movsd (%rsi,%rax), %xmm0
ucomisd (%rdi,%rax), %xmm0
jp .L14
jne .L14
addq $8, %rax
cmpq %rcx, %rax
jne .L12
addl $1, %r9d
addq %r10, %rcx
cmpl %r9d, %edx
jne .L10
movl $1, %eax
ret
.L13:
movl $1, %eax
ret
.L14:
movl $0, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z9isCorrectPdS_i, .-_Z9isCorrectPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CORRECT"
.LC1:
.string "FAIL"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\nTransposing matrix on CPU for validation...\n"
.align 8
.LC4:
.string "\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n"
.section .rodata.str1.1
.LC5:
.string "\nKernel: %s\n\n"
.LC6:
.string "%s: %s\n"
.LC7:
.string "GPU Time: %f\n"
.LC10:
.string "Bandwidth (GB/s): %f\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "-------------------------------\n"
.text
.globl _Z17testCudaBandwidthPFvPdS_iEPKcii
.type _Z17testCudaBandwidthPFvPdS_iEPKcii, @function
_Z17testCudaBandwidthPFvPdS_iEPKcii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 8(%rsp)
movq %rsi, %r15
movl %edx, %r12d
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 72(%rsp)
movl $8192, %ecx
movl %ecx, %eax
movl $0, %edx
divl %r12d
movl %eax, 76(%rsp)
movl %ecx, %eax
movl $0, %edx
divl %ebp
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $536870912, %edi
call malloc@PLT
movq %rax, %rbx
movl $536870912, %edi
call malloc@PLT
movq %rax, %r14
movl $536870912, %edi
call malloc@PLT
movq %rax, %r13
leaq 32(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl $0, %eax
.L19:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $67108864, %rax
jne .L19
movl $1, %ecx
movl $536870912, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0x00000000, 28(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8192, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _Z12transposeCpuPdS_i
pushq %rbp
.cfi_def_cfa_offset 168
pushq %r12
.cfi_def_cfa_offset 176
movl $32, %r9d
movl $32, %r8d
movl $8192, %ecx
movl $8192, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq %r15, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %r12d, 64(%rsp)
movl %ebp, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L20
movl $8192, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
movq 8(%rsp), %rax
call *%rax
.L20:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $536870912, %edx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $8192, %edx
movq %r13, %rsi
movq %r14, %rdi
call _Z9isCorrectPdS_i
testl %eax, %eax
leaq .LC1(%rip), %rcx
leaq .LC0(%rip), %rax
cmovne %rax, %rcx
movq %r15, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC8(%rip), %xmm0
divss 28(%rsp), %xmm0
divss .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z17testCudaBandwidthPFvPdS_iEPKcii, .-_Z17testCudaBandwidthPFvPdS_iEPKcii
.section .rodata.str1.1
.LC12:
.string "Naive Transpose"
.LC13:
.string "Optimized Transpose"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $32, %ecx
movl $32, %edx
leaq .LC12(%rip), %rsi
leaq _Z14transposeNaivePdS_i(%rip), %rdi
call _Z17testCudaBandwidthPFvPdS_iEPKcii
movl $2, (%rsp)
movl $4, 4(%rsp)
movl $8, 8(%rsp)
movl $16, 12(%rsp)
movl $32, 16(%rsp)
movq %rsp, %r15
leaq 20(%rsp), %r12
movq %r15, %rbp
leaq .LC13(%rip), %r14
leaq _Z18transposeOptimizedPdS_i(%rip), %r13
.L28:
movq %r15, %rbx
.L29:
movl (%rbx), %ecx
movl 0(%rbp), %edx
movq %r14, %rsi
movq %r13, %rdi
call _Z17testCudaBandwidthPFvPdS_iEPKcii
addq $4, %rbx
cmpq %r12, %rbx
jne .L29
addq $4, %rbp
cmpq %r12, %rbp
jne .L28
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.globl _Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i
.type _Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i, @function
_Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18transposeOptimizedPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i, .-_Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i
.globl _Z18transposeOptimizedPdS_i
.type _Z18transposeOptimizedPdS_i, @function
_Z18transposeOptimizedPdS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18transposeOptimizedPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z18transposeOptimizedPdS_i, .-_Z18transposeOptimizedPdS_i
.globl _Z37__device_stub__Z14transposeNaivePdS_iPdS_i
.type _Z37__device_stub__Z14transposeNaivePdS_iPdS_i, @function
_Z37__device_stub__Z14transposeNaivePdS_iPdS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14transposeNaivePdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z37__device_stub__Z14transposeNaivePdS_iPdS_i, .-_Z37__device_stub__Z14transposeNaivePdS_iPdS_i
.globl _Z14transposeNaivePdS_i
.type _Z14transposeNaivePdS_i, @function
_Z14transposeNaivePdS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14transposeNaivePdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z14transposeNaivePdS_i, .-_Z14transposeNaivePdS_i
.section .rodata.str1.1
.LC14:
.string "_Z14transposeNaivePdS_i"
.LC15:
.string "_Z18transposeOptimizedPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z14transposeNaivePdS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeOptimizedPdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1317011456
.align 4
.LC9:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ex6.hip"
.globl _Z33__device_stub__transposeOptimizedPdS_i # -- Begin function _Z33__device_stub__transposeOptimizedPdS_i
.p2align 4, 0x90
.type _Z33__device_stub__transposeOptimizedPdS_i,@function
_Z33__device_stub__transposeOptimizedPdS_i: # @_Z33__device_stub__transposeOptimizedPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18transposeOptimizedPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__transposeOptimizedPdS_i, .Lfunc_end0-_Z33__device_stub__transposeOptimizedPdS_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__transposeNaivePdS_i # -- Begin function _Z29__device_stub__transposeNaivePdS_i
.p2align 4, 0x90
.type _Z29__device_stub__transposeNaivePdS_i,@function
_Z29__device_stub__transposeNaivePdS_i: # @_Z29__device_stub__transposeNaivePdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14transposeNaivePdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z29__device_stub__transposeNaivePdS_i, .Lfunc_end1-_Z29__device_stub__transposeNaivePdS_i
.cfi_endproc
# -- End function
.globl _Z12transposeCpuPdS_i # -- Begin function _Z12transposeCpuPdS_i
.p2align 4, 0x90
.type _Z12transposeCpuPdS_i,@function
_Z12transposeCpuPdS_i: # @_Z12transposeCpuPdS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %eax
leaq (,%rax,8), %rcx
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r8d, %r10d
leaq (%rdi,%r10,8), %r10
movq %rsi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r10,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r11)
incq %rbx
addq %rcx, %r11
cmpq %rbx, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r9
addl %edx, %r8d
addq $8, %rsi
cmpq %rax, %r9
jne .LBB2_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB2_6: # %._crit_edge17
retq
.Lfunc_end2:
.size _Z12transposeCpuPdS_i, .Lfunc_end2-_Z12transposeCpuPdS_i
.cfi_endproc
# -- End function
.globl _Z9isCorrectPdS_i # -- Begin function _Z9isCorrectPdS_i
.p2align 4, 0x90
.type _Z9isCorrectPdS_i,@function
_Z9isCorrectPdS_i: # @_Z9isCorrectPdS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
setle %al
jle .LBB3_9
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %ecx
leaq 8(%rsi), %rdx
leaq (,%rcx,8), %r8
leaq 8(%rdi), %r9
leaq -1(%rcx), %r10
xorl %r11d, %r11d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %.critedge
# in Loop: Header=BB3_2 Depth=1
incq %r11
cmpq %rcx, %r11
setae %al
addq %r8, %rdx
addq %r8, %r9
cmpq %rcx, %r11
je .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
movq %r11, %rbx
imulq %rcx, %rbx
movsd (%rsi,%rbx,8), %xmm0 # xmm0 = mem[0],zero
ucomisd (%rdi,%rbx,8), %xmm0
jne .LBB3_8
jp .LBB3_8
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB3_2 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_4: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rbx, %r10
je .LBB3_7
# %bb.5: # in Loop: Header=BB3_4 Depth=2
movsd (%rdx,%rbx,8), %xmm0 # xmm0 = mem[0],zero
leaq 1(%rbx), %r14
ucomisd (%r9,%rbx,8), %xmm0
movq %r14, %rbx
jne .LBB3_6
jnp .LBB3_4
.LBB3_6: # %._crit_edge39
# in Loop: Header=BB3_2 Depth=1
cmpq %rcx, %r14
jae .LBB3_7
.LBB3_8:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB3_9: # %._crit_edge
movzbl %al, %eax
andl $1, %eax
retq
.Lfunc_end3:
.size _Z9isCorrectPdS_i, .Lfunc_end3-_Z9isCorrectPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17testCudaBandwidthPFvPdS_iEPKcii
.LCPI4_0:
.long 0x4e800000 # float 1.07374182E+9
.LCPI4_1:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z17testCudaBandwidthPFvPdS_iEPKcii
.p2align 4, 0x90
.type _Z17testCudaBandwidthPFvPdS_iEPKcii,@function
_Z17testCudaBandwidthPFvPdS_iEPKcii: # @_Z17testCudaBandwidthPFvPdS_iEPKcii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r14d
movl %edx, %r12d
movq %rsi, 48(%rsp) # 8-byte Spill
movq %rdi, 64(%rsp) # 8-byte Spill
movl %edx, %eax
movq %r14, %rbp
shlq $32, %rbp
orq %rax, %rbp
xorl %r15d, %r15d
movl $8192, %eax # imm = 0x2000
xorl %edx, %edx
divl %ecx
movl %eax, %r13d
shlq $32, %r13
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, %rbx
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movl $536870912, %edi # imm = 0x20000000
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
leaq 40(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq $67108864, %r15 # imm = 0x4000000
jne .LBB4_1
# %bb.2:
xorl %r15d, %r15d
movl $8192, %eax # imm = 0x2000
xorl %edx, %edx
divl %r12d
# kill: def $eax killed $eax def $rax
movq %rax, 72(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
movl $536870912, %edx # imm = 0x20000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $0, 12(%rsp)
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
movq 56(%rsp), %rax # 8-byte Reload
movq %rbx, %rcx
.p2align 4, 0x90
.LBB4_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movq %rax, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rcx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rdx)
incq %rsi
addq $65536, %rdx # imm = 0x10000
cmpq $8192, %rsi # imm = 0x2000
jne .LBB4_4
# %bb.5: # %._crit_edge.i
# in Loop: Header=BB4_3 Depth=1
incq %r15
addq $65536, %rcx # imm = 0x10000
addq $8, %rax
cmpq $8192, %r15 # imm = 0x2000
jne .LBB4_3
# %bb.6: # %_Z12transposeCpuPdS_i.exit
orq 72(%rsp), %r13 # 8-byte Folded Reload
movl %r14d, (%rsp)
movl $.L.str.1, %edi
movl $8192, %esi # imm = 0x2000
movl $8192, %edx # imm = 0x2000
movl $32, %ecx
movl $32, %r8d
movl %r12d, %r9d
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq 48(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 40(%rsp), %rdi
movq 32(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq 64(%rsp), %rax # 8-byte Reload
callq *(%rax)
.LBB4_8:
movq 16(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rsi
movl $536870912, %edx # imm = 0x20000000
movq 80(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r15, %rax
addq $8, %rax
movq 56(%rsp), %r12 # 8-byte Reload
movq %r12, %rcx
addq $8, %rcx
xorl %esi, %esi
.LBB4_9: # %.preheader.i28
# =>This Loop Header: Depth=1
# Child Loop BB4_11 Depth 2
movq %r14, %rdx
shlq $16, %rdx
movsd (%r12,%rdx), %xmm0 # xmm0 = mem[0],zero
ucomisd (%r15,%rdx), %xmm0
jne .LBB4_14
jp .LBB4_14
# %bb.10: # %.lr.ph.preheader
# in Loop: Header=BB4_9 Depth=1
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_11: # %.lr.ph
# Parent Loop BB4_9 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $8191, %rdx # imm = 0x1FFF
je .LBB4_13
# %bb.12: # in Loop: Header=BB4_11 Depth=2
movsd (%rcx,%rdx,8), %xmm0 # xmm0 = mem[0],zero
ucomisd (%rax,%rdx,8), %xmm0
leaq 1(%rdx), %rdx
jne .LBB4_14
jnp .LBB4_11
jmp .LBB4_14
.p2align 4, 0x90
.LBB4_13: # %.critedge.i
# in Loop: Header=BB4_9 Depth=1
cmpq $8191, %r14 # imm = 0x1FFF
leaq 1(%r14), %rdx
setae %sil
addq $65536, %rax # imm = 0x10000
addq $65536, %rcx # imm = 0x10000
movq %rdx, %r14
cmpq $8192, %rdx # imm = 0x2000
jne .LBB4_9
.LBB4_14: # %_Z9isCorrectPdS_i.exit
movl $.L.str.4, %eax
movl $.L.str.5, %edx
testb $1, %sil
cmovneq %rax, %rdx
movl $.L.str.3, %edi
movq 48(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
callq printf
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movss .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 12(%rsp), %xmm0
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z17testCudaBandwidthPFvPdS_iEPKcii, .Lfunc_end4-_Z17testCudaBandwidthPFvPdS_iEPKcii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI5_0:
.long 2 # 0x2
.long 4 # 0x4
.long 8 # 0x8
.long 16 # 0x10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_Z14transposeNaivePdS_i, %edi
movl $.L.str.9, %esi
movl $32, %edx
movl $32, %ecx
callq _Z17testCudaBandwidthPFvPdS_iEPKcii
movaps .LCPI5_0(%rip), %xmm0 # xmm0 = [2,4,8,16]
movaps %xmm0, (%rsp)
movl $32, 16(%rsp)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
movl (%rsp,%r14,4), %ebx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsp,%r15,4), %ecx
movl $_Z18transposeOptimizedPdS_i, %edi
movl $.L.str.10, %esi
movl %ebx, %edx
callq _Z17testCudaBandwidthPFvPdS_iEPKcii
incq %r15
cmpq $5, %r15
jne .LBB5_2
# %bb.3: # in Loop: Header=BB5_1 Depth=1
incq %r14
cmpq $5, %r14
jne .LBB5_1
# %bb.4:
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeOptimizedPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14transposeNaivePdS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18transposeOptimizedPdS_i,@object # @_Z18transposeOptimizedPdS_i
.section .rodata,"a",@progbits
.globl _Z18transposeOptimizedPdS_i
.p2align 3, 0x0
_Z18transposeOptimizedPdS_i:
.quad _Z33__device_stub__transposeOptimizedPdS_i
.size _Z18transposeOptimizedPdS_i, 8
.type _Z14transposeNaivePdS_i,@object # @_Z14transposeNaivePdS_i
.globl _Z14transposeNaivePdS_i
.p2align 3, 0x0
_Z14transposeNaivePdS_i:
.quad _Z29__device_stub__transposeNaivePdS_i
.size _Z14transposeNaivePdS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\nMatrix size: %dx%d, tile: %dx%d, block:%dx%d \n"
.size .L.str.1, 48
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nKernel: %s\n\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s: %s\n"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CORRECT"
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "FAIL"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU Time: %f\n"
.size .L.str.6, 14
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Bandwidth (GB/s): %f\n"
.size .L.str.7, 22
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Naive Transpose"
.size .L.str.9, 16
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Optimized Transpose"
.size .L.str.10, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18transposeOptimizedPdS_i"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14transposeNaivePdS_i"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nTransposing matrix on CPU for validation..."
.size .Lstr, 45
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "-------------------------------"
.size .Lstr.1, 32
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__transposeOptimizedPdS_i
.addrsig_sym _Z29__device_stub__transposeNaivePdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18transposeOptimizedPdS_i
.addrsig_sym _Z14transposeNaivePdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2013/2014, March 3 - April 4
// ###
// ###
// ### Evgeny Strekalovskiy, Maria Klodt, Jan Stuehmer, Mohamed Souiai
// ###
// ###
// ### Shiv, painkiller047@gmail.com, p053
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
// adds elements at a particular index (i) of all input arrays
__device__ float add_elements_at(size_t i, float ** d_in_arrays, int noOfInArrays) {
float sum = 0;
// sum all arrays
for (int arrNo = 0; arrNo < noOfInArrays; arrNo++) {
sum += d_in_arrays[arrNo][i];
}
// return result
return sum;
}
// add arrays - given to be summed arrays as arrays or arrays, out array, size of each array (n), no of arrays to be summed
__global__ void add_arrays(float ** d_in_arrays, float * d_out_array, int n, int noOfInArrays) {
// get thread id
int id = threadIdx.x + blockDim.x * blockIdx.x;
// only threads inside array range compute
if(id < n) {
d_out_array[id] = add_elements_at(id, d_in_arrays, noOfInArrays);
}
}
// GPU allocs, mem copy and calls add arrays kernel
void add_arrays_caller(float * h_AoA[], int n, int noOfInArrays) {
// define block and grid sizes - 1D assumed
// setting a block of 512 threads
dim3 block = dim3(512, 1, 1);
dim3 grid = dim3((n + block.x - 1) / block.x, 1, 1);
// alloc GPU memory for all arrays be added and copy those arrays
float * arraysOnGPU[noOfInArrays];
int bytesPerArray = n * sizeof(float);
for(int i = 0; i < noOfInArrays; i++) {
cudaMalloc((void **) &arraysOnGPU[i], bytesPerArray);
CUDA_CHECK;
cudaMemcpy(arraysOnGPU[i], h_AoA[i], bytesPerArray, cudaMemcpyHostToDevice);
CUDA_CHECK;
}
// GPU memory that contains the above allocation addresses to the in arrays on GPU
float ** d_in_arrays;
cudaMalloc((void ***) &d_in_arrays, sizeof(float *) * noOfInArrays);
CUDA_CHECK;
cudaMemcpy(d_in_arrays, arraysOnGPU, sizeof(float *) * noOfInArrays, cudaMemcpyHostToDevice);
CUDA_CHECK;
// allocate GPU memory for output array
float * d_out_array;
cudaMalloc((void **) &d_out_array, sizeof(float) * bytesPerArray);
CUDA_CHECK;
// call kernel
add_arrays<<<grid, block>>>(d_in_arrays, d_out_array, n, noOfInArrays);
// wait for kernel call to finish
cudaDeviceSynchronize();
CUDA_CHECK;
// copy summed data in output array in GPU back to host
cudaMemcpy(h_AoA[noOfInArrays], d_out_array, bytesPerArray, cudaMemcpyDeviceToHost);
CUDA_CHECK;
// free GPU memory - for both in and out arrays
for(int i = 0; i < noOfInArrays; i++) {
cudaFree(arraysOnGPU[i]);
CUDA_CHECK;
}
cudaFree(d_out_array);
CUDA_CHECK;
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 20;
int NO_IN_ARRAYS = 2;
float *a = new float[n];
float *b = new float[n];
float *c = new float[n];
for(int i=0; i<n; i++)
{
a[i] = i;
b[i] = (i%5)+1;
c[i] = 0;
}
// CPU computation
for(int i=0; i<n; i++) c[i] = a[i] + b[i];
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// init c
for(int i=0; i<n; i++) c[i] = 0;
// GPU computation
// ###
// ### TODO: Implement the array addition on the GPU, store the result in "c"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "aux.h"
// following convention
// total arrays including result array
float * h_AoA[] = {a, b, c};
// kernel caller
add_arrays_caller(h_AoA, n, NO_IN_ARRAYS);
// print result
cout << "GPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
delete[] b;
delete[] c;
} | code for sm_80
Function : _Z10add_arraysPPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff047624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0080*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*00a0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00b0*/ @!P0 BRA 0xd20 ; /* 0x00000c6000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0110*/ @!P0 BRA 0xc00 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R8, -R4, c[0x0][0x174], RZ ; /* 0x00005d0004087a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0140*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0150*/ SHF.L.U64.HI R6, R0.reuse, 0x2, R3 ; /* 0x0000000200067819 */
/* 0x040fe20000010203 */
/*0160*/ IMAD.SHL.U32 R7, R0, 0x4, RZ ; /* 0x0000000400077824 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0180*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0c7624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0d7624 */
/* 0x000fd400078e00ff */
/*01a0*/ @!P0 BRA 0xa60 ; /* 0x000008b000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x750 ; /* 0x0000057000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ LDG.E.64 R10, [R12.64] ; /* 0x000000080c0a7981 */
/* 0x000ea8000c1e1b00 */
/*0200*/ LDG.E.64 R24, [R12.64+0x8] ; /* 0x000008080c187981 */
/* 0x000ee8000c1e1b00 */
/*0210*/ LDG.E.64 R22, [R12.64+0x10] ; /* 0x000010080c167981 */
/* 0x000f28000c1e1b00 */
/*0220*/ LDG.E.64 R20, [R12.64+0x18] ; /* 0x000018080c147981 */
/* 0x000f68000c1e1b00 */
/*0230*/ LDG.E.64 R14, [R12.64+0x28] ; /* 0x000028080c0e7981 */
/* 0x000f28000c1e1b00 */
/*0240*/ LDG.E.64 R18, [R12.64+0x30] ; /* 0x000030080c127981 */
/* 0x000f68000c1e1b00 */
/*0250*/ LDG.E.64 R16, [R12.64+0x38] ; /* 0x000038080c107981 */
/* 0x000f62000c1e1b00 */
/*0260*/ IADD3 R26, P1, R10, R7, RZ ; /* 0x000000070a1a7210 */
/* 0x004fca0007f3e0ff */
/*0270*/ IMAD.X R27, R11, 0x1, R6, P1 ; /* 0x000000010b1b7824 */
/* 0x000fe400008e0606 */
/*0280*/ LDG.E.64 R10, [R12.64+0x20] ; /* 0x000020080c0a7981 */
/* 0x000ea8000c1e1b00 */
/*0290*/ LDG.E R26, [R26.64] ; /* 0x000000081a1a7981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IADD3 R28, P1, R24, R7, RZ ; /* 0x00000007181c7210 */
/* 0x008fca0007f3e0ff */
/*02b0*/ IMAD.X R29, R25, 0x1, R6, P1 ; /* 0x00000001191d7824 */
/* 0x000fe200008e0606 */
/*02c0*/ IADD3 R24, P1, R22, R7, RZ ; /* 0x0000000716187210 */
/* 0x010fc80007f3e0ff */
/*02d0*/ IADD3.X R25, R23, R6, RZ, P1, !PT ; /* 0x0000000617197210 */
/* 0x000fe20000ffe4ff */
/*02e0*/ LDG.E R2, [R28.64] ; /* 0x000000081c027981 */
/* 0x0000e2000c1e1900 */
/*02f0*/ IADD3 R20, P1, R20, R7, RZ ; /* 0x0000000714147210 */
/* 0x020fc60007f3e0ff */
/*0300*/ LDG.E R24, [R24.64] ; /* 0x0000000818187981 */
/* 0x000324000c1e1900 */
/*0310*/ IMAD.X R21, R21, 0x1, R6, P1 ; /* 0x0000000115157824 */
/* 0x000fe200008e0606 */
/*0320*/ IADD3 R14, P1, R14, R7, RZ ; /* 0x000000070e0e7210 */
/* 0x000fc80007f3e0ff */
/*0330*/ LDG.E R23, [R20.64] ; /* 0x0000000814177981 */
/* 0x000ae2000c1e1900 */
/*0340*/ IMAD.X R15, R15, 0x1, R6, P1 ; /* 0x000000010f0f7824 */
/* 0x000fe200008e0606 */
/*0350*/ IADD3 R28, P1, R18, R7, RZ ; /* 0x00000007121c7210 */
/* 0x001fc80007f3e0ff */
/*0360*/ LDG.E R21, [R14.64] ; /* 0x000000080e157981 */
/* 0x020162000c1e1900 */
/*0370*/ IMAD.X R29, R19, 0x1, R6, P1 ; /* 0x00000001131d7824 */
/* 0x000fca00008e0606 */
/*0380*/ LDG.E R20, [R28.64] ; /* 0x000000081c147981 */
/* 0x0002e8000c1e1900 */
/*0390*/ LDG.E.64 R14, [R12.64+0x58] ; /* 0x000058080c0e7981 */
/* 0x001e62000c1e1b00 */
/*03a0*/ IADD3 R10, P2, R10, R7, RZ ; /* 0x000000070a0a7210 */
/* 0x004fe20007f5e0ff */
/*03b0*/ FADD R5, R26, R5 ; /* 0x000000051a057221 */
/* 0x000fc80000000000 */
/*03c0*/ IMAD.X R11, R11, 0x1, R6, P2 ; /* 0x000000010b0b7824 */
/* 0x000fe200010e0606 */
/*03d0*/ LDG.E.64 R26, [R12.64+0x40] ; /* 0x000040080c1a7981 */
/* 0x000ea2000c1e1b00 */
/*03e0*/ IADD3 R18, P2, R16, R7, RZ ; /* 0x0000000710127210 */
/* 0x000fc60007f5e0ff */
/*03f0*/ LDG.E R22, [R10.64] ; /* 0x000000080a167981 */
/* 0x0000e2000c1e1900 */
/*0400*/ IADD3.X R19, R17, R6, RZ, P2, !PT ; /* 0x0000000611137210 */
/* 0x000fc600017fe4ff */
/*0410*/ LDG.E.64 R16, [R12.64+0x50] ; /* 0x000050080c107981 */
/* 0x000ee8000c1e1b00 */
/*0420*/ LDG.E R19, [R18.64] ; /* 0x0000000812137981 */
/* 0x0002e8000c1e1900 */
/*0430*/ LDG.E.64 R10, [R12.64+0x48] ; /* 0x000048080c0a7981 */
/* 0x001ee2000c1e1b00 */
/*0440*/ IADD3 R28, P2, R14, R7, RZ ; /* 0x000000070e1c7210 */
/* 0x002fca0007f5e0ff */
/*0450*/ IMAD.X R29, R15, 0x1, R6, P2 ; /* 0x000000010f1d7824 */
/* 0x000fe400010e0606 */
/*0460*/ LDG.E.64 R14, [R12.64+0x68] ; /* 0x000068080c0e7981 */
/* 0x000f28000c1e1b00 */
/*0470*/ LDG.E R9, [R28.64] ; /* 0x000000081c097981 */
/* 0x000162000c1e1900 */
/*0480*/ IADD3 R26, P1, R26, R7, RZ ; /* 0x000000071a1a7210 */
/* 0x004fca0007f3e0ff */
/*0490*/ IMAD.X R27, R27, 0x1, R6, P1 ; /* 0x000000011b1b7824 */
/* 0x000fca00008e0606 */
/*04a0*/ LDG.E R18, [R26.64] ; /* 0x000000081a127981 */
/* 0x0002a2000c1e1900 */
/*04b0*/ IADD3 R10, P1, R10, R7, RZ ; /* 0x000000070a0a7210 */
/* 0x008fca0007f3e0ff */
/*04c0*/ IMAD.X R11, R11, 0x1, R6, P1 ; /* 0x000000010b0b7824 */
/* 0x000fe200008e0606 */
/*04d0*/ IADD3 R26, P1, R16, R7, RZ ; /* 0x00000007101a7210 */
/* 0x002fca0007f3e0ff */
/*04e0*/ IMAD.X R27, R17, 0x1, R6, P1 ; /* 0x00000001111b7824 */
/* 0x000fe200008e0606 */
/*04f0*/ LDG.E R11, [R10.64] ; /* 0x000000080a0b7981 */
/* 0x0002e8000c1e1900 */
/*0500*/ LDG.E.64 R16, [R12.64+0x60] ; /* 0x000060080c107981 */
/* 0x000e28000c1e1b00 */
/*0510*/ LDG.E R10, [R26.64] ; /* 0x000000081a0a7981 */
/* 0x0028a4000c1e1900 */
/*0520*/ IADD3 R26, P2, R14, R7, RZ ; /* 0x000000070e1a7210 */
/* 0x010fca0007f5e0ff */
/*0530*/ IMAD.X R27, R15, 0x1, R6, P2 ; /* 0x000000010f1b7824 */
/* 0x000fe400010e0606 */
/*0540*/ LDG.E.64 R14, [R12.64+0x70] ; /* 0x000070080c0e7981 */
/* 0x000f28000c1e1b00 */
/*0550*/ LDG.E R26, [R26.64] ; /* 0x000000081a1a7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IADD3 R28, P1, R16, R7, RZ ; /* 0x00000007101c7210 */
/* 0x001fc80007f3e0ff */
/*0570*/ IADD3.X R29, R17, R6, RZ, P1, !PT ; /* 0x00000006111d7210 */
/* 0x000fe40000ffe4ff */
/*0580*/ LDG.E.64 R16, [R12.64+0x78] ; /* 0x000078080c107981 */
/* 0x000ea8000c1e1b00 */
/*0590*/ LDG.E R25, [R28.64] ; /* 0x000000081c197981 */
/* 0x000ee2000c1e1900 */
/*05a0*/ IADD3 R14, P1, R14, R7, RZ ; /* 0x000000070e0e7210 */
/* 0x010fca0007f3e0ff */
/*05b0*/ IMAD.X R15, R15, 0x1, R6, P1 ; /* 0x000000010f0f7824 */
/* 0x000fca00008e0606 */
/*05c0*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000f22000c1e1900 */
/*05d0*/ FADD R5, R5, R2 ; /* 0x0000000205057221 */
/* 0x000fc80000000000 */
/*05e0*/ FADD R24, R5, R24 ; /* 0x0000001805187221 */
/* 0x000fc80000000000 */
/*05f0*/ FADD R23, R24, R23 ; /* 0x0000001718177221 */
/* 0x000fe20000000000 */
/*0600*/ IADD3 R16, P1, R16, R7, RZ ; /* 0x0000000710107210 */
/* 0x004fca0007f3e0ff */
/*0610*/ IMAD.X R17, R17, 0x1, R6, P1 ; /* 0x0000000111117824 */
/* 0x000fca00008e0606 */
/*0620*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000ea2000c1e1900 */
/*0630*/ FADD R22, R23, R22 ; /* 0x0000001617167221 */
/* 0x000fc80000000000 */
/*0640*/ FADD R21, R22, R21 ; /* 0x0000001516157221 */
/* 0x020fc80000000000 */
/*0650*/ FADD R20, R21, R20 ; /* 0x0000001415147221 */
/* 0x000fc80000000000 */
/*0660*/ FADD R19, R20, R19 ; /* 0x0000001314137221 */
/* 0x000fc80000000000 */
/*0670*/ FADD R18, R19, R18 ; /* 0x0000001213127221 */
/* 0x000fc80000000000 */
/*0680*/ FADD R11, R18, R11 ; /* 0x0000000b120b7221 */
/* 0x008fe20000000000 */
/*0690*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*06a0*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x000fe20000000000 */
/*06b0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*06c0*/ FADD R10, R10, R9 ; /* 0x000000090a0a7221 */
/* 0x000fc80000000000 */
/*06d0*/ FADD R25, R10, R25 ; /* 0x000000190a197221 */
/* 0x000fe20000000000 */
/*06e0*/ IADD3 R12, P2, R12, 0x80, RZ ; /* 0x000000800c0c7810 */
/* 0x000fc60007f5e0ff */
/*06f0*/ FADD R25, R25, R26 ; /* 0x0000001a19197221 */
/* 0x000fe20000000000 */
/*0700*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc6000fffe03f */
/*0710*/ FADD R25, R25, R14 ; /* 0x0000000e19197221 */
/* 0x010fe40000000000 */
/*0720*/ IMAD.X R13, RZ, RZ, R13, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe400010e060d */
/*0730*/ FADD R5, R25, R16 ; /* 0x0000001019057221 */
/* 0x004fe20000000000 */
/*0740*/ @P1 BRA 0x1f0 ; /* 0xfffffaa000001947 */
/* 0x000fea000383ffff */
/*0750*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0760*/ @!P1 BRA 0xa40 ; /* 0x000002d000009947 */
/* 0x000fea0003800000 */
/*0770*/ LDG.E.64 R26, [R12.64] ; /* 0x000000080c1a7981 */
/* 0x000ea8000c1e1b00 */
/*0780*/ LDG.E.64 R18, [R12.64+0x8] ; /* 0x000008080c127981 */
/* 0x000ee8000c1e1b00 */
/*0790*/ LDG.E.64 R20, [R12.64+0x10] ; /* 0x000010080c147981 */
/* 0x000f28000c1e1b00 */
/*07a0*/ LDG.E.64 R22, [R12.64+0x18] ; /* 0x000018080c167981 */
/* 0x000f68000c1e1b00 */
/*07b0*/ LDG.E.64 R24, [R12.64+0x20] ; /* 0x000020080c187981 */
/* 0x000f68000c1e1b00 */
/*07c0*/ LDG.E.64 R10, [R12.64+0x28] ; /* 0x000028080c0a7981 */
/* 0x000f68000c1e1b00 */
/*07d0*/ LDG.E.64 R14, [R12.64+0x30] ; /* 0x000030080c0e7981 */
/* 0x000f68000c1e1b00 */
/*07e0*/ LDG.E.64 R16, [R12.64+0x38] ; /* 0x000038080c107981 */
/* 0x000f62000c1e1b00 */
/*07f0*/ IADD3 R26, P0, R26, R7, RZ ; /* 0x000000071a1a7210 */
/* 0x004fc80007f1e0ff */
/*0800*/ IADD3.X R27, R27, R6, RZ, P0, !PT ; /* 0x000000061b1b7210 */
/* 0x000fe400007fe4ff */
/*0810*/ IADD3 R18, P0, R18, R7, RZ ; /* 0x0000000712127210 */
/* 0x008fc60007f1e0ff */
/*0820*/ LDG.E R2, [R26.64] ; /* 0x000000081a027981 */
/* 0x000ea4000c1e1900 */
/*0830*/ IMAD.X R19, R19, 0x1, R6, P0 ; /* 0x0000000113137824 */
/* 0x000fe200000e0606 */
/*0840*/ IADD3 R20, P0, R20, R7, RZ ; /* 0x0000000714147210 */
/* 0x010fc80007f1e0ff */
/*0850*/ LDG.E R18, [R18.64] ; /* 0x0000000812127981 */
/* 0x000ee2000c1e1900 */
/*0860*/ IMAD.X R21, R21, 0x1, R6, P0 ; /* 0x0000000115157824 */
/* 0x000fe200000e0606 */
/*0870*/ IADD3 R22, P0, R22, R7, RZ ; /* 0x0000000716167210 */
/* 0x020fc80007f1e0ff */
/*0880*/ LDG.E R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000f22000c1e1900 */
/*0890*/ IMAD.X R23, R23, 0x1, R6.reuse, P0 ; /* 0x0000000117177824 */
/* 0x100fe200000e0606 */
/*08a0*/ IADD3 R24, P0, R24, R7.reuse, RZ ; /* 0x0000000718187210 */
/* 0x080fe40007f1e0ff */
/*08b0*/ IADD3 R10, P1, R10, R7.reuse, RZ ; /* 0x000000070a0a7210 */
/* 0x080fe40007f3e0ff */
/*08c0*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000f62000c1e1900 */
/*08d0*/ IMAD.X R25, R25, 0x1, R6, P0 ; /* 0x0000000119197824 */
/* 0x000fe200000e0606 */
/*08e0*/ IADD3 R14, P0, R14, R7, RZ ; /* 0x000000070e0e7210 */
/* 0x000fe40007f1e0ff */
/*08f0*/ IADD3.X R11, R11, R6, RZ, P1, !PT ; /* 0x000000060b0b7210 */
/* 0x000fc40000ffe4ff */
/*0900*/ LDG.E R24, [R24.64] ; /* 0x0000000818187981 */
/* 0x000f62000c1e1900 */
/*0910*/ IMAD.X R15, R15, 0x1, R6.reuse, P0 ; /* 0x000000010f0f7824 */
/* 0x100fe200000e0606 */
/*0920*/ IADD3 R16, P0, R16, R7, RZ ; /* 0x0000000710107210 */
/* 0x000fe40007f1e0ff */
/*0930*/ LDG.E R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000f66000c1e1900 */
/*0940*/ IMAD.X R17, R17, 0x1, R6, P0 ; /* 0x0000000111117824 */
/* 0x000fe200000e0606 */
/*0950*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000f68000c1e1900 */
/*0960*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000f62000c1e1900 */
/*0970*/ IADD3 R12, P1, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x000fc40007f3e0ff */
/*0980*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0990*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e060d */
/*09b0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*09c0*/ FADD R5, R5, R2 ; /* 0x0000000205057221 */
/* 0x004fc80000000000 */
/*09d0*/ FADD R5, R5, R18 ; /* 0x0000001205057221 */
/* 0x008fc80000000000 */
/*09e0*/ FADD R5, R5, R20 ; /* 0x0000001405057221 */
/* 0x010fc80000000000 */
/*09f0*/ FADD R5, R5, R22 ; /* 0x0000001605057221 */
/* 0x020fc80000000000 */
/*0a00*/ FADD R5, R5, R24 ; /* 0x0000001805057221 */
/* 0x000fc80000000000 */
/*0a10*/ FADD R5, R5, R10 ; /* 0x0000000a05057221 */
/* 0x000fc80000000000 */
/*0a20*/ FADD R5, R5, R14 ; /* 0x0000000e05057221 */
/* 0x000fc80000000000 */
/*0a30*/ FADD R5, R5, R16 ; /* 0x0000001005057221 */
/* 0x000fe40000000000 */
/*0a40*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0a50*/ @!P0 BRA 0xc00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a60*/ LDG.E.64 R14, [R12.64] ; /* 0x000000080c0e7981 */
/* 0x000ea8000c1e1b00 */
/*0a70*/ LDG.E.64 R18, [R12.64+0x8] ; /* 0x000008080c127981 */
/* 0x000ee8000c1e1b00 */
/*0a80*/ LDG.E.64 R16, [R12.64+0x10] ; /* 0x000010080c107981 */
/* 0x000f28000c1e1b00 */
/*0a90*/ LDG.E.64 R10, [R12.64+0x18] ; /* 0x000018080c0a7981 */
/* 0x000f62000c1e1b00 */
/*0aa0*/ IADD3 R20, P0, R14, R7, RZ ; /* 0x000000070e147210 */
/* 0x004fca0007f1e0ff */
/*0ab0*/ IMAD.X R21, R15, 0x1, R6.reuse, P0 ; /* 0x000000010f157824 */
/* 0x100fe200000e0606 */
/*0ac0*/ IADD3 R14, P0, R18, R7.reuse, RZ ; /* 0x00000007120e7210 */
/* 0x088fe40007f1e0ff */
/*0ad0*/ IADD3 R16, P1, R16, R7.reuse, RZ ; /* 0x0000000710107210 */
/* 0x090fe40007f3e0ff */
/*0ae0*/ IADD3.X R15, R19, R6, RZ, P0, !PT ; /* 0x00000006130f7210 */
/* 0x000fe200007fe4ff */
/*0af0*/ LDG.E R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000ea2000c1e1900 */
/*0b00*/ IADD3 R10, P0, R10, R7, RZ ; /* 0x000000070a0a7210 */
/* 0x020fe20007f1e0ff */
/*0b10*/ IMAD.X R17, R17, 0x1, R6.reuse, P1 ; /* 0x0000000111117824 */
/* 0x100fe400008e0606 */
/*0b20*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000ee4000c1e1900 */
/*0b30*/ IMAD.X R11, R11, 0x1, R6, P0 ; /* 0x000000010b0b7824 */
/* 0x000fc400000e0606 */
/*0b40*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000f28000c1e1900 */
/*0b50*/ LDG.E R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000f62000c1e1900 */
/*0b60*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0b70*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0b80*/ IADD3 R12, P1, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x000fe40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f05270 */
/*0ba0*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e060d */
/*0bb0*/ FADD R5, R20, R5 ; /* 0x0000000514057221 */
/* 0x004fc80000000000 */
/*0bc0*/ FADD R5, R5, R14 ; /* 0x0000000e05057221 */
/* 0x008fc80000000000 */
/*0bd0*/ FADD R5, R5, R16 ; /* 0x0000001005057221 */
/* 0x010fc80000000000 */
/*0be0*/ FADD R5, R5, R10 ; /* 0x0000000a05057221 */
/* 0x020fe20000000000 */
/*0bf0*/ @P0 BRA 0xa60 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0c00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0c10*/ @!P0 BRA 0xd20 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0c20*/ SHF.L.U64.HI R11, R0, 0x2, R3 ; /* 0x00000002000b7819 */
/* 0x000fe20000010203 */
/*0c30*/ UMOV UR5, 0x8 ; /* 0x0000000800057882 */
/* 0x000fe40000000000 */
/*0c40*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0c50*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*0c60*/ MOV R6, UR4 ; /* 0x0000000400067c02 */
/* 0x000fe20008000f00 */
/*0c70*/ IMAD.U32 R7, RZ, RZ, UR5 ; /* 0x00000005ff077e24 */
/* 0x000fcc000f8e00ff */
/*0c80*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ea2000c1e1b00 */
/*0c90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ca0*/ LEA R8, P0, R0, R6, 0x2 ; /* 0x0000000600087211 */
/* 0x004fca00078010ff */
/*0cb0*/ IMAD.X R9, R7, 0x1, R11, P0 ; /* 0x0000000107097824 */
/* 0x000fca00000e060b */
/*0cc0*/ LDG.E R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000ea2000c1e1900 */
/*0cd0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0ce0*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fc8000ff1e03f */
/*0cf0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0d00*/ FADD R5, R8, R5 ; /* 0x0000000508057221 */
/* 0x004fce0000000000 */
/*0d10*/ @P0 BRA 0xc60 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0d20*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0d30*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f1403 */
/*0d40*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*0d50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d60*/ BRA 0xd60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2013/2014, March 3 - April 4
// ###
// ###
// ### Evgeny Strekalovskiy, Maria Klodt, Jan Stuehmer, Mohamed Souiai
// ###
// ###
// ### Shiv, painkiller047@gmail.com, p053
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
// adds elements at a particular index (i) of all input arrays
__device__ float add_elements_at(size_t i, float ** d_in_arrays, int noOfInArrays) {
float sum = 0;
// sum all arrays
for (int arrNo = 0; arrNo < noOfInArrays; arrNo++) {
sum += d_in_arrays[arrNo][i];
}
// return result
return sum;
}
// add arrays - given to be summed arrays as arrays or arrays, out array, size of each array (n), no of arrays to be summed
__global__ void add_arrays(float ** d_in_arrays, float * d_out_array, int n, int noOfInArrays) {
// get thread id
int id = threadIdx.x + blockDim.x * blockIdx.x;
// only threads inside array range compute
if(id < n) {
d_out_array[id] = add_elements_at(id, d_in_arrays, noOfInArrays);
}
}
// GPU allocs, mem copy and calls add arrays kernel
void add_arrays_caller(float * h_AoA[], int n, int noOfInArrays) {
// define block and grid sizes - 1D assumed
// setting a block of 512 threads
dim3 block = dim3(512, 1, 1);
dim3 grid = dim3((n + block.x - 1) / block.x, 1, 1);
// alloc GPU memory for all arrays be added and copy those arrays
float * arraysOnGPU[noOfInArrays];
int bytesPerArray = n * sizeof(float);
for(int i = 0; i < noOfInArrays; i++) {
cudaMalloc((void **) &arraysOnGPU[i], bytesPerArray);
CUDA_CHECK;
cudaMemcpy(arraysOnGPU[i], h_AoA[i], bytesPerArray, cudaMemcpyHostToDevice);
CUDA_CHECK;
}
// GPU memory that contains the above allocation addresses to the in arrays on GPU
float ** d_in_arrays;
cudaMalloc((void ***) &d_in_arrays, sizeof(float *) * noOfInArrays);
CUDA_CHECK;
cudaMemcpy(d_in_arrays, arraysOnGPU, sizeof(float *) * noOfInArrays, cudaMemcpyHostToDevice);
CUDA_CHECK;
// allocate GPU memory for output array
float * d_out_array;
cudaMalloc((void **) &d_out_array, sizeof(float) * bytesPerArray);
CUDA_CHECK;
// call kernel
add_arrays<<<grid, block>>>(d_in_arrays, d_out_array, n, noOfInArrays);
// wait for kernel call to finish
cudaDeviceSynchronize();
CUDA_CHECK;
// copy summed data in output array in GPU back to host
cudaMemcpy(h_AoA[noOfInArrays], d_out_array, bytesPerArray, cudaMemcpyDeviceToHost);
CUDA_CHECK;
// free GPU memory - for both in and out arrays
for(int i = 0; i < noOfInArrays; i++) {
cudaFree(arraysOnGPU[i]);
CUDA_CHECK;
}
cudaFree(d_out_array);
CUDA_CHECK;
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 20;
int NO_IN_ARRAYS = 2;
float *a = new float[n];
float *b = new float[n];
float *c = new float[n];
for(int i=0; i<n; i++)
{
a[i] = i;
b[i] = (i%5)+1;
c[i] = 0;
}
// CPU computation
for(int i=0; i<n; i++) c[i] = a[i] + b[i];
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// init c
for(int i=0; i<n; i++) c[i] = 0;
// GPU computation
// ###
// ### TODO: Implement the array addition on the GPU, store the result in "c"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "aux.h"
// following convention
// total arrays including result array
float * h_AoA[] = {a, b, c};
// kernel caller
add_arrays_caller(h_AoA, n, NO_IN_ARRAYS);
// print result
cout << "GPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
delete[] b;
delete[] c;
} | .file "tmpxft_00061f27_00000000-6_add_arrays.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ", line "
.LC1:
.string ": "
.LC2:
.string " ("
.LC3:
.string ")"
.text
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, @function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.globl _Z15add_elements_atmPPfi
.type _Z15add_elements_atmPPfi, @function
_Z15add_elements_atmPPfi:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z15add_elements_atmPPfi, .-_Z15add_elements_atmPPfi
.globl _Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii
.type _Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii, @function
_Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_arraysPPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii, .-_Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii
.globl _Z10add_arraysPPfS_ii
.type _Z10add_arraysPPfS_ii, @function
_Z10add_arraysPPfS_ii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z10add_arraysPPfS_ii, .-_Z10add_arraysPPfS_ii
.section .rodata.str1.1
.LC4:
.string "_Z10add_arraysPPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_arraysPPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag:
.LFB4086:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L26
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L22
movzbl (%rsi), %eax
movb %al, (%rdi)
.L23:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L21:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L23
.L22:
testq %rdx, %rdx
je .L23
jmp .L21
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4086:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/shiviser/TUM_GPUComputerVision/master/cuda_team_warp64/exercises/2/add_arrays.cu"
.text
.globl _Z17add_arrays_callerPPfii
.type _Z17add_arrays_callerPPfii, @function
_Z17add_arrays_callerPPfii:
.LFB3671:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3671
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $168, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, -176(%rbp)
movl %esi, -184(%rbp)
movl %edx, -180(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $1, -116(%rbp)
movl $1, -112(%rbp)
leal 511(%rsi), %eax
shrl $9, %eax
movl %eax, -108(%rbp)
movl $1, -104(%rbp)
movl $1, -100(%rbp)
movslq %edx, %rax
movq %rax, -200(%rbp)
salq $3, %rax
movq %rax, -168(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L29:
cmpq %rdx, %rsp
je .L30
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L29
.L30:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L31
orq $0, -8(%rsp,%rax)
.L31:
movq %rsp, %rax
movq %rax, -192(%rbp)
movl -184(%rbp), %ecx
leal 0(,%rcx,4), %edx
movl %edx, -204(%rbp)
cmpl $0, -180(%rbp)
jle .L32
movq %rax, %rbx
movq -176(%rbp), %r13
movq -168(%rbp), %rcx
addq %rcx, %rax
movq %rax, -160(%rbp)
movslq %edx, %r14
leaq -96(%rbp), %r12
leaq .LC5(%rip), %r15
jmp .L35
.L77:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L33
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L33:
movq 0(%r13), %rsi
movq -152(%rbp), %rax
movq (%rax), %rdi
movl $1, %ecx
movq %r14, %rdx
.LEHB0:
call cudaMemcpy@PLT
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
movq %r15, %rsi
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE0:
movl $75, %esi
movq %r12, %rdi
.LEHB1:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE1:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L34
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L34:
addq $8, %rbx
addq $8, %r13
movq -160(%rbp), %rax
cmpq %rax, %rbx
je .L32
.L35:
movq %rbx, -152(%rbp)
movq %r14, %rsi
movq %rbx, %rdi
.LEHB2:
call cudaMalloc@PLT
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
movq %r15, %rsi
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE2:
movl $73, %esi
movq %r12, %rdi
.LEHB3:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE3:
jmp .L77
.L32:
leaq -136(%rbp), %rdi
movq -168(%rbp), %rsi
.LEHB4:
call cudaMalloc@PLT
leaq -96(%rbp), %rbx
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
leaq -127(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE4:
movl $81, %esi
movq %rbx, %rdi
.LEHB5:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE5:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L36
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L36:
movl $1, %ecx
movq -168(%rbp), %rdx
movq -192(%rbp), %rsi
movq -136(%rbp), %rdi
.LEHB6:
call cudaMemcpy@PLT
leaq -96(%rbp), %rbx
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
leaq -127(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE6:
movl $83, %esi
movq %rbx, %rdi
.LEHB7:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE7:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L37
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L37:
movslq -204(%rbp), %rbx
leaq 0(,%rbx,4), %rsi
leaq -128(%rbp), %rdi
.LEHB8:
call cudaMalloc@PLT
leaq -96(%rbp), %r12
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
leaq -127(%rdx), %rsi
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE8:
movl $88, %esi
movq %r12, %rdi
.LEHB9:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE9:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L38
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L38:
movl $512, -120(%rbp)
movl -112(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -120(%rbp), %rdx
movq -108(%rbp), %rdi
movl -100(%rbp), %esi
.LEHB10:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L78
.L39:
call cudaDeviceSynchronize@PLT
leaq -96(%rbp), %r12
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
leaq -127(%rdx), %rsi
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE10:
movl $95, %esi
movq %r12, %rdi
.LEHB11:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE11:
jmp .L79
.L78:
movl -180(%rbp), %ecx
movl -184(%rbp), %edx
movq -128(%rbp), %rsi
movq -136(%rbp), %rdi
.LEHB12:
call _Z35__device_stub__Z10add_arraysPPfS_iiPPfS_ii
jmp .L39
.L79:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L40
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L40:
movq -176(%rbp), %rax
movq -200(%rbp), %rcx
movq (%rax,%rcx,8), %rdi
movl $2, %ecx
movq %rbx, %rdx
movq -128(%rbp), %rsi
call cudaMemcpy@PLT
leaq -96(%rbp), %rbx
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
leaq -127(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE12:
movl $99, %esi
movq %rbx, %rdi
.LEHB13:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE13:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L41
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L41:
cmpl $0, -180(%rbp)
jle .L42
movq -192(%rbp), %r14
movq %r14, %rbx
movq -168(%rbp), %rax
addq %rax, %r14
leaq -96(%rbp), %r13
leaq -80(%rbp), %r12
leaq 127+.LC5(%rip), %r15
jmp .L44
.L80:
movq -96(%rbp), %rdi
cmpq %r12, %rdi
je .L43
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L43:
addq $8, %rbx
cmpq %r14, %rbx
je .L42
.L44:
movq (%rbx), %rdi
.LEHB14:
call cudaFree@PLT
movq %r12, -96(%rbp)
movq %r15, %rdx
leaq -127(%r15), %rsi
movq %r13, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE14:
movl $104, %esi
movq %r13, %rdi
.LEHB15:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE15:
jmp .L80
.L42:
movq -128(%rbp), %rdi
.LEHB16:
call cudaFree@PLT
leaq -96(%rbp), %rbx
leaq -80(%rbp), %rax
movq %rax, -96(%rbp)
leaq 127+.LC5(%rip), %rdx
leaq -127(%rdx), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE16:
movl $107, %esi
movq %rbx, %rdi
.LEHB17:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE17:
movq -96(%rbp), %rdi
leaq -80(%rbp), %rax
cmpq %rax, %rdi
je .L28
movq -80(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L28:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L81
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L65:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L47
call __stack_chk_fail@PLT
.L47:
movq %rbx, %rdi
.LEHB18:
call _Unwind_Resume@PLT
.L66:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L49
call __stack_chk_fail@PLT
.L49:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L67:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L51:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L68:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L53
call __stack_chk_fail@PLT
.L53:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L69:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L55
call __stack_chk_fail@PLT
.L55:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L70:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L57
call __stack_chk_fail@PLT
.L57:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L71:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L59
call __stack_chk_fail@PLT
.L59:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L72:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L61
call __stack_chk_fail@PLT
.L61:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L73:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L63
call __stack_chk_fail@PLT
.L63:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE18:
.L81:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3671:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3671-.LLSDACSB3671
.LLSDACSB3671:
.uleb128 .LEHB0-.LFB3671
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3671
.uleb128 .LEHE1-.LEHB1
.uleb128 .L66-.LFB3671
.uleb128 0
.uleb128 .LEHB2-.LFB3671
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3671
.uleb128 .LEHE3-.LEHB3
.uleb128 .L65-.LFB3671
.uleb128 0
.uleb128 .LEHB4-.LFB3671
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3671
.uleb128 .LEHE5-.LEHB5
.uleb128 .L67-.LFB3671
.uleb128 0
.uleb128 .LEHB6-.LFB3671
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB3671
.uleb128 .LEHE7-.LEHB7
.uleb128 .L68-.LFB3671
.uleb128 0
.uleb128 .LEHB8-.LFB3671
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB3671
.uleb128 .LEHE9-.LEHB9
.uleb128 .L69-.LFB3671
.uleb128 0
.uleb128 .LEHB10-.LFB3671
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.uleb128 .LEHB11-.LFB3671
.uleb128 .LEHE11-.LEHB11
.uleb128 .L70-.LFB3671
.uleb128 0
.uleb128 .LEHB12-.LFB3671
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.uleb128 .LEHB13-.LFB3671
.uleb128 .LEHE13-.LEHB13
.uleb128 .L71-.LFB3671
.uleb128 0
.uleb128 .LEHB14-.LFB3671
.uleb128 .LEHE14-.LEHB14
.uleb128 0
.uleb128 0
.uleb128 .LEHB15-.LFB3671
.uleb128 .LEHE15-.LEHB15
.uleb128 .L72-.LFB3671
.uleb128 0
.uleb128 .LEHB16-.LFB3671
.uleb128 .LEHE16-.LEHB16
.uleb128 0
.uleb128 0
.uleb128 .LEHB17-.LFB3671
.uleb128 .LEHE17-.LEHB17
.uleb128 .L73-.LFB3671
.uleb128 0
.uleb128 .LEHB18-.LFB3671
.uleb128 .LEHE18-.LEHB18
.uleb128 0
.uleb128 0
.LLSDACSE3671:
.text
.size _Z17add_arrays_callerPPfii, .-_Z17add_arrays_callerPPfii
.section .rodata.str1.1
.LC7:
.string "CPU:"
.LC8:
.string " + "
.LC9:
.string " = "
.LC10:
.string "GPU:"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $80, %edi
call _Znam@PLT
movq %rax, %r15
movl $80, %edi
call _Znam@PLT
movq %rax, %r14
movl $80, %edi
call _Znam@PLT
movq %rax, %r13
movl $0, %eax
.L83:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
movl %eax, %edx
subl %ecx, %edx
addl $1, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%r14,%rax,4)
movl $0x00000000, 0(%r13,%rax,4)
addq $1, %rax
cmpq $20, %rax
jne .L83
movl $0, %eax
.L84:
movss (%r15,%rax), %xmm0
addss (%r14,%rax), %xmm0
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq $80, %rax
jne .L84
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
jmp .L89
.L105:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L103
call _ZSt16__throw_bad_castv@PLT
.L103:
call __stack_chk_fail@PLT
.L87:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L88:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $20, %rbx
je .L104
.L89:
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L105
cmpb $0, 56(%r12)
je .L87
movzbl 67(%r12), %esi
jmp .L88
.L104:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rax
leaq 80(%r13), %rdx
.L90:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L90
movq %r15, (%rsp)
movq %r14, 8(%rsp)
movq %r13, 16(%rsp)
movq %rsp, %rdi
movl $2, %edx
movl $20, %esi
call _Z17add_arrays_callerPPfii
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
jmp .L95
.L108:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L106
call _ZSt16__throw_bad_castv@PLT
.L106:
call __stack_chk_fail@PLT
.L93:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L94:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $20, %rbx
je .L107
.L95:
movl %ebx, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L108
cmpb $0, 56(%r12)
je .L93
movzbl 67(%r12), %esi
jmp .L94
.L107:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L109
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L109:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2013/2014, March 3 - April 4
// ###
// ###
// ### Evgeny Strekalovskiy, Maria Klodt, Jan Stuehmer, Mohamed Souiai
// ###
// ###
// ### Shiv, painkiller047@gmail.com, p053
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
// adds elements at a particular index (i) of all input arrays
__device__ float add_elements_at(size_t i, float ** d_in_arrays, int noOfInArrays) {
float sum = 0;
// sum all arrays
for (int arrNo = 0; arrNo < noOfInArrays; arrNo++) {
sum += d_in_arrays[arrNo][i];
}
// return result
return sum;
}
// add arrays - given to be summed arrays as arrays or arrays, out array, size of each array (n), no of arrays to be summed
__global__ void add_arrays(float ** d_in_arrays, float * d_out_array, int n, int noOfInArrays) {
// get thread id
int id = threadIdx.x + blockDim.x * blockIdx.x;
// only threads inside array range compute
if(id < n) {
d_out_array[id] = add_elements_at(id, d_in_arrays, noOfInArrays);
}
}
// GPU allocs, mem copy and calls add arrays kernel
void add_arrays_caller(float * h_AoA[], int n, int noOfInArrays) {
// define block and grid sizes - 1D assumed
// setting a block of 512 threads
dim3 block = dim3(512, 1, 1);
dim3 grid = dim3((n + block.x - 1) / block.x, 1, 1);
// alloc GPU memory for all arrays be added and copy those arrays
float * arraysOnGPU[noOfInArrays];
int bytesPerArray = n * sizeof(float);
for(int i = 0; i < noOfInArrays; i++) {
cudaMalloc((void **) &arraysOnGPU[i], bytesPerArray);
CUDA_CHECK;
cudaMemcpy(arraysOnGPU[i], h_AoA[i], bytesPerArray, cudaMemcpyHostToDevice);
CUDA_CHECK;
}
// GPU memory that contains the above allocation addresses to the in arrays on GPU
float ** d_in_arrays;
cudaMalloc((void ***) &d_in_arrays, sizeof(float *) * noOfInArrays);
CUDA_CHECK;
cudaMemcpy(d_in_arrays, arraysOnGPU, sizeof(float *) * noOfInArrays, cudaMemcpyHostToDevice);
CUDA_CHECK;
// allocate GPU memory for output array
float * d_out_array;
cudaMalloc((void **) &d_out_array, sizeof(float) * bytesPerArray);
CUDA_CHECK;
// call kernel
add_arrays<<<grid, block>>>(d_in_arrays, d_out_array, n, noOfInArrays);
// wait for kernel call to finish
cudaDeviceSynchronize();
CUDA_CHECK;
// copy summed data in output array in GPU back to host
cudaMemcpy(h_AoA[noOfInArrays], d_out_array, bytesPerArray, cudaMemcpyDeviceToHost);
CUDA_CHECK;
// free GPU memory - for both in and out arrays
for(int i = 0; i < noOfInArrays; i++) {
cudaFree(arraysOnGPU[i]);
CUDA_CHECK;
}
cudaFree(d_out_array);
CUDA_CHECK;
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 20;
int NO_IN_ARRAYS = 2;
float *a = new float[n];
float *b = new float[n];
float *c = new float[n];
for(int i=0; i<n; i++)
{
a[i] = i;
b[i] = (i%5)+1;
c[i] = 0;
}
// CPU computation
for(int i=0; i<n; i++) c[i] = a[i] + b[i];
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// init c
for(int i=0; i<n; i++) c[i] = 0;
// GPU computation
// ###
// ### TODO: Implement the array addition on the GPU, store the result in "c"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "aux.h"
// following convention
// total arrays including result array
float * h_AoA[] = {a, b, c};
// kernel caller
add_arrays_caller(h_AoA, n, NO_IN_ARRAYS);
// print result
cout << "GPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
delete[] b;
delete[] c;
} | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2013/2014, March 3 - April 4
// ###
// ###
// ### Evgeny Strekalovskiy, Maria Klodt, Jan Stuehmer, Mohamed Souiai
// ###
// ###
// ### Shiv, painkiller047@gmail.com, p053
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
// adds elements at a particular index (i) of all input arrays
__device__ float add_elements_at(size_t i, float ** d_in_arrays, int noOfInArrays) {
float sum = 0;
// sum all arrays
for (int arrNo = 0; arrNo < noOfInArrays; arrNo++) {
sum += d_in_arrays[arrNo][i];
}
// return result
return sum;
}
// add arrays - given to be summed arrays as arrays or arrays, out array, size of each array (n), no of arrays to be summed
__global__ void add_arrays(float ** d_in_arrays, float * d_out_array, int n, int noOfInArrays) {
// get thread id
int id = threadIdx.x + blockDim.x * blockIdx.x;
// only threads inside array range compute
if(id < n) {
d_out_array[id] = add_elements_at(id, d_in_arrays, noOfInArrays);
}
}
// GPU allocs, mem copy and calls add arrays kernel
void add_arrays_caller(float * h_AoA[], int n, int noOfInArrays) {
// define block and grid sizes - 1D assumed
// setting a block of 512 threads
dim3 block = dim3(512, 1, 1);
dim3 grid = dim3((n + block.x - 1) / block.x, 1, 1);
// alloc GPU memory for all arrays be added and copy those arrays
float * arraysOnGPU[noOfInArrays];
int bytesPerArray = n * sizeof(float);
for(int i = 0; i < noOfInArrays; i++) {
hipMalloc((void **) &arraysOnGPU[i], bytesPerArray);
CUDA_CHECK;
hipMemcpy(arraysOnGPU[i], h_AoA[i], bytesPerArray, hipMemcpyHostToDevice);
CUDA_CHECK;
}
// GPU memory that contains the above allocation addresses to the in arrays on GPU
float ** d_in_arrays;
hipMalloc((void ***) &d_in_arrays, sizeof(float *) * noOfInArrays);
CUDA_CHECK;
hipMemcpy(d_in_arrays, arraysOnGPU, sizeof(float *) * noOfInArrays, hipMemcpyHostToDevice);
CUDA_CHECK;
// allocate GPU memory for output array
float * d_out_array;
hipMalloc((void **) &d_out_array, sizeof(float) * bytesPerArray);
CUDA_CHECK;
// call kernel
add_arrays<<<grid, block>>>(d_in_arrays, d_out_array, n, noOfInArrays);
// wait for kernel call to finish
hipDeviceSynchronize();
CUDA_CHECK;
// copy summed data in output array in GPU back to host
hipMemcpy(h_AoA[noOfInArrays], d_out_array, bytesPerArray, hipMemcpyDeviceToHost);
CUDA_CHECK;
// free GPU memory - for both in and out arrays
for(int i = 0; i < noOfInArrays; i++) {
hipFree(arraysOnGPU[i]);
CUDA_CHECK;
}
hipFree(d_out_array);
CUDA_CHECK;
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 20;
int NO_IN_ARRAYS = 2;
float *a = new float[n];
float *b = new float[n];
float *c = new float[n];
for(int i=0; i<n; i++)
{
a[i] = i;
b[i] = (i%5)+1;
c[i] = 0;
}
// CPU computation
for(int i=0; i<n; i++) c[i] = a[i] + b[i];
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// init c
for(int i=0; i<n; i++) c[i] = 0;
// GPU computation
// ###
// ### TODO: Implement the array addition on the GPU, store the result in "c"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "aux.h"
// following convention
// total arrays including result array
float * h_AoA[] = {a, b, c};
// kernel caller
add_arrays_caller(h_AoA, n, NO_IN_ARRAYS);
// print result
cout << "GPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
delete[] b;
delete[] c;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2013/2014, March 3 - April 4
// ###
// ###
// ### Evgeny Strekalovskiy, Maria Klodt, Jan Stuehmer, Mohamed Souiai
// ###
// ###
// ### Shiv, painkiller047@gmail.com, p053
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
// adds elements at a particular index (i) of all input arrays
__device__ float add_elements_at(size_t i, float ** d_in_arrays, int noOfInArrays) {
float sum = 0;
// sum all arrays
for (int arrNo = 0; arrNo < noOfInArrays; arrNo++) {
sum += d_in_arrays[arrNo][i];
}
// return result
return sum;
}
// add arrays - given to be summed arrays as arrays or arrays, out array, size of each array (n), no of arrays to be summed
__global__ void add_arrays(float ** d_in_arrays, float * d_out_array, int n, int noOfInArrays) {
// get thread id
int id = threadIdx.x + blockDim.x * blockIdx.x;
// only threads inside array range compute
if(id < n) {
d_out_array[id] = add_elements_at(id, d_in_arrays, noOfInArrays);
}
}
// GPU allocs, mem copy and calls add arrays kernel
void add_arrays_caller(float * h_AoA[], int n, int noOfInArrays) {
// define block and grid sizes - 1D assumed
// setting a block of 512 threads
dim3 block = dim3(512, 1, 1);
dim3 grid = dim3((n + block.x - 1) / block.x, 1, 1);
// alloc GPU memory for all arrays be added and copy those arrays
float * arraysOnGPU[noOfInArrays];
int bytesPerArray = n * sizeof(float);
for(int i = 0; i < noOfInArrays; i++) {
hipMalloc((void **) &arraysOnGPU[i], bytesPerArray);
CUDA_CHECK;
hipMemcpy(arraysOnGPU[i], h_AoA[i], bytesPerArray, hipMemcpyHostToDevice);
CUDA_CHECK;
}
// GPU memory that contains the above allocation addresses to the in arrays on GPU
float ** d_in_arrays;
hipMalloc((void ***) &d_in_arrays, sizeof(float *) * noOfInArrays);
CUDA_CHECK;
hipMemcpy(d_in_arrays, arraysOnGPU, sizeof(float *) * noOfInArrays, hipMemcpyHostToDevice);
CUDA_CHECK;
// allocate GPU memory for output array
float * d_out_array;
hipMalloc((void **) &d_out_array, sizeof(float) * bytesPerArray);
CUDA_CHECK;
// call kernel
add_arrays<<<grid, block>>>(d_in_arrays, d_out_array, n, noOfInArrays);
// wait for kernel call to finish
hipDeviceSynchronize();
CUDA_CHECK;
// copy summed data in output array in GPU back to host
hipMemcpy(h_AoA[noOfInArrays], d_out_array, bytesPerArray, hipMemcpyDeviceToHost);
CUDA_CHECK;
// free GPU memory - for both in and out arrays
for(int i = 0; i < noOfInArrays; i++) {
hipFree(arraysOnGPU[i]);
CUDA_CHECK;
}
hipFree(d_out_array);
CUDA_CHECK;
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 20;
int NO_IN_ARRAYS = 2;
float *a = new float[n];
float *b = new float[n];
float *c = new float[n];
for(int i=0; i<n; i++)
{
a[i] = i;
b[i] = (i%5)+1;
c[i] = 0;
}
// CPU computation
for(int i=0; i<n; i++) c[i] = a[i] + b[i];
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// init c
for(int i=0; i<n; i++) c[i] = 0;
// GPU computation
// ###
// ### TODO: Implement the array addition on the GPU, store the result in "c"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "aux.h"
// following convention
// total arrays including result array
float * h_AoA[] = {a, b, c};
// kernel caller
add_arrays_caller(h_AoA, n, NO_IN_ARRAYS);
// print result
cout << "GPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
delete[] b;
delete[] c;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_arraysPPfS_ii
.globl _Z10add_arraysPPfS_ii
.p2align 8
.type _Z10add_arraysPPfS_ii,@function
_Z10add_arraysPPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b32 s4, s[0:1], 0x14
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, 0
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_load_b64 s[6:7], s[2:3], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
flat_load_b32 v5, v[5:6]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v5
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_arraysPPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_arraysPPfS_ii, .Lfunc_end0-_Z10add_arraysPPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_arraysPPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_arraysPPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Winter Semester 2013/2014, March 3 - April 4
// ###
// ###
// ### Evgeny Strekalovskiy, Maria Klodt, Jan Stuehmer, Mohamed Souiai
// ###
// ###
// ### Shiv, painkiller047@gmail.com, p053
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
// adds elements at a particular index (i) of all input arrays
__device__ float add_elements_at(size_t i, float ** d_in_arrays, int noOfInArrays) {
float sum = 0;
// sum all arrays
for (int arrNo = 0; arrNo < noOfInArrays; arrNo++) {
sum += d_in_arrays[arrNo][i];
}
// return result
return sum;
}
// add arrays - given to be summed arrays as arrays or arrays, out array, size of each array (n), no of arrays to be summed
__global__ void add_arrays(float ** d_in_arrays, float * d_out_array, int n, int noOfInArrays) {
// get thread id
int id = threadIdx.x + blockDim.x * blockIdx.x;
// only threads inside array range compute
if(id < n) {
d_out_array[id] = add_elements_at(id, d_in_arrays, noOfInArrays);
}
}
// GPU allocs, mem copy and calls add arrays kernel
void add_arrays_caller(float * h_AoA[], int n, int noOfInArrays) {
// define block and grid sizes - 1D assumed
// setting a block of 512 threads
dim3 block = dim3(512, 1, 1);
dim3 grid = dim3((n + block.x - 1) / block.x, 1, 1);
// alloc GPU memory for all arrays be added and copy those arrays
float * arraysOnGPU[noOfInArrays];
int bytesPerArray = n * sizeof(float);
for(int i = 0; i < noOfInArrays; i++) {
hipMalloc((void **) &arraysOnGPU[i], bytesPerArray);
CUDA_CHECK;
hipMemcpy(arraysOnGPU[i], h_AoA[i], bytesPerArray, hipMemcpyHostToDevice);
CUDA_CHECK;
}
// GPU memory that contains the above allocation addresses to the in arrays on GPU
float ** d_in_arrays;
hipMalloc((void ***) &d_in_arrays, sizeof(float *) * noOfInArrays);
CUDA_CHECK;
hipMemcpy(d_in_arrays, arraysOnGPU, sizeof(float *) * noOfInArrays, hipMemcpyHostToDevice);
CUDA_CHECK;
// allocate GPU memory for output array
float * d_out_array;
hipMalloc((void **) &d_out_array, sizeof(float) * bytesPerArray);
CUDA_CHECK;
// call kernel
add_arrays<<<grid, block>>>(d_in_arrays, d_out_array, n, noOfInArrays);
// wait for kernel call to finish
hipDeviceSynchronize();
CUDA_CHECK;
// copy summed data in output array in GPU back to host
hipMemcpy(h_AoA[noOfInArrays], d_out_array, bytesPerArray, hipMemcpyDeviceToHost);
CUDA_CHECK;
// free GPU memory - for both in and out arrays
for(int i = 0; i < noOfInArrays; i++) {
hipFree(arraysOnGPU[i]);
CUDA_CHECK;
}
hipFree(d_out_array);
CUDA_CHECK;
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 20;
int NO_IN_ARRAYS = 2;
float *a = new float[n];
float *b = new float[n];
float *c = new float[n];
for(int i=0; i<n; i++)
{
a[i] = i;
b[i] = (i%5)+1;
c[i] = 0;
}
// CPU computation
for(int i=0; i<n; i++) c[i] = a[i] + b[i];
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// init c
for(int i=0; i<n; i++) c[i] = 0;
// GPU computation
// ###
// ### TODO: Implement the array addition on the GPU, store the result in "c"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "aux.h"
// following convention
// total arrays including result array
float * h_AoA[] = {a, b, c};
// kernel caller
add_arrays_caller(h_AoA, n, NO_IN_ARRAYS);
// print result
cout << "GPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << " + " << b[i] << " = " << c[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
delete[] b;
delete[] c;
} | .text
.file "add_arrays.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi # -- Begin function _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.p2align 4, 0x90
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi,@function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi: # @_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cout, %edi
movl %eax, %ebx
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .Lfunc_end0-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__add_arraysPPfS_ii # -- Begin function _Z25__device_stub__add_arraysPPfS_ii
.p2align 4, 0x90
.type _Z25__device_stub__add_arraysPPfS_ii,@function
_Z25__device_stub__add_arraysPPfS_ii: # @_Z25__device_stub__add_arraysPPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_arraysPPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__add_arraysPPfS_ii, .Lfunc_end1-_Z25__device_stub__add_arraysPPfS_ii
.cfi_endproc
# -- End function
.globl _Z17add_arrays_callerPPfii # -- Begin function _Z17add_arrays_callerPPfii
.p2align 4, 0x90
.type _Z17add_arrays_callerPPfii,@function
_Z17add_arrays_callerPPfii: # @_Z17add_arrays_callerPPfii
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $472, %rsp # imm = 0x1D8
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
# kill: def $esi killed $esi def $rsi
movq %rdi, -104(%rbp) # 8-byte Spill
movl %edx, %eax
.cfi_escape 0x2e, 0x00
movq %rsp, %rcx
movq %rax, -96(%rbp) # 8-byte Spill
leaq 15(,%rax,8), %rax
andq $-16, %rax
subq %rax, %rcx
movq %rcx, -56(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %rsi, -88(%rbp) # 8-byte Spill
leal (,%rsi,4), %eax
cltq
movq %rax, -48(%rbp) # 8-byte Spill
movl %edx, -68(%rbp) # 4-byte Spill
testl %edx, %edx
jle .LBB2_9
# %bb.1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i71.lr.ph
leaq -392(%rbp), %r13
leaq -360(%rbp), %r12
movq -96(%rbp), %rax # 8-byte Reload
leaq (,%rax,8), %rax
movq %rax, -120(%rbp) # 8-byte Spill
xorl %ebx, %ebx
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit87
# in Loop: Header=BB2_2 Depth=1
addq $8, %rbx
cmpq %rbx, -120(%rbp) # 8-byte Folded Reload
je .LBB2_9
.LBB2_2: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i71
# =>This Inner Loop Header: Depth=1
movq -56(%rbp), %rax # 8-byte Reload
leaq (%rax,%rbx), %r15
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq -48(%rbp), %rsi # 8-byte Reload
callq hipMalloc
movq %r13, -408(%rbp)
.cfi_escape 0x2e, 0x00
movl $139, %edi
callq _Znwm
movq %r13, %r14
movq %rax, %r13
movq %rax, -408(%rbp)
movq $138, -392(%rbp)
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $138, %edx
movq %rax, %rdi
callq memcpy@PLT
movq $138, -400(%rbp)
movb $0, 138(%r13)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq -408(%rbp), %rdi
movl $73, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp1:
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movq -408(%rbp), %rdi
cmpq %r14, %rdi
movq %r14, %r13
je .LBB2_5
# %bb.4: # %.critedge.i.i
# in Loop: Header=BB2_2 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
# in Loop: Header=BB2_2 Depth=1
movq (%r15), %rdi
movq -104(%rbp), %rax # 8-byte Reload
movq (%rax,%rbx), %rsi
.cfi_escape 0x2e, 0x00
movq -48(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq %r12, -376(%rbp)
.cfi_escape 0x2e, 0x00
movl $139, %edi
callq _Znwm
movq %rax, %r15
movq %rax, -376(%rbp)
movq $138, -360(%rbp)
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $138, %edx
movq %rax, %rdi
callq memcpy@PLT
movq $138, -368(%rbp)
movb $0, 138(%r15)
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq -376(%rbp), %rdi
movl $75, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp4:
# %bb.6: # in Loop: Header=BB2_2 Depth=1
movq -376(%rbp), %rdi
cmpq %r12, %rdi
je .LBB2_8
# %bb.7: # %.critedge.i.i85
# in Loop: Header=BB2_2 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZdlPv
jmp .LBB2_8
.LBB2_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
movl -68(%rbp), %r12d # 4-byte Reload
movslq %r12d, %r13
leaq (,%r13,8), %r14
.cfi_escape 0x2e, 0x00
leaq -112(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq -328(%rbp), %rbx
movq %rbx, -344(%rbp)
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $139, %edi
callq _Znwm
.Ltmp7:
# %bb.10: # %.noexc70
movq %rax, %r15
movq %rax, -344(%rbp)
movq $138, -328(%rbp)
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $138, %edx
movq %rax, %rdi
callq memcpy@PLT
movq $138, -336(%rbp)
movb $0, 138(%r15)
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq -344(%rbp), %rdi
movl $81, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp10:
# %bb.11:
movq -344(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_13
# %bb.12: # %.critedge.i.i94
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_13: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit96
movq -112(%rbp), %rdi
.cfi_escape 0x2e, 0x00
movq -56(%rbp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq -296(%rbp), %rbx
movq %rbx, -312(%rbp)
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $139, %edi
callq _Znwm
.Ltmp13:
# %bb.14: # %.noexc102
movq %rax, %r14
movq %rax, -312(%rbp)
movq $138, -296(%rbp)
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $138, %edx
movq %rax, %rdi
callq memcpy@PLT
movq $138, -304(%rbp)
movb $0, 138(%r14)
.Ltmp15:
.cfi_escape 0x2e, 0x00
leaq -312(%rbp), %rdi
movl $83, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp16:
# %bb.15:
movq -312(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_17
# %bb.16: # %.critedge.i.i104
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit106
movq -48(%rbp), %rax # 8-byte Reload
leaq (,%rax,4), %rsi
.cfi_escape 0x2e, 0x00
leaq -64(%rbp), %rdi
callq hipMalloc
leaq -264(%rbp), %rbx
movq %rbx, -280(%rbp)
.Ltmp18:
.cfi_escape 0x2e, 0x00
movl $139, %edi
callq _Znwm
.Ltmp19:
# %bb.18: # %.noexc112
movq %rax, %r14
movq %rax, -280(%rbp)
movq $138, -264(%rbp)
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $138, %edx
movq %rax, %rdi
callq memcpy@PLT
movq $138, -272(%rbp)
movb $0, 138(%r14)
.Ltmp21:
.cfi_escape 0x2e, 0x00
leaq -280(%rbp), %rdi
movl $88, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp22:
# %bb.19:
movq -88(%rbp), %rax # 8-byte Reload
leal 511(%rax), %r14d
shrl $9, %r14d
movabsq $4294967296, %r15 # imm = 0x100000000
orq %r15, %r14
movq -280(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_21
# %bb.20: # %.critedge.i.i114
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_21: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit116
addq $512, %r15 # imm = 0x200
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_23
# %bb.22:
movq -112(%rbp), %rax
movq -64(%rbp), %rcx
movq %rax, -472(%rbp)
movq %rcx, -464(%rbp)
movq -88(%rbp), %rax # 8-byte Reload
movl %eax, -76(%rbp)
movl %r12d, -72(%rbp)
leaq -472(%rbp), %rax
movq %rax, -512(%rbp)
leaq -464(%rbp), %rax
movq %rax, -504(%rbp)
leaq -76(%rbp), %rax
movq %rax, -496(%rbp)
leaq -72(%rbp), %rax
movq %rax, -488(%rbp)
.cfi_escape 0x2e, 0x00
leaq -456(%rbp), %rdi
leaq -440(%rbp), %rsi
leaq -424(%rbp), %rdx
leaq -416(%rbp), %rcx
callq __hipPopCallConfiguration
movq -456(%rbp), %rsi
movl -448(%rbp), %edx
movq -440(%rbp), %rcx
movl -432(%rbp), %r8d
.cfi_escape 0x2e, 0x10
leaq -512(%rbp), %r9
movl $_Z10add_arraysPPfS_ii, %edi
pushq -416(%rbp)
pushq -424(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB2_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i126
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
leaq -232(%rbp), %rbx
movq %rbx, -248(%rbp)
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $139, %edi
callq _Znwm
.Ltmp25:
# %bb.24: # %.noexc131
movq %rax, %r14
movq %rax, -248(%rbp)
movq $138, -232(%rbp)
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $138, %edx
movq %rax, %rdi
callq memcpy@PLT
movq $138, -240(%rbp)
movb $0, 138(%r14)
.Ltmp27:
.cfi_escape 0x2e, 0x00
leaq -248(%rbp), %rdi
movl $95, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp28:
# %bb.25:
movq -248(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_27
# %bb.26: # %.critedge.i.i133
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_27: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit135
movq -104(%rbp), %rax # 8-byte Reload
movq (%rax,%r13,8), %rdi
movq -64(%rbp), %rsi
.cfi_escape 0x2e, 0x00
movq -48(%rbp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
leaq -200(%rbp), %rbx
movq %rbx, -216(%rbp)
.Ltmp30:
.cfi_escape 0x2e, 0x00
movl $139, %edi
callq _Znwm
.Ltmp31:
# %bb.28: # %.noexc141
movq %rax, %r14
movq %rax, -216(%rbp)
movq $138, -200(%rbp)
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $138, %edx
movq %rax, %rdi
callq memcpy@PLT
movq $138, -208(%rbp)
movb $0, 138(%r14)
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq -216(%rbp), %rdi
movl $99, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp34:
# %bb.29:
movq -216(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_31
# %bb.30: # %.critedge.i.i143
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_31: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit145
testl %r12d, %r12d
jle .LBB2_38
# %bb.32: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i159.lr.ph
leaq -168(%rbp), %rbx
xorl %r12d, %r12d
leaq -184(%rbp), %r14
jmp .LBB2_33
.p2align 4, 0x90
.LBB2_37: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit168
# in Loop: Header=BB2_33 Depth=1
incq %r12
cmpq %r12, -96(%rbp) # 8-byte Folded Reload
je .LBB2_38
.LBB2_33: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i159
# =>This Inner Loop Header: Depth=1
movq -56(%rbp), %rax # 8-byte Reload
movq (%rax,%r12,8), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq %rbx, -184(%rbp)
.Ltmp36:
.cfi_escape 0x2e, 0x00
movl $139, %edi
callq _Znwm
.Ltmp37:
# %bb.34: # %.noexc164
# in Loop: Header=BB2_33 Depth=1
movq %rax, %r15
movq %rax, -184(%rbp)
movq $138, -168(%rbp)
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $138, %edx
movq %rax, %rdi
callq memcpy@PLT
movq $138, -176(%rbp)
movb $0, 138(%r15)
.Ltmp39:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $104, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp40:
# %bb.35: # in Loop: Header=BB2_33 Depth=1
movq -184(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_37
# %bb.36: # %.critedge.i.i166
# in Loop: Header=BB2_33 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZdlPv
jmp .LBB2_37
.LBB2_38: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i146
movq -64(%rbp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
leaq -136(%rbp), %r14
movq %r14, -152(%rbp)
.Ltmp42:
.cfi_escape 0x2e, 0x00
movl $139, %edi
callq _Znwm
.Ltmp43:
# %bb.39: # %.noexc151
movq %rax, %rbx
movq %rax, -152(%rbp)
movq $138, -136(%rbp)
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $138, %edx
movq %rax, %rdi
callq memcpy@PLT
movq $138, -144(%rbp)
movb $0, 138(%rbx)
.Ltmp45:
.cfi_escape 0x2e, 0x00
leaq -152(%rbp), %rdi
movl $107, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp46:
# %bb.40:
movq -152(%rbp), %rdi
cmpq %r14, %rdi
je .LBB2_42
# %bb.41: # %.critedge.i.i172
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_42: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit174
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB2_66:
.cfi_def_cfa %rbp, 16
.Ltmp47:
movq %rax, %r15
movq -152(%rbp), %rdi
cmpq %r14, %rdi
je .LBB2_69
# %bb.67: # %.critedge.i.i175
.cfi_escape 0x2e, 0x00
jmp .LBB2_68
.LBB2_65:
.Ltmp44:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _Unwind_Resume@PLT
.LBB2_60:
.Ltmp35:
movq %rax, %r15
movq -216(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_69
# %bb.61: # %.critedge.i.i156
.cfi_escape 0x2e, 0x00
jmp .LBB2_68
.LBB2_59:
.Ltmp32:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _Unwind_Resume@PLT
.LBB2_57:
.Ltmp29:
movq %rax, %r15
movq -248(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_69
# %bb.58: # %.critedge.i.i153
.cfi_escape 0x2e, 0x00
jmp .LBB2_68
.LBB2_56:
.Ltmp26:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _Unwind_Resume@PLT
.LBB2_54:
.Ltmp23:
movq %rax, %r15
movq -280(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_69
# %bb.55: # %.critedge.i.i123
.cfi_escape 0x2e, 0x00
jmp .LBB2_68
.LBB2_53:
.Ltmp20:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _Unwind_Resume@PLT
.LBB2_51:
.Ltmp17:
movq %rax, %r15
movq -312(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_69
# %bb.52: # %.critedge.i.i120
.cfi_escape 0x2e, 0x00
jmp .LBB2_68
.LBB2_50:
.Ltmp14:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _Unwind_Resume@PLT
.LBB2_48:
.Ltmp11:
movq %rax, %r15
movq -344(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_69
# %bb.49: # %.critedge.i.i117
.cfi_escape 0x2e, 0x00
jmp .LBB2_68
.LBB2_47:
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _Unwind_Resume@PLT
.LBB2_62:
.Ltmp38:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _Unwind_Resume@PLT
.LBB2_63:
.Ltmp41:
movq %rax, %r15
movq -184(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB2_69
# %bb.64: # %.critedge.i.i169
.cfi_escape 0x2e, 0x00
jmp .LBB2_68
.LBB2_43:
.Ltmp2:
movq %rax, %r15
movq -408(%rbp), %rdi
cmpq %r14, %rdi
je .LBB2_69
# %bb.44: # %.critedge.i.i88
.cfi_escape 0x2e, 0x00
jmp .LBB2_68
.LBB2_45:
.Ltmp5:
movq %rax, %r15
movq -376(%rbp), %rdi
cmpq %r12, %rdi
je .LBB2_69
# %bb.46: # %.critedge.i.i91
.cfi_escape 0x2e, 0x00
.LBB2_68: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit125
callq _ZdlPv
.LBB2_69: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit90
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _Z17add_arrays_callerPPfii, .Lfunc_end2-_Z17add_arrays_callerPPfii
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp12-.Ltmp10 # Call between .Ltmp10 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp15-.Ltmp13 # Call between .Ltmp13 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp18-.Ltmp16 # Call between .Ltmp16 and .Ltmp18
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp21-.Ltmp19 # Call between .Ltmp19 and .Ltmp21
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp24-.Ltmp22 # Call between .Ltmp22 and .Ltmp24
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp27-.Ltmp25 # Call between .Ltmp25 and .Ltmp27
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 21 <<
.uleb128 .Ltmp30-.Ltmp28 # Call between .Ltmp28 and .Ltmp30
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 22 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin0 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 23 <<
.uleb128 .Ltmp33-.Ltmp31 # Call between .Ltmp31 and .Ltmp33
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 24 <<
.uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 25 <<
.uleb128 .Ltmp36-.Ltmp34 # Call between .Ltmp34 and .Ltmp36
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 26 <<
.uleb128 .Ltmp37-.Ltmp36 # Call between .Ltmp36 and .Ltmp37
.uleb128 .Ltmp38-.Lfunc_begin0 # jumps to .Ltmp38
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 27 <<
.uleb128 .Ltmp39-.Ltmp37 # Call between .Ltmp37 and .Ltmp39
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 28 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 29 <<
.uleb128 .Ltmp42-.Ltmp40 # Call between .Ltmp40 and .Ltmp42
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp42-.Lfunc_begin0 # >> Call Site 30 <<
.uleb128 .Ltmp43-.Ltmp42 # Call between .Ltmp42 and .Ltmp43
.uleb128 .Ltmp44-.Lfunc_begin0 # jumps to .Ltmp44
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 31 <<
.uleb128 .Ltmp45-.Ltmp43 # Call between .Ltmp43 and .Ltmp45
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 32 <<
.uleb128 .Ltmp46-.Ltmp45 # Call between .Ltmp45 and .Ltmp46
.uleb128 .Ltmp47-.Lfunc_begin0 # jumps to .Ltmp47
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin0 # >> Call Site 33 <<
.uleb128 .Lfunc_end2-.Ltmp46 # Call between .Ltmp46 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $80, %edi
callq _Znam
movq %rax, %rbx
movl $80, %edi
callq _Znam
movq %rax, %r14
movl $80, %edi
callq _Znam
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
xorl %eax, %eax
movl $3435973837, %ecx # imm = 0xCCCCCCCD
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %eax, %edx
imulq %rcx, %rdx
shrq $34, %rdx
leal (%rdx,%rdx,4), %edx
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
negl %edx
addl %eax, %edx
incl %edx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
movss %xmm0, (%rbx,%rax,4)
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB3_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $20, %rax
jne .LBB3_3
# %bb.4:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB3_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB3_8
.LBB3_7:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_19: # in Loop: Header=BB3_9 Depth=1
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB3_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
# in Loop: Header=BB3_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq $20, %r12
je .LBB3_12
.LBB3_9: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.6, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB3_33
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
# in Loop: Header=BB3_9 Depth=1
cmpb $0, 56(%r13)
je .LBB3_19
# %bb.11: # in Loop: Header=BB3_9 Depth=1
movzbl 67(%r13), %ecx
jmp .LBB3_20
.LBB3_12:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%r12)
je .LBB3_15
# %bb.14:
movzbl 67(%r12), %eax
jmp .LBB3_16
.LBB3_15:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorps %xmm0, %xmm0
movups %xmm0, (%r15)
movups %xmm0, 16(%r15)
movups %xmm0, 32(%r15)
movups %xmm0, 48(%r15)
movups %xmm0, 64(%r15)
movq %rbx, (%rsp)
movq %r14, 8(%rsp)
movq %r15, 16(%rsp)
movq %rsp, %rdi
movl $20, %esi
movl $2, %edx
callq _Z17add_arrays_callerPPfii
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i71
cmpb $0, 56(%r12)
je .LBB3_21
# %bb.18:
movzbl 67(%r12), %eax
jmp .LBB3_22
.LBB3_21:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit74
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
jmp .LBB3_23
.p2align 4, 0x90
.LBB3_31: # in Loop: Header=BB3_23 Depth=1
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB3_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit84
# in Loop: Header=BB3_23 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
cmpq $20, %r12
je .LBB3_26
.LBB3_23: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.6, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB3_33
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i81
# in Loop: Header=BB3_23 Depth=1
cmpb $0, 56(%r13)
je .LBB3_31
# %bb.25: # in Loop: Header=BB3_23 Depth=1
movzbl 67(%r13), %ecx
jmp .LBB3_32
.LBB3_26:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i76
cmpb $0, 56(%r12)
je .LBB3_29
# %bb.28:
movzbl 67(%r12), %eax
jmp .LBB3_30
.LBB3_29:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit79
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_33:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_arraysPPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", line "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ("
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type _Z10add_arraysPPfS_ii,@object # @_Z10add_arraysPPfS_ii
.section .rodata,"a",@progbits
.globl _Z10add_arraysPPfS_ii
.p2align 3, 0x0
_Z10add_arraysPPfS_ii:
.quad _Z25__device_stub__add_arraysPPfS_ii
.size _Z10add_arraysPPfS_ii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/shiviser/TUM_GPUComputerVision/master/cuda_team_warp64/exercises/2/add_arrays.hip"
.size .L.str.4, 139
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CPU:"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " + "
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " = "
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU:"
.size .L.str.8, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_arraysPPfS_ii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_arraysPPfS_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _Z10add_arraysPPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10add_arraysPPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff047624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0080*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*00a0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00b0*/ @!P0 BRA 0xd20 ; /* 0x00000c6000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0110*/ @!P0 BRA 0xc00 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R8, -R4, c[0x0][0x174], RZ ; /* 0x00005d0004087a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0140*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0150*/ SHF.L.U64.HI R6, R0.reuse, 0x2, R3 ; /* 0x0000000200067819 */
/* 0x040fe20000010203 */
/*0160*/ IMAD.SHL.U32 R7, R0, 0x4, RZ ; /* 0x0000000400077824 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0180*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0c7624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0d7624 */
/* 0x000fd400078e00ff */
/*01a0*/ @!P0 BRA 0xa60 ; /* 0x000008b000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x750 ; /* 0x0000057000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ LDG.E.64 R10, [R12.64] ; /* 0x000000080c0a7981 */
/* 0x000ea8000c1e1b00 */
/*0200*/ LDG.E.64 R24, [R12.64+0x8] ; /* 0x000008080c187981 */
/* 0x000ee8000c1e1b00 */
/*0210*/ LDG.E.64 R22, [R12.64+0x10] ; /* 0x000010080c167981 */
/* 0x000f28000c1e1b00 */
/*0220*/ LDG.E.64 R20, [R12.64+0x18] ; /* 0x000018080c147981 */
/* 0x000f68000c1e1b00 */
/*0230*/ LDG.E.64 R14, [R12.64+0x28] ; /* 0x000028080c0e7981 */
/* 0x000f28000c1e1b00 */
/*0240*/ LDG.E.64 R18, [R12.64+0x30] ; /* 0x000030080c127981 */
/* 0x000f68000c1e1b00 */
/*0250*/ LDG.E.64 R16, [R12.64+0x38] ; /* 0x000038080c107981 */
/* 0x000f62000c1e1b00 */
/*0260*/ IADD3 R26, P1, R10, R7, RZ ; /* 0x000000070a1a7210 */
/* 0x004fca0007f3e0ff */
/*0270*/ IMAD.X R27, R11, 0x1, R6, P1 ; /* 0x000000010b1b7824 */
/* 0x000fe400008e0606 */
/*0280*/ LDG.E.64 R10, [R12.64+0x20] ; /* 0x000020080c0a7981 */
/* 0x000ea8000c1e1b00 */
/*0290*/ LDG.E R26, [R26.64] ; /* 0x000000081a1a7981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IADD3 R28, P1, R24, R7, RZ ; /* 0x00000007181c7210 */
/* 0x008fca0007f3e0ff */
/*02b0*/ IMAD.X R29, R25, 0x1, R6, P1 ; /* 0x00000001191d7824 */
/* 0x000fe200008e0606 */
/*02c0*/ IADD3 R24, P1, R22, R7, RZ ; /* 0x0000000716187210 */
/* 0x010fc80007f3e0ff */
/*02d0*/ IADD3.X R25, R23, R6, RZ, P1, !PT ; /* 0x0000000617197210 */
/* 0x000fe20000ffe4ff */
/*02e0*/ LDG.E R2, [R28.64] ; /* 0x000000081c027981 */
/* 0x0000e2000c1e1900 */
/*02f0*/ IADD3 R20, P1, R20, R7, RZ ; /* 0x0000000714147210 */
/* 0x020fc60007f3e0ff */
/*0300*/ LDG.E R24, [R24.64] ; /* 0x0000000818187981 */
/* 0x000324000c1e1900 */
/*0310*/ IMAD.X R21, R21, 0x1, R6, P1 ; /* 0x0000000115157824 */
/* 0x000fe200008e0606 */
/*0320*/ IADD3 R14, P1, R14, R7, RZ ; /* 0x000000070e0e7210 */
/* 0x000fc80007f3e0ff */
/*0330*/ LDG.E R23, [R20.64] ; /* 0x0000000814177981 */
/* 0x000ae2000c1e1900 */
/*0340*/ IMAD.X R15, R15, 0x1, R6, P1 ; /* 0x000000010f0f7824 */
/* 0x000fe200008e0606 */
/*0350*/ IADD3 R28, P1, R18, R7, RZ ; /* 0x00000007121c7210 */
/* 0x001fc80007f3e0ff */
/*0360*/ LDG.E R21, [R14.64] ; /* 0x000000080e157981 */
/* 0x020162000c1e1900 */
/*0370*/ IMAD.X R29, R19, 0x1, R6, P1 ; /* 0x00000001131d7824 */
/* 0x000fca00008e0606 */
/*0380*/ LDG.E R20, [R28.64] ; /* 0x000000081c147981 */
/* 0x0002e8000c1e1900 */
/*0390*/ LDG.E.64 R14, [R12.64+0x58] ; /* 0x000058080c0e7981 */
/* 0x001e62000c1e1b00 */
/*03a0*/ IADD3 R10, P2, R10, R7, RZ ; /* 0x000000070a0a7210 */
/* 0x004fe20007f5e0ff */
/*03b0*/ FADD R5, R26, R5 ; /* 0x000000051a057221 */
/* 0x000fc80000000000 */
/*03c0*/ IMAD.X R11, R11, 0x1, R6, P2 ; /* 0x000000010b0b7824 */
/* 0x000fe200010e0606 */
/*03d0*/ LDG.E.64 R26, [R12.64+0x40] ; /* 0x000040080c1a7981 */
/* 0x000ea2000c1e1b00 */
/*03e0*/ IADD3 R18, P2, R16, R7, RZ ; /* 0x0000000710127210 */
/* 0x000fc60007f5e0ff */
/*03f0*/ LDG.E R22, [R10.64] ; /* 0x000000080a167981 */
/* 0x0000e2000c1e1900 */
/*0400*/ IADD3.X R19, R17, R6, RZ, P2, !PT ; /* 0x0000000611137210 */
/* 0x000fc600017fe4ff */
/*0410*/ LDG.E.64 R16, [R12.64+0x50] ; /* 0x000050080c107981 */
/* 0x000ee8000c1e1b00 */
/*0420*/ LDG.E R19, [R18.64] ; /* 0x0000000812137981 */
/* 0x0002e8000c1e1900 */
/*0430*/ LDG.E.64 R10, [R12.64+0x48] ; /* 0x000048080c0a7981 */
/* 0x001ee2000c1e1b00 */
/*0440*/ IADD3 R28, P2, R14, R7, RZ ; /* 0x000000070e1c7210 */
/* 0x002fca0007f5e0ff */
/*0450*/ IMAD.X R29, R15, 0x1, R6, P2 ; /* 0x000000010f1d7824 */
/* 0x000fe400010e0606 */
/*0460*/ LDG.E.64 R14, [R12.64+0x68] ; /* 0x000068080c0e7981 */
/* 0x000f28000c1e1b00 */
/*0470*/ LDG.E R9, [R28.64] ; /* 0x000000081c097981 */
/* 0x000162000c1e1900 */
/*0480*/ IADD3 R26, P1, R26, R7, RZ ; /* 0x000000071a1a7210 */
/* 0x004fca0007f3e0ff */
/*0490*/ IMAD.X R27, R27, 0x1, R6, P1 ; /* 0x000000011b1b7824 */
/* 0x000fca00008e0606 */
/*04a0*/ LDG.E R18, [R26.64] ; /* 0x000000081a127981 */
/* 0x0002a2000c1e1900 */
/*04b0*/ IADD3 R10, P1, R10, R7, RZ ; /* 0x000000070a0a7210 */
/* 0x008fca0007f3e0ff */
/*04c0*/ IMAD.X R11, R11, 0x1, R6, P1 ; /* 0x000000010b0b7824 */
/* 0x000fe200008e0606 */
/*04d0*/ IADD3 R26, P1, R16, R7, RZ ; /* 0x00000007101a7210 */
/* 0x002fca0007f3e0ff */
/*04e0*/ IMAD.X R27, R17, 0x1, R6, P1 ; /* 0x00000001111b7824 */
/* 0x000fe200008e0606 */
/*04f0*/ LDG.E R11, [R10.64] ; /* 0x000000080a0b7981 */
/* 0x0002e8000c1e1900 */
/*0500*/ LDG.E.64 R16, [R12.64+0x60] ; /* 0x000060080c107981 */
/* 0x000e28000c1e1b00 */
/*0510*/ LDG.E R10, [R26.64] ; /* 0x000000081a0a7981 */
/* 0x0028a4000c1e1900 */
/*0520*/ IADD3 R26, P2, R14, R7, RZ ; /* 0x000000070e1a7210 */
/* 0x010fca0007f5e0ff */
/*0530*/ IMAD.X R27, R15, 0x1, R6, P2 ; /* 0x000000010f1b7824 */
/* 0x000fe400010e0606 */
/*0540*/ LDG.E.64 R14, [R12.64+0x70] ; /* 0x000070080c0e7981 */
/* 0x000f28000c1e1b00 */
/*0550*/ LDG.E R26, [R26.64] ; /* 0x000000081a1a7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IADD3 R28, P1, R16, R7, RZ ; /* 0x00000007101c7210 */
/* 0x001fc80007f3e0ff */
/*0570*/ IADD3.X R29, R17, R6, RZ, P1, !PT ; /* 0x00000006111d7210 */
/* 0x000fe40000ffe4ff */
/*0580*/ LDG.E.64 R16, [R12.64+0x78] ; /* 0x000078080c107981 */
/* 0x000ea8000c1e1b00 */
/*0590*/ LDG.E R25, [R28.64] ; /* 0x000000081c197981 */
/* 0x000ee2000c1e1900 */
/*05a0*/ IADD3 R14, P1, R14, R7, RZ ; /* 0x000000070e0e7210 */
/* 0x010fca0007f3e0ff */
/*05b0*/ IMAD.X R15, R15, 0x1, R6, P1 ; /* 0x000000010f0f7824 */
/* 0x000fca00008e0606 */
/*05c0*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000f22000c1e1900 */
/*05d0*/ FADD R5, R5, R2 ; /* 0x0000000205057221 */
/* 0x000fc80000000000 */
/*05e0*/ FADD R24, R5, R24 ; /* 0x0000001805187221 */
/* 0x000fc80000000000 */
/*05f0*/ FADD R23, R24, R23 ; /* 0x0000001718177221 */
/* 0x000fe20000000000 */
/*0600*/ IADD3 R16, P1, R16, R7, RZ ; /* 0x0000000710107210 */
/* 0x004fca0007f3e0ff */
/*0610*/ IMAD.X R17, R17, 0x1, R6, P1 ; /* 0x0000000111117824 */
/* 0x000fca00008e0606 */
/*0620*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000ea2000c1e1900 */
/*0630*/ FADD R22, R23, R22 ; /* 0x0000001617167221 */
/* 0x000fc80000000000 */
/*0640*/ FADD R21, R22, R21 ; /* 0x0000001516157221 */
/* 0x020fc80000000000 */
/*0650*/ FADD R20, R21, R20 ; /* 0x0000001415147221 */
/* 0x000fc80000000000 */
/*0660*/ FADD R19, R20, R19 ; /* 0x0000001314137221 */
/* 0x000fc80000000000 */
/*0670*/ FADD R18, R19, R18 ; /* 0x0000001213127221 */
/* 0x000fc80000000000 */
/*0680*/ FADD R11, R18, R11 ; /* 0x0000000b120b7221 */
/* 0x008fe20000000000 */
/*0690*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*06a0*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x000fe20000000000 */
/*06b0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*06c0*/ FADD R10, R10, R9 ; /* 0x000000090a0a7221 */
/* 0x000fc80000000000 */
/*06d0*/ FADD R25, R10, R25 ; /* 0x000000190a197221 */
/* 0x000fe20000000000 */
/*06e0*/ IADD3 R12, P2, R12, 0x80, RZ ; /* 0x000000800c0c7810 */
/* 0x000fc60007f5e0ff */
/*06f0*/ FADD R25, R25, R26 ; /* 0x0000001a19197221 */
/* 0x000fe20000000000 */
/*0700*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc6000fffe03f */
/*0710*/ FADD R25, R25, R14 ; /* 0x0000000e19197221 */
/* 0x010fe40000000000 */
/*0720*/ IMAD.X R13, RZ, RZ, R13, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe400010e060d */
/*0730*/ FADD R5, R25, R16 ; /* 0x0000001019057221 */
/* 0x004fe20000000000 */
/*0740*/ @P1 BRA 0x1f0 ; /* 0xfffffaa000001947 */
/* 0x000fea000383ffff */
/*0750*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0760*/ @!P1 BRA 0xa40 ; /* 0x000002d000009947 */
/* 0x000fea0003800000 */
/*0770*/ LDG.E.64 R26, [R12.64] ; /* 0x000000080c1a7981 */
/* 0x000ea8000c1e1b00 */
/*0780*/ LDG.E.64 R18, [R12.64+0x8] ; /* 0x000008080c127981 */
/* 0x000ee8000c1e1b00 */
/*0790*/ LDG.E.64 R20, [R12.64+0x10] ; /* 0x000010080c147981 */
/* 0x000f28000c1e1b00 */
/*07a0*/ LDG.E.64 R22, [R12.64+0x18] ; /* 0x000018080c167981 */
/* 0x000f68000c1e1b00 */
/*07b0*/ LDG.E.64 R24, [R12.64+0x20] ; /* 0x000020080c187981 */
/* 0x000f68000c1e1b00 */
/*07c0*/ LDG.E.64 R10, [R12.64+0x28] ; /* 0x000028080c0a7981 */
/* 0x000f68000c1e1b00 */
/*07d0*/ LDG.E.64 R14, [R12.64+0x30] ; /* 0x000030080c0e7981 */
/* 0x000f68000c1e1b00 */
/*07e0*/ LDG.E.64 R16, [R12.64+0x38] ; /* 0x000038080c107981 */
/* 0x000f62000c1e1b00 */
/*07f0*/ IADD3 R26, P0, R26, R7, RZ ; /* 0x000000071a1a7210 */
/* 0x004fc80007f1e0ff */
/*0800*/ IADD3.X R27, R27, R6, RZ, P0, !PT ; /* 0x000000061b1b7210 */
/* 0x000fe400007fe4ff */
/*0810*/ IADD3 R18, P0, R18, R7, RZ ; /* 0x0000000712127210 */
/* 0x008fc60007f1e0ff */
/*0820*/ LDG.E R2, [R26.64] ; /* 0x000000081a027981 */
/* 0x000ea4000c1e1900 */
/*0830*/ IMAD.X R19, R19, 0x1, R6, P0 ; /* 0x0000000113137824 */
/* 0x000fe200000e0606 */
/*0840*/ IADD3 R20, P0, R20, R7, RZ ; /* 0x0000000714147210 */
/* 0x010fc80007f1e0ff */
/*0850*/ LDG.E R18, [R18.64] ; /* 0x0000000812127981 */
/* 0x000ee2000c1e1900 */
/*0860*/ IMAD.X R21, R21, 0x1, R6, P0 ; /* 0x0000000115157824 */
/* 0x000fe200000e0606 */
/*0870*/ IADD3 R22, P0, R22, R7, RZ ; /* 0x0000000716167210 */
/* 0x020fc80007f1e0ff */
/*0880*/ LDG.E R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000f22000c1e1900 */
/*0890*/ IMAD.X R23, R23, 0x1, R6.reuse, P0 ; /* 0x0000000117177824 */
/* 0x100fe200000e0606 */
/*08a0*/ IADD3 R24, P0, R24, R7.reuse, RZ ; /* 0x0000000718187210 */
/* 0x080fe40007f1e0ff */
/*08b0*/ IADD3 R10, P1, R10, R7.reuse, RZ ; /* 0x000000070a0a7210 */
/* 0x080fe40007f3e0ff */
/*08c0*/ LDG.E R22, [R22.64] ; /* 0x0000000816167981 */
/* 0x000f62000c1e1900 */
/*08d0*/ IMAD.X R25, R25, 0x1, R6, P0 ; /* 0x0000000119197824 */
/* 0x000fe200000e0606 */
/*08e0*/ IADD3 R14, P0, R14, R7, RZ ; /* 0x000000070e0e7210 */
/* 0x000fe40007f1e0ff */
/*08f0*/ IADD3.X R11, R11, R6, RZ, P1, !PT ; /* 0x000000060b0b7210 */
/* 0x000fc40000ffe4ff */
/*0900*/ LDG.E R24, [R24.64] ; /* 0x0000000818187981 */
/* 0x000f62000c1e1900 */
/*0910*/ IMAD.X R15, R15, 0x1, R6.reuse, P0 ; /* 0x000000010f0f7824 */
/* 0x100fe200000e0606 */
/*0920*/ IADD3 R16, P0, R16, R7, RZ ; /* 0x0000000710107210 */
/* 0x000fe40007f1e0ff */
/*0930*/ LDG.E R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000f66000c1e1900 */
/*0940*/ IMAD.X R17, R17, 0x1, R6, P0 ; /* 0x0000000111117824 */
/* 0x000fe200000e0606 */
/*0950*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000f68000c1e1900 */
/*0960*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000f62000c1e1900 */
/*0970*/ IADD3 R12, P1, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x000fc40007f3e0ff */
/*0980*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0990*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e060d */
/*09b0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*09c0*/ FADD R5, R5, R2 ; /* 0x0000000205057221 */
/* 0x004fc80000000000 */
/*09d0*/ FADD R5, R5, R18 ; /* 0x0000001205057221 */
/* 0x008fc80000000000 */
/*09e0*/ FADD R5, R5, R20 ; /* 0x0000001405057221 */
/* 0x010fc80000000000 */
/*09f0*/ FADD R5, R5, R22 ; /* 0x0000001605057221 */
/* 0x020fc80000000000 */
/*0a00*/ FADD R5, R5, R24 ; /* 0x0000001805057221 */
/* 0x000fc80000000000 */
/*0a10*/ FADD R5, R5, R10 ; /* 0x0000000a05057221 */
/* 0x000fc80000000000 */
/*0a20*/ FADD R5, R5, R14 ; /* 0x0000000e05057221 */
/* 0x000fc80000000000 */
/*0a30*/ FADD R5, R5, R16 ; /* 0x0000001005057221 */
/* 0x000fe40000000000 */
/*0a40*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0a50*/ @!P0 BRA 0xc00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a60*/ LDG.E.64 R14, [R12.64] ; /* 0x000000080c0e7981 */
/* 0x000ea8000c1e1b00 */
/*0a70*/ LDG.E.64 R18, [R12.64+0x8] ; /* 0x000008080c127981 */
/* 0x000ee8000c1e1b00 */
/*0a80*/ LDG.E.64 R16, [R12.64+0x10] ; /* 0x000010080c107981 */
/* 0x000f28000c1e1b00 */
/*0a90*/ LDG.E.64 R10, [R12.64+0x18] ; /* 0x000018080c0a7981 */
/* 0x000f62000c1e1b00 */
/*0aa0*/ IADD3 R20, P0, R14, R7, RZ ; /* 0x000000070e147210 */
/* 0x004fca0007f1e0ff */
/*0ab0*/ IMAD.X R21, R15, 0x1, R6.reuse, P0 ; /* 0x000000010f157824 */
/* 0x100fe200000e0606 */
/*0ac0*/ IADD3 R14, P0, R18, R7.reuse, RZ ; /* 0x00000007120e7210 */
/* 0x088fe40007f1e0ff */
/*0ad0*/ IADD3 R16, P1, R16, R7.reuse, RZ ; /* 0x0000000710107210 */
/* 0x090fe40007f3e0ff */
/*0ae0*/ IADD3.X R15, R19, R6, RZ, P0, !PT ; /* 0x00000006130f7210 */
/* 0x000fe200007fe4ff */
/*0af0*/ LDG.E R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000ea2000c1e1900 */
/*0b00*/ IADD3 R10, P0, R10, R7, RZ ; /* 0x000000070a0a7210 */
/* 0x020fe20007f1e0ff */
/*0b10*/ IMAD.X R17, R17, 0x1, R6.reuse, P1 ; /* 0x0000000111117824 */
/* 0x100fe400008e0606 */
/*0b20*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000ee4000c1e1900 */
/*0b30*/ IMAD.X R11, R11, 0x1, R6, P0 ; /* 0x000000010b0b7824 */
/* 0x000fc400000e0606 */
/*0b40*/ LDG.E R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000f28000c1e1900 */
/*0b50*/ LDG.E R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000f62000c1e1900 */
/*0b60*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0b70*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0b80*/ IADD3 R12, P1, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x000fe40007f3e0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f05270 */
/*0ba0*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e060d */
/*0bb0*/ FADD R5, R20, R5 ; /* 0x0000000514057221 */
/* 0x004fc80000000000 */
/*0bc0*/ FADD R5, R5, R14 ; /* 0x0000000e05057221 */
/* 0x008fc80000000000 */
/*0bd0*/ FADD R5, R5, R16 ; /* 0x0000001005057221 */
/* 0x010fc80000000000 */
/*0be0*/ FADD R5, R5, R10 ; /* 0x0000000a05057221 */
/* 0x020fe20000000000 */
/*0bf0*/ @P0 BRA 0xa60 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0c00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0c10*/ @!P0 BRA 0xd20 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0c20*/ SHF.L.U64.HI R11, R0, 0x2, R3 ; /* 0x00000002000b7819 */
/* 0x000fe20000010203 */
/*0c30*/ UMOV UR5, 0x8 ; /* 0x0000000800057882 */
/* 0x000fe40000000000 */
/*0c40*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0c50*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*0c60*/ MOV R6, UR4 ; /* 0x0000000400067c02 */
/* 0x000fe20008000f00 */
/*0c70*/ IMAD.U32 R7, RZ, RZ, UR5 ; /* 0x00000005ff077e24 */
/* 0x000fcc000f8e00ff */
/*0c80*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ea2000c1e1b00 */
/*0c90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ca0*/ LEA R8, P0, R0, R6, 0x2 ; /* 0x0000000600087211 */
/* 0x004fca00078010ff */
/*0cb0*/ IMAD.X R9, R7, 0x1, R11, P0 ; /* 0x0000000107097824 */
/* 0x000fca00000e060b */
/*0cc0*/ LDG.E R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000ea2000c1e1900 */
/*0cd0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0ce0*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fc8000ff1e03f */
/*0cf0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0d00*/ FADD R5, R8, R5 ; /* 0x0000000508057221 */
/* 0x004fce0000000000 */
/*0d10*/ @P0 BRA 0xc60 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0d20*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0d30*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f1403 */
/*0d40*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*0d50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d60*/ BRA 0xd60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_arraysPPfS_ii
.globl _Z10add_arraysPPfS_ii
.p2align 8
.type _Z10add_arraysPPfS_ii,@function
_Z10add_arraysPPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b32 s4, s[0:1], 0x14
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, 0
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_load_b64 s[6:7], s[2:3], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
flat_load_b32 v5, v[5:6]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v0, v0, v5
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_arraysPPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_arraysPPfS_ii, .Lfunc_end0-_Z10add_arraysPPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_arraysPPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_arraysPPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <vector>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
int main(int argc, char **argv)
{
thrust::host_vector<int> h_vec(100);
std::vector<int> a_std(100);
thrust::generate(h_vec.begin(), h_vec.end(), rand);
thrust::copy(h_vec.begin(), h_vec.end(), a_std.begin());
printf("%d\n", a_std[0]);
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <vector>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
int main(int argc, char **argv)
{
thrust::host_vector<int> h_vec(100);
std::vector<int> a_std(100);
thrust::generate(h_vec.begin(), h_vec.end(), rand);
thrust::copy(h_vec.begin(), h_vec.end(), a_std.begin());
printf("%d\n", a_std[0]);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <vector>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
int main(int argc, char **argv)
{
thrust::host_vector<int> h_vec(100);
std::vector<int> a_std(100);
thrust::generate(h_vec.begin(), h_vec.end(), rand);
thrust::copy(h_vec.begin(), h_vec.end(), a_std.begin());
printf("%d\n", a_std[0]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <vector>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
int main(int argc, char **argv)
{
thrust::host_vector<int> h_vec(100);
std::vector<int> a_std(100);
thrust::generate(h_vec.begin(), h_vec.end(), rand);
thrust::copy(h_vec.begin(), h_vec.end(), a_std.begin());
printf("%d\n", a_std[0]);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <vector>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <algorithm>
int main(int argc, char **argv)
{
thrust::host_vector<int> h_vec(100);
std::vector<int> a_std(100);
thrust::generate(h_vec.begin(), h_vec.end(), rand);
thrust::copy(h_vec.begin(), h_vec.end(), a_std.begin());
printf("%d\n", a_std[0]);
return 0;
} | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZN6thrust11host_vectorIiSaIiEEC2Em.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq _Znwm
movq %rax, %rbx
movl $400, %edx # imm = 0x190
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
movl $400, %edi # imm = 0x190
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
movq %rax, %r14
xorl %r15d, %r15d
movl $400, %edx # imm = 0x190
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_2: # %.lr.ph.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r15)
addq $4, %r15
cmpq $400, %r15 # imm = 0x190
jne .LBB0_2
# %bb.3: # %_ZN6thrust8generateINS_6detail15normal_iteratorIPiEEPDoFivEEEvT_S7_T0_.exit
movl $400, %edx # imm = 0x190
movq %r14, %rdi
movq %rbx, %rsi
callq memcpy@PLT
movl (%r14), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %r14, %rdi
callq _ZdlPv
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_4: # %_ZN6thrust6detail11vector_baseIiSaIiEED2Ev.exit15
.cfi_def_cfa_offset 32
.Ltmp2:
movq %rax, %r14
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end0-.Ltmp1 # Call between .Ltmp1 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // This code is copied from https://github.com/msracver/Deep-Image-Analogy
#include <stdio.h>
#include <curand_kernel.h>
#define FLT_MIN 1.175494351e-38F
__host__ __device__ int clamp(int x, int x_max, int x_min) {//assume x_max >= x_min
if (x > x_max)
{
return x_max;
}
else if (x < x_min)
{
return x_min;
}
else
{
return x;
}
}
__host__ __device__ unsigned int XY_TO_INT(int x, int y) {//r represent the number of 10 degree, x,y - 11 bits, max = 2047, r - max = 36, 6 bits
return (((y) << 11) | (x));
}
__host__ __device__ int INT_TO_X(unsigned int v) {
return (v)&((1 << 11) - 1);
}
__host__ __device__ int INT_TO_Y(unsigned int v) {
return (v >> 11)&((1 << 11) - 1);
}
__host__ __device__ int cuMax(int a, int b) {
if (a > b) {
return a;
}
else {
return b;
}
}
__host__ __device__ int cuMin(int a, int b) {
if (a < b) {
return a;
}
else {
return b;
}
}
__device__ float MycuRand(curandState &state) {//random number in cuda, between 0 and 1
return curand_uniform(&state);
}
__device__ void InitcuRand(curandState &state) {//random number in cuda, between 0 and 1
int i = threadIdx.x + blockIdx.x * blockDim.x;
curand_init(i, 0, 0, &state);
}
__host__ __device__ float dist_compute(float * a, float * b, float * a1, float * b1, int channels, int a_rows, int a_cols, int b_rows, int b_cols, int ax, int ay, int bx, int by, int patch_w, float cutoff = INT_MAX) {//this is the average number of all matched pixel //suppose patch_w is an odd number
float pixel_sum = 0, pixel_no = 0, pixel_dist = 0;//number of pixels realy counted
float pixel_sum1 = 0;
int a_slice = a_rows*a_cols, b_slice = b_rows*b_cols;
int a_pitch = a_cols, b_pitch = b_cols;
float dp_tmp;
for (int dy = -patch_w / 2; dy <= patch_w / 2; dy++) {
for (int dx = -patch_w / 2; dx <= patch_w / 2; dx++) {
if (
(ay + dy) < a_rows && (ay + dy) >= 0 && (ax + dx) < a_cols && (ax + dx) >= 0
&&
(by + dy) < b_rows && (by + dy) >= 0 && (bx + dx) < b_cols && (bx + dx) >= 0
)//the pixel in a should exist and pixel in b should exist
{
if (channels == 3)
{
for (int dc = 0; dc < channels; dc++)
{
dp_tmp = a[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] - b[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum += dp_tmp * dp_tmp;
dp_tmp = a1[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] - b1[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum1 += dp_tmp * dp_tmp;
}
}
else
{
for (int dc = 0; dc < channels; dc++)
{
dp_tmp = a[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] * b[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum -= dp_tmp;
dp_tmp = a1[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] * b1[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum1 -= dp_tmp;
}
}
pixel_no += 1;
}
}
}
pixel_dist = (pixel_sum + pixel_sum1) / pixel_no;
if (pixel_dist >= cutoff) { return cutoff; }
else {
return pixel_dist;
}
}
__host__ __device__ float dist(float * a, float * b, float *a1, float *b1, int channels, int a_rows, int a_cols, int b_rows, int b_cols, int ax, int ay, int xp, int yp, int patch_w, float cutoff = INT_MAX) {
return dist_compute(a, b, a1, b1, channels, a_rows, a_cols, b_rows, b_cols, ax, ay, xp, yp, patch_w, cutoff);
}
__device__ void improve_guess(float * a, float * b, float *a1, float *b1, int channels, int a_rows, int a_cols, int b_rows, int b_cols, int ax, int ay, int &xbest, int &ybest, float &dbest, int xp, int yp, int patch_w, float rr) {
float d;
d = dist(a, b, a1, b1, channels, a_rows, a_cols, b_rows, b_cols, ax, ay, xp, yp, patch_w);
if (d + rr < dbest) {
xbest = xp;
ybest = yp;
dbest = d;
}
}
__global__ void initialAnn_kernel(unsigned int * ann, int * params) {
//just use 7 of 9 parameters
int ah = params[1];
int aw = params[2];
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
if (ax < aw && ay < ah) {
int bx = ax;
int by = ay;
ann[ay*aw + ax] = XY_TO_INT(bx, by);
}
}
__global__ void upSample_kernel(unsigned int * ann, unsigned int * ann_tmp,int * params, int aw_half,int ah_half) {
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
int ah = params[1];
int aw = params[2];
int bh = params[3];
int bw = params[4];
float aw_ratio = (float)aw / (float)aw_half;
float ah_ratio = (float)ah / (float)ah_half;
int ax_half = (ax+0.5) / aw_ratio;
int ay_half = (ay+0.5) / ah_ratio;
ax_half = clamp(ax_half, aw_half - 1, 0);
ay_half = clamp(ay_half, ah_half - 1, 0);
if (ax < aw&&ay < ah) {
unsigned int v_half = ann[ay_half*aw_half + ax_half];
int bx_half = INT_TO_X(v_half);
int by_half = INT_TO_Y(v_half);
int bx = ax + (bx_half - ax_half)*aw_ratio + 0.5;
int by = ay + (by_half - ay_half)*ah_ratio + 0.5;
bx = clamp(bx, bw-1, 0);
by = clamp(by, bh-1, 0);
ann_tmp[ay*aw + ax] = XY_TO_INT(bx, by);
}
}
extern "C"
__global__ void patch_match(float * a, float * b, float *a1, float *b1, unsigned int *ann, float *annd, int ch, int a_rows, int a_cols, int b_rows, int b_cols, int patch_w, int pm_iters, int rs_max) {
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
if (ax < a_cols && ay < a_rows) {
// for random number
curandState state;
InitcuRand(state);
unsigned int v, vp;
int xp, yp, xbest, ybest;
int xmin, xmax, ymin, ymax;
float dbest;
v = ann[ay*a_cols + ax];
xbest = INT_TO_X(v), ybest = INT_TO_Y(v);
annd[ay*a_cols + ax] = dist(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, patch_w);
for (int iter = 0; iter < pm_iters; iter++) {
/* Current (best) guess. */
v = ann[ay*a_cols + ax];
xbest = INT_TO_X(v), ybest = INT_TO_Y(v);
dbest = annd[ay*a_cols + ax];
/* In each iteration, improve the NNF, by jumping flooding. */
for (int jump = 8; jump > 0; jump /= 2) {
/* Propagation: Improve current guess by trying instead correspondences from left, right, up and downs. */
if ((ax - jump) < a_cols && (ax - jump) >= 0)//left
{
vp = ann[ay*a_cols + ax - jump];//the pixel coordinates in image b
xp = INT_TO_X(vp) + jump, yp = INT_TO_Y(vp);//the propagated match from vp, the center of the patch, which should be in the image
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
if ((ax + jump) < a_cols)//right
{
vp = ann[ay*a_cols + ax + jump];//the pixel coordinates in image b
xp = INT_TO_X(vp) - jump, yp = INT_TO_Y(vp);
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
if ((ay - jump) < a_rows && (ay - jump) >= 0)//up
{
vp = ann[(ay - jump)*a_cols + ax];//the pixel coordinates in image b
xp = INT_TO_X(vp), yp = INT_TO_Y(vp) + jump;
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
if ((ay + jump) < a_rows)//down
{
vp = ann[(ay + jump)*a_cols + ax];//the pixel coordinates in image b
xp = INT_TO_X(vp), yp = INT_TO_Y(vp) - jump;
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
}
/* Random search: Improve current guess by searching in boxes of exponentially decreasing size around the current best guess. */
int rs_start = rs_max;
for (int mag = rs_start; mag >= 1; mag /= 2) {
/* Sampling window */
xmin = cuMax(xbest - mag, 0), xmax = cuMin(xbest + mag + 1, b_cols);
ymin = cuMax(ybest - mag, 0), ymax = cuMin(ybest + mag + 1, b_rows);
xp = xmin + (int)(MycuRand(state)*(xmax - xmin)) % (xmax - xmin);
yp = ymin + (int)(MycuRand(state)*(ymax - ymin)) % (ymax - ymin);
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, FLT_MIN);
}
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
__syncthreads();
}
}
}
__global__ void blend(float *cmap, float* oldd, float* newd, float weight,int * params)
{
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
int ch = params[0];
int ah = params[1];
int aw = params[2];
int slice_a = ah * aw;
int pitch_a = aw;
float thre = 0.05;
if (ax < aw&& ay < ah)
{
float fa = cmap[ay*pitch_a + ax];
if (fa < thre)
fa = 0.0f;
else fa = weight;
for (int i = 0; i < ch; i++)
{
newd[i*slice_a + ay*pitch_a + ax] = oldd[i*slice_a + ay*pitch_a + ax]* fa + newd[i*slice_a + ay*pitch_a + ax] * (1.0-fa);
}
}
}
// ********** VOTE ***********
extern "C"
__global__ void avg_vote(unsigned int * ann, float * pb, float * pc, int ch, int ah, int aw, int bh, int bw, int patch_w) {
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
int slice_a = ah * aw;
int pitch_a = aw;
int slice_b = bh * bw;
int pitch_b = bw;
int count = 0;
if (ax < aw&&ay < ah)
{
//set zero for all the channels at (ax,ay)
for (int i = 0; i < ch; i++)
{
pc[i*slice_a + ay*pitch_a + ax] = 0;
}
//count the sum of all the possible value of (ax,ay)
for (int dx = -patch_w / 2; dx <= patch_w / 2; dx++) {
for (int dy = -patch_w / 2; dy <= patch_w / 2; dy++)
{
if ((ax + dx) < aw && (ax + dx) >= 0 && (ay + dy) < ah && (ay + dy) >= 0)
{
unsigned int vp = ann[(ay + dy)*aw + ax + dx];
int xp = INT_TO_X(vp);
int yp = INT_TO_Y(vp);
if ((xp - dx) < bw && (xp - dx) >= 0 && (yp - dy) < bh && (yp - dy) >= 0)
{
count++;
for (int dc = 0; dc < ch; dc++)
{
pc[dc*slice_a + ay*pitch_a + ax] += pb[dc*slice_b + (yp - dy)*pitch_b + xp - dx];
}
}
}
}
}
//count average value
for (int i = 0; i < ch; i++)
{
pc[i*slice_a + ay*pitch_a + ax] /= count;
}
}
} | .file "tmpxft_000eaadc_00000000-6_GeneralizedPatchMatch.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2284:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2284:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5clampiii
.type _Z5clampiii, @function
_Z5clampiii:
.LFB2271:
.cfi_startproc
endbr64
cmpl %edx, %edi
cmovge %edi, %edx
cmpl %esi, %edi
movl %esi, %eax
cmovle %edx, %eax
ret
.cfi_endproc
.LFE2271:
.size _Z5clampiii, .-_Z5clampiii
.globl _Z9XY_TO_INTii
.type _Z9XY_TO_INTii, @function
_Z9XY_TO_INTii:
.LFB2272:
.cfi_startproc
endbr64
movl %esi, %eax
sall $11, %eax
orl %edi, %eax
ret
.cfi_endproc
.LFE2272:
.size _Z9XY_TO_INTii, .-_Z9XY_TO_INTii
.globl _Z8INT_TO_Xj
.type _Z8INT_TO_Xj, @function
_Z8INT_TO_Xj:
.LFB2273:
.cfi_startproc
endbr64
movl %edi, %eax
andl $2047, %eax
ret
.cfi_endproc
.LFE2273:
.size _Z8INT_TO_Xj, .-_Z8INT_TO_Xj
.globl _Z8INT_TO_Yj
.type _Z8INT_TO_Yj, @function
_Z8INT_TO_Yj:
.LFB2274:
.cfi_startproc
endbr64
movl %edi, %eax
shrl $11, %eax
andl $2047, %eax
ret
.cfi_endproc
.LFE2274:
.size _Z8INT_TO_Yj, .-_Z8INT_TO_Yj
.globl _Z5cuMaxii
.type _Z5cuMaxii, @function
_Z5cuMaxii:
.LFB2275:
.cfi_startproc
endbr64
cmpl %esi, %edi
movl %esi, %eax
cmovge %edi, %eax
ret
.cfi_endproc
.LFE2275:
.size _Z5cuMaxii, .-_Z5cuMaxii
.globl _Z5cuMinii
.type _Z5cuMinii, @function
_Z5cuMinii:
.LFB2276:
.cfi_startproc
endbr64
cmpl %esi, %edi
movl %esi, %eax
cmovle %edi, %eax
ret
.cfi_endproc
.LFE2276:
.size _Z5cuMinii, .-_Z5cuMinii
.globl _Z8MycuRandR17curandStateXORWOW
.type _Z8MycuRandR17curandStateXORWOW, @function
_Z8MycuRandR17curandStateXORWOW:
.LFB2277:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2277:
.size _Z8MycuRandR17curandStateXORWOW, .-_Z8MycuRandR17curandStateXORWOW
.globl _Z10InitcuRandR17curandStateXORWOW
.type _Z10InitcuRandR17curandStateXORWOW, @function
_Z10InitcuRandR17curandStateXORWOW:
.LFB2278:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2278:
.size _Z10InitcuRandR17curandStateXORWOW, .-_Z10InitcuRandR17curandStateXORWOW
.globl _Z12dist_computePfS_S_S_iiiiiiiiiif
.type _Z12dist_computePfS_S_S_iiiiiiiiiif, @function
_Z12dist_computePfS_S_S_iiiiiiiiiif:
.LFB2279:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, -72(%rsp)
movq %rsi, -64(%rsp)
movq %rdx, -56(%rsp)
movq %rcx, -48(%rsp)
movl %r8d, -80(%rsp)
movl 56(%rsp), %r11d
movl 72(%rsp), %r14d
movl 80(%rsp), %ebx
movl 88(%rsp), %ecx
movl 96(%rsp), %r13d
movl 112(%rsp), %edx
movl %r9d, %eax
imull %r11d, %eax
movl %eax, -76(%rsp)
movl %r14d, %eax
imull 64(%rsp), %eax
movl %eax, -16(%rsp)
movl %edx, %eax
shrl $31, %eax
addl %eax, %edx
sarl %edx
negl %edx
movl %edx, %esi
negl %esi
cmpl %esi, %edx
jg .L16
movaps %xmm0, %xmm3
movl %edx, %r10d
movl %edx, %r8d
addl 104(%rsp), %r8d
leal (%rdx,%rcx), %esi
movl %esi, %ebp
imull %r11d, %ebp
movl %r8d, %r15d
imull %r14d, %r15d
addl $1, %ecx
subl %edx, %ecx
movl %ecx, %r12d
pxor %xmm2, %xmm2
movaps %xmm2, %xmm4
movaps %xmm2, %xmm0
leal 1(%rbx), %edi
subl %edx, %edi
movl %ebp, %r14d
jmp .L17
.L19:
movslq -76(%rsp), %r10
leaq 0(,%r10,4), %rbp
movq %rbp, -40(%rsp)
movslq %r14d, %r10
movslq -96(%rsp), %rbp
addq %rbp, %r10
salq $2, %r10
movq %r10, -96(%rsp)
movslq -16(%rsp), %rbp
salq $2, %rbp
movq %rbp, -32(%rsp)
movslq -84(%rsp), %rbp
movslq %r15d, %r10
addq %rbp, %r10
leaq 0(,%r10,4), %rbp
movq -96(%rsp), %r10
movl %r12d, -96(%rsp)
movl %eax, -24(%rsp)
movq %rbp, %rax
movl %edx, -12(%rsp)
movl $3, %edx
movl %r8d, -84(%rsp)
movl %esi, -8(%rsp)
movq -40(%rsp), %rsi
movl %r14d, -40(%rsp)
movl %edi, -4(%rsp)
movq -32(%rsp), %rdi
movq -72(%rsp), %r8
movq -64(%rsp), %rbp
movq -56(%rsp), %r12
movq -48(%rsp), %r14
.L22:
movss (%r8,%r10), %xmm1
subss 0(%rbp,%rax), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
movss (%r12,%r10), %xmm1
subss (%r14,%rax), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm2
addq %rsi, %r10
addq %rdi, %rax
subl $1, %edx
jne .L22
movl -96(%rsp), %r12d
movl -24(%rsp), %eax
movl -12(%rsp), %edx
movl -84(%rsp), %r8d
movl -8(%rsp), %esi
movl -40(%rsp), %r14d
movl -4(%rsp), %edi
jmp .L21
.L23:
movss (%r8,%r10), %xmm1
mulss 0(%rbp,%rax), %xmm1
subss %xmm1, %xmm0
movss (%r12,%r10), %xmm1
mulss (%r14,%rax), %xmm1
subss %xmm1, %xmm2
addl $1, %edx
addq %rsi, %r10
addq %rdi, %rax
cmpl %edx, %ecx
jne .L23
movl -84(%rsp), %r12d
movl -40(%rsp), %eax
movl -12(%rsp), %edx
movl -96(%rsp), %r8d
movl -8(%rsp), %esi
movl -32(%rsp), %r14d
movl -4(%rsp), %edi
movl -24(%rsp), %ecx
.L21:
addss .LC1(%rip), %xmm4
.L18:
addl $1, %eax
addl $1, %edx
cmpl %edi, %eax
je .L33
.L24:
testb %cl, %cl
je .L18
cmpl %esi, %r9d
jle .L18
movl %eax, -96(%rsp)
movl %eax, %r10d
orl %r8d, %r10d
js .L18
cmpl %r11d, %eax
jge .L18
cmpl %r8d, 64(%rsp)
jle .L18
movl %edx, -84(%rsp)
testl %edx, %edx
js .L18
cmpl 72(%rsp), %edx
jge .L18
movl -80(%rsp), %r10d
cmpl $3, %r10d
je .L19
testl %r10d, %r10d
jle .L21
movslq -76(%rsp), %r10
salq $2, %r10
movq %r10, -32(%rsp)
movslq -96(%rsp), %rbp
movslq %r14d, %r10
addq %rbp, %r10
salq $2, %r10
movq %r10, -40(%rsp)
movslq -16(%rsp), %r10
salq $2, %r10
movq %r10, -24(%rsp)
movslq -84(%rsp), %r10
movq %r10, -96(%rsp)
movslq %r15d, %r10
movq %r10, %rbp
movq -96(%rsp), %r10
addq %r10, %rbp
salq $2, %rbp
movl %r12d, -84(%rsp)
movq -40(%rsp), %r10
movl %eax, -40(%rsp)
movq %rbp, %rax
movl %edx, -12(%rsp)
movl $0, %edx
movl %r8d, -96(%rsp)
movl %esi, -8(%rsp)
movq -32(%rsp), %rsi
movl %r14d, -32(%rsp)
movl %edi, -4(%rsp)
movq -24(%rsp), %rdi
movq -72(%rsp), %r8
movq -64(%rsp), %rbp
movq -56(%rsp), %r12
movq -48(%rsp), %r14
movl %ecx, -24(%rsp)
movl -80(%rsp), %ecx
jmp .L23
.L33:
movl -88(%rsp), %r10d
addl $1, %r8d
addl $1, %esi
addl %r11d, %r14d
addl 72(%rsp), %r15d
cmpl %esi, %r12d
je .L25
.L17:
leal (%rbx,%r10), %eax
leal 0(%r13,%r10), %edx
movl %esi, %ecx
notl %ecx
shrl $31, %ecx
movl %r10d, -88(%rsp)
jmp .L24
.L25:
addss %xmm2, %xmm0
divss %xmm4, %xmm0
movaps %xmm3, %xmm1
cmpnless %xmm0, %xmm1
andps %xmm1, %xmm0
andnps %xmm3, %xmm1
orps %xmm1, %xmm0
.L15:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pxor %xmm0, %xmm0
divss %xmm0, %xmm0
jmp .L15
.cfi_endproc
.LFE2279:
.size _Z12dist_computePfS_S_S_iiiiiiiiiif, .-_Z12dist_computePfS_S_S_iiiiiiiiiif
.globl _Z4distPfS_S_S_iiiiiiiiiif
.type _Z4distPfS_S_S_iiiiiiiiiif, @function
_Z4distPfS_S_S_iiiiiiiiiif:
.LFB2280:
.cfi_startproc
endbr64
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 16
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
call _Z12dist_computePfS_S_S_iiiiiiiiiif
addq $64, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2280:
.size _Z4distPfS_S_S_iiiiiiiiiif, .-_Z4distPfS_S_S_iiiiiiiiiif
.globl _Z13improve_guessPfS_S_S_iiiiiiiRiS0_Rfiiif
.type _Z13improve_guessPfS_S_S_iiiiiiiRiS0_Rfiiif, @function
_Z13improve_guessPfS_S_S_iiiiiiiRiS0_Rfiiif:
.LFB2281:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2281:
.size _Z13improve_guessPfS_S_S_iiiiiiiRiS0_Rfiiif, .-_Z13improve_guessPfS_S_S_iiiiiiiRiS0_Rfiiif
.globl _Z39__device_stub__Z17initialAnn_kernelPjPiPjPi
.type _Z39__device_stub__Z17initialAnn_kernelPjPiPjPi, @function
_Z39__device_stub__Z17initialAnn_kernelPjPiPjPi:
.LFB2306:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17initialAnn_kernelPjPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2306:
.size _Z39__device_stub__Z17initialAnn_kernelPjPiPjPi, .-_Z39__device_stub__Z17initialAnn_kernelPjPiPjPi
.globl _Z17initialAnn_kernelPjPi
.type _Z17initialAnn_kernelPjPi, @function
_Z17initialAnn_kernelPjPi:
.LFB2307:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17initialAnn_kernelPjPiPjPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2307:
.size _Z17initialAnn_kernelPjPi, .-_Z17initialAnn_kernelPjPi
.globl _Z41__device_stub__Z15upSample_kernelPjS_PiiiPjS_Piii
.type _Z41__device_stub__Z15upSample_kernelPjS_PiiiPjS_Piii, @function
_Z41__device_stub__Z15upSample_kernelPjS_PiiiPjS_Piii:
.LFB2308:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15upSample_kernelPjS_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2308:
.size _Z41__device_stub__Z15upSample_kernelPjS_PiiiPjS_Piii, .-_Z41__device_stub__Z15upSample_kernelPjS_PiiiPjS_Piii
.globl _Z15upSample_kernelPjS_Piii
.type _Z15upSample_kernelPjS_Piii, @function
_Z15upSample_kernelPjS_Piii:
.LFB2309:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15upSample_kernelPjS_PiiiPjS_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2309:
.size _Z15upSample_kernelPjS_Piii, .-_Z15upSample_kernelPjS_Piii
.globl _Z49__device_stub__Z11patch_matchPfS_S_S_PjS_iiiiiiiiPfS_S_S_PjS_iiiiiiii
.type _Z49__device_stub__Z11patch_matchPfS_S_S_PjS_iiiiiiiiPfS_S_S_PjS_iiiiiiii, @function
_Z49__device_stub__Z11patch_matchPfS_S_S_PjS_iiiiiiiiPfS_S_S_PjS_iiiiiiii:
.LFB2310:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 312(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L57
.L53:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 264
pushq 56(%rsp)
.cfi_def_cfa_offset 272
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq patch_match(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L53
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2310:
.size _Z49__device_stub__Z11patch_matchPfS_S_S_PjS_iiiiiiiiPfS_S_S_PjS_iiiiiiii, .-_Z49__device_stub__Z11patch_matchPfS_S_S_PjS_iiiiiiiiPfS_S_S_PjS_iiiiiiii
.globl patch_match
.type patch_match, @function
patch_match:
.LFB2311:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
call _Z49__device_stub__Z11patch_matchPfS_S_S_PjS_iiiiiiiiPfS_S_S_PjS_iiiiiiii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2311:
.size patch_match, .-patch_match
.globl _Z31__device_stub__Z5blendPfS_S_fPiPfS_S_fPi
.type _Z31__device_stub__Z5blendPfS_S_fPiPfS_S_fPi, @function
_Z31__device_stub__Z5blendPfS_S_fPiPfS_S_fPi:
.LFB2312:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L65
.L61:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L66
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5blendPfS_S_fPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L61
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2312:
.size _Z31__device_stub__Z5blendPfS_S_fPiPfS_S_fPi, .-_Z31__device_stub__Z5blendPfS_S_fPiPfS_S_fPi
.globl _Z5blendPfS_S_fPi
.type _Z5blendPfS_S_fPi, @function
_Z5blendPfS_S_fPi:
.LFB2313:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z5blendPfS_S_fPiPfS_S_fPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2313:
.size _Z5blendPfS_S_fPi, .-_Z5blendPfS_S_fPi
.globl _Z38__device_stub__Z8avg_votePjPfS0_iiiiiiPjPfS0_iiiiii
.type _Z38__device_stub__Z8avg_votePjPfS0_iiiiiiPjPfS0_iiiiii, @function
_Z38__device_stub__Z8avg_votePjPfS0_iiiiiiPjPfS0_iiiiii:
.LFB2314:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L73
.L69:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq avg_vote(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L69
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2314:
.size _Z38__device_stub__Z8avg_votePjPfS0_iiiiiiPjPfS0_iiiiii, .-_Z38__device_stub__Z8avg_votePjPfS0_iiiiiiPjPfS0_iiiiii
.globl avg_vote
.type avg_vote, @function
avg_vote:
.LFB2315:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z38__device_stub__Z8avg_votePjPfS0_iiiiiiPjPfS0_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2315:
.size avg_vote, .-avg_vote
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "avg_vote"
.LC3:
.string "_Z5blendPfS_S_fPi"
.LC4:
.string "patch_match"
.LC5:
.string "_Z15upSample_kernelPjS_Piii"
.LC6:
.string "_Z17initialAnn_kernelPjPi"
.LC7:
.string "precalc_xorwow_matrix"
.LC8:
.string "precalc_xorwow_offset_matrix"
.LC9:
.string "mrg32k3aM1"
.LC10:
.string "mrg32k3aM2"
.LC11:
.string "mrg32k3aM1SubSeq"
.LC12:
.string "mrg32k3aM2SubSeq"
.LC13:
.string "mrg32k3aM1Seq"
.LC14:
.string "mrg32k3aM2Seq"
.LC15:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2317:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq avg_vote(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5blendPfS_S_fPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq patch_match(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15upSample_kernelPjS_Piii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z17initialAnn_kernelPjPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2317:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // This code is copied from https://github.com/msracver/Deep-Image-Analogy
#include <stdio.h>
#include <curand_kernel.h>
#define FLT_MIN 1.175494351e-38F
__host__ __device__ int clamp(int x, int x_max, int x_min) {//assume x_max >= x_min
if (x > x_max)
{
return x_max;
}
else if (x < x_min)
{
return x_min;
}
else
{
return x;
}
}
__host__ __device__ unsigned int XY_TO_INT(int x, int y) {//r represent the number of 10 degree, x,y - 11 bits, max = 2047, r - max = 36, 6 bits
return (((y) << 11) | (x));
}
__host__ __device__ int INT_TO_X(unsigned int v) {
return (v)&((1 << 11) - 1);
}
__host__ __device__ int INT_TO_Y(unsigned int v) {
return (v >> 11)&((1 << 11) - 1);
}
__host__ __device__ int cuMax(int a, int b) {
if (a > b) {
return a;
}
else {
return b;
}
}
__host__ __device__ int cuMin(int a, int b) {
if (a < b) {
return a;
}
else {
return b;
}
}
__device__ float MycuRand(curandState &state) {//random number in cuda, between 0 and 1
return curand_uniform(&state);
}
__device__ void InitcuRand(curandState &state) {//random number in cuda, between 0 and 1
int i = threadIdx.x + blockIdx.x * blockDim.x;
curand_init(i, 0, 0, &state);
}
__host__ __device__ float dist_compute(float * a, float * b, float * a1, float * b1, int channels, int a_rows, int a_cols, int b_rows, int b_cols, int ax, int ay, int bx, int by, int patch_w, float cutoff = INT_MAX) {//this is the average number of all matched pixel //suppose patch_w is an odd number
float pixel_sum = 0, pixel_no = 0, pixel_dist = 0;//number of pixels realy counted
float pixel_sum1 = 0;
int a_slice = a_rows*a_cols, b_slice = b_rows*b_cols;
int a_pitch = a_cols, b_pitch = b_cols;
float dp_tmp;
for (int dy = -patch_w / 2; dy <= patch_w / 2; dy++) {
for (int dx = -patch_w / 2; dx <= patch_w / 2; dx++) {
if (
(ay + dy) < a_rows && (ay + dy) >= 0 && (ax + dx) < a_cols && (ax + dx) >= 0
&&
(by + dy) < b_rows && (by + dy) >= 0 && (bx + dx) < b_cols && (bx + dx) >= 0
)//the pixel in a should exist and pixel in b should exist
{
if (channels == 3)
{
for (int dc = 0; dc < channels; dc++)
{
dp_tmp = a[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] - b[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum += dp_tmp * dp_tmp;
dp_tmp = a1[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] - b1[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum1 += dp_tmp * dp_tmp;
}
}
else
{
for (int dc = 0; dc < channels; dc++)
{
dp_tmp = a[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] * b[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum -= dp_tmp;
dp_tmp = a1[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] * b1[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum1 -= dp_tmp;
}
}
pixel_no += 1;
}
}
}
pixel_dist = (pixel_sum + pixel_sum1) / pixel_no;
if (pixel_dist >= cutoff) { return cutoff; }
else {
return pixel_dist;
}
}
__host__ __device__ float dist(float * a, float * b, float *a1, float *b1, int channels, int a_rows, int a_cols, int b_rows, int b_cols, int ax, int ay, int xp, int yp, int patch_w, float cutoff = INT_MAX) {
return dist_compute(a, b, a1, b1, channels, a_rows, a_cols, b_rows, b_cols, ax, ay, xp, yp, patch_w, cutoff);
}
__device__ void improve_guess(float * a, float * b, float *a1, float *b1, int channels, int a_rows, int a_cols, int b_rows, int b_cols, int ax, int ay, int &xbest, int &ybest, float &dbest, int xp, int yp, int patch_w, float rr) {
float d;
d = dist(a, b, a1, b1, channels, a_rows, a_cols, b_rows, b_cols, ax, ay, xp, yp, patch_w);
if (d + rr < dbest) {
xbest = xp;
ybest = yp;
dbest = d;
}
}
__global__ void initialAnn_kernel(unsigned int * ann, int * params) {
//just use 7 of 9 parameters
int ah = params[1];
int aw = params[2];
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
if (ax < aw && ay < ah) {
int bx = ax;
int by = ay;
ann[ay*aw + ax] = XY_TO_INT(bx, by);
}
}
__global__ void upSample_kernel(unsigned int * ann, unsigned int * ann_tmp,int * params, int aw_half,int ah_half) {
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
int ah = params[1];
int aw = params[2];
int bh = params[3];
int bw = params[4];
float aw_ratio = (float)aw / (float)aw_half;
float ah_ratio = (float)ah / (float)ah_half;
int ax_half = (ax+0.5) / aw_ratio;
int ay_half = (ay+0.5) / ah_ratio;
ax_half = clamp(ax_half, aw_half - 1, 0);
ay_half = clamp(ay_half, ah_half - 1, 0);
if (ax < aw&&ay < ah) {
unsigned int v_half = ann[ay_half*aw_half + ax_half];
int bx_half = INT_TO_X(v_half);
int by_half = INT_TO_Y(v_half);
int bx = ax + (bx_half - ax_half)*aw_ratio + 0.5;
int by = ay + (by_half - ay_half)*ah_ratio + 0.5;
bx = clamp(bx, bw-1, 0);
by = clamp(by, bh-1, 0);
ann_tmp[ay*aw + ax] = XY_TO_INT(bx, by);
}
}
extern "C"
__global__ void patch_match(float * a, float * b, float *a1, float *b1, unsigned int *ann, float *annd, int ch, int a_rows, int a_cols, int b_rows, int b_cols, int patch_w, int pm_iters, int rs_max) {
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
if (ax < a_cols && ay < a_rows) {
// for random number
curandState state;
InitcuRand(state);
unsigned int v, vp;
int xp, yp, xbest, ybest;
int xmin, xmax, ymin, ymax;
float dbest;
v = ann[ay*a_cols + ax];
xbest = INT_TO_X(v), ybest = INT_TO_Y(v);
annd[ay*a_cols + ax] = dist(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, patch_w);
for (int iter = 0; iter < pm_iters; iter++) {
/* Current (best) guess. */
v = ann[ay*a_cols + ax];
xbest = INT_TO_X(v), ybest = INT_TO_Y(v);
dbest = annd[ay*a_cols + ax];
/* In each iteration, improve the NNF, by jumping flooding. */
for (int jump = 8; jump > 0; jump /= 2) {
/* Propagation: Improve current guess by trying instead correspondences from left, right, up and downs. */
if ((ax - jump) < a_cols && (ax - jump) >= 0)//left
{
vp = ann[ay*a_cols + ax - jump];//the pixel coordinates in image b
xp = INT_TO_X(vp) + jump, yp = INT_TO_Y(vp);//the propagated match from vp, the center of the patch, which should be in the image
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
if ((ax + jump) < a_cols)//right
{
vp = ann[ay*a_cols + ax + jump];//the pixel coordinates in image b
xp = INT_TO_X(vp) - jump, yp = INT_TO_Y(vp);
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
if ((ay - jump) < a_rows && (ay - jump) >= 0)//up
{
vp = ann[(ay - jump)*a_cols + ax];//the pixel coordinates in image b
xp = INT_TO_X(vp), yp = INT_TO_Y(vp) + jump;
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
if ((ay + jump) < a_rows)//down
{
vp = ann[(ay + jump)*a_cols + ax];//the pixel coordinates in image b
xp = INT_TO_X(vp), yp = INT_TO_Y(vp) - jump;
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
}
/* Random search: Improve current guess by searching in boxes of exponentially decreasing size around the current best guess. */
int rs_start = rs_max;
for (int mag = rs_start; mag >= 1; mag /= 2) {
/* Sampling window */
xmin = cuMax(xbest - mag, 0), xmax = cuMin(xbest + mag + 1, b_cols);
ymin = cuMax(ybest - mag, 0), ymax = cuMin(ybest + mag + 1, b_rows);
xp = xmin + (int)(MycuRand(state)*(xmax - xmin)) % (xmax - xmin);
yp = ymin + (int)(MycuRand(state)*(ymax - ymin)) % (ymax - ymin);
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, FLT_MIN);
}
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
__syncthreads();
}
}
}
__global__ void blend(float *cmap, float* oldd, float* newd, float weight,int * params)
{
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
int ch = params[0];
int ah = params[1];
int aw = params[2];
int slice_a = ah * aw;
int pitch_a = aw;
float thre = 0.05;
if (ax < aw&& ay < ah)
{
float fa = cmap[ay*pitch_a + ax];
if (fa < thre)
fa = 0.0f;
else fa = weight;
for (int i = 0; i < ch; i++)
{
newd[i*slice_a + ay*pitch_a + ax] = oldd[i*slice_a + ay*pitch_a + ax]* fa + newd[i*slice_a + ay*pitch_a + ax] * (1.0-fa);
}
}
}
// ********** VOTE ***********
extern "C"
__global__ void avg_vote(unsigned int * ann, float * pb, float * pc, int ch, int ah, int aw, int bh, int bw, int patch_w) {
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
int slice_a = ah * aw;
int pitch_a = aw;
int slice_b = bh * bw;
int pitch_b = bw;
int count = 0;
if (ax < aw&&ay < ah)
{
//set zero for all the channels at (ax,ay)
for (int i = 0; i < ch; i++)
{
pc[i*slice_a + ay*pitch_a + ax] = 0;
}
//count the sum of all the possible value of (ax,ay)
for (int dx = -patch_w / 2; dx <= patch_w / 2; dx++) {
for (int dy = -patch_w / 2; dy <= patch_w / 2; dy++)
{
if ((ax + dx) < aw && (ax + dx) >= 0 && (ay + dy) < ah && (ay + dy) >= 0)
{
unsigned int vp = ann[(ay + dy)*aw + ax + dx];
int xp = INT_TO_X(vp);
int yp = INT_TO_Y(vp);
if ((xp - dx) < bw && (xp - dx) >= 0 && (yp - dy) < bh && (yp - dy) >= 0)
{
count++;
for (int dc = 0; dc < ch; dc++)
{
pc[dc*slice_a + ay*pitch_a + ax] += pb[dc*slice_b + (yp - dy)*pitch_b + xp - dx];
}
}
}
}
}
//count average value
for (int i = 0; i < ch; i++)
{
pc[i*slice_a + ay*pitch_a + ax] /= count;
}
}
} | // This code is copied from https://github.com/msracver/Deep-Image-Analogy
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hiprand/hiprand_kernel.h>
#define FLT_MIN 1.175494351e-38F
__host__ __device__ int clamp(int x, int x_max, int x_min) {//assume x_max >= x_min
if (x > x_max)
{
return x_max;
}
else if (x < x_min)
{
return x_min;
}
else
{
return x;
}
}
__host__ __device__ unsigned int XY_TO_INT(int x, int y) {//r represent the number of 10 degree, x,y - 11 bits, max = 2047, r - max = 36, 6 bits
return (((y) << 11) | (x));
}
__host__ __device__ int INT_TO_X(unsigned int v) {
return (v)&((1 << 11) - 1);
}
__host__ __device__ int INT_TO_Y(unsigned int v) {
return (v >> 11)&((1 << 11) - 1);
}
__host__ __device__ int cuMax(int a, int b) {
if (a > b) {
return a;
}
else {
return b;
}
}
__host__ __device__ int cuMin(int a, int b) {
if (a < b) {
return a;
}
else {
return b;
}
}
__device__ float MycuRand(hiprandState &state) {//random number in cuda, between 0 and 1
return hiprand_uniform(&state);
}
__device__ void InitcuRand(hiprandState &state) {//random number in cuda, between 0 and 1
int i = threadIdx.x + blockIdx.x * blockDim.x;
hiprand_init(i, 0, 0, &state);
}
__host__ __device__ float dist_compute(float * a, float * b, float * a1, float * b1, int channels, int a_rows, int a_cols, int b_rows, int b_cols, int ax, int ay, int bx, int by, int patch_w, float cutoff = INT_MAX) {//this is the average number of all matched pixel //suppose patch_w is an odd number
float pixel_sum = 0, pixel_no = 0, pixel_dist = 0;//number of pixels realy counted
float pixel_sum1 = 0;
int a_slice = a_rows*a_cols, b_slice = b_rows*b_cols;
int a_pitch = a_cols, b_pitch = b_cols;
float dp_tmp;
for (int dy = -patch_w / 2; dy <= patch_w / 2; dy++) {
for (int dx = -patch_w / 2; dx <= patch_w / 2; dx++) {
if (
(ay + dy) < a_rows && (ay + dy) >= 0 && (ax + dx) < a_cols && (ax + dx) >= 0
&&
(by + dy) < b_rows && (by + dy) >= 0 && (bx + dx) < b_cols && (bx + dx) >= 0
)//the pixel in a should exist and pixel in b should exist
{
if (channels == 3)
{
for (int dc = 0; dc < channels; dc++)
{
dp_tmp = a[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] - b[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum += dp_tmp * dp_tmp;
dp_tmp = a1[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] - b1[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum1 += dp_tmp * dp_tmp;
}
}
else
{
for (int dc = 0; dc < channels; dc++)
{
dp_tmp = a[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] * b[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum -= dp_tmp;
dp_tmp = a1[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] * b1[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum1 -= dp_tmp;
}
}
pixel_no += 1;
}
}
}
pixel_dist = (pixel_sum + pixel_sum1) / pixel_no;
if (pixel_dist >= cutoff) { return cutoff; }
else {
return pixel_dist;
}
}
__host__ __device__ float dist(float * a, float * b, float *a1, float *b1, int channels, int a_rows, int a_cols, int b_rows, int b_cols, int ax, int ay, int xp, int yp, int patch_w, float cutoff = INT_MAX) {
return dist_compute(a, b, a1, b1, channels, a_rows, a_cols, b_rows, b_cols, ax, ay, xp, yp, patch_w, cutoff);
}
__device__ void improve_guess(float * a, float * b, float *a1, float *b1, int channels, int a_rows, int a_cols, int b_rows, int b_cols, int ax, int ay, int &xbest, int &ybest, float &dbest, int xp, int yp, int patch_w, float rr) {
float d;
d = dist(a, b, a1, b1, channels, a_rows, a_cols, b_rows, b_cols, ax, ay, xp, yp, patch_w);
if (d + rr < dbest) {
xbest = xp;
ybest = yp;
dbest = d;
}
}
__global__ void initialAnn_kernel(unsigned int * ann, int * params) {
//just use 7 of 9 parameters
int ah = params[1];
int aw = params[2];
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
if (ax < aw && ay < ah) {
int bx = ax;
int by = ay;
ann[ay*aw + ax] = XY_TO_INT(bx, by);
}
}
__global__ void upSample_kernel(unsigned int * ann, unsigned int * ann_tmp,int * params, int aw_half,int ah_half) {
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
int ah = params[1];
int aw = params[2];
int bh = params[3];
int bw = params[4];
float aw_ratio = (float)aw / (float)aw_half;
float ah_ratio = (float)ah / (float)ah_half;
int ax_half = (ax+0.5) / aw_ratio;
int ay_half = (ay+0.5) / ah_ratio;
ax_half = clamp(ax_half, aw_half - 1, 0);
ay_half = clamp(ay_half, ah_half - 1, 0);
if (ax < aw&&ay < ah) {
unsigned int v_half = ann[ay_half*aw_half + ax_half];
int bx_half = INT_TO_X(v_half);
int by_half = INT_TO_Y(v_half);
int bx = ax + (bx_half - ax_half)*aw_ratio + 0.5;
int by = ay + (by_half - ay_half)*ah_ratio + 0.5;
bx = clamp(bx, bw-1, 0);
by = clamp(by, bh-1, 0);
ann_tmp[ay*aw + ax] = XY_TO_INT(bx, by);
}
}
extern "C"
__global__ void patch_match(float * a, float * b, float *a1, float *b1, unsigned int *ann, float *annd, int ch, int a_rows, int a_cols, int b_rows, int b_cols, int patch_w, int pm_iters, int rs_max) {
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
if (ax < a_cols && ay < a_rows) {
// for random number
hiprandState state;
InitcuRand(state);
unsigned int v, vp;
int xp, yp, xbest, ybest;
int xmin, xmax, ymin, ymax;
float dbest;
v = ann[ay*a_cols + ax];
xbest = INT_TO_X(v), ybest = INT_TO_Y(v);
annd[ay*a_cols + ax] = dist(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, patch_w);
for (int iter = 0; iter < pm_iters; iter++) {
/* Current (best) guess. */
v = ann[ay*a_cols + ax];
xbest = INT_TO_X(v), ybest = INT_TO_Y(v);
dbest = annd[ay*a_cols + ax];
/* In each iteration, improve the NNF, by jumping flooding. */
for (int jump = 8; jump > 0; jump /= 2) {
/* Propagation: Improve current guess by trying instead correspondences from left, right, up and downs. */
if ((ax - jump) < a_cols && (ax - jump) >= 0)//left
{
vp = ann[ay*a_cols + ax - jump];//the pixel coordinates in image b
xp = INT_TO_X(vp) + jump, yp = INT_TO_Y(vp);//the propagated match from vp, the center of the patch, which should be in the image
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
if ((ax + jump) < a_cols)//right
{
vp = ann[ay*a_cols + ax + jump];//the pixel coordinates in image b
xp = INT_TO_X(vp) - jump, yp = INT_TO_Y(vp);
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
if ((ay - jump) < a_rows && (ay - jump) >= 0)//up
{
vp = ann[(ay - jump)*a_cols + ax];//the pixel coordinates in image b
xp = INT_TO_X(vp), yp = INT_TO_Y(vp) + jump;
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
if ((ay + jump) < a_rows)//down
{
vp = ann[(ay + jump)*a_cols + ax];//the pixel coordinates in image b
xp = INT_TO_X(vp), yp = INT_TO_Y(vp) - jump;
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
}
/* Random search: Improve current guess by searching in boxes of exponentially decreasing size around the current best guess. */
int rs_start = rs_max;
for (int mag = rs_start; mag >= 1; mag /= 2) {
/* Sampling window */
xmin = cuMax(xbest - mag, 0), xmax = cuMin(xbest + mag + 1, b_cols);
ymin = cuMax(ybest - mag, 0), ymax = cuMin(ybest + mag + 1, b_rows);
xp = xmin + (int)(MycuRand(state)*(xmax - xmin)) % (xmax - xmin);
yp = ymin + (int)(MycuRand(state)*(ymax - ymin)) % (ymax - ymin);
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, FLT_MIN);
}
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
__syncthreads();
}
}
}
__global__ void blend(float *cmap, float* oldd, float* newd, float weight,int * params)
{
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
int ch = params[0];
int ah = params[1];
int aw = params[2];
int slice_a = ah * aw;
int pitch_a = aw;
float thre = 0.05;
if (ax < aw&& ay < ah)
{
float fa = cmap[ay*pitch_a + ax];
if (fa < thre)
fa = 0.0f;
else fa = weight;
for (int i = 0; i < ch; i++)
{
newd[i*slice_a + ay*pitch_a + ax] = oldd[i*slice_a + ay*pitch_a + ax]* fa + newd[i*slice_a + ay*pitch_a + ax] * (1.0-fa);
}
}
}
// ********** VOTE ***********
extern "C"
__global__ void avg_vote(unsigned int * ann, float * pb, float * pc, int ch, int ah, int aw, int bh, int bw, int patch_w) {
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
int slice_a = ah * aw;
int pitch_a = aw;
int slice_b = bh * bw;
int pitch_b = bw;
int count = 0;
if (ax < aw&&ay < ah)
{
//set zero for all the channels at (ax,ay)
for (int i = 0; i < ch; i++)
{
pc[i*slice_a + ay*pitch_a + ax] = 0;
}
//count the sum of all the possible value of (ax,ay)
for (int dx = -patch_w / 2; dx <= patch_w / 2; dx++) {
for (int dy = -patch_w / 2; dy <= patch_w / 2; dy++)
{
if ((ax + dx) < aw && (ax + dx) >= 0 && (ay + dy) < ah && (ay + dy) >= 0)
{
unsigned int vp = ann[(ay + dy)*aw + ax + dx];
int xp = INT_TO_X(vp);
int yp = INT_TO_Y(vp);
if ((xp - dx) < bw && (xp - dx) >= 0 && (yp - dy) < bh && (yp - dy) >= 0)
{
count++;
for (int dc = 0; dc < ch; dc++)
{
pc[dc*slice_a + ay*pitch_a + ax] += pb[dc*slice_b + (yp - dy)*pitch_b + xp - dx];
}
}
}
}
}
//count average value
for (int i = 0; i < ch; i++)
{
pc[i*slice_a + ay*pitch_a + ax] /= count;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // This code is copied from https://github.com/msracver/Deep-Image-Analogy
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hiprand/hiprand_kernel.h>
#define FLT_MIN 1.175494351e-38F
__host__ __device__ int clamp(int x, int x_max, int x_min) {//assume x_max >= x_min
if (x > x_max)
{
return x_max;
}
else if (x < x_min)
{
return x_min;
}
else
{
return x;
}
}
__host__ __device__ unsigned int XY_TO_INT(int x, int y) {//r represent the number of 10 degree, x,y - 11 bits, max = 2047, r - max = 36, 6 bits
return (((y) << 11) | (x));
}
__host__ __device__ int INT_TO_X(unsigned int v) {
return (v)&((1 << 11) - 1);
}
__host__ __device__ int INT_TO_Y(unsigned int v) {
return (v >> 11)&((1 << 11) - 1);
}
__host__ __device__ int cuMax(int a, int b) {
if (a > b) {
return a;
}
else {
return b;
}
}
__host__ __device__ int cuMin(int a, int b) {
if (a < b) {
return a;
}
else {
return b;
}
}
__device__ float MycuRand(hiprandState &state) {//random number in cuda, between 0 and 1
return hiprand_uniform(&state);
}
__device__ void InitcuRand(hiprandState &state) {//random number in cuda, between 0 and 1
int i = threadIdx.x + blockIdx.x * blockDim.x;
hiprand_init(i, 0, 0, &state);
}
__host__ __device__ float dist_compute(float * a, float * b, float * a1, float * b1, int channels, int a_rows, int a_cols, int b_rows, int b_cols, int ax, int ay, int bx, int by, int patch_w, float cutoff = INT_MAX) {//this is the average number of all matched pixel //suppose patch_w is an odd number
float pixel_sum = 0, pixel_no = 0, pixel_dist = 0;//number of pixels realy counted
float pixel_sum1 = 0;
int a_slice = a_rows*a_cols, b_slice = b_rows*b_cols;
int a_pitch = a_cols, b_pitch = b_cols;
float dp_tmp;
for (int dy = -patch_w / 2; dy <= patch_w / 2; dy++) {
for (int dx = -patch_w / 2; dx <= patch_w / 2; dx++) {
if (
(ay + dy) < a_rows && (ay + dy) >= 0 && (ax + dx) < a_cols && (ax + dx) >= 0
&&
(by + dy) < b_rows && (by + dy) >= 0 && (bx + dx) < b_cols && (bx + dx) >= 0
)//the pixel in a should exist and pixel in b should exist
{
if (channels == 3)
{
for (int dc = 0; dc < channels; dc++)
{
dp_tmp = a[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] - b[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum += dp_tmp * dp_tmp;
dp_tmp = a1[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] - b1[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum1 += dp_tmp * dp_tmp;
}
}
else
{
for (int dc = 0; dc < channels; dc++)
{
dp_tmp = a[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] * b[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum -= dp_tmp;
dp_tmp = a1[dc * a_slice + (ay + dy) * a_pitch + (ax + dx)] * b1[dc * b_slice + (by + dy) * b_pitch + (bx + dx)];
pixel_sum1 -= dp_tmp;
}
}
pixel_no += 1;
}
}
}
pixel_dist = (pixel_sum + pixel_sum1) / pixel_no;
if (pixel_dist >= cutoff) { return cutoff; }
else {
return pixel_dist;
}
}
__host__ __device__ float dist(float * a, float * b, float *a1, float *b1, int channels, int a_rows, int a_cols, int b_rows, int b_cols, int ax, int ay, int xp, int yp, int patch_w, float cutoff = INT_MAX) {
return dist_compute(a, b, a1, b1, channels, a_rows, a_cols, b_rows, b_cols, ax, ay, xp, yp, patch_w, cutoff);
}
__device__ void improve_guess(float * a, float * b, float *a1, float *b1, int channels, int a_rows, int a_cols, int b_rows, int b_cols, int ax, int ay, int &xbest, int &ybest, float &dbest, int xp, int yp, int patch_w, float rr) {
float d;
d = dist(a, b, a1, b1, channels, a_rows, a_cols, b_rows, b_cols, ax, ay, xp, yp, patch_w);
if (d + rr < dbest) {
xbest = xp;
ybest = yp;
dbest = d;
}
}
__global__ void initialAnn_kernel(unsigned int * ann, int * params) {
//just use 7 of 9 parameters
int ah = params[1];
int aw = params[2];
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
if (ax < aw && ay < ah) {
int bx = ax;
int by = ay;
ann[ay*aw + ax] = XY_TO_INT(bx, by);
}
}
__global__ void upSample_kernel(unsigned int * ann, unsigned int * ann_tmp,int * params, int aw_half,int ah_half) {
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
int ah = params[1];
int aw = params[2];
int bh = params[3];
int bw = params[4];
float aw_ratio = (float)aw / (float)aw_half;
float ah_ratio = (float)ah / (float)ah_half;
int ax_half = (ax+0.5) / aw_ratio;
int ay_half = (ay+0.5) / ah_ratio;
ax_half = clamp(ax_half, aw_half - 1, 0);
ay_half = clamp(ay_half, ah_half - 1, 0);
if (ax < aw&&ay < ah) {
unsigned int v_half = ann[ay_half*aw_half + ax_half];
int bx_half = INT_TO_X(v_half);
int by_half = INT_TO_Y(v_half);
int bx = ax + (bx_half - ax_half)*aw_ratio + 0.5;
int by = ay + (by_half - ay_half)*ah_ratio + 0.5;
bx = clamp(bx, bw-1, 0);
by = clamp(by, bh-1, 0);
ann_tmp[ay*aw + ax] = XY_TO_INT(bx, by);
}
}
extern "C"
__global__ void patch_match(float * a, float * b, float *a1, float *b1, unsigned int *ann, float *annd, int ch, int a_rows, int a_cols, int b_rows, int b_cols, int patch_w, int pm_iters, int rs_max) {
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
if (ax < a_cols && ay < a_rows) {
// for random number
hiprandState state;
InitcuRand(state);
unsigned int v, vp;
int xp, yp, xbest, ybest;
int xmin, xmax, ymin, ymax;
float dbest;
v = ann[ay*a_cols + ax];
xbest = INT_TO_X(v), ybest = INT_TO_Y(v);
annd[ay*a_cols + ax] = dist(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, patch_w);
for (int iter = 0; iter < pm_iters; iter++) {
/* Current (best) guess. */
v = ann[ay*a_cols + ax];
xbest = INT_TO_X(v), ybest = INT_TO_Y(v);
dbest = annd[ay*a_cols + ax];
/* In each iteration, improve the NNF, by jumping flooding. */
for (int jump = 8; jump > 0; jump /= 2) {
/* Propagation: Improve current guess by trying instead correspondences from left, right, up and downs. */
if ((ax - jump) < a_cols && (ax - jump) >= 0)//left
{
vp = ann[ay*a_cols + ax - jump];//the pixel coordinates in image b
xp = INT_TO_X(vp) + jump, yp = INT_TO_Y(vp);//the propagated match from vp, the center of the patch, which should be in the image
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
if ((ax + jump) < a_cols)//right
{
vp = ann[ay*a_cols + ax + jump];//the pixel coordinates in image b
xp = INT_TO_X(vp) - jump, yp = INT_TO_Y(vp);
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
if ((ay - jump) < a_rows && (ay - jump) >= 0)//up
{
vp = ann[(ay - jump)*a_cols + ax];//the pixel coordinates in image b
xp = INT_TO_X(vp), yp = INT_TO_Y(vp) + jump;
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
if ((ay + jump) < a_rows)//down
{
vp = ann[(ay + jump)*a_cols + ax];//the pixel coordinates in image b
xp = INT_TO_X(vp), yp = INT_TO_Y(vp) - jump;
if (yp >= 0 && yp < b_rows && xp >= 0 && xp < b_cols)
{
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, 0);
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
}
}
}
/* Random search: Improve current guess by searching in boxes of exponentially decreasing size around the current best guess. */
int rs_start = rs_max;
for (int mag = rs_start; mag >= 1; mag /= 2) {
/* Sampling window */
xmin = cuMax(xbest - mag, 0), xmax = cuMin(xbest + mag + 1, b_cols);
ymin = cuMax(ybest - mag, 0), ymax = cuMin(ybest + mag + 1, b_rows);
xp = xmin + (int)(MycuRand(state)*(xmax - xmin)) % (xmax - xmin);
yp = ymin + (int)(MycuRand(state)*(ymax - ymin)) % (ymax - ymin);
//improve guess
improve_guess(a, b, a1, b1, ch, a_rows, a_cols, b_rows, b_cols, ax, ay, xbest, ybest, dbest, xp, yp, patch_w, FLT_MIN);
}
ann[ay*a_cols + ax] = XY_TO_INT(xbest, ybest);
annd[ay*a_cols + ax] = dbest;
__syncthreads();
}
}
}
__global__ void blend(float *cmap, float* oldd, float* newd, float weight,int * params)
{
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
int ch = params[0];
int ah = params[1];
int aw = params[2];
int slice_a = ah * aw;
int pitch_a = aw;
float thre = 0.05;
if (ax < aw&& ay < ah)
{
float fa = cmap[ay*pitch_a + ax];
if (fa < thre)
fa = 0.0f;
else fa = weight;
for (int i = 0; i < ch; i++)
{
newd[i*slice_a + ay*pitch_a + ax] = oldd[i*slice_a + ay*pitch_a + ax]* fa + newd[i*slice_a + ay*pitch_a + ax] * (1.0-fa);
}
}
}
// ********** VOTE ***********
extern "C"
__global__ void avg_vote(unsigned int * ann, float * pb, float * pc, int ch, int ah, int aw, int bh, int bw, int patch_w) {
int ax = blockIdx.x*blockDim.x + threadIdx.x;
int ay = blockIdx.y*blockDim.y + threadIdx.y;
int slice_a = ah * aw;
int pitch_a = aw;
int slice_b = bh * bw;
int pitch_b = bw;
int count = 0;
if (ax < aw&&ay < ah)
{
//set zero for all the channels at (ax,ay)
for (int i = 0; i < ch; i++)
{
pc[i*slice_a + ay*pitch_a + ax] = 0;
}
//count the sum of all the possible value of (ax,ay)
for (int dx = -patch_w / 2; dx <= patch_w / 2; dx++) {
for (int dy = -patch_w / 2; dy <= patch_w / 2; dy++)
{
if ((ax + dx) < aw && (ax + dx) >= 0 && (ay + dy) < ah && (ay + dy) >= 0)
{
unsigned int vp = ann[(ay + dy)*aw + ax + dx];
int xp = INT_TO_X(vp);
int yp = INT_TO_Y(vp);
if ((xp - dx) < bw && (xp - dx) >= 0 && (yp - dy) < bh && (yp - dy) >= 0)
{
count++;
for (int dc = 0; dc < ch; dc++)
{
pc[dc*slice_a + ay*pitch_a + ax] += pb[dc*slice_b + (yp - dy)*pitch_b + xp - dx];
}
}
}
}
}
//count average value
for (int i = 0; i < ch; i++)
{
pc[i*slice_a + ay*pitch_a + ax] /= count;
}
}
} | .text
.file "GeneralizedPatchMatch.hip"
.globl _Z5clampiii # -- Begin function _Z5clampiii
.p2align 4, 0x90
.type _Z5clampiii,@function
_Z5clampiii: # @_Z5clampiii
.cfi_startproc
# %bb.0:
movl %edx, %eax
cmpl %edx, %edi
cmovgl %edi, %eax
cmpl %esi, %edi
cmovgl %esi, %eax
retq
.Lfunc_end0:
.size _Z5clampiii, .Lfunc_end0-_Z5clampiii
.cfi_endproc
# -- End function
.globl _Z9XY_TO_INTii # -- Begin function _Z9XY_TO_INTii
.p2align 4, 0x90
.type _Z9XY_TO_INTii,@function
_Z9XY_TO_INTii: # @_Z9XY_TO_INTii
.cfi_startproc
# %bb.0:
movl %esi, %eax
shll $11, %eax
orl %edi, %eax
retq
.Lfunc_end1:
.size _Z9XY_TO_INTii, .Lfunc_end1-_Z9XY_TO_INTii
.cfi_endproc
# -- End function
.globl _Z8INT_TO_Xj # -- Begin function _Z8INT_TO_Xj
.p2align 4, 0x90
.type _Z8INT_TO_Xj,@function
_Z8INT_TO_Xj: # @_Z8INT_TO_Xj
.cfi_startproc
# %bb.0:
movl %edi, %eax
andl $2047, %eax # imm = 0x7FF
retq
.Lfunc_end2:
.size _Z8INT_TO_Xj, .Lfunc_end2-_Z8INT_TO_Xj
.cfi_endproc
# -- End function
.globl _Z8INT_TO_Yj # -- Begin function _Z8INT_TO_Yj
.p2align 4, 0x90
.type _Z8INT_TO_Yj,@function
_Z8INT_TO_Yj: # @_Z8INT_TO_Yj
.cfi_startproc
# %bb.0:
movl %edi, %eax
shrl $11, %eax
andl $2047, %eax # imm = 0x7FF
retq
.Lfunc_end3:
.size _Z8INT_TO_Yj, .Lfunc_end3-_Z8INT_TO_Yj
.cfi_endproc
# -- End function
.globl _Z5cuMaxii # -- Begin function _Z5cuMaxii
.p2align 4, 0x90
.type _Z5cuMaxii,@function
_Z5cuMaxii: # @_Z5cuMaxii
.cfi_startproc
# %bb.0:
movl %esi, %eax
cmpl %esi, %edi
cmovgl %edi, %eax
retq
.Lfunc_end4:
.size _Z5cuMaxii, .Lfunc_end4-_Z5cuMaxii
.cfi_endproc
# -- End function
.globl _Z5cuMinii # -- Begin function _Z5cuMinii
.p2align 4, 0x90
.type _Z5cuMinii,@function
_Z5cuMinii: # @_Z5cuMinii
.cfi_startproc
# %bb.0:
movl %esi, %eax
cmpl %esi, %edi
cmovll %edi, %eax
retq
.Lfunc_end5:
.size _Z5cuMinii, .Lfunc_end5-_Z5cuMinii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12dist_computePfS_S_S_iiiiiiiiiif
.LCPI6_0:
.long 0x7fc00000 # float NaN
.LCPI6_1:
.long 0x3f800000 # float 1
.text
.globl _Z12dist_computePfS_S_S_iiiiiiiiiif
.p2align 4, 0x90
.type _Z12dist_computePfS_S_S_iiiiiiiiiif,@function
_Z12dist_computePfS_S_S_iiiiiiiiiif: # @_Z12dist_computePfS_S_S_iiiiiiiiiif
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %r14d
movl 112(%rsp), %r10d
movl %r10d, %eax
shrl $31, %eax
addl %r10d, %eax
sarl %eax
movl %eax, %r8d
negl %r8d
cmpl %eax, %r8d
jle .LBB6_2
# %bb.1:
movss .LCPI6_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
jmp .LBB6_12
.LBB6_2: # %.preheader154.lr.ph
movl 104(%rsp), %r11d
movl 96(%rsp), %r15d
movl 88(%rsp), %ebx
movl 80(%rsp), %r12d
movl 72(%rsp), %ebp
movl 56(%rsp), %r13d
movl %r14d, %r10d
movq %r10, -8(%rsp) # 8-byte Spill
leal (%r8,%r11), %r11d
imull %ebp, %r11d
addl %r8d, %r11d
addl %r15d, %r11d
imull 64(%rsp), %ebp
leal (%r8,%r12), %r10d
movl %r11d, %r12d
addl %r8d, %ebx
imull %r13d, %ebx
addl %r10d, %ebx
imull %r9d, %r13d
xorps %xmm1, %xmm1
movss .LCPI6_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movl %r8d, %r10d
xorps %xmm4, %xmm4
xorps %xmm2, %xmm2
movl %r14d, -40(%rsp) # 4-byte Spill
movl %r9d, -36(%rsp) # 4-byte Spill
movq %r8, -24(%rsp) # 8-byte Spill
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_17: # %._crit_edge
# in Loop: Header=BB6_3 Depth=1
movq -16(%rsp), %r10 # 8-byte Reload
leal 1(%r10), %r9d
movl -28(%rsp), %r12d # 4-byte Reload
addl 72(%rsp), %r12d
movl -32(%rsp), %ebx # 4-byte Reload
addl 56(%rsp), %ebx
cmpl %eax, %r10d
movl %r9d, %r10d
movl -36(%rsp), %r9d # 4-byte Reload
movq -24(%rsp), %r8 # 8-byte Reload
je .LBB6_11
.LBB6_3: # %.preheader154
# =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
# Child Loop BB6_10 Depth 3
# Child Loop BB6_14 Depth 3
movl %r10d, %r11d
movq %r10, %r14
movl 88(%rsp), %r10d
addl %r10d, %r11d
setns %r10b
cmpl %r9d, %r11d
movl %ebx, %r11d
setl %bl
andb %r10b, %bl
movq %r14, -16(%rsp) # 8-byte Spill
movl %r14d, %r10d
movl 104(%rsp), %r9d
addl %r9d, %r10d
sets %r9b
cmpl 64(%rsp), %r10d
setge %r10b
orb %r9b, %r10b
movb %r10b, -41(%rsp) # 1-byte Spill
movl %r11d, -32(%rsp) # 4-byte Spill
movl %r11d, %r10d
movl %r12d, -28(%rsp) # 4-byte Spill
movl %r8d, %r14d
movl -40(%rsp), %r8d # 4-byte Reload
jmp .LBB6_4
.LBB6_15: # %.loopexit
# in Loop: Header=BB6_4 Depth=2
addss %xmm3, %xmm4
movl -40(%rsp), %r8d # 4-byte Reload
movl 96(%rsp), %r15d
.p2align 4, 0x90
.LBB6_16: # in Loop: Header=BB6_4 Depth=2
leal 1(%r14), %r9d
incl %r12d
incl %r10d
cmpl %eax, %r14d
movl %r9d, %r14d
je .LBB6_17
.LBB6_4: # Parent Loop BB6_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_10 Depth 3
# Child Loop BB6_14 Depth 3
testb %bl, %bl
je .LBB6_16
# %bb.5: # in Loop: Header=BB6_4 Depth=2
movl %r14d, %r9d
movl 80(%rsp), %r11d
addl %r11d, %r9d
sets %r11b
cmpl 56(%rsp), %r9d
setge %r9b
orb -41(%rsp), %r11b # 1-byte Folded Reload
orb %r9b, %r11b
jne .LBB6_16
# %bb.6: # in Loop: Header=BB6_4 Depth=2
leal (%r14,%r15), %r9d
cmpl 72(%rsp), %r9d
jge .LBB6_16
# %bb.7: # in Loop: Header=BB6_4 Depth=2
testl %r9d, %r9d
js .LBB6_16
# %bb.8: # in Loop: Header=BB6_4 Depth=2
cmpl $3, %r8d
jne .LBB6_9
# %bb.13: # %.preheader
# in Loop: Header=BB6_4 Depth=2
movl $3, %r15d
movl %r10d, %r9d
movl %r12d, %r11d
.p2align 4, 0x90
.LBB6_14: # Parent Loop BB6_3 Depth=1
# Parent Loop BB6_4 Depth=2
# => This Inner Loop Header: Depth=3
movslq %r9d, %r9
movss (%rdi,%r9,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movslq %r11d, %r11
subss (%rsi,%r11,4), %xmm5
mulss %xmm5, %xmm5
addss %xmm5, %xmm1
movss (%rdx,%r9,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss (%rcx,%r11,4), %xmm5
mulss %xmm5, %xmm5
addss %xmm5, %xmm2
addl %ebp, %r11d
addl %r13d, %r9d
decq %r15
jne .LBB6_14
jmp .LBB6_15
.LBB6_9: # %.preheader152
# in Loop: Header=BB6_4 Depth=2
movq -8(%rsp), %r15 # 8-byte Reload
movl %r10d, %r11d
movl %r12d, %r9d
testl %r8d, %r8d
jle .LBB6_15
.p2align 4, 0x90
.LBB6_10: # Parent Loop BB6_3 Depth=1
# Parent Loop BB6_4 Depth=2
# => This Inner Loop Header: Depth=3
movslq %r11d, %r11
movss (%rdi,%r11,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movslq %r9d, %r9
mulss (%rsi,%r9,4), %xmm5
subss %xmm5, %xmm1
movss (%rdx,%r11,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
mulss (%rcx,%r9,4), %xmm5
subss %xmm5, %xmm2
addl %ebp, %r9d
addl %r13d, %r11d
decq %r15
jne .LBB6_10
jmp .LBB6_15
.LBB6_11: # %._crit_edge176.loopexit
addss %xmm1, %xmm2
divss %xmm4, %xmm2
.LBB6_12: # %._crit_edge176
movaps %xmm0, %xmm1
cmpless %xmm2, %xmm1
andps %xmm1, %xmm0
andnps %xmm2, %xmm1
orps %xmm0, %xmm1
movaps %xmm1, %xmm0
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z12dist_computePfS_S_S_iiiiiiiiiif, .Lfunc_end6-_Z12dist_computePfS_S_S_iiiiiiiiiif
.cfi_endproc
# -- End function
.globl _Z4distPfS_S_S_iiiiiiiiiif # -- Begin function _Z4distPfS_S_S_iiiiiiiiiif
.p2align 4, 0x90
.type _Z4distPfS_S_S_iiiiiiiiiif,@function
_Z4distPfS_S_S_iiiiiiiiiif: # @_Z4distPfS_S_S_iiiiiiiiiif
.cfi_startproc
# %bb.0:
jmp _Z12dist_computePfS_S_S_iiiiiiiiiif # TAILCALL
.Lfunc_end7:
.size _Z4distPfS_S_S_iiiiiiiiiif, .Lfunc_end7-_Z4distPfS_S_S_iiiiiiiiiif
.cfi_endproc
# -- End function
.globl _Z32__device_stub__initialAnn_kernelPjPi # -- Begin function _Z32__device_stub__initialAnn_kernelPjPi
.p2align 4, 0x90
.type _Z32__device_stub__initialAnn_kernelPjPi,@function
_Z32__device_stub__initialAnn_kernelPjPi: # @_Z32__device_stub__initialAnn_kernelPjPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17initialAnn_kernelPjPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end8:
.size _Z32__device_stub__initialAnn_kernelPjPi, .Lfunc_end8-_Z32__device_stub__initialAnn_kernelPjPi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__upSample_kernelPjS_Piii # -- Begin function _Z30__device_stub__upSample_kernelPjS_Piii
.p2align 4, 0x90
.type _Z30__device_stub__upSample_kernelPjS_Piii,@function
_Z30__device_stub__upSample_kernelPjS_Piii: # @_Z30__device_stub__upSample_kernelPjS_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15upSample_kernelPjS_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end9:
.size _Z30__device_stub__upSample_kernelPjS_Piii, .Lfunc_end9-_Z30__device_stub__upSample_kernelPjS_Piii
.cfi_endproc
# -- End function
.globl __device_stub__patch_match # -- Begin function __device_stub__patch_match
.p2align 4, 0x90
.type __device_stub__patch_match,@function
__device_stub__patch_match: # @__device_stub__patch_match
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $patch_match, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end10:
.size __device_stub__patch_match, .Lfunc_end10-__device_stub__patch_match
.cfi_endproc
# -- End function
.globl _Z20__device_stub__blendPfS_S_fPi # -- Begin function _Z20__device_stub__blendPfS_S_fPi
.p2align 4, 0x90
.type _Z20__device_stub__blendPfS_S_fPi,@function
_Z20__device_stub__blendPfS_S_fPi: # @_Z20__device_stub__blendPfS_S_fPi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rcx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5blendPfS_S_fPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end11:
.size _Z20__device_stub__blendPfS_S_fPi, .Lfunc_end11-_Z20__device_stub__blendPfS_S_fPi
.cfi_endproc
# -- End function
.globl __device_stub__avg_vote # -- Begin function __device_stub__avg_vote
.p2align 4, 0x90
.type __device_stub__avg_vote,@function
__device_stub__avg_vote: # @__device_stub__avg_vote
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $avg_vote, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end12:
.size __device_stub__avg_vote, .Lfunc_end12-__device_stub__avg_vote
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB13_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB13_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17initialAnn_kernelPjPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15upSample_kernelPjS_Piii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $patch_match, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5blendPfS_S_fPi, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $avg_vote, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end13:
.size __hip_module_ctor, .Lfunc_end13-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB14_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB14_2:
retq
.Lfunc_end14:
.size __hip_module_dtor, .Lfunc_end14-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17initialAnn_kernelPjPi,@object # @_Z17initialAnn_kernelPjPi
.section .rodata,"a",@progbits
.globl _Z17initialAnn_kernelPjPi
.p2align 3, 0x0
_Z17initialAnn_kernelPjPi:
.quad _Z32__device_stub__initialAnn_kernelPjPi
.size _Z17initialAnn_kernelPjPi, 8
.type _Z15upSample_kernelPjS_Piii,@object # @_Z15upSample_kernelPjS_Piii
.globl _Z15upSample_kernelPjS_Piii
.p2align 3, 0x0
_Z15upSample_kernelPjS_Piii:
.quad _Z30__device_stub__upSample_kernelPjS_Piii
.size _Z15upSample_kernelPjS_Piii, 8
.type patch_match,@object # @patch_match
.globl patch_match
.p2align 3, 0x0
patch_match:
.quad __device_stub__patch_match
.size patch_match, 8
.type _Z5blendPfS_S_fPi,@object # @_Z5blendPfS_S_fPi
.globl _Z5blendPfS_S_fPi
.p2align 3, 0x0
_Z5blendPfS_S_fPi:
.quad _Z20__device_stub__blendPfS_S_fPi
.size _Z5blendPfS_S_fPi, 8
.type avg_vote,@object # @avg_vote
.globl avg_vote
.p2align 3, 0x0
avg_vote:
.quad __device_stub__avg_vote
.size avg_vote, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17initialAnn_kernelPjPi"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15upSample_kernelPjS_Piii"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "patch_match"
.size .L__unnamed_3, 12
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z5blendPfS_S_fPi"
.size .L__unnamed_4, 18
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "avg_vote"
.size .L__unnamed_5, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__initialAnn_kernelPjPi
.addrsig_sym _Z30__device_stub__upSample_kernelPjS_Piii
.addrsig_sym __device_stub__patch_match
.addrsig_sym _Z20__device_stub__blendPfS_S_fPi
.addrsig_sym __device_stub__avg_vote
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17initialAnn_kernelPjPi
.addrsig_sym _Z15upSample_kernelPjS_Piii
.addrsig_sym patch_match
.addrsig_sym _Z5blendPfS_S_fPi
.addrsig_sym avg_vote
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eaadc_00000000-6_GeneralizedPatchMatch.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2284:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2284:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5clampiii
.type _Z5clampiii, @function
_Z5clampiii:
.LFB2271:
.cfi_startproc
endbr64
cmpl %edx, %edi
cmovge %edi, %edx
cmpl %esi, %edi
movl %esi, %eax
cmovle %edx, %eax
ret
.cfi_endproc
.LFE2271:
.size _Z5clampiii, .-_Z5clampiii
.globl _Z9XY_TO_INTii
.type _Z9XY_TO_INTii, @function
_Z9XY_TO_INTii:
.LFB2272:
.cfi_startproc
endbr64
movl %esi, %eax
sall $11, %eax
orl %edi, %eax
ret
.cfi_endproc
.LFE2272:
.size _Z9XY_TO_INTii, .-_Z9XY_TO_INTii
.globl _Z8INT_TO_Xj
.type _Z8INT_TO_Xj, @function
_Z8INT_TO_Xj:
.LFB2273:
.cfi_startproc
endbr64
movl %edi, %eax
andl $2047, %eax
ret
.cfi_endproc
.LFE2273:
.size _Z8INT_TO_Xj, .-_Z8INT_TO_Xj
.globl _Z8INT_TO_Yj
.type _Z8INT_TO_Yj, @function
_Z8INT_TO_Yj:
.LFB2274:
.cfi_startproc
endbr64
movl %edi, %eax
shrl $11, %eax
andl $2047, %eax
ret
.cfi_endproc
.LFE2274:
.size _Z8INT_TO_Yj, .-_Z8INT_TO_Yj
.globl _Z5cuMaxii
.type _Z5cuMaxii, @function
_Z5cuMaxii:
.LFB2275:
.cfi_startproc
endbr64
cmpl %esi, %edi
movl %esi, %eax
cmovge %edi, %eax
ret
.cfi_endproc
.LFE2275:
.size _Z5cuMaxii, .-_Z5cuMaxii
.globl _Z5cuMinii
.type _Z5cuMinii, @function
_Z5cuMinii:
.LFB2276:
.cfi_startproc
endbr64
cmpl %esi, %edi
movl %esi, %eax
cmovle %edi, %eax
ret
.cfi_endproc
.LFE2276:
.size _Z5cuMinii, .-_Z5cuMinii
.globl _Z8MycuRandR17curandStateXORWOW
.type _Z8MycuRandR17curandStateXORWOW, @function
_Z8MycuRandR17curandStateXORWOW:
.LFB2277:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2277:
.size _Z8MycuRandR17curandStateXORWOW, .-_Z8MycuRandR17curandStateXORWOW
.globl _Z10InitcuRandR17curandStateXORWOW
.type _Z10InitcuRandR17curandStateXORWOW, @function
_Z10InitcuRandR17curandStateXORWOW:
.LFB2278:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2278:
.size _Z10InitcuRandR17curandStateXORWOW, .-_Z10InitcuRandR17curandStateXORWOW
.globl _Z12dist_computePfS_S_S_iiiiiiiiiif
.type _Z12dist_computePfS_S_S_iiiiiiiiiif, @function
_Z12dist_computePfS_S_S_iiiiiiiiiif:
.LFB2279:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, -72(%rsp)
movq %rsi, -64(%rsp)
movq %rdx, -56(%rsp)
movq %rcx, -48(%rsp)
movl %r8d, -80(%rsp)
movl 56(%rsp), %r11d
movl 72(%rsp), %r14d
movl 80(%rsp), %ebx
movl 88(%rsp), %ecx
movl 96(%rsp), %r13d
movl 112(%rsp), %edx
movl %r9d, %eax
imull %r11d, %eax
movl %eax, -76(%rsp)
movl %r14d, %eax
imull 64(%rsp), %eax
movl %eax, -16(%rsp)
movl %edx, %eax
shrl $31, %eax
addl %eax, %edx
sarl %edx
negl %edx
movl %edx, %esi
negl %esi
cmpl %esi, %edx
jg .L16
movaps %xmm0, %xmm3
movl %edx, %r10d
movl %edx, %r8d
addl 104(%rsp), %r8d
leal (%rdx,%rcx), %esi
movl %esi, %ebp
imull %r11d, %ebp
movl %r8d, %r15d
imull %r14d, %r15d
addl $1, %ecx
subl %edx, %ecx
movl %ecx, %r12d
pxor %xmm2, %xmm2
movaps %xmm2, %xmm4
movaps %xmm2, %xmm0
leal 1(%rbx), %edi
subl %edx, %edi
movl %ebp, %r14d
jmp .L17
.L19:
movslq -76(%rsp), %r10
leaq 0(,%r10,4), %rbp
movq %rbp, -40(%rsp)
movslq %r14d, %r10
movslq -96(%rsp), %rbp
addq %rbp, %r10
salq $2, %r10
movq %r10, -96(%rsp)
movslq -16(%rsp), %rbp
salq $2, %rbp
movq %rbp, -32(%rsp)
movslq -84(%rsp), %rbp
movslq %r15d, %r10
addq %rbp, %r10
leaq 0(,%r10,4), %rbp
movq -96(%rsp), %r10
movl %r12d, -96(%rsp)
movl %eax, -24(%rsp)
movq %rbp, %rax
movl %edx, -12(%rsp)
movl $3, %edx
movl %r8d, -84(%rsp)
movl %esi, -8(%rsp)
movq -40(%rsp), %rsi
movl %r14d, -40(%rsp)
movl %edi, -4(%rsp)
movq -32(%rsp), %rdi
movq -72(%rsp), %r8
movq -64(%rsp), %rbp
movq -56(%rsp), %r12
movq -48(%rsp), %r14
.L22:
movss (%r8,%r10), %xmm1
subss 0(%rbp,%rax), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
movss (%r12,%r10), %xmm1
subss (%r14,%rax), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm2
addq %rsi, %r10
addq %rdi, %rax
subl $1, %edx
jne .L22
movl -96(%rsp), %r12d
movl -24(%rsp), %eax
movl -12(%rsp), %edx
movl -84(%rsp), %r8d
movl -8(%rsp), %esi
movl -40(%rsp), %r14d
movl -4(%rsp), %edi
jmp .L21
.L23:
movss (%r8,%r10), %xmm1
mulss 0(%rbp,%rax), %xmm1
subss %xmm1, %xmm0
movss (%r12,%r10), %xmm1
mulss (%r14,%rax), %xmm1
subss %xmm1, %xmm2
addl $1, %edx
addq %rsi, %r10
addq %rdi, %rax
cmpl %edx, %ecx
jne .L23
movl -84(%rsp), %r12d
movl -40(%rsp), %eax
movl -12(%rsp), %edx
movl -96(%rsp), %r8d
movl -8(%rsp), %esi
movl -32(%rsp), %r14d
movl -4(%rsp), %edi
movl -24(%rsp), %ecx
.L21:
addss .LC1(%rip), %xmm4
.L18:
addl $1, %eax
addl $1, %edx
cmpl %edi, %eax
je .L33
.L24:
testb %cl, %cl
je .L18
cmpl %esi, %r9d
jle .L18
movl %eax, -96(%rsp)
movl %eax, %r10d
orl %r8d, %r10d
js .L18
cmpl %r11d, %eax
jge .L18
cmpl %r8d, 64(%rsp)
jle .L18
movl %edx, -84(%rsp)
testl %edx, %edx
js .L18
cmpl 72(%rsp), %edx
jge .L18
movl -80(%rsp), %r10d
cmpl $3, %r10d
je .L19
testl %r10d, %r10d
jle .L21
movslq -76(%rsp), %r10
salq $2, %r10
movq %r10, -32(%rsp)
movslq -96(%rsp), %rbp
movslq %r14d, %r10
addq %rbp, %r10
salq $2, %r10
movq %r10, -40(%rsp)
movslq -16(%rsp), %r10
salq $2, %r10
movq %r10, -24(%rsp)
movslq -84(%rsp), %r10
movq %r10, -96(%rsp)
movslq %r15d, %r10
movq %r10, %rbp
movq -96(%rsp), %r10
addq %r10, %rbp
salq $2, %rbp
movl %r12d, -84(%rsp)
movq -40(%rsp), %r10
movl %eax, -40(%rsp)
movq %rbp, %rax
movl %edx, -12(%rsp)
movl $0, %edx
movl %r8d, -96(%rsp)
movl %esi, -8(%rsp)
movq -32(%rsp), %rsi
movl %r14d, -32(%rsp)
movl %edi, -4(%rsp)
movq -24(%rsp), %rdi
movq -72(%rsp), %r8
movq -64(%rsp), %rbp
movq -56(%rsp), %r12
movq -48(%rsp), %r14
movl %ecx, -24(%rsp)
movl -80(%rsp), %ecx
jmp .L23
.L33:
movl -88(%rsp), %r10d
addl $1, %r8d
addl $1, %esi
addl %r11d, %r14d
addl 72(%rsp), %r15d
cmpl %esi, %r12d
je .L25
.L17:
leal (%rbx,%r10), %eax
leal 0(%r13,%r10), %edx
movl %esi, %ecx
notl %ecx
shrl $31, %ecx
movl %r10d, -88(%rsp)
jmp .L24
.L25:
addss %xmm2, %xmm0
divss %xmm4, %xmm0
movaps %xmm3, %xmm1
cmpnless %xmm0, %xmm1
andps %xmm1, %xmm0
andnps %xmm3, %xmm1
orps %xmm1, %xmm0
.L15:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pxor %xmm0, %xmm0
divss %xmm0, %xmm0
jmp .L15
.cfi_endproc
.LFE2279:
.size _Z12dist_computePfS_S_S_iiiiiiiiiif, .-_Z12dist_computePfS_S_S_iiiiiiiiiif
.globl _Z4distPfS_S_S_iiiiiiiiiif
.type _Z4distPfS_S_S_iiiiiiiiiif, @function
_Z4distPfS_S_S_iiiiiiiiiif:
.LFB2280:
.cfi_startproc
endbr64
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 16
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 64(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
call _Z12dist_computePfS_S_S_iiiiiiiiiif
addq $64, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2280:
.size _Z4distPfS_S_S_iiiiiiiiiif, .-_Z4distPfS_S_S_iiiiiiiiiif
.globl _Z13improve_guessPfS_S_S_iiiiiiiRiS0_Rfiiif
.type _Z13improve_guessPfS_S_S_iiiiiiiRiS0_Rfiiif, @function
_Z13improve_guessPfS_S_S_iiiiiiiRiS0_Rfiiif:
.LFB2281:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2281:
.size _Z13improve_guessPfS_S_S_iiiiiiiRiS0_Rfiiif, .-_Z13improve_guessPfS_S_S_iiiiiiiRiS0_Rfiiif
.globl _Z39__device_stub__Z17initialAnn_kernelPjPiPjPi
.type _Z39__device_stub__Z17initialAnn_kernelPjPiPjPi, @function
_Z39__device_stub__Z17initialAnn_kernelPjPiPjPi:
.LFB2306:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17initialAnn_kernelPjPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2306:
.size _Z39__device_stub__Z17initialAnn_kernelPjPiPjPi, .-_Z39__device_stub__Z17initialAnn_kernelPjPiPjPi
.globl _Z17initialAnn_kernelPjPi
.type _Z17initialAnn_kernelPjPi, @function
_Z17initialAnn_kernelPjPi:
.LFB2307:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17initialAnn_kernelPjPiPjPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2307:
.size _Z17initialAnn_kernelPjPi, .-_Z17initialAnn_kernelPjPi
.globl _Z41__device_stub__Z15upSample_kernelPjS_PiiiPjS_Piii
.type _Z41__device_stub__Z15upSample_kernelPjS_PiiiPjS_Piii, @function
_Z41__device_stub__Z15upSample_kernelPjS_PiiiPjS_Piii:
.LFB2308:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15upSample_kernelPjS_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2308:
.size _Z41__device_stub__Z15upSample_kernelPjS_PiiiPjS_Piii, .-_Z41__device_stub__Z15upSample_kernelPjS_PiiiPjS_Piii
.globl _Z15upSample_kernelPjS_Piii
.type _Z15upSample_kernelPjS_Piii, @function
_Z15upSample_kernelPjS_Piii:
.LFB2309:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15upSample_kernelPjS_PiiiPjS_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2309:
.size _Z15upSample_kernelPjS_Piii, .-_Z15upSample_kernelPjS_Piii
.globl _Z49__device_stub__Z11patch_matchPfS_S_S_PjS_iiiiiiiiPfS_S_S_PjS_iiiiiiii
.type _Z49__device_stub__Z11patch_matchPfS_S_S_PjS_iiiiiiiiPfS_S_S_PjS_iiiiiiii, @function
_Z49__device_stub__Z11patch_matchPfS_S_S_PjS_iiiiiiiiPfS_S_S_PjS_iiiiiiii:
.LFB2310:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 312(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L57
.L53:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 264
pushq 56(%rsp)
.cfi_def_cfa_offset 272
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq patch_match(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L53
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2310:
.size _Z49__device_stub__Z11patch_matchPfS_S_S_PjS_iiiiiiiiPfS_S_S_PjS_iiiiiiii, .-_Z49__device_stub__Z11patch_matchPfS_S_S_PjS_iiiiiiiiPfS_S_S_PjS_iiiiiiii
.globl patch_match
.type patch_match, @function
patch_match:
.LFB2311:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
call _Z49__device_stub__Z11patch_matchPfS_S_S_PjS_iiiiiiiiPfS_S_S_PjS_iiiiiiii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2311:
.size patch_match, .-patch_match
.globl _Z31__device_stub__Z5blendPfS_S_fPiPfS_S_fPi
.type _Z31__device_stub__Z5blendPfS_S_fPiPfS_S_fPi, @function
_Z31__device_stub__Z5blendPfS_S_fPiPfS_S_fPi:
.LFB2312:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L65
.L61:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L66
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5blendPfS_S_fPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L61
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2312:
.size _Z31__device_stub__Z5blendPfS_S_fPiPfS_S_fPi, .-_Z31__device_stub__Z5blendPfS_S_fPiPfS_S_fPi
.globl _Z5blendPfS_S_fPi
.type _Z5blendPfS_S_fPi, @function
_Z5blendPfS_S_fPi:
.LFB2313:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z5blendPfS_S_fPiPfS_S_fPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2313:
.size _Z5blendPfS_S_fPi, .-_Z5blendPfS_S_fPi
.globl _Z38__device_stub__Z8avg_votePjPfS0_iiiiiiPjPfS0_iiiiii
.type _Z38__device_stub__Z8avg_votePjPfS0_iiiiiiPjPfS0_iiiiii, @function
_Z38__device_stub__Z8avg_votePjPfS0_iiiiiiPjPfS0_iiiiii:
.LFB2314:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L73
.L69:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq avg_vote(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L69
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2314:
.size _Z38__device_stub__Z8avg_votePjPfS0_iiiiiiPjPfS0_iiiiii, .-_Z38__device_stub__Z8avg_votePjPfS0_iiiiiiPjPfS0_iiiiii
.globl avg_vote
.type avg_vote, @function
avg_vote:
.LFB2315:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z38__device_stub__Z8avg_votePjPfS0_iiiiiiPjPfS0_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2315:
.size avg_vote, .-avg_vote
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "avg_vote"
.LC3:
.string "_Z5blendPfS_S_fPi"
.LC4:
.string "patch_match"
.LC5:
.string "_Z15upSample_kernelPjS_Piii"
.LC6:
.string "_Z17initialAnn_kernelPjPi"
.LC7:
.string "precalc_xorwow_matrix"
.LC8:
.string "precalc_xorwow_offset_matrix"
.LC9:
.string "mrg32k3aM1"
.LC10:
.string "mrg32k3aM2"
.LC11:
.string "mrg32k3aM1SubSeq"
.LC12:
.string "mrg32k3aM2SubSeq"
.LC13:
.string "mrg32k3aM1Seq"
.LC14:
.string "mrg32k3aM2Seq"
.LC15:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2317:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq avg_vote(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5blendPfS_S_fPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq patch_match(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15upSample_kernelPjS_Piii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z17initialAnn_kernelPjPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2317:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "GeneralizedPatchMatch.hip"
.globl _Z5clampiii # -- Begin function _Z5clampiii
.p2align 4, 0x90
.type _Z5clampiii,@function
_Z5clampiii: # @_Z5clampiii
.cfi_startproc
# %bb.0:
movl %edx, %eax
cmpl %edx, %edi
cmovgl %edi, %eax
cmpl %esi, %edi
cmovgl %esi, %eax
retq
.Lfunc_end0:
.size _Z5clampiii, .Lfunc_end0-_Z5clampiii
.cfi_endproc
# -- End function
.globl _Z9XY_TO_INTii # -- Begin function _Z9XY_TO_INTii
.p2align 4, 0x90
.type _Z9XY_TO_INTii,@function
_Z9XY_TO_INTii: # @_Z9XY_TO_INTii
.cfi_startproc
# %bb.0:
movl %esi, %eax
shll $11, %eax
orl %edi, %eax
retq
.Lfunc_end1:
.size _Z9XY_TO_INTii, .Lfunc_end1-_Z9XY_TO_INTii
.cfi_endproc
# -- End function
.globl _Z8INT_TO_Xj # -- Begin function _Z8INT_TO_Xj
.p2align 4, 0x90
.type _Z8INT_TO_Xj,@function
_Z8INT_TO_Xj: # @_Z8INT_TO_Xj
.cfi_startproc
# %bb.0:
movl %edi, %eax
andl $2047, %eax # imm = 0x7FF
retq
.Lfunc_end2:
.size _Z8INT_TO_Xj, .Lfunc_end2-_Z8INT_TO_Xj
.cfi_endproc
# -- End function
.globl _Z8INT_TO_Yj # -- Begin function _Z8INT_TO_Yj
.p2align 4, 0x90
.type _Z8INT_TO_Yj,@function
_Z8INT_TO_Yj: # @_Z8INT_TO_Yj
.cfi_startproc
# %bb.0:
movl %edi, %eax
shrl $11, %eax
andl $2047, %eax # imm = 0x7FF
retq
.Lfunc_end3:
.size _Z8INT_TO_Yj, .Lfunc_end3-_Z8INT_TO_Yj
.cfi_endproc
# -- End function
.globl _Z5cuMaxii # -- Begin function _Z5cuMaxii
.p2align 4, 0x90
.type _Z5cuMaxii,@function
_Z5cuMaxii: # @_Z5cuMaxii
.cfi_startproc
# %bb.0:
movl %esi, %eax
cmpl %esi, %edi
cmovgl %edi, %eax
retq
.Lfunc_end4:
.size _Z5cuMaxii, .Lfunc_end4-_Z5cuMaxii
.cfi_endproc
# -- End function
.globl _Z5cuMinii # -- Begin function _Z5cuMinii
.p2align 4, 0x90
.type _Z5cuMinii,@function
_Z5cuMinii: # @_Z5cuMinii
.cfi_startproc
# %bb.0:
movl %esi, %eax
cmpl %esi, %edi
cmovll %edi, %eax
retq
.Lfunc_end5:
.size _Z5cuMinii, .Lfunc_end5-_Z5cuMinii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z12dist_computePfS_S_S_iiiiiiiiiif
.LCPI6_0:
.long 0x7fc00000 # float NaN
.LCPI6_1:
.long 0x3f800000 # float 1
.text
.globl _Z12dist_computePfS_S_S_iiiiiiiiiif
.p2align 4, 0x90
.type _Z12dist_computePfS_S_S_iiiiiiiiiif,@function
_Z12dist_computePfS_S_S_iiiiiiiiiif: # @_Z12dist_computePfS_S_S_iiiiiiiiiif
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %r14d
movl 112(%rsp), %r10d
movl %r10d, %eax
shrl $31, %eax
addl %r10d, %eax
sarl %eax
movl %eax, %r8d
negl %r8d
cmpl %eax, %r8d
jle .LBB6_2
# %bb.1:
movss .LCPI6_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
jmp .LBB6_12
.LBB6_2: # %.preheader154.lr.ph
movl 104(%rsp), %r11d
movl 96(%rsp), %r15d
movl 88(%rsp), %ebx
movl 80(%rsp), %r12d
movl 72(%rsp), %ebp
movl 56(%rsp), %r13d
movl %r14d, %r10d
movq %r10, -8(%rsp) # 8-byte Spill
leal (%r8,%r11), %r11d
imull %ebp, %r11d
addl %r8d, %r11d
addl %r15d, %r11d
imull 64(%rsp), %ebp
leal (%r8,%r12), %r10d
movl %r11d, %r12d
addl %r8d, %ebx
imull %r13d, %ebx
addl %r10d, %ebx
imull %r9d, %r13d
xorps %xmm1, %xmm1
movss .LCPI6_1(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movl %r8d, %r10d
xorps %xmm4, %xmm4
xorps %xmm2, %xmm2
movl %r14d, -40(%rsp) # 4-byte Spill
movl %r9d, -36(%rsp) # 4-byte Spill
movq %r8, -24(%rsp) # 8-byte Spill
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_17: # %._crit_edge
# in Loop: Header=BB6_3 Depth=1
movq -16(%rsp), %r10 # 8-byte Reload
leal 1(%r10), %r9d
movl -28(%rsp), %r12d # 4-byte Reload
addl 72(%rsp), %r12d
movl -32(%rsp), %ebx # 4-byte Reload
addl 56(%rsp), %ebx
cmpl %eax, %r10d
movl %r9d, %r10d
movl -36(%rsp), %r9d # 4-byte Reload
movq -24(%rsp), %r8 # 8-byte Reload
je .LBB6_11
.LBB6_3: # %.preheader154
# =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
# Child Loop BB6_10 Depth 3
# Child Loop BB6_14 Depth 3
movl %r10d, %r11d
movq %r10, %r14
movl 88(%rsp), %r10d
addl %r10d, %r11d
setns %r10b
cmpl %r9d, %r11d
movl %ebx, %r11d
setl %bl
andb %r10b, %bl
movq %r14, -16(%rsp) # 8-byte Spill
movl %r14d, %r10d
movl 104(%rsp), %r9d
addl %r9d, %r10d
sets %r9b
cmpl 64(%rsp), %r10d
setge %r10b
orb %r9b, %r10b
movb %r10b, -41(%rsp) # 1-byte Spill
movl %r11d, -32(%rsp) # 4-byte Spill
movl %r11d, %r10d
movl %r12d, -28(%rsp) # 4-byte Spill
movl %r8d, %r14d
movl -40(%rsp), %r8d # 4-byte Reload
jmp .LBB6_4
.LBB6_15: # %.loopexit
# in Loop: Header=BB6_4 Depth=2
addss %xmm3, %xmm4
movl -40(%rsp), %r8d # 4-byte Reload
movl 96(%rsp), %r15d
.p2align 4, 0x90
.LBB6_16: # in Loop: Header=BB6_4 Depth=2
leal 1(%r14), %r9d
incl %r12d
incl %r10d
cmpl %eax, %r14d
movl %r9d, %r14d
je .LBB6_17
.LBB6_4: # Parent Loop BB6_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_10 Depth 3
# Child Loop BB6_14 Depth 3
testb %bl, %bl
je .LBB6_16
# %bb.5: # in Loop: Header=BB6_4 Depth=2
movl %r14d, %r9d
movl 80(%rsp), %r11d
addl %r11d, %r9d
sets %r11b
cmpl 56(%rsp), %r9d
setge %r9b
orb -41(%rsp), %r11b # 1-byte Folded Reload
orb %r9b, %r11b
jne .LBB6_16
# %bb.6: # in Loop: Header=BB6_4 Depth=2
leal (%r14,%r15), %r9d
cmpl 72(%rsp), %r9d
jge .LBB6_16
# %bb.7: # in Loop: Header=BB6_4 Depth=2
testl %r9d, %r9d
js .LBB6_16
# %bb.8: # in Loop: Header=BB6_4 Depth=2
cmpl $3, %r8d
jne .LBB6_9
# %bb.13: # %.preheader
# in Loop: Header=BB6_4 Depth=2
movl $3, %r15d
movl %r10d, %r9d
movl %r12d, %r11d
.p2align 4, 0x90
.LBB6_14: # Parent Loop BB6_3 Depth=1
# Parent Loop BB6_4 Depth=2
# => This Inner Loop Header: Depth=3
movslq %r9d, %r9
movss (%rdi,%r9,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movslq %r11d, %r11
subss (%rsi,%r11,4), %xmm5
mulss %xmm5, %xmm5
addss %xmm5, %xmm1
movss (%rdx,%r9,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss (%rcx,%r11,4), %xmm5
mulss %xmm5, %xmm5
addss %xmm5, %xmm2
addl %ebp, %r11d
addl %r13d, %r9d
decq %r15
jne .LBB6_14
jmp .LBB6_15
.LBB6_9: # %.preheader152
# in Loop: Header=BB6_4 Depth=2
movq -8(%rsp), %r15 # 8-byte Reload
movl %r10d, %r11d
movl %r12d, %r9d
testl %r8d, %r8d
jle .LBB6_15
.p2align 4, 0x90
.LBB6_10: # Parent Loop BB6_3 Depth=1
# Parent Loop BB6_4 Depth=2
# => This Inner Loop Header: Depth=3
movslq %r11d, %r11
movss (%rdi,%r11,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movslq %r9d, %r9
mulss (%rsi,%r9,4), %xmm5
subss %xmm5, %xmm1
movss (%rdx,%r11,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
mulss (%rcx,%r9,4), %xmm5
subss %xmm5, %xmm2
addl %ebp, %r9d
addl %r13d, %r11d
decq %r15
jne .LBB6_10
jmp .LBB6_15
.LBB6_11: # %._crit_edge176.loopexit
addss %xmm1, %xmm2
divss %xmm4, %xmm2
.LBB6_12: # %._crit_edge176
movaps %xmm0, %xmm1
cmpless %xmm2, %xmm1
andps %xmm1, %xmm0
andnps %xmm2, %xmm1
orps %xmm0, %xmm1
movaps %xmm1, %xmm0
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z12dist_computePfS_S_S_iiiiiiiiiif, .Lfunc_end6-_Z12dist_computePfS_S_S_iiiiiiiiiif
.cfi_endproc
# -- End function
.globl _Z4distPfS_S_S_iiiiiiiiiif # -- Begin function _Z4distPfS_S_S_iiiiiiiiiif
.p2align 4, 0x90
.type _Z4distPfS_S_S_iiiiiiiiiif,@function
_Z4distPfS_S_S_iiiiiiiiiif: # @_Z4distPfS_S_S_iiiiiiiiiif
.cfi_startproc
# %bb.0:
jmp _Z12dist_computePfS_S_S_iiiiiiiiiif # TAILCALL
.Lfunc_end7:
.size _Z4distPfS_S_S_iiiiiiiiiif, .Lfunc_end7-_Z4distPfS_S_S_iiiiiiiiiif
.cfi_endproc
# -- End function
.globl _Z32__device_stub__initialAnn_kernelPjPi # -- Begin function _Z32__device_stub__initialAnn_kernelPjPi
.p2align 4, 0x90
.type _Z32__device_stub__initialAnn_kernelPjPi,@function
_Z32__device_stub__initialAnn_kernelPjPi: # @_Z32__device_stub__initialAnn_kernelPjPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17initialAnn_kernelPjPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end8:
.size _Z32__device_stub__initialAnn_kernelPjPi, .Lfunc_end8-_Z32__device_stub__initialAnn_kernelPjPi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__upSample_kernelPjS_Piii # -- Begin function _Z30__device_stub__upSample_kernelPjS_Piii
.p2align 4, 0x90
.type _Z30__device_stub__upSample_kernelPjS_Piii,@function
_Z30__device_stub__upSample_kernelPjS_Piii: # @_Z30__device_stub__upSample_kernelPjS_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15upSample_kernelPjS_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end9:
.size _Z30__device_stub__upSample_kernelPjS_Piii, .Lfunc_end9-_Z30__device_stub__upSample_kernelPjS_Piii
.cfi_endproc
# -- End function
.globl __device_stub__patch_match # -- Begin function __device_stub__patch_match
.p2align 4, 0x90
.type __device_stub__patch_match,@function
__device_stub__patch_match: # @__device_stub__patch_match
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $patch_match, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end10:
.size __device_stub__patch_match, .Lfunc_end10-__device_stub__patch_match
.cfi_endproc
# -- End function
.globl _Z20__device_stub__blendPfS_S_fPi # -- Begin function _Z20__device_stub__blendPfS_S_fPi
.p2align 4, 0x90
.type _Z20__device_stub__blendPfS_S_fPi,@function
_Z20__device_stub__blendPfS_S_fPi: # @_Z20__device_stub__blendPfS_S_fPi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rcx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5blendPfS_S_fPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end11:
.size _Z20__device_stub__blendPfS_S_fPi, .Lfunc_end11-_Z20__device_stub__blendPfS_S_fPi
.cfi_endproc
# -- End function
.globl __device_stub__avg_vote # -- Begin function __device_stub__avg_vote
.p2align 4, 0x90
.type __device_stub__avg_vote,@function
__device_stub__avg_vote: # @__device_stub__avg_vote
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $avg_vote, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end12:
.size __device_stub__avg_vote, .Lfunc_end12-__device_stub__avg_vote
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB13_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB13_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17initialAnn_kernelPjPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15upSample_kernelPjS_Piii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $patch_match, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5blendPfS_S_fPi, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $avg_vote, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end13:
.size __hip_module_ctor, .Lfunc_end13-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB14_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB14_2:
retq
.Lfunc_end14:
.size __hip_module_dtor, .Lfunc_end14-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17initialAnn_kernelPjPi,@object # @_Z17initialAnn_kernelPjPi
.section .rodata,"a",@progbits
.globl _Z17initialAnn_kernelPjPi
.p2align 3, 0x0
_Z17initialAnn_kernelPjPi:
.quad _Z32__device_stub__initialAnn_kernelPjPi
.size _Z17initialAnn_kernelPjPi, 8
.type _Z15upSample_kernelPjS_Piii,@object # @_Z15upSample_kernelPjS_Piii
.globl _Z15upSample_kernelPjS_Piii
.p2align 3, 0x0
_Z15upSample_kernelPjS_Piii:
.quad _Z30__device_stub__upSample_kernelPjS_Piii
.size _Z15upSample_kernelPjS_Piii, 8
.type patch_match,@object # @patch_match
.globl patch_match
.p2align 3, 0x0
patch_match:
.quad __device_stub__patch_match
.size patch_match, 8
.type _Z5blendPfS_S_fPi,@object # @_Z5blendPfS_S_fPi
.globl _Z5blendPfS_S_fPi
.p2align 3, 0x0
_Z5blendPfS_S_fPi:
.quad _Z20__device_stub__blendPfS_S_fPi
.size _Z5blendPfS_S_fPi, 8
.type avg_vote,@object # @avg_vote
.globl avg_vote
.p2align 3, 0x0
avg_vote:
.quad __device_stub__avg_vote
.size avg_vote, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17initialAnn_kernelPjPi"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15upSample_kernelPjS_Piii"
.size .L__unnamed_2, 28
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "patch_match"
.size .L__unnamed_3, 12
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z5blendPfS_S_fPi"
.size .L__unnamed_4, 18
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "avg_vote"
.size .L__unnamed_5, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__initialAnn_kernelPjPi
.addrsig_sym _Z30__device_stub__upSample_kernelPjS_Piii
.addrsig_sym __device_stub__patch_match
.addrsig_sym _Z20__device_stub__blendPfS_S_fPi
.addrsig_sym __device_stub__avg_vote
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17initialAnn_kernelPjPi
.addrsig_sym _Z15upSample_kernelPjS_Piii
.addrsig_sym patch_match
.addrsig_sym _Z5blendPfS_S_fPi
.addrsig_sym avg_vote
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define t_max 1
#define t 1
/*
(u[0][0][0][0][0]=((alpha*(ux[1][0][0][0][1]-ux[-1][0][0][0][1]))+((beta*(uy[0][1][0][0][2]-uy[0][-1][0][0][2]))+(gamma*(uz[0][0][1][0][3]-uz[0][0][-1][0][3])))))
*/
__global__ void divergence(float * * u_0_0_out, float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
/*
float * const u__u_0[16] = { u_0_0 } ;
float * const u__ux_1[16] = { ux_1_0 } ;
float * const u__uy_2[16] = { uy_2_0 } ;
float * const u__uz_3[16] = { uz_3_0 } ;
*/
int _idx0;
int _idx1;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int chunk_idx_x;
int chunk_idx_x_max;
int chunk_idx_y;
int chunk_idx_y_max;
int chunk_idx_z;
int chunk_idx_z_max;
int idx_1_2;
int size_1_1;
int size_1_2;
//int t;
int thd_idx_x;
int thd_idx_y;
int thd_idx_z;
int thdblks_idx_x;
int thdblks_idx_x_max;
int thdblks_idx_y;
int thdblks_idx_y_max;
int thdblks_idx_z;
int thdblks_idx_z_max;
int tmp;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
chunk_idx_x_max=(chunk_idx_x+c);
chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
chunk_idx_y_max=(chunk_idx_y+1);
chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
chunk_idx_z_max=(chunk_idx_z+1);
thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
thdblks_idx_x_max=(thdblks_idx_x+tbx);
thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
thdblks_idx_y_max=(thdblks_idx_y+tby);
thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
thdblks_idx_z_max=(thdblks_idx_z+tbz);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
/*
for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
thd_idx_z=chunk_idx_z;
thd_idx_y=chunk_idx_y;
for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
/*
u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
*/
/* _idx0 = (((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2) */
_idx0=(((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2);
/* _idx1 = ((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x) */
_idx1=(_idx0-2);
/* _idx2 = ((((thd_idx_z*x_max)*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+2)*x_max))+thd_idx_x) */
_idx2=(((_idx1-(((2*t)*thd_idx_z)*y_max))+((((2*t)*thd_idx_z)+2)*x_max))-((2*t)*thd_idx_y));
/* _idx3 = ((((thd_idx_z*x_max)*y_max)+((((2*t)*thd_idx_z)+thd_idx_y)*x_max))+thd_idx_x) */
_idx3=(_idx2-(2*x_max));
/* _idx4 = (((((thd_idx_z+2)*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx4=((_idx3+((2*x_max)*y_max))-(((2*t)*thd_idx_z)*x_max));
/* _idx5 = ((((thd_idx_z*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx5=(_idx4-((2*x_max)*y_max));
u_0_0[_idx5]=((alpha*(ux_1_0[_idx0]-ux_1_0[_idx1]))+((beta*(uy_2_0[_idx2]-uy_2_0[_idx3]))+(gamma*(uz_3_0[_idx4]-uz_3_0[_idx5]))));
}
}
}
}
__global__ void initialize(float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
float * const u__u_0[16] = { u_0_0 } ;
float * const u__ux_1[16] = { ux_1_0 } ;
float * const u__uy_2[16] = { uy_2_0 } ;
float * const u__uz_3[16] = { uz_3_0 } ;
int _idx0;
int _idx1;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int chunk_idx_x;
int chunk_idx_x_max;
int chunk_idx_y;
int chunk_idx_y_max;
int chunk_idx_z;
int chunk_idx_z_max;
int idx_1_2;
int size_1_1;
int size_1_2;
//int t;
int thd_idx_x;
int thd_idx_y;
int thd_idx_z;
int thdblks_idx_x;
int thdblks_idx_x_max;
int thdblks_idx_y;
int thdblks_idx_y_max;
int thdblks_idx_z;
int thdblks_idx_z_max;
int tmp;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
chunk_idx_x_max=(chunk_idx_x+c);
chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
chunk_idx_y_max=(chunk_idx_y+1);
chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
chunk_idx_z_max=(chunk_idx_z+1);
thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
thdblks_idx_x_max=(thdblks_idx_x+tbx);
thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
thdblks_idx_y_max=(thdblks_idx_y+tby);
thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
thdblks_idx_z_max=(thdblks_idx_z+tbz);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
/*
for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
thd_idx_z=chunk_idx_z;
thd_idx_y=chunk_idx_y;
for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
/*
u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x) */
_idx0=((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x);
u__ux_1[(t-1)][_idx0]=0.2;
/* _idx1 = ((((thd_idx_z*x_max)*y_max)+((((2*t)*thd_idx_z)+thd_idx_y)*x_max))+thd_idx_x) */
_idx1=(((_idx0-(((2*t)*thd_idx_z)*y_max))+(((2*t)*thd_idx_z)*x_max))-((2*t)*thd_idx_y));
u__uy_2[(t-1)][_idx1]=0.30000000000000004;
/* _idx2 = ((((thd_idx_z*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx2=(_idx1-(((2*t)*thd_idx_z)*x_max));
u__uz_3[(t-1)][_idx2]=0.4;
/* _idx3 = (((((thd_idx_z+2)*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx3=(_idx2+((2*x_max)*y_max));
u__uz_3[(t-1)][_idx3]=0.4;
/* _idx4 = ((((thd_idx_z*x_max)*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+2)*x_max))+thd_idx_x) */
_idx4=(_idx1+(2*x_max));
u__uy_2[(t-1)][_idx4]=0.30000000000000004;
/* _idx5 = (((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2) */
_idx5=(_idx0+2);
u__ux_1[(t-1)][_idx5]=0.2;
u__u_0[(t-1)][_idx2]=0.1;
}
}
}
} | .file "tmpxft_0009d1cc_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z10divergencePPfS_S_S_S_fffiiiiiiiPPfS_S_S_S_fffiiiiiii
.type _Z49__device_stub__Z10divergencePPfS_S_S_S_fffiiiiiiiPPfS_S_S_S_fffiiiiiii, @function
_Z49__device_stub__Z10divergencePPfS_S_S_S_fffiiiiiiiPPfS_S_S_S_fffiiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
leaq 288(%rsp), %rax
movq %rax, 216(%rsp)
leaq 296(%rsp), %rax
movq %rax, 224(%rsp)
leaq 304(%rsp), %rax
movq %rax, 232(%rsp)
leaq 312(%rsp), %rax
movq %rax, 240(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 280
pushq 72(%rsp)
.cfi_def_cfa_offset 288
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z10divergencePPfS_S_S_S_fffiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z10divergencePPfS_S_S_S_fffiiiiiiiPPfS_S_S_S_fffiiiiiii, .-_Z49__device_stub__Z10divergencePPfS_S_S_S_fffiiiiiiiPPfS_S_S_S_fffiiiiiii
.globl _Z10divergencePPfS_S_S_S_fffiiiiiii
.type _Z10divergencePPfS_S_S_S_fffiiiiiii, @function
_Z10divergencePPfS_S_S_S_fffiiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z49__device_stub__Z10divergencePPfS_S_S_S_fffiiiiiiiPPfS_S_S_S_fffiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10divergencePPfS_S_S_S_fffiiiiiii, .-_Z10divergencePPfS_S_S_S_fffiiiiiii
.globl _Z46__device_stub__Z10initializePfS_S_S_fffiiiiiiiPfS_S_S_fffiiiiiii
.type _Z46__device_stub__Z10initializePfS_S_S_fffiiiiiiiPfS_S_S_fffiiiiiii, @function
_Z46__device_stub__Z10initializePfS_S_S_fffiiiiiiiPfS_S_S_fffiiiiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
leaq 288(%rsp), %rax
movq %rax, 216(%rsp)
leaq 296(%rsp), %rax
movq %rax, 224(%rsp)
leaq 304(%rsp), %rax
movq %rax, 232(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 280
pushq 72(%rsp)
.cfi_def_cfa_offset 288
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z10initializePfS_S_S_fffiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z46__device_stub__Z10initializePfS_S_S_fffiiiiiiiPfS_S_S_fffiiiiiii, .-_Z46__device_stub__Z10initializePfS_S_S_fffiiiiiiiPfS_S_S_fffiiiiiii
.globl _Z10initializePfS_S_S_fffiiiiiii
.type _Z10initializePfS_S_S_fffiiiiiii, @function
_Z10initializePfS_S_S_fffiiiiiii:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z46__device_stub__Z10initializePfS_S_S_fffiiiiiiiPfS_S_S_fffiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z10initializePfS_S_S_fffiiiiiii, .-_Z10initializePfS_S_S_fffiiiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10initializePfS_S_S_fffiiiiiii"
.align 8
.LC1:
.string "_Z10divergencePPfS_S_S_S_fffiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePfS_S_S_fffiiiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10divergencePPfS_S_S_S_fffiiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define t_max 1
#define t 1
/*
(u[0][0][0][0][0]=((alpha*(ux[1][0][0][0][1]-ux[-1][0][0][0][1]))+((beta*(uy[0][1][0][0][2]-uy[0][-1][0][0][2]))+(gamma*(uz[0][0][1][0][3]-uz[0][0][-1][0][3])))))
*/
__global__ void divergence(float * * u_0_0_out, float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
/*
float * const u__u_0[16] = { u_0_0 } ;
float * const u__ux_1[16] = { ux_1_0 } ;
float * const u__uy_2[16] = { uy_2_0 } ;
float * const u__uz_3[16] = { uz_3_0 } ;
*/
int _idx0;
int _idx1;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int chunk_idx_x;
int chunk_idx_x_max;
int chunk_idx_y;
int chunk_idx_y_max;
int chunk_idx_z;
int chunk_idx_z_max;
int idx_1_2;
int size_1_1;
int size_1_2;
//int t;
int thd_idx_x;
int thd_idx_y;
int thd_idx_z;
int thdblks_idx_x;
int thdblks_idx_x_max;
int thdblks_idx_y;
int thdblks_idx_y_max;
int thdblks_idx_z;
int thdblks_idx_z_max;
int tmp;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
chunk_idx_x_max=(chunk_idx_x+c);
chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
chunk_idx_y_max=(chunk_idx_y+1);
chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
chunk_idx_z_max=(chunk_idx_z+1);
thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
thdblks_idx_x_max=(thdblks_idx_x+tbx);
thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
thdblks_idx_y_max=(thdblks_idx_y+tby);
thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
thdblks_idx_z_max=(thdblks_idx_z+tbz);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
/*
for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
thd_idx_z=chunk_idx_z;
thd_idx_y=chunk_idx_y;
for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
/*
u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
*/
/* _idx0 = (((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2) */
_idx0=(((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2);
/* _idx1 = ((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x) */
_idx1=(_idx0-2);
/* _idx2 = ((((thd_idx_z*x_max)*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+2)*x_max))+thd_idx_x) */
_idx2=(((_idx1-(((2*t)*thd_idx_z)*y_max))+((((2*t)*thd_idx_z)+2)*x_max))-((2*t)*thd_idx_y));
/* _idx3 = ((((thd_idx_z*x_max)*y_max)+((((2*t)*thd_idx_z)+thd_idx_y)*x_max))+thd_idx_x) */
_idx3=(_idx2-(2*x_max));
/* _idx4 = (((((thd_idx_z+2)*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx4=((_idx3+((2*x_max)*y_max))-(((2*t)*thd_idx_z)*x_max));
/* _idx5 = ((((thd_idx_z*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx5=(_idx4-((2*x_max)*y_max));
u_0_0[_idx5]=((alpha*(ux_1_0[_idx0]-ux_1_0[_idx1]))+((beta*(uy_2_0[_idx2]-uy_2_0[_idx3]))+(gamma*(uz_3_0[_idx4]-uz_3_0[_idx5]))));
}
}
}
}
__global__ void initialize(float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
float * const u__u_0[16] = { u_0_0 } ;
float * const u__ux_1[16] = { ux_1_0 } ;
float * const u__uy_2[16] = { uy_2_0 } ;
float * const u__uz_3[16] = { uz_3_0 } ;
int _idx0;
int _idx1;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int chunk_idx_x;
int chunk_idx_x_max;
int chunk_idx_y;
int chunk_idx_y_max;
int chunk_idx_z;
int chunk_idx_z_max;
int idx_1_2;
int size_1_1;
int size_1_2;
//int t;
int thd_idx_x;
int thd_idx_y;
int thd_idx_z;
int thdblks_idx_x;
int thdblks_idx_x_max;
int thdblks_idx_y;
int thdblks_idx_y_max;
int thdblks_idx_z;
int thdblks_idx_z_max;
int tmp;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
chunk_idx_x_max=(chunk_idx_x+c);
chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
chunk_idx_y_max=(chunk_idx_y+1);
chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
chunk_idx_z_max=(chunk_idx_z+1);
thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
thdblks_idx_x_max=(thdblks_idx_x+tbx);
thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
thdblks_idx_y_max=(thdblks_idx_y+tby);
thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
thdblks_idx_z_max=(thdblks_idx_z+tbz);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
/*
for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
thd_idx_z=chunk_idx_z;
thd_idx_y=chunk_idx_y;
for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
/*
u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x) */
_idx0=((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x);
u__ux_1[(t-1)][_idx0]=0.2;
/* _idx1 = ((((thd_idx_z*x_max)*y_max)+((((2*t)*thd_idx_z)+thd_idx_y)*x_max))+thd_idx_x) */
_idx1=(((_idx0-(((2*t)*thd_idx_z)*y_max))+(((2*t)*thd_idx_z)*x_max))-((2*t)*thd_idx_y));
u__uy_2[(t-1)][_idx1]=0.30000000000000004;
/* _idx2 = ((((thd_idx_z*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx2=(_idx1-(((2*t)*thd_idx_z)*x_max));
u__uz_3[(t-1)][_idx2]=0.4;
/* _idx3 = (((((thd_idx_z+2)*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx3=(_idx2+((2*x_max)*y_max));
u__uz_3[(t-1)][_idx3]=0.4;
/* _idx4 = ((((thd_idx_z*x_max)*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+2)*x_max))+thd_idx_x) */
_idx4=(_idx1+(2*x_max));
u__uy_2[(t-1)][_idx4]=0.30000000000000004;
/* _idx5 = (((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2) */
_idx5=(_idx0+2);
u__ux_1[(t-1)][_idx5]=0.2;
u__u_0[(t-1)][_idx2]=0.1;
}
}
}
} | #include <hip/hip_runtime.h>
#define t_max 1
#define t 1
/*
(u[0][0][0][0][0]=((alpha*(ux[1][0][0][0][1]-ux[-1][0][0][0][1]))+((beta*(uy[0][1][0][0][2]-uy[0][-1][0][0][2]))+(gamma*(uz[0][0][1][0][3]-uz[0][0][-1][0][3])))))
*/
__global__ void divergence(float * * u_0_0_out, float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
/*
float * const u__u_0[16] = { u_0_0 } ;
float * const u__ux_1[16] = { ux_1_0 } ;
float * const u__uy_2[16] = { uy_2_0 } ;
float * const u__uz_3[16] = { uz_3_0 } ;
*/
int _idx0;
int _idx1;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int chunk_idx_x;
int chunk_idx_x_max;
int chunk_idx_y;
int chunk_idx_y_max;
int chunk_idx_z;
int chunk_idx_z_max;
int idx_1_2;
int size_1_1;
int size_1_2;
//int t;
int thd_idx_x;
int thd_idx_y;
int thd_idx_z;
int thdblks_idx_x;
int thdblks_idx_x_max;
int thdblks_idx_y;
int thdblks_idx_y_max;
int thdblks_idx_z;
int thdblks_idx_z_max;
int tmp;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
chunk_idx_x_max=(chunk_idx_x+c);
chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
chunk_idx_y_max=(chunk_idx_y+1);
chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
chunk_idx_z_max=(chunk_idx_z+1);
thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
thdblks_idx_x_max=(thdblks_idx_x+tbx);
thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
thdblks_idx_y_max=(thdblks_idx_y+tby);
thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
thdblks_idx_z_max=(thdblks_idx_z+tbz);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
/*
for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
thd_idx_z=chunk_idx_z;
thd_idx_y=chunk_idx_y;
for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
/*
u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
*/
/* _idx0 = (((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2) */
_idx0=(((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2);
/* _idx1 = ((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x) */
_idx1=(_idx0-2);
/* _idx2 = ((((thd_idx_z*x_max)*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+2)*x_max))+thd_idx_x) */
_idx2=(((_idx1-(((2*t)*thd_idx_z)*y_max))+((((2*t)*thd_idx_z)+2)*x_max))-((2*t)*thd_idx_y));
/* _idx3 = ((((thd_idx_z*x_max)*y_max)+((((2*t)*thd_idx_z)+thd_idx_y)*x_max))+thd_idx_x) */
_idx3=(_idx2-(2*x_max));
/* _idx4 = (((((thd_idx_z+2)*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx4=((_idx3+((2*x_max)*y_max))-(((2*t)*thd_idx_z)*x_max));
/* _idx5 = ((((thd_idx_z*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx5=(_idx4-((2*x_max)*y_max));
u_0_0[_idx5]=((alpha*(ux_1_0[_idx0]-ux_1_0[_idx1]))+((beta*(uy_2_0[_idx2]-uy_2_0[_idx3]))+(gamma*(uz_3_0[_idx4]-uz_3_0[_idx5]))));
}
}
}
}
__global__ void initialize(float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
float * const u__u_0[16] = { u_0_0 } ;
float * const u__ux_1[16] = { ux_1_0 } ;
float * const u__uy_2[16] = { uy_2_0 } ;
float * const u__uz_3[16] = { uz_3_0 } ;
int _idx0;
int _idx1;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int chunk_idx_x;
int chunk_idx_x_max;
int chunk_idx_y;
int chunk_idx_y_max;
int chunk_idx_z;
int chunk_idx_z_max;
int idx_1_2;
int size_1_1;
int size_1_2;
//int t;
int thd_idx_x;
int thd_idx_y;
int thd_idx_z;
int thdblks_idx_x;
int thdblks_idx_x_max;
int thdblks_idx_y;
int thdblks_idx_y_max;
int thdblks_idx_z;
int thdblks_idx_z_max;
int tmp;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
chunk_idx_x_max=(chunk_idx_x+c);
chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
chunk_idx_y_max=(chunk_idx_y+1);
chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
chunk_idx_z_max=(chunk_idx_z+1);
thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
thdblks_idx_x_max=(thdblks_idx_x+tbx);
thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
thdblks_idx_y_max=(thdblks_idx_y+tby);
thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
thdblks_idx_z_max=(thdblks_idx_z+tbz);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
/*
for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
thd_idx_z=chunk_idx_z;
thd_idx_y=chunk_idx_y;
for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
/*
u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x) */
_idx0=((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x);
u__ux_1[(t-1)][_idx0]=0.2;
/* _idx1 = ((((thd_idx_z*x_max)*y_max)+((((2*t)*thd_idx_z)+thd_idx_y)*x_max))+thd_idx_x) */
_idx1=(((_idx0-(((2*t)*thd_idx_z)*y_max))+(((2*t)*thd_idx_z)*x_max))-((2*t)*thd_idx_y));
u__uy_2[(t-1)][_idx1]=0.30000000000000004;
/* _idx2 = ((((thd_idx_z*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx2=(_idx1-(((2*t)*thd_idx_z)*x_max));
u__uz_3[(t-1)][_idx2]=0.4;
/* _idx3 = (((((thd_idx_z+2)*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx3=(_idx2+((2*x_max)*y_max));
u__uz_3[(t-1)][_idx3]=0.4;
/* _idx4 = ((((thd_idx_z*x_max)*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+2)*x_max))+thd_idx_x) */
_idx4=(_idx1+(2*x_max));
u__uy_2[(t-1)][_idx4]=0.30000000000000004;
/* _idx5 = (((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2) */
_idx5=(_idx0+2);
u__ux_1[(t-1)][_idx5]=0.2;
u__u_0[(t-1)][_idx2]=0.1;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define t_max 1
#define t 1
/*
(u[0][0][0][0][0]=((alpha*(ux[1][0][0][0][1]-ux[-1][0][0][0][1]))+((beta*(uy[0][1][0][0][2]-uy[0][-1][0][0][2]))+(gamma*(uz[0][0][1][0][3]-uz[0][0][-1][0][3])))))
*/
__global__ void divergence(float * * u_0_0_out, float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
/*
float * const u__u_0[16] = { u_0_0 } ;
float * const u__ux_1[16] = { ux_1_0 } ;
float * const u__uy_2[16] = { uy_2_0 } ;
float * const u__uz_3[16] = { uz_3_0 } ;
*/
int _idx0;
int _idx1;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int chunk_idx_x;
int chunk_idx_x_max;
int chunk_idx_y;
int chunk_idx_y_max;
int chunk_idx_z;
int chunk_idx_z_max;
int idx_1_2;
int size_1_1;
int size_1_2;
//int t;
int thd_idx_x;
int thd_idx_y;
int thd_idx_z;
int thdblks_idx_x;
int thdblks_idx_x_max;
int thdblks_idx_y;
int thdblks_idx_y_max;
int thdblks_idx_z;
int thdblks_idx_z_max;
int tmp;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
chunk_idx_x_max=(chunk_idx_x+c);
chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
chunk_idx_y_max=(chunk_idx_y+1);
chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
chunk_idx_z_max=(chunk_idx_z+1);
thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
thdblks_idx_x_max=(thdblks_idx_x+tbx);
thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
thdblks_idx_y_max=(thdblks_idx_y+tby);
thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
thdblks_idx_z_max=(thdblks_idx_z+tbz);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
/*
for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
thd_idx_z=chunk_idx_z;
thd_idx_y=chunk_idx_y;
for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
/*
u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
*/
/* _idx0 = (((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2) */
_idx0=(((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2);
/* _idx1 = ((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x) */
_idx1=(_idx0-2);
/* _idx2 = ((((thd_idx_z*x_max)*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+2)*x_max))+thd_idx_x) */
_idx2=(((_idx1-(((2*t)*thd_idx_z)*y_max))+((((2*t)*thd_idx_z)+2)*x_max))-((2*t)*thd_idx_y));
/* _idx3 = ((((thd_idx_z*x_max)*y_max)+((((2*t)*thd_idx_z)+thd_idx_y)*x_max))+thd_idx_x) */
_idx3=(_idx2-(2*x_max));
/* _idx4 = (((((thd_idx_z+2)*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx4=((_idx3+((2*x_max)*y_max))-(((2*t)*thd_idx_z)*x_max));
/* _idx5 = ((((thd_idx_z*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx5=(_idx4-((2*x_max)*y_max));
u_0_0[_idx5]=((alpha*(ux_1_0[_idx0]-ux_1_0[_idx1]))+((beta*(uy_2_0[_idx2]-uy_2_0[_idx3]))+(gamma*(uz_3_0[_idx4]-uz_3_0[_idx5]))));
}
}
}
}
__global__ void initialize(float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
float * const u__u_0[16] = { u_0_0 } ;
float * const u__ux_1[16] = { ux_1_0 } ;
float * const u__uy_2[16] = { uy_2_0 } ;
float * const u__uz_3[16] = { uz_3_0 } ;
int _idx0;
int _idx1;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int chunk_idx_x;
int chunk_idx_x_max;
int chunk_idx_y;
int chunk_idx_y_max;
int chunk_idx_z;
int chunk_idx_z_max;
int idx_1_2;
int size_1_1;
int size_1_2;
//int t;
int thd_idx_x;
int thd_idx_y;
int thd_idx_z;
int thdblks_idx_x;
int thdblks_idx_x_max;
int thdblks_idx_y;
int thdblks_idx_y_max;
int thdblks_idx_z;
int thdblks_idx_z_max;
int tmp;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
chunk_idx_x_max=(chunk_idx_x+c);
chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
chunk_idx_y_max=(chunk_idx_y+1);
chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
chunk_idx_z_max=(chunk_idx_z+1);
thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
thdblks_idx_x_max=(thdblks_idx_x+tbx);
thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
thdblks_idx_y_max=(thdblks_idx_y+tby);
thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
thdblks_idx_z_max=(thdblks_idx_z+tbz);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
/*
for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
thd_idx_z=chunk_idx_z;
thd_idx_y=chunk_idx_y;
for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
/*
u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x) */
_idx0=((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x);
u__ux_1[(t-1)][_idx0]=0.2;
/* _idx1 = ((((thd_idx_z*x_max)*y_max)+((((2*t)*thd_idx_z)+thd_idx_y)*x_max))+thd_idx_x) */
_idx1=(((_idx0-(((2*t)*thd_idx_z)*y_max))+(((2*t)*thd_idx_z)*x_max))-((2*t)*thd_idx_y));
u__uy_2[(t-1)][_idx1]=0.30000000000000004;
/* _idx2 = ((((thd_idx_z*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx2=(_idx1-(((2*t)*thd_idx_z)*x_max));
u__uz_3[(t-1)][_idx2]=0.4;
/* _idx3 = (((((thd_idx_z+2)*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx3=(_idx2+((2*x_max)*y_max));
u__uz_3[(t-1)][_idx3]=0.4;
/* _idx4 = ((((thd_idx_z*x_max)*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+2)*x_max))+thd_idx_x) */
_idx4=(_idx1+(2*x_max));
u__uy_2[(t-1)][_idx4]=0.30000000000000004;
/* _idx5 = (((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2) */
_idx5=(_idx0+2);
u__ux_1[(t-1)][_idx5]=0.2;
u__u_0[(t-1)][_idx2]=0.1;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10divergencePPfS_S_S_S_fffiiiiiii
.globl _Z10divergencePPfS_S_S_S_fffiiiiiii
.p2align 8
.type _Z10divergencePPfS_S_S_S_fffiiiiiii,@function
_Z10divergencePPfS_S_S_S_fffiiiiiii:
s_load_b32 s2, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x2
s_load_b64 s[12:13], s[0:1], 0x5c
s_load_b64 s[20:21], s[0:1], 0x38
s_load_b128 s[16:19], s[0:1], 0x28
v_bfe_u32 v2, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s13, 0xffff
s_and_b32 s6, s12, 0xffff
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s5, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s4, v1
s_mul_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s21, s4
s_mul_i32 s5, s4, s3
s_add_i32 s7, s4, 1
s_sub_i32 s5, s21, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s8, s5, s3
s_cmp_ge_u32 s5, s3
s_cselect_b32 s4, s7, s4
s_cselect_b32 s5, s8, s5
s_add_i32 s7, s4, 1
s_cmp_ge_u32 s5, s3
s_cselect_b32 s13, s7, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s13
s_sub_i32 s5, 0, s13
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s4, v1
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
s_mul_i32 s5, s5, s4
v_mad_u64_u32 v[3:4], null, s14, s6, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v8, 1, v0
s_mul_hi_u32 s5, s4, s5
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s15, s4
s_mul_i32 s5, s4, s13
s_add_i32 s7, s4, 1
s_sub_i32 s5, s15, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s8, s5, s13
s_cmp_ge_u32 s5, s13
s_cselect_b32 s14, s7, s4
s_cselect_b32 s4, s8, s5
s_add_i32 s21, s14, 1
s_cmp_ge_u32 s4, s13
s_load_b256 s[4:11], s[0:1], 0x8
s_cselect_b32 s0, s21, s14
s_lshr_b32 s1, s12, 16
v_mad_u64_u32 v[4:5], null, s0, s3, v[2:3]
s_add_i32 s12, s20, 2
v_mul_lo_u32 v2, v3, s2
s_mul_i32 s0, s0, s13
s_add_i32 s3, s19, 2
s_sub_i32 s0, s15, s0
s_mul_i32 s3, s3, s20
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v1, 2, v4
v_mul_lo_u32 v3, v4, s12
v_mul_lo_u32 v5, s20, v4
s_mul_i32 s0, s0, s1
v_mul_lo_u32 v4, s3, v4
v_mul_lo_u32 v1, s20, v1
v_add_nc_u32_e32 v6, s0, v0
s_lshl_b32 s1, s0, 1
v_add3_u32 v7, v0, v3, s0
v_add3_u32 v3, v0, v5, s0
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v9, v6, s19
v_add3_u32 v10, v4, s1, v2
v_add3_u32 v0, v0, v1, s0
v_add_nc_u32_e32 v1, 2, v7
v_mul_lo_u32 v3, s19, v3
v_mul_lo_u32 v4, s19, v7
v_add_nc_u32_e32 v7, s2, v2
v_mul_lo_u32 v5, s19, v0
v_mul_lo_u32 v6, s19, v1
v_add3_u32 v0, v10, v9, v8
s_mov_b32 s1, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v6, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v12, v5, v2
v_add_nc_u32_e32 v14, v3, v2
v_add_nc_u32_e32 v10, v4, v2
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[16:17], 2, v[0:1]
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v15, 31, v14
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_nc_u32_e32 v2, 1, v2
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v16, vcc_lo, s6, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo
v_lshlrev_b64 v[14:15], 2, v[14:15]
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v12, vcc_lo, s10, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
v_add_co_u32 v18, vcc_lo, s10, v14
v_add_co_ci_u32_e32 v19, vcc_lo, s11, v15, vcc_lo
v_add_co_u32 v10, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
s_clause 0x1
global_load_b32 v1, v[12:13], off
global_load_b32 v12, v[18:19], off
s_clause 0x1
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[10:11], off
s_clause 0x1
global_load_b32 v10, v[16:17], off offset:8
global_load_b32 v11, v[16:17], off
v_cmp_ge_i32_e32 vcc_lo, v2, v7
v_add_nc_u32_e32 v0, 1, v0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_dual_sub_f32 v1, v1, v12 :: v_dual_sub_f32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, s18, v1
v_sub_f32_e32 v8, v8, v9
v_fmac_f32_e32 v1, s17, v8
v_add_co_u32 v8, s0, s4, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v9, s0, s5, v15, s0
v_fmac_f32_e32 v1, s16, v10
global_store_b32 v[8:9], v1, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10divergencePPfS_S_S_S_fffiiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10divergencePPfS_S_S_S_fffiiiiiii, .Lfunc_end0-_Z10divergencePPfS_S_S_S_fffiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10initializePfS_S_S_fffiiiiiii
.globl _Z10initializePfS_S_S_fffiiiiiii
.p2align 8
.type _Z10initializePfS_S_S_fffiiiiiii,@function
_Z10initializePfS_S_S_fffiiiiiii:
s_load_b32 s8, s[0:1], 0x44
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB1_3
s_clause 0x2
s_load_b64 s[10:11], s[0:1], 0x54
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[12:13], s[0:1], 0x2c
v_bfe_u32 v3, v0, 20, 10
v_mov_b32_e32 v11, 0x3dcccccd
v_mov_b32_e32 v10, 0x3ecccccd
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s11, 0xffff
s_and_b32 s11, s10, 0xffff
v_cvt_f32_u32_e32 v1, s9
s_sub_i32 s4, 0, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s3, v1
s_mul_i32 s4, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s3, s4
s_add_i32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s2, s3
s_mul_i32 s4, s3, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s2, s2, s4
s_add_i32 s4, s3, 1
s_sub_i32 s5, s2, s9
s_cmp_ge_u32 s2, s9
s_cselect_b32 s3, s4, s3
s_cselect_b32 s2, s5, s2
s_add_i32 s4, s3, 1
s_cmp_ge_u32 s2, s9
s_cselect_b32 s16, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s16
s_sub_i32 s2, 0, s16
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s17, v1
v_and_b32_e32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s2, s2, s17
v_mad_u64_u32 v[4:5], null, s14, s11, v[1:2]
s_mul_hi_u32 s18, s17, s2
v_bfe_u32 v5, v0, 10, 10
s_add_i32 s17, s17, s18
s_load_b256 s[0:7], s[0:1], 0x0
s_mul_hi_u32 s17, s15, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s18, s17, s16
s_add_i32 s14, s17, 1
s_sub_i32 s11, s15, s18
v_mul_lo_u32 v2, v4, s8
s_sub_i32 s18, s11, s16
s_cmp_ge_u32 s11, s16
v_lshlrev_b32_e32 v8, 1, v5
s_cselect_b32 s14, s14, s17
s_cselect_b32 s11, s18, s11
s_add_i32 s17, s14, 1
s_cmp_ge_u32 s11, s16
s_cselect_b32 s11, s17, s14
s_add_i32 s14, s13, 2
v_mad_u64_u32 v[0:1], null, s11, s9, v[3:4]
s_mul_i32 s11, s11, s16
s_lshr_b32 s9, s10, 16
s_add_i32 s10, s12, 2
s_sub_i32 s11, s15, s11
s_mul_i32 s10, s10, s13
s_mul_i32 s11, s11, s9
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, 2, v0
v_mul_lo_u32 v4, v0, s14
v_add_nc_u32_e32 v6, s11, v5
v_mul_lo_u32 v7, s13, v0
v_mul_lo_u32 v0, s10, v0
v_add_nc_u32_e32 v3, s8, v2
s_lshl_b32 s8, s11, 1
v_mul_lo_u32 v6, v6, s12
v_add3_u32 v4, v5, v4, s11
v_add3_u32 v7, v5, v7, s11
v_add3_u32 v0, v0, s8, v2
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v9, 2, v4
v_mul_lo_u32 v4, s12, v4
v_add3_u32 v0, v0, v6, v8
v_mov_b32_e32 v8, 0x3e4ccccd
v_mul_lo_u32 v1, s13, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add3_u32 v1, v5, v1, s11
v_mul_lo_u32 v5, s12, v7
v_mul_lo_u32 v7, s12, v9
v_mov_b32_e32 v9, 0x3e99999a
v_mul_lo_u32 v6, s12, v1
.LBB1_2:
v_add_nc_u32_e32 v12, v4, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v14, v5, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v16, v6, v2
v_add_nc_u32_e32 v18, v7, v2
v_add_nc_u32_e32 v2, 1, v2
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[20:21], 2, v[0:1]
v_ashrrev_i32_e32 v15, 31, v14
v_ashrrev_i32_e32 v17, 31, v16
v_cmp_ge_i32_e32 vcc_lo, v2, v3
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_ashrrev_i32_e32 v19, 31, v18
v_lshlrev_b64 v[14:15], 2, v[14:15]
v_lshlrev_b64 v[16:17], 2, v[16:17]
s_or_b32 s8, vcc_lo, s8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v20, vcc_lo, s2, v20
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
v_add_co_u32 v12, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
v_lshlrev_b64 v[18:19], 2, v[18:19]
v_add_co_u32 v22, vcc_lo, s6, v14
v_add_co_ci_u32_e32 v23, vcc_lo, s7, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s6, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s7, v17, vcc_lo
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v18, vcc_lo, s4, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s5, v19, vcc_lo
v_add_co_u32 v14, vcc_lo, s0, v14
global_store_b32 v[20:21], v8, off
v_add_co_ci_u32_e32 v15, vcc_lo, s1, v15, vcc_lo
global_store_b32 v[12:13], v9, off
s_clause 0x1
global_store_b32 v[22:23], v10, off
global_store_b32 v[16:17], v10, off
global_store_b32 v[18:19], v9, off
global_store_b32 v[20:21], v8, off offset:8
global_store_b32 v[14:15], v11, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializePfS_S_S_fffiiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10initializePfS_S_S_fffiiiiiii, .Lfunc_end1-_Z10initializePfS_S_S_fffiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 68
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10divergencePPfS_S_S_S_fffiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z10divergencePPfS_S_S_S_fffiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 68
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializePfS_S_S_fffiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z10initializePfS_S_S_fffiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define t_max 1
#define t 1
/*
(u[0][0][0][0][0]=((alpha*(ux[1][0][0][0][1]-ux[-1][0][0][0][1]))+((beta*(uy[0][1][0][0][2]-uy[0][-1][0][0][2]))+(gamma*(uz[0][0][1][0][3]-uz[0][0][-1][0][3])))))
*/
__global__ void divergence(float * * u_0_0_out, float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
/*
float * const u__u_0[16] = { u_0_0 } ;
float * const u__ux_1[16] = { ux_1_0 } ;
float * const u__uy_2[16] = { uy_2_0 } ;
float * const u__uz_3[16] = { uz_3_0 } ;
*/
int _idx0;
int _idx1;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int chunk_idx_x;
int chunk_idx_x_max;
int chunk_idx_y;
int chunk_idx_y_max;
int chunk_idx_z;
int chunk_idx_z_max;
int idx_1_2;
int size_1_1;
int size_1_2;
//int t;
int thd_idx_x;
int thd_idx_y;
int thd_idx_z;
int thdblks_idx_x;
int thdblks_idx_x_max;
int thdblks_idx_y;
int thdblks_idx_y_max;
int thdblks_idx_z;
int thdblks_idx_z_max;
int tmp;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
chunk_idx_x_max=(chunk_idx_x+c);
chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
chunk_idx_y_max=(chunk_idx_y+1);
chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
chunk_idx_z_max=(chunk_idx_z+1);
thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
thdblks_idx_x_max=(thdblks_idx_x+tbx);
thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
thdblks_idx_y_max=(thdblks_idx_y+tby);
thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
thdblks_idx_z_max=(thdblks_idx_z+tbz);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
/*
for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
thd_idx_z=chunk_idx_z;
thd_idx_y=chunk_idx_y;
for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
/*
u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
*/
/* _idx0 = (((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2) */
_idx0=(((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2);
/* _idx1 = ((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x) */
_idx1=(_idx0-2);
/* _idx2 = ((((thd_idx_z*x_max)*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+2)*x_max))+thd_idx_x) */
_idx2=(((_idx1-(((2*t)*thd_idx_z)*y_max))+((((2*t)*thd_idx_z)+2)*x_max))-((2*t)*thd_idx_y));
/* _idx3 = ((((thd_idx_z*x_max)*y_max)+((((2*t)*thd_idx_z)+thd_idx_y)*x_max))+thd_idx_x) */
_idx3=(_idx2-(2*x_max));
/* _idx4 = (((((thd_idx_z+2)*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx4=((_idx3+((2*x_max)*y_max))-(((2*t)*thd_idx_z)*x_max));
/* _idx5 = ((((thd_idx_z*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx5=(_idx4-((2*x_max)*y_max));
u_0_0[_idx5]=((alpha*(ux_1_0[_idx0]-ux_1_0[_idx1]))+((beta*(uy_2_0[_idx2]-uy_2_0[_idx3]))+(gamma*(uz_3_0[_idx4]-uz_3_0[_idx5]))));
}
}
}
}
__global__ void initialize(float * u_0_0, float * ux_1_0, float * uy_2_0, float * uz_3_0, float alpha, float beta, float gamma, int x_max, int y_max, int z_max, int tbx, int tby, int tbz, int c)
{
float * const u__u_0[16] = { u_0_0 } ;
float * const u__ux_1[16] = { ux_1_0 } ;
float * const u__uy_2[16] = { uy_2_0 } ;
float * const u__uz_3[16] = { uz_3_0 } ;
int _idx0;
int _idx1;
int _idx2;
int _idx3;
int _idx4;
int _idx5;
int chunk_idx_x;
int chunk_idx_x_max;
int chunk_idx_y;
int chunk_idx_y_max;
int chunk_idx_z;
int chunk_idx_z_max;
int idx_1_2;
int size_1_1;
int size_1_2;
//int t;
int thd_idx_x;
int thd_idx_y;
int thd_idx_z;
int thdblks_idx_x;
int thdblks_idx_x_max;
int thdblks_idx_y;
int thdblks_idx_y_max;
int thdblks_idx_z;
int thdblks_idx_z_max;
int tmp;
/*
Initializations
*/
size_1_1=(y_max/blockDim.y);
size_1_2=(z_max/blockDim.z);
idx_1_2=(blockIdx.y/size_1_2);
tmp=(blockIdx.y-(idx_1_2*size_1_2));
chunk_idx_x=(c*(threadIdx.x+(blockDim.x*blockIdx.x)));
chunk_idx_x_max=(chunk_idx_x+c);
chunk_idx_y=(threadIdx.y+(tmp*blockDim.y));
chunk_idx_y_max=(chunk_idx_y+1);
chunk_idx_z=(threadIdx.z+(idx_1_2*blockDim.z));
chunk_idx_z_max=(chunk_idx_z+1);
thdblks_idx_x=(tbx*(threadIdx.x+(blockDim.x*blockIdx.x)));
thdblks_idx_x_max=(thdblks_idx_x+tbx);
thdblks_idx_y=(tby*(threadIdx.y+(tmp*blockDim.y)));
thdblks_idx_y_max=(thdblks_idx_y+tby);
thdblks_idx_z=(tbz*(threadIdx.z+(idx_1_2*blockDim.z)));
thdblks_idx_z_max=(thdblks_idx_z+tbz);
/*
Implementation
*/
/*
for t = 1..t_max by 1 parallel 1 <level 0> schedule { ... }
*/
//for (t=1; t<=t_max; t+=1)
{
/* Index bounds calculations for iterators in thdblks[t=t, s=(tbx, tby, tbz)][0] */
/* Index bounds calculations for iterators in chunk[t=t, s=(c, 1, 1)][0] */
/*
for POINT thd[t=t, s=(1, 1, 1)][0] of size [1, 1, 1] in chunk[t=t, s=(:, :, :)][0] parallel 1 <level 2> schedule default { ... }
*/
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
thd_idx_z=chunk_idx_z;
thd_idx_y=chunk_idx_y;
for (thd_idx_x=chunk_idx_x; thd_idx_x<(chunk_idx_x_max-0); thd_idx_x+=1)
{
/* Index bounds calculations for iterators in thd[t=t, s=(1, 1, 1)][0] */
/*
u[t=(t+1), s=thd[t=?, s=?][0]][0]=stencil(u[t=t, s=thd[t=?, s=?][0]][0])
*/
/* _idx0 = ((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x) */
_idx0=((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x);
u__ux_1[(t-1)][_idx0]=0.2;
/* _idx1 = ((((thd_idx_z*x_max)*y_max)+((((2*t)*thd_idx_z)+thd_idx_y)*x_max))+thd_idx_x) */
_idx1=(((_idx0-(((2*t)*thd_idx_z)*y_max))+(((2*t)*thd_idx_z)*x_max))-((2*t)*thd_idx_y));
u__uy_2[(t-1)][_idx1]=0.30000000000000004;
/* _idx2 = ((((thd_idx_z*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx2=(_idx1-(((2*t)*thd_idx_z)*x_max));
u__uz_3[(t-1)][_idx2]=0.4;
/* _idx3 = (((((thd_idx_z+2)*x_max)*y_max)+(thd_idx_y*x_max))+thd_idx_x) */
_idx3=(_idx2+((2*x_max)*y_max));
u__uz_3[(t-1)][_idx3]=0.4;
/* _idx4 = ((((thd_idx_z*x_max)*y_max)+(((((2*t)*thd_idx_z)+thd_idx_y)+2)*x_max))+thd_idx_x) */
_idx4=(_idx1+(2*x_max));
u__uy_2[(t-1)][_idx4]=0.30000000000000004;
/* _idx5 = (((((((thd_idx_z*x_max)+((2*t)*thd_idx_z))*y_max)+(thd_idx_y*x_max))+((2*t)*thd_idx_y))+thd_idx_x)+2) */
_idx5=(_idx0+2);
u__ux_1[(t-1)][_idx5]=0.2;
u__u_0[(t-1)][_idx2]=0.1;
}
}
}
} | .text
.file "kernel.hip"
.globl _Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii # -- Begin function _Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii
.p2align 4, 0x90
.type _Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii,@function
_Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii: # @_Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 272(%rsp), %rax
movq %rax, 216(%rsp)
leaq 280(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10divergencePPfS_S_S_S_fffiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii, .Lfunc_end0-_Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__initializePfS_S_S_fffiiiiiii # -- Begin function _Z25__device_stub__initializePfS_S_S_fffiiiiiii
.p2align 4, 0x90
.type _Z25__device_stub__initializePfS_S_S_fffiiiiiii,@function
_Z25__device_stub__initializePfS_S_S_fffiiiiiii: # @_Z25__device_stub__initializePfS_S_S_fffiiiiiii
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 272(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10initializePfS_S_S_fffiiiiiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end1:
.size _Z25__device_stub__initializePfS_S_S_fffiiiiiii, .Lfunc_end1-_Z25__device_stub__initializePfS_S_S_fffiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10divergencePPfS_S_S_S_fffiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePfS_S_S_fffiiiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10divergencePPfS_S_S_S_fffiiiiiii,@object # @_Z10divergencePPfS_S_S_S_fffiiiiiii
.section .rodata,"a",@progbits
.globl _Z10divergencePPfS_S_S_S_fffiiiiiii
.p2align 3, 0x0
_Z10divergencePPfS_S_S_S_fffiiiiiii:
.quad _Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii
.size _Z10divergencePPfS_S_S_S_fffiiiiiii, 8
.type _Z10initializePfS_S_S_fffiiiiiii,@object # @_Z10initializePfS_S_S_fffiiiiiii
.globl _Z10initializePfS_S_S_fffiiiiiii
.p2align 3, 0x0
_Z10initializePfS_S_S_fffiiiiiii:
.quad _Z25__device_stub__initializePfS_S_S_fffiiiiiii
.size _Z10initializePfS_S_S_fffiiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10divergencePPfS_S_S_S_fffiiiiiii"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10initializePfS_S_S_fffiiiiiii"
.size .L__unnamed_2, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii
.addrsig_sym _Z25__device_stub__initializePfS_S_S_fffiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10divergencePPfS_S_S_S_fffiiiiiii
.addrsig_sym _Z10initializePfS_S_S_fffiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009d1cc_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z10divergencePPfS_S_S_S_fffiiiiiiiPPfS_S_S_S_fffiiiiiii
.type _Z49__device_stub__Z10divergencePPfS_S_S_S_fffiiiiiiiPPfS_S_S_S_fffiiiiiii, @function
_Z49__device_stub__Z10divergencePPfS_S_S_S_fffiiiiiiiPPfS_S_S_S_fffiiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
leaq 288(%rsp), %rax
movq %rax, 216(%rsp)
leaq 296(%rsp), %rax
movq %rax, 224(%rsp)
leaq 304(%rsp), %rax
movq %rax, 232(%rsp)
leaq 312(%rsp), %rax
movq %rax, 240(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 280
pushq 72(%rsp)
.cfi_def_cfa_offset 288
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z10divergencePPfS_S_S_S_fffiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z10divergencePPfS_S_S_S_fffiiiiiiiPPfS_S_S_S_fffiiiiiii, .-_Z49__device_stub__Z10divergencePPfS_S_S_S_fffiiiiiiiPPfS_S_S_S_fffiiiiiii
.globl _Z10divergencePPfS_S_S_S_fffiiiiiii
.type _Z10divergencePPfS_S_S_S_fffiiiiiii, @function
_Z10divergencePPfS_S_S_S_fffiiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z49__device_stub__Z10divergencePPfS_S_S_S_fffiiiiiiiPPfS_S_S_S_fffiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10divergencePPfS_S_S_S_fffiiiiiii, .-_Z10divergencePPfS_S_S_S_fffiiiiiii
.globl _Z46__device_stub__Z10initializePfS_S_S_fffiiiiiiiPfS_S_S_fffiiiiiii
.type _Z46__device_stub__Z10initializePfS_S_S_fffiiiiiiiPfS_S_S_fffiiiiiii, @function
_Z46__device_stub__Z10initializePfS_S_S_fffiiiiiiiPfS_S_S_fffiiiiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 280(%rsp), %rax
movq %rax, 208(%rsp)
leaq 288(%rsp), %rax
movq %rax, 216(%rsp)
leaq 296(%rsp), %rax
movq %rax, 224(%rsp)
leaq 304(%rsp), %rax
movq %rax, 232(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 280
pushq 72(%rsp)
.cfi_def_cfa_offset 288
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z10initializePfS_S_S_fffiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z46__device_stub__Z10initializePfS_S_S_fffiiiiiiiPfS_S_S_fffiiiiiii, .-_Z46__device_stub__Z10initializePfS_S_S_fffiiiiiiiPfS_S_S_fffiiiiiii
.globl _Z10initializePfS_S_S_fffiiiiiii
.type _Z10initializePfS_S_S_fffiiiiiii, @function
_Z10initializePfS_S_S_fffiiiiiii:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z46__device_stub__Z10initializePfS_S_S_fffiiiiiiiPfS_S_S_fffiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z10initializePfS_S_S_fffiiiiiii, .-_Z10initializePfS_S_S_fffiiiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10initializePfS_S_S_fffiiiiiii"
.align 8
.LC1:
.string "_Z10divergencePPfS_S_S_S_fffiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePfS_S_S_fffiiiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10divergencePPfS_S_S_S_fffiiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii # -- Begin function _Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii
.p2align 4, 0x90
.type _Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii,@function
_Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii: # @_Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 272(%rsp), %rax
movq %rax, 216(%rsp)
leaq 280(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10divergencePPfS_S_S_S_fffiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii, .Lfunc_end0-_Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__initializePfS_S_S_fffiiiiiii # -- Begin function _Z25__device_stub__initializePfS_S_S_fffiiiiiii
.p2align 4, 0x90
.type _Z25__device_stub__initializePfS_S_S_fffiiiiiii,@function
_Z25__device_stub__initializePfS_S_S_fffiiiiiii: # @_Z25__device_stub__initializePfS_S_S_fffiiiiiii
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 272(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10initializePfS_S_S_fffiiiiiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end1:
.size _Z25__device_stub__initializePfS_S_S_fffiiiiiii, .Lfunc_end1-_Z25__device_stub__initializePfS_S_S_fffiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10divergencePPfS_S_S_S_fffiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePfS_S_S_fffiiiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10divergencePPfS_S_S_S_fffiiiiiii,@object # @_Z10divergencePPfS_S_S_S_fffiiiiiii
.section .rodata,"a",@progbits
.globl _Z10divergencePPfS_S_S_S_fffiiiiiii
.p2align 3, 0x0
_Z10divergencePPfS_S_S_S_fffiiiiiii:
.quad _Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii
.size _Z10divergencePPfS_S_S_S_fffiiiiiii, 8
.type _Z10initializePfS_S_S_fffiiiiiii,@object # @_Z10initializePfS_S_S_fffiiiiiii
.globl _Z10initializePfS_S_S_fffiiiiiii
.p2align 3, 0x0
_Z10initializePfS_S_S_fffiiiiiii:
.quad _Z25__device_stub__initializePfS_S_S_fffiiiiiii
.size _Z10initializePfS_S_S_fffiiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10divergencePPfS_S_S_S_fffiiiiiii"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10initializePfS_S_S_fffiiiiiii"
.size .L__unnamed_2, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__divergencePPfS_S_S_S_fffiiiiiii
.addrsig_sym _Z25__device_stub__initializePfS_S_S_fffiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10divergencePPfS_S_S_S_fffiiiiiii
.addrsig_sym _Z10initializePfS_S_S_fffiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
for (int i=0; i<N; i++) {
C[i] = A[i] + B[i];
}
} | code for sm_80
Function : _Z6VecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xb80 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fd20000000f00 */
/*0130*/ @!P0 BRA 0x990 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x670 ; /* 0x0000050000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*01c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0200*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0240*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0270*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0280*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*02b0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x0001e8000c10190c */
/*02c0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*02e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*02f0*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0003e8000c10190c */
/*0300*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0320*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0330*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x0005e8000c10190c */
/*0340*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0350*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0360*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0370*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0007e8000c10190c */
/*0380*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0x20] ; /* 0x0000200c060a7981 */
/* 0x000f24000c1e1900 */
/*03a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*03b0*/ STG.E [R4.64+0x20], R9 ; /* 0x0000200904007986 */
/* 0x0001e8000c10190c */
/*03c0*/ LDG.E R10, [R2.64+0x24] ; /* 0x0000240c020a7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R11, [R6.64+0x24] ; /* 0x0000240c060b7981 */
/* 0x002f24000c1e1900 */
/*03e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*03f0*/ STG.E [R4.64+0x24], R11 ; /* 0x0000240b04007986 */
/* 0x0003e8000c10190c */
/*0400*/ LDG.E R10, [R2.64+0x28] ; /* 0x0000280c020a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R13, [R6.64+0x28] ; /* 0x0000280c060d7981 */
/* 0x004f24000c1e1900 */
/*0420*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0430*/ STG.E [R4.64+0x28], R13 ; /* 0x0000280d04007986 */
/* 0x0005e8000c10190c */
/*0440*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R15, [R6.64+0x2c] ; /* 0x00002c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0460*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0470*/ STG.E [R4.64+0x2c], R15 ; /* 0x00002c0f04007986 */
/* 0x0007e8000c10190c */
/*0480*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300c02097981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R10, [R6.64+0x30] ; /* 0x0000300c060a7981 */
/* 0x000f24000c1e1900 */
/*04a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*04b0*/ STG.E [R4.64+0x30], R9 ; /* 0x0000300904007986 */
/* 0x000fe8000c10190c */
/*04c0*/ LDG.E R10, [R2.64+0x34] ; /* 0x0000340c020a7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R6.64+0x34] ; /* 0x0000340c060b7981 */
/* 0x002f24000c1e1900 */
/*04e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*04f0*/ STG.E [R4.64+0x34], R11 ; /* 0x0000340b04007986 */
/* 0x0001e8000c10190c */
/*0500*/ LDG.E R10, [R2.64+0x38] ; /* 0x0000380c020a7981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R6.64+0x38] ; /* 0x0000380c060d7981 */
/* 0x004f22000c1e1900 */
/*0520*/ IADD3 R12, P1, R2, 0x40, RZ ; /* 0x00000040020c7810 */
/* 0x000fe40007f3e0ff */
/*0530*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0540*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0550*/ STG.E [R4.64+0x38], R13 ; /* 0x0000380d04007986 */
/* 0x000fe8000c10190c */
/*0560*/ LDG.E R10, [R2.64+0x3c] ; /* 0x00003c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0570*/ LDG.E R15, [R6.64+0x3c] ; /* 0x00003c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0580*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe20000ffe4ff */
/*0590*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*05a0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc40003f24270 */
/*05b0*/ IADD3 R9, P3, R4, 0x40, RZ ; /* 0x0000004004097810 */
/* 0x000fe20007f7e0ff */
/*05c0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*05d0*/ IADD3 R14, P2, R6, 0x40, RZ ; /* 0x00000040060e7810 */
/* 0x000fe40007f5e0ff */
/*05e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*05f0*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x008fe400010e0607 */
/*0600*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0610*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0620*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0630*/ STG.E [R4.64+0x3c], R15 ; /* 0x00003c0f04007986 */
/* 0x0001e4000c10190c */
/*0640*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0660*/ @P1 BRA 0x180 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x970 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*06c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*06d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0700*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0710*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0730*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0740*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0750*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0760*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0770*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0780*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0790*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*07a0*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*07b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*07c0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x000fe8000c10190c */
/*07d0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*07f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*0800*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0001e8000c10190c */
/*0810*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0830*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0840*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x000fe8000c10190c */
/*0850*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0860*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0870*/ IADD3 R11, P2, R2, 0x20, RZ ; /* 0x00000020020b7810 */
/* 0x001fe20007f5e0ff */
/*0880*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0890*/ IADD3 R9, P3, R4, 0x20, RZ ; /* 0x0000002004097810 */
/* 0x000fc40007f7e0ff */
/*08a0*/ IADD3 R14, P1, R6, 0x20, RZ ; /* 0x00000020060e7810 */
/* 0x000fe20007f3e0ff */
/*08b0*/ IMAD.X R12, RZ, RZ, R3, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200010e0603 */
/*08c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000b */
/*08e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x008fe200078e000e */
/*0900*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0910*/ MOV R3, R12 ; /* 0x0000000c00037202 */
/* 0x000fe20000000f00 */
/*0920*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0930*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0940*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0001e4000c10190c */
/*0950*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000a */
/*0970*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*09c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c10190c */
/*09d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0a00*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0a10*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0a20*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R12, P0, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f1e0ff */
/*0a40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0a60*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c10190c */
/*0a70*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0a80*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x0006a2000c1e1900 */
/*0a90*/ IADD3.X R11, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe200007fe4ff */
/*0aa0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0ab0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc40003f05270 */
/*0ac0*/ IADD3 R9, P2, R4, 0x10, RZ ; /* 0x0000001004097810 */
/* 0x000fe20007f5e0ff */
/*0ad0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*0ae0*/ IADD3 R14, P1, R6, 0x10, RZ ; /* 0x00000010060e7810 */
/* 0x000fe40007f3e0ff */
/*0af0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*0b00*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x008fe400008e0607 */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0b20*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0b30*/ IADD3.X R10, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc800017fe4ff */
/*0b40*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0001e4000c10190c */
/*0b50*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0b60*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0b70*/ @P0 BRA 0x990 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*0b80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0b90*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ba0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0bb0*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0bc0*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0bd0*/ ULDC.64 UR10, c[0x0][0x160] ; /* 0x00005800000a7ab9 */
/* 0x000fe40000000a00 */
/*0be0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0bf0*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fc4000f8e0208 */
/*0c00*/ UIMAD.WIDE UR4, UR4, UR5, UR10 ; /* 0x00000005040472a5 */
/* 0x000fca000f8e020a */
/*0c10*/ MOV R2, UR8 ; /* 0x0000000800027c02 */
/* 0x000fe20008000f00 */
/*0c20*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe2000f8e00ff */
/*0c30*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe20008000f00 */
/*0c40*/ IMAD.U32 R3, RZ, RZ, UR9 ; /* 0x00000009ff037e24 */
/* 0x000fc8000f8e00ff */
/*0c50*/ LDG.E R5, [R4.64] ; /* 0x0000000c04057981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R2, [R2.64] ; /* 0x0000000c02027981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0c90*/ UIADD3 UR8, UP1, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff3e03f */
/*0ca0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x001fe20008000f00 */
/*0cb0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*0cc0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*0cd0*/ UIADD3 UR4, UP2, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000ff5e03f */
/*0ce0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0cf0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe40008ffe43f */
/*0d00*/ UIADD3.X UR5, URZ, UR5, URZ, UP2, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200097fe43f */
/*0d10*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0d20*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c10190c */
/*0d30*/ @P0 BRA 0xc10 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
for (int i=0; i<N; i++) {
C[i] = A[i] + B[i];
}
} | .file "tmpxft_001bc9a7_00000000-6_VecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.globl _Z6VecAddPfS_S_i
.type _Z6VecAddPfS_S_i, @function
_Z6VecAddPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6VecAddPfS_S_i, .-_Z6VecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6VecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
for (int i=0; i<N; i++) {
C[i] = A[i] + B[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
for (int i=0; i<N; i++) {
C[i] = A[i] + B[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
for (int i=0; i<N; i++) {
C[i] = A[i] + B[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_i
.globl _Z6VecAddPfS_S_i
.p2align 8
.type _Z6VecAddPfS_S_i,@function
_Z6VecAddPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_add_i32 s2, s2, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_i, .Lfunc_end0-_Z6VecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
for (int i=0; i<N; i++) {
C[i] = A[i] + B[i];
}
} | .text
.file "VecAdd.hip"
.globl _Z21__device_stub__VecAddPfS_S_i # -- Begin function _Z21__device_stub__VecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_i,@function
_Z21__device_stub__VecAddPfS_S_i: # @_Z21__device_stub__VecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_i,@object # @_Z6VecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_i
.p2align 3, 0x0
_Z6VecAddPfS_S_i:
.quad _Z21__device_stub__VecAddPfS_S_i
.size _Z6VecAddPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6VecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xb80 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fd20000000f00 */
/*0130*/ @!P0 BRA 0x990 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x670 ; /* 0x0000050000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*01c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0200*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0240*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0270*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0280*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*02b0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x0001e8000c10190c */
/*02c0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*02e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*02f0*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0003e8000c10190c */
/*0300*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0320*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0330*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x0005e8000c10190c */
/*0340*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0350*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0360*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0370*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0007e8000c10190c */
/*0380*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0x20] ; /* 0x0000200c060a7981 */
/* 0x000f24000c1e1900 */
/*03a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*03b0*/ STG.E [R4.64+0x20], R9 ; /* 0x0000200904007986 */
/* 0x0001e8000c10190c */
/*03c0*/ LDG.E R10, [R2.64+0x24] ; /* 0x0000240c020a7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R11, [R6.64+0x24] ; /* 0x0000240c060b7981 */
/* 0x002f24000c1e1900 */
/*03e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*03f0*/ STG.E [R4.64+0x24], R11 ; /* 0x0000240b04007986 */
/* 0x0003e8000c10190c */
/*0400*/ LDG.E R10, [R2.64+0x28] ; /* 0x0000280c020a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R13, [R6.64+0x28] ; /* 0x0000280c060d7981 */
/* 0x004f24000c1e1900 */
/*0420*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0430*/ STG.E [R4.64+0x28], R13 ; /* 0x0000280d04007986 */
/* 0x0005e8000c10190c */
/*0440*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R15, [R6.64+0x2c] ; /* 0x00002c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0460*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0470*/ STG.E [R4.64+0x2c], R15 ; /* 0x00002c0f04007986 */
/* 0x0007e8000c10190c */
/*0480*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300c02097981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R10, [R6.64+0x30] ; /* 0x0000300c060a7981 */
/* 0x000f24000c1e1900 */
/*04a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*04b0*/ STG.E [R4.64+0x30], R9 ; /* 0x0000300904007986 */
/* 0x000fe8000c10190c */
/*04c0*/ LDG.E R10, [R2.64+0x34] ; /* 0x0000340c020a7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R6.64+0x34] ; /* 0x0000340c060b7981 */
/* 0x002f24000c1e1900 */
/*04e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*04f0*/ STG.E [R4.64+0x34], R11 ; /* 0x0000340b04007986 */
/* 0x0001e8000c10190c */
/*0500*/ LDG.E R10, [R2.64+0x38] ; /* 0x0000380c020a7981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R6.64+0x38] ; /* 0x0000380c060d7981 */
/* 0x004f22000c1e1900 */
/*0520*/ IADD3 R12, P1, R2, 0x40, RZ ; /* 0x00000040020c7810 */
/* 0x000fe40007f3e0ff */
/*0530*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0540*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0550*/ STG.E [R4.64+0x38], R13 ; /* 0x0000380d04007986 */
/* 0x000fe8000c10190c */
/*0560*/ LDG.E R10, [R2.64+0x3c] ; /* 0x00003c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0570*/ LDG.E R15, [R6.64+0x3c] ; /* 0x00003c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0580*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe20000ffe4ff */
/*0590*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*05a0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc40003f24270 */
/*05b0*/ IADD3 R9, P3, R4, 0x40, RZ ; /* 0x0000004004097810 */
/* 0x000fe20007f7e0ff */
/*05c0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*05d0*/ IADD3 R14, P2, R6, 0x40, RZ ; /* 0x00000040060e7810 */
/* 0x000fe40007f5e0ff */
/*05e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*05f0*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x008fe400010e0607 */
/*0600*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0610*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0620*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0630*/ STG.E [R4.64+0x3c], R15 ; /* 0x00003c0f04007986 */
/* 0x0001e4000c10190c */
/*0640*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0660*/ @P1 BRA 0x180 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x970 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*06c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*06d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0700*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0710*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0730*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0740*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0750*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0760*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0770*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0780*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0790*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*07a0*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*07b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*07c0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x000fe8000c10190c */
/*07d0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*07f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*0800*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0001e8000c10190c */
/*0810*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0830*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0840*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x000fe8000c10190c */
/*0850*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0860*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0870*/ IADD3 R11, P2, R2, 0x20, RZ ; /* 0x00000020020b7810 */
/* 0x001fe20007f5e0ff */
/*0880*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0890*/ IADD3 R9, P3, R4, 0x20, RZ ; /* 0x0000002004097810 */
/* 0x000fc40007f7e0ff */
/*08a0*/ IADD3 R14, P1, R6, 0x20, RZ ; /* 0x00000020060e7810 */
/* 0x000fe20007f3e0ff */
/*08b0*/ IMAD.X R12, RZ, RZ, R3, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200010e0603 */
/*08c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000b */
/*08e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x008fe200078e000e */
/*0900*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0910*/ MOV R3, R12 ; /* 0x0000000c00037202 */
/* 0x000fe20000000f00 */
/*0920*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0930*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0940*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0001e4000c10190c */
/*0950*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000a */
/*0970*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*09c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c10190c */
/*09d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0a00*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0a10*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0a20*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R12, P0, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f1e0ff */
/*0a40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0a60*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c10190c */
/*0a70*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0a80*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x0006a2000c1e1900 */
/*0a90*/ IADD3.X R11, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe200007fe4ff */
/*0aa0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0ab0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc40003f05270 */
/*0ac0*/ IADD3 R9, P2, R4, 0x10, RZ ; /* 0x0000001004097810 */
/* 0x000fe20007f5e0ff */
/*0ad0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*0ae0*/ IADD3 R14, P1, R6, 0x10, RZ ; /* 0x00000010060e7810 */
/* 0x000fe40007f3e0ff */
/*0af0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*0b00*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x008fe400008e0607 */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0b20*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0b30*/ IADD3.X R10, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc800017fe4ff */
/*0b40*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0001e4000c10190c */
/*0b50*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0b60*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0b70*/ @P0 BRA 0x990 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*0b80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0b90*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ba0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0bb0*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0bc0*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0bd0*/ ULDC.64 UR10, c[0x0][0x160] ; /* 0x00005800000a7ab9 */
/* 0x000fe40000000a00 */
/*0be0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0bf0*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fc4000f8e0208 */
/*0c00*/ UIMAD.WIDE UR4, UR4, UR5, UR10 ; /* 0x00000005040472a5 */
/* 0x000fca000f8e020a */
/*0c10*/ MOV R2, UR8 ; /* 0x0000000800027c02 */
/* 0x000fe20008000f00 */
/*0c20*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe2000f8e00ff */
/*0c30*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe20008000f00 */
/*0c40*/ IMAD.U32 R3, RZ, RZ, UR9 ; /* 0x00000009ff037e24 */
/* 0x000fc8000f8e00ff */
/*0c50*/ LDG.E R5, [R4.64] ; /* 0x0000000c04057981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R2, [R2.64] ; /* 0x0000000c02027981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0c90*/ UIADD3 UR8, UP1, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff3e03f */
/*0ca0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x001fe20008000f00 */
/*0cb0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*0cc0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*0cd0*/ UIADD3 UR4, UP2, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000ff5e03f */
/*0ce0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0cf0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe40008ffe43f */
/*0d00*/ UIADD3.X UR5, URZ, UR5, URZ, UP2, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200097fe43f */
/*0d10*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0d20*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c10190c */
/*0d30*/ @P0 BRA 0xc10 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_i
.globl _Z6VecAddPfS_S_i
.p2align 8
.type _Z6VecAddPfS_S_i,@function
_Z6VecAddPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_add_i32 s2, s2, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_i, .Lfunc_end0-_Z6VecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bc9a7_00000000-6_VecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.globl _Z6VecAddPfS_S_i
.type _Z6VecAddPfS_S_i, @function
_Z6VecAddPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6VecAddPfS_S_i, .-_Z6VecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6VecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VecAdd.hip"
.globl _Z21__device_stub__VecAddPfS_S_i # -- Begin function _Z21__device_stub__VecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_i,@function
_Z21__device_stub__VecAddPfS_S_i: # @_Z21__device_stub__VecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_i,@object # @_Z6VecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_i
.p2align 3, 0x0
_Z6VecAddPfS_S_i:
.quad _Z21__device_stub__VecAddPfS_S_i
.size _Z6VecAddPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
This program will numerically compute the integral of
4/(1+x*x)
from 0 to 1. The value of this integral is pi -- which
is great since it gives us an easy way to check the answer.
The is the original sequential program. It uses the timer
from the OpenMP runtime library
History: Written by Tim Mattson, 11/99.
*/
#include <stdio.h>
#include "cuda.h"
/*#include <omp.h>*/
static long num_steps = 1000000000;
double step;
int main ()
{
int i;
double x, pi, sum = 0.0;
cudaEvent_t start_time, stop_time;
float elapsed_time;
step = 1.0/(double) num_steps;
cudaEventCreate( &start_time );
cudaEventCreate( &stop_time );
cudaEventRecord( start_time, 0 );
/* start_time = omp_get_wtime();*/
for (i=1;i<= num_steps; i++){
x = (i-0.5)*step;
sum = sum + 4.0/(1.0+x*x);
}
pi = step * sum;
cudaEventRecord( stop_time, 0 );
cudaEventSynchronize( stop_time );
cudaEventElapsedTime(&elapsed_time,start_time,stop_time);
/* run_time = omp_get_wtime() - start_time;*/
printf("\n pi with %ld steps is %lf in %lf millisecond\n ",num_steps,pi,elapsed_time);
cudaEventDestroy( start_time );
cudaEventDestroy( stop_time );
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
This program will numerically compute the integral of
4/(1+x*x)
from 0 to 1. The value of this integral is pi -- which
is great since it gives us an easy way to check the answer.
The is the original sequential program. It uses the timer
from the OpenMP runtime library
History: Written by Tim Mattson, 11/99.
*/
#include <stdio.h>
#include "cuda.h"
/*#include <omp.h>*/
static long num_steps = 1000000000;
double step;
int main ()
{
int i;
double x, pi, sum = 0.0;
cudaEvent_t start_time, stop_time;
float elapsed_time;
step = 1.0/(double) num_steps;
cudaEventCreate( &start_time );
cudaEventCreate( &stop_time );
cudaEventRecord( start_time, 0 );
/* start_time = omp_get_wtime();*/
for (i=1;i<= num_steps; i++){
x = (i-0.5)*step;
sum = sum + 4.0/(1.0+x*x);
}
pi = step * sum;
cudaEventRecord( stop_time, 0 );
cudaEventSynchronize( stop_time );
cudaEventElapsedTime(&elapsed_time,start_time,stop_time);
/* run_time = omp_get_wtime() - start_time;*/
printf("\n pi with %ld steps is %lf in %lf millisecond\n ",num_steps,pi,elapsed_time);
cudaEventDestroy( start_time );
cudaEventDestroy( stop_time );
} | .file "tmpxft_000dbe75_00000000-6_pi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "\n pi with %ld steps is %lf in %lf millisecond\n "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq .LC1(%rip), %rax
movq %rax, step(%rip)
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movsd step(%rip), %xmm3
pxor %xmm1, %xmm1
movl $1, %eax
movsd .LC2(%rip), %xmm6
movsd .LC3(%rip), %xmm5
movsd .LC4(%rip), %xmm4
.L4:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
subsd %xmm6, %xmm0
mulsd %xmm3, %xmm0
mulsd %xmm0, %xmm0
addsd %xmm5, %xmm0
movapd %xmm4, %xmm2
divsd %xmm0, %xmm2
addsd %xmm2, %xmm1
addl $1, %eax
cmpl $1000000001, %eax
jne .L4
mulsd %xmm1, %xmm3
movsd %xmm3, 8(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm1, %xmm1
cvtss2sd 20(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movl $1000000000, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl step
.bss
.align 8
.type step, @object
.size step, 8
step:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -400107883
.long 1041313291
.align 8
.LC2:
.long 0
.long 1071644672
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
This program will numerically compute the integral of
4/(1+x*x)
from 0 to 1. The value of this integral is pi -- which
is great since it gives us an easy way to check the answer.
The is the original sequential program. It uses the timer
from the OpenMP runtime library
History: Written by Tim Mattson, 11/99.
*/
#include <stdio.h>
#include "cuda.h"
/*#include <omp.h>*/
static long num_steps = 1000000000;
double step;
int main ()
{
int i;
double x, pi, sum = 0.0;
cudaEvent_t start_time, stop_time;
float elapsed_time;
step = 1.0/(double) num_steps;
cudaEventCreate( &start_time );
cudaEventCreate( &stop_time );
cudaEventRecord( start_time, 0 );
/* start_time = omp_get_wtime();*/
for (i=1;i<= num_steps; i++){
x = (i-0.5)*step;
sum = sum + 4.0/(1.0+x*x);
}
pi = step * sum;
cudaEventRecord( stop_time, 0 );
cudaEventSynchronize( stop_time );
cudaEventElapsedTime(&elapsed_time,start_time,stop_time);
/* run_time = omp_get_wtime() - start_time;*/
printf("\n pi with %ld steps is %lf in %lf millisecond\n ",num_steps,pi,elapsed_time);
cudaEventDestroy( start_time );
cudaEventDestroy( stop_time );
} | /*
This program will numerically compute the integral of
4/(1+x*x)
from 0 to 1. The value of this integral is pi -- which
is great since it gives us an easy way to check the answer.
The is the original sequential program. It uses the timer
from the OpenMP runtime library
History: Written by Tim Mattson, 11/99.
*/
#include <stdio.h>
#include "hip/hip_runtime.h"
/*#include <omp.h>*/
static long num_steps = 1000000000;
double step;
int main ()
{
int i;
double x, pi, sum = 0.0;
hipEvent_t start_time, stop_time;
float elapsed_time;
step = 1.0/(double) num_steps;
hipEventCreate( &start_time );
hipEventCreate( &stop_time );
hipEventRecord( start_time, 0 );
/* start_time = omp_get_wtime();*/
for (i=1;i<= num_steps; i++){
x = (i-0.5)*step;
sum = sum + 4.0/(1.0+x*x);
}
pi = step * sum;
hipEventRecord( stop_time, 0 );
hipEventSynchronize( stop_time );
hipEventElapsedTime(&elapsed_time,start_time,stop_time);
/* run_time = omp_get_wtime() - start_time;*/
printf("\n pi with %ld steps is %lf in %lf millisecond\n ",num_steps,pi,elapsed_time);
hipEventDestroy( start_time );
hipEventDestroy( stop_time );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
This program will numerically compute the integral of
4/(1+x*x)
from 0 to 1. The value of this integral is pi -- which
is great since it gives us an easy way to check the answer.
The is the original sequential program. It uses the timer
from the OpenMP runtime library
History: Written by Tim Mattson, 11/99.
*/
#include <stdio.h>
#include "hip/hip_runtime.h"
/*#include <omp.h>*/
static long num_steps = 1000000000;
double step;
int main ()
{
int i;
double x, pi, sum = 0.0;
hipEvent_t start_time, stop_time;
float elapsed_time;
step = 1.0/(double) num_steps;
hipEventCreate( &start_time );
hipEventCreate( &stop_time );
hipEventRecord( start_time, 0 );
/* start_time = omp_get_wtime();*/
for (i=1;i<= num_steps; i++){
x = (i-0.5)*step;
sum = sum + 4.0/(1.0+x*x);
}
pi = step * sum;
hipEventRecord( stop_time, 0 );
hipEventSynchronize( stop_time );
hipEventElapsedTime(&elapsed_time,start_time,stop_time);
/* run_time = omp_get_wtime() - start_time;*/
printf("\n pi with %ld steps is %lf in %lf millisecond\n ",num_steps,pi,elapsed_time);
hipEventDestroy( start_time );
hipEventDestroy( stop_time );
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
This program will numerically compute the integral of
4/(1+x*x)
from 0 to 1. The value of this integral is pi -- which
is great since it gives us an easy way to check the answer.
The is the original sequential program. It uses the timer
from the OpenMP runtime library
History: Written by Tim Mattson, 11/99.
*/
#include <stdio.h>
#include "hip/hip_runtime.h"
/*#include <omp.h>*/
static long num_steps = 1000000000;
double step;
int main ()
{
int i;
double x, pi, sum = 0.0;
hipEvent_t start_time, stop_time;
float elapsed_time;
step = 1.0/(double) num_steps;
hipEventCreate( &start_time );
hipEventCreate( &stop_time );
hipEventRecord( start_time, 0 );
/* start_time = omp_get_wtime();*/
for (i=1;i<= num_steps; i++){
x = (i-0.5)*step;
sum = sum + 4.0/(1.0+x*x);
}
pi = step * sum;
hipEventRecord( stop_time, 0 );
hipEventSynchronize( stop_time );
hipEventElapsedTime(&elapsed_time,start_time,stop_time);
/* run_time = omp_get_wtime() - start_time;*/
printf("\n pi with %ld steps is %lf in %lf millisecond\n ",num_steps,pi,elapsed_time);
hipEventDestroy( start_time );
hipEventDestroy( stop_time );
} | .text
.file "pi.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.LCPI0_1:
.quad 0xbfe0000000000000 # double -0.5
.LCPI0_2:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movabsq $4472406533629990549, %rax # imm = 0x3E112E0BE826D695
movq %rax, step(%rip)
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm7, %xmm7
movl $1000000000, %eax # imm = 0x3B9ACA00
movsd step(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI0_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI0_2(%rip), %xmm3 # xmm3 = mem[0],zero
movapd %xmm0, %xmm4
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movapd %xmm4, %xmm5
addsd %xmm2, %xmm5
mulsd %xmm1, %xmm5
mulsd %xmm5, %xmm5
addsd %xmm0, %xmm5
movapd %xmm3, %xmm6
divsd %xmm5, %xmm6
addsd %xmm6, %xmm7
addsd %xmm0, %xmm4
decl %eax
jne .LBB0_1
# %bb.2:
mulsd step(%rip), %xmm7
movsd %xmm7, 32(%rsp) # 8-byte Spill
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 28(%rsp), %rdi
callq hipEventElapsedTime
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movl $.L.str, %edi
movl $1000000000, %esi # imm = 0x3B9ACA00
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $2, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type step,@object # @step
.bss
.globl step
.p2align 3, 0x0
step:
.quad 0x0000000000000000 # double 0
.size step, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n pi with %ld steps is %lf in %lf millisecond\n "
.size .L.str, 48
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dbe75_00000000-6_pi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "\n pi with %ld steps is %lf in %lf millisecond\n "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq .LC1(%rip), %rax
movq %rax, step(%rip)
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movsd step(%rip), %xmm3
pxor %xmm1, %xmm1
movl $1, %eax
movsd .LC2(%rip), %xmm6
movsd .LC3(%rip), %xmm5
movsd .LC4(%rip), %xmm4
.L4:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
subsd %xmm6, %xmm0
mulsd %xmm3, %xmm0
mulsd %xmm0, %xmm0
addsd %xmm5, %xmm0
movapd %xmm4, %xmm2
divsd %xmm0, %xmm2
addsd %xmm2, %xmm1
addl $1, %eax
cmpl $1000000001, %eax
jne .L4
mulsd %xmm1, %xmm3
movsd %xmm3, 8(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm1, %xmm1
cvtss2sd 20(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movl $1000000000, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl step
.bss
.align 8
.type step, @object
.size step, 8
step:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -400107883
.long 1041313291
.align 8
.LC2:
.long 0
.long 1071644672
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pi.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.LCPI0_1:
.quad 0xbfe0000000000000 # double -0.5
.LCPI0_2:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
movabsq $4472406533629990549, %rax # imm = 0x3E112E0BE826D695
movq %rax, step(%rip)
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm7, %xmm7
movl $1000000000, %eax # imm = 0x3B9ACA00
movsd step(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI0_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI0_2(%rip), %xmm3 # xmm3 = mem[0],zero
movapd %xmm0, %xmm4
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movapd %xmm4, %xmm5
addsd %xmm2, %xmm5
mulsd %xmm1, %xmm5
mulsd %xmm5, %xmm5
addsd %xmm0, %xmm5
movapd %xmm3, %xmm6
divsd %xmm5, %xmm6
addsd %xmm6, %xmm7
addsd %xmm0, %xmm4
decl %eax
jne .LBB0_1
# %bb.2:
mulsd step(%rip), %xmm7
movsd %xmm7, 32(%rsp) # 8-byte Spill
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 28(%rsp), %rdi
callq hipEventElapsedTime
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movl $.L.str, %edi
movl $1000000000, %esi # imm = 0x3B9ACA00
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $2, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type step,@object # @step
.bss
.globl step
.p2align 3, 0x0
step:
.quad 0x0000000000000000 # double 0
.size step, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n pi with %ld steps is %lf in %lf millisecond\n "
.size .L.str, 48
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda_runtime.h>
#include <iomanip>
using namespace std;
struct feature {
int channel;
int width;
int height;
size_t size;
float* h_elements;
float* d_elements;
};
struct kernel {
int number;
int channel;
int width;
int height;
size_t size;
float* h_elements;
float* d_elements;
};
__global__ void Conv2dKernel(feature A, kernel B, feature C){
float Cvalue = 0;
int c = threadIdx.x;
int n = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
extern __shared__ float channels[];
channels[c] = 0;
for (int i = 0; i < B.width; i++){
for (int j = 0; j < B.height; j++){
int idxA = c * A.height * A.width + (w + i) * A.height + h + j;
int idxB = n * B.channel * B.width * B.height + c * B.width * B.height + i * B.width + j;
channels[c] += A.d_elements[idxA] * B.d_elements[idxB];
}
}
__syncthreads();
for (int i = 0; i < B.channel; i++)
Cvalue += channels[i];
__syncthreads();
C.d_elements[n * gridDim.y * gridDim.z + w * gridDim.z + h] = Cvalue;
}
__global__ void AddBiasKernel(feature A, kernel B){
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
int idxA = c * A.width*A.height + w * A.height + h;
A.d_elements[idxA] += B.d_elements[c];
}
__global__ void paddingKernel(float* A, feature B, int padding){
// A is original array, B is padded array
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
int idxA = c * gridDim.y*gridDim.z + w * gridDim.z + h;
int idxB = c * B.width*B.height + (w + padding) * B.height + (h + padding);
B.d_elements[idxB] = A[idxA];
}
__global__ void ReLUKernel(feature A){
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
int idxA = c * A.width*A.height + w * A.height + h;
if (A.d_elements[idxA] < 0)
A.d_elements[idxA] = 0;
}
__global__ void MaxpoolingKernel(feature A, feature B, int filter){
// A is input B is output
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
float max_value = A.d_elements[c * A.width*A.height + w*filter * A.height + h*filter];
for (int i = 0; i < filter; i++){
for (int j = 0; j < filter; j++){
int idxA = c * A.height * A.width + (w*filter + i) * A.height + h*filter + j;
if (max_value < A.d_elements[idxA])
max_value = A.d_elements[idxA];
}
}
int idxB = c * gridDim.y * gridDim.z + w * gridDim.z + h;
B.d_elements[idxB] = max_value;
}
void init_feature(feature& A, int channel, int width, int height, float init_value = 0);
void init_kernel(kernel& A, int number, int channel, int width, int height, float init_value = 0);
void init_feature(feature& A, int channel, int width, int height, string filename);
void init_kernel(kernel& A, int number, int channel, int width, int height, string filename);
void fprint(feature data);
void kprint(kernel data);
void make_pad(feature& A, int pad);
void ReLU(feature& A);
void convolution(feature& A, kernel B, int stride);
void addBias(feature& A, kernel B);
void maxPooling(feature& A, int filter);
void view(feature& A);
int main()
{
//feature A initialization
feature A;
init_feature(A, 3, 8, 8, 1);
cudaMalloc(&A.d_elements, A.size);
cudaMemcpy(A.d_elements, A.h_elements, A.size, cudaMemcpyHostToDevice);
fprint(A);
//kernel B initialization
kernel B;
init_kernel(B, 3, 3, 3, 3, 1);
cudaMalloc(&B.d_elements, B.size);
cudaMemcpy(B.d_elements, B.h_elements, B.size, cudaMemcpyHostToDevice);
kprint(B);
//kernel C initialization
kernel C;
init_kernel(C, 3, 1, 1, 1, 1);
cudaMalloc(&C.d_elements, C.size);
cudaMemcpy(C.d_elements, C.h_elements, C.size, cudaMemcpyHostToDevice);
kprint(C);
//calculation
make_pad(A, 1);
convolution(A, B, 1);
addBias(A,C);
ReLU(A);
maxPooling(A, 2);
view(A);
//receive data from device
delete A.h_elements;
A.size = A.channel * A.width * A.height * sizeof(float);
A.h_elements = new float [A.size];
cudaMemcpy(A.h_elements, A.d_elements, A.size, cudaMemcpyDeviceToHost);
//print data
fprint(A);
//release all cuda memories
cudaFree(A.d_elements);
cudaFree(B.d_elements);
cudaFree(C.d_elements);
return 0;
}
void init_feature(feature& A, int channel, int width, int height, float init_value){
A.channel = channel;
A.width = width;
A.height = height;
size_t size = channel * width * height;
A.h_elements = new float [size];
if (init_value != 0)
for (int i = 0; i < size; i++)
A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void init_kernel(kernel& A, int number, int channel, int width, int height, float init_value){
A.number = number;
A.channel = channel;
A.width = width;
A.height = height;
size_t size = number * channel * width * height;
A.h_elements = new float [size];
if (init_value != 0)
for (int i = 0; i < size; i++)
A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void init_feature(feature& A, int channel, int width, int height, string filename){
A.channel = channel;
A.width = width;
A.height = height;
size_t size = channel * width * height;
A.h_elements = new float [size];
// if (init_value != 0)
// for (int i = 0; i < size; i++)
// A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void init_kernel(kernel& A, int number, int channel, int width, int height, string filename){
A.number = number;
A.channel = channel;
A.width = width;
A.height = height;
size_t size = number * channel * width * height;
A.h_elements = new float [size];
// if (init_value != 0)
// for (int i = 0; i < size; i++)
// A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void fprint(feature data){
cout << "feature type \n[ " << data.channel << ", " << data.width << ", " << data.height << " ]" << endl;
for (int i = 0; i < data.channel; i++){
for (int j = 0; j < data.width; j++){
for (int k = 0; k < data.height; k++){
cout << setw(3) << data.h_elements[i * data.width*data.height + j * data.height + k];
}
cout << endl;
}
cout << endl;
}
}
void kprint(kernel data){
cout << "kernel type \n[ " << data.number << ", " << data.channel << ", " << data.width << ", " << data.height << " ]" << endl;
for (int i = 0; i < data.number; i++){
for (int j = 0; j < data.channel; j++){
for (int k = 0; k < data.width; k++){
for (int l = 0; l < data.height; l++){
cout << setw(3) << data.h_elements[i * data.channel*data.width*data.height + j * data.width*data.height + k * data.height + l];
}
cout << endl;
}
cout << endl;
}
cout << endl;
}
}
void make_pad(feature& A, int pad){
//invoke kernel padding
float* temp;
cudaMalloc(&temp, A.size);
cudaMemcpy(temp, A.d_elements, A.size, cudaMemcpyDeviceToDevice);
dim3 dimGrid(A.channel, A.width, A.height);
A.height += 2*pad; A.width += 2*pad;
A.size = A.channel * A.width * A.height * sizeof(float);
cudaFree(A.d_elements);
cudaMalloc(&A.d_elements, A.size);
cudaMemset(A.d_elements, 0, A.size);
paddingKernel<<<dimGrid, 1>>> (temp, A, pad);
cudaFree(temp);
}
void ReLU(feature& A){
//invoke kernel relu
dim3 dimGrid(A.channel, A.width, A.height);
ReLUKernel<<<dimGrid, 1>>>(A);
}
void convolution(feature& A, kernel B, int stride){
feature temp;
init_feature(temp, B.number, A.width - B.width + 1, A.height - B.height + 1, 0);
cudaMalloc(&temp.d_elements, temp.size);
dim3 dimGrid(temp.channel, temp.width, temp.height);
Conv2dKernel<<<dimGrid, A.channel, A.channel>>>(A, B, temp);
cudaFree(A.d_elements);
cudaMalloc(&A.d_elements, temp.size);
cudaMemcpy(A.d_elements, temp.d_elements, temp.size, cudaMemcpyDeviceToDevice);
delete temp.h_elements;
cudaFree(temp.d_elements);
A.channel = temp.channel;
A.width = temp.width;
A.height = temp.height;
}
void addBias(feature& A, kernel B){
dim3 dimGrid(A.channel, A.width, A.height);
AddBiasKernel<<<dimGrid, 1>>>(A, B);
}
void maxPooling(feature& A, int filter){
feature temp;
init_feature(temp, A.channel, A.width / filter, A.height / filter);
cudaMalloc(&temp.d_elements, temp.size);
dim3 dimGrid(temp.channel, temp.width, temp.height);
MaxpoolingKernel<<<dimGrid, 1>>>(A, temp, filter);
cudaFree(A.d_elements);
cudaMalloc(&A.d_elements, temp.size);
cudaMemcpy(A.d_elements, temp.d_elements, temp.size, cudaMemcpyDeviceToDevice);
delete temp.h_elements;
cudaFree(temp.d_elements);
A.channel = temp.channel;
A.width = temp.width;
A.height = temp.height;
}
void view(feature& A){
A.channel = A.channel*A.width*A.height;
A.width = 1;
A.height = 1;
} | .file "tmpxft_00000f31_00000000-6_VGG_CUDA.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3964:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3964:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12init_featureR7featureiiif
.type _Z12init_featureR7featureiiif, @function
_Z12init_featureR7featureiiif:
.LFB3950:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %esi, (%rdi)
movl %edx, 4(%rdi)
movl %ecx, 8(%rdi)
imull %edx, %esi
imull %ecx, %esi
movslq %esi, %rbx
movabsq $2305843009213693950, %rax
cmpq %rbx, %rax
jb .L4
movq %rdi, %rbp
movd %xmm0, %r12d
leaq 0(,%rbx,4), %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, 24(%rbp)
pxor %xmm0, %xmm0
movd %r12d, %xmm1
ucomiss %xmm0, %xmm1
jp .L9
jne .L9
.L5:
movq %r13, 16(%rbp)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movl $0, %eax
testq %rbx, %rbx
je .L5
.L7:
movq 24(%rbp), %rdx
movl %r12d, (%rdx,%rax)
addq $4, %rax
cmpq %r13, %rax
jne .L7
jmp .L5
.L4:
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3950:
.size _Z12init_featureR7featureiiif, .-_Z12init_featureR7featureiiif
.globl _Z11init_kernelR6kerneliiiif
.type _Z11init_kernelR6kerneliiiif, @function
_Z11init_kernelR6kerneliiiif:
.LFB3951:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %esi, (%rdi)
movl %edx, 4(%rdi)
movl %ecx, 8(%rdi)
movl %r8d, 12(%rdi)
imull %edx, %esi
movl %esi, %ebx
imull %ecx, %ebx
imull %r8d, %ebx
movslq %ebx, %rbx
movabsq $2305843009213693950, %rax
cmpq %rbx, %rax
jb .L14
movq %rdi, %rbp
movd %xmm0, %r12d
leaq 0(,%rbx,4), %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, 24(%rbp)
pxor %xmm0, %xmm0
movd %r12d, %xmm1
ucomiss %xmm0, %xmm1
jp .L19
jne .L19
.L15:
movq %r13, 16(%rbp)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $0, %eax
testq %rbx, %rbx
je .L15
.L17:
movq 24(%rbp), %rdx
movl %r12d, (%rdx,%rax)
addq $4, %rax
cmpq %r13, %rax
jne .L17
jmp .L15
.L14:
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3951:
.size _Z11init_kernelR6kerneliiiif, .-_Z11init_kernelR6kerneliiiif
.globl _Z12init_featureR7featureiiiNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _Z12init_featureR7featureiiiNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_Z12init_featureR7featureiiiNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3952:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %esi, (%rdi)
movl %edx, 4(%rdi)
movl %ecx, 8(%rdi)
imull %edx, %esi
imull %ecx, %esi
movslq %esi, %rbx
movabsq $2305843009213693950, %rax
cmpq %rbx, %rax
jb .L24
movq %rdi, %rbp
salq $2, %rbx
movq %rbx, %rdi
call _Znam@PLT
movq %rax, 24(%rbp)
movq %rbx, 16(%rbp)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3952:
.size _Z12init_featureR7featureiiiNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_Z12init_featureR7featureiiiNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.globl _Z11init_kernelR6kerneliiiiNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _Z11init_kernelR6kerneliiiiNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_Z11init_kernelR6kerneliiiiNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3953:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %esi, (%rdi)
movl %edx, 4(%rdi)
movl %ecx, 8(%rdi)
movl %r8d, 12(%rdi)
imull %edx, %esi
movl %esi, %ebx
imull %ecx, %ebx
imull %r8d, %ebx
movslq %ebx, %rbx
movabsq $2305843009213693950, %rax
cmpq %rbx, %rax
jb .L28
movq %rdi, %rbp
salq $2, %rbx
movq %rbx, %rdi
call _Znam@PLT
movq %rax, 24(%rbp)
movq %rbx, 16(%rbp)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3953:
.size _Z11init_kernelR6kerneliiiiNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_Z11init_kernelR6kerneliiiiNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "feature type \n[ "
.LC2:
.string ", "
.LC3:
.string " ]"
.text
.globl _Z6fprint7feature
.type _Z6fprint7feature, @function
_Z6fprint7feature:
.LFB3954:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl 96(%rsp), %r14d
movl %r14d, 24(%rsp)
movl 100(%rsp), %r13d
movl %r13d, 12(%rsp)
movl 104(%rsp), %r15d
movl $16, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r14d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
leaq .LC2(%rip), %rbp
movq %rbp, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %rbp, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r15d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L52
cmpb $0, 56(%rbp)
je .L33
movzbl 67(%rbp), %eax
.L34:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
cmpl $0, 24(%rsp)
jle .L31
movl 12(%rsp), %eax
imull %r15d, %eax
movl %eax, 28(%rsp)
movl $0, 20(%rsp)
movl $0, 16(%rsp)
leaq _ZSt4cout(%rip), %rbp
jmp .L36
.L52:
call _ZSt16__throw_bad_castv@PLT
.L33:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L34
.L53:
call _ZSt16__throw_bad_castv@PLT
.L39:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L40:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L41
.L47:
testl %r15d, %r15d
jle .L43
movslq %r14d, %rax
leaq 0(,%rax,4), %rbx
movslq %r15d, %r12
addq %rax, %r12
salq $2, %r12
.L37:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq $3, 16(%rbp,%rax)
movq 120(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
addq $4, %rbx
cmpq %rbx, %r12
jne .L37
.L43:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L53
cmpb $0, 56(%rbx)
je .L39
movzbl 67(%rbx), %esi
jmp .L40
.L41:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L54
cmpb $0, 56(%rbx)
je .L45
movzbl 67(%rbx), %eax
.L46:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, 16(%rsp)
movl 16(%rsp), %eax
movl 28(%rsp), %edx
addl %edx, 20(%rsp)
cmpl %eax, 24(%rsp)
je .L31
.L36:
movl 20(%rsp), %r14d
movl $0, %r13d
cmpl $0, 12(%rsp)
jg .L47
jmp .L41
.L54:
call _ZSt16__throw_bad_castv@PLT
.L45:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L46
.L31:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3954:
.size _Z6fprint7feature, .-_Z6fprint7feature
.section .rodata.str1.1
.LC4:
.string "kernel type \n[ "
.text
.globl _Z6kprint6kernel
.type _Z6kprint6kernel, @function
_Z6kprint6kernel:
.LFB3955:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl 112(%rsp), %r13d
movl 116(%rsp), %r15d
movl %r15d, 24(%rsp)
movl 120(%rsp), %r14d
movl %r14d, 12(%rsp)
movl 124(%rsp), %r12d
movl $15, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
leaq .LC2(%rip), %rbp
movq %rbp, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r15d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %rbp, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r14d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %rbp, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L87
cmpb $0, 56(%rbp)
je .L57
movzbl 67(%rbp), %eax
.L58:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
testl %r13d, %r13d
jle .L55
movl 24(%rsp), %eax
movl 12(%rsp), %edx
imull %edx, %eax
imull %r12d, %eax
movl %eax, 32(%rsp)
imull %r12d, %edx
movl %edx, 28(%rsp)
movl $0, %r15d
movl $0, %r14d
leaq _ZSt4cout(%rip), %rbp
jmp .L60
.L87:
call _ZSt16__throw_bad_castv@PLT
.L57:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L58
.L88:
call _ZSt16__throw_bad_castv@PLT
.L63:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L64:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
addl %r12d, %r15d
cmpl %r14d, 12(%rsp)
je .L82
.L72:
testl %r12d, %r12d
jle .L67
movslq %r15d, %rax
leaq 0(,%rax,4), %rbx
movslq %r12d, %r13
addq %rax, %r13
salq $2, %r13
.L61:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq $3, 16(%rbp,%rax)
movq 136(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L61
.L67:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L88
cmpb $0, 56(%rbx)
je .L63
movzbl 67(%rbx), %esi
jmp .L64
.L82:
movl 20(%rsp), %ebx
.L65:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r13
testq %r13, %r13
je .L89
cmpb $0, 56(%r13)
je .L69
movzbl 67(%r13), %eax
.L70:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebx
movl 28(%rsp), %ecx
addl %ecx, 16(%rsp)
cmpl %ebx, 24(%rsp)
je .L83
.L76:
movl 16(%rsp), %r15d
movl $0, %r14d
cmpl $0, 12(%rsp)
jle .L65
movl %ebx, 20(%rsp)
jmp .L72
.L89:
call _ZSt16__throw_bad_castv@PLT
.L69:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
jmp .L70
.L83:
movl 36(%rsp), %r13d
movl 40(%rsp), %r14d
movl 44(%rsp), %r15d
.L71:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L90
cmpb $0, 56(%rbx)
je .L74
movzbl 67(%rbx), %eax
.L75:
movsbl %al, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
movl 32(%rsp), %eax
addl %eax, %r15d
cmpl %r14d, %r13d
je .L55
.L60:
movl %r15d, 16(%rsp)
movl $0, %ebx
cmpl $0, 24(%rsp)
jle .L71
movl %r13d, 36(%rsp)
movl %r14d, 40(%rsp)
movl %r15d, 44(%rsp)
jmp .L76
.L90:
call _ZSt16__throw_bad_castv@PLT
.L74:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L75
.L55:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _Z6kprint6kernel, .-_Z6kprint6kernel
.globl _Z4viewR7feature
.type _Z4viewR7feature, @function
_Z4viewR7feature:
.LFB3961:
.cfi_startproc
endbr64
movl (%rdi), %eax
imull 4(%rdi), %eax
imull 8(%rdi), %eax
movl %eax, (%rdi)
movl $1, 4(%rdi)
movl $1, 8(%rdi)
ret
.cfi_endproc
.LFE3961:
.size _Z4viewR7feature, .-_Z4viewR7feature
.globl _Z47__device_stub__Z12Conv2dKernel7feature6kernelS_R7featureR6kernelS0_
.type _Z47__device_stub__Z12Conv2dKernel7feature6kernelS_R7featureR6kernelS0_, @function
_Z47__device_stub__Z12Conv2dKernel7feature6kernelS_R7featureR6kernelS0_:
.LFB3986:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L96
.L92:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L97
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L96:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12Conv2dKernel7feature6kernelS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L92
.L97:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3986:
.size _Z47__device_stub__Z12Conv2dKernel7feature6kernelS_R7featureR6kernelS0_, .-_Z47__device_stub__Z12Conv2dKernel7feature6kernelS_R7featureR6kernelS0_
.globl _Z12Conv2dKernel7feature6kernelS_
.type _Z12Conv2dKernel7feature6kernelS_, @function
_Z12Conv2dKernel7feature6kernelS_:
.LFB3987:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 96(%rsp), %rdx
leaq 56(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z47__device_stub__Z12Conv2dKernel7feature6kernelS_R7featureR6kernelS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3987:
.size _Z12Conv2dKernel7feature6kernelS_, .-_Z12Conv2dKernel7feature6kernelS_
.globl _Z11convolutionR7feature6kerneli
.type _Z11convolutionR7feature6kerneli, @function
_Z11convolutionR7feature6kerneli:
.LFB3958:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $224, %rsp
.cfi_def_cfa_offset 240
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movl 8(%rdi), %ecx
subl 252(%rsp), %ecx
addl $1, %ecx
movl 4(%rdi), %edx
subl 248(%rsp), %edx
addl $1, %edx
leaq 32(%rsp), %rdi
pxor %xmm0, %xmm0
movl 240(%rsp), %esi
call _Z12init_featureR7featureiiif
leaq 64(%rsp), %rdi
movq 48(%rsp), %rsi
call cudaMalloc@PLT
movl 32(%rsp), %eax
movl %eax, 8(%rsp)
movl 36(%rsp), %eax
movl %eax, 12(%rsp)
movl (%rbx), %r8d
movl %r8d, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L105
.L101:
movq 32(%rbx), %rdi
call cudaFree@PLT
leaq 32(%rbx), %rdi
movq 48(%rsp), %rsi
call cudaMalloc@PLT
movq 32(%rbx), %rdi
movl $3, %ecx
movq 48(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
testq %rdi, %rdi
je .L102
movl $4, %esi
call _ZdlPvm@PLT
.L102:
movq 64(%rsp), %rdi
call cudaFree@PLT
movl 32(%rsp), %eax
movl %eax, (%rbx)
movl 36(%rsp), %eax
movl %eax, 4(%rbx)
movl 40(%rsp), %eax
movl %eax, 8(%rbx)
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L106
addq $224, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L105:
.cfi_restore_state
movdqu (%rbx), %xmm1
movaps %xmm1, 80(%rsp)
movdqu 16(%rbx), %xmm2
movaps %xmm2, 96(%rsp)
movq 32(%rbx), %rax
movq %rax, 112(%rsp)
movdqu 240(%rsp), %xmm3
movaps %xmm3, 128(%rsp)
movdqu 256(%rsp), %xmm4
movaps %xmm4, 144(%rsp)
movq 272(%rsp), %rax
movq %rax, 160(%rsp)
movdqa 32(%rsp), %xmm5
movaps %xmm5, 176(%rsp)
movdqa 48(%rsp), %xmm6
movaps %xmm6, 192(%rsp)
movq 64(%rsp), %rax
movq %rax, 208(%rsp)
leaq 176(%rsp), %rdx
leaq 128(%rsp), %rsi
leaq 80(%rsp), %rdi
call _Z47__device_stub__Z12Conv2dKernel7feature6kernelS_R7featureR6kernelS0_
jmp .L101
.L106:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3958:
.size _Z11convolutionR7feature6kerneli, .-_Z11convolutionR7feature6kerneli
.globl _Z46__device_stub__Z13AddBiasKernel7feature6kernelR7featureR6kernel
.type _Z46__device_stub__Z13AddBiasKernel7feature6kernelR7featureR6kernel, @function
_Z46__device_stub__Z13AddBiasKernel7feature6kernelR7featureR6kernel:
.LFB3988:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L111
.L107:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L112
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L111:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13AddBiasKernel7feature6kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L107
.L112:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3988:
.size _Z46__device_stub__Z13AddBiasKernel7feature6kernelR7featureR6kernel, .-_Z46__device_stub__Z13AddBiasKernel7feature6kernelR7featureR6kernel
.globl _Z13AddBiasKernel7feature6kernel
.type _Z13AddBiasKernel7feature6kernel, @function
_Z13AddBiasKernel7feature6kernel:
.LFB3989:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 56(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z46__device_stub__Z13AddBiasKernel7feature6kernelR7featureR6kernel
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3989:
.size _Z13AddBiasKernel7feature6kernel, .-_Z13AddBiasKernel7feature6kernel
.globl _Z7addBiasR7feature6kernel
.type _Z7addBiasR7feature6kernel, @function
_Z7addBiasR7feature6kernel:
.LFB3959:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
addq $-128, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl 8(%rdi), %esi
movl 4(%rdi), %eax
movl (%rdi), %edx
movl %edx, 8(%rsp)
movl %eax, 12(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L119
.L115:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L120
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L119:
.cfi_restore_state
movdqu (%rbx), %xmm0
movaps %xmm0, 32(%rsp)
movdqu 16(%rbx), %xmm1
movaps %xmm1, 48(%rsp)
movq 32(%rbx), %rax
movq %rax, 64(%rsp)
movdqu 144(%rsp), %xmm2
movaps %xmm2, 80(%rsp)
movdqu 160(%rsp), %xmm3
movaps %xmm3, 96(%rsp)
movq 176(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z46__device_stub__Z13AddBiasKernel7feature6kernelR7featureR6kernel
jmp .L115
.L120:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3959:
.size _Z7addBiasR7feature6kernel, .-_Z7addBiasR7feature6kernel
.globl _Z42__device_stub__Z13paddingKernelPf7featureiPfR7featurei
.type _Z42__device_stub__Z13paddingKernelPf7featureiPfR7featurei, @function
_Z42__device_stub__Z13paddingKernelPf7featureiPfR7featurei:
.LFB3990:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsi, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L125
.L121:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L126
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L125:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13paddingKernelPf7featurei(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L121
.L126:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3990:
.size _Z42__device_stub__Z13paddingKernelPf7featureiPfR7featurei, .-_Z42__device_stub__Z13paddingKernelPf7featureiPfR7featurei
.globl _Z13paddingKernelPf7featurei
.type _Z13paddingKernelPf7featurei, @function
_Z13paddingKernelPf7featurei:
.LFB3991:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %esi, %edx
leaq 16(%rsp), %rsi
call _Z42__device_stub__Z13paddingKernelPf7featureiPfR7featurei
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3991:
.size _Z13paddingKernelPf7featurei, .-_Z13paddingKernelPf7featurei
.globl _Z8make_padR7featurei
.type _Z8make_padR7featurei, @function
_Z8make_padR7featurei:
.LFB3956:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 16(%rdi), %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movq 16(%rbx), %rdx
movq 32(%rbx), %rsi
movl $3, %ecx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl 8(%rbx), %edx
movl 4(%rbx), %ecx
movl (%rbx), %eax
movl %eax, 8(%rsp)
movl %ecx, 12(%rsp)
movl %edx, 16(%rsp)
leal (%rbp,%rbp), %esi
addl %esi, %edx
movl %edx, 8(%rbx)
addl %esi, %ecx
movl %ecx, 4(%rbx)
imull %ecx, %eax
imull %edx, %eax
cltq
salq $2, %rax
movq %rax, 16(%rbx)
movq 32(%rbx), %rdi
call cudaFree@PLT
movq 16(%rbx), %rsi
leaq 32(%rbx), %rdi
call cudaMalloc@PLT
movq 16(%rbx), %rdx
movq 32(%rbx), %rdi
movl $0, %esi
call cudaMemset@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L133
.L130:
movq (%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L134
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L133:
.cfi_restore_state
movdqu (%rbx), %xmm0
movaps %xmm0, 32(%rsp)
movdqu 16(%rbx), %xmm1
movaps %xmm1, 48(%rsp)
movq 32(%rbx), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rsi
movl %ebp, %edx
movq (%rsp), %rdi
call _Z42__device_stub__Z13paddingKernelPf7featureiPfR7featurei
jmp .L130
.L134:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3956:
.size _Z8make_padR7featurei, .-_Z8make_padR7featurei
.globl _Z36__device_stub__Z10ReLUKernel7featureR7feature
.type _Z36__device_stub__Z10ReLUKernel7featureR7feature, @function
_Z36__device_stub__Z10ReLUKernel7featureR7feature:
.LFB3992:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L139
.L135:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L140
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L139:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10ReLUKernel7feature(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L135
.L140:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3992:
.size _Z36__device_stub__Z10ReLUKernel7featureR7feature, .-_Z36__device_stub__Z10ReLUKernel7featureR7feature
.globl _Z10ReLUKernel7feature
.type _Z10ReLUKernel7feature, @function
_Z10ReLUKernel7feature:
.LFB3993:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdi
call _Z36__device_stub__Z10ReLUKernel7featureR7feature
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3993:
.size _Z10ReLUKernel7feature, .-_Z10ReLUKernel7feature
.globl _Z4ReLUR7feature
.type _Z4ReLUR7feature, @function
_Z4ReLUR7feature:
.LFB3957:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $80, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl 8(%rdi), %esi
movl 4(%rdi), %eax
movl (%rdi), %edx
movl %edx, 8(%rsp)
movl %eax, 12(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L147
.L143:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L148
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L147:
.cfi_restore_state
movdqu (%rbx), %xmm0
movaps %xmm0, 32(%rsp)
movdqu 16(%rbx), %xmm1
movaps %xmm1, 48(%rsp)
movq 32(%rbx), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
call _Z36__device_stub__Z10ReLUKernel7featureR7feature
jmp .L143
.L148:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3957:
.size _Z4ReLUR7feature, .-_Z4ReLUR7feature
.globl _Z45__device_stub__Z16MaxpoolingKernel7featureS_iR7featureS0_i
.type _Z45__device_stub__Z16MaxpoolingKernel7featureS_iR7featureS0_i, @function
_Z45__device_stub__Z16MaxpoolingKernel7featureS_iR7featureS0_i:
.LFB3994:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L153
.L149:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L154
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L153:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16MaxpoolingKernel7featureS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L149
.L154:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3994:
.size _Z45__device_stub__Z16MaxpoolingKernel7featureS_iR7featureS0_i, .-_Z45__device_stub__Z16MaxpoolingKernel7featureS_iR7featureS0_i
.globl _Z16MaxpoolingKernel7featureS_i
.type _Z16MaxpoolingKernel7featureS_i, @function
_Z16MaxpoolingKernel7featureS_i:
.LFB3995:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %edx
leaq 56(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z45__device_stub__Z16MaxpoolingKernel7featureS_iR7featureS0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3995:
.size _Z16MaxpoolingKernel7featureS_i, .-_Z16MaxpoolingKernel7featureS_i
.globl _Z10maxPoolingR7featurei
.type _Z10maxPoolingR7featurei, @function
_Z10maxPoolingR7featurei:
.LFB3960:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $184, %rsp
.cfi_def_cfa_offset 208
movq %rdi, %rbx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl 8(%rdi), %eax
cltd
idivl %esi
movl %eax, %ecx
movl 4(%rdi), %eax
cltd
idivl %esi
movl (%rdi), %esi
leaq 32(%rsp), %rdi
pxor %xmm0, %xmm0
movl %eax, %edx
call _Z12init_featureR7featureiiif
leaq 64(%rsp), %rdi
movq 48(%rsp), %rsi
call cudaMalloc@PLT
movl 32(%rsp), %eax
movl %eax, 8(%rsp)
movl 36(%rsp), %eax
movl %eax, 12(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L162
.L158:
movq 32(%rbx), %rdi
call cudaFree@PLT
leaq 32(%rbx), %rdi
movq 48(%rsp), %rsi
call cudaMalloc@PLT
movq 32(%rbx), %rdi
movl $3, %ecx
movq 48(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
testq %rdi, %rdi
je .L159
movl $4, %esi
call _ZdlPvm@PLT
.L159:
movq 64(%rsp), %rdi
call cudaFree@PLT
movl 32(%rsp), %eax
movl %eax, (%rbx)
movl 36(%rsp), %eax
movl %eax, 4(%rbx)
movl 40(%rsp), %eax
movl %eax, 8(%rbx)
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L163
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L162:
.cfi_restore_state
movdqu (%rbx), %xmm1
movaps %xmm1, 80(%rsp)
movdqu 16(%rbx), %xmm2
movaps %xmm2, 96(%rsp)
movq 32(%rbx), %rax
movq %rax, 112(%rsp)
movdqa 32(%rsp), %xmm3
movaps %xmm3, 128(%rsp)
movdqa 48(%rsp), %xmm4
movaps %xmm4, 144(%rsp)
movq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 128(%rsp), %rsi
leaq 80(%rsp), %rdi
movl %ebp, %edx
call _Z45__device_stub__Z16MaxpoolingKernel7featureS_iR7featureS0_i
jmp .L158
.L163:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3960:
.size _Z10maxPoolingR7featurei, .-_Z10maxPoolingR7featurei
.globl main
.type main, @function
main:
.LFB3949:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $144, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movss .LC5(%rip), %xmm0
movl $8, %ecx
movl $8, %edx
movl $3, %esi
movq %rbx, %rdi
call _Z12init_featureR7featureiiif
leaq 32(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
subq $48, %rsp
.cfi_def_cfa_offset 208
movdqa 48(%rsp), %xmm1
movups %xmm1, (%rsp)
movdqa 64(%rsp), %xmm2
movups %xmm2, 16(%rsp)
movq 80(%rsp), %rax
movq %rax, 32(%rsp)
call _Z6fprint7feature
movq %rbx, %rsp
.cfi_def_cfa_offset 160
leaq 48(%rsp), %rdi
movss .LC5(%rip), %xmm0
movl $3, %r8d
movl $3, %ecx
movl $3, %edx
movl $3, %esi
call _Z11init_kernelR6kerneliiiif
leaq 80(%rsp), %rdi
movq 64(%rsp), %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 64(%rsp), %rdx
movq 72(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
subq $48, %rsp
.cfi_def_cfa_offset 208
movdqa 96(%rsp), %xmm3
movups %xmm3, (%rsp)
movdqa 112(%rsp), %xmm4
movups %xmm4, 16(%rsp)
movq 128(%rsp), %rax
movq %rax, 32(%rsp)
call _Z6kprint6kernel
movq %rbx, %rsp
.cfi_def_cfa_offset 160
leaq 96(%rsp), %rdi
movss .LC5(%rip), %xmm0
movl $1, %r8d
movl $1, %ecx
movl $1, %edx
movl $3, %esi
call _Z11init_kernelR6kerneliiiif
leaq 128(%rsp), %rdi
movq 112(%rsp), %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 112(%rsp), %rdx
movq 120(%rsp), %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
subq $48, %rsp
.cfi_def_cfa_offset 208
movdqa 144(%rsp), %xmm5
movups %xmm5, (%rsp)
movdqa 160(%rsp), %xmm6
movups %xmm6, 16(%rsp)
movq 176(%rsp), %rax
movq %rax, 32(%rsp)
call _Z6kprint6kernel
movq %rbx, %rsp
.cfi_def_cfa_offset 160
movl $1, %esi
movq %rbx, %rdi
call _Z8make_padR7featurei
subq $48, %rsp
.cfi_def_cfa_offset 208
movdqa 96(%rsp), %xmm7
movups %xmm7, (%rsp)
movdqa 112(%rsp), %xmm1
movups %xmm1, 16(%rsp)
movq 128(%rsp), %rax
movq %rax, 32(%rsp)
movl $1, %esi
movq %rbx, %rdi
call _Z11convolutionR7feature6kerneli
movdqa 144(%rsp), %xmm2
movups %xmm2, (%rsp)
movdqa 160(%rsp), %xmm3
movups %xmm3, 16(%rsp)
movq 176(%rsp), %rax
movq %rax, 32(%rsp)
movq %rbx, %rdi
call _Z7addBiasR7feature6kernel
movq %rbx, %rsp
.cfi_def_cfa_offset 160
movq %rbx, %rdi
call _Z4ReLUR7feature
movl $2, %esi
movq %rbx, %rdi
call _Z10maxPoolingR7featurei
movq %rbx, %rdi
call _Z4viewR7feature
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .L165
movl $4, %esi
call _ZdlPvm@PLT
.L165:
movl (%rsp), %edi
imull 4(%rsp), %edi
imull 8(%rsp), %edi
movslq %edi, %rdi
leaq 0(,%rdi,4), %rax
movq %rax, 16(%rsp)
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L166
salq $4, %rdi
call _Znam@PLT
movq %rax, %rdi
movq %rax, 24(%rsp)
movl $2, %ecx
movq 16(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
subq $48, %rsp
.cfi_def_cfa_offset 208
movdqa 48(%rsp), %xmm4
movups %xmm4, (%rsp)
movdqa 64(%rsp), %xmm5
movups %xmm5, 16(%rsp)
movq 80(%rsp), %rax
movq %rax, 32(%rsp)
call _Z6fprint7feature
addq $48, %rsp
.cfi_def_cfa_offset 160
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L171
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L166:
.cfi_restore_state
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L167
call __stack_chk_fail@PLT
.L167:
call __cxa_throw_bad_array_new_length@PLT
.L171:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z16MaxpoolingKernel7featureS_i"
.section .rodata.str1.1
.LC7:
.string "_Z10ReLUKernel7feature"
.LC8:
.string "_Z13paddingKernelPf7featurei"
.section .rodata.str1.8
.align 8
.LC9:
.string "_Z13AddBiasKernel7feature6kernel"
.align 8
.LC10:
.string "_Z12Conv2dKernel7feature6kernelS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3997:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16MaxpoolingKernel7featureS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10ReLUKernel7feature(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13paddingKernelPf7featurei(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z13AddBiasKernel7feature6kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z12Conv2dKernel7feature6kernelS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3997:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda_runtime.h>
#include <iomanip>
using namespace std;
struct feature {
int channel;
int width;
int height;
size_t size;
float* h_elements;
float* d_elements;
};
struct kernel {
int number;
int channel;
int width;
int height;
size_t size;
float* h_elements;
float* d_elements;
};
__global__ void Conv2dKernel(feature A, kernel B, feature C){
float Cvalue = 0;
int c = threadIdx.x;
int n = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
extern __shared__ float channels[];
channels[c] = 0;
for (int i = 0; i < B.width; i++){
for (int j = 0; j < B.height; j++){
int idxA = c * A.height * A.width + (w + i) * A.height + h + j;
int idxB = n * B.channel * B.width * B.height + c * B.width * B.height + i * B.width + j;
channels[c] += A.d_elements[idxA] * B.d_elements[idxB];
}
}
__syncthreads();
for (int i = 0; i < B.channel; i++)
Cvalue += channels[i];
__syncthreads();
C.d_elements[n * gridDim.y * gridDim.z + w * gridDim.z + h] = Cvalue;
}
__global__ void AddBiasKernel(feature A, kernel B){
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
int idxA = c * A.width*A.height + w * A.height + h;
A.d_elements[idxA] += B.d_elements[c];
}
__global__ void paddingKernel(float* A, feature B, int padding){
// A is original array, B is padded array
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
int idxA = c * gridDim.y*gridDim.z + w * gridDim.z + h;
int idxB = c * B.width*B.height + (w + padding) * B.height + (h + padding);
B.d_elements[idxB] = A[idxA];
}
__global__ void ReLUKernel(feature A){
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
int idxA = c * A.width*A.height + w * A.height + h;
if (A.d_elements[idxA] < 0)
A.d_elements[idxA] = 0;
}
__global__ void MaxpoolingKernel(feature A, feature B, int filter){
// A is input B is output
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
float max_value = A.d_elements[c * A.width*A.height + w*filter * A.height + h*filter];
for (int i = 0; i < filter; i++){
for (int j = 0; j < filter; j++){
int idxA = c * A.height * A.width + (w*filter + i) * A.height + h*filter + j;
if (max_value < A.d_elements[idxA])
max_value = A.d_elements[idxA];
}
}
int idxB = c * gridDim.y * gridDim.z + w * gridDim.z + h;
B.d_elements[idxB] = max_value;
}
void init_feature(feature& A, int channel, int width, int height, float init_value = 0);
void init_kernel(kernel& A, int number, int channel, int width, int height, float init_value = 0);
void init_feature(feature& A, int channel, int width, int height, string filename);
void init_kernel(kernel& A, int number, int channel, int width, int height, string filename);
void fprint(feature data);
void kprint(kernel data);
void make_pad(feature& A, int pad);
void ReLU(feature& A);
void convolution(feature& A, kernel B, int stride);
void addBias(feature& A, kernel B);
void maxPooling(feature& A, int filter);
void view(feature& A);
int main()
{
//feature A initialization
feature A;
init_feature(A, 3, 8, 8, 1);
cudaMalloc(&A.d_elements, A.size);
cudaMemcpy(A.d_elements, A.h_elements, A.size, cudaMemcpyHostToDevice);
fprint(A);
//kernel B initialization
kernel B;
init_kernel(B, 3, 3, 3, 3, 1);
cudaMalloc(&B.d_elements, B.size);
cudaMemcpy(B.d_elements, B.h_elements, B.size, cudaMemcpyHostToDevice);
kprint(B);
//kernel C initialization
kernel C;
init_kernel(C, 3, 1, 1, 1, 1);
cudaMalloc(&C.d_elements, C.size);
cudaMemcpy(C.d_elements, C.h_elements, C.size, cudaMemcpyHostToDevice);
kprint(C);
//calculation
make_pad(A, 1);
convolution(A, B, 1);
addBias(A,C);
ReLU(A);
maxPooling(A, 2);
view(A);
//receive data from device
delete A.h_elements;
A.size = A.channel * A.width * A.height * sizeof(float);
A.h_elements = new float [A.size];
cudaMemcpy(A.h_elements, A.d_elements, A.size, cudaMemcpyDeviceToHost);
//print data
fprint(A);
//release all cuda memories
cudaFree(A.d_elements);
cudaFree(B.d_elements);
cudaFree(C.d_elements);
return 0;
}
void init_feature(feature& A, int channel, int width, int height, float init_value){
A.channel = channel;
A.width = width;
A.height = height;
size_t size = channel * width * height;
A.h_elements = new float [size];
if (init_value != 0)
for (int i = 0; i < size; i++)
A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void init_kernel(kernel& A, int number, int channel, int width, int height, float init_value){
A.number = number;
A.channel = channel;
A.width = width;
A.height = height;
size_t size = number * channel * width * height;
A.h_elements = new float [size];
if (init_value != 0)
for (int i = 0; i < size; i++)
A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void init_feature(feature& A, int channel, int width, int height, string filename){
A.channel = channel;
A.width = width;
A.height = height;
size_t size = channel * width * height;
A.h_elements = new float [size];
// if (init_value != 0)
// for (int i = 0; i < size; i++)
// A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void init_kernel(kernel& A, int number, int channel, int width, int height, string filename){
A.number = number;
A.channel = channel;
A.width = width;
A.height = height;
size_t size = number * channel * width * height;
A.h_elements = new float [size];
// if (init_value != 0)
// for (int i = 0; i < size; i++)
// A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void fprint(feature data){
cout << "feature type \n[ " << data.channel << ", " << data.width << ", " << data.height << " ]" << endl;
for (int i = 0; i < data.channel; i++){
for (int j = 0; j < data.width; j++){
for (int k = 0; k < data.height; k++){
cout << setw(3) << data.h_elements[i * data.width*data.height + j * data.height + k];
}
cout << endl;
}
cout << endl;
}
}
void kprint(kernel data){
cout << "kernel type \n[ " << data.number << ", " << data.channel << ", " << data.width << ", " << data.height << " ]" << endl;
for (int i = 0; i < data.number; i++){
for (int j = 0; j < data.channel; j++){
for (int k = 0; k < data.width; k++){
for (int l = 0; l < data.height; l++){
cout << setw(3) << data.h_elements[i * data.channel*data.width*data.height + j * data.width*data.height + k * data.height + l];
}
cout << endl;
}
cout << endl;
}
cout << endl;
}
}
void make_pad(feature& A, int pad){
//invoke kernel padding
float* temp;
cudaMalloc(&temp, A.size);
cudaMemcpy(temp, A.d_elements, A.size, cudaMemcpyDeviceToDevice);
dim3 dimGrid(A.channel, A.width, A.height);
A.height += 2*pad; A.width += 2*pad;
A.size = A.channel * A.width * A.height * sizeof(float);
cudaFree(A.d_elements);
cudaMalloc(&A.d_elements, A.size);
cudaMemset(A.d_elements, 0, A.size);
paddingKernel<<<dimGrid, 1>>> (temp, A, pad);
cudaFree(temp);
}
void ReLU(feature& A){
//invoke kernel relu
dim3 dimGrid(A.channel, A.width, A.height);
ReLUKernel<<<dimGrid, 1>>>(A);
}
void convolution(feature& A, kernel B, int stride){
feature temp;
init_feature(temp, B.number, A.width - B.width + 1, A.height - B.height + 1, 0);
cudaMalloc(&temp.d_elements, temp.size);
dim3 dimGrid(temp.channel, temp.width, temp.height);
Conv2dKernel<<<dimGrid, A.channel, A.channel>>>(A, B, temp);
cudaFree(A.d_elements);
cudaMalloc(&A.d_elements, temp.size);
cudaMemcpy(A.d_elements, temp.d_elements, temp.size, cudaMemcpyDeviceToDevice);
delete temp.h_elements;
cudaFree(temp.d_elements);
A.channel = temp.channel;
A.width = temp.width;
A.height = temp.height;
}
void addBias(feature& A, kernel B){
dim3 dimGrid(A.channel, A.width, A.height);
AddBiasKernel<<<dimGrid, 1>>>(A, B);
}
void maxPooling(feature& A, int filter){
feature temp;
init_feature(temp, A.channel, A.width / filter, A.height / filter);
cudaMalloc(&temp.d_elements, temp.size);
dim3 dimGrid(temp.channel, temp.width, temp.height);
MaxpoolingKernel<<<dimGrid, 1>>>(A, temp, filter);
cudaFree(A.d_elements);
cudaMalloc(&A.d_elements, temp.size);
cudaMemcpy(A.d_elements, temp.d_elements, temp.size, cudaMemcpyDeviceToDevice);
delete temp.h_elements;
cudaFree(temp.d_elements);
A.channel = temp.channel;
A.width = temp.width;
A.height = temp.height;
}
void view(feature& A){
A.channel = A.channel*A.width*A.height;
A.width = 1;
A.height = 1;
} | #include <iostream>
#include <hip/hip_runtime.h>
#include <iomanip>
using namespace std;
struct feature {
int channel;
int width;
int height;
size_t size;
float* h_elements;
float* d_elements;
};
struct kernel {
int number;
int channel;
int width;
int height;
size_t size;
float* h_elements;
float* d_elements;
};
__global__ void Conv2dKernel(feature A, kernel B, feature C){
float Cvalue = 0;
int c = threadIdx.x;
int n = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
extern __shared__ float channels[];
channels[c] = 0;
for (int i = 0; i < B.width; i++){
for (int j = 0; j < B.height; j++){
int idxA = c * A.height * A.width + (w + i) * A.height + h + j;
int idxB = n * B.channel * B.width * B.height + c * B.width * B.height + i * B.width + j;
channels[c] += A.d_elements[idxA] * B.d_elements[idxB];
}
}
__syncthreads();
for (int i = 0; i < B.channel; i++)
Cvalue += channels[i];
__syncthreads();
C.d_elements[n * gridDim.y * gridDim.z + w * gridDim.z + h] = Cvalue;
}
__global__ void AddBiasKernel(feature A, kernel B){
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
int idxA = c * A.width*A.height + w * A.height + h;
A.d_elements[idxA] += B.d_elements[c];
}
__global__ void paddingKernel(float* A, feature B, int padding){
// A is original array, B is padded array
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
int idxA = c * gridDim.y*gridDim.z + w * gridDim.z + h;
int idxB = c * B.width*B.height + (w + padding) * B.height + (h + padding);
B.d_elements[idxB] = A[idxA];
}
__global__ void ReLUKernel(feature A){
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
int idxA = c * A.width*A.height + w * A.height + h;
if (A.d_elements[idxA] < 0)
A.d_elements[idxA] = 0;
}
__global__ void MaxpoolingKernel(feature A, feature B, int filter){
// A is input B is output
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
float max_value = A.d_elements[c * A.width*A.height + w*filter * A.height + h*filter];
for (int i = 0; i < filter; i++){
for (int j = 0; j < filter; j++){
int idxA = c * A.height * A.width + (w*filter + i) * A.height + h*filter + j;
if (max_value < A.d_elements[idxA])
max_value = A.d_elements[idxA];
}
}
int idxB = c * gridDim.y * gridDim.z + w * gridDim.z + h;
B.d_elements[idxB] = max_value;
}
void init_feature(feature& A, int channel, int width, int height, float init_value = 0);
void init_kernel(kernel& A, int number, int channel, int width, int height, float init_value = 0);
void init_feature(feature& A, int channel, int width, int height, string filename);
void init_kernel(kernel& A, int number, int channel, int width, int height, string filename);
void fprint(feature data);
void kprint(kernel data);
void make_pad(feature& A, int pad);
void ReLU(feature& A);
void convolution(feature& A, kernel B, int stride);
void addBias(feature& A, kernel B);
void maxPooling(feature& A, int filter);
void view(feature& A);
int main()
{
//feature A initialization
feature A;
init_feature(A, 3, 8, 8, 1);
hipMalloc(&A.d_elements, A.size);
hipMemcpy(A.d_elements, A.h_elements, A.size, hipMemcpyHostToDevice);
fprint(A);
//kernel B initialization
kernel B;
init_kernel(B, 3, 3, 3, 3, 1);
hipMalloc(&B.d_elements, B.size);
hipMemcpy(B.d_elements, B.h_elements, B.size, hipMemcpyHostToDevice);
kprint(B);
//kernel C initialization
kernel C;
init_kernel(C, 3, 1, 1, 1, 1);
hipMalloc(&C.d_elements, C.size);
hipMemcpy(C.d_elements, C.h_elements, C.size, hipMemcpyHostToDevice);
kprint(C);
//calculation
make_pad(A, 1);
convolution(A, B, 1);
addBias(A,C);
ReLU(A);
maxPooling(A, 2);
view(A);
//receive data from device
delete A.h_elements;
A.size = A.channel * A.width * A.height * sizeof(float);
A.h_elements = new float [A.size];
hipMemcpy(A.h_elements, A.d_elements, A.size, hipMemcpyDeviceToHost);
//print data
fprint(A);
//release all cuda memories
hipFree(A.d_elements);
hipFree(B.d_elements);
hipFree(C.d_elements);
return 0;
}
void init_feature(feature& A, int channel, int width, int height, float init_value){
A.channel = channel;
A.width = width;
A.height = height;
size_t size = channel * width * height;
A.h_elements = new float [size];
if (init_value != 0)
for (int i = 0; i < size; i++)
A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void init_kernel(kernel& A, int number, int channel, int width, int height, float init_value){
A.number = number;
A.channel = channel;
A.width = width;
A.height = height;
size_t size = number * channel * width * height;
A.h_elements = new float [size];
if (init_value != 0)
for (int i = 0; i < size; i++)
A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void init_feature(feature& A, int channel, int width, int height, string filename){
A.channel = channel;
A.width = width;
A.height = height;
size_t size = channel * width * height;
A.h_elements = new float [size];
// if (init_value != 0)
// for (int i = 0; i < size; i++)
// A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void init_kernel(kernel& A, int number, int channel, int width, int height, string filename){
A.number = number;
A.channel = channel;
A.width = width;
A.height = height;
size_t size = number * channel * width * height;
A.h_elements = new float [size];
// if (init_value != 0)
// for (int i = 0; i < size; i++)
// A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void fprint(feature data){
cout << "feature type \n[ " << data.channel << ", " << data.width << ", " << data.height << " ]" << endl;
for (int i = 0; i < data.channel; i++){
for (int j = 0; j < data.width; j++){
for (int k = 0; k < data.height; k++){
cout << setw(3) << data.h_elements[i * data.width*data.height + j * data.height + k];
}
cout << endl;
}
cout << endl;
}
}
void kprint(kernel data){
cout << "kernel type \n[ " << data.number << ", " << data.channel << ", " << data.width << ", " << data.height << " ]" << endl;
for (int i = 0; i < data.number; i++){
for (int j = 0; j < data.channel; j++){
for (int k = 0; k < data.width; k++){
for (int l = 0; l < data.height; l++){
cout << setw(3) << data.h_elements[i * data.channel*data.width*data.height + j * data.width*data.height + k * data.height + l];
}
cout << endl;
}
cout << endl;
}
cout << endl;
}
}
void make_pad(feature& A, int pad){
//invoke kernel padding
float* temp;
hipMalloc(&temp, A.size);
hipMemcpy(temp, A.d_elements, A.size, hipMemcpyDeviceToDevice);
dim3 dimGrid(A.channel, A.width, A.height);
A.height += 2*pad; A.width += 2*pad;
A.size = A.channel * A.width * A.height * sizeof(float);
hipFree(A.d_elements);
hipMalloc(&A.d_elements, A.size);
hipMemset(A.d_elements, 0, A.size);
paddingKernel<<<dimGrid, 1>>> (temp, A, pad);
hipFree(temp);
}
void ReLU(feature& A){
//invoke kernel relu
dim3 dimGrid(A.channel, A.width, A.height);
ReLUKernel<<<dimGrid, 1>>>(A);
}
void convolution(feature& A, kernel B, int stride){
feature temp;
init_feature(temp, B.number, A.width - B.width + 1, A.height - B.height + 1, 0);
hipMalloc(&temp.d_elements, temp.size);
dim3 dimGrid(temp.channel, temp.width, temp.height);
Conv2dKernel<<<dimGrid, A.channel, A.channel>>>(A, B, temp);
hipFree(A.d_elements);
hipMalloc(&A.d_elements, temp.size);
hipMemcpy(A.d_elements, temp.d_elements, temp.size, hipMemcpyDeviceToDevice);
delete temp.h_elements;
hipFree(temp.d_elements);
A.channel = temp.channel;
A.width = temp.width;
A.height = temp.height;
}
void addBias(feature& A, kernel B){
dim3 dimGrid(A.channel, A.width, A.height);
AddBiasKernel<<<dimGrid, 1>>>(A, B);
}
void maxPooling(feature& A, int filter){
feature temp;
init_feature(temp, A.channel, A.width / filter, A.height / filter);
hipMalloc(&temp.d_elements, temp.size);
dim3 dimGrid(temp.channel, temp.width, temp.height);
MaxpoolingKernel<<<dimGrid, 1>>>(A, temp, filter);
hipFree(A.d_elements);
hipMalloc(&A.d_elements, temp.size);
hipMemcpy(A.d_elements, temp.d_elements, temp.size, hipMemcpyDeviceToDevice);
delete temp.h_elements;
hipFree(temp.d_elements);
A.channel = temp.channel;
A.width = temp.width;
A.height = temp.height;
}
void view(feature& A){
A.channel = A.channel*A.width*A.height;
A.width = 1;
A.height = 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include <iomanip>
using namespace std;
struct feature {
int channel;
int width;
int height;
size_t size;
float* h_elements;
float* d_elements;
};
struct kernel {
int number;
int channel;
int width;
int height;
size_t size;
float* h_elements;
float* d_elements;
};
__global__ void Conv2dKernel(feature A, kernel B, feature C){
float Cvalue = 0;
int c = threadIdx.x;
int n = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
extern __shared__ float channels[];
channels[c] = 0;
for (int i = 0; i < B.width; i++){
for (int j = 0; j < B.height; j++){
int idxA = c * A.height * A.width + (w + i) * A.height + h + j;
int idxB = n * B.channel * B.width * B.height + c * B.width * B.height + i * B.width + j;
channels[c] += A.d_elements[idxA] * B.d_elements[idxB];
}
}
__syncthreads();
for (int i = 0; i < B.channel; i++)
Cvalue += channels[i];
__syncthreads();
C.d_elements[n * gridDim.y * gridDim.z + w * gridDim.z + h] = Cvalue;
}
__global__ void AddBiasKernel(feature A, kernel B){
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
int idxA = c * A.width*A.height + w * A.height + h;
A.d_elements[idxA] += B.d_elements[c];
}
__global__ void paddingKernel(float* A, feature B, int padding){
// A is original array, B is padded array
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
int idxA = c * gridDim.y*gridDim.z + w * gridDim.z + h;
int idxB = c * B.width*B.height + (w + padding) * B.height + (h + padding);
B.d_elements[idxB] = A[idxA];
}
__global__ void ReLUKernel(feature A){
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
int idxA = c * A.width*A.height + w * A.height + h;
if (A.d_elements[idxA] < 0)
A.d_elements[idxA] = 0;
}
__global__ void MaxpoolingKernel(feature A, feature B, int filter){
// A is input B is output
int c = blockIdx.x;
int w = blockIdx.y;
int h = blockIdx.z;
float max_value = A.d_elements[c * A.width*A.height + w*filter * A.height + h*filter];
for (int i = 0; i < filter; i++){
for (int j = 0; j < filter; j++){
int idxA = c * A.height * A.width + (w*filter + i) * A.height + h*filter + j;
if (max_value < A.d_elements[idxA])
max_value = A.d_elements[idxA];
}
}
int idxB = c * gridDim.y * gridDim.z + w * gridDim.z + h;
B.d_elements[idxB] = max_value;
}
void init_feature(feature& A, int channel, int width, int height, float init_value = 0);
void init_kernel(kernel& A, int number, int channel, int width, int height, float init_value = 0);
void init_feature(feature& A, int channel, int width, int height, string filename);
void init_kernel(kernel& A, int number, int channel, int width, int height, string filename);
void fprint(feature data);
void kprint(kernel data);
void make_pad(feature& A, int pad);
void ReLU(feature& A);
void convolution(feature& A, kernel B, int stride);
void addBias(feature& A, kernel B);
void maxPooling(feature& A, int filter);
void view(feature& A);
int main()
{
//feature A initialization
feature A;
init_feature(A, 3, 8, 8, 1);
hipMalloc(&A.d_elements, A.size);
hipMemcpy(A.d_elements, A.h_elements, A.size, hipMemcpyHostToDevice);
fprint(A);
//kernel B initialization
kernel B;
init_kernel(B, 3, 3, 3, 3, 1);
hipMalloc(&B.d_elements, B.size);
hipMemcpy(B.d_elements, B.h_elements, B.size, hipMemcpyHostToDevice);
kprint(B);
//kernel C initialization
kernel C;
init_kernel(C, 3, 1, 1, 1, 1);
hipMalloc(&C.d_elements, C.size);
hipMemcpy(C.d_elements, C.h_elements, C.size, hipMemcpyHostToDevice);
kprint(C);
//calculation
make_pad(A, 1);
convolution(A, B, 1);
addBias(A,C);
ReLU(A);
maxPooling(A, 2);
view(A);
//receive data from device
delete A.h_elements;
A.size = A.channel * A.width * A.height * sizeof(float);
A.h_elements = new float [A.size];
hipMemcpy(A.h_elements, A.d_elements, A.size, hipMemcpyDeviceToHost);
//print data
fprint(A);
//release all cuda memories
hipFree(A.d_elements);
hipFree(B.d_elements);
hipFree(C.d_elements);
return 0;
}
void init_feature(feature& A, int channel, int width, int height, float init_value){
A.channel = channel;
A.width = width;
A.height = height;
size_t size = channel * width * height;
A.h_elements = new float [size];
if (init_value != 0)
for (int i = 0; i < size; i++)
A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void init_kernel(kernel& A, int number, int channel, int width, int height, float init_value){
A.number = number;
A.channel = channel;
A.width = width;
A.height = height;
size_t size = number * channel * width * height;
A.h_elements = new float [size];
if (init_value != 0)
for (int i = 0; i < size; i++)
A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void init_feature(feature& A, int channel, int width, int height, string filename){
A.channel = channel;
A.width = width;
A.height = height;
size_t size = channel * width * height;
A.h_elements = new float [size];
// if (init_value != 0)
// for (int i = 0; i < size; i++)
// A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void init_kernel(kernel& A, int number, int channel, int width, int height, string filename){
A.number = number;
A.channel = channel;
A.width = width;
A.height = height;
size_t size = number * channel * width * height;
A.h_elements = new float [size];
// if (init_value != 0)
// for (int i = 0; i < size; i++)
// A.h_elements[i] = init_value;
A.size = size*sizeof(float);
}
void fprint(feature data){
cout << "feature type \n[ " << data.channel << ", " << data.width << ", " << data.height << " ]" << endl;
for (int i = 0; i < data.channel; i++){
for (int j = 0; j < data.width; j++){
for (int k = 0; k < data.height; k++){
cout << setw(3) << data.h_elements[i * data.width*data.height + j * data.height + k];
}
cout << endl;
}
cout << endl;
}
}
void kprint(kernel data){
cout << "kernel type \n[ " << data.number << ", " << data.channel << ", " << data.width << ", " << data.height << " ]" << endl;
for (int i = 0; i < data.number; i++){
for (int j = 0; j < data.channel; j++){
for (int k = 0; k < data.width; k++){
for (int l = 0; l < data.height; l++){
cout << setw(3) << data.h_elements[i * data.channel*data.width*data.height + j * data.width*data.height + k * data.height + l];
}
cout << endl;
}
cout << endl;
}
cout << endl;
}
}
void make_pad(feature& A, int pad){
//invoke kernel padding
float* temp;
hipMalloc(&temp, A.size);
hipMemcpy(temp, A.d_elements, A.size, hipMemcpyDeviceToDevice);
dim3 dimGrid(A.channel, A.width, A.height);
A.height += 2*pad; A.width += 2*pad;
A.size = A.channel * A.width * A.height * sizeof(float);
hipFree(A.d_elements);
hipMalloc(&A.d_elements, A.size);
hipMemset(A.d_elements, 0, A.size);
paddingKernel<<<dimGrid, 1>>> (temp, A, pad);
hipFree(temp);
}
void ReLU(feature& A){
//invoke kernel relu
dim3 dimGrid(A.channel, A.width, A.height);
ReLUKernel<<<dimGrid, 1>>>(A);
}
void convolution(feature& A, kernel B, int stride){
feature temp;
init_feature(temp, B.number, A.width - B.width + 1, A.height - B.height + 1, 0);
hipMalloc(&temp.d_elements, temp.size);
dim3 dimGrid(temp.channel, temp.width, temp.height);
Conv2dKernel<<<dimGrid, A.channel, A.channel>>>(A, B, temp);
hipFree(A.d_elements);
hipMalloc(&A.d_elements, temp.size);
hipMemcpy(A.d_elements, temp.d_elements, temp.size, hipMemcpyDeviceToDevice);
delete temp.h_elements;
hipFree(temp.d_elements);
A.channel = temp.channel;
A.width = temp.width;
A.height = temp.height;
}
void addBias(feature& A, kernel B){
dim3 dimGrid(A.channel, A.width, A.height);
AddBiasKernel<<<dimGrid, 1>>>(A, B);
}
void maxPooling(feature& A, int filter){
feature temp;
init_feature(temp, A.channel, A.width / filter, A.height / filter);
hipMalloc(&temp.d_elements, temp.size);
dim3 dimGrid(temp.channel, temp.width, temp.height);
MaxpoolingKernel<<<dimGrid, 1>>>(A, temp, filter);
hipFree(A.d_elements);
hipMalloc(&A.d_elements, temp.size);
hipMemcpy(A.d_elements, temp.d_elements, temp.size, hipMemcpyDeviceToDevice);
delete temp.h_elements;
hipFree(temp.d_elements);
A.channel = temp.channel;
A.width = temp.width;
A.height = temp.height;
}
void view(feature& A){
A.channel = A.channel*A.width*A.height;
A.width = 1;
A.height = 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12Conv2dKernel7feature6kernelS_
.globl _Z12Conv2dKernel7feature6kernelS_
.p2align 8
.type _Z12Conv2dKernel7feature6kernelS_,@function
_Z12Conv2dKernel7feature6kernelS_:
s_load_b64 s[6:7], s[0:1], 0x2c
v_lshl_add_u32 v6, v0, 2, 0
v_mov_b32_e32 v5, 0
s_add_u32 s10, s0, 40
s_addc_u32 s11, s1, 0
s_mov_b32 s4, s15
s_mov_b32 s5, 0
ds_store_b32 v6, v5
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x4
s_load_b32 s12, s[10:11], 0xc
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b64 s[10:11], s[10:11], 0x20
v_mad_u64_u32 v[1:2], null, s6, s13, v[0:1]
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s2, v0, s[14:15]
s_mul_i32 s2, s12, s7
s_cmp_gt_i32 s12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v7, s2, v1
s_cselect_b32 s2, -1, 0
v_cndmask_b32_e64 v3, 0, 1, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s3, v2, s[4:5]
v_cmp_ne_u32_e64 s2, 1, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v7, s7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v0, s3, v0
s_add_i32 s5, s5, 1
s_cmp_eq_u32 s5, s7
s_cbranch_scc1 .LBB0_7
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_2
ds_load_b32 v8, v6
v_mov_b32_e32 v1, v0
v_mov_b32_e32 v3, v7
s_mov_b32 s15, s12
.p2align 6
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s15, s15, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s15, 0
v_lshlrev_b64 v[9:10], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[3:4]
v_add_nc_u32_e32 v1, 1, v1
v_add_co_u32 v9, vcc_lo, s8, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s10, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v12, vcc_lo
global_load_b32 v2, v[9:10], off
global_load_b32 v4, v[11:12], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_fmac_f32 v8, v2, v4 :: v_dual_add_nc_u32 v3, 1, v3
s_cbranch_scc0 .LBB0_5
ds_store_b32 v6, v8
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[2:3], s[0:1], 0x70
s_cmp_lt_i32 s6, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_10
v_mov_b32_e32 v5, 0
s_mov_b32 s5, 0
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v0, s5
s_add_i32 s6, s6, -1
s_add_i32 s5, s5, 4
s_cmp_eq_u32 s6, 0
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v0
s_cbranch_scc0 .LBB0_9
.LBB0_10:
s_barrier
buffer_gl0_inv
s_load_b64 s[0:1], s[0:1], 0x7c
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s0, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_mul_i32 s0, s0, s1
s_mov_b32 s1, 0
s_add_i32 s0, s0, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
global_store_b32 v0, v5, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12Conv2dKernel7feature6kernelS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 376
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12Conv2dKernel7feature6kernelS_, .Lfunc_end0-_Z12Conv2dKernel7feature6kernelS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13AddBiasKernel7feature6kernel
.globl _Z13AddBiasKernel7feature6kernel
.p2align 8
.type _Z13AddBiasKernel7feature6kernel,@function
_Z13AddBiasKernel7feature6kernel:
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x4
s_load_b64 s[6:7], s[0:1], 0x48
s_load_b64 s[0:1], s[0:1], 0x20
s_mov_b32 s2, s13
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s4, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s3, s14
s_ashr_i32 s3, s13, 31
s_mul_i32 s4, s4, s5
s_lshl_b64 s[2:3], s[2:3], 2
s_add_i32 s4, s4, s15
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v1, s2, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13AddBiasKernel7feature6kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 80
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13AddBiasKernel7feature6kernel, .Lfunc_end1-_Z13AddBiasKernel7feature6kernel
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13paddingKernelPf7featurei
.globl _Z13paddingKernelPf7featurei
.p2align 8
.type _Z13paddingKernelPf7featurei,@function
_Z13paddingKernelPf7featurei:
s_clause 0x4
s_load_b64 s[2:3], s[0:1], 0x3c
s_load_b64 s[4:5], s[0:1], 0xc
s_load_b32 s8, s[0:1], 0x30
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s13
s_mul_i32 s4, s4, s13
s_add_i32 s2, s2, s14
s_add_i32 s9, s14, s8
s_mul_i32 s2, s2, s3
s_add_i32 s3, s9, s4
s_add_i32 s2, s2, s15
s_mul_i32 s4, s3, s5
s_ashr_i32 s3, s2, 31
s_add_i32 s5, s15, s8
s_lshl_b64 s[2:3], s[2:3], 2
s_add_i32 s4, s5, s4
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_ashr_i32 s5, s4, 31
s_load_b32 s6, s[2:3], 0x0
s_lshl_b64 s[2:3], s[4:5], 2
v_mov_b32_e32 v0, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s6
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13paddingKernelPf7featurei
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13paddingKernelPf7featurei, .Lfunc_end2-_Z13paddingKernelPf7featurei
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10ReLUKernel7feature
.globl _Z10ReLUKernel7feature
.p2align 8
.type _Z10ReLUKernel7feature,@function
_Z10ReLUKernel7feature:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x4
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_mul_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s15
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_nlt_f32_e64 s2, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB3_2
v_mov_b32_e32 v0, 0
global_store_b32 v0, v0, s[0:1]
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10ReLUKernel7feature
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z10ReLUKernel7feature, .Lfunc_end3-_Z10ReLUKernel7feature
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16MaxpoolingKernel7featureS_i
.globl _Z16MaxpoolingKernel7featureS_i
.p2align 8
.type _Z16MaxpoolingKernel7featureS_i,@function
_Z16MaxpoolingKernel7featureS_i:
s_clause 0x3
s_load_b64 s[4:5], s[0:1], 0x4
s_load_b32 s10, s[0:1], 0x50
s_load_b64 s[6:7], s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x48
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s13
s_mul_i32 s8, s14, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s4, s8
s_mul_i32 s8, s15, s10
s_mul_i32 s4, s4, s5
s_add_i32 s8, s4, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[16:17], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s6, s16
s_addc_u32 s17, s7, s17
s_cmp_lt_i32 s10, 1
s_load_b32 s4, s[16:17], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s4
s_cbranch_scc1 .LBB4_5
s_mov_b32 s4, 0
.p2align 6
.LBB4_2:
s_mov_b32 s9, 0
.LBB4_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s16, s8, s9
s_ashr_i32 s17, s16, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[16:17], 2
s_add_u32 s16, s6, s16
s_addc_u32 s17, s7, s17
s_add_i32 s9, s9, 1
s_load_b32 s11, s[16:17], 0x0
s_cmp_eq_u32 s10, s9
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, s11, v0
v_cndmask_b32_e64 v0, v0, s11, vcc_lo
s_cbranch_scc0 .LBB4_3
s_add_i32 s4, s4, 1
s_add_i32 s8, s8, s5
s_cmp_eq_u32 s4, s10
s_cbranch_scc0 .LBB4_2
.LBB4_5:
s_load_b64 s[0:1], s[0:1], 0x5c
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s0, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_mul_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s15
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16MaxpoolingKernel7featureS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z16MaxpoolingKernel7featureS_i, .Lfunc_end4-_Z16MaxpoolingKernel7featureS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 40
.value_kind: by_value
- .offset: 40
.size: 40
.value_kind: by_value
- .offset: 80
.size: 40
.value_kind: by_value
- .offset: 120
.size: 4
.value_kind: hidden_block_count_x
- .offset: 124
.size: 4
.value_kind: hidden_block_count_y
- .offset: 128
.size: 4
.value_kind: hidden_block_count_z
- .offset: 132
.size: 2
.value_kind: hidden_group_size_x
- .offset: 134
.size: 2
.value_kind: hidden_group_size_y
- .offset: 136
.size: 2
.value_kind: hidden_group_size_z
- .offset: 138
.size: 2
.value_kind: hidden_remainder_x
- .offset: 140
.size: 2
.value_kind: hidden_remainder_y
- .offset: 142
.size: 2
.value_kind: hidden_remainder_z
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 168
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 176
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 184
.size: 2
.value_kind: hidden_grid_dims
- .offset: 240
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 376
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12Conv2dKernel7feature6kernelS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12Conv2dKernel7feature6kernelS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 40
.value_kind: by_value
- .offset: 40
.size: 40
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 80
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13AddBiasKernel7feature6kernel
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z13AddBiasKernel7feature6kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 40
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13paddingKernelPf7featurei
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z13paddingKernelPf7featurei.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 40
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10ReLUKernel7feature
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10ReLUKernel7feature.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 1
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 40
.value_kind: by_value
- .offset: 40
.size: 40
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16MaxpoolingKernel7featureS_i
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z16MaxpoolingKernel7featureS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by heidies on 7/5/18.
//
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
int main(int argc, char **argv){
cout << "Starting... " << endl;
int deviceCount = 0;
cudaError_t error_id = cudaGetDeviceCount(&deviceCount);
if (error_id != cudaSuccess){
cout << "cudaGetDeviceCount returned " << int(error_id) << endl;
cout << "-> " <<cudaGetErrorString(error_id) << endl;
cout << "Result = FAIL" << endl;
//exit(EXIT_FAILURE);
}
if (deviceCount == 0){
cout << "There is no available device that support CUDA" << endl;
}
else{
cout << "Deteced " << deviceCount <<" CUDA Capable device(s)" << endl;
}
int dev, driverVersion = 0, runtimeVersion = 0;
dev = 0;
cudaSetDevice(dev);
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
cout << "Device " << dev << "\"" << deviceProp.name << "\"" << endl;
cudaDriverGetVersion(&driverVersion);
cudaRuntimeGetVersion(&runtimeVersion);
cout << " CUDA Driver Version / Runtime Version " << driverVersion / 1000 << "." << (driverVersion %100) / 10 << "/" <<
runtimeVersion / 1000 << "." << (runtimeVersion%100) / 10 << endl;
cout << " CUDA Capability Major/Minor version number: " << deviceProp.major << "." << deviceProp.minor << endl;
cout << " Total amount of global memory: " << (float)deviceProp.totalGlobalMem/(pow(1024.0, 3)) << " GBytes" <<
"(" << (unsigned long long) deviceProp.totalGlobalMem << " bytes)" << endl;
cout << " GPU Clock rate: " << deviceProp.clockRate * 1e-3f << " MHz" << "(" <<
deviceProp.clockRate * 1e-6f << " GHz)" << endl;
cout << " Memory Clock rate: " << deviceProp.memoryClockRate * 1e-3f << " Mhz" << endl;
cout << " Memory Bus Width: " << deviceProp.memoryBusWidth << "-bit" << endl;
if (deviceProp.l2CacheSize)
cout << " L2 Cache Size: " << deviceProp.l2CacheSize << " bytes" << endl;
cout << " Max Texture Dimension Size (x, y, z) 1D=(" << deviceProp.maxTexture1D << "), " << "2D=(" <<
deviceProp.maxTexture2D[0] << ", " << deviceProp.maxTexture2D[1] << "), " << "3D=(" << deviceProp.maxTexture3D[0] << ", " <<
deviceProp.maxTexture3D[1] << ", " << deviceProp.maxTexture3D[2] << ")" << endl;
cout << " Max Layered Texture Size (dim) x layers 1D=(" << deviceProp.maxTexture1DLayered[0] << ") x " <<
deviceProp.maxTexture1DLayered[1] << "2D=(" << deviceProp.maxTexture2DLayered[0] << ", " << deviceProp.maxTexture2DLayered[1] << ") x " <<
deviceProp.maxTexture2DLayered[2] << endl;
cout << " Total amount of constant memory: " << deviceProp.totalConstMem << " bytes" << endl;
cout << " Total amount of shared memory per block: " << deviceProp.sharedMemPerBlock << " bytes" << endl;
cout << " Total number of registers available per block: " << deviceProp.regsPerBlock << endl;
cout << " Warp size: " << deviceProp.warpSize << endl;
cout << " Number of multiprocessors: " << deviceProp.multiProcessorCount << endl;
cout << " Maximum number of warps per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor / 32 << endl;
cout << " Maximum number of threads per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor << endl;
cout << " Maximum number of threads per block: " << deviceProp.maxThreadsPerBlock << endl;
cout << " Maximum sizes of each dimension of a block: " << deviceProp.maxThreadsDim[0] << " x " <<
deviceProp.maxThreadsDim[1] << " x " << deviceProp.maxThreadsDim[2] << endl;
cout << " Maximum sizes of each dimension of a grid: " << deviceProp.maxGridSize[0] << " x " <<
deviceProp.maxGridSize[1] << " x " << deviceProp.maxGridSize[2] << endl;
cout << " Maximum memory pitch: " << deviceProp.memPitch << " bytes" << endl;
exit(EXIT_SUCCESS);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by heidies on 7/5/18.
//
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
int main(int argc, char **argv){
cout << "Starting... " << endl;
int deviceCount = 0;
cudaError_t error_id = cudaGetDeviceCount(&deviceCount);
if (error_id != cudaSuccess){
cout << "cudaGetDeviceCount returned " << int(error_id) << endl;
cout << "-> " <<cudaGetErrorString(error_id) << endl;
cout << "Result = FAIL" << endl;
//exit(EXIT_FAILURE);
}
if (deviceCount == 0){
cout << "There is no available device that support CUDA" << endl;
}
else{
cout << "Deteced " << deviceCount <<" CUDA Capable device(s)" << endl;
}
int dev, driverVersion = 0, runtimeVersion = 0;
dev = 0;
cudaSetDevice(dev);
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
cout << "Device " << dev << "\"" << deviceProp.name << "\"" << endl;
cudaDriverGetVersion(&driverVersion);
cudaRuntimeGetVersion(&runtimeVersion);
cout << " CUDA Driver Version / Runtime Version " << driverVersion / 1000 << "." << (driverVersion %100) / 10 << "/" <<
runtimeVersion / 1000 << "." << (runtimeVersion%100) / 10 << endl;
cout << " CUDA Capability Major/Minor version number: " << deviceProp.major << "." << deviceProp.minor << endl;
cout << " Total amount of global memory: " << (float)deviceProp.totalGlobalMem/(pow(1024.0, 3)) << " GBytes" <<
"(" << (unsigned long long) deviceProp.totalGlobalMem << " bytes)" << endl;
cout << " GPU Clock rate: " << deviceProp.clockRate * 1e-3f << " MHz" << "(" <<
deviceProp.clockRate * 1e-6f << " GHz)" << endl;
cout << " Memory Clock rate: " << deviceProp.memoryClockRate * 1e-3f << " Mhz" << endl;
cout << " Memory Bus Width: " << deviceProp.memoryBusWidth << "-bit" << endl;
if (deviceProp.l2CacheSize)
cout << " L2 Cache Size: " << deviceProp.l2CacheSize << " bytes" << endl;
cout << " Max Texture Dimension Size (x, y, z) 1D=(" << deviceProp.maxTexture1D << "), " << "2D=(" <<
deviceProp.maxTexture2D[0] << ", " << deviceProp.maxTexture2D[1] << "), " << "3D=(" << deviceProp.maxTexture3D[0] << ", " <<
deviceProp.maxTexture3D[1] << ", " << deviceProp.maxTexture3D[2] << ")" << endl;
cout << " Max Layered Texture Size (dim) x layers 1D=(" << deviceProp.maxTexture1DLayered[0] << ") x " <<
deviceProp.maxTexture1DLayered[1] << "2D=(" << deviceProp.maxTexture2DLayered[0] << ", " << deviceProp.maxTexture2DLayered[1] << ") x " <<
deviceProp.maxTexture2DLayered[2] << endl;
cout << " Total amount of constant memory: " << deviceProp.totalConstMem << " bytes" << endl;
cout << " Total amount of shared memory per block: " << deviceProp.sharedMemPerBlock << " bytes" << endl;
cout << " Total number of registers available per block: " << deviceProp.regsPerBlock << endl;
cout << " Warp size: " << deviceProp.warpSize << endl;
cout << " Number of multiprocessors: " << deviceProp.multiProcessorCount << endl;
cout << " Maximum number of warps per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor / 32 << endl;
cout << " Maximum number of threads per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor << endl;
cout << " Maximum number of threads per block: " << deviceProp.maxThreadsPerBlock << endl;
cout << " Maximum sizes of each dimension of a block: " << deviceProp.maxThreadsDim[0] << " x " <<
deviceProp.maxThreadsDim[1] << " x " << deviceProp.maxThreadsDim[2] << endl;
cout << " Maximum sizes of each dimension of a grid: " << deviceProp.maxGridSize[0] << " x " <<
deviceProp.maxGridSize[1] << " x " << deviceProp.maxGridSize[2] << endl;
cout << " Maximum memory pitch: " << deviceProp.memPitch << " bytes" << endl;
exit(EXIT_SUCCESS);
} | .file "tmpxft_000862ea_00000000-6_checkDeviceInfor.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Starting... "
.LC1:
.string "cudaGetDeviceCount returned "
.LC2:
.string "-> "
.LC3:
.string "Result = FAIL"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "There is no available device that support CUDA"
.section .rodata.str1.1
.LC5:
.string "Deteced "
.LC6:
.string " CUDA Capable device(s)"
.LC7:
.string "Device "
.LC8:
.string "\""
.section .rodata.str1.8
.align 8
.LC9:
.string " CUDA Driver Version / Runtime Version "
.section .rodata.str1.1
.LC10:
.string "."
.LC11:
.string "/"
.section .rodata.str1.8
.align 8
.LC12:
.string " CUDA Capability Major/Minor version number: "
.align 8
.LC13:
.string " Total amount of global memory: "
.section .rodata.str1.1
.LC15:
.string " GBytes"
.LC16:
.string "("
.LC17:
.string " bytes)"
.section .rodata.str1.8
.align 8
.LC18:
.string " GPU Clock rate: "
.section .rodata.str1.1
.LC20:
.string " MHz"
.LC22:
.string " GHz)"
.section .rodata.str1.8
.align 8
.LC23:
.string " Memory Clock rate: "
.section .rodata.str1.1
.LC24:
.string " Mhz"
.section .rodata.str1.8
.align 8
.LC25:
.string " Memory Bus Width: "
.section .rodata.str1.1
.LC26:
.string "-bit"
.section .rodata.str1.8
.align 8
.LC27:
.string " L2 Cache Size: "
.section .rodata.str1.1
.LC28:
.string " bytes"
.section .rodata.str1.8
.align 8
.LC29:
.string " Max Texture Dimension Size (x, y, z) 1D=("
.section .rodata.str1.1
.LC30:
.string "), "
.LC31:
.string "2D=("
.LC32:
.string ", "
.LC33:
.string "3D=("
.LC34:
.string ")"
.section .rodata.str1.8
.align 8
.LC35:
.string " Max Layered Texture Size (dim) x layers 1D=("
.section .rodata.str1.1
.LC36:
.string ") x "
.section .rodata.str1.8
.align 8
.LC37:
.string " Total amount of constant memory: "
.align 8
.LC38:
.string " Total amount of shared memory per block: "
.align 8
.LC39:
.string " Total number of registers available per block: "
.align 8
.LC40:
.string " Warp size: "
.align 8
.LC41:
.string " Number of multiprocessors: "
.align 8
.LC42:
.string " Maximum number of warps per multiprocessor: "
.align 8
.LC43:
.string " Maximum number of threads per multiprocessor: "
.align 8
.LC44:
.string " Maximum number of threads per block: "
.align 8
.LC45:
.string " Maximum sizes of each dimension of a block: "
.section .rodata.str1.1
.LC46:
.string " x "
.section .rodata.str1.8
.align 8
.LC47:
.string " Maximum sizes of each dimension of a grid: "
.align 8
.LC48:
.string " Maximum memory pitch: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1064, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L12
.L4:
cmpl $0, 4(%rsp)
jne .L5
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L6:
movl $0, 8(%rsp)
movl $0, 12(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %r12
movl $0, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $0, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 8(%rsp), %rdi
call cudaDriverGetVersion@PLT
leaq 12(%rsp), %rdi
call cudaRuntimeGetVersion@PLT
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %edx
movslq %edx, %rsi
imulq $274877907, %rsi, %rsi
sarq $38, %rsi
sarl $31, %edx
subl %edx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %edx
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $100, %eax, %eax
subl %eax, %edx
movslq %edx, %rsi
imulq $1717986919, %rsi, %rsi
sarq $34, %rsi
sarl $31, %edx
subl %edx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %edx
movslq %edx, %rsi
imulq $274877907, %rsi, %rsi
sarq $38, %rsi
sarl $31, %edx
subl %edx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %edx
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $100, %eax, %eax
subl %eax, %edx
movslq %edx, %rsi
imulq $1717986919, %rsi, %rsi
sarq $34, %rsi
sarl $31, %edx
subl %edx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC12(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 376(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 380(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 304(%rsp), %rdx
testq %rdx, %rdx
js .L7
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
.L8:
cvtss2sd %xmm0, %xmm0
mulsd .LC14(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC15(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 304(%rsp), %rsi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
mulss .LC19(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC20(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
mulss .LC21(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC22(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC23(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssl 624(%rsp), %xmm0
mulss .LC19(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC24(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC25(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 628(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC26(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 632(%rsp)
jne .L13
.L9:
leaq .LC29(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 424(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC30(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC31(%rip), %r13
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 436(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC32(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 440(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC33(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 472(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 476(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 480(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC34(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC35(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 500(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC36(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 504(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 508(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 512(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 516(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC37(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 368(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC28(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC38(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 312(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC39(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 320(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC40(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 324(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC41(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 404(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC42(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 640(%rsp), %eax
leal 31(%rax), %esi
testl %eax, %eax
cmovns %eax, %esi
sarl $5, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC43(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 640(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC44(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 336(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC45(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 340(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC46(%rip), %rbp
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 344(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 348(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC47(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 352(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 356(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 360(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC48(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 328(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %edi
call exit@PLT
.L12:
movl %eax, %ebx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r12
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L4
.L5:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 4(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L6
.L7:
movq %rdx, %rax
shrq %rax
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L8
.L13:
leaq .LC27(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 632(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC28(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L9
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC14:
.long 0
.long 1041235968
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC19:
.long 981668463
.align 4
.LC21:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by heidies on 7/5/18.
//
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
int main(int argc, char **argv){
cout << "Starting... " << endl;
int deviceCount = 0;
cudaError_t error_id = cudaGetDeviceCount(&deviceCount);
if (error_id != cudaSuccess){
cout << "cudaGetDeviceCount returned " << int(error_id) << endl;
cout << "-> " <<cudaGetErrorString(error_id) << endl;
cout << "Result = FAIL" << endl;
//exit(EXIT_FAILURE);
}
if (deviceCount == 0){
cout << "There is no available device that support CUDA" << endl;
}
else{
cout << "Deteced " << deviceCount <<" CUDA Capable device(s)" << endl;
}
int dev, driverVersion = 0, runtimeVersion = 0;
dev = 0;
cudaSetDevice(dev);
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
cout << "Device " << dev << "\"" << deviceProp.name << "\"" << endl;
cudaDriverGetVersion(&driverVersion);
cudaRuntimeGetVersion(&runtimeVersion);
cout << " CUDA Driver Version / Runtime Version " << driverVersion / 1000 << "." << (driverVersion %100) / 10 << "/" <<
runtimeVersion / 1000 << "." << (runtimeVersion%100) / 10 << endl;
cout << " CUDA Capability Major/Minor version number: " << deviceProp.major << "." << deviceProp.minor << endl;
cout << " Total amount of global memory: " << (float)deviceProp.totalGlobalMem/(pow(1024.0, 3)) << " GBytes" <<
"(" << (unsigned long long) deviceProp.totalGlobalMem << " bytes)" << endl;
cout << " GPU Clock rate: " << deviceProp.clockRate * 1e-3f << " MHz" << "(" <<
deviceProp.clockRate * 1e-6f << " GHz)" << endl;
cout << " Memory Clock rate: " << deviceProp.memoryClockRate * 1e-3f << " Mhz" << endl;
cout << " Memory Bus Width: " << deviceProp.memoryBusWidth << "-bit" << endl;
if (deviceProp.l2CacheSize)
cout << " L2 Cache Size: " << deviceProp.l2CacheSize << " bytes" << endl;
cout << " Max Texture Dimension Size (x, y, z) 1D=(" << deviceProp.maxTexture1D << "), " << "2D=(" <<
deviceProp.maxTexture2D[0] << ", " << deviceProp.maxTexture2D[1] << "), " << "3D=(" << deviceProp.maxTexture3D[0] << ", " <<
deviceProp.maxTexture3D[1] << ", " << deviceProp.maxTexture3D[2] << ")" << endl;
cout << " Max Layered Texture Size (dim) x layers 1D=(" << deviceProp.maxTexture1DLayered[0] << ") x " <<
deviceProp.maxTexture1DLayered[1] << "2D=(" << deviceProp.maxTexture2DLayered[0] << ", " << deviceProp.maxTexture2DLayered[1] << ") x " <<
deviceProp.maxTexture2DLayered[2] << endl;
cout << " Total amount of constant memory: " << deviceProp.totalConstMem << " bytes" << endl;
cout << " Total amount of shared memory per block: " << deviceProp.sharedMemPerBlock << " bytes" << endl;
cout << " Total number of registers available per block: " << deviceProp.regsPerBlock << endl;
cout << " Warp size: " << deviceProp.warpSize << endl;
cout << " Number of multiprocessors: " << deviceProp.multiProcessorCount << endl;
cout << " Maximum number of warps per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor / 32 << endl;
cout << " Maximum number of threads per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor << endl;
cout << " Maximum number of threads per block: " << deviceProp.maxThreadsPerBlock << endl;
cout << " Maximum sizes of each dimension of a block: " << deviceProp.maxThreadsDim[0] << " x " <<
deviceProp.maxThreadsDim[1] << " x " << deviceProp.maxThreadsDim[2] << endl;
cout << " Maximum sizes of each dimension of a grid: " << deviceProp.maxGridSize[0] << " x " <<
deviceProp.maxGridSize[1] << " x " << deviceProp.maxGridSize[2] << endl;
cout << " Maximum memory pitch: " << deviceProp.memPitch << " bytes" << endl;
exit(EXIT_SUCCESS);
} | //
// Created by heidies on 7/5/18.
//
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
int main(int argc, char **argv){
cout << "Starting... " << endl;
int deviceCount = 0;
hipError_t error_id = hipGetDeviceCount(&deviceCount);
if (error_id != hipSuccess){
cout << "hipGetDeviceCount returned " << int(error_id) << endl;
cout << "-> " <<hipGetErrorString(error_id) << endl;
cout << "Result = FAIL" << endl;
//exit(EXIT_FAILURE);
}
if (deviceCount == 0){
cout << "There is no available device that support CUDA" << endl;
}
else{
cout << "Deteced " << deviceCount <<" CUDA Capable device(s)" << endl;
}
int dev, driverVersion = 0, runtimeVersion = 0;
dev = 0;
hipSetDevice(dev);
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
cout << "Device " << dev << "\"" << deviceProp.name << "\"" << endl;
hipDriverGetVersion(&driverVersion);
hipRuntimeGetVersion(&runtimeVersion);
cout << " CUDA Driver Version / Runtime Version " << driverVersion / 1000 << "." << (driverVersion %100) / 10 << "/" <<
runtimeVersion / 1000 << "." << (runtimeVersion%100) / 10 << endl;
cout << " CUDA Capability Major/Minor version number: " << deviceProp.major << "." << deviceProp.minor << endl;
cout << " Total amount of global memory: " << (float)deviceProp.totalGlobalMem/(pow(1024.0, 3)) << " GBytes" <<
"(" << (unsigned long long) deviceProp.totalGlobalMem << " bytes)" << endl;
cout << " GPU Clock rate: " << deviceProp.clockRate * 1e-3f << " MHz" << "(" <<
deviceProp.clockRate * 1e-6f << " GHz)" << endl;
cout << " Memory Clock rate: " << deviceProp.memoryClockRate * 1e-3f << " Mhz" << endl;
cout << " Memory Bus Width: " << deviceProp.memoryBusWidth << "-bit" << endl;
if (deviceProp.l2CacheSize)
cout << " L2 Cache Size: " << deviceProp.l2CacheSize << " bytes" << endl;
cout << " Max Texture Dimension Size (x, y, z) 1D=(" << deviceProp.maxTexture1D << "), " << "2D=(" <<
deviceProp.maxTexture2D[0] << ", " << deviceProp.maxTexture2D[1] << "), " << "3D=(" << deviceProp.maxTexture3D[0] << ", " <<
deviceProp.maxTexture3D[1] << ", " << deviceProp.maxTexture3D[2] << ")" << endl;
cout << " Max Layered Texture Size (dim) x layers 1D=(" << deviceProp.maxTexture1DLayered[0] << ") x " <<
deviceProp.maxTexture1DLayered[1] << "2D=(" << deviceProp.maxTexture2DLayered[0] << ", " << deviceProp.maxTexture2DLayered[1] << ") x " <<
deviceProp.maxTexture2DLayered[2] << endl;
cout << " Total amount of constant memory: " << deviceProp.totalConstMem << " bytes" << endl;
cout << " Total amount of shared memory per block: " << deviceProp.sharedMemPerBlock << " bytes" << endl;
cout << " Total number of registers available per block: " << deviceProp.regsPerBlock << endl;
cout << " Warp size: " << deviceProp.warpSize << endl;
cout << " Number of multiprocessors: " << deviceProp.multiProcessorCount << endl;
cout << " Maximum number of warps per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor / 32 << endl;
cout << " Maximum number of threads per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor << endl;
cout << " Maximum number of threads per block: " << deviceProp.maxThreadsPerBlock << endl;
cout << " Maximum sizes of each dimension of a block: " << deviceProp.maxThreadsDim[0] << " x " <<
deviceProp.maxThreadsDim[1] << " x " << deviceProp.maxThreadsDim[2] << endl;
cout << " Maximum sizes of each dimension of a grid: " << deviceProp.maxGridSize[0] << " x " <<
deviceProp.maxGridSize[1] << " x " << deviceProp.maxGridSize[2] << endl;
cout << " Maximum memory pitch: " << deviceProp.memPitch << " bytes" << endl;
exit(EXIT_SUCCESS);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by heidies on 7/5/18.
//
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
int main(int argc, char **argv){
cout << "Starting... " << endl;
int deviceCount = 0;
hipError_t error_id = hipGetDeviceCount(&deviceCount);
if (error_id != hipSuccess){
cout << "hipGetDeviceCount returned " << int(error_id) << endl;
cout << "-> " <<hipGetErrorString(error_id) << endl;
cout << "Result = FAIL" << endl;
//exit(EXIT_FAILURE);
}
if (deviceCount == 0){
cout << "There is no available device that support CUDA" << endl;
}
else{
cout << "Deteced " << deviceCount <<" CUDA Capable device(s)" << endl;
}
int dev, driverVersion = 0, runtimeVersion = 0;
dev = 0;
hipSetDevice(dev);
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
cout << "Device " << dev << "\"" << deviceProp.name << "\"" << endl;
hipDriverGetVersion(&driverVersion);
hipRuntimeGetVersion(&runtimeVersion);
cout << " CUDA Driver Version / Runtime Version " << driverVersion / 1000 << "." << (driverVersion %100) / 10 << "/" <<
runtimeVersion / 1000 << "." << (runtimeVersion%100) / 10 << endl;
cout << " CUDA Capability Major/Minor version number: " << deviceProp.major << "." << deviceProp.minor << endl;
cout << " Total amount of global memory: " << (float)deviceProp.totalGlobalMem/(pow(1024.0, 3)) << " GBytes" <<
"(" << (unsigned long long) deviceProp.totalGlobalMem << " bytes)" << endl;
cout << " GPU Clock rate: " << deviceProp.clockRate * 1e-3f << " MHz" << "(" <<
deviceProp.clockRate * 1e-6f << " GHz)" << endl;
cout << " Memory Clock rate: " << deviceProp.memoryClockRate * 1e-3f << " Mhz" << endl;
cout << " Memory Bus Width: " << deviceProp.memoryBusWidth << "-bit" << endl;
if (deviceProp.l2CacheSize)
cout << " L2 Cache Size: " << deviceProp.l2CacheSize << " bytes" << endl;
cout << " Max Texture Dimension Size (x, y, z) 1D=(" << deviceProp.maxTexture1D << "), " << "2D=(" <<
deviceProp.maxTexture2D[0] << ", " << deviceProp.maxTexture2D[1] << "), " << "3D=(" << deviceProp.maxTexture3D[0] << ", " <<
deviceProp.maxTexture3D[1] << ", " << deviceProp.maxTexture3D[2] << ")" << endl;
cout << " Max Layered Texture Size (dim) x layers 1D=(" << deviceProp.maxTexture1DLayered[0] << ") x " <<
deviceProp.maxTexture1DLayered[1] << "2D=(" << deviceProp.maxTexture2DLayered[0] << ", " << deviceProp.maxTexture2DLayered[1] << ") x " <<
deviceProp.maxTexture2DLayered[2] << endl;
cout << " Total amount of constant memory: " << deviceProp.totalConstMem << " bytes" << endl;
cout << " Total amount of shared memory per block: " << deviceProp.sharedMemPerBlock << " bytes" << endl;
cout << " Total number of registers available per block: " << deviceProp.regsPerBlock << endl;
cout << " Warp size: " << deviceProp.warpSize << endl;
cout << " Number of multiprocessors: " << deviceProp.multiProcessorCount << endl;
cout << " Maximum number of warps per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor / 32 << endl;
cout << " Maximum number of threads per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor << endl;
cout << " Maximum number of threads per block: " << deviceProp.maxThreadsPerBlock << endl;
cout << " Maximum sizes of each dimension of a block: " << deviceProp.maxThreadsDim[0] << " x " <<
deviceProp.maxThreadsDim[1] << " x " << deviceProp.maxThreadsDim[2] << endl;
cout << " Maximum sizes of each dimension of a grid: " << deviceProp.maxGridSize[0] << " x " <<
deviceProp.maxGridSize[1] << " x " << deviceProp.maxGridSize[2] << endl;
cout << " Maximum memory pitch: " << deviceProp.memPitch << " bytes" << endl;
exit(EXIT_SUCCESS);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by heidies on 7/5/18.
//
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
int main(int argc, char **argv){
cout << "Starting... " << endl;
int deviceCount = 0;
hipError_t error_id = hipGetDeviceCount(&deviceCount);
if (error_id != hipSuccess){
cout << "hipGetDeviceCount returned " << int(error_id) << endl;
cout << "-> " <<hipGetErrorString(error_id) << endl;
cout << "Result = FAIL" << endl;
//exit(EXIT_FAILURE);
}
if (deviceCount == 0){
cout << "There is no available device that support CUDA" << endl;
}
else{
cout << "Deteced " << deviceCount <<" CUDA Capable device(s)" << endl;
}
int dev, driverVersion = 0, runtimeVersion = 0;
dev = 0;
hipSetDevice(dev);
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
cout << "Device " << dev << "\"" << deviceProp.name << "\"" << endl;
hipDriverGetVersion(&driverVersion);
hipRuntimeGetVersion(&runtimeVersion);
cout << " CUDA Driver Version / Runtime Version " << driverVersion / 1000 << "." << (driverVersion %100) / 10 << "/" <<
runtimeVersion / 1000 << "." << (runtimeVersion%100) / 10 << endl;
cout << " CUDA Capability Major/Minor version number: " << deviceProp.major << "." << deviceProp.minor << endl;
cout << " Total amount of global memory: " << (float)deviceProp.totalGlobalMem/(pow(1024.0, 3)) << " GBytes" <<
"(" << (unsigned long long) deviceProp.totalGlobalMem << " bytes)" << endl;
cout << " GPU Clock rate: " << deviceProp.clockRate * 1e-3f << " MHz" << "(" <<
deviceProp.clockRate * 1e-6f << " GHz)" << endl;
cout << " Memory Clock rate: " << deviceProp.memoryClockRate * 1e-3f << " Mhz" << endl;
cout << " Memory Bus Width: " << deviceProp.memoryBusWidth << "-bit" << endl;
if (deviceProp.l2CacheSize)
cout << " L2 Cache Size: " << deviceProp.l2CacheSize << " bytes" << endl;
cout << " Max Texture Dimension Size (x, y, z) 1D=(" << deviceProp.maxTexture1D << "), " << "2D=(" <<
deviceProp.maxTexture2D[0] << ", " << deviceProp.maxTexture2D[1] << "), " << "3D=(" << deviceProp.maxTexture3D[0] << ", " <<
deviceProp.maxTexture3D[1] << ", " << deviceProp.maxTexture3D[2] << ")" << endl;
cout << " Max Layered Texture Size (dim) x layers 1D=(" << deviceProp.maxTexture1DLayered[0] << ") x " <<
deviceProp.maxTexture1DLayered[1] << "2D=(" << deviceProp.maxTexture2DLayered[0] << ", " << deviceProp.maxTexture2DLayered[1] << ") x " <<
deviceProp.maxTexture2DLayered[2] << endl;
cout << " Total amount of constant memory: " << deviceProp.totalConstMem << " bytes" << endl;
cout << " Total amount of shared memory per block: " << deviceProp.sharedMemPerBlock << " bytes" << endl;
cout << " Total number of registers available per block: " << deviceProp.regsPerBlock << endl;
cout << " Warp size: " << deviceProp.warpSize << endl;
cout << " Number of multiprocessors: " << deviceProp.multiProcessorCount << endl;
cout << " Maximum number of warps per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor / 32 << endl;
cout << " Maximum number of threads per multiprocessor: " << deviceProp.maxThreadsPerMultiProcessor << endl;
cout << " Maximum number of threads per block: " << deviceProp.maxThreadsPerBlock << endl;
cout << " Maximum sizes of each dimension of a block: " << deviceProp.maxThreadsDim[0] << " x " <<
deviceProp.maxThreadsDim[1] << " x " << deviceProp.maxThreadsDim[2] << endl;
cout << " Maximum sizes of each dimension of a grid: " << deviceProp.maxGridSize[0] << " x " <<
deviceProp.maxGridSize[1] << " x " << deviceProp.maxGridSize[2] << endl;
cout << " Maximum memory pitch: " << deviceProp.memPitch << " bytes" << endl;
exit(EXIT_SUCCESS);
} | .text
.file "checkDeviceInfor.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI0_1:
.long 0x3a83126f # float 0.00100000005
.LCPI0_2:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
jne .LBB0_1
.LBB0_70:
callq _ZSt16__throw_bad_castv
.LBB0_1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
jne .LBB0_2
# %bb.3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_4
.LBB0_2:
movzbl 67(%rbx), %eax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_5
# %bb.21:
cmpl $0, 12(%rsp)
jne .LBB0_27
.LBB0_22:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_70
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i24
cmpb $0, 56(%rbx)
jne .LBB0_24
# %bb.25:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_26
.LBB0_5:
movl %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_70
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i9
cmpb $0, 56(%r14)
jne .LBB0_7
# %bb.8:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
jmp .LBB0_9
.LBB0_7:
movzbl 67(%r14), %ecx
.LBB0_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit12
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %ebx, %edi
callq hipGetErrorString
testq %rax, %rax
jne .LBB0_11
# %bb.10:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
jmp .LBB0_12
.LBB0_11:
movq %rax, %rdi
movq %rax, %rbx
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_70
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i14
cmpb $0, 56(%rbx)
jne .LBB0_14
# %bb.15:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_16
.LBB0_24:
movzbl 67(%rbx), %eax
.LBB0_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit27
movsbl %al, %esi
movl $_ZSt4cout, %edi
jmp .LBB0_32
.LBB0_14:
movzbl 67(%rbx), %eax
.LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit17
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_70
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i19
cmpb $0, 56(%rbx)
jne .LBB0_18
# %bb.19:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_20
.LBB0_18:
movzbl 67(%rbx), %eax
.LBB0_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit22
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 12(%rsp)
je .LBB0_22
.LBB0_27:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 12(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.6, %esi
movl $23, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_70
# %bb.28: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i29
cmpb $0, 56(%r14)
jne .LBB0_29
# %bb.30:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_31
.LBB0_29:
movzbl 67(%r14), %eax
.LBB0_31: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32
movsbl %al, %esi
movq %rbx, %rdi
.LBB0_32:
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $0, 8(%rsp)
movl $0, 4(%rsp)
xorl %edi, %edi
callq hipSetDevice
leaq 16(%rsp), %r14
movq %r14, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
xorl %esi, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.8, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movq %rbx, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.8, %esi
movl $1, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_70
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i34
cmpb $0, 56(%r14)
jne .LBB0_34
# %bb.35:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_36
.LBB0_34:
movzbl 67(%r14), %eax
.LBB0_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit37
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 8(%rsp), %rdi
callq hipDriverGetVersion
leaq 4(%rsp), %rdi
callq hipRuntimeGetVersion
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $61, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 8(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $_ZSt4cout, %edi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.10, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 8(%rsp), %rax
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rsi # imm = 0x66666667
movq %rsi, %rax
shrq $63, %rax
sarq $34, %rsi
addl %eax, %esi
movq %rbx, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.11, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 4(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movq %rbx, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.10, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 4(%rsp), %rax
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
cltq
imulq $1717986919, %rax, %rsi # imm = 0x66666667
movq %rsi, %rax
shrq $63, %rax
sarq $34, %rsi
addl %eax, %esi
movq %rbx, %rdi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_70
# %bb.37: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i39
cmpb $0, 56(%rbx)
jne .LBB0_38
# %bb.39:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
jmp .LBB0_40
.LBB0_38:
movzbl 67(%rbx), %ecx
.LBB0_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit42
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $61, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 376(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.10, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 380(%rsp), %esi
movq %rbx, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_70
# %bb.41: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i44
cmpb $0, 56(%rbx)
jne .LBB0_42
# %bb.43:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
jmp .LBB0_44
.LBB0_42:
movzbl 67(%rbx), %ecx
.LBB0_44: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit47
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $61, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 304(%rsp), %rax
testq %rax, %rax
js .LBB0_45
# %bb.46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit47
cvtsi2ss %rax, %xmm0
jmp .LBB0_47
.LBB0_45:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB0_47: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit47
cvtss2sd %xmm0, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.14, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.15, %esi
movl $1, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 304(%rsp), %rsi
movq %rbx, %rdi
callq _ZNSo9_M_insertIyEERSoT_
movq %rax, %rbx
movl $.L.str.16, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_70
# %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i49
cmpb $0, 56(%r14)
jne .LBB0_49
# %bb.50:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_51
.LBB0_49:
movzbl 67(%r14), %eax
.LBB0_51: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit52
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.17, %esi
movl $61, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
mulss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.18, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.15, %esi
movl $1, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
mulss .LCPI0_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.19, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_70
# %bb.52: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i54
cmpb $0, 56(%r14)
jne .LBB0_53
# %bb.54:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_55
.LBB0_53:
movzbl 67(%r14), %eax
.LBB0_55: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit57
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.20, %esi
movl $61, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2ssl 624(%rsp), %xmm0
mulss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.21, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_70
# %bb.56: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i59
cmpb $0, 56(%r14)
jne .LBB0_57
# %bb.58:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_59
.LBB0_57:
movzbl 67(%r14), %eax
.LBB0_59: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit62
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.22, %esi
movl $61, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 628(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.23, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_70
# %bb.60: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i64
cmpb $0, 56(%r14)
jne .LBB0_61
# %bb.62:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_63
.LBB0_61:
movzbl 67(%r14), %eax
.LBB0_63: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit67
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 632(%rsp)
je .LBB0_69
# %bb.64:
movl $_ZSt4cout, %edi
movl $.L.str.24, %esi
movl $61, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 632(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.25, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_70
# %bb.65: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i69
cmpb $0, 56(%r14)
jne .LBB0_66
# %bb.67:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB0_68
.LBB0_66:
movzbl 67(%r14), %eax
.LBB0_68: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit72
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB0_69:
movl $_ZSt4cout, %edi
movl $.L.str.26, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 424(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.27, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.28, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 436(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.29, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 440(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.27, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.30, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 472(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.29, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 476(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.29, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 480(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.31, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.32, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 500(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.33, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 504(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.28, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 508(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.29, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 512(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.33, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 516(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.34, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq 368(%rsp), %rsi
movq %rax, %rdi
callq _ZNSolsEm
movl $.L.str.25, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.35, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq 312(%rsp), %rsi
movq %rax, %rdi
callq _ZNSolsEm
movl $.L.str.25, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.36, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 320(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.37, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 324(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.38, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 404(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.39, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 640(%rsp), %ecx
leal 31(%rcx), %esi
testl %ecx, %ecx
cmovnsl %ecx, %esi
sarl $5, %esi
movq %rax, %rdi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.40, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 640(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.41, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 336(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.42, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 340(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.43, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 344(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.43, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 348(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.44, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 352(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.43, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 356(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movl $.L.str.43, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl 360(%rsp), %esi
movq %rax, %rdi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cout, %edi
movl $.L.str.45, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq 328(%rsp), %rsi
movq %rax, %rdi
callq _ZNSolsEm
movl $.L.str.25, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Starting... "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipGetDeviceCount returned "
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "-> "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Result = FAIL"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "There is no available device that support CUDA"
.size .L.str.4, 47
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Deteced "
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " CUDA Capable device(s)"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Device "
.size .L.str.7, 8
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\""
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " CUDA Driver Version / Runtime Version "
.size .L.str.9, 62
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "."
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "/"
.size .L.str.11, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " CUDA Capability Major/Minor version number: "
.size .L.str.12, 62
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Total amount of global memory: "
.size .L.str.13, 62
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " GBytes"
.size .L.str.14, 8
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "("
.size .L.str.15, 2
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " bytes)"
.size .L.str.16, 8
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " GPU Clock rate: "
.size .L.str.17, 62
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " MHz"
.size .L.str.18, 5
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " GHz)"
.size .L.str.19, 6
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " Memory Clock rate: "
.size .L.str.20, 62
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " Mhz"
.size .L.str.21, 5
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz " Memory Bus Width: "
.size .L.str.22, 62
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "-bit"
.size .L.str.23, 5
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz " L2 Cache Size: "
.size .L.str.24, 62
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz " bytes"
.size .L.str.25, 7
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz " Max Texture Dimension Size (x, y, z) 1D=("
.size .L.str.26, 52
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "), "
.size .L.str.27, 4
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "2D=("
.size .L.str.28, 5
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz ", "
.size .L.str.29, 3
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "3D=("
.size .L.str.30, 5
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz ")"
.size .L.str.31, 2
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz " Max Layered Texture Size (dim) x layers 1D=("
.size .L.str.32, 55
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz ") x "
.size .L.str.33, 5
.type .L.str.34,@object # @.str.34
.L.str.34:
.asciz " Total amount of constant memory: "
.size .L.str.34, 62
.type .L.str.35,@object # @.str.35
.L.str.35:
.asciz " Total amount of shared memory per block: "
.size .L.str.35, 62
.type .L.str.36,@object # @.str.36
.L.str.36:
.asciz " Total number of registers available per block: "
.size .L.str.36, 62
.type .L.str.37,@object # @.str.37
.L.str.37:
.asciz " Warp size: "
.size .L.str.37, 62
.type .L.str.38,@object # @.str.38
.L.str.38:
.asciz " Number of multiprocessors: "
.size .L.str.38, 62
.type .L.str.39,@object # @.str.39
.L.str.39:
.asciz " Maximum number of warps per multiprocessor: "
.size .L.str.39, 62
.type .L.str.40,@object # @.str.40
.L.str.40:
.asciz " Maximum number of threads per multiprocessor: "
.size .L.str.40, 62
.type .L.str.41,@object # @.str.41
.L.str.41:
.asciz " Maximum number of threads per block: "
.size .L.str.41, 62
.type .L.str.42,@object # @.str.42
.L.str.42:
.asciz " Maximum sizes of each dimension of a block: "
.size .L.str.42, 62
.type .L.str.43,@object # @.str.43
.L.str.43:
.asciz " x "
.size .L.str.43, 4
.type .L.str.44,@object # @.str.44
.L.str.44:
.asciz " Maximum sizes of each dimension of a grid: "
.size .L.str.44, 62
.type .L.str.45,@object # @.str.45
.L.str.45:
.asciz " Maximum memory pitch: "
.size .L.str.45, 62
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ComputeLaplacianInPlace(float* d, int n)
{
// Column to sum
auto x = blockIdx.x * blockDim.x + threadIdx.x;
if(x < n)
{
auto dCol = &d[x * n];
for(auto i = 0; i < n; ++i)
{
if(i != x)
{
dCol[x] += dCol[i];
dCol[i] = -dCol[i];
}
}
}
} | code for sm_80
Function : _Z23ComputeLaplacianInPlacePfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD R0, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006007a24 */
/* 0x040fe200078e02ff */
/*0070*/ IMNMX R8, R6.reuse, c[0x0][0x168], PT ; /* 0x00005a0006087a17 */
/* 0x040fe20003800200 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ BSSY B0, 0x5c0 ; /* 0x0000052000007945 */
/* 0x000fe20003800000 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R3, P0, R6, R0, RZ ; /* 0x0000000006037210 */
/* 0x000fc80007f1e0ff */
/*00c0*/ LEA R2, P1, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003027a11 */
/* 0x000fe200078210ff */
/*00d0*/ IMAD.X R4, RZ, RZ, RZ, P0 ; /* 0x000000ffff047224 */
/* 0x000fe200000e06ff */
/*00e0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fc80003f06270 */
/*00f0*/ LEA.HI.X R3, R3, c[0x0][0x164], R4, 0x2, P1 ; /* 0x0000590003037a11 */
/* 0x000fd200008f1404 */
/*0100*/ @!P0 BRA 0x5b0 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R4, R8.reuse, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x040fe20007ffe0ff */
/*0120*/ BSSY B1, 0x470 ; /* 0x0000034000017945 */
/* 0x000fe20003800000 */
/*0130*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe200078ec0ff */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*0160*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fd60003f05270 */
/*0170*/ @!P1 BRA 0x460 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0180*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0190*/ LEA R10, P1, R0, c[0x0][0x160], 0x2 ; /* 0x00005800000a7a11 */
/* 0x000fe200078210ff */
/*01a0*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fe2000f8e333f */
/*01b0*/ LOP3.LUT R4, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff047212 */
/* 0x000fe200078e33ff */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*01d0*/ IADD3 R10, P2, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007f5e0ff */
/*01e0*/ LEA.HI.X R13, R0, c[0x0][0x164], RZ, 0x2, P1 ; /* 0x00005900000d7a11 */
/* 0x000fe400008f14ff */
/*01f0*/ IMNMX R9, R4, UR4, !PT ; /* 0x0000000404097c17 */
/* 0x000fc6000f800200 */
/*0200*/ IMAD.X R13, RZ, RZ, R13, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e060d */
/*0210*/ IADD3 R9, RZ, -R8, -R9 ; /* 0x80000008ff097210 */
/* 0x000fe40007ffe809 */
/*0220*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x008fe400078e000a */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0240*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R11, [R4.64+-0x8] ; /* 0xfffff806040b7981 */
/* 0x000ea4000c1e1900 */
/*0260*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0270*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101906 */
/*0280*/ LDG.E R10, [R4.64+-0x8] ; /* 0xfffff806040a7981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R13, [R4.64+-0x4] ; /* 0xfffffc06040d7981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ FADD R17, -R10, -RZ ; /* 0x800000ff0a117221 */
/* 0x004fca0000000100 */
/*02b0*/ STG.E [R4.64+-0x8], R17 ; /* 0xfffff81104007986 */
/* 0x0003e8000c101906 */
/*02c0*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ee4000c1e1900 */
/*02d0*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x008fca0000000000 */
/*02e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe8000c101906 */
/*02f0*/ LDG.E R10, [R4.64+-0x4] ; /* 0xfffffc06040a7981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R15, [R4.64] ; /* 0x00000006040f7981 */
/* 0x000ee2000c1e1900 */
/*0310*/ FADD R19, -R10, -RZ ; /* 0x800000ff0a137221 */
/* 0x004fca0000000100 */
/*0320*/ STG.E [R4.64+-0x4], R19 ; /* 0xfffffc1304007986 */
/* 0x0005e8000c101906 */
/*0330*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ee4000c1e1900 */
/*0340*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0350*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101906 */
/*0360*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000e68000c1e1900 */
/*0370*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000406040b7981 */
/* 0x001f22000c1e1900 */
/*0380*/ FADD R17, -R10, -RZ ; /* 0x800000ff0a117221 */
/* 0x002fca0000000100 */
/*0390*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x0007e8000c101906 */
/*03a0*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000f24000c1e1900 */
/*03b0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*03c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e8000c101906 */
/*03d0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000406040a7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fc80007ffe0ff */
/*03f0*/ ISETP.NE.AND P1, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f25270 */
/*0400*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007ffe0ff */
/*0410*/ FADD R19, -R10, -RZ ; /* 0x800000ff0a137221 */
/* 0x004fca0000000100 */
/*0420*/ STG.E [R4.64+0x4], R19 ; /* 0x0000041304007986 */
/* 0x0007e2000c101906 */
/*0430*/ IADD3 R10, P2, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fca0007f5e0ff */
/*0440*/ IMAD.X R13, RZ, RZ, R5, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e0605 */
/*0450*/ @P1 BRA 0x220 ; /* 0xfffffdc000001947 */
/* 0x000fea000383ffff */
/*0460*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0470*/ @!P0 BRA 0x5b0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0480*/ IADD3 R11, P0, R0, R7, RZ ; /* 0x00000007000b7210 */
/* 0x008fc80007f1e0ff */
/*0490*/ LEA R10, P1, R11, c[0x0][0x160], 0x2 ; /* 0x000058000b0a7a11 */
/* 0x000fe400078210ff */
/*04a0*/ LEA.HI.X.SX32 R4, R7, RZ, 0x1, P0 ; /* 0x000000ff07047211 */
/* 0x000fc800000f0eff */
/*04b0*/ LEA.HI.X R11, R11, c[0x0][0x164], R4, 0x2, P1 ; /* 0x000059000b0b7a11 */
/* 0x000fc600008f1404 */
/*04c0*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x001fe200078e000a */
/*04d0*/ LDG.E R9, [R2.64] ; /* 0x0000000602097981 */
/* 0x000ea2000c1e1900 */
/*04e0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000b */
/*04f0*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ea4000c1e1900 */
/*0500*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*0510*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101906 */
/*0520*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*0540*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0550*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0560*/ FADD R13, -R10, -RZ ; /* 0x800000ff0a0d7221 */
/* 0x004fca0000000100 */
/*0570*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e2000c101906 */
/*0580*/ IADD3 R10, P1, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fca0007f3e0ff */
/*0590*/ IMAD.X R11, RZ, RZ, R5, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e0605 */
/*05a0*/ @P0 BRA 0x4c0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06270 */
/*05d0*/ BSSY B0, 0x700 ; /* 0x0000012000007945 */
/* 0x000fd80003800000 */
/*05e0*/ @P0 BRA 0x6f0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.NE.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe20003f05270 */
/*0600*/ BSSY B1, 0x6e0 ; /* 0x000000d000017945 */
/* 0x000fd80003800000 */
/*0610*/ @!P0 BRA 0x6d0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0620*/ IADD3 R5, P0, R0, R7, RZ ; /* 0x0000000700057210 */
/* 0x009fc80007f1e0ff */
/*0630*/ LEA.HI.X.SX32 R6, R7, RZ, 0x1, P0 ; /* 0x000000ff07067211 */
/* 0x000fe400000f0eff */
/*0640*/ LEA R4, P0, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005047a11 */
/* 0x000fc800078010ff */
/*0650*/ LEA.HI.X R5, R5, c[0x0][0x164], R6, 0x2, P0 ; /* 0x0000590005057a11 */
/* 0x000fe400000f1406 */
/*0660*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea4000c1e1900 */
/*0680*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x004fca0000000000 */
/*0690*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101906 */
/*06a0*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ FADD R11, -R6, -RZ ; /* 0x800000ff060b7221 */
/* 0x004fca0000000100 */
/*06c0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101906 */
/*06d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06e0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fda0003f06270 */
/*0710*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0720*/ IADD3 R4, -R7, c[0x0][0x168], RZ ; /* 0x00005a0007047a10 */
/* 0x009fe20007ffe1ff */
/*0730*/ BSSY B0, 0x8e0 ; /* 0x000001a000007945 */
/* 0x000fe20003800000 */
/*0740*/ LOP3.LUT R5, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff057212 */
/* 0x000fe400078e33ff */
/*0750*/ LOP3.LUT P1, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe4000782c0ff */
/*0760*/ IADD3 R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a10 */
/* 0x000fc80007ffe0ff */
/*0770*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fce0003f06070 */
/*0780*/ @!P1 BRA 0x8d0 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*0790*/ IADD3 R11, P1, R0, R7, RZ ; /* 0x00000007000b7210 */
/* 0x000fe20007f3e0ff */
/*07a0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0004 */
/*07b0*/ LEA R8, P2, R11, c[0x0][0x160], 0x2 ; /* 0x000058000b087a11 */
/* 0x000fe400078410ff */
/*07c0*/ LEA.HI.X.SX32 R10, R7, RZ, 0x1, P1 ; /* 0x000000ff070a7211 */
/* 0x000fc800008f0eff */
/*07d0*/ LEA.HI.X R11, R11, c[0x0][0x164], R10, 0x2, P2 ; /* 0x000059000b0b7a11 */
/* 0x000fc600010f140a */
/*07e0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0008 */
/*07f0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0800*/ LDG.E R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ea8000c1e1900 */
/*0810*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea4000c1e1900 */
/*0820*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*0830*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101906 */
/*0840*/ LDG.E R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea2000c1e1900 */
/*0850*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*0870*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*0880*/ FADD R13, -R8, -RZ ; /* 0x800000ff080d7221 */
/* 0x004fe20000000100 */
/*0890*/ IADD3 R8, P2, R4, 0x4, RZ ; /* 0x0000000404087810 */
/* 0x000fc80007f5e0ff */
/*08a0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e2000c101906 */
/*08b0*/ IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00010e0605 */
/*08c0*/ @P1 BRA 0x7e0 ; /* 0xffffff1000001947 */
/* 0x000fea000383ffff */
/*08d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08f0*/ IADD3 R11, P0, R0, R7, RZ ; /* 0x00000007000b7210 */
/* 0x000fc80007f1e0ff */
/*0900*/ LEA R0, P1, R11, c[0x0][0x160], 0x2 ; /* 0x000058000b007a11 */
/* 0x000fe400078210ff */
/*0910*/ LEA.HI.X.SX32 R4, R7, RZ, 0x1, P0 ; /* 0x000000ff07047211 */
/* 0x001fc800000f0eff */
/*0920*/ LEA.HI.X R11, R11, c[0x0][0x164], R4, 0x2, P1 ; /* 0x000059000b0b7a11 */
/* 0x000fc600008f1404 */
/*0930*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x008fe400078e0000 */
/*0940*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0950*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea4000c1e1900 */
/*0970*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fca0000000000 */
/*0980*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101906 */
/*0990*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000406040b7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ FADD R15, -R0, -RZ ; /* 0x800000ff000f7221 */
/* 0x004fca0000000100 */
/*09c0*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0003e8000c101906 */
/*09d0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ee4000c1e1900 */
/*09e0*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x008fca0000000000 */
/*09f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101906 */
/*0a00*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040604007981 */
/* 0x000ea8000c1e1900 */
/*0a10*/ LDG.E R13, [R4.64+0x8] ; /* 0x00000806040d7981 */
/* 0x000ee2000c1e1900 */
/*0a20*/ FADD R17, -R0, -RZ ; /* 0x800000ff00117221 */
/* 0x004fca0000000100 */
/*0a30*/ STG.E [R4.64+0x4], R17 ; /* 0x0000041104007986 */
/* 0x0005e8000c101906 */
/*0a40*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ee4000c1e1900 */
/*0a50*/ FADD R13, R0, R13 ; /* 0x0000000d000d7221 */
/* 0x008fca0000000000 */
/*0a60*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101906 */
/*0a70*/ LDG.E R0, [R4.64+0x8] ; /* 0x0000080604007981 */
/* 0x000e68000c1e1900 */
/*0a80*/ LDG.E R9, [R4.64+0xc] ; /* 0x00000c0604097981 */
/* 0x001f22000c1e1900 */
/*0a90*/ FADD R15, -R0, -RZ ; /* 0x800000ff000f7221 */
/* 0x002fca0000000100 */
/*0aa0*/ STG.E [R4.64+0x8], R15 ; /* 0x0000080f04007986 */
/* 0x0007e8000c101906 */
/*0ab0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000f24000c1e1900 */
/*0ac0*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x010fca0000000000 */
/*0ad0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0007e8000c101906 */
/*0ae0*/ LDG.E R0, [R4.64+0xc] ; /* 0x00000c0604007981 */
/* 0x000ea2000c1e1900 */
/*0af0*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06270 */
/*0b10*/ FADD R17, -R0, -RZ ; /* 0x800000ff00117221 */
/* 0x004fca0000000100 */
/*0b20*/ STG.E [R4.64+0xc], R17 ; /* 0x00000c1104007986 */
/* 0x0007e2000c101906 */
/*0b30*/ IADD3 R0, P1, R4, 0x10, RZ ; /* 0x0000001004007810 */
/* 0x000fca0007f3e0ff */
/*0b40*/ IMAD.X R11, RZ, RZ, R5, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e0605 */
/*0b50*/ @!P0 BRA 0x930 ; /* 0xfffffdd000008947 */
/* 0x000fea000383ffff */
/*0b60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b70*/ BRA 0xb70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ComputeLaplacianInPlace(float* d, int n)
{
// Column to sum
auto x = blockIdx.x * blockDim.x + threadIdx.x;
if(x < n)
{
auto dCol = &d[x * n];
for(auto i = 0; i < n; ++i)
{
if(i != x)
{
dCol[x] += dCol[i];
dCol[i] = -dCol[i];
}
}
}
} | .file "tmpxft_000e66fe_00000000-6_ComputeLaplacianInPlace.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z23ComputeLaplacianInPlacePfiPfi
.type _Z44__device_stub__Z23ComputeLaplacianInPlacePfiPfi, @function
_Z44__device_stub__Z23ComputeLaplacianInPlacePfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z23ComputeLaplacianInPlacePfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z23ComputeLaplacianInPlacePfiPfi, .-_Z44__device_stub__Z23ComputeLaplacianInPlacePfiPfi
.globl _Z23ComputeLaplacianInPlacePfi
.type _Z23ComputeLaplacianInPlacePfi, @function
_Z23ComputeLaplacianInPlacePfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z23ComputeLaplacianInPlacePfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23ComputeLaplacianInPlacePfi, .-_Z23ComputeLaplacianInPlacePfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23ComputeLaplacianInPlacePfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23ComputeLaplacianInPlacePfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ComputeLaplacianInPlace(float* d, int n)
{
// Column to sum
auto x = blockIdx.x * blockDim.x + threadIdx.x;
if(x < n)
{
auto dCol = &d[x * n];
for(auto i = 0; i < n; ++i)
{
if(i != x)
{
dCol[x] += dCol[i];
dCol[i] = -dCol[i];
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeLaplacianInPlace(float* d, int n)
{
// Column to sum
auto x = blockIdx.x * blockDim.x + threadIdx.x;
if(x < n)
{
auto dCol = &d[x * n];
for(auto i = 0; i < n; ++i)
{
if(i != x)
{
dCol[x] += dCol[i];
dCol[i] = -dCol[i];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeLaplacianInPlace(float* d, int n)
{
// Column to sum
auto x = blockIdx.x * blockDim.x + threadIdx.x;
if(x < n)
{
auto dCol = &d[x * n];
for(auto i = 0; i < n; ++i)
{
if(i != x)
{
dCol[x] += dCol[i];
dCol[i] = -dCol[i];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23ComputeLaplacianInPlacePfi
.globl _Z23ComputeLaplacianInPlacePfi
.p2align 8
.type _Z23ComputeLaplacianInPlacePfi,@function
_Z23ComputeLaplacianInPlacePfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_lo_u32 v3, v1, s2
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v2, v4
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v4, vcc_lo, v2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, v3, v6, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_nc_u32_e32 v1, -1, v1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_cbranch_scc0 .LBB0_6
.LBB0_4:
s_mov_b32 s0, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_3
global_load_b32 v0, v[2:3], off
global_load_b32 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
global_store_b32 v[4:5], v0, off
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_xor_b32_e32 v0, 0x80000000, v0
global_store_b32 v[2:3], v0, off
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23ComputeLaplacianInPlacePfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23ComputeLaplacianInPlacePfi, .Lfunc_end0-_Z23ComputeLaplacianInPlacePfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23ComputeLaplacianInPlacePfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23ComputeLaplacianInPlacePfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeLaplacianInPlace(float* d, int n)
{
// Column to sum
auto x = blockIdx.x * blockDim.x + threadIdx.x;
if(x < n)
{
auto dCol = &d[x * n];
for(auto i = 0; i < n; ++i)
{
if(i != x)
{
dCol[x] += dCol[i];
dCol[i] = -dCol[i];
}
}
}
} | .text
.file "ComputeLaplacianInPlace.hip"
.globl _Z38__device_stub__ComputeLaplacianInPlacePfi # -- Begin function _Z38__device_stub__ComputeLaplacianInPlacePfi
.p2align 4, 0x90
.type _Z38__device_stub__ComputeLaplacianInPlacePfi,@function
_Z38__device_stub__ComputeLaplacianInPlacePfi: # @_Z38__device_stub__ComputeLaplacianInPlacePfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z23ComputeLaplacianInPlacePfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z38__device_stub__ComputeLaplacianInPlacePfi, .Lfunc_end0-_Z38__device_stub__ComputeLaplacianInPlacePfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23ComputeLaplacianInPlacePfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23ComputeLaplacianInPlacePfi,@object # @_Z23ComputeLaplacianInPlacePfi
.section .rodata,"a",@progbits
.globl _Z23ComputeLaplacianInPlacePfi
.p2align 3, 0x0
_Z23ComputeLaplacianInPlacePfi:
.quad _Z38__device_stub__ComputeLaplacianInPlacePfi
.size _Z23ComputeLaplacianInPlacePfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23ComputeLaplacianInPlacePfi"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__ComputeLaplacianInPlacePfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23ComputeLaplacianInPlacePfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23ComputeLaplacianInPlacePfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD R0, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006007a24 */
/* 0x040fe200078e02ff */
/*0070*/ IMNMX R8, R6.reuse, c[0x0][0x168], PT ; /* 0x00005a0006087a17 */
/* 0x040fe20003800200 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ BSSY B0, 0x5c0 ; /* 0x0000052000007945 */
/* 0x000fe20003800000 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R3, P0, R6, R0, RZ ; /* 0x0000000006037210 */
/* 0x000fc80007f1e0ff */
/*00c0*/ LEA R2, P1, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003027a11 */
/* 0x000fe200078210ff */
/*00d0*/ IMAD.X R4, RZ, RZ, RZ, P0 ; /* 0x000000ffff047224 */
/* 0x000fe200000e06ff */
/*00e0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fc80003f06270 */
/*00f0*/ LEA.HI.X R3, R3, c[0x0][0x164], R4, 0x2, P1 ; /* 0x0000590003037a11 */
/* 0x000fd200008f1404 */
/*0100*/ @!P0 BRA 0x5b0 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R4, R8.reuse, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x040fe20007ffe0ff */
/*0120*/ BSSY B1, 0x470 ; /* 0x0000034000017945 */
/* 0x000fe20003800000 */
/*0130*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe200078ec0ff */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*0160*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fd60003f05270 */
/*0170*/ @!P1 BRA 0x460 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0180*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0190*/ LEA R10, P1, R0, c[0x0][0x160], 0x2 ; /* 0x00005800000a7a11 */
/* 0x000fe200078210ff */
/*01a0*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fe2000f8e333f */
/*01b0*/ LOP3.LUT R4, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff047212 */
/* 0x000fe200078e33ff */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*01d0*/ IADD3 R10, P2, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007f5e0ff */
/*01e0*/ LEA.HI.X R13, R0, c[0x0][0x164], RZ, 0x2, P1 ; /* 0x00005900000d7a11 */
/* 0x000fe400008f14ff */
/*01f0*/ IMNMX R9, R4, UR4, !PT ; /* 0x0000000404097c17 */
/* 0x000fc6000f800200 */
/*0200*/ IMAD.X R13, RZ, RZ, R13, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e060d */
/*0210*/ IADD3 R9, RZ, -R8, -R9 ; /* 0x80000008ff097210 */
/* 0x000fe40007ffe809 */
/*0220*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x008fe400078e000a */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0240*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R11, [R4.64+-0x8] ; /* 0xfffff806040b7981 */
/* 0x000ea4000c1e1900 */
/*0260*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0270*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101906 */
/*0280*/ LDG.E R10, [R4.64+-0x8] ; /* 0xfffff806040a7981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R13, [R4.64+-0x4] ; /* 0xfffffc06040d7981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ FADD R17, -R10, -RZ ; /* 0x800000ff0a117221 */
/* 0x004fca0000000100 */
/*02b0*/ STG.E [R4.64+-0x8], R17 ; /* 0xfffff81104007986 */
/* 0x0003e8000c101906 */
/*02c0*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ee4000c1e1900 */
/*02d0*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x008fca0000000000 */
/*02e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe8000c101906 */
/*02f0*/ LDG.E R10, [R4.64+-0x4] ; /* 0xfffffc06040a7981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R15, [R4.64] ; /* 0x00000006040f7981 */
/* 0x000ee2000c1e1900 */
/*0310*/ FADD R19, -R10, -RZ ; /* 0x800000ff0a137221 */
/* 0x004fca0000000100 */
/*0320*/ STG.E [R4.64+-0x4], R19 ; /* 0xfffffc1304007986 */
/* 0x0005e8000c101906 */
/*0330*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ee4000c1e1900 */
/*0340*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0350*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0007e8000c101906 */
/*0360*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000e68000c1e1900 */
/*0370*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000406040b7981 */
/* 0x001f22000c1e1900 */
/*0380*/ FADD R17, -R10, -RZ ; /* 0x800000ff0a117221 */
/* 0x002fca0000000100 */
/*0390*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x0007e8000c101906 */
/*03a0*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000f24000c1e1900 */
/*03b0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*03c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0007e8000c101906 */
/*03d0*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000406040a7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fc80007ffe0ff */
/*03f0*/ ISETP.NE.AND P1, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f25270 */
/*0400*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007ffe0ff */
/*0410*/ FADD R19, -R10, -RZ ; /* 0x800000ff0a137221 */
/* 0x004fca0000000100 */
/*0420*/ STG.E [R4.64+0x4], R19 ; /* 0x0000041304007986 */
/* 0x0007e2000c101906 */
/*0430*/ IADD3 R10, P2, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fca0007f5e0ff */
/*0440*/ IMAD.X R13, RZ, RZ, R5, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e0605 */
/*0450*/ @P1 BRA 0x220 ; /* 0xfffffdc000001947 */
/* 0x000fea000383ffff */
/*0460*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0470*/ @!P0 BRA 0x5b0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0480*/ IADD3 R11, P0, R0, R7, RZ ; /* 0x00000007000b7210 */
/* 0x008fc80007f1e0ff */
/*0490*/ LEA R10, P1, R11, c[0x0][0x160], 0x2 ; /* 0x000058000b0a7a11 */
/* 0x000fe400078210ff */
/*04a0*/ LEA.HI.X.SX32 R4, R7, RZ, 0x1, P0 ; /* 0x000000ff07047211 */
/* 0x000fc800000f0eff */
/*04b0*/ LEA.HI.X R11, R11, c[0x0][0x164], R4, 0x2, P1 ; /* 0x000059000b0b7a11 */
/* 0x000fc600008f1404 */
/*04c0*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x001fe200078e000a */
/*04d0*/ LDG.E R9, [R2.64] ; /* 0x0000000602097981 */
/* 0x000ea2000c1e1900 */
/*04e0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000b */
/*04f0*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ea4000c1e1900 */
/*0500*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*0510*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101906 */
/*0520*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*0540*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0550*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0560*/ FADD R13, -R10, -RZ ; /* 0x800000ff0a0d7221 */
/* 0x004fca0000000100 */
/*0570*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e2000c101906 */
/*0580*/ IADD3 R10, P1, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fca0007f3e0ff */
/*0590*/ IMAD.X R11, RZ, RZ, R5, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e0605 */
/*05a0*/ @P0 BRA 0x4c0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06270 */
/*05d0*/ BSSY B0, 0x700 ; /* 0x0000012000007945 */
/* 0x000fd80003800000 */
/*05e0*/ @P0 BRA 0x6f0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.NE.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe20003f05270 */
/*0600*/ BSSY B1, 0x6e0 ; /* 0x000000d000017945 */
/* 0x000fd80003800000 */
/*0610*/ @!P0 BRA 0x6d0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0620*/ IADD3 R5, P0, R0, R7, RZ ; /* 0x0000000700057210 */
/* 0x009fc80007f1e0ff */
/*0630*/ LEA.HI.X.SX32 R6, R7, RZ, 0x1, P0 ; /* 0x000000ff07067211 */
/* 0x000fe400000f0eff */
/*0640*/ LEA R4, P0, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005047a11 */
/* 0x000fc800078010ff */
/*0650*/ LEA.HI.X R5, R5, c[0x0][0x164], R6, 0x2, P0 ; /* 0x0000590005057a11 */
/* 0x000fe400000f1406 */
/*0660*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea4000c1e1900 */
/*0680*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x004fca0000000000 */
/*0690*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101906 */
/*06a0*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ FADD R11, -R6, -RZ ; /* 0x800000ff060b7221 */
/* 0x004fca0000000100 */
/*06c0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101906 */
/*06d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06e0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fda0003f06270 */
/*0710*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0720*/ IADD3 R4, -R7, c[0x0][0x168], RZ ; /* 0x00005a0007047a10 */
/* 0x009fe20007ffe1ff */
/*0730*/ BSSY B0, 0x8e0 ; /* 0x000001a000007945 */
/* 0x000fe20003800000 */
/*0740*/ LOP3.LUT R5, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff057212 */
/* 0x000fe400078e33ff */
/*0750*/ LOP3.LUT P1, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe4000782c0ff */
/*0760*/ IADD3 R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a10 */
/* 0x000fc80007ffe0ff */
/*0770*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fce0003f06070 */
/*0780*/ @!P1 BRA 0x8d0 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*0790*/ IADD3 R11, P1, R0, R7, RZ ; /* 0x00000007000b7210 */
/* 0x000fe20007f3e0ff */
/*07a0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0004 */
/*07b0*/ LEA R8, P2, R11, c[0x0][0x160], 0x2 ; /* 0x000058000b087a11 */
/* 0x000fe400078410ff */
/*07c0*/ LEA.HI.X.SX32 R10, R7, RZ, 0x1, P1 ; /* 0x000000ff070a7211 */
/* 0x000fc800008f0eff */
/*07d0*/ LEA.HI.X R11, R11, c[0x0][0x164], R10, 0x2, P2 ; /* 0x000059000b0b7a11 */
/* 0x000fc600010f140a */
/*07e0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0008 */
/*07f0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0800*/ LDG.E R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ea8000c1e1900 */
/*0810*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea4000c1e1900 */
/*0820*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*0830*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101906 */
/*0840*/ LDG.E R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea2000c1e1900 */
/*0850*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*0870*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*0880*/ FADD R13, -R8, -RZ ; /* 0x800000ff080d7221 */
/* 0x004fe20000000100 */
/*0890*/ IADD3 R8, P2, R4, 0x4, RZ ; /* 0x0000000404087810 */
/* 0x000fc80007f5e0ff */
/*08a0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e2000c101906 */
/*08b0*/ IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00010e0605 */
/*08c0*/ @P1 BRA 0x7e0 ; /* 0xffffff1000001947 */
/* 0x000fea000383ffff */
/*08d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08f0*/ IADD3 R11, P0, R0, R7, RZ ; /* 0x00000007000b7210 */
/* 0x000fc80007f1e0ff */
/*0900*/ LEA R0, P1, R11, c[0x0][0x160], 0x2 ; /* 0x000058000b007a11 */
/* 0x000fe400078210ff */
/*0910*/ LEA.HI.X.SX32 R4, R7, RZ, 0x1, P0 ; /* 0x000000ff07047211 */
/* 0x001fc800000f0eff */
/*0920*/ LEA.HI.X R11, R11, c[0x0][0x164], R4, 0x2, P1 ; /* 0x000059000b0b7a11 */
/* 0x000fc600008f1404 */
/*0930*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x008fe400078e0000 */
/*0940*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0950*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea4000c1e1900 */
/*0970*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fca0000000000 */
/*0980*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101906 */
/*0990*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000406040b7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ FADD R15, -R0, -RZ ; /* 0x800000ff000f7221 */
/* 0x004fca0000000100 */
/*09c0*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0003e8000c101906 */
/*09d0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ee4000c1e1900 */
/*09e0*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x008fca0000000000 */
/*09f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101906 */
/*0a00*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040604007981 */
/* 0x000ea8000c1e1900 */
/*0a10*/ LDG.E R13, [R4.64+0x8] ; /* 0x00000806040d7981 */
/* 0x000ee2000c1e1900 */
/*0a20*/ FADD R17, -R0, -RZ ; /* 0x800000ff00117221 */
/* 0x004fca0000000100 */
/*0a30*/ STG.E [R4.64+0x4], R17 ; /* 0x0000041104007986 */
/* 0x0005e8000c101906 */
/*0a40*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ee4000c1e1900 */
/*0a50*/ FADD R13, R0, R13 ; /* 0x0000000d000d7221 */
/* 0x008fca0000000000 */
/*0a60*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101906 */
/*0a70*/ LDG.E R0, [R4.64+0x8] ; /* 0x0000080604007981 */
/* 0x000e68000c1e1900 */
/*0a80*/ LDG.E R9, [R4.64+0xc] ; /* 0x00000c0604097981 */
/* 0x001f22000c1e1900 */
/*0a90*/ FADD R15, -R0, -RZ ; /* 0x800000ff000f7221 */
/* 0x002fca0000000100 */
/*0aa0*/ STG.E [R4.64+0x8], R15 ; /* 0x0000080f04007986 */
/* 0x0007e8000c101906 */
/*0ab0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000f24000c1e1900 */
/*0ac0*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x010fca0000000000 */
/*0ad0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0007e8000c101906 */
/*0ae0*/ LDG.E R0, [R4.64+0xc] ; /* 0x00000c0604007981 */
/* 0x000ea2000c1e1900 */
/*0af0*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06270 */
/*0b10*/ FADD R17, -R0, -RZ ; /* 0x800000ff00117221 */
/* 0x004fca0000000100 */
/*0b20*/ STG.E [R4.64+0xc], R17 ; /* 0x00000c1104007986 */
/* 0x0007e2000c101906 */
/*0b30*/ IADD3 R0, P1, R4, 0x10, RZ ; /* 0x0000001004007810 */
/* 0x000fca0007f3e0ff */
/*0b40*/ IMAD.X R11, RZ, RZ, R5, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e0605 */
/*0b50*/ @!P0 BRA 0x930 ; /* 0xfffffdd000008947 */
/* 0x000fea000383ffff */
/*0b60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b70*/ BRA 0xb70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23ComputeLaplacianInPlacePfi
.globl _Z23ComputeLaplacianInPlacePfi
.p2align 8
.type _Z23ComputeLaplacianInPlacePfi,@function
_Z23ComputeLaplacianInPlacePfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_mul_lo_u32 v3, v1, s2
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v2, v4
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v4, vcc_lo, v2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, v3, v6, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_nc_u32_e32 v1, -1, v1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_cbranch_scc0 .LBB0_6
.LBB0_4:
s_mov_b32 s0, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_3
global_load_b32 v0, v[2:3], off
global_load_b32 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
global_store_b32 v[4:5], v0, off
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_xor_b32_e32 v0, 0x80000000, v0
global_store_b32 v[2:3], v0, off
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23ComputeLaplacianInPlacePfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23ComputeLaplacianInPlacePfi, .Lfunc_end0-_Z23ComputeLaplacianInPlacePfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23ComputeLaplacianInPlacePfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23ComputeLaplacianInPlacePfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e66fe_00000000-6_ComputeLaplacianInPlace.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z23ComputeLaplacianInPlacePfiPfi
.type _Z44__device_stub__Z23ComputeLaplacianInPlacePfiPfi, @function
_Z44__device_stub__Z23ComputeLaplacianInPlacePfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z23ComputeLaplacianInPlacePfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z23ComputeLaplacianInPlacePfiPfi, .-_Z44__device_stub__Z23ComputeLaplacianInPlacePfiPfi
.globl _Z23ComputeLaplacianInPlacePfi
.type _Z23ComputeLaplacianInPlacePfi, @function
_Z23ComputeLaplacianInPlacePfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z23ComputeLaplacianInPlacePfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23ComputeLaplacianInPlacePfi, .-_Z23ComputeLaplacianInPlacePfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23ComputeLaplacianInPlacePfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23ComputeLaplacianInPlacePfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ComputeLaplacianInPlace.hip"
.globl _Z38__device_stub__ComputeLaplacianInPlacePfi # -- Begin function _Z38__device_stub__ComputeLaplacianInPlacePfi
.p2align 4, 0x90
.type _Z38__device_stub__ComputeLaplacianInPlacePfi,@function
_Z38__device_stub__ComputeLaplacianInPlacePfi: # @_Z38__device_stub__ComputeLaplacianInPlacePfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z23ComputeLaplacianInPlacePfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z38__device_stub__ComputeLaplacianInPlacePfi, .Lfunc_end0-_Z38__device_stub__ComputeLaplacianInPlacePfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23ComputeLaplacianInPlacePfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23ComputeLaplacianInPlacePfi,@object # @_Z23ComputeLaplacianInPlacePfi
.section .rodata,"a",@progbits
.globl _Z23ComputeLaplacianInPlacePfi
.p2align 3, 0x0
_Z23ComputeLaplacianInPlacePfi:
.quad _Z38__device_stub__ComputeLaplacianInPlacePfi
.size _Z23ComputeLaplacianInPlacePfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23ComputeLaplacianInPlacePfi"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__ComputeLaplacianInPlacePfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23ComputeLaplacianInPlacePfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/scan.h>
#include <stdint.h>
#include <stdio.h>
void performExperiment(int size ) {
thrust::host_vector<float> values(size);
//can I fread directly into values ?
for (int i = 0; i < size; ++i) {
values[i] = 1.0;
}
thrust::device_vector<float> dvalues = values;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
thrust::inclusive_scan(dvalues.begin(),dvalues.end(),dvalues.begin());
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
// std::cout << std::endl;
printf("%f\n", elapsedTime);
//for (int i = 0; i < size; ++i) {
values[0] = dvalues[size-1];
//}
//for (int i = 0; i < 512; ++i) {
printf("%f ",values[0]);
//}
}
int main(int argc, char **argv){
performExperiment(4096*4096);
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/scan.h>
#include <stdint.h>
#include <stdio.h>
void performExperiment(int size ) {
thrust::host_vector<float> values(size);
//can I fread directly into values ?
for (int i = 0; i < size; ++i) {
values[i] = 1.0;
}
thrust::device_vector<float> dvalues = values;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
thrust::inclusive_scan(dvalues.begin(),dvalues.end(),dvalues.begin());
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
// std::cout << std::endl;
printf("%f\n", elapsedTime);
//for (int i = 0; i < size; ++i) {
values[0] = dvalues[size-1];
//}
//for (int i = 0; i < 512; ++i) {
printf("%f ",values[0]);
//}
}
int main(int argc, char **argv){
performExperiment(4096*4096);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <curand_kernel.h>
/**
* Some kernel functions for LDA
*
* @author Lin Chi-Min (v381654729@gmail.com)
*/
/**
* wpt[k][v] : words per topic
* wt[k] : total words per topic
* tpd[m][k] : topics per document
* td[m] : total topics per document
*
* wpt and phis : a K * V matrix
* tpd and thetas : a M * K matrix
*
* numElements = (num documents in one batch)
*
* p: K * numDocumentsInOneBatch
*/
extern "C"
__global__ void drawLatentVariables(
const int* __restrict__ docsWordCounts, const int* __restrict__ docsWordOffsets, const int* __restrict__ docsWordIndices,
int* wpt, int* wt, int* tpd, int* td, const float* __restrict__ phis, const float* __restrict__ thetas,
float* p,
int docOffset, int K, int M, int V, int numDocumentsInOneBatch) {
/**
* with size numDocumentsInOneBatch * K
*/
int m = blockDim.x * blockIdx.x + threadIdx.x;
if (m < numDocumentsInOneBatch) {
int Nm = docsWordCounts[m];
int docIndex = docOffset + m;
int docWordOffset = docsWordOffsets[m];
curandState s;
// reset a random number generator
curand_init(docIndex, 0, 0, &s);
int pOffset = m * K;
for (int i = 0; i < Nm; i++) {
float sum = 0;
int c_word = docsWordIndices[docWordOffset + i];
if (c_word < 0 || c_word >= V){
continue;
}
int j;
for (j = 0; j < K; j++) {
sum += phis[j + (c_word * K)] * thetas[docIndex + (j * M)];
p[j + pOffset] = sum;
}
float stop = curand_uniform(&s) * sum;
for (j = 0; j < K; j++) {
if (stop < p[j + pOffset]) {
break;
}
}
if (j == K){
j--;
}
atomicAdd(&wpt[j + (c_word * K)], 1);
atomicAdd(&wt[j], 1);
tpd[docIndex + (j * M)]++;
}
td[docIndex] += Nm;
}
}
extern "C"
__global__ void drawLatentVariablesForTestingQuick(
const int* __restrict__ docsWordCounts, const int* __restrict__ docsWordOffsets, const int* __restrict__ docsWordIndices,
int* tpd, int* td, const float* __restrict__ phis, const float* __restrict__ thetas,
int docOffset, int K, int M, int numDocumentsInOneBatch) {
extern __shared__ float p[];
/**
* with size numDocumentsInOneBatch * K
*/
int m = blockDim.x * blockIdx.x + threadIdx.x;
if (m < numDocumentsInOneBatch) {
int Nm = docsWordCounts[m];
int docIndex = docOffset + m;
int docWordOffset = docsWordOffsets[m];
curandState s;
// reset a random number generator
curand_init(docIndex, 0, 0, &s);
int pOffset = m * K;
for (int i = 0; i < Nm; i++) {
float sum = 0;
int c_word = docsWordIndices[docWordOffset + i];
if (c_word < 0){
continue;
}
int j;
for (j = 0; j < K; j++) {
sum += phis[j + (c_word * K)] * thetas[docIndex + (j * M)];
p[j + pOffset] = sum;
}
float stop = curand_uniform(&s) * sum;
for (j = 0; j < K; j++) {
if (stop < p[j + pOffset]) {
break;
}
}
if (j == K){
j--;
}
tpd[docIndex + (j * M)]++;
}
td[docIndex] += Nm;
}
}
/**
* Use this to infer topics for testing;
* phis are fixed and not updated
*
*/
extern "C"
__global__ void drawLatentVariablesForTesting(
const int* __restrict__ docsWordCounts, const int* __restrict__ docsWordOffsets, const int* __restrict__ docsWordIndices,
int* tpd, int* td, const float* __restrict__ phis, const float* __restrict__ thetas,
float* p,
int docOffset, int K, int M, int numDocumentsInOneBatch) {
/**
* with size numDocumentsInOneBatch * K
*/
int m = blockDim.x * blockIdx.x + threadIdx.x;
if (m < numDocumentsInOneBatch) {
int Nm = docsWordCounts[m];
int docIndex = docOffset + m;
int docWordOffset = docsWordOffsets[m];
curandState s;
// reset a random number generator
curand_init(docIndex, 0, 0, &s);
int pOffset = m * K;
for (int i = 0; i < Nm; i++) {
float sum = 0;
int c_word = docsWordIndices[docWordOffset + i];
if (c_word < 0){
continue;
}
int j;
for (j = 0; j < K; j++) {
sum += phis[j + (c_word * K)] * thetas[docIndex + (j * M)];
p[j + pOffset] = sum;
}
float stop = curand_uniform(&s) * sum;
for (j = 0; j < K; j++) {
if (stop < p[j + pOffset]) {
break;
}
}
if (j == K){
j--;
}
tpd[docIndex + (j * M)]++;
}
td[docIndex] += Nm;
}
}
/**
* K = 30
* V = 120000
*
* numElements = K * V
*
* wpt and phis : a K * V matrix
*
* wpt[k][v] : words per topic
* wt[k] : total words per topic
*
*/
extern "C"
__global__ void computePhis(const int* __restrict__ wpt, const int* __restrict__ wt, float* phis, float beta, float betaV, int K, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements) {
int k = i % K;
phis[i] = (wpt[i] + beta) / (wt[k] + betaV);
}
}
extern "C"
__global__ void computePhisExact(const int* __restrict__ wpt, const int* __restrict__ wt, float* phis, int K, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements) {
int k = i % K;
phis[i] = (wpt[i] + 0.0) / wt[k];
}
}
/**
* M = 90000
* K = 30
*
* numElements = M * K
*
* thetas : a M * K matrix
*
* tpd[m][k] : topics per document
* td[m] : total topics per document
*/
extern "C"
__global__ void computeThetas(const int* __restrict__ tpd, const int* __restrict__ td, float* thetas,
float alpha, float alphaK, int M, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements) {
int m = i % M;
thetas[i] = (tpd[i] + alpha) / (td[m] + alphaK);
}
} | .file "tmpxft_000d5749_00000000-6_CudaLDAFunctions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2243:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2243:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z70__device_stub__Z19drawLatentVariablesPKiS0_S0_PiS1_S1_S1_PKfS3_PfiiiiiPKiS0_S0_PiS1_S1_S1_PKfS3_Pfiiiii
.type _Z70__device_stub__Z19drawLatentVariablesPKiS0_S0_PiS1_S1_S1_PKfS3_PfiiiiiPKiS0_S0_PiS1_S1_S1_PKfS3_Pfiiiii, @function
_Z70__device_stub__Z19drawLatentVariablesPKiS0_S0_PiS1_S1_S1_PKfS3_PfiiiiiPKiS0_S0_PiS1_S1_S1_PKfS3_Pfiiiii:
.LFB2265:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 328(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
movq %rdi, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
movq %rdx, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
movq 312(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 216(%rsp)
movq 320(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
leaq 336(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
leaq 352(%rsp), %rax
movq %rax, 256(%rsp)
leaq 360(%rsp), %rax
movq %rax, 264(%rsp)
leaq 368(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 312
pushq 104(%rsp)
.cfi_def_cfa_offset 320
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq drawLatentVariables(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2265:
.size _Z70__device_stub__Z19drawLatentVariablesPKiS0_S0_PiS1_S1_S1_PKfS3_PfiiiiiPKiS0_S0_PiS1_S1_S1_PKfS3_Pfiiiii, .-_Z70__device_stub__Z19drawLatentVariablesPKiS0_S0_PiS1_S1_S1_PKfS3_PfiiiiiPKiS0_S0_PiS1_S1_S1_PKfS3_Pfiiiii
.globl drawLatentVariables
.type drawLatentVariables, @function
drawLatentVariables:
.LFB2266:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z70__device_stub__Z19drawLatentVariablesPKiS0_S0_PiS1_S1_S1_PKfS3_PfiiiiiPKiS0_S0_PiS1_S1_S1_PKfS3_Pfiiiii
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2266:
.size drawLatentVariables, .-drawLatentVariables
.globl _Z76__device_stub__Z34drawLatentVariablesForTestingQuickPKiS0_S0_PiS1_PKfS3_iiiiPKiS0_S0_PiS1_PKfS3_iiii
.type _Z76__device_stub__Z34drawLatentVariablesForTestingQuickPKiS0_S0_PiS1_PKfS3_iiiiPKiS0_S0_PiS1_PKfS3_iiii, @function
_Z76__device_stub__Z34drawLatentVariablesForTestingQuickPKiS0_S0_PiS1_PKfS3_iiiiPKiS0_S0_PiS1_PKfS3_iiii:
.LFB2267:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
movq %rdx, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movq %r9, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
movq 240(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq drawLatentVariablesForTestingQuick(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2267:
.size _Z76__device_stub__Z34drawLatentVariablesForTestingQuickPKiS0_S0_PiS1_PKfS3_iiiiPKiS0_S0_PiS1_PKfS3_iiii, .-_Z76__device_stub__Z34drawLatentVariablesForTestingQuickPKiS0_S0_PiS1_PKfS3_iiiiPKiS0_S0_PiS1_PKfS3_iiii
.globl drawLatentVariablesForTestingQuick
.type drawLatentVariablesForTestingQuick, @function
drawLatentVariablesForTestingQuick:
.LFB2268:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z76__device_stub__Z34drawLatentVariablesForTestingQuickPKiS0_S0_PiS1_PKfS3_iiiiPKiS0_S0_PiS1_PKfS3_iiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2268:
.size drawLatentVariablesForTestingQuick, .-drawLatentVariablesForTestingQuick
.globl _Z73__device_stub__Z29drawLatentVariablesForTestingPKiS0_S0_PiS1_PKfS3_PfiiiiPKiS0_S0_PiS1_PKfS3_Pfiiii
.type _Z73__device_stub__Z29drawLatentVariablesForTestingPKiS0_S0_PiS1_PKfS3_PfiiiiPKiS0_S0_PiS1_PKfS3_Pfiiii, @function
_Z73__device_stub__Z29drawLatentVariablesForTestingPKiS0_S0_PiS1_PKfS3_PfiiiiPKiS0_S0_PiS1_PKfS3_Pfiiii:
.LFB2269:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq 280(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movq %rdi, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsi, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
movq %rdx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
movq %r9, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
movq 272(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 296(%rsp), %rax
movq %rax, 216(%rsp)
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
leaq 312(%rsp), %rax
movq %rax, 232(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq drawLatentVariablesForTesting(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2269:
.size _Z73__device_stub__Z29drawLatentVariablesForTestingPKiS0_S0_PiS1_PKfS3_PfiiiiPKiS0_S0_PiS1_PKfS3_Pfiiii, .-_Z73__device_stub__Z29drawLatentVariablesForTestingPKiS0_S0_PiS1_PKfS3_PfiiiiPKiS0_S0_PiS1_PKfS3_Pfiiii
.globl drawLatentVariablesForTesting
.type drawLatentVariablesForTesting, @function
drawLatentVariablesForTesting:
.LFB2270:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z73__device_stub__Z29drawLatentVariablesForTestingPKiS0_S0_PiS1_PKfS3_PfiiiiPKiS0_S0_PiS1_PKfS3_Pfiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2270:
.size drawLatentVariablesForTesting, .-drawLatentVariablesForTesting
.globl _Z41__device_stub__Z11computePhisPKiS0_PfffiiPKiS0_Pfffii
.type _Z41__device_stub__Z11computePhisPKiS0_PfffiiPKiS0_Pfffii, @function
_Z41__device_stub__Z11computePhisPKiS0_PfffiiPKiS0_Pfffii:
.LFB2271:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq computePhis(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size _Z41__device_stub__Z11computePhisPKiS0_PfffiiPKiS0_Pfffii, .-_Z41__device_stub__Z11computePhisPKiS0_PfffiiPKiS0_Pfffii
.globl computePhis
.type computePhis, @function
computePhis:
.LFB2272:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z11computePhisPKiS0_PfffiiPKiS0_Pfffii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2272:
.size computePhis, .-computePhis
.globl _Z44__device_stub__Z16computePhisExactPKiS0_PfiiPKiS0_Pfii
.type _Z44__device_stub__Z16computePhisExactPKiS0_PfiiPKiS0_Pfii, @function
_Z44__device_stub__Z16computePhisExactPKiS0_PfiiPKiS0_Pfii:
.LFB2273:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq computePhisExact(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2273:
.size _Z44__device_stub__Z16computePhisExactPKiS0_PfiiPKiS0_Pfii, .-_Z44__device_stub__Z16computePhisExactPKiS0_PfiiPKiS0_Pfii
.globl computePhisExact
.type computePhisExact, @function
computePhisExact:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z16computePhisExactPKiS0_PfiiPKiS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size computePhisExact, .-computePhisExact
.globl _Z43__device_stub__Z13computeThetasPKiS0_PfffiiPKiS0_Pfffii
.type _Z43__device_stub__Z13computeThetasPKiS0_PfffiiPKiS0_Pfffii, @function
_Z43__device_stub__Z13computeThetasPKiS0_PfffiiPKiS0_Pfffii:
.LFB2275:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq computeThetas(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2275:
.size _Z43__device_stub__Z13computeThetasPKiS0_PfffiiPKiS0_Pfffii, .-_Z43__device_stub__Z13computeThetasPKiS0_PfffiiPKiS0_Pfffii
.globl computeThetas
.type computeThetas, @function
computeThetas:
.LFB2276:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z13computeThetasPKiS0_PfffiiPKiS0_Pfffii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2276:
.size computeThetas, .-computeThetas
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "computeThetas"
.LC1:
.string "computePhisExact"
.LC2:
.string "computePhis"
.LC3:
.string "drawLatentVariablesForTesting"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "drawLatentVariablesForTestingQuick"
.section .rodata.str1.1
.LC5:
.string "drawLatentVariables"
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2278:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq computeThetas(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq computePhisExact(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq computePhis(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq drawLatentVariablesForTesting(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq drawLatentVariablesForTestingQuick(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq drawLatentVariables(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2278:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.